lurwu.adoc

th.lurwu

Synopsis

Load unsigned indexed unsigned word.

Mnemonic

th.lurwu rd, rs1, rs2, imm2

Encoding

{reg:[
    { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
    { bits:  5, name: 'rd' },
    { bits:  3, name: 0x4, attr: ['Mem-Load'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 'rs2' },
    { bits:  2, name: 'imm2' },
    { bits:  5, name: 0x1a },
]}

Description

This instruction loads a zero extended 32-bit value into GP register rd from the address rs1 + (zero_extend(rs2) << imm2).

Note, that this instruction is equivalent to a zext.w rs2, rs2 followed by a th.lrwu with the same arguments.

Operation

addr := rs1 + (zero_extend(rs2) << imm2)
rd := zero_extend(mem[addr+3:addr])

Permission

This instruction can be executed in all privilege levels.

Exceptions

This instruction triggers the same exceptions that a corresponding LWU instruction would trigger.

Included in

Extension
XTheadMemIdx ([xtheadmemidx])