lbuia.adoc

th.lbuia

Synopsis

Load indexed unsigned byte, increment address after loading.

Mnemonic

th.lbuia rd, (rs1), imm5, imm2

Encoding

{reg:[
    { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
    { bits:  5, name: 'rd' },
    { bits:  3, name: 0x4, attr: ['Mem-Load'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 'imm5' },
    { bits:  2, name: 'imm2' },
    { bits:  5, name: 0x13 },
]}

Description

This instruction loads a zero extended 8-bit value into the GP register rd from the address rs1. After the load, this instruction increments the value in rs1 by (sign_extend(imm5) << imm2) and writes the result back to rs1.

The encoding of this instruction with equal rd and rs1 is reserved.

Operation

if (rs1 != rd) {
    rs := zero_extend(mem[rs1])
    rs1 := rs1 + (sign_extend(imm5) << imm2)
}

Permission

This instruction can be executed in all privilege levels.

Exceptions

This instruction triggers the same exceptions that a corresponding LBU instruction would trigger.

Included in

Extension
XTheadMemIdx ([xtheadmemidx])