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xtheadint.adoc

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Acceleration interruption instructions

Frozen
The XTheadInt extension is stable.

The XTheadInt ISA extension provides instructions to reduce the code size of ISRs and/or the interrupt latencies that are caused by ISR entry/exit code.

Extension version: 1.0.

The table below gives an overview of the instructions:

RV32 RV64 Mnemonic Instruction

Y

Y

th.ipush

[xtheadint-insns-ipush]

Y

Y

th.ipop

[xtheadint-insns-ipop]

Availability

The XTheadInt extension’s availability can be probed via the th.sxstatus.THEADISAEE bit (bit 22). The XTheadInt extension is available if and only if this bit is 1. Refer to [xtheadsxstatus] for more information about the th.sxstatus CSR.