dcache_ipa.adoc

th.dcache.ipa

Synopsis

Invalidate D-cache at PA

Mnemonic

th.dcache.ipa rs1

Encoding

{reg:[
    { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
    { bits:  5, name: 0x0 },
    { bits:  3, name: 0x0, attr: ['CMO'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 0xA, attr: ['dcache.ipa'] },
    { bits:  7, name: 0x01 },
]}

Description

This instruction invalidates the cache lines that match the specified physical address in the D-cache. Dirty cache lines will not be written back to the next-level storage.

Operation

if (priv_level == U)
  <raise illegal instruction exception>
}

<invalidate all data cache lines matching the PA>

Permission

This instruction can be executed in all privilege levels higher than U mode. Attempts to execute this instruction in U mode raise an illegal instruction exception.

Exceptions

This instruction does not trigger any exceptions.

Included in

Extension	HW requirements
XTheadCmo ([xtheadcmo])	D-cache