- Synopsis
-
Add a shifted operand to a second operand.
- Mnemonic
-
th.addsl rd, rs1, rs2, imm2
- Encoding
{reg:[
{ bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] },
{ bits: 5, name: 'rd' },
{ bits: 3, name: 0x1, attr: ['Arithmetic'] },
{ bits: 5, name: 'rs1' },
{ bits: 5, name: 'rs2' },
{ bits: 2, name: 'imm2' },
{ bits: 5, name: 0x00 },
]}
- Description
-
This operation adds the shifted operand (rs2 << imm2) with rs1.
- Operation
reg[rd] := reg[rs1] + (reg[rs2] << imm2)- Permission
-
This instruction can be executed in all privilege levels.
- Exceptions
-
This instruction does not trigger any exceptions.
- Included in
| Extension |
|---|
XTheadBa ([xtheadba]) |