diff --git a/docs/cli.rst b/docs/cli.rst index 97530598b..81799dda8 100644 --- a/docs/cli.rst +++ b/docs/cli.rst @@ -2,13 +2,13 @@ Command Line Interface ====================== -A :class:`VUnit ` object can be created from command +A :class:`VUnit ` object can be created from command line arguments by using the :meth:`from_argv -` method effectively creating a custom +` method effectively creating a custom command line tool for running tests in the user project. Source files and libraries are added to the project by using methods on the VUnit object. The configuration is followed by a call to the :meth:`main -` method which will execute the function +` method which will execute the function specified by the command line arguments and exit the script. The added source files are automatically scanned for test cases. diff --git a/docs/installing.rst b/docs/installing.rst index 619fe81fe..6c4750922 100644 --- a/docs/installing.rst +++ b/docs/installing.rst @@ -27,7 +27,7 @@ Start by cloning our `GIT repository on GitHub The ``--recursive`` option initializes `OSVVM `__ which is included as a submodule in the VUnit repository. -To be able to import :class:`VUnit ` in your ``run.py`` script +To be able to import :class:`VUnit ` in your ``run.py`` script you need to make it visible to Python or else the following error occurs. diff --git a/docs/py/ui.rst b/docs/py/ui.rst index 601c946e0..c08cb47f2 100644 --- a/docs/py/ui.rst +++ b/docs/py/ui.rst @@ -3,7 +3,7 @@ Python Interface ================ The Python interface of VUnit is exposed through the :class:`VUnit -class ` that can be imported directly. See the +class ` that can be imported directly. See the :ref:`User Guide ` for a quick introduction. The following list provides detailed references of the Python API and about how to set compilation and simulation options. diff --git a/docs/py/vunit.rst b/docs/py/vunit.rst index 668f6caaa..705baf0d7 100644 --- a/docs/py/vunit.rst +++ b/docs/py/vunit.rst @@ -1,7 +1,7 @@ -vunit.ui.vunit +vunit.ui ============== -.. autoclass:: vunit.ui.vunit.VUnit() +.. autoclass:: vunit.ui.VUnit() :exclude-members: add_preprocessor, add_builtins diff --git a/setup.py b/setup.py index 4fc232ebd..5dc246e1e 100644 --- a/setup.py +++ b/setup.py @@ -40,14 +40,16 @@ def find_all_files(directory, endings=None): name="vunit_hdl", version=version(), packages=[ + "tests", + "tests.lint", + "tests.unit", + "tests.acceptance", "vunit", "vunit.com", "vunit.parsing", "vunit.parsing.verilog", + "vunit.sim_if", "vunit.test", - "vunit.test.lint", - "vunit.test.unit", - "vunit.test.acceptance", "vunit.ui", "vunit.vivado", ], diff --git a/vunit/test/acceptance/__init__.py b/tests/__init__.py similarity index 100% rename from vunit/test/acceptance/__init__.py rename to tests/__init__.py diff --git a/vunit/test/lint/__init__.py b/tests/acceptance/__init__.py similarity index 100% rename from vunit/test/lint/__init__.py rename to tests/acceptance/__init__.py diff --git a/vunit/test/acceptance/artificial/verilog/other_file_tests.sv b/tests/acceptance/artificial/verilog/other_file_tests.sv similarity index 100% rename from vunit/test/acceptance/artificial/verilog/other_file_tests.sv rename to tests/acceptance/artificial/verilog/other_file_tests.sv diff --git a/vunit/test/acceptance/artificial/verilog/run.py b/tests/acceptance/artificial/verilog/run.py similarity index 100% rename from vunit/test/acceptance/artificial/verilog/run.py rename to tests/acceptance/artificial/verilog/run.py diff --git a/vunit/test/acceptance/artificial/verilog/tb_fail_on_fatal_and_early_finish.sv b/tests/acceptance/artificial/verilog/tb_fail_on_fatal_and_early_finish.sv similarity index 100% rename from vunit/test/acceptance/artificial/verilog/tb_fail_on_fatal_and_early_finish.sv rename to tests/acceptance/artificial/verilog/tb_fail_on_fatal_and_early_finish.sv diff --git a/vunit/test/acceptance/artificial/verilog/tb_fail_on_warning.sv b/tests/acceptance/artificial/verilog/tb_fail_on_warning.sv similarity index 100% rename from vunit/test/acceptance/artificial/verilog/tb_fail_on_warning.sv rename to tests/acceptance/artificial/verilog/tb_fail_on_warning.sv diff --git a/vunit/test/acceptance/artificial/verilog/tb_magic_paths.sv b/tests/acceptance/artificial/verilog/tb_magic_paths.sv similarity index 100% rename from vunit/test/acceptance/artificial/verilog/tb_magic_paths.sv rename to tests/acceptance/artificial/verilog/tb_magic_paths.sv diff --git a/vunit/test/acceptance/artificial/verilog/tb_other_file_tests.sv b/tests/acceptance/artificial/verilog/tb_other_file_tests.sv similarity index 100% rename from vunit/test/acceptance/artificial/verilog/tb_other_file_tests.sv rename to tests/acceptance/artificial/verilog/tb_other_file_tests.sv diff --git a/vunit/test/acceptance/artificial/verilog/tb_same_sim_all_pass.sv b/tests/acceptance/artificial/verilog/tb_same_sim_all_pass.sv similarity index 100% rename from vunit/test/acceptance/artificial/verilog/tb_same_sim_all_pass.sv rename to tests/acceptance/artificial/verilog/tb_same_sim_all_pass.sv diff --git a/vunit/test/acceptance/artificial/verilog/tb_same_sim_some_fail.sv b/tests/acceptance/artificial/verilog/tb_same_sim_some_fail.sv similarity index 100% rename from vunit/test/acceptance/artificial/verilog/tb_same_sim_some_fail.sv rename to tests/acceptance/artificial/verilog/tb_same_sim_some_fail.sv diff --git a/vunit/test/acceptance/artificial/verilog/tb_with_define.sv b/tests/acceptance/artificial/verilog/tb_with_define.sv similarity index 100% rename from vunit/test/acceptance/artificial/verilog/tb_with_define.sv rename to tests/acceptance/artificial/verilog/tb_with_define.sv diff --git a/vunit/test/acceptance/artificial/verilog/tb_with_parameter_config.sv b/tests/acceptance/artificial/verilog/tb_with_parameter_config.sv similarity index 100% rename from vunit/test/acceptance/artificial/verilog/tb_with_parameter_config.sv rename to tests/acceptance/artificial/verilog/tb_with_parameter_config.sv diff --git a/vunit/test/acceptance/artificial/verilog/tb_with_runner.sv b/tests/acceptance/artificial/verilog/tb_with_runner.sv similarity index 100% rename from vunit/test/acceptance/artificial/verilog/tb_with_runner.sv rename to tests/acceptance/artificial/verilog/tb_with_runner.sv diff --git a/vunit/test/acceptance/artificial/vhdl/bool_driver.vhd b/tests/acceptance/artificial/vhdl/bool_driver.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/bool_driver.vhd rename to tests/acceptance/artificial/vhdl/bool_driver.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/other_file_tests.vhd b/tests/acceptance/artificial/vhdl/other_file_tests.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/other_file_tests.vhd rename to tests/acceptance/artificial/vhdl/other_file_tests.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/run.py b/tests/acceptance/artificial/vhdl/run.py similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/run.py rename to tests/acceptance/artificial/vhdl/run.py diff --git a/vunit/test/acceptance/artificial/vhdl/tb_assert_stop_level.vhd b/tests/acceptance/artificial/vhdl/tb_assert_stop_level.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_assert_stop_level.vhd rename to tests/acceptance/artificial/vhdl/tb_assert_stop_level.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_elab_fail.vhd b/tests/acceptance/artificial/vhdl/tb_elab_fail.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_elab_fail.vhd rename to tests/acceptance/artificial/vhdl/tb_elab_fail.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_fail.vhd b/tests/acceptance/artificial/vhdl/tb_fail.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_fail.vhd rename to tests/acceptance/artificial/vhdl/tb_fail.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_fail_on_warning.vhd b/tests/acceptance/artificial/vhdl/tb_fail_on_warning.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_fail_on_warning.vhd rename to tests/acceptance/artificial/vhdl/tb_fail_on_warning.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_ieee_warning.vhd b/tests/acceptance/artificial/vhdl/tb_ieee_warning.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_ieee_warning.vhd rename to tests/acceptance/artificial/vhdl/tb_ieee_warning.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_infinite_events.vhd b/tests/acceptance/artificial/vhdl/tb_infinite_events.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_infinite_events.vhd rename to tests/acceptance/artificial/vhdl/tb_infinite_events.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_magic_paths.vhd b/tests/acceptance/artificial/vhdl/tb_magic_paths.vhd similarity index 82% rename from vunit/test/acceptance/artificial/vhdl/tb_magic_paths.vhd rename to tests/acceptance/artificial/vhdl/tb_magic_paths.vhd index 91812b71f..01b3fd5dc 100644 --- a/vunit/test/acceptance/artificial/vhdl/tb_magic_paths.vhd +++ b/tests/acceptance/artificial/vhdl/tb_magic_paths.vhd @@ -23,8 +23,8 @@ begin end procedure; begin test_runner_setup(runner, runner_cfg); - check_has_suffix(tb_path, "/vunit/test/acceptance/artificial/vhdl/"); - check_has_suffix(vunit_lib.run_pkg.tb_path(runner_cfg), "/vunit/test/acceptance/artificial/vhdl/"); + check_has_suffix(tb_path, "/tests/acceptance/artificial/vhdl/"); + check_has_suffix(vunit_lib.run_pkg.tb_path(runner_cfg), "/tests/acceptance/artificial/vhdl/"); test_runner_cleanup(runner); wait; end process; diff --git a/vunit/test/acceptance/artificial/vhdl/tb_no_fail_after_cleanup.vhd b/tests/acceptance/artificial/vhdl/tb_no_fail_after_cleanup.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_no_fail_after_cleanup.vhd rename to tests/acceptance/artificial/vhdl/tb_no_fail_after_cleanup.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_no_fail_on_warning.vhd b/tests/acceptance/artificial/vhdl/tb_no_fail_on_warning.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_no_fail_on_warning.vhd rename to tests/acceptance/artificial/vhdl/tb_no_fail_on_warning.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_no_generic_override.vhd b/tests/acceptance/artificial/vhdl/tb_no_generic_override.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_no_generic_override.vhd rename to tests/acceptance/artificial/vhdl/tb_no_generic_override.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_other_file_tests.vhd b/tests/acceptance/artificial/vhdl/tb_other_file_tests.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_other_file_tests.vhd rename to tests/acceptance/artificial/vhdl/tb_other_file_tests.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_pass.vhd b/tests/acceptance/artificial/vhdl/tb_pass.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_pass.vhd rename to tests/acceptance/artificial/vhdl/tb_pass.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_same_sim_all_pass.vhd b/tests/acceptance/artificial/vhdl/tb_same_sim_all_pass.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_same_sim_all_pass.vhd rename to tests/acceptance/artificial/vhdl/tb_same_sim_all_pass.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_same_sim_some_fail.vhd b/tests/acceptance/artificial/vhdl/tb_same_sim_some_fail.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_same_sim_some_fail.vhd rename to tests/acceptance/artificial/vhdl/tb_same_sim_some_fail.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_set_generic.vhd b/tests/acceptance/artificial/vhdl/tb_set_generic.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_set_generic.vhd rename to tests/acceptance/artificial/vhdl/tb_set_generic.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_with_checks.vhd b/tests/acceptance/artificial/vhdl/tb_with_checks.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_with_checks.vhd rename to tests/acceptance/artificial/vhdl/tb_with_checks.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_with_generic_config.vhd b/tests/acceptance/artificial/vhdl/tb_with_generic_config.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_with_generic_config.vhd rename to tests/acceptance/artificial/vhdl/tb_with_generic_config.vhd diff --git a/vunit/test/acceptance/artificial/vhdl/tb_with_vhdl_runner.vhd b/tests/acceptance/artificial/vhdl/tb_with_vhdl_runner.vhd similarity index 100% rename from vunit/test/acceptance/artificial/vhdl/tb_with_vhdl_runner.vhd rename to tests/acceptance/artificial/vhdl/tb_with_vhdl_runner.vhd diff --git a/vunit/test/acceptance/dependencies/pkg.vhd b/tests/acceptance/dependencies/pkg.vhd similarity index 100% rename from vunit/test/acceptance/dependencies/pkg.vhd rename to tests/acceptance/dependencies/pkg.vhd diff --git a/vunit/test/acceptance/dependencies/pkg_body1.vhd b/tests/acceptance/dependencies/pkg_body1.vhd similarity index 100% rename from vunit/test/acceptance/dependencies/pkg_body1.vhd rename to tests/acceptance/dependencies/pkg_body1.vhd diff --git a/vunit/test/acceptance/dependencies/pkg_body2.vhd b/tests/acceptance/dependencies/pkg_body2.vhd similarity index 100% rename from vunit/test/acceptance/dependencies/pkg_body2.vhd rename to tests/acceptance/dependencies/pkg_body2.vhd diff --git a/vunit/test/acceptance/dependencies/tb_pkg.vhd b/tests/acceptance/dependencies/tb_pkg.vhd similarity index 100% rename from vunit/test/acceptance/dependencies/tb_pkg.vhd rename to tests/acceptance/dependencies/tb_pkg.vhd diff --git a/vunit/test/acceptance/test_artificial.py b/tests/acceptance/test_artificial.py similarity index 98% rename from vunit/test/acceptance/test_artificial.py rename to tests/acceptance/test_artificial.py index c8a3525ba..052975042 100644 --- a/vunit/test/acceptance/test_artificial.py +++ b/tests/acceptance/test_artificial.py @@ -8,13 +8,13 @@ Acceptance test of VUnit end to end functionality """ - import unittest from os.path import join, dirname from os import environ from subprocess import call import sys -from vunit.test.common import has_simulator, check_report, simulator_is +from tests.common import check_report +from vunit.sim_if.common import has_simulator, simulator_is @unittest.skipUnless(has_simulator(), "Requires simulator") diff --git a/vunit/test/acceptance/test_dependencies.py b/tests/acceptance/test_dependencies.py similarity index 100% rename from vunit/test/acceptance/test_dependencies.py rename to tests/acceptance/test_dependencies.py diff --git a/vunit/test/acceptance/test_external_run_scripts.py b/tests/acceptance/test_external_run_scripts.py similarity index 99% rename from vunit/test/acceptance/test_external_run_scripts.py rename to tests/acceptance/test_external_run_scripts.py index 98533f18b..a17c5c9fe 100644 --- a/vunit/test/acceptance/test_external_run_scripts.py +++ b/tests/acceptance/test_external_run_scripts.py @@ -8,15 +8,15 @@ Verify that all external run scripts work correctly """ - import unittest from os import environ from os.path import join, dirname from subprocess import call import sys +from tests.common import check_report from vunit import ROOT from vunit.builtins import VHDL_PATH -from vunit.test.common import has_simulator, check_report, simulator_is, simulator_check +from vunit.sim_if.common import has_simulator, simulator_is, simulator_check def simulator_supports_verilog(): diff --git a/vunit/test/common.py b/tests/common.py similarity index 89% rename from vunit/test/common.py rename to tests/common.py index 6a957ad50..0ef09f0fe 100644 --- a/vunit/test/common.py +++ b/tests/common.py @@ -8,38 +8,12 @@ Common functions re-used between test cases """ - from xml.etree import ElementTree import contextlib import functools import os import shutil import random -from vunit.simulator_factory import SIMULATOR_FACTORY - - -def has_simulator(): - return SIMULATOR_FACTORY.has_simulator - - -def simulator_is(*names): - """ - Check that current simulator is any of names - """ - supported_names = [sim.name for sim in SIMULATOR_FACTORY.supported_simulators()] - for name in names: - assert name in supported_names - return SIMULATOR_FACTORY.select_simulator().name in names - - -def simulator_check(func): - """ - Check some method of the selected simulator - """ - simif = SIMULATOR_FACTORY.select_simulator() - if simif is None: - return False - return func(simif) def check_report(report_file, tests=None): diff --git a/vunit/test/unit/__init__.py b/tests/lint/__init__.py similarity index 100% rename from vunit/test/unit/__init__.py rename to tests/lint/__init__.py diff --git a/vunit/test/lint/pylintrc b/tests/lint/pylintrc similarity index 100% rename from vunit/test/lint/pylintrc rename to tests/lint/pylintrc diff --git a/vunit/test/lint/test_license.py b/tests/lint/test_license.py similarity index 100% rename from vunit/test/lint/test_license.py rename to tests/lint/test_license.py diff --git a/vunit/test/lint/test_pycodestyle.py b/tests/lint/test_pycodestyle.py similarity index 100% rename from vunit/test/lint/test_pycodestyle.py rename to tests/lint/test_pycodestyle.py diff --git a/vunit/test/lint/test_pylint.py b/tests/lint/test_pylint.py similarity index 92% rename from vunit/test/lint/test_pylint.py rename to tests/lint/test_pylint.py index e0afb4199..c1975aad1 100644 --- a/vunit/test/lint/test_pylint.py +++ b/tests/lint/test_pylint.py @@ -13,7 +13,7 @@ from subprocess import check_call from os.path import join, dirname import sys -from vunit.test.lint.test_pycodestyle import get_files_and_folders +from tests.lint.test_pycodestyle import get_files_and_folders class TestPylint(unittest.TestCase): diff --git a/vunit/test/lint/test_readme.py b/tests/lint/test_readme.py similarity index 100% rename from vunit/test/lint/test_readme.py rename to tests/lint/test_readme.py diff --git a/vunit/test/mock_2or3.py b/tests/mock_2or3.py similarity index 100% rename from vunit/test/mock_2or3.py rename to tests/mock_2or3.py diff --git a/tests/unit/__init__.py b/tests/unit/__init__.py new file mode 100644 index 000000000..17b27373b --- /dev/null +++ b/tests/unit/__init__.py @@ -0,0 +1,5 @@ +# This Source Code Form is subject to the terms of the Mozilla Public +# License, v. 2.0. If a copy of the MPL was not distributed with this file, +# You can obtain one at http://mozilla.org/MPL/2.0/. +# +# Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com diff --git a/vunit/test/unit/non_utf8_printer.py b/tests/unit/non_utf8_printer.py similarity index 100% rename from vunit/test/unit/non_utf8_printer.py rename to tests/unit/non_utf8_printer.py diff --git a/vunit/test/unit/test_activehdl_interface.py b/tests/unit/test_activehdl_interface.py similarity index 87% rename from vunit/test/unit/test_activehdl_interface.py rename to tests/unit/test_activehdl_interface.py index 47e64e8fa..94c504292 100644 --- a/vunit/test/unit/test_activehdl_interface.py +++ b/tests/unit/test_activehdl_interface.py @@ -13,8 +13,8 @@ from os.path import join, dirname, exists import os from shutil import rmtree -from vunit.activehdl_interface import ActiveHDLInterface -from vunit.test.mock_2or3 import mock +from tests.mock_2or3 import mock +from vunit.sim_if.activehdl import ActiveHDLInterface from vunit.project import Project from vunit.ostools import renew_path, write_file from vunit.vhdl_standard import VHDL @@ -25,10 +25,8 @@ class TestActiveHDLInterface(unittest.TestCase): Test the ActiveHDL interface """ - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.activehdl_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_vhdl_2008(self, process, check_output): simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) project = Project() @@ -62,10 +60,8 @@ def test_compile_project_vhdl_2008(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.activehdl_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_vhdl_2002(self, process, check_output): simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) project = Project() @@ -99,10 +95,8 @@ def test_compile_project_vhdl_2002(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.activehdl_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_vhdl_93(self, process, check_output): simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) project = Project() @@ -136,10 +130,8 @@ def test_compile_project_vhdl_93(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.activehdl_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_vhdl_extra_flags(self, process, check_output): simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) project = Project() @@ -174,10 +166,8 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.activehdl_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_verilog(self, process, check_output): library_cfg = join(self.output_path, "library.cfg") simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) @@ -211,10 +201,8 @@ def test_compile_project_verilog(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.activehdl_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_system_verilog(self, process, check_output): library_cfg = join(self.output_path, "library.cfg") simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) @@ -248,10 +236,8 @@ def test_compile_project_system_verilog(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.activehdl_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_verilog_extra_flags(self, process, check_output): library_cfg = join(self.output_path, "library.cfg") simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) @@ -288,10 +274,8 @@ def test_compile_project_verilog_extra_flags(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.activehdl_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_verilog_include(self, process, check_output): library_cfg = join(self.output_path, "library.cfg") simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) @@ -328,10 +312,8 @@ def test_compile_project_verilog_include(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.activehdl_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_verilog_define(self, process, check_output): library_cfg = join(self.output_path, "library.cfg") simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) diff --git a/vunit/test/unit/test_builtins.py b/tests/unit/test_builtins.py similarity index 98% rename from vunit/test/unit/test_builtins.py rename to tests/unit/test_builtins.py index e1302e818..21e7136b6 100644 --- a/vunit/test/unit/test_builtins.py +++ b/tests/unit/test_builtins.py @@ -9,7 +9,7 @@ """ import unittest -from vunit.test.mock_2or3 import mock +from tests.mock_2or3 import mock from vunit.builtins import BuiltinsAdder diff --git a/vunit/test/unit/test_cds_file.py b/tests/unit/test_cds_file.py similarity index 92% rename from vunit/test/unit/test_cds_file.py rename to tests/unit/test_cds_file.py index a12ceaeed..a51b1ec7a 100644 --- a/vunit/test/unit/test_cds_file.py +++ b/tests/unit/test_cds_file.py @@ -9,8 +9,8 @@ """ import unittest -from vunit.test.mock_2or3 import mock -from vunit.cds_file import CDSFile +from tests.mock_2or3 import mock +from vunit.sim_if.cds_file import CDSFile class TestCDSFile(unittest.TestCase): @@ -90,7 +90,7 @@ def _create_cds_file(contents): """ Create a CDSFile object with 'contents' """ - with mock.patch("vunit.cds_file.read_file", autospec=True) as read_file: + with mock.patch("vunit.sim_if.cds_file.read_file", autospec=True) as read_file: read_file.return_value = contents return CDSFile.parse("file_name") @@ -98,7 +98,9 @@ def _check_written_as(self, cds, contents): """ Check that the CDSFile object writes the 'contents to the file """ - with mock.patch("vunit.cds_file.write_file", autospec=True) as write_file: + with mock.patch( + "vunit.sim_if.cds_file.write_file", autospec=True + ) as write_file: cds.write("filename") self.assertEqual(len(write_file.mock_calls), 1) args = write_file.mock_calls[0][1] diff --git a/vunit/test/unit/test_check_preprocessor.py b/tests/unit/test_check_preprocessor.py similarity index 100% rename from vunit/test/unit/test_check_preprocessor.py rename to tests/unit/test_check_preprocessor.py diff --git a/vunit/test/unit/test_configuration.py b/tests/unit/test_configuration.py similarity index 98% rename from vunit/test/unit/test_configuration.py rename to tests/unit/test_configuration.py index b3c96d6e3..0227733cc 100644 --- a/vunit/test/unit/test_configuration.py +++ b/tests/unit/test_configuration.py @@ -14,10 +14,10 @@ import unittest import contextlib from os.path import join +from tests.mock_2or3 import mock +from tests.common import with_tempdir, create_tempdir +from tests.unit.test_test_bench import Entity from vunit.configuration import Configuration, AttributeException -from vunit.test.mock_2or3 import mock -from vunit.test.common import with_tempdir, create_tempdir -from vunit.test.unit.test_test_bench import Entity class TestConfiguration(unittest.TestCase): diff --git a/vunit/test/unit/test_csv_logs.py b/tests/unit/test_csv_logs.py similarity index 100% rename from vunit/test/unit/test_csv_logs.py rename to tests/unit/test_csv_logs.py diff --git a/vunit/test/unit/test_database.py b/tests/unit/test_database.py similarity index 98% rename from vunit/test/unit/test_database.py rename to tests/unit/test_database.py index 5fc1d3f4d..f8e81f9a0 100644 --- a/vunit/test/unit/test_database.py +++ b/tests/unit/test_database.py @@ -10,8 +10,8 @@ import unittest from os.path import join +from tests.common import with_tempdir from vunit.database import DataBase, PickledDataBase -from vunit.test.common import with_tempdir class TestDataBase(unittest.TestCase): diff --git a/vunit/test/unit/test_dependency_graph.py b/tests/unit/test_dependency_graph.py similarity index 100% rename from vunit/test/unit/test_dependency_graph.py rename to tests/unit/test_dependency_graph.py diff --git a/vunit/test/unit/test_ghdl_interface.py b/tests/unit/test_ghdl_interface.py similarity index 94% rename from vunit/test/unit/test_ghdl_interface.py rename to tests/unit/test_ghdl_interface.py index 89003e381..2416340e7 100644 --- a/vunit/test/unit/test_ghdl_interface.py +++ b/tests/unit/test_ghdl_interface.py @@ -12,12 +12,12 @@ from os.path import join, dirname, exists import os from shutil import rmtree -from vunit.ghdl_interface import GHDLInterface -from vunit.test.mock_2or3 import mock +from tests.mock_2or3 import mock +from tests.unit.test_test_bench import Entity +from vunit.sim_if.ghdl import GHDLInterface from vunit.project import Project from vunit.ostools import renew_path, write_file from vunit.exceptions import CompileError -from vunit.test.unit.test_test_bench import Entity from vunit.configuration import Configuration from vunit.vhdl_standard import VHDL @@ -27,7 +27,7 @@ class TestGHDLInterface(unittest.TestCase): Test the GHDL interface """ - @mock.patch("vunit.ghdl_interface.GHDLInterface.find_executable") + @mock.patch("vunit.sim_if.ghdl.GHDLInterface.find_executable") def test_runtime_error_on_missing_gtkwave(self, find_executable): executables = {} @@ -106,7 +106,7 @@ def test_assertion_on_unknown_backend(self, check_output): self.assertRaises(AssertionError, GHDLInterface.determine_backend, "prefix") @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" + "vunit.sim_if.check_output", autospec=True, return_value="" ) # pylint: disable=no-self-use def test_compile_project_2008(self, check_output): simif = GHDLInterface(prefix="prefix", output_path="") @@ -132,7 +132,7 @@ def test_compile_project_2008(self, check_output): ) @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" + "vunit.sim_if.check_output", autospec=True, return_value="" ) # pylint: disable=no-self-use def test_compile_project_2002(self, check_output): simif = GHDLInterface(prefix="prefix", output_path="") @@ -158,7 +158,7 @@ def test_compile_project_2002(self, check_output): ) @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" + "vunit.sim_if.check_output", autospec=True, return_value="" ) # pylint: disable=no-self-use def test_compile_project_93(self, check_output): simif = GHDLInterface(prefix="prefix", output_path="") @@ -184,7 +184,7 @@ def test_compile_project_93(self, check_output): ) @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" + "vunit.sim_if.check_output", autospec=True, return_value="" ) # pylint: disable=no-self-use def test_compile_project_extra_flags(self, check_output): simif = GHDLInterface(prefix="prefix", output_path="") diff --git a/vunit/test/unit/test_incisive_interface.py b/tests/unit/test_incisive_interface.py similarity index 86% rename from vunit/test/unit/test_incisive_interface.py rename to tests/unit/test_incisive_interface.py index 362a98522..ec69ac73a 100644 --- a/vunit/test/unit/test_incisive_interface.py +++ b/tests/unit/test_incisive_interface.py @@ -15,11 +15,11 @@ from os.path import join, dirname, exists, basename import os from shutil import rmtree -from vunit.incisive_interface import IncisiveInterface -from vunit.test.mock_2or3 import mock +from tests.mock_2or3 import mock +from vunit.sim_if.incisive import IncisiveInterface from vunit.project import Project from vunit.ostools import renew_path, write_file, read_file -from vunit.test_bench import Configuration +from vunit.test.bench import Configuration from vunit.vhdl_standard import VHDL @@ -28,11 +28,9 @@ class TestIncisiveInterface(unittest.TestCase): Test the Incisive interface """ - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_vhdl_2008( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -84,11 +82,9 @@ def test_compile_project_vhdl_2008( % self.output_path, ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_vhdl_2002( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -126,11 +122,9 @@ def test_compile_project_vhdl_2002( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_vhdl_93( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -168,11 +162,9 @@ def test_compile_project_vhdl_93( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_vhdl_extra_flags( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -211,11 +203,9 @@ def test_compile_project_vhdl_extra_flags( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_vhdl_hdlvar( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -254,11 +244,9 @@ def test_compile_project_vhdl_hdlvar( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_verilog( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -296,11 +284,9 @@ def test_compile_project_verilog( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_system_verilog( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -352,11 +338,9 @@ def test_compile_project_system_verilog( % self.output_path, ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_verilog_extra_flags( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -399,11 +383,9 @@ def test_compile_project_verilog_extra_flags( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_verilog_include( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -444,11 +426,9 @@ def test_compile_project_verilog_include( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_verilog_define( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -489,11 +469,9 @@ def test_compile_project_verilog_define( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") def test_compile_project_verilog_hdlvar( self, check_output, find_cds_root_irun, find_cds_root_virtuoso ): @@ -537,8 +515,8 @@ def test_compile_project_verilog_hdlvar( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") def test_create_cds_lib(self, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None @@ -556,8 +534,8 @@ def test_create_cds_lib(self, find_cds_root_irun, find_cds_root_virtuoso): % self.output_path, ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") def test_create_cds_lib_virtuoso(self, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = "cds_root_virtuoso" @@ -574,11 +552,9 @@ def test_create_cds_lib_virtuoso(self, find_cds_root_irun, find_cds_root_virtuos % self.output_path, ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.incisive_interface.run_command", autospec=True, return_value=True - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.run_command", autospec=True, return_value=True) def test_simulate_vhdl( self, run_command, find_cds_root_irun, find_cds_root_virtuoso ): @@ -592,7 +568,7 @@ def test_simulate_vhdl( project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" + "vunit.sim_if.check_output", autospec=True, return_value="" ) as dummy: simif.compile_project(project) @@ -668,11 +644,9 @@ def test_simulate_vhdl( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.incisive_interface.run_command", autospec=True, return_value=True - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.run_command", autospec=True, return_value=True) def test_simulate_verilog( self, run_command, find_cds_root_irun, find_cds_root_virtuoso ): @@ -686,7 +660,7 @@ def test_simulate_verilog( project.add_source_file("file.vhd", "lib", file_type="vhdl") with mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" + "vunit.sim_if.check_output", autospec=True, return_value="" ) as dummy: simif.compile_project(project) @@ -762,11 +736,9 @@ def test_simulate_verilog( ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.incisive_interface.run_command", autospec=True, return_value=True - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.run_command", autospec=True, return_value=True) def test_simulate_extra_flags( self, run_command, find_cds_root_irun, find_cds_root_virtuoso ): @@ -804,11 +776,9 @@ def test_simulate_extra_flags( self.assertIn("custom", args) self.assertIn("flags", args) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.incisive_interface.run_command", autospec=True, return_value=True - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.run_command", autospec=True, return_value=True) def test_simulate_generics_and_parameters( self, run_command, find_cds_root_irun, find_cds_root_virtuoso ): @@ -844,11 +814,9 @@ def test_simulate_generics_and_parameters( self.assertIn('-gpg "modulename.genint => 1"', args) self.assertIn('-gpg "modulename.genbool => \\"True\\""', args) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.incisive_interface.run_command", autospec=True, return_value=True - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.run_command", autospec=True, return_value=True) def test_simulate_hdlvar( self, run_command, find_cds_root_irun, find_cds_root_virtuoso ): @@ -882,11 +850,9 @@ def test_simulate_hdlvar( args = read_file(args_file).splitlines() self.assertIn('-hdlvar "custom_hdlvar"', args) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.incisive_interface.run_command", autospec=True, return_value=True - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.run_command", autospec=True, return_value=True) def test_elaborate(self, run_command, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_irun.return_value = "cds_root_irun" find_cds_root_virtuoso.return_value = None @@ -935,11 +901,9 @@ def test_elaborate(self, run_command, find_cds_root_irun, find_cds_root_virtuoso ], ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.incisive_interface.run_command", autospec=True, return_value=False - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.run_command", autospec=True, return_value=False) def test_elaborate_fail( self, run_command, find_cds_root_irun, find_cds_root_virtuoso ): @@ -961,10 +925,10 @@ def test_elaborate_fail( ] ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") @mock.patch( - "vunit.incisive_interface.run_command", autospec=True, side_effect=[True, False] + "vunit.sim_if.incisive.run_command", autospec=True, side_effect=[True, False] ) def test_simulate_fail( self, run_command, find_cds_root_irun, find_cds_root_virtuoso @@ -993,11 +957,9 @@ def test_simulate_fail( ] ) - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_virtuoso") - @mock.patch("vunit.incisive_interface.IncisiveInterface.find_cds_root_irun") - @mock.patch( - "vunit.incisive_interface.run_command", autospec=True, return_value=True - ) + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso") + @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun") + @mock.patch("vunit.sim_if.incisive.run_command", autospec=True, return_value=True) def test_simulate_gui( self, run_command, find_cds_root_irun, find_cds_root_virtuoso ): @@ -1013,7 +975,7 @@ def test_simulate_gui( prefix="prefix", output_path=self.output_path, gui=True ) with mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" + "vunit.sim_if.check_output", autospec=True, return_value="" ) as dummy: simif.compile_project(project) config = make_config() diff --git a/vunit/test/unit/test_location_preprocessor.py b/tests/unit/test_location_preprocessor.py similarity index 100% rename from vunit/test/unit/test_location_preprocessor.py rename to tests/unit/test_location_preprocessor.py diff --git a/vunit/test/unit/test_modelsim_interface.py b/tests/unit/test_modelsim_interface.py similarity index 88% rename from vunit/test/unit/test_modelsim_interface.py rename to tests/unit/test_modelsim_interface.py index a4b425c86..9f068f266 100644 --- a/vunit/test/unit/test_modelsim_interface.py +++ b/tests/unit/test_modelsim_interface.py @@ -13,9 +13,9 @@ from os.path import join, dirname, exists import os from shutil import rmtree -from vunit.modelsim_interface import ModelSimInterface -from vunit.test.mock_2or3 import mock -from vunit.test.common import set_env +from tests.mock_2or3 import mock +from tests.common import set_env +from vunit.sim_if.modelsim import ModelSimInterface from vunit.project import Project from vunit.ostools import renew_path, write_file from vunit.vhdl_standard import VHDL @@ -26,10 +26,8 @@ class TestModelSimInterface(unittest.TestCase): Test the ModelSim interface """ - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.modelsim_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.modelsim.Process", autospec=True) def test_compile_project_vhdl_2008(self, process, check_output): simif = ModelSimInterface( prefix=self.prefix_path, output_path=self.output_path, persistent=False @@ -55,10 +53,8 @@ def test_compile_project_vhdl_2008(self, process, check_output): ] check_output.assert_called_once_with(check_args, env=simif.get_env()) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.modelsim_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.modelsim.Process", autospec=True) def test_compile_project_vhdl_2002(self, process, check_output): simif = ModelSimInterface( prefix=self.prefix_path, output_path=self.output_path, persistent=False @@ -84,10 +80,8 @@ def test_compile_project_vhdl_2002(self, process, check_output): ] check_output.assert_called_once_with(check_args, env=simif.get_env()) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.modelsim_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.modelsim.Process", autospec=True) def test_compile_project_vhdl_93(self, process, check_output): simif = ModelSimInterface( prefix=self.prefix_path, output_path=self.output_path, persistent=False @@ -113,10 +107,8 @@ def test_compile_project_vhdl_93(self, process, check_output): ] check_output.assert_called_once_with(check_args, env=simif.get_env()) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.modelsim_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.modelsim.Process", autospec=True) def test_compile_project_vhdl_extra_flags(self, process, check_output): simif = ModelSimInterface( prefix=self.prefix_path, output_path=self.output_path, persistent=False @@ -143,10 +135,8 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output): ] check_output.assert_called_once_with(check_args, env=simif.get_env()) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.modelsim_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.modelsim.Process", autospec=True) def test_compile_project_verilog(self, process, check_output): simif = ModelSimInterface( prefix=self.prefix_path, output_path=self.output_path, persistent=False @@ -171,10 +161,8 @@ def test_compile_project_verilog(self, process, check_output): ] check_output.assert_called_once_with(check_args, env=simif.get_env()) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.modelsim_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.modelsim.Process", autospec=True) def test_compile_project_system_verilog(self, process, check_output): simif = ModelSimInterface( prefix=self.prefix_path, output_path=self.output_path, persistent=False @@ -200,10 +188,8 @@ def test_compile_project_system_verilog(self, process, check_output): ] check_output.assert_called_once_with(check_args, env=simif.get_env()) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.modelsim_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.modelsim.Process", autospec=True) def test_compile_project_verilog_extra_flags(self, process, check_output): simif = ModelSimInterface( prefix=self.prefix_path, output_path=self.output_path, persistent=False @@ -231,10 +217,8 @@ def test_compile_project_verilog_extra_flags(self, process, check_output): ] check_output.assert_called_once_with(check_args, env=simif.get_env()) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.modelsim_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.modelsim.Process", autospec=True) def test_compile_project_verilog_include(self, process, check_output): simif = ModelSimInterface( prefix=self.prefix_path, output_path=self.output_path, persistent=False @@ -262,10 +246,8 @@ def test_compile_project_verilog_include(self, process, check_output): ] check_output.assert_called_once_with(check_args, env=simif.get_env()) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.modelsim_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.modelsim.Process", autospec=True) def test_compile_project_verilog_define(self, process, check_output): simif = ModelSimInterface( prefix=self.prefix_path, output_path=self.output_path, persistent=False diff --git a/vunit/test/unit/test_ostools.py b/tests/unit/test_ostools.py similarity index 100% rename from vunit/test/unit/test_ostools.py rename to tests/unit/test_ostools.py diff --git a/vunit/test/unit/test_project.py b/tests/unit/test_project.py similarity index 99% rename from vunit/test/unit/test_project.py rename to tests/unit/test_project.py index b8f3852ee..15827a9bd 100644 --- a/vunit/test/unit/test_project.py +++ b/tests/unit/test_project.py @@ -17,7 +17,7 @@ import os from time import sleep import itertools -from vunit.test.mock_2or3 import mock +from tests.mock_2or3 import mock from vunit.exceptions import CompileError from vunit.ostools import renew_path, write_file from vunit.project import Project diff --git a/vunit/test/unit/test_rivierapro_interface.py b/tests/unit/test_rivierapro_interface.py similarity index 87% rename from vunit/test/unit/test_rivierapro_interface.py rename to tests/unit/test_rivierapro_interface.py index a821f1898..c9ba83d6e 100644 --- a/vunit/test/unit/test_rivierapro_interface.py +++ b/tests/unit/test_rivierapro_interface.py @@ -13,8 +13,8 @@ from os.path import join, dirname, exists import os from shutil import rmtree -from vunit.rivierapro_interface import RivieraProInterface -from vunit.test.mock_2or3 import mock +from tests.mock_2or3 import mock +from vunit.sim_if.rivierapro import RivieraProInterface from vunit.project import Project from vunit.ostools import renew_path, write_file from vunit.vhdl_standard import VHDL @@ -25,10 +25,8 @@ class TestRivieraProInterface(unittest.TestCase): Test the RivieraPro interface """ - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.rivierapro_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_vhdl_2019(self, process, check_output): simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) project = Project() @@ -62,10 +60,8 @@ def test_compile_project_vhdl_2019(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.rivierapro_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_vhdl_2008(self, process, check_output): simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) project = Project() @@ -99,10 +95,8 @@ def test_compile_project_vhdl_2008(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.rivierapro_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_vhdl_2002(self, process, check_output): simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) project = Project() @@ -136,10 +130,8 @@ def test_compile_project_vhdl_2002(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.rivierapro_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_vhdl_93(self, process, check_output): simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) project = Project() @@ -173,10 +165,8 @@ def test_compile_project_vhdl_93(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.rivierapro_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_vhdl_extra_flags(self, process, check_output): simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) project = Project() @@ -211,10 +201,8 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.rivierapro_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_verilog(self, process, check_output): library_cfg = join(self.output_path, "library.cfg") simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) @@ -248,10 +236,8 @@ def test_compile_project_verilog(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.rivierapro_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_system_verilog(self, process, check_output): library_cfg = join(self.output_path, "library.cfg") simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) @@ -286,10 +272,8 @@ def test_compile_project_system_verilog(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.rivierapro_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_verilog_extra_flags(self, process, check_output): library_cfg = join(self.output_path, "library.cfg") simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) @@ -326,10 +310,8 @@ def test_compile_project_verilog_extra_flags(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.rivierapro_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_verilog_include(self, process, check_output): library_cfg = join(self.output_path, "library.cfg") simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) @@ -364,10 +346,8 @@ def test_compile_project_verilog_include(self, process, check_output): env=simif.get_env(), ) - @mock.patch( - "vunit.simulator_interface.check_output", autospec=True, return_value="" - ) - @mock.patch("vunit.rivierapro_interface.Process", autospec=True) + @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") + @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_verilog_define(self, process, check_output): library_cfg = join(self.output_path, "library.cfg") simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) diff --git a/vunit/test/unit/test_simulator_interface.py b/tests/unit/test_simulator_interface.py similarity index 95% rename from vunit/test/unit/test_simulator_interface.py rename to tests/unit/test_simulator_interface.py index 0e8243f11..d53ba2e26 100644 --- a/vunit/test/unit/test_simulator_interface.py +++ b/tests/unit/test_simulator_interface.py @@ -13,15 +13,15 @@ import os import subprocess from shutil import rmtree +from tests.mock_2or3 import mock from vunit.project import Project -from vunit.simulator_interface import ( +from vunit.sim_if import ( SimulatorInterface, BooleanOption, ListOfStringOption, StringOption, VHDLAssertLevelOption, ) -from vunit.test.mock_2or3 import mock from vunit.exceptions import CompileError from vunit.ostools import renew_path, write_file @@ -44,9 +44,7 @@ def test_compile_source_files(self): file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl") project.add_manual_dependency(file2, depends_on=file1) - with mock.patch( - "vunit.simulator_interface.check_output", autospec=True - ) as check_output: + with mock.patch("vunit.sim_if.check_output", autospec=True) as check_output: check_output.side_effect = iter(["", ""]) printer = MockPrinter() simif.compile_source_files(project, printer=printer) @@ -122,9 +120,7 @@ def check_output_side_effect( simif.compile_source_file_command.side_effect = compile_source_file_command - with mock.patch( - "vunit.simulator_interface.check_output", autospec=True - ) as check_output: + with mock.patch("vunit.sim_if.check_output", autospec=True) as check_output: check_output.side_effect = check_output_side_effect printer = MockPrinter() self.assertRaises( @@ -168,9 +164,7 @@ def test_compile_source_files_check_output_error(self): write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") - with mock.patch( - "vunit.simulator_interface.check_output", autospec=True - ) as check_output: + with mock.patch("vunit.sim_if.check_output", autospec=True) as check_output: def check_output_side_effect( command, env=None @@ -208,9 +202,7 @@ def test_compile_source_files_create_command_error(self): write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") - with mock.patch( - "vunit.simulator_interface.check_output", autospec=True - ) as check_output: + with mock.patch("vunit.sim_if.check_output", autospec=True) as check_output: check_output.return_value = "" def raise_compile_error(source_file): # pylint: disable=unused-argument diff --git a/vunit/test/unit/test_test_bench.py b/tests/unit/test_test_bench.py similarity index 98% rename from vunit/test/unit/test_test_bench.py rename to tests/unit/test_test_bench.py index 56fecda4c..a5068c884 100644 --- a/vunit/test/unit/test_test_bench.py +++ b/tests/unit/test_test_bench.py @@ -14,7 +14,9 @@ import unittest from os.path import join -from vunit.test_bench import ( +from tests.mock_2or3 import mock +from tests.common import with_tempdir, get_vhdl_test_bench +from vunit.test.bench import ( TestBench, _remove_verilog_comments, _find_tests, @@ -29,8 +31,6 @@ ) from vunit.configuration import AttributeException from vunit.ostools import write_file -from vunit.test.mock_2or3 import mock -from vunit.test.common import with_tempdir, get_vhdl_test_bench class TestTestBench(unittest.TestCase): @@ -588,7 +588,7 @@ def test_find_explicit_tests_verilog(self): self.assertEqual(test2.location.lineno, 6) def test_find_implicit_test_vhdl(self): - with mock.patch("vunit.test_bench.LOGGER") as logger: + with mock.patch("vunit.test.bench.LOGGER") as logger: (test,) = _find_tests( """\ @@ -601,7 +601,7 @@ def test_find_implicit_test_vhdl(self): self.assertEqual(test.location.lineno, 2) assert not logger.warning.called - with mock.patch("vunit.test_bench.LOGGER") as logger: + with mock.patch("vunit.test.bench.LOGGER") as logger: (test,) = _find_tests( """\ @@ -614,7 +614,7 @@ def test_find_implicit_test_vhdl(self): self.assertEqual(test.location.lineno, 1) assert logger.warning.called - with mock.patch("vunit.test_bench.LOGGER") as logger: + with mock.patch("vunit.test.bench.LOGGER") as logger: (test,) = _find_tests( """\ @@ -627,7 +627,7 @@ def test_find_implicit_test_vhdl(self): assert logger.warning.called def test_find_implicit_test_verilog(self): - with mock.patch("vunit.test_bench.LOGGER") as logger: + with mock.patch("vunit.test.bench.LOGGER") as logger: (test,) = _find_tests( """\ @@ -639,7 +639,7 @@ def test_find_implicit_test_verilog(self): self.assertEqual(test.location.lineno, 2) assert not logger.warning.called - with mock.patch("vunit.test_bench.LOGGER") as logger: + with mock.patch("vunit.test.bench.LOGGER") as logger: (test,) = _find_tests( """\ TEST_SUITE @@ -651,7 +651,7 @@ def test_find_implicit_test_verilog(self): self.assertEqual(test.location.lineno, 1) assert logger.warning.called - with mock.patch("vunit.test_bench.LOGGER") as logger: + with mock.patch("vunit.test.bench.LOGGER") as logger: (test,) = _find_tests( """\ """, @@ -662,7 +662,7 @@ def test_find_implicit_test_verilog(self): self.assertEqual(test.location.lineno, 1) assert logger.warning.called - @mock.patch("vunit.test_bench.LOGGER") + @mock.patch("vunit.test.bench.LOGGER") def test_duplicate_tests_cause_error(self, mock_logger): file_name = "file.vhd" self.assertRaises( diff --git a/vunit/test/unit/test_test_bench_list.py b/tests/unit/test_test_bench_list.py similarity index 89% rename from vunit/test/unit/test_test_bench_list.py rename to tests/unit/test_test_bench_list.py index 433016971..d25c134a6 100644 --- a/vunit/test/unit/test_test_bench_list.py +++ b/tests/unit/test_test_bench_list.py @@ -14,10 +14,10 @@ import unittest from os.path import join -from vunit.test_bench_list import TestBenchList, tb_filter -from vunit.test.unit.test_test_bench import Entity, Module -from vunit.test.mock_2or3 import mock -from vunit.test.common import with_tempdir +from tests.unit.test_test_bench import Entity, Module +from tests.mock_2or3 import mock +from tests.common import with_tempdir +from vunit.test.bench_list import TestBenchList, tb_filter class TestTestBenchList(unittest.TestCase): @@ -52,7 +52,7 @@ def test_tb_filter_match_prefix_and_suffix_only(self, tempdir): """ Issue #263 """ - with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: + with mock.patch("vunit.test.bench_list.LOGGER", autospec=True) as logger: design_unit = Entity("mul_tbl_scale", file_name=join(tempdir, "file.vhd")) self.assertFalse(tb_filter(design_unit)) self.assertFalse(logger.warning.called) @@ -64,7 +64,7 @@ def test_tb_filter_warning_on_missing_runner_cfg_when_matching_tb_pattern( design_unit = Module("tb_module_not_ok", file_name=join(tempdir, "file.vhd")) design_unit.generic_names = [] - with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: + with mock.patch("vunit.test.bench_list.LOGGER", autospec=True) as logger: self.assertFalse(tb_filter(design_unit)) logger.warning.assert_has_calls( [ @@ -88,7 +88,7 @@ def test_tb_filter_warning_on_runner_cfg_but_not_matching_tb_pattern(self, tempd ) design_unit.generic_names = ["runner_cfg"] - with mock.patch("vunit.test_bench_list.LOGGER", autospec=True) as logger: + with mock.patch("vunit.test.bench_list.LOGGER", autospec=True) as logger: self.assertTrue(tb_filter(design_unit)) logger.warning.assert_has_calls( [ diff --git a/vunit/test/unit/test_test_report.py b/tests/unit/test_test_report.py similarity index 99% rename from vunit/test/unit/test_test_report.py rename to tests/unit/test_test_report.py index df0b79d79..88d13349a 100644 --- a/vunit/test/unit/test_test_report.py +++ b/tests/unit/test_test_report.py @@ -12,7 +12,7 @@ from xml.etree import ElementTree from os.path import join, dirname import os -from vunit.test_report import TestReport, PASSED, SKIPPED, FAILED +from vunit.test.report import TestReport, PASSED, SKIPPED, FAILED class TestTestReport(TestCase): diff --git a/vunit/test/unit/test_test_runner.py b/tests/unit/test_test_runner.py similarity index 97% rename from vunit/test/unit/test_test_runner.py rename to tests/unit/test_test_runner.py index 0d1535741..aa2e6da33 100644 --- a/vunit/test/unit/test_test_runner.py +++ b/tests/unit/test_test_runner.py @@ -8,18 +8,17 @@ Test the test runner """ - from __future__ import print_function import unittest from os.path import join, abspath +from tests.mock_2or3 import mock +from tests.common import with_tempdir from vunit.hashing import hash_string -from vunit.test_runner import TestRunner, create_output_path -from vunit.test_report import TestReport -from vunit.test_list import TestList -from vunit.test.mock_2or3 import mock -from vunit.test.common import with_tempdir +from vunit.test.runner import TestRunner, create_output_path +from vunit.test.report import TestReport +from vunit.test.list import TestList class TestTestRunner(unittest.TestCase): diff --git a/vunit/test/unit/test_test_suites.py b/tests/unit/test_test_suites.py similarity index 96% rename from vunit/test/unit/test_test_suites.py rename to tests/unit/test_test_suites.py index c367369e1..0b13baa39 100644 --- a/vunit/test/unit/test_test_suites.py +++ b/tests/unit/test_test_suites.py @@ -10,10 +10,10 @@ from os.path import join from unittest import TestCase -from vunit.test_suites import TestRun -from vunit.test_report import PASSED, SKIPPED, FAILED -from vunit.test.common import create_tempdir -from vunit.simulator_interface import SimulatorInterface +from tests.common import create_tempdir +from vunit.test.suites import TestRun +from vunit.test.report import PASSED, SKIPPED, FAILED +from vunit.sim_if import SimulatorInterface class TestTestSuites(TestCase): diff --git a/vunit/test/unit/test_tokenizer.py b/tests/unit/test_tokenizer.py similarity index 98% rename from vunit/test/unit/test_tokenizer.py rename to tests/unit/test_tokenizer.py index 258afeb44..8429e05a2 100644 --- a/vunit/test/unit/test_tokenizer.py +++ b/tests/unit/test_tokenizer.py @@ -9,8 +9,8 @@ """ from unittest import TestCase +from tests.mock_2or3 import mock from vunit.parsing.tokenizer import describe_location -from vunit.test.mock_2or3 import mock class TestTokenizer(TestCase): diff --git a/vunit/test/unit/test_ui.py b/tests/unit/test_ui.py similarity index 98% rename from vunit/test/unit/test_ui.py rename to tests/unit/test_ui.py index d971151aa..2dc3909d8 100644 --- a/vunit/test/unit/test_ui.py +++ b/tests/unit/test_ui.py @@ -19,13 +19,13 @@ import re from re import MULTILINE from shutil import rmtree -from vunit.ui.vunit import VUnit +from tests.mock_2or3 import mock +from tests.common import set_env, with_tempdir, create_vhdl_test_bench_file +from vunit.ui import VUnit from vunit.source_file import VHDL_EXTENSIONS, VERILOG_EXTENSIONS -from vunit.test.mock_2or3 import mock -from vunit.test.common import set_env, with_tempdir, create_vhdl_test_bench_file from vunit.ostools import renew_path from vunit.builtins import add_verilog_include_dir -from vunit.simulator_interface import SimulatorInterface +from vunit.sim_if import SimulatorInterface class TestUi(unittest.TestCase): @@ -159,7 +159,7 @@ def test_locally_specified_preprocessors_should_be_used_instead_of_any_globally_ ) self.assertEqual(fread.read(), expectd) - @mock.patch("vunit.ui.vunit.LOGGER.error", autospec=True) + @mock.patch("vunit.ui.LOGGER.error", autospec=True) def test_recovers_from_preprocessing_error(self, logger): ui = self._create_ui() ui.add_library("lib") @@ -906,7 +906,7 @@ def test_verilog_file_has_vhdl_standard_none(self): source_file = lib.add_source_file(file_name) self.assertEqual(source_file.vhdl_standard, None) - @mock.patch("vunit.test_bench_list.LOGGER", autospec=True) + @mock.patch("vunit.test.bench_list.LOGGER", autospec=True) def test_warning_on_no_tests(self, logger): ui = self._create_ui("--compile") self._run_main(ui) @@ -1092,7 +1092,7 @@ def test_can_list_files_without_simulator(self): ui = self._create_ui_real_sim("--files") self._run_main(ui, 0) - @mock.patch("vunit.ui.vunit.LOGGER", autospec=True) + @mock.patch("vunit.ui.LOGGER", autospec=True) def test_compile_without_simulator_fails(self, logger): with set_env(): ui = self._create_ui_real_sim("--compile") @@ -1102,7 +1102,7 @@ def test_compile_without_simulator_fails(self, logger): "No available simulator detected" in str(logger.error.mock_calls) ) - @mock.patch("vunit.ui.vunit.LOGGER", autospec=True) + @mock.patch("vunit.ui.LOGGER", autospec=True) def test_simulate_without_simulator_fails(self, logger): with set_env(): ui = self._create_ui_real_sim() @@ -1187,7 +1187,7 @@ def test_get_testbench_files(self): def _create_ui(self, *args): """ Create an instance of the VUnit public interface class """ with mock.patch( - "vunit.simulator_factory.SIMULATOR_FACTORY.select_simulator", + "vunit.sim_if.factory.SIMULATOR_FACTORY.select_simulator", new=lambda: MockSimulator, ): return self._create_ui_real_sim(*args) diff --git a/vunit/test/unit/test_verilog_parser.py b/tests/unit/test_verilog_parser.py similarity index 99% rename from vunit/test/unit/test_verilog_parser.py rename to tests/unit/test_verilog_parser.py index 1dd873481..ee6155fa8 100644 --- a/vunit/test/unit/test_verilog_parser.py +++ b/tests/unit/test_verilog_parser.py @@ -13,9 +13,9 @@ from os.path import join, dirname, exists import time import shutil +from tests.mock_2or3 import mock from vunit.ostools import renew_path from vunit.parsing.verilog.parser import VerilogParser -from vunit.test.mock_2or3 import mock class TestVerilogParser(TestCase): # pylint: disable=too-many-public-methods diff --git a/vunit/test/unit/test_verilog_preprocessor.py b/tests/unit/test_verilog_preprocessor.py similarity index 99% rename from vunit/test/unit/test_verilog_preprocessor.py rename to tests/unit/test_verilog_preprocessor.py index 2c08f5bc9..99f8a6be4 100644 --- a/vunit/test/unit/test_verilog_preprocessor.py +++ b/tests/unit/test_verilog_preprocessor.py @@ -16,11 +16,11 @@ import os from unittest import TestCase import shutil +from tests.mock_2or3 import mock from vunit.ostools import renew_path, write_file from vunit.parsing.verilog.preprocess import VerilogPreprocessor, Macro from vunit.parsing.verilog.tokenizer import VerilogTokenizer from vunit.parsing.tokenizer import Token -from vunit.test.mock_2or3 import mock class TestVerilogPreprocessor(TestCase): diff --git a/vunit/test/unit/test_verilog_tokenizer.py b/tests/unit/test_verilog_tokenizer.py similarity index 100% rename from vunit/test/unit/test_verilog_tokenizer.py rename to tests/unit/test_verilog_tokenizer.py diff --git a/vunit/test/unit/test_vhdl_parser.py b/tests/unit/test_vhdl_parser.py similarity index 100% rename from vunit/test/unit/test_vhdl_parser.py rename to tests/unit/test_vhdl_parser.py diff --git a/vunit/test/unit/test_vhdl_standard.py b/tests/unit/test_vhdl_standard.py similarity index 100% rename from vunit/test/unit/test_vhdl_standard.py rename to tests/unit/test_vhdl_standard.py diff --git a/tox.ini b/tox.ini index 397c2b3f1..bf18fbe67 100644 --- a/tox.ini +++ b/tox.ini @@ -25,8 +25,8 @@ setenv= commands= fmt: {envpython} -m black ./ --exclude 'vunit\/vhdl\/JSON-for-VHDL|\.eggs|\.git|\.hg|\.mypy_cache|\.nox|\.tox|\.venv|_build|buck-out|build|dist' {posargs} - unit: {envpython} -m pytest -v vunit/test/unit - lint: {envpython} -m pytest -v vunit/test/lint + unit: {envpython} -m pytest -v tests/unit + lint: {envpython} -m pytest -v tests/lint docs: {envpython} tools/build_docs.py {envtmpdir}/docsbuild - acceptance: {envpython} -m pytest -v vunit/test/acceptance + acceptance: {envpython} -m pytest -v tests/acceptance vcomponents: {envpython} vunit/vhdl/verification_components/run.py --clean diff --git a/vunit/__init__.py b/vunit/__init__.py index 7a20c0039..776a4f7ac 100644 --- a/vunit/__init__.py +++ b/vunit/__init__.py @@ -10,7 +10,7 @@ from os.path import dirname, join, abspath import vunit.version_check -from vunit.ui.vunit import VUnit +from vunit.ui import VUnit from vunit.vunit_cli import VUnitCLI from vunit.about import version, doc from vunit.json4vhdl import read_json, encode_json diff --git a/vunit/builtins.py b/vunit/builtins.py index 6aed91290..f6548f4ff 100644 --- a/vunit/builtins.py +++ b/vunit/builtins.py @@ -8,11 +8,10 @@ Functions to add builtin VHDL code to a project for compilation """ - from os.path import join, abspath, dirname, basename from glob import glob from vunit.vhdl_standard import VHDL -from vunit.test.common import simulator_check +from vunit.sim_if.common import simulator_check VHDL_PATH = abspath(join(dirname(__file__), "vhdl")) VERILOG_PATH = abspath(join(dirname(__file__), "verilog")) diff --git a/vunit/configuration.py b/vunit/configuration.py index c12a2b332..46f1805c2 100644 --- a/vunit/configuration.py +++ b/vunit/configuration.py @@ -12,7 +12,7 @@ import inspect from os.path import dirname from copy import copy -from vunit.simulator_factory import SIMULATOR_FACTORY +from vunit.sim_if.factory import SIMULATOR_FACTORY LOGGER = logging.getLogger(__name__) diff --git a/vunit/simulator_interface.py b/vunit/sim_if/__init__.py similarity index 98% rename from vunit/simulator_interface.py rename to vunit/sim_if/__init__.py index 0bef26ba9..0204ed080 100644 --- a/vunit/simulator_interface.py +++ b/vunit/sim_if/__init__.py @@ -5,16 +5,17 @@ # Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com """ -Generic simulator interface +Simulator interface(s) """ from __future__ import print_function + import sys import os import subprocess -from vunit.ostools import Process, simplify_path -from vunit.exceptions import CompileError -from vunit.color_printer import NO_COLOR_PRINTER +from ..ostools import Process, simplify_path +from ..exceptions import CompileError +from ..color_printer import NO_COLOR_PRINTER class SimulatorInterface(object): # pylint: disable=too-many-public-methods diff --git a/vunit/activehdl_interface.py b/vunit/sim_if/activehdl.py similarity index 97% rename from vunit/activehdl_interface.py rename to vunit/sim_if/activehdl.py index 5ecf8c322..33addc316 100644 --- a/vunit/activehdl_interface.py +++ b/vunit/sim_if/activehdl.py @@ -8,23 +8,18 @@ Interface towards Aldec Active HDL """ - from __future__ import print_function from os.path import join, dirname, abspath import os import re import logging -from vunit.ostools import Process, write_file, file_exists, renew_path -from vunit.test_suites import get_result_file_name -from vunit.vhdl_standard import VHDL -from vunit.vsim_simulator_mixin import get_is_test_suite_done_tcl, fix_path -from vunit.simulator_interface import ( - SimulatorInterface, - ListOfStringOption, - StringOption, -) -from vunit.exceptions import CompileError +from ..exceptions import CompileError +from ..ostools import Process, write_file, file_exists, renew_path +from ..vhdl_standard import VHDL +from ..test.suites import get_result_file_name +from . import SimulatorInterface, ListOfStringOption, StringOption +from .vsim_simulator_mixin import get_is_test_suite_done_tcl, fix_path LOGGER = logging.getLogger(__name__) diff --git a/vunit/cds_file.py b/vunit/sim_if/cds_file.py similarity index 97% rename from vunit/cds_file.py rename to vunit/sim_if/cds_file.py index 9c7f11dd6..f6526faa0 100644 --- a/vunit/cds_file.py +++ b/vunit/sim_if/cds_file.py @@ -9,7 +9,7 @@ """ import re -from vunit.ostools import read_file, write_file +from ..ostools import read_file, write_file class CDSFile(dict): diff --git a/vunit/sim_if/common.py b/vunit/sim_if/common.py new file mode 100644 index 000000000..ea5ed6a3a --- /dev/null +++ b/vunit/sim_if/common.py @@ -0,0 +1,35 @@ +# This Source Code Form is subject to the terms of the Mozilla Public +# License, v. 2.0. If a copy of the MPL was not distributed with this file, +# You can obtain one at http://mozilla.org/MPL/2.0/. +# +# Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com + +""" +Common functions +""" + +from .factory import SIMULATOR_FACTORY + + +def has_simulator(): + return SIMULATOR_FACTORY.has_simulator + + +def simulator_is(*names): + """ + Check that current simulator is any of names + """ + supported_names = [sim.name for sim in SIMULATOR_FACTORY.supported_simulators()] + for name in names: + assert name in supported_names + return SIMULATOR_FACTORY.select_simulator().name in names + + +def simulator_check(func): + """ + Check some method of the selected simulator + """ + simif = SIMULATOR_FACTORY.select_simulator() + if simif is None: + return False + return func(simif) diff --git a/vunit/simulator_factory.py b/vunit/sim_if/factory.py similarity index 92% rename from vunit/simulator_factory.py rename to vunit/sim_if/factory.py index 2d2fde8fa..91b2428d7 100644 --- a/vunit/simulator_factory.py +++ b/vunit/sim_if/factory.py @@ -9,16 +9,12 @@ """ import os -from vunit.modelsim_interface import ModelSimInterface -from vunit.activehdl_interface import ActiveHDLInterface -from vunit.rivierapro_interface import RivieraProInterface -from vunit.ghdl_interface import GHDLInterface -from vunit.incisive_interface import IncisiveInterface -from vunit.simulator_interface import ( - BooleanOption, - ListOfStringOption, - VHDLAssertLevelOption, -) +from .activehdl import ActiveHDLInterface +from .ghdl import GHDLInterface +from .incisive import IncisiveInterface +from .modelsim import ModelSimInterface +from .rivierapro import RivieraProInterface +from . import BooleanOption, ListOfStringOption, VHDLAssertLevelOption class SimulatorFactory(object): diff --git a/vunit/ghdl_interface.py b/vunit/sim_if/ghdl.py similarity index 97% rename from vunit/ghdl_interface.py rename to vunit/sim_if/ghdl.py index 71b92b291..77242341e 100644 --- a/vunit/ghdl_interface.py +++ b/vunit/sim_if/ghdl.py @@ -9,21 +9,17 @@ """ from __future__ import print_function -import logging + from os.path import exists, join, abspath import os +import logging import subprocess import shlex from sys import stdout # To avoid output catched in non-verbose mode -from vunit.ostools import Process -from vunit.vhdl_standard import VHDL -from vunit.simulator_interface import ( - SimulatorInterface, - ListOfStringOption, - StringOption, - BooleanOption, -) -from vunit.exceptions import CompileError +from ..exceptions import CompileError +from ..ostools import Process +from . import SimulatorInterface, ListOfStringOption, StringOption, BooleanOption +from ..vhdl_standard import VHDL LOGGER = logging.getLogger(__name__) diff --git a/vunit/incisive_interface.py b/vunit/sim_if/incisive.py similarity index 98% rename from vunit/incisive_interface.py rename to vunit/sim_if/incisive.py index e3fc41a07..6ab59d4e9 100644 --- a/vunit/incisive_interface.py +++ b/vunit/sim_if/incisive.py @@ -9,20 +9,17 @@ """ from __future__ import print_function -import os + from os.path import join, dirname, abspath, relpath +import os import subprocess import sys import logging -from vunit.ostools import write_file, file_exists -from vunit.simulator_interface import ( - SimulatorInterface, - run_command, - ListOfStringOption, -) -from vunit.vhdl_standard import VHDL -from vunit.exceptions import CompileError -from vunit.cds_file import CDSFile +from ..exceptions import CompileError +from ..ostools import write_file, file_exists +from ..vhdl_standard import VHDL +from . import SimulatorInterface, run_command, ListOfStringOption +from .cds_file import CDSFile LOGGER = logging.getLogger(__name__) diff --git a/vunit/modelsim_interface.py b/vunit/sim_if/modelsim.py similarity index 97% rename from vunit/modelsim_interface.py rename to vunit/sim_if/modelsim.py index 016423520..eae8405f3 100644 --- a/vunit/modelsim_interface.py +++ b/vunit/sim_if/modelsim.py @@ -8,14 +8,13 @@ Interface towards Mentor Graphics ModelSim """ - from __future__ import print_function +from os.path import join, dirname, abspath +import os import logging import sys import io -import os -from os.path import join, dirname, abspath try: # Python 3 @@ -24,15 +23,11 @@ # Python 2 from ConfigParser import RawConfigParser # pylint: disable=import-error -from vunit.ostools import Process, file_exists -from vunit.simulator_interface import ( - SimulatorInterface, - ListOfStringOption, - StringOption, -) -from vunit.exceptions import CompileError -from vunit.vsim_simulator_mixin import VsimSimulatorMixin, fix_path -from vunit.vhdl_standard import VHDL +from ..exceptions import CompileError +from ..ostools import Process, file_exists +from ..vhdl_standard import VHDL +from . import SimulatorInterface, ListOfStringOption, StringOption +from .vsim_simulator_mixin import VsimSimulatorMixin, fix_path LOGGER = logging.getLogger(__name__) diff --git a/vunit/rivierapro_interface.py b/vunit/sim_if/rivierapro.py similarity index 97% rename from vunit/rivierapro_interface.py rename to vunit/sim_if/rivierapro.py index 3c24b15b5..3bd96d524 100644 --- a/vunit/rivierapro_interface.py +++ b/vunit/sim_if/rivierapro.py @@ -8,22 +8,17 @@ Interface towards Aldec Riviera Pro """ - from __future__ import print_function from os.path import join, dirname, abspath import os import re import logging -from vunit.ostools import Process, file_exists -from vunit.simulator_interface import ( - SimulatorInterface, - ListOfStringOption, - StringOption, -) -from vunit.vhdl_standard import VHDL -from vunit.exceptions import CompileError -from vunit.vsim_simulator_mixin import VsimSimulatorMixin, fix_path +from ..exceptions import CompileError +from ..ostools import Process, file_exists +from ..vhdl_standard import VHDL +from . import SimulatorInterface, ListOfStringOption, StringOption +from .vsim_simulator_mixin import VsimSimulatorMixin, fix_path LOGGER = logging.getLogger(__name__) diff --git a/vunit/vsim_simulator_mixin.py b/vunit/sim_if/vsim_simulator_mixin.py similarity index 98% rename from vunit/vsim_simulator_mixin.py rename to vunit/sim_if/vsim_simulator_mixin.py index 22697c13b..4a9a9affc 100644 --- a/vunit/vsim_simulator_mixin.py +++ b/vunit/sim_if/vsim_simulator_mixin.py @@ -12,9 +12,9 @@ import sys import os from os.path import join, dirname, abspath -from vunit.ostools import write_file, Process -from vunit.test_suites import get_result_file_name -from vunit.persistent_tcl_shell import PersistentTclShell +from ..ostools import write_file, Process +from ..test.suites import get_result_file_name +from ..persistent_tcl_shell import PersistentTclShell class VsimSimulatorMixin(object): diff --git a/vunit/source_file.py b/vunit/source_file.py index 27a8a0c7e..0bf9b8fbf 100644 --- a/vunit/source_file.py +++ b/vunit/source_file.py @@ -11,7 +11,7 @@ import logging from copy import copy import traceback -from vunit.simulator_factory import SIMULATOR_FACTORY +from vunit.sim_if.factory import SIMULATOR_FACTORY from vunit.hashing import hash_string from vunit.vhdl_parser import VHDLReference from vunit.cached import file_content_hash diff --git a/vunit/test/__init__.py b/vunit/test/__init__.py index 17b27373b..8375fea15 100644 --- a/vunit/test/__init__.py +++ b/vunit/test/__init__.py @@ -3,3 +3,7 @@ # You can obtain one at http://mozilla.org/MPL/2.0/. # # Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com + +""" +Test bench, runner, etc. +""" diff --git a/vunit/test_bench.py b/vunit/test/bench.py similarity index 97% rename from vunit/test_bench.py rename to vunit/test/bench.py index 396f0faf9..65f83e442 100644 --- a/vunit/test_bench.py +++ b/vunit/test/bench.py @@ -14,15 +14,14 @@ import bisect import collections from collections import OrderedDict -from vunit.ostools import file_exists -from vunit.cached import cached -from vunit.test_list import TestList -from vunit.vhdl_parser import remove_comments as remove_vhdl_comments -from vunit.test_suites import IndependentSimTestCase, SameSimTestSuite -from vunit.parsing.encodings import HDL_FILE_ENCODING -from vunit.source_file import file_type_of, VERILOG_FILE_TYPES -from vunit.configuration import Configuration, ConfigurationVisitor, DEFAULT_NAME - +from ..ostools import file_exists +from ..cached import cached +from ..vhdl_parser import remove_comments as remove_vhdl_comments +from ..parsing.encodings import HDL_FILE_ENCODING +from ..source_file import file_type_of, VERILOG_FILE_TYPES +from ..configuration import Configuration, ConfigurationVisitor, DEFAULT_NAME +from .list import TestList +from .suites import IndependentSimTestCase, SameSimTestSuite LOGGER = logging.getLogger(__name__) diff --git a/vunit/test_bench_list.py b/vunit/test/bench_list.py similarity index 98% rename from vunit/test_bench_list.py rename to vunit/test/bench_list.py index 4437851b5..02061bedd 100644 --- a/vunit/test_bench_list.py +++ b/vunit/test/bench_list.py @@ -7,12 +7,12 @@ """ Contains classes to manage the creation of test benches and runnable test cases thereof """ + import re import logging from collections import OrderedDict -from vunit.test_list import TestList -from vunit.test_bench import TestBench - +from .list import TestList +from .bench import TestBench LOGGER = logging.getLogger(__name__) diff --git a/vunit/test_list.py b/vunit/test/list.py similarity index 98% rename from vunit/test_list.py rename to vunit/test/list.py index 86a094371..b4497de5b 100644 --- a/vunit/test_list.py +++ b/vunit/test/list.py @@ -8,7 +8,7 @@ Functionality to handle lists of test suites and filtering of them """ -from vunit.test_report import PASSED, FAILED +from .report import PASSED, FAILED class TestList(object): diff --git a/vunit/test_report.py b/vunit/test/report.py similarity index 100% rename from vunit/test_report.py rename to vunit/test/report.py diff --git a/vunit/test_runner.py b/vunit/test/runner.py similarity index 99% rename from vunit/test_runner.py rename to vunit/test/runner.py index 6a12b29ab..a5e9753d5 100644 --- a/vunit/test_runner.py +++ b/vunit/test/runner.py @@ -8,7 +8,6 @@ Provided functionality to run a suite of test in a robust way """ - from __future__ import print_function import os @@ -20,9 +19,9 @@ import logging import string from contextlib import contextmanager -from vunit import ostools -from vunit.test_report import PASSED, FAILED, SKIPPED -from vunit.hashing import hash_string +from .. import ostools +from ..hashing import hash_string +from .report import PASSED, FAILED, SKIPPED LOGGER = logging.getLogger(__name__) diff --git a/vunit/test_suites.py b/vunit/test/suites.py similarity index 99% rename from vunit/test_suites.py rename to vunit/test/suites.py index 4b8f90606..f669290bc 100644 --- a/vunit/test_suites.py +++ b/vunit/test/suites.py @@ -8,10 +8,9 @@ Contains different kinds of test suites """ - from os.path import join -from vunit import ostools -from vunit.test_report import PASSED, SKIPPED, FAILED +from .. import ostools +from .report import PASSED, SKIPPED, FAILED class IndependentSimTestCase(object): diff --git a/vunit/ui/__init__.py b/vunit/ui/__init__.py index b4e48fd7f..99c48afb4 100644 --- a/vunit/ui/__init__.py +++ b/vunit/ui/__init__.py @@ -4,6 +4,1037 @@ # # Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com +# pylint: disable=too-many-lines + """ Public VUnit User Interface (UI) """ + +from __future__ import print_function + +import csv +import sys +import traceback +import logging +import json +import os +from os.path import exists, abspath, join, basename, normpath, dirname +from fnmatch import fnmatch +from ..database import PickledDataBase, DataBase +from .. import ostools +from ..vunit_cli import VUnitCLI +from ..sim_if.factory import SIMULATOR_FACTORY +from ..sim_if import SimulatorInterface +from ..color_printer import COLOR_PRINTER, NO_COLOR_PRINTER + +from ..project import Project +from ..exceptions import CompileError +from ..location_preprocessor import LocationPreprocessor +from ..check_preprocessor import CheckPreprocessor +from ..parsing.encodings import HDL_FILE_ENCODING +from ..builtins import Builtins +from ..vhdl_standard import VHDL +from ..test.bench_list import TestBenchList +from ..test.report import TestReport +from ..test.runner import TestRunner + +from .common import LOGGER, select_vhdl_standard, check_not_empty +from .source import SourceFile, SourceFileList +from .library import Library +from .results import Results + + +class VUnit( # pylint: disable=too-many-instance-attributes, too-many-public-methods + object +): + """ + The public interface of VUnit + + :example: + + .. code-block:: python + + from vunit import VUnit + """ + + @classmethod + def from_argv(cls, argv=None, compile_builtins=True, vhdl_standard=None): + """ + Create VUnit instance from command line arguments. + + :param argv: Use explicit argv instead of actual command line argument + :param compile_builtins: Do not compile builtins. Used for VUnit internal testing. + :param vhdl_standard: The VHDL standard used to compile files, + if None the VUNIT_VHDL_STANDARD environment variable is used + :returns: A :class:`.VUnit` object instance + + :example: + + .. code-block:: python + + from vunit import VUnit + prj = VUnit.from_argv() + + """ + args = VUnitCLI().parse_args(argv=argv) + return cls.from_args( + args, compile_builtins=compile_builtins, vhdl_standard=vhdl_standard + ) + + @classmethod + def from_args(cls, args, compile_builtins=True, vhdl_standard=None): + """ + Create VUnit instance from args namespace. + Intended for users who adds custom command line options. + See :class:`vunit.vunit_cli.VUnitCLI` class to learn about + adding custom command line options. + + :param args: The parsed argument namespace object + :param compile_builtins: Do not compile builtins. Used for VUnit internal testing. + :param vhdl_standard: The VHDL standard used to compile files, + if None the VUNIT_VHDL_STANDARD environment variable is used + :returns: A :class:`.VUnit` object instance + + """ + return cls(args, compile_builtins=compile_builtins, vhdl_standard=vhdl_standard) + + def __init__(self, args, compile_builtins=True, vhdl_standard=None): + self._args = args + self._configure_logging(args.log_level) + self._output_path = abspath(args.output_path) + + if args.no_color: + self._printer = NO_COLOR_PRINTER + else: + self._printer = COLOR_PRINTER + + def test_filter(name, attribute_names): + keep = any(fnmatch(name, pattern) for pattern in args.test_patterns) + + if args.with_attributes is not None: + keep = keep and set(args.with_attributes).issubset(attribute_names) + + if args.without_attributes is not None: + keep = keep and set(args.without_attributes).isdisjoint(attribute_names) + return keep + + self._test_filter = test_filter + self._vhdl_standard = select_vhdl_standard(vhdl_standard) + + self._external_preprocessors = [] + self._location_preprocessor = None + self._check_preprocessor = None + + self._simulator_class = SIMULATOR_FACTORY.select_simulator() + + # Use default simulator options if no simulator was present + if self._simulator_class is None: + simulator_class = SimulatorInterface + self._simulator_output_path = join(self._output_path, "none") + else: + simulator_class = self._simulator_class + self._simulator_output_path = join(self._output_path, simulator_class.name) + + self._create_output_path(args.clean) + + database = self._create_database() + self._project = Project( + database=database, + depend_on_package_body=simulator_class.package_users_depend_on_bodies, + ) + + self._test_bench_list = TestBenchList(database=database) + + self._builtins = Builtins(self, self._vhdl_standard, simulator_class) + if compile_builtins: + self.add_builtins() + + def _create_database(self): + """ + Create a persistent database to store expensive parse results + + Check for Python version used to create the database is the + same as the running python instance or re-create + """ + project_database_file_name = join(self._output_path, "project_database") + create_new = False + key = b"version" + version = str((9, sys.version)).encode() + database = None + try: + database = DataBase(project_database_file_name) + create_new = (key not in database) or (database[key] != version) + except KeyboardInterrupt: + raise KeyboardInterrupt + except: # pylint: disable=bare-except + traceback.print_exc() + create_new = True + + if create_new: + database = DataBase(project_database_file_name, new=True) + database[key] = version + + return PickledDataBase(database) + + @staticmethod + def _configure_logging(log_level): + """ + Configure logging based on log_level string + """ + level = getattr(logging, log_level.upper()) + logging.basicConfig( + filename=None, format="%(levelname)7s - %(message)s", level=level + ) + + def _which_vhdl_standard(self, vhdl_standard): + """ + Return default vhdl_standard if the argument is None + The argument is a string from the user + """ + if vhdl_standard is None: + return self._vhdl_standard + + return VHDL.standard(vhdl_standard) + + def add_external_library(self, library_name, path, vhdl_standard=None): + """ + Add an externally compiled library as a black-box + + :param library_name: The name of the external library + :param path: The path to the external library directory + :param vhdl_standard: The VHDL standard used to compile files, + if None the VUNIT_VHDL_STANDARD environment variable is used + :returns: The created :class:`.Library` object + + :example: + + .. code-block:: python + + prj.add_external_library("unisim", "path/to/unisim/") + + """ + + self._project.add_library( + library_name, + abspath(path), + self._which_vhdl_standard(vhdl_standard), + is_external=True, + ) + return self.library(library_name) + + def add_source_files_from_csv(self, project_csv_path, vhdl_standard=None): + """ + Add a project configuration, mapping all the libraries and files + + :param project_csv_path: path to csv project specification, each line contains the name + of the library and the path to one file 'lib_name,filename' + note that all filenames are relative to the parent folder of the + csv file + :param vhdl_standard: The VHDL standard used to compile files, + if None, the VUNIT_VHDL_STANDARD environment variable is used + :returns: A list of files (:class `.SourceFileList`) that were added + + """ + libs = set() + files = SourceFileList(list()) + + with open(project_csv_path) as csv_path_file: + for row in csv.reader(csv_path_file): + if len(row) == 2: + lib_name = row[0].strip() + no_normalized_file = row[1].strip() + file_name_ = normpath( + join(dirname(project_csv_path), no_normalized_file) + ) + lib = ( + self.library(lib_name) + if lib_name in libs + else self.add_library(lib_name) + ) + libs.add(lib_name) + file_ = lib.add_source_file(file_name_, vhdl_standard=vhdl_standard) + files.append(file_) + elif len(row) > 2: + LOGGER.error( + "More than one library and one file in csv description" + ) + return files + + def add_library(self, library_name, vhdl_standard=None, allow_duplicate=False): + """ + Add a library managed by VUnit. + + :param library_name: The name of the library + :param vhdl_standard: The VHDL standard used to compile files, + if None the VUNIT_VHDL_STANDARD environment variable is used + :param allow_duplicate: Set to True to allow the same library + to be added multiple times. Subsequent additions will just + return the previously created library. + :returns: The created :class:`.Library` object + + :example: + + .. code-block:: python + + library = prj.add_library("lib") + + """ + vhdl_standard = self._which_vhdl_standard(vhdl_standard) + + path = join(self._simulator_output_path, "libraries", library_name) + if not self._project.has_library(library_name): + self._project.add_library(library_name, abspath(path), vhdl_standard) + elif not allow_duplicate: + raise ValueError( + "Library %s already added. Use allow_duplicate to ignore this error." + % library_name + ) + return self.library(library_name) + + def library(self, library_name): + """ + Get a library + + :param library_name: The name of the library + :returns: A :class:`.Library` object + """ + if not self._project.has_library(library_name): + raise KeyError(library_name) + return Library(library_name, self, self._project, self._test_bench_list) + + def set_attribute(self, name, value, allow_empty=False): + """ + Set a value of attribute in all |configurations| + + :param name: The name of the attribute + :param value: The value of the attribute + :param allow_empty: To disable an error when no test benches were found + + :example: + + .. code-block:: python + + prj.set_attribute(".foo", "bar") + + .. note:: + Only affects test benches added *before* the attribute is set. + """ + test_benches = self._test_bench_list.get_test_benches() + for test_bench in check_not_empty( + test_benches, allow_empty, "No test benches found" + ): + test_bench.set_attribute(name, value) + + def set_generic(self, name, value, allow_empty=False): + """ + Set a value of generic in all |configurations| + + :param name: The name of the generic + :param value: The value of the generic + :param allow_empty: To disable an error when no test benches were found + + :example: + + .. code-block:: python + + prj.set_generic("data_width", 16) + + .. note:: + Only affects test benches added *before* the generic is set. + """ + test_benches = self._test_bench_list.get_test_benches() + for test_bench in check_not_empty( + test_benches, allow_empty, "No test benches found" + ): + test_bench.set_generic(name.lower(), value) + + def set_parameter(self, name, value, allow_empty=False): + """ + Set value of parameter in all |configurations| + + :param name: The name of the parameter + :param value: The value of the parameter + :param allow_empty: To disable an error when no test benches were found + + :example: + + .. code-block:: python + + prj.set_parameter("data_width", 16) + + .. note:: + Only affects test benches added *before* the parameter is set. + """ + test_benches = self._test_bench_list.get_test_benches() + for test_bench in check_not_empty( + test_benches, allow_empty, "No test benches found" + ): + test_bench.set_generic(name, value) + + def set_sim_option(self, name, value, allow_empty=False, overwrite=True): + """ + Set simulation option in all |configurations| + + :param name: |simulation_options| + :param value: The value of the simulation option + :param allow_empty: To disable an error when no test benches were found + :param overwrite: To overwrite the option or append to the existing value + + :example: + + .. code-block:: python + + prj.set_sim_option("ghdl.flags", ["--no-vital-checks"]) + + .. note:: + Only affects test benches added *before* the option is set. + """ + test_benches = self._test_bench_list.get_test_benches() + for test_bench in check_not_empty( + test_benches, allow_empty, "No test benches found" + ): + test_bench.set_sim_option(name, value, overwrite) + + def set_compile_option(self, name, value, allow_empty=False): + """ + Set compile option of all files + + :param name: |compile_option| + :param value: The value of the compile option + :param allow_empty: To disable an error when no source files were found + + :example: + + .. code-block:: python + + prj.set_compile_option("ghdl.flags", ["--no-vital-checks"]) + + + .. note:: + Only affects files added *before* the option is set. + """ + source_files = self._project.get_source_files_in_order() + for source_file in check_not_empty( + source_files, allow_empty, "No source files found" + ): + source_file.set_compile_option(name, value) + + def add_compile_option(self, name, value, allow_empty=False): + """ + Add compile option to all files + + :param name: |compile_option| + :param value: The value of the compile option + :param allow_empty: To disable an error when no source files were found + + .. note:: + Only affects files added *before* the option is set. + """ + source_files = self._project.get_source_files_in_order() + for source_file in check_not_empty( + source_files, allow_empty, "No source files found" + ): + source_file.add_compile_option(name, value) + + def get_source_file(self, file_name, library_name=None): + """ + Get a source file + + :param file_name: The name of the file as a relative or absolute path + :param library_name: The name of a specific library to search if not all libraries + :returns: A :class:`.SourceFile` object + """ + + files = self.get_source_files(file_name, library_name, allow_empty=True) + if len(files) > 1: + raise ValueError( + "Found file named '%s' in multiple-libraries, " + "add explicit library_name." % file_name + ) + if not files: + if library_name is None: + raise ValueError("Found no file named '%s'" % file_name) + + raise ValueError( + "Found no file named '%s' in library '%s'" % (file_name, library_name) + ) + return files[0] + + def get_source_files(self, pattern="*", library_name=None, allow_empty=False): + """ + Get a list of source files + + :param pattern: A wildcard pattern matching either an absolute or relative path + :param library_name: The name of a specific library to search if not all libraries + :param allow_empty: To disable an error if no files matched the pattern + :returns: A :class:`.SourceFileList` object + """ + results = [] + for source_file in self._project.get_source_files_in_order(): + if library_name is not None: + if source_file.library.name != library_name: + continue + + if not ( + fnmatch(abspath(source_file.name), pattern) + or fnmatch(ostools.simplify_path(source_file.name), pattern) + ): + continue + + results.append(SourceFile(source_file, self._project, self)) + + check_not_empty( + results, + allow_empty, + ("Pattern %r did not match any file" % pattern) + + ( + ("within library %s" % library_name) if library_name is not None else "" + ), + ) + + return SourceFileList(results) + + def add_source_files( # pylint: disable=too-many-arguments + self, + pattern, + library_name, + preprocessors=None, + include_dirs=None, + defines=None, + allow_empty=False, + vhdl_standard=None, + no_parse=False, + file_type=None, + ): + """ + Add source files matching wildcard pattern to library + + :param pattern: A wildcard pattern matching the files to add or a list of files + :param library_name: The name of the library to add files into + :param include_dirs: A list of include directories + :param defines: A dictionary containing Verilog defines to be set + :param allow_empty: To disable an error if no files matched the pattern + :param vhdl_standard: The VHDL standard used to compile files, + if None VUNIT_VHDL_STANDARD environment variable is used + :param no_parse: Do not parse file(s) for dependency or test scanning purposes + :param file_type: The type of the file; ``"vhdl"``, ``"verilog"`` or ``"systemverilog"``. + Auto-detected by default when set to ``None``. + :returns: A list of files (:class:`.SourceFileList`) which were added + + :example: + + .. code-block:: python + + prj.add_source_files("*.vhd", "lib") + + """ + return self.library(library_name).add_source_files( + pattern=pattern, + preprocessors=preprocessors, + include_dirs=include_dirs, + defines=defines, + allow_empty=allow_empty, + vhdl_standard=vhdl_standard, + no_parse=no_parse, + file_type=file_type, + ) + + def add_source_file( # pylint: disable=too-many-arguments + self, + file_name, + library_name, + preprocessors=None, + include_dirs=None, + defines=None, + vhdl_standard=None, + no_parse=False, + file_type=None, + ): + """ + Add source file to library + + :param file_name: The name of the file + :param library_name: The name of the library to add the file into + :param include_dirs: A list of include directories + :param defines: A dictionary containing Verilog defines to be set + :param vhdl_standard: The VHDL standard used to compile this file, + if None VUNIT_VHDL_STANDARD environment variable is used + :param no_parse: Do not parse file for dependency or test scanning purposes + :param file_type: The type of the file; ``"vhdl"``, ``"verilog"`` or ``"systemverilog"``. + Auto-detected by default when set to ``None``. + :returns: The :class:`.SourceFile` which was added + + :example: + + .. code-block:: python + + prj.add_source_file("file.vhd", "lib") + + """ + return self.library(library_name).add_source_file( + file_name=file_name, + preprocessors=preprocessors, + include_dirs=include_dirs, + defines=defines, + vhdl_standard=vhdl_standard, + no_parse=no_parse, + file_type=file_type, + ) + + def _preprocess(self, library_name, file_name, preprocessors): + """ + Preprocess file_name within library_name using explicit preprocessors + if preprocessors is None then use implicit globally defined processors + """ + # @TODO dependency checking etc... + + if preprocessors is None: + preprocessors = [self._location_preprocessor, self._check_preprocessor] + preprocessors = [p for p in preprocessors if p is not None] + preprocessors = self._external_preprocessors + preprocessors + + if not preprocessors: + return file_name + + try: + code = ostools.read_file(file_name, encoding=HDL_FILE_ENCODING) + for preprocessor in preprocessors: + code = preprocessor.run(code, basename(file_name)) + except KeyboardInterrupt: + raise KeyboardInterrupt + except: # pylint: disable=bare-except + traceback.print_exc() + LOGGER.error("Failed to preprocess %s", file_name) + return file_name + else: + pp_file_name = join( + self._preprocessed_path, library_name, basename(file_name) + ) + + idx = 1 + while ostools.file_exists(pp_file_name): + LOGGER.debug( + "Preprocessed file exists '%s', adding prefix", pp_file_name + ) + pp_file_name = join( + self._preprocessed_path, + library_name, + "%i_%s" % (idx, basename(file_name)), + ) + idx += 1 + + ostools.write_file(pp_file_name, code, encoding=HDL_FILE_ENCODING) + return pp_file_name + + def add_preprocessor(self, preprocessor): + """ + Add a custom preprocessor to be used on all files, must be called before adding any files + """ + self._external_preprocessors.append(preprocessor) + + def enable_location_preprocessing( + self, additional_subprograms=None, exclude_subprograms=None + ): + """ + Inserts file name and line number information into VUnit check and log subprograms calls. Custom + subprograms can also be added. Must be called before adding any files. + + :param additional_subprograms: List of custom subprograms to add the line_num and file_name parameters to. + :param exclude_subprograms: List of VUnit subprograms to exclude from location preprocessing. Used to \ +avoid location preprocessing of other functions sharing name with a VUnit log or check subprogram. + + :example: + + .. code-block:: python + + prj.enable_location_preprocessing(additional_subprograms=['my_check'], + exclude_subprograms=['log']) + + """ + preprocessor = LocationPreprocessor() + if additional_subprograms is not None: + for subprogram in additional_subprograms: + preprocessor.add_subprogram(subprogram) + + if exclude_subprograms is not None: + for subprogram in exclude_subprograms: + preprocessor.remove_subprogram(subprogram) + self._location_preprocessor = preprocessor + + def enable_check_preprocessing(self): + """ + Inserts error context information into VUnit check_relation calls + """ + self._check_preprocessor = CheckPreprocessor() + + def main(self, post_run=None): + """ + Run vunit main function and exit + + :param post_run: A callback function which is called after + running tests. The function must accept a single `results` + argument which is an instance of :class:`.Results` + """ + try: + all_ok = self._main(post_run) + except KeyboardInterrupt: + sys.exit(1) + except CompileError: + sys.exit(1) + except SystemExit: + sys.exit(1) + except: # pylint: disable=bare-except + if self._args.dont_catch_exceptions: + raise + traceback.print_exc() + sys.exit(1) + + if (not all_ok) and (not self._args.exit_0): + sys.exit(1) + + sys.exit(0) + + def _create_tests(self, simulator_if): + """ + Create the test cases + """ + self._test_bench_list.warn_when_empty() + test_list = self._test_bench_list.create_tests( + simulator_if, self._args.elaborate + ) + test_list.keep_matches(self._test_filter) + return test_list + + def _main(self, post_run): + """ + Base vunit main function without performing exit + """ + + if self._args.export_json is not None: + return self._main_export_json(self._args.export_json) + + if self._args.list: + return self._main_list_only() + + if self._args.files: + return self._main_list_files_only() + + if self._args.compile: + return self._main_compile_only() + + all_ok = self._main_run(post_run) + return all_ok + + def _create_simulator_if(self): + """ + Create new simulator instance + """ + + if self._simulator_class is None: + LOGGER.error( + "No available simulator detected.\n" + "Simulator binary folder must be available in PATH environment variable.\n" + "Simulator binary folder can also be set the in VUNIT__PATH environment variable.\n" + ) + sys.exit(1) + + if not exists(self._simulator_output_path): + os.makedirs(self._simulator_output_path) + + return self._simulator_class.from_args( + args=self._args, output_path=self._simulator_output_path + ) + + def _main_run(self, post_run): + """ + Main with running tests + """ + simulator_if = self._create_simulator_if() + test_list = self._create_tests(simulator_if) + self._compile(simulator_if) + print() + + start_time = ostools.get_time() + report = TestReport(printer=self._printer) + + try: + self._run_test(test_list, report) + except KeyboardInterrupt: + print() + LOGGER.debug("_main: Caught Ctrl-C shutting down") + finally: + del test_list + + report.set_real_total_time(ostools.get_time() - start_time) + report.print_str() + + if post_run is not None: + post_run(results=Results(simulator_if)) + + del simulator_if + + if self._args.xunit_xml is not None: + xml = report.to_junit_xml_str(self._args.xunit_xml_format) + ostools.write_file(self._args.xunit_xml, xml) + + return report.all_ok() + + def _main_list_only(self): + """ + Main function when only listing test cases + """ + test_list = self._create_tests(simulator_if=None) + for test_name in test_list.test_names: + print(test_name) + print("Listed %i tests" % test_list.num_tests) + return True + + def _main_export_json(self, json_file_name): # pylint: disable=too-many-locals + """ + Main function when exporting to JSON + """ + + file_objects = self.get_compile_order() + files = [] + for source_file in file_objects: + files.append( + dict( + file_name=abspath(source_file.name), + library_name=source_file.library.name, + ) + ) + + tests = [] + for test_suite in self._create_tests(simulator_if=None): + test_information = test_suite.test_information + test_configuration = test_suite.test_configuration + for name in test_suite.test_names: + info = test_information[name] + config = test_configuration[name] + + attributes = {} + for attr in info.attributes: + attributes[attr.name] = attr.value + + attributes.update(config.attributes) + + tests.append( + dict( + name=name, + location=dict( + file_name=info.location.file_name, + offset=info.location.offset, + length=info.location.length, + ), + attributes=attributes, + ) + ) + + json_data = dict( + # The semantic version (https://semver.org/) of the JSON export data format + export_format_version=dict(major=1, minor=0, patch=0), + # The set of files added to the project + files=files, + # The list of all tests + tests=tests, + ) + + with open(json_file_name, "w") as fptr: + json.dump(json_data, fptr, sort_keys=True, indent=4, separators=(",", ": ")) + + return True + + def _main_list_files_only(self): + """ + Main function when only listing files + """ + files = self.get_compile_order() + for source_file in files: + print("%s, %s" % (source_file.library.name, source_file.name)) + print("Listed %i files" % len(files)) + return True + + def _main_compile_only(self): + """ + Main function when only compiling + """ + simulator_if = self._create_simulator_if() + self._compile(simulator_if) + return True + + def _create_output_path(self, clean): + """ + Create or re-create the output path if necessary + """ + if clean: + ostools.renew_path(self._output_path) + elif not exists(self._output_path): + os.makedirs(self._output_path) + + ostools.renew_path(self._preprocessed_path) + + @property + def vhdl_standard(self): + return str(self._vhdl_standard) + + @property + def _preprocessed_path(self): + return join(self._output_path, "preprocessed") + + @property + def codecs_path(self): + return join(self._output_path, "codecs") + + def _compile(self, simulator_if): + """ + Compile entire project + """ + # get test benches + if self._args.minimal: + target_files = self._get_testbench_files(simulator_if) + else: + target_files = None + + simulator_if.compile_project( + self._project, + continue_on_error=self._args.keep_compiling, + printer=self._printer, + target_files=target_files, + ) + + def _get_testbench_files(self, simulator_if): + """ + Return the list of all test bench files for the currently selected tests to run + """ + test_list = self._create_tests(simulator_if) + tb_file_names = {test_suite.file_name for test_suite in test_list} + return [ + self.get_source_file( # pylint: disable=protected-access + file_name + )._source_file + for file_name in tb_file_names + ] + + def _run_test(self, test_cases, report): + """ + Run the test suites and return the report + """ + + if self._args.verbose: + verbosity = TestRunner.VERBOSITY_VERBOSE + elif self._args.quiet: + verbosity = TestRunner.VERBOSITY_QUIET + else: + verbosity = TestRunner.VERBOSITY_NORMAL + + runner = TestRunner( + report, + join(self._output_path, "test_output"), + verbosity=verbosity, + num_threads=self._args.num_threads, + fail_fast=self._args.fail_fast, + dont_catch_exceptions=self._args.dont_catch_exceptions, + no_color=self._args.no_color, + ) + runner.run(test_cases) + + def add_builtins(self, external=None): + """ + Add vunit VHDL builtin libraries + + :param external: struct to select whether to enable external models for 'string' and/or 'integer' vectors. + {'string': , 'integer': }. Allowed values are: None, False/True or + ['path/to/custom/file']. + """ + self._builtins.add_vhdl_builtins(external=external) + + def add_com(self): + """ + Add communication package + """ + self._builtins.add("com") + + def add_array_util(self): + """ + Add array util + """ + self._builtins.add("array_util") + + def add_random(self): + """ + Add random + """ + self._builtins.add("random") + + def add_verification_components(self): + """ + Add verification component library + """ + self._builtins.add("verification_components") + + def add_osvvm(self): + """ + Add osvvm library + """ + self._builtins.add("osvvm") + + def add_json4vhdl(self): + """ + Add JSON-for-VHDL library + """ + self._builtins.add("json4vhdl") + + def get_compile_order(self, source_files=None): + """ + Get the compile order of all or specific source files and + their dependencies. + + A dependency of file **A** in terms of compile order is any + file **B** which **must** be successfully compiled before **A** + can be successfully compiled. + + This is **not** the same as all files required to successfully elaborate **A**. + For example using component instantiation in VHDL there is no + compile order dependency but the component instance will not + elaborate if there is no binding component. + + :param source_files: A list of :class:`.SourceFile` objects or `None` meaing all + :returns: A list of :class:`.SourceFile` objects in compile order. + """ + if source_files is None: + source_files = self.get_source_files(allow_empty=True) + + target_files = [ + source_file._source_file # pylint: disable=protected-access + for source_file in source_files + ] + source_files = self._project.get_dependencies_in_compile_order(target_files) + return SourceFileList( + [ + SourceFile(source_file, self._project, self) + for source_file in source_files + ] + ) + + def get_implementation_subset(self, source_files): + """ + Get the subset of files which are required to successfully + elaborate the list of input files without any missing + dependencies. + + :param source_files: A list of :class:`.SourceFile` objects + :returns: A list of :class:`.SourceFile` objects which is the implementation subset. + """ + target_files = [ + source_file._source_file # pylint: disable=protected-access + for source_file in source_files + ] + source_files = self._project.get_dependencies_in_compile_order( + target_files, implementation_dependencies=True + ) + return SourceFileList( + [ + SourceFile(source_file, self._project, self) + for source_file in source_files + ] + ) diff --git a/vunit/ui/library.py b/vunit/ui/library.py index f48d0554c..3e5d5e374 100644 --- a/vunit/ui/library.py +++ b/vunit/ui/library.py @@ -11,7 +11,7 @@ from os.path import abspath from glob import glob from fnmatch import fnmatch -from ..simulator_interface import is_string_not_iterable +from ..sim_if import is_string_not_iterable from ..source_file import file_type_of, FILE_TYPES, VERILOG_FILE_TYPES from ..builtins import add_verilog_include_dir diff --git a/vunit/ui/vunit.py b/vunit/ui/vunit.py deleted file mode 100644 index 3859ef2fb..000000000 --- a/vunit/ui/vunit.py +++ /dev/null @@ -1,1043 +0,0 @@ -# This Source Code Form is subject to the terms of the Mozilla Public -# License, v. 2.0. If a copy of the MPL was not distributed with this file, -# You can obtain one at http://mozilla.org/MPL/2.0/. -# -# Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com - -# pylint: disable=too-many-lines - -""" -UI class VUnit -""" - -from __future__ import print_function - -import csv -import sys -import traceback -import logging -import json -import os -from os.path import exists, abspath, join, basename, normpath, dirname -from fnmatch import fnmatch -from ..database import PickledDataBase, DataBase -from .. import ostools -from ..vunit_cli import VUnitCLI -from ..simulator_factory import SIMULATOR_FACTORY -from ..simulator_interface import SimulatorInterface -from ..color_printer import COLOR_PRINTER, NO_COLOR_PRINTER - -from ..project import Project -from ..test_runner import TestRunner -from ..test_report import TestReport -from ..test_bench_list import TestBenchList -from ..exceptions import CompileError -from ..location_preprocessor import LocationPreprocessor -from ..check_preprocessor import CheckPreprocessor -from ..parsing.encodings import HDL_FILE_ENCODING -from ..builtins import Builtins -from ..vhdl_standard import VHDL - -from .common import LOGGER, select_vhdl_standard, check_not_empty -from .source import SourceFile, SourceFileList -from .test import Test # pylint: disable=unused-import -from .testbench import TestBench # pylint: disable=unused-import -from .packagefacade import PackageFacade # pylint: disable=unused-import -from .library import Library -from .results import Results - - -class VUnit( # pylint: disable=too-many-instance-attributes, too-many-public-methods - object -): - """ - The public interface of VUnit - - :example: - - .. code-block:: python - - from vunit import VUnit - """ - - @classmethod - def from_argv(cls, argv=None, compile_builtins=True, vhdl_standard=None): - """ - Create VUnit instance from command line arguments. - - :param argv: Use explicit argv instead of actual command line argument - :param compile_builtins: Do not compile builtins. Used for VUnit internal testing. - :param vhdl_standard: The VHDL standard used to compile files, - if None the VUNIT_VHDL_STANDARD environment variable is used - :returns: A :class:`.VUnit` object instance - - :example: - - .. code-block:: python - - from vunit import VUnit - prj = VUnit.from_argv() - - """ - args = VUnitCLI().parse_args(argv=argv) - return cls.from_args( - args, compile_builtins=compile_builtins, vhdl_standard=vhdl_standard - ) - - @classmethod - def from_args(cls, args, compile_builtins=True, vhdl_standard=None): - """ - Create VUnit instance from args namespace. - Intended for users who adds custom command line options. - See :class:`vunit.vunit_cli.VUnitCLI` class to learn about - adding custom command line options. - - :param args: The parsed argument namespace object - :param compile_builtins: Do not compile builtins. Used for VUnit internal testing. - :param vhdl_standard: The VHDL standard used to compile files, - if None the VUNIT_VHDL_STANDARD environment variable is used - :returns: A :class:`.VUnit` object instance - - """ - return cls(args, compile_builtins=compile_builtins, vhdl_standard=vhdl_standard) - - def __init__(self, args, compile_builtins=True, vhdl_standard=None): - self._args = args - self._configure_logging(args.log_level) - self._output_path = abspath(args.output_path) - - if args.no_color: - self._printer = NO_COLOR_PRINTER - else: - self._printer = COLOR_PRINTER - - def test_filter(name, attribute_names): - keep = any(fnmatch(name, pattern) for pattern in args.test_patterns) - - if args.with_attributes is not None: - keep = keep and set(args.with_attributes).issubset(attribute_names) - - if args.without_attributes is not None: - keep = keep and set(args.without_attributes).isdisjoint(attribute_names) - return keep - - self._test_filter = test_filter - self._vhdl_standard = select_vhdl_standard(vhdl_standard) - - self._external_preprocessors = [] - self._location_preprocessor = None - self._check_preprocessor = None - - self._simulator_class = SIMULATOR_FACTORY.select_simulator() - - # Use default simulator options if no simulator was present - if self._simulator_class is None: - simulator_class = SimulatorInterface - self._simulator_output_path = join(self._output_path, "none") - else: - simulator_class = self._simulator_class - self._simulator_output_path = join(self._output_path, simulator_class.name) - - self._create_output_path(args.clean) - - database = self._create_database() - self._project = Project( - database=database, - depend_on_package_body=simulator_class.package_users_depend_on_bodies, - ) - - self._test_bench_list = TestBenchList(database=database) - - self._builtins = Builtins(self, self._vhdl_standard, simulator_class) - if compile_builtins: - self.add_builtins() - - def _create_database(self): - """ - Create a persistent database to store expensive parse results - - Check for Python version used to create the database is the - same as the running python instance or re-create - """ - project_database_file_name = join(self._output_path, "project_database") - create_new = False - key = b"version" - version = str((9, sys.version)).encode() - database = None - try: - database = DataBase(project_database_file_name) - create_new = (key not in database) or (database[key] != version) - except KeyboardInterrupt: - raise KeyboardInterrupt - except: # pylint: disable=bare-except - traceback.print_exc() - create_new = True - - if create_new: - database = DataBase(project_database_file_name, new=True) - database[key] = version - - return PickledDataBase(database) - - @staticmethod - def _configure_logging(log_level): - """ - Configure logging based on log_level string - """ - level = getattr(logging, log_level.upper()) - logging.basicConfig( - filename=None, format="%(levelname)7s - %(message)s", level=level - ) - - def _which_vhdl_standard(self, vhdl_standard): - """ - Return default vhdl_standard if the argument is None - The argument is a string from the user - """ - if vhdl_standard is None: - return self._vhdl_standard - - return VHDL.standard(vhdl_standard) - - def add_external_library(self, library_name, path, vhdl_standard=None): - """ - Add an externally compiled library as a black-box - - :param library_name: The name of the external library - :param path: The path to the external library directory - :param vhdl_standard: The VHDL standard used to compile files, - if None the VUNIT_VHDL_STANDARD environment variable is used - :returns: The created :class:`.Library` object - - :example: - - .. code-block:: python - - prj.add_external_library("unisim", "path/to/unisim/") - - """ - - self._project.add_library( - library_name, - abspath(path), - self._which_vhdl_standard(vhdl_standard), - is_external=True, - ) - return self.library(library_name) - - def add_source_files_from_csv(self, project_csv_path, vhdl_standard=None): - """ - Add a project configuration, mapping all the libraries and files - - :param project_csv_path: path to csv project specification, each line contains the name - of the library and the path to one file 'lib_name,filename' - note that all filenames are relative to the parent folder of the - csv file - :param vhdl_standard: The VHDL standard used to compile files, - if None, the VUNIT_VHDL_STANDARD environment variable is used - :returns: A list of files (:class `.SourceFileList`) that were added - - """ - libs = set() - files = SourceFileList(list()) - - with open(project_csv_path) as csv_path_file: - for row in csv.reader(csv_path_file): - if len(row) == 2: - lib_name = row[0].strip() - no_normalized_file = row[1].strip() - file_name_ = normpath( - join(dirname(project_csv_path), no_normalized_file) - ) - lib = ( - self.library(lib_name) - if lib_name in libs - else self.add_library(lib_name) - ) - libs.add(lib_name) - file_ = lib.add_source_file(file_name_, vhdl_standard=vhdl_standard) - files.append(file_) - elif len(row) > 2: - LOGGER.error( - "More than one library and one file in csv description" - ) - return files - - def add_library(self, library_name, vhdl_standard=None, allow_duplicate=False): - """ - Add a library managed by VUnit. - - :param library_name: The name of the library - :param vhdl_standard: The VHDL standard used to compile files, - if None the VUNIT_VHDL_STANDARD environment variable is used - :param allow_duplicate: Set to True to allow the same library - to be added multiple times. Subsequent additions will just - return the previously created library. - :returns: The created :class:`.Library` object - - :example: - - .. code-block:: python - - library = prj.add_library("lib") - - """ - vhdl_standard = self._which_vhdl_standard(vhdl_standard) - - path = join(self._simulator_output_path, "libraries", library_name) - if not self._project.has_library(library_name): - self._project.add_library(library_name, abspath(path), vhdl_standard) - elif not allow_duplicate: - raise ValueError( - "Library %s already added. Use allow_duplicate to ignore this error." - % library_name - ) - return self.library(library_name) - - def library(self, library_name): - """ - Get a library - - :param library_name: The name of the library - :returns: A :class:`.Library` object - """ - if not self._project.has_library(library_name): - raise KeyError(library_name) - return Library(library_name, self, self._project, self._test_bench_list) - - def set_attribute(self, name, value, allow_empty=False): - """ - Set a value of attribute in all |configurations| - - :param name: The name of the attribute - :param value: The value of the attribute - :param allow_empty: To disable an error when no test benches were found - - :example: - - .. code-block:: python - - prj.set_attribute(".foo", "bar") - - .. note:: - Only affects test benches added *before* the attribute is set. - """ - test_benches = self._test_bench_list.get_test_benches() - for test_bench in check_not_empty( - test_benches, allow_empty, "No test benches found" - ): - test_bench.set_attribute(name, value) - - def set_generic(self, name, value, allow_empty=False): - """ - Set a value of generic in all |configurations| - - :param name: The name of the generic - :param value: The value of the generic - :param allow_empty: To disable an error when no test benches were found - - :example: - - .. code-block:: python - - prj.set_generic("data_width", 16) - - .. note:: - Only affects test benches added *before* the generic is set. - """ - test_benches = self._test_bench_list.get_test_benches() - for test_bench in check_not_empty( - test_benches, allow_empty, "No test benches found" - ): - test_bench.set_generic(name.lower(), value) - - def set_parameter(self, name, value, allow_empty=False): - """ - Set value of parameter in all |configurations| - - :param name: The name of the parameter - :param value: The value of the parameter - :param allow_empty: To disable an error when no test benches were found - - :example: - - .. code-block:: python - - prj.set_parameter("data_width", 16) - - .. note:: - Only affects test benches added *before* the parameter is set. - """ - test_benches = self._test_bench_list.get_test_benches() - for test_bench in check_not_empty( - test_benches, allow_empty, "No test benches found" - ): - test_bench.set_generic(name, value) - - def set_sim_option(self, name, value, allow_empty=False, overwrite=True): - """ - Set simulation option in all |configurations| - - :param name: |simulation_options| - :param value: The value of the simulation option - :param allow_empty: To disable an error when no test benches were found - :param overwrite: To overwrite the option or append to the existing value - - :example: - - .. code-block:: python - - prj.set_sim_option("ghdl.flags", ["--no-vital-checks"]) - - .. note:: - Only affects test benches added *before* the option is set. - """ - test_benches = self._test_bench_list.get_test_benches() - for test_bench in check_not_empty( - test_benches, allow_empty, "No test benches found" - ): - test_bench.set_sim_option(name, value, overwrite) - - def set_compile_option(self, name, value, allow_empty=False): - """ - Set compile option of all files - - :param name: |compile_option| - :param value: The value of the compile option - :param allow_empty: To disable an error when no source files were found - - :example: - - .. code-block:: python - - prj.set_compile_option("ghdl.flags", ["--no-vital-checks"]) - - - .. note:: - Only affects files added *before* the option is set. - """ - source_files = self._project.get_source_files_in_order() - for source_file in check_not_empty( - source_files, allow_empty, "No source files found" - ): - source_file.set_compile_option(name, value) - - def add_compile_option(self, name, value, allow_empty=False): - """ - Add compile option to all files - - :param name: |compile_option| - :param value: The value of the compile option - :param allow_empty: To disable an error when no source files were found - - .. note:: - Only affects files added *before* the option is set. - """ - source_files = self._project.get_source_files_in_order() - for source_file in check_not_empty( - source_files, allow_empty, "No source files found" - ): - source_file.add_compile_option(name, value) - - def get_source_file(self, file_name, library_name=None): - """ - Get a source file - - :param file_name: The name of the file as a relative or absolute path - :param library_name: The name of a specific library to search if not all libraries - :returns: A :class:`.SourceFile` object - """ - - files = self.get_source_files(file_name, library_name, allow_empty=True) - if len(files) > 1: - raise ValueError( - "Found file named '%s' in multiple-libraries, " - "add explicit library_name." % file_name - ) - if not files: - if library_name is None: - raise ValueError("Found no file named '%s'" % file_name) - - raise ValueError( - "Found no file named '%s' in library '%s'" % (file_name, library_name) - ) - return files[0] - - def get_source_files(self, pattern="*", library_name=None, allow_empty=False): - """ - Get a list of source files - - :param pattern: A wildcard pattern matching either an absolute or relative path - :param library_name: The name of a specific library to search if not all libraries - :param allow_empty: To disable an error if no files matched the pattern - :returns: A :class:`.SourceFileList` object - """ - results = [] - for source_file in self._project.get_source_files_in_order(): - if library_name is not None: - if source_file.library.name != library_name: - continue - - if not ( - fnmatch(abspath(source_file.name), pattern) - or fnmatch(ostools.simplify_path(source_file.name), pattern) - ): - continue - - results.append(SourceFile(source_file, self._project, self)) - - check_not_empty( - results, - allow_empty, - ("Pattern %r did not match any file" % pattern) - + ( - ("within library %s" % library_name) if library_name is not None else "" - ), - ) - - return SourceFileList(results) - - def add_source_files( # pylint: disable=too-many-arguments - self, - pattern, - library_name, - preprocessors=None, - include_dirs=None, - defines=None, - allow_empty=False, - vhdl_standard=None, - no_parse=False, - file_type=None, - ): - """ - Add source files matching wildcard pattern to library - - :param pattern: A wildcard pattern matching the files to add or a list of files - :param library_name: The name of the library to add files into - :param include_dirs: A list of include directories - :param defines: A dictionary containing Verilog defines to be set - :param allow_empty: To disable an error if no files matched the pattern - :param vhdl_standard: The VHDL standard used to compile files, - if None VUNIT_VHDL_STANDARD environment variable is used - :param no_parse: Do not parse file(s) for dependency or test scanning purposes - :param file_type: The type of the file; ``"vhdl"``, ``"verilog"`` or ``"systemverilog"``. - Auto-detected by default when set to ``None``. - :returns: A list of files (:class:`.SourceFileList`) which were added - - :example: - - .. code-block:: python - - prj.add_source_files("*.vhd", "lib") - - """ - return self.library(library_name).add_source_files( - pattern=pattern, - preprocessors=preprocessors, - include_dirs=include_dirs, - defines=defines, - allow_empty=allow_empty, - vhdl_standard=vhdl_standard, - no_parse=no_parse, - file_type=file_type, - ) - - def add_source_file( # pylint: disable=too-many-arguments - self, - file_name, - library_name, - preprocessors=None, - include_dirs=None, - defines=None, - vhdl_standard=None, - no_parse=False, - file_type=None, - ): - """ - Add source file to library - - :param file_name: The name of the file - :param library_name: The name of the library to add the file into - :param include_dirs: A list of include directories - :param defines: A dictionary containing Verilog defines to be set - :param vhdl_standard: The VHDL standard used to compile this file, - if None VUNIT_VHDL_STANDARD environment variable is used - :param no_parse: Do not parse file for dependency or test scanning purposes - :param file_type: The type of the file; ``"vhdl"``, ``"verilog"`` or ``"systemverilog"``. - Auto-detected by default when set to ``None``. - :returns: The :class:`.SourceFile` which was added - - :example: - - .. code-block:: python - - prj.add_source_file("file.vhd", "lib") - - """ - return self.library(library_name).add_source_file( - file_name=file_name, - preprocessors=preprocessors, - include_dirs=include_dirs, - defines=defines, - vhdl_standard=vhdl_standard, - no_parse=no_parse, - file_type=file_type, - ) - - def _preprocess(self, library_name, file_name, preprocessors): - """ - Preprocess file_name within library_name using explicit preprocessors - if preprocessors is None then use implicit globally defined processors - """ - # @TODO dependency checking etc... - - if preprocessors is None: - preprocessors = [self._location_preprocessor, self._check_preprocessor] - preprocessors = [p for p in preprocessors if p is not None] - preprocessors = self._external_preprocessors + preprocessors - - if not preprocessors: - return file_name - - try: - code = ostools.read_file(file_name, encoding=HDL_FILE_ENCODING) - for preprocessor in preprocessors: - code = preprocessor.run(code, basename(file_name)) - except KeyboardInterrupt: - raise KeyboardInterrupt - except: # pylint: disable=bare-except - traceback.print_exc() - LOGGER.error("Failed to preprocess %s", file_name) - return file_name - else: - pp_file_name = join( - self._preprocessed_path, library_name, basename(file_name) - ) - - idx = 1 - while ostools.file_exists(pp_file_name): - LOGGER.debug( - "Preprocessed file exists '%s', adding prefix", pp_file_name - ) - pp_file_name = join( - self._preprocessed_path, - library_name, - "%i_%s" % (idx, basename(file_name)), - ) - idx += 1 - - ostools.write_file(pp_file_name, code, encoding=HDL_FILE_ENCODING) - return pp_file_name - - def add_preprocessor(self, preprocessor): - """ - Add a custom preprocessor to be used on all files, must be called before adding any files - """ - self._external_preprocessors.append(preprocessor) - - def enable_location_preprocessing( - self, additional_subprograms=None, exclude_subprograms=None - ): - """ - Inserts file name and line number information into VUnit check and log subprograms calls. Custom - subprograms can also be added. Must be called before adding any files. - - :param additional_subprograms: List of custom subprograms to add the line_num and file_name parameters to. - :param exclude_subprograms: List of VUnit subprograms to exclude from location preprocessing. Used to \ -avoid location preprocessing of other functions sharing name with a VUnit log or check subprogram. - - :example: - - .. code-block:: python - - prj.enable_location_preprocessing(additional_subprograms=['my_check'], - exclude_subprograms=['log']) - - """ - preprocessor = LocationPreprocessor() - if additional_subprograms is not None: - for subprogram in additional_subprograms: - preprocessor.add_subprogram(subprogram) - - if exclude_subprograms is not None: - for subprogram in exclude_subprograms: - preprocessor.remove_subprogram(subprogram) - self._location_preprocessor = preprocessor - - def enable_check_preprocessing(self): - """ - Inserts error context information into VUnit check_relation calls - """ - self._check_preprocessor = CheckPreprocessor() - - def main(self, post_run=None): - """ - Run vunit main function and exit - - :param post_run: A callback function which is called after - running tests. The function must accept a single `results` - argument which is an instance of :class:`.Results` - """ - try: - all_ok = self._main(post_run) - except KeyboardInterrupt: - sys.exit(1) - except CompileError: - sys.exit(1) - except SystemExit: - sys.exit(1) - except: # pylint: disable=bare-except - if self._args.dont_catch_exceptions: - raise - traceback.print_exc() - sys.exit(1) - - if (not all_ok) and (not self._args.exit_0): - sys.exit(1) - - sys.exit(0) - - def _create_tests(self, simulator_if): - """ - Create the test cases - """ - self._test_bench_list.warn_when_empty() - test_list = self._test_bench_list.create_tests( - simulator_if, self._args.elaborate - ) - test_list.keep_matches(self._test_filter) - return test_list - - def _main(self, post_run): - """ - Base vunit main function without performing exit - """ - - if self._args.export_json is not None: - return self._main_export_json(self._args.export_json) - - if self._args.list: - return self._main_list_only() - - if self._args.files: - return self._main_list_files_only() - - if self._args.compile: - return self._main_compile_only() - - all_ok = self._main_run(post_run) - return all_ok - - def _create_simulator_if(self): - """ - Create new simulator instance - """ - - if self._simulator_class is None: - LOGGER.error( - "No available simulator detected.\n" - "Simulator binary folder must be available in PATH environment variable.\n" - "Simulator binary folder can also be set the in VUNIT__PATH environment variable.\n" - ) - sys.exit(1) - - if not exists(self._simulator_output_path): - os.makedirs(self._simulator_output_path) - - return self._simulator_class.from_args( - args=self._args, output_path=self._simulator_output_path - ) - - def _main_run(self, post_run): - """ - Main with running tests - """ - simulator_if = self._create_simulator_if() - test_list = self._create_tests(simulator_if) - self._compile(simulator_if) - print() - - start_time = ostools.get_time() - report = TestReport(printer=self._printer) - - try: - self._run_test(test_list, report) - except KeyboardInterrupt: - print() - LOGGER.debug("_main: Caught Ctrl-C shutting down") - finally: - del test_list - - report.set_real_total_time(ostools.get_time() - start_time) - report.print_str() - - if post_run is not None: - post_run(results=Results(simulator_if)) - - del simulator_if - - if self._args.xunit_xml is not None: - xml = report.to_junit_xml_str(self._args.xunit_xml_format) - ostools.write_file(self._args.xunit_xml, xml) - - return report.all_ok() - - def _main_list_only(self): - """ - Main function when only listing test cases - """ - test_list = self._create_tests(simulator_if=None) - for test_name in test_list.test_names: - print(test_name) - print("Listed %i tests" % test_list.num_tests) - return True - - def _main_export_json(self, json_file_name): # pylint: disable=too-many-locals - """ - Main function when exporting to JSON - """ - - file_objects = self.get_compile_order() - files = [] - for source_file in file_objects: - files.append( - dict( - file_name=abspath(source_file.name), - library_name=source_file.library.name, - ) - ) - - tests = [] - for test_suite in self._create_tests(simulator_if=None): - test_information = test_suite.test_information - test_configuration = test_suite.test_configuration - for name in test_suite.test_names: - info = test_information[name] - config = test_configuration[name] - - attributes = {} - for attr in info.attributes: - attributes[attr.name] = attr.value - - attributes.update(config.attributes) - - tests.append( - dict( - name=name, - location=dict( - file_name=info.location.file_name, - offset=info.location.offset, - length=info.location.length, - ), - attributes=attributes, - ) - ) - - json_data = dict( - # The semantic version (https://semver.org/) of the JSON export data format - export_format_version=dict(major=1, minor=0, patch=0), - # The set of files added to the project - files=files, - # The list of all tests - tests=tests, - ) - - with open(json_file_name, "w") as fptr: - json.dump(json_data, fptr, sort_keys=True, indent=4, separators=(",", ": ")) - - return True - - def _main_list_files_only(self): - """ - Main function when only listing files - """ - files = self.get_compile_order() - for source_file in files: - print("%s, %s" % (source_file.library.name, source_file.name)) - print("Listed %i files" % len(files)) - return True - - def _main_compile_only(self): - """ - Main function when only compiling - """ - simulator_if = self._create_simulator_if() - self._compile(simulator_if) - return True - - def _create_output_path(self, clean): - """ - Create or re-create the output path if necessary - """ - if clean: - ostools.renew_path(self._output_path) - elif not exists(self._output_path): - os.makedirs(self._output_path) - - ostools.renew_path(self._preprocessed_path) - - @property - def vhdl_standard(self): - return str(self._vhdl_standard) - - @property - def _preprocessed_path(self): - return join(self._output_path, "preprocessed") - - @property - def codecs_path(self): - return join(self._output_path, "codecs") - - def _compile(self, simulator_if): - """ - Compile entire project - """ - # get test benches - if self._args.minimal: - target_files = self._get_testbench_files(simulator_if) - else: - target_files = None - - simulator_if.compile_project( - self._project, - continue_on_error=self._args.keep_compiling, - printer=self._printer, - target_files=target_files, - ) - - def _get_testbench_files(self, simulator_if): - """ - Return the list of all test bench files for the currently selected tests to run - """ - test_list = self._create_tests(simulator_if) - tb_file_names = {test_suite.file_name for test_suite in test_list} - return [ - self.get_source_file( # pylint: disable=protected-access - file_name - )._source_file - for file_name in tb_file_names - ] - - def _run_test(self, test_cases, report): - """ - Run the test suites and return the report - """ - - if self._args.verbose: - verbosity = TestRunner.VERBOSITY_VERBOSE - elif self._args.quiet: - verbosity = TestRunner.VERBOSITY_QUIET - else: - verbosity = TestRunner.VERBOSITY_NORMAL - - runner = TestRunner( - report, - join(self._output_path, "test_output"), - verbosity=verbosity, - num_threads=self._args.num_threads, - fail_fast=self._args.fail_fast, - dont_catch_exceptions=self._args.dont_catch_exceptions, - no_color=self._args.no_color, - ) - runner.run(test_cases) - - def add_builtins(self, external=None): - """ - Add vunit VHDL builtin libraries - - :param external: struct to select whether to enable external models for 'string' and/or 'integer' vectors. - {'string': , 'integer': }. Allowed values are: None, False/True or - ['path/to/custom/file']. - """ - self._builtins.add_vhdl_builtins(external=external) - - def add_com(self): - """ - Add communication package - """ - self._builtins.add("com") - - def add_array_util(self): - """ - Add array util - """ - self._builtins.add("array_util") - - def add_random(self): - """ - Add random - """ - self._builtins.add("random") - - def add_verification_components(self): - """ - Add verification component library - """ - self._builtins.add("verification_components") - - def add_osvvm(self): - """ - Add osvvm library - """ - self._builtins.add("osvvm") - - def add_json4vhdl(self): - """ - Add JSON-for-VHDL library - """ - self._builtins.add("json4vhdl") - - def get_compile_order(self, source_files=None): - """ - Get the compile order of all or specific source files and - their dependencies. - - A dependency of file **A** in terms of compile order is any - file **B** which **must** be successfully compiled before **A** - can be successfully compiled. - - This is **not** the same as all files required to successfully elaborate **A**. - For example using component instantiation in VHDL there is no - compile order dependency but the component instance will not - elaborate if there is no binding component. - - :param source_files: A list of :class:`.SourceFile` objects or `None` meaing all - :returns: A list of :class:`.SourceFile` objects in compile order. - """ - if source_files is None: - source_files = self.get_source_files(allow_empty=True) - - target_files = [ - source_file._source_file # pylint: disable=protected-access - for source_file in source_files - ] - source_files = self._project.get_dependencies_in_compile_order(target_files) - return SourceFileList( - [ - SourceFile(source_file, self._project, self) - for source_file in source_files - ] - ) - - def get_implementation_subset(self, source_files): - """ - Get the subset of files which are required to successfully - elaborate the list of input files without any missing - dependencies. - - :param source_files: A list of :class:`.SourceFile` objects - :returns: A list of :class:`.SourceFile` objects which is the implementation subset. - """ - target_files = [ - source_file._source_file # pylint: disable=protected-access - for source_file in source_files - ] - source_files = self._project.get_dependencies_in_compile_order( - target_files, implementation_dependencies=True - ) - return SourceFileList( - [ - SourceFile(source_file, self._project, self) - for source_file in source_files - ] - ) diff --git a/vunit/verilog.py b/vunit/verilog.py index 088ed5262..c0126361e 100644 --- a/vunit/verilog.py +++ b/vunit/verilog.py @@ -8,7 +8,7 @@ The main public Python interface of VUnit-Verilog. """ -from vunit.ui.vunit import VUnit as VUnitVHDL +from vunit.ui import VUnit as VUnitVHDL class VUnit(VUnitVHDL): diff --git a/vunit/vunit_cli.py b/vunit/vunit_cli.py index 16f8d5df8..f247fca0d 100644 --- a/vunit/vunit_cli.py +++ b/vunit/vunit_cli.py @@ -41,7 +41,7 @@ import argparse from os.path import join, abspath import os -from vunit.simulator_factory import SIMULATOR_FACTORY +from vunit.sim_if.factory import SIMULATOR_FACTORY from vunit.about import version