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why parameter names have to be lower case? #783

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nndurj opened this issue Dec 17, 2021 · 1 comment

nndurj commented Dec 17, 2021

vunit/vunit/ui/__init__.py

Line 380 in f344c8b

test_bench.set_generic(name.lower(), value)

Why parameters have to be lower case? I think its common in systemverilog to have upper case for parameters.

Member

umarcor commented Jan 8, 2022

I think it's because VHDL is not case sensitive. See #77 and 8360eaa.
It might be sensible to revisit that fix taking SV into account.

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