diff --git a/examples/vhdl/axi_dma/run.py b/examples/vhdl/axi_dma/run.py
index eb0b60bb..a03df85a 100644
--- a/examples/vhdl/axi_dma/run.py
+++ b/examples/vhdl/axi_dma/run.py
@@ -19,6 +19,7 @@ via AXI-lite.
 
 from pathlib import Path
 from vunit import VUnit
+import re
 
 VU = VUnit.from_argv()
 VU.add_vhdl_builtins()
@@ -27,6 +28,16 @@ VU.add_verification_components()
 
 SRC_PATH = Path(__file__).parent / "src"
 
-VU.add_library("axi_dma_lib").add_source_files([SRC_PATH / "*.vhd", SRC_PATH / "test" / "*.vhd"])
+lib = VU.add_library("axi_dma_lib")
+lib.add_source_files([SRC_PATH / "*.vhd", SRC_PATH / "test" / "*.vhd"])
+
+def vivado_check(output):
+    if re.search(re.compile("^Failure:", re.MULTILINE), output):
+        return False
+    else:
+        return True
+
+for tb in lib.get_test_benches():
+    tb.set_post_check(vivado_check)
 
 VU.main()
diff --git a/examples/vhdl/axi_dma/src/test/tb_axi_dma.vhd b/examples/vhdl/axi_dma/src/test/tb_axi_dma.vhd
index dc5b6ad9..770ce309 100644
--- a/examples/vhdl/axi_dma/src/test/tb_axi_dma.vhd
+++ b/examples/vhdl/axi_dma/src/test/tb_axi_dma.vhd
@@ -9,7 +9,9 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 library vunit_lib;
-context vunit_lib.vunit_context;
+use vunit_lib.run_pkg.all;
+use vunit_lib.check_pkg.all;
+use vunit_lib.logger_pkg.all;
 context vunit_lib.vc_context;
 
 library osvvm;
@@ -113,7 +115,7 @@ begin
   begin
     test_runner_setup(runner, runner_cfg);
     rnd.InitSeed(rnd'instance_name);
-    show(display_handler, debug);
+    --show(display_handler, debug);
 
     if run("Perform simple transfers") then
       -- Perform transfer that are a multiple of the max_burst_length and