diff --git a/vunit/test/unit/test_ghdl_interface.py b/vunit/test/unit/test_ghdl_interface.py
index 7a817ea6ac..141a624828 100644
--- a/vunit/test/unit/test_ghdl_interface.py
+++ b/vunit/test/unit/test_ghdl_interface.py
@@ -154,6 +154,33 @@ def test_compile_project_extra_flags(self, check_output):  # pylint: disable=no-
             [join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib', '--std=08',
              '-Plib_path', 'custom', 'flags', 'file.vhd'], env=simif.get_env())
 
+    @mock.patch("vunit.simulator_interface.check_output", autospec=True, return_value="")
+    def test_elaborate_e_project(self, check_output):  # pylint: disable=no-self-use
+        simif = GHDLInterface(prefix="prefix", output_path="")
+        write_file("file.vhd", "")
+
+        from vunit.test.unit.test_test_bench import Entity
+        from vunit.configuration import Configuration
+
+        design_unit = Entity('tb_entity', file_name=join("tempdir", "file.vhd"))
+        design_unit.original_file_name = join("tempdir", "other_path", "original_file.vhd")
+        design_unit.generic_names = ["runner_cfg", "tb_path"]
+
+        config = Configuration("name", design_unit, sim_options={"ghdl.elab_e": True})
+        simif._vhdl_standard = "2008"
+        simif._project = Project()
+        simif._project.add_library("lib", "lib_path")
+
+        simif.simulate(
+            output_path="output_path",
+            test_suite_name="test_suite_name",
+            config=config,
+            elaborate_only=True
+        )
+        check_output.assert_called_once_with(
+            [join("prefix", 'ghdl'), '-e', '--std=08', '--work=lib', '--workdir=lib_path',
+             '-Plib_path',  '-o', 'output_path/ghdl/tb_entity-arch', 'tb_entity', 'arch'], env=simif.get_env())
+
     def test_compile_project_verilog_error(self):
         simif = GHDLInterface(prefix="prefix", output_path="")
         write_file("file.v", "")