xtheadmempair: Clarify atomicity for load/store-pair instructions

Load/store-pair instructions raise the question about atomicity
and exception behaviour. The current description does not define
the exact behaviour (and thus makes this an implementation detail).

This patch clarifies, that the instructions don't provide any
atomicity guarantees and that that exceptions may re-execute
the instruction causing duplicated memory transactions.

Signed-off-by: Christoph Müllner <[email protected]>

xtheadmempair/ldd.adoc

@@ -27,6 +27,11 @@ from the address _rs1_ + (zero_extend(_imm2_) << 4).
 
 The encoding of this instruction with equal _rd1_, _rd2_ and _rs1_ is reserved.
 
+Note, that there is no atomicity guarantee for this instruction.
+I.e., an implementation can realize this instruction in form of two
+memory transactions and an exception can be handled in-between, in which
+case the whole instruction will be re-executed.
+
 Operation::
 [source,sail]
 --

xtheadmempair/lwd.adoc

@@ -27,6 +27,11 @@ from the address _rs1_ + (zero_extend(_imm2_) << 3).
 
 The encoding of this instruction with equal _rd1_, _rd2_ and _rs1_ is reserved.
 
+Note, that there is no atomicity guarantee for this instruction.
+I.e., an implementation can realize this instruction in form of two
+memory transactions and an exception can be handled in-between, in which
+case the whole instruction will be re-executed.
+
 Operation::
 [source,sail]
 --

xtheadmempair/lwud.adoc

@@ -27,6 +27,11 @@ from the address _rs1_ + (zero_extend(_imm2_) << 3).
 
 The encoding of this instruction with equal _rd1_, _rd2_ and _rs1_ is reserved.
 
+Note, that there is no atomicity guarantee for this instruction.
+I.e., an implementation can realize this instruction in form of two
+memory transactions and an exception can be handled in-between, in which
+case the whole instruction will be re-executed.
+
 Operation::
 [source,sail]
 --

xtheadmempair/sdd.adoc

@@ -25,6 +25,11 @@ Description::
 This instruction stores two 64-bit values from the two GP registers _rd1_ and _rd2_
 to the address _rs1_ + (zero_extend(_imm2_) << 4).
 
+Note, that there is no atomicity guarantee for this instruction.
+I.e., an implementation can realize this instruction in form of two
+memory transactions and an exception can be handled in-between, in which
+case the whole instruction will be re-executed.
+
 Operation::
 [source,sail]
 --

xtheadmempair/swd.adoc

@@ -25,6 +25,11 @@ Description::
 This instruction loads two 32-bit values into the two GP registers _rd1_ and _rd2_
 from the address _rs1_ + (zero_extend(_imm2_) << 3).
 
+Note, that there is no atomicity guarantee for this instruction.
+I.e., an implementation can realize this instruction in form of two
+memory transactions and an exception can be handled in-between, in which
+case the whole instruction will be re-executed.
+
 Operation::
 [source,sail]
 --