Update for newest rust toolchain and svdtools

Author: G33KatWork

patch/attiny817.yaml

@@ -32,6 +32,21 @@ SLPCTRL:
         STANDBY: [1, "Standby Mode"]
         PDOWN: [2, "Power-down Mode"]
 
+TCB0:
+  _add:
+    # FIXME: no idea how to add a write constraint with range [0x0, 0xFF] to
+    #        added registers to prevent bits() from being marked as unsafe
+    CCMPL:
+      description: Lower Compare or Capture in 8-bit PWM mode
+      addressOffset: 0x0C
+      access: read-write
+      size: 8
+    CCMPH:
+      description: Upper Compare or Capture in 8-bit PWM mode
+      addressOffset: 0x0D
+      access: read-write
+      size: 8
+
 TCD0:
   EVCTRL?:
     CFG:
@@ -100,8 +115,19 @@ CPUINT:
 
 EVSYS:
   # make ASYNCCHx, SYNCCHx, ASYNCUSERx and SYNCUSERx a rust slice
+  _modify:
+    "ASYNCUSER*":
+      description: "Users of asynchronous channels"
+    "SYNCUSER*":
+      description: "Users of synchronous channels"
   _array:
     "ASYNCCH*": {}
     "SYNCCH*": {}
     "ASYNCUSER*": {}
     "SYNCUSER*": {}
+
+"SIGROW":
+  # make a bunch of registers rust slices for easier access
+  _array:
+    "DEVICEID?": {}
+    "SERNUM?": {}

src/ccp.rs

@@ -7,35 +7,35 @@ pub mod attiny817 {
     use crate::generic::{UnlockRegister, Protected};
 
     // Mark the CPU.CCP register with the UnlockRegister trait so that it can be used to unlock the below defined registers
-    impl UnlockRegister for crate::attiny817::cpu::ccp::CCP_SPEC { const PTR: *mut u8 = 0x34 as *mut u8; }
+    impl UnlockRegister for crate::attiny817::cpu::ccp::CcpSpec { const PTR: *mut u8 = 0x34 as *mut u8; }
 
     // Configuration change protected registers in NVMCTRL
-    impl Protected for crate::attiny817::nvmctrl::ctrla::CTRLA_SPEC { const MAGIC: u8 = 0x9D; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
-    impl Protected for crate::attiny817::nvmctrl::ctrlb::CTRLB_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::nvmctrl::ctrla::CtrlaSpec { const MAGIC: u8 = 0x9D; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::nvmctrl::ctrlb::CtrlbSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
 
     // Configuration change protected registers in CLKCTRL
-    impl Protected for crate::attiny817::clkctrl::mclkctrlb::MCLKCTRLB_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
-    impl Protected for crate::attiny817::clkctrl::mclklock::MCLKLOCK_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
-    impl Protected for crate::attiny817::clkctrl::xosc32kctrla::XOSC32KCTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
-    impl Protected for crate::attiny817::clkctrl::mclkctrla::MCLKCTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
-    impl Protected for crate::attiny817::clkctrl::osc20mctrla::OSC20MCTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
-    impl Protected for crate::attiny817::clkctrl::osc20mcaliba::OSC20MCALIBA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
-    impl Protected for crate::attiny817::clkctrl::osc20mcalibb::OSC20MCALIBB_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
-    impl Protected for crate::attiny817::clkctrl::osc32kctrla::OSC32KCTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::clkctrl::mclkctrlb::MclkctrlbSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::mclklock::MclklockSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::xosc32kctrla::Xosc32kctrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::mclkctrla::MclkctrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::osc20mctrla::Osc20mctrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::osc20mcaliba::Osc20mcalibaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::osc20mcalibb::Osc20mcalibbSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::osc32kctrla::Osc32kctrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
 
     // Configuration change protected registers in RSTCTRL
-    impl Protected for crate::attiny817::rstctrl::swrr::SWRR_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::rstctrl::swrr::SwrrSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
 
     // Configuration change protected registers in CPUINT
-    impl Protected for crate::attiny817::cpuint::ctrla::CTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::cpuint::ctrla::CtrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
 
     // Configuration change protected registers in BOD
-    impl Protected for crate::attiny817::bod::ctrla::CTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::bod::ctrla::CtrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
 
     // Configuration change protected registers in WDT
-    impl Protected for crate::attiny817::wdt::ctrla::CTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
-    impl Protected for crate::attiny817::wdt::status::STATUS_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::wdt::ctrla::CtrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::wdt::status::StatusSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
 
     // Configuration change protected registers in TCD0
-    impl Protected for crate::attiny817::tcd0::faultctrl::FAULTCTRL_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::tcd0::faultctrl::FaultctrlSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
 }

src/lib.rs

@@ -1,6 +1,4 @@
 //! This crate contains register definitions for
-#![feature(asm_const)]
-
 #![cfg_attr(feature = "at90usb1286", doc = "**at90usb1286**,")]
 #![cfg_attr(feature = "atmega1280", doc = "**atmega1280**,")]
 #![cfg_attr(feature = "atmega1284p", doc = "**atmega1284p**,")]