diff --git a/bsp/rockchip/common/.ignore_format.yml b/bsp/rockchip/common/.ignore_format.yml new file mode 100644 index 00000000000..1ee81ddd89f --- /dev/null +++ b/bsp/rockchip/common/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- rk_hal diff --git a/bsp/rockchip/common/HalSConscript b/bsp/rockchip/common/HalSConscript new file mode 100644 index 00000000000..c49baa1dbfa --- /dev/null +++ b/bsp/rockchip/common/HalSConscript @@ -0,0 +1,24 @@ +import rtconfig +Import('RTT_ROOT') +Import('SOC') +from building import * + +# get current directory +cwd = GetCurrentDir() +hal_lib = cwd + '/rk_hal/lib' + +# The set of source files associated with this SConscript file. +src = Glob(hal_lib + '/CMSIS/Device/' + SOC + '/Source/*.c') +src += Glob(hal_lib + '/hal/src/*.c') +src += Glob(hal_lib + '/hal/src/*/*.c') +src += Glob(hal_lib + '/bsp/' + SOC + '/*.c') + +#add include path +path = [hal_lib + '/hal/inc', + hal_lib + '/bsp/' + SOC, + hal_lib + '/CMSIS/Device/' + SOC + '/Include', + hal_lib + '/CMSIS/Core/Include'] + +group = DefineGroup(SOC + '_StdPeriph', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/rockchip/common/drivers/Kconfig b/bsp/rockchip/common/drivers/Kconfig new file mode 100644 index 00000000000..a910b1481ad --- /dev/null +++ b/bsp/rockchip/common/drivers/Kconfig @@ -0,0 +1,56 @@ +menu "RT-Thread rockchip common drivers" + +config RT_USING_RESET + bool "Enable reset support" + +config RT_USING_CACHE + bool "Enable cache" + default y + +config RT_USING_UNCACHE_HEAP + bool "Enable uncache heap" + select RT_USING_MEMHEAP + default n + + if RT_USING_UNCACHE_HEAP && ARCH_ARM_CORTEX_M + config RT_UNCACHE_HEAP_ORDER + hex "For MCU uncache heap size(0x0D=16KB, 0x0E=32KB, 0x0F=64KB)" + range 0x0D 0x10 + depends on RT_USING_UNCACHE_HEAP + default 0x0E + help + set uncache heap size, it in tail of sram + Examples: + 0x0D => 16KB + 0x0E => 32KB + 0x0F => 64KB + 0x10 => 128KB + endif + +config RT_USING_LARGE_HEAP + bool "Enable large heap" + select RT_USING_MEMHEAP + default n + + if RT_USING_LARGE_HEAP + config RT_LARGE_MALLOC_THRRESH + int "large heap malloc threshold" + default 512 + depends on RT_USING_LARGE_HEAP + help + the memory will allocate in large heap while the allocated size over this + + config RT_LARGE_HEAP_SIZE + int "large heap size" + default 524288 + depends on RT_USING_LARGE_HEAP + help + the remaining memory must be able to accommodate this heap + + endif + +config RT_USING_PM_RUNTIME + bool "Enable pm runtime" + default n + +endmenu diff --git a/bsp/rockchip/common/drivers/SConscript b/bsp/rockchip/common/drivers/SConscript new file mode 100644 index 00000000000..904f0dc0f05 --- /dev/null +++ b/bsp/rockchip/common/drivers/SConscript @@ -0,0 +1,17 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('CommonDrivers', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + group = group + SConscript(os.path.join(d, 'SConscript')) + +Return('group') diff --git a/bsp/rockchip/common/drivers/drv_cache.c b/bsp/rockchip/common/drivers/drv_cache.c new file mode 100644 index 00000000000..641d76d3dab --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_cache.c @@ -0,0 +1,289 @@ +/** + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_cache.c + * @version V0.1 + * @brief cpu cache interface + * + * Change Logs: + * Date Author Notes + * 2019-04-01 Cliff.Chen first implementation + * + ****************************************************************************** + */ + +/** @addtogroup RKBSP_Driver_Reference + * @{ + */ + +/** @addtogroup Cache + * @{ + */ + +/** @defgroup Cache_How_To_Use How To Use + * @{ + +The Cache driver use to keeping data coherent between cpu and device, it can be used in the following three scenarios: + +- **The cpu want to read the latest data that has been modified by device**: + - The device modify the data; + - The cpu invalidate the data by rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, + addr, size); + - The cpu read the latest data; + +- **The device want to read the latest data that was modified by cpu**: + - The cpu modify the data; + - The device flush the data by rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, addr, size); + - The device read the latest data; + +- **The cpu want to execute two code section on the same memory**: + - Loading the code A in the memory from start address of ADDR; + - Executing the code A; + - Loading the code B in the memory from start address of ADDR; + - Invalidating by rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, ADDR, size); + - Executing the code B + + @} */ + +#include +#include "drv_cache.h" +#include "hal_base.h" + +#if defined(ARCH_ARM_CORTEX_M) + +#ifdef RT_USING_CMBACKTRACE +#include "cm_backtrace.h" +#endif + +/********************* Private MACRO Definition ******************************/ +/** @defgroup CACHE_Private_Macro Private Macro + * @{ + */ + +/** @} */ // CACHE_Private_Macro + +/********************* Private Structure Definition **************************/ +/** @defgroup CACHE_Private_Structure Private Structure + * @{ + */ + +/** @} */ // CACHE_Private_Structure + +/********************* Private Variable Definition ***************************/ +/** @defgroup CACHE_Private_Variable Private Variable + * @{ + */ + +/** @} */ // CACHE_Private_Variable + +/********************* Private Function Definition ***************************/ +/** @defgroup CACHE_Private_Function Private Function + * @{ + */ + +/** @} */ // CACHE_Private_Function + +/********************* Public Function Definition ****************************/ + +/** @defgroup CACHE_Public_Functions Public Functions + * @{ + */ + +/** + * @brief Enable the icache of cpu. + * @attention The cache will be enabled when board initialization, do not dynamically switch cache + * unless specifically required. + */ +void rt_hw_cpu_icache_enable(void) +{ + HAL_ICACHE_Enable(); +} + +/** + * @brief Disable the icache of cpu. + * @attention The cache will be enabled when board initialization, do not dynamically switch cache + * unless specifically required. + */ +void rt_hw_cpu_icache_disable(void) +{ + HAL_ICACHE_Disable(); +} + +/** + * @brief Get icache status. + * @return 0 + * @attention Not yet implemnted. + */ +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +/** + * @brief Icache maintain operation. + * @param ops: RT_HW_CACHE_INVALIDATE for cache invalidate. + * @param addr: The start address of memory you want maintain. + * @param size: The length of memory you want maintain. + */ +void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ + if (ops & RT_HW_CACHE_INVALIDATE) + { + HAL_ICACHE_InvalidateByRange((uint32_t)addr, size); + } +} + +/** + * @brief Enable the dcache of cpu. + * @attention The cache will be enabled when board initialization, do not dynamically switch cache + * unless specifically required. + */ +void rt_hw_cpu_dcache_enable(void) +{ + HAL_DCACHE_Enable(); +} + +/** + * @brief Disable the dcache of cpu. + * @attention The cache will be enabled when board initialization, do not dynamically switch cache + * unless specifically required. + */ +void rt_hw_cpu_dcache_disable(void) +{ + HAL_DCACHE_Disable(); +} + +/** + * @brief Get dcache status. + * @return 0 + * @attention Not yet implemnted. + */ +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} + +/** + * @brief Dcache maintain operation. + * @param ops: RT_HW_CACHE_INVALIDATE for cache invalidate, + * RT_HW_CACHE_FLUSH for cache clean. + * @param addr: The start address of memory you want maintain. + * @param size: The length of memory you want maintain. + */ +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if ((ops & RT_HW_CACHE_FLUSH) && (ops & RT_HW_CACHE_INVALIDATE)) + { + HAL_DCACHE_CleanInvalidateByRange((uint32_t)addr, size); + } + else if (ops & RT_HW_CACHE_FLUSH) + { + HAL_DCACHE_CleanByRange((uint32_t)addr, size); + } + else if (ops & RT_HW_CACHE_INVALIDATE) + { + HAL_DCACHE_InvalidateByRange((uint32_t)addr, size); + } + else + { + RT_ASSERT(0); + } +} + +/** + * @brief Dump ahb error occur in icache & dcache, it called by cache interrupt. + * @param fault_handler_lr: The value of LR register. + * @param fault_handler_sp: The value of SP register. + */ +void cache_dump_ahb_error(uint32_t fault_handler_lr, uint32_t fault_handler_sp) +{ + uint32_t addr; + + if (HAL_ICACHE_GetInt()) + { + addr = HAL_ICACHE_GetErrAddr(); + rt_kprintf("a ahb bus error occur in icache, addr=%p\n", (void *)addr); + HAL_ICACHE_ClearInt(); + } + + if (HAL_DCACHE_GetInt()) + { + addr = HAL_DCACHE_GetErrAddr(); + rt_kprintf("a ahb bus error occur in dcache, addr=%p\n", (void *)addr); + HAL_DCACHE_ClearInt(); + } + +#ifdef RT_USING_CMBACKTRACE + cm_backtrace_fault(fault_handler_lr, fault_handler_sp); +#endif +} + +extern void CACHE_IRQHandler(void); + +/** + * @brief Enable cache interrupt and register the handler, it called by board initialization. + * @return RT_EOK + */ +int rt_hw_cpu_cache_init(void) +{ +#if defined(ICACHE) || defined(DCACHE) + HAL_ICACHE_EnableInt(); + HAL_DCACHE_EnableInt(); +#if defined(RKMCU_PISCES) || defined(RKMCU_RK2108) + rt_hw_interrupt_install(CACHE_IRQn, (rt_isr_handler_t)CACHE_IRQHandler, RT_NULL, RT_NULL); + rt_hw_interrupt_umask(CACHE_IRQn); +#elif defined(RKMCU_RK2206) + rt_hw_interrupt_install(CACHE0_I_IRQn, (rt_isr_handler_t)CACHE_IRQHandler, RT_NULL, RT_NULL); + rt_hw_interrupt_install(CACHE0_D_IRQn, (rt_isr_handler_t)CACHE_IRQHandler, RT_NULL, RT_NULL); + rt_hw_interrupt_umask(CACHE0_I_IRQn); + rt_hw_interrupt_umask(CACHE0_D_IRQn); +#endif +#endif + return RT_EOK; +} + +/** @} */ // CACHE_Public_Functions + +#else + +RT_WEAK void rt_hw_cpu_icache_enable(void) +{ +} + +RT_WEAK void rt_hw_cpu_icache_disable(void) +{ +} + +RT_WEAK rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +RT_WEAK void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ +} + +RT_WEAK void rt_hw_cpu_dcache_enable(void) +{ +} + +RT_WEAK void rt_hw_cpu_dcache_disable(void) +{ +} + +RT_WEAK rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} + +RT_WEAK void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ +} + +#endif + +/** @} */ // Cache + +/** @} */ // RKBSP_Driver_Reference diff --git a/bsp/rockchip/common/drivers/drv_cache.h b/bsp/rockchip/common/drivers/drv_cache.h new file mode 100644 index 00000000000..bc53d48fadd --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_cache.h @@ -0,0 +1,22 @@ +/** + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_cache.h + * @version V0.1 + * @brief cpu cache interface + * + * Change Logs: + * Date Author Notes + * 2019-04-01 Cliff.Chen first implementation + * + ****************************************************************************** + */ +#ifndef __DRV_CACHE_H__ +#define __DRV_CACHE_H__ + +#include + +int rt_hw_cpu_cache_init(void); +#endif diff --git a/bsp/rockchip/common/drivers/drv_cache_arm.s b/bsp/rockchip/common/drivers/drv_cache_arm.s new file mode 100644 index 00000000000..50aed1ae072 --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_cache_arm.s @@ -0,0 +1,36 @@ +/** + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_cache_arm.s + * @version V0.1 + * @brief cpu cache interface + * + * Change Logs: + * Date Author Notes + * 2019-04-01 Cliff.Chen first implementation + * + ****************************************************************************** + */ + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT cache_dump_ahb_error + EXPORT CACHE_IRQHandler + +CACHE_IRQHandler PROC + MRS r2, PRIMASK + CPSID I + MOV r0, lr ; get lr + MOV r1, sp ; get stack pointer (current is MSP) + BL cm_backtrace_fault + +Fault_Loop + BL Fault_Loop ;while(1) + ENDP + + END diff --git a/bsp/rockchip/common/drivers/drv_cache_gcc.S b/bsp/rockchip/common/drivers/drv_cache_gcc.S new file mode 100644 index 00000000000..32b07f3d25e --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_cache_gcc.S @@ -0,0 +1,33 @@ +/** + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_cache_gcc.S + * @version V0.1 + * @brief cpu cache interface + * + * Change Logs: + * Date Author Notes + * 2019-04-01 Cliff.Chen first implementation + * + ****************************************************************************** + */ + +.cpu cortex-m4 +.syntax unified +.thumb +.text + +.global CACHE_IRQHandler +.type CACHE_IRQHandler, %function +CACHE_IRQHandler: + MRS r2, PRIMASK + CPSID I + MOV r0, lr /* get lr */ + MOV r1, sp /* get stack pointer (current is MSP) */ + BL cache_dump_ahb_error + +Fault_Loop: + BL Fault_Loop /* while(1) */ + diff --git a/bsp/rockchip/common/drivers/drv_cache_iar.s b/bsp/rockchip/common/drivers/drv_cache_iar.s new file mode 100644 index 00000000000..485f68589a8 --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_cache_iar.s @@ -0,0 +1,35 @@ +/** + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_cache_iar.s + * @version V0.1 + * @brief cpu cache interface + * + * Change Logs: + * Date Author Notes + * 2019-04-01 Cliff.Chen first implementation + * + ****************************************************************************** + */ + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT cache_dump_ahb_error + EXPORT CACHE_IRQHandler + +CACHE_IRQHandler: + MRS r2, PRIMASK + CPSID I + MOV r0, lr ; get lr + MOV r1, sp ; get stack pointer (current is MSP) + BL cm_backtrace_fault + +Fault_Loop + BL Fault_Loop ;while(1) + + END diff --git a/bsp/rockchip/common/drivers/drv_clock.c b/bsp/rockchip/common/drivers/drv_clock.c new file mode 100644 index 00000000000..a6cf98700a5 --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_clock.c @@ -0,0 +1,491 @@ +/** + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_clock.c + * @version V0.1 + * @brief cru clock interface + * + * Change Logs: + * Date Author Notes + * 2019-07-11 Elaine.Zhang first implementation + * + ****************************************************************************** + */ + +/** @addtogroup RKBSP_Driver_Reference +* @{ +*/ + +/** @addtogroup Clock + * @{ + */ + +/** @defgroup Clock_How_To_Use How To Use + * @{ + +The Clock driver use to configure clock frequency, enable/disable clock output, clock reset, power on/off power domain, + it can be used in the following three scenarios: + +- **Configure clock frequency**: + - The device set clock rate by clk_set_rate(eCLOCK_Name clk_id, uint32_t rate); + - The device get clock rate by clk_get_rate(eCLOCK_Name clk_id); + +- **Enable/disable clock output**: + - The device get clock by get_clk_gate_from_id(int clk_id); + - The device set clock enable/disable by clk_enable(struct clk_gate *gate) or clk_disable(struct clk_gate *gate); + +- **Power on/off power domain**: + - The device get pd by get_pd_from_id(int pd_id); + - The device power on/off pd by pd_power(struct pd *power, int on); + + @} */ + +#include +#include + +#if defined(RT_USING_CRU) + +#include "hal_base.h" +#include "drv_clock.h" + +static const struct clk_init *g_clk_init = RT_NULL; + +static rt_slist_t clk_gate_list; + +static struct rt_mutex clk_lock; +static struct rt_mutex gate_lock; +#if defined(RT_USING_PMU) +static struct rt_mutex pd_lock; +static rt_slist_t pd_list; +#endif + +/********************* Public Function Definition ****************************/ + +/** @defgroup CLOCK_Public_Functions Public Functions + * @{ + */ + +/** + * @brief clk set enable. + * @param gate: get_clk_gate_from_id. + * @retval -RT_EINVAL: struct gate is invalid argument + * @retval -RT_ERROR: clk enable failed. + */ +rt_err_t clk_enable(struct clk_gate *gate) +{ + rt_err_t error = RT_EOK; + HAL_Status ret; + + if (!gate) + { + return -RT_EINVAL; + } + + rt_mutex_take(&gate_lock, RT_WAITING_FOREVER); + + if (gate->enable_count == 0) + { + ret = HAL_CRU_ClkEnable(gate->gate_id); + if (ret != HAL_OK) + error = -RT_ERROR; + } + gate->enable_count++; + + rt_mutex_release(&gate_lock); + + return error; +} + +/** + * @brief clk set disable. + * @param gate: get_clk_gate_from_id. + * @retval -RT_EINVAL: struct gate is invalid argument + * @retval -RT_ERROR: clk disable failed. + */ +rt_err_t clk_disable(struct clk_gate *gate) +{ + rt_err_t error = RT_EOK; + HAL_Status ret; + + if (!gate) + { + return -RT_EINVAL; + } + + rt_mutex_take(&gate_lock, RT_WAITING_FOREVER); + + if (gate->enable_count == 0) + { + rt_kprintf("It may be wrong to used, make enable first.(gate_id = %d)\n", __func__, gate->gate_id); + goto out; + } + + if (--gate->enable_count > 0) + { + goto out; + } + ret = HAL_CRU_ClkDisable(gate->gate_id); + if (ret != HAL_OK) + error = -RT_ERROR; + +out: + rt_mutex_release(&gate_lock); + + return error; +} + +/** + * @brief clk is enabled. + * @param gate: get_clk_gate_from_id. + * @retval 0: clk is disabled + * @retval 1: clk is enabled + */ +int clk_is_enabled(struct clk_gate *gate) +{ + if (!gate) + { + return 0; + } + + return HAL_CRU_ClkIsEnabled(gate->gate_id); +} + +/** + * @brief get clk gate by id. + * @param gate_id: clk gate id. + * @return struct of type clk_gate + */ +struct clk_gate *get_clk_gate_from_id(int gate_id) +{ + struct clk_gate *clk_gate; + + rt_mutex_take(&gate_lock, RT_WAITING_FOREVER); + + rt_slist_for_each_entry(clk_gate, &clk_gate_list, node) + { + if (clk_gate->gate_id == gate_id) + { + goto out; + } + } + + clk_gate = rt_calloc(1, sizeof(struct clk_gate)); + clk_gate->gate_id = gate_id; + clk_gate->enable_count = 0; + rt_slist_insert(&clk_gate_list, &clk_gate->node); + +out: + clk_gate->ref_count++; + rt_mutex_release(&gate_lock); + + return clk_gate; +} + +/** + * @brief put clk gate. + * @param gate: get_clk_gate_from_id. + */ +void put_clk_gate(struct clk_gate *gate) +{ + if (!gate) + return; + + rt_mutex_take(&gate_lock, RT_WAITING_FOREVER); + + if (--gate->ref_count > 0) + { + goto out; + } + rt_slist_remove(&clk_gate_list, &gate->node); + rt_free(gate); + +out: + rt_mutex_release(&gate_lock); +} + +/** + * @brief clk get rate. + * @param clk_id: clk id. + * @return the return value of HAL_CRU_ClkGetFreq, which returns the frequency value in unit hz. + */ +uint32_t clk_get_rate(eCLOCK_Name clk_id) +{ + uint32_t rate; + + rt_mutex_take(&clk_lock, RT_WAITING_FOREVER); + + rate = HAL_CRU_ClkGetFreq(clk_id); + + rt_mutex_release(&clk_lock); + + return rate; +} + +/** + * @brief clk set rate. + * @param clk_id: clk id. + * @param rate: frequency value hz. + * @retval RT_EOK: clk set successful + * @retval HAL_OK: HAL_CRU_ClkSetFreq set frequency successfully + * @retval HAL_ERROR: HAL_CRU_ClkSetFreq set frequency failed + * @retval HAL_INVAL: HAL_CRU_ClkSetFreq set frequency unsupported + */ +rt_err_t clk_set_rate(eCLOCK_Name clk_id, uint32_t rate) +{ + rt_err_t error = RT_EOK; + + if (rate == clk_get_rate(clk_id)) + return error; + + rt_mutex_take(&clk_lock, RT_WAITING_FOREVER); + + error = HAL_CRU_ClkSetFreq(clk_id, rate); + + rt_mutex_release(&clk_lock); + + return error; +} + +#if defined(RT_USING_PMU) + +/** + * @brief pd power on. + * @param power: get_pd_from_id. + * @retval -RT_EINVAL: struct pd is invalid argument + * @retval -RT_ERROR: pd power on failed. + * @retval RT_EOK: pd power on success. + */ +rt_err_t pd_on(struct pd *power) +{ + rt_err_t error = RT_EOK; + HAL_Status ret; + + if (!power) + { + return -RT_EINVAL; + } + + rt_mutex_take(&pd_lock, RT_WAITING_FOREVER); + + if (power->enable_count == 0) + { + ret = HAL_PD_On(power->pd_id); + if (ret != HAL_OK) + error = -RT_ERROR; + } + power->enable_count++; + rt_mutex_release(&pd_lock); + + return error; +} + +/** + * @brief pd power off. + * @param power: get_pd_from_id. + * @retval -RT_EINVAL: struct pd is invalid argument + * @retval -RT_ERROR: pd power off failed. + * @retval RT_EOK: pd power off success. + */ +rt_err_t pd_off(struct pd *power) +{ + rt_err_t error = RT_EOK; + HAL_Status ret; + + if (!power) + { + return -RT_EINVAL; + } + + rt_mutex_take(&pd_lock, RT_WAITING_FOREVER); + + if (--power->enable_count > 0) + { + goto out; + } + ret = HAL_PD_Off(power->pd_id); + if (ret != HAL_OK) + error = -RT_ERROR; + +out: + rt_mutex_release(&pd_lock); + + return error; +} + +/** + * @brief get pd by id. + * @param pd_id: pd id. + * @return struct of type pd + */ +struct pd *get_pd_from_id(ePD_Id pd_id) +{ + struct pd *pd; + + if (!pd_id) + return NULL; + + rt_mutex_take(&pd_lock, RT_WAITING_FOREVER); + + rt_slist_for_each_entry(pd, &pd_list, node) + { + if (pd->pd_id == pd_id) + { + goto out; + } + } + pd = rt_calloc(1, sizeof(struct pd)); + pd->pd_id = pd_id; + pd->enable_count = 0; + rt_slist_insert(&pd_list, &pd->node); + +out: + pd->ref_count++; + rt_mutex_release(&pd_lock); + + return pd; +} + +/** + * @brief put pd. + * @param power: get_pd_from_id. + */ +void put_pd(struct pd *power) +{ + if (!power) + return; + + rt_mutex_take(&pd_lock, RT_WAITING_FOREVER); + + if (--power->ref_count > 0) + { + goto out; + } + rt_slist_remove(&pd_list, &power->node); + rt_free(power); + +out: + rt_mutex_release(&pd_lock); +} +#endif + +/** + * @brief clock dev init. + * @return RT_EOK + */ +int clock_dev_init(void) +{ + if (rt_mutex_init(&(clk_lock), "clkLock", RT_IPC_FLAG_FIFO) != RT_EOK) + { + RT_ASSERT(0); + } + if (rt_mutex_init(&(gate_lock), "gateLock", RT_IPC_FLAG_FIFO) != RT_EOK) + { + RT_ASSERT(0); + } + rt_slist_init(&clk_gate_list); +#if defined(RT_USING_PMU) + if (rt_mutex_init(&(pd_lock), "pdLock", RT_IPC_FLAG_FIFO) != RT_EOK) + { + RT_ASSERT(0); + } + rt_slist_init(&pd_list); +#endif + + return RT_EOK; +} +INIT_BOARD_EXPORT(clock_dev_init); + +/** + * @brief clock init frequency. + * @param clk_inits: some need init clks. + * @param clk_dump: if need printf clk get freq after setting. + */ +void clk_init(const struct clk_init *clk_inits, bool clk_dump) +{ + const struct clk_init *clks = clk_inits; + + while (clks->name) + { + if (clks->init_rate) + { + HAL_CRU_ClkSetFreq(clks->clk_id, clks->init_rate); + } + if (clk_dump) + rt_kprintf("%s: %s = %d\n", __func__, clks->name, HAL_CRU_ClkGetFreq(clks->clk_id)); + clks++; + } + g_clk_init = clk_inits; +} + +/** + * @brief clock disable unused. + * @param clks_unused: disable some not needed clks. + */ +void clk_disable_unused(const struct clk_unused *clks_unused) +{ + const struct clk_unused *clks = clks_unused; + + while (clks->gate_val) + { + if (clks->is_pmucru) + { +#if defined(CRU_PMU_CLKGATE_CON0_OFFSET) + CRU->PMU_CLKGATE_CON[clks->gate_con] = clks->gate_val; +#endif + } + else + { + CRU->CRU_CLKGATE_CON[clks->gate_con] = clks->gate_val; + } + clks++; + } +} + +#if defined(RT_USING_CRU_DUMP) + +/** + * @brief clock dump frequency, dump cru registers, used for debug. + */ +static void clk_dump(void) +{ + const struct clk_init *clks = g_clk_init; + int i; + + if (clks) + { + while (clks->name) + { + rt_kprintf("%s: %s[%x] = %d\n", __func__, clks->name, clks->clk_id, + HAL_CRU_ClkGetFreq(clks->clk_id)); + clks++; + } + } + for (i = 0; i < HAL_ARRAY_SIZE(CRU->CRU_CLKSEL_CON); i++) + { + rt_kprintf("%s: cru_sel_con[%d] = %lx\n", __func__, i, CRU->CRU_CLKSEL_CON[i]); + } + for (i = 0; i < HAL_ARRAY_SIZE(CRU->CRU_CLKGATE_CON); i++) + { + rt_kprintf("%s: cru_gate_con[%d] = %lx\n", __func__, i, CRU->CRU_CLKGATE_CON[i]); + } + for (i = 0; i < HAL_ARRAY_SIZE(CRU->CRU_SOFTRST_CON); i++) + { + rt_kprintf("%s: cru_softreset_con[%d] = %lx\n", __func__, i, CRU->CRU_SOFTRST_CON[i]); + } +} + +#ifdef RT_USING_FINSH +#include +MSH_CMD_EXPORT(clk_dump, cru drive test. e.g: clk_dump); +#endif +#endif + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/drivers/drv_clock.h b/bsp/rockchip/common/drivers/drv_clock.h new file mode 100644 index 00000000000..dcb9c25c45a --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_clock.h @@ -0,0 +1,108 @@ +/** + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_clock.h + * @version V0.1 + * @brief clock interface + * + * Change Logs: + * Date Author Notes + * 2019-07-11 Elaine.Zhang first implementation + * + ****************************************************************************** + */ + +#ifndef _DRV_CLOCK_H_ +#define _DRV_CLOCK_H_ + +#include + +#ifdef RT_CONSOLE_DEVICE_NAME +#define RT_CONSOLE_DEVICE_UART(ID) \ + ((strcmp(RT_CONSOLE_DEVICE_NAME, "uart"#ID)) ? 0:1) +#else +#define RT_CONSOLE_DEVICE_UART(ID) 0 +#endif + +#define INIT_CLK(NAME, ID, RATE) \ + { .name = NAME, .clk_id = ID, .init_rate = RATE, } + +struct clk_gate +{ + uint32_t gate_id; + int enable_count; + int ref_count; + rt_slist_t node; +}; + +struct clk_init +{ + const char *name; + uint32_t clk_id; + uint32_t init_rate; +}; + +struct clk_unused +{ + uint32_t is_pmucru : 1; + uint32_t gate_con : 31; + uint32_t gate_val; +}; + +struct pd +{ + uint32_t pd_id; + int enable_count; + int ref_count; + rt_slist_t node; +}; + +/** + * @brief clk set enable by id. + * @param gate_id: gate id. + * @retval RT_EOK: clk set enable success. + * @retval -RT_ERROR: clk set enable failed. + */ +static inline rt_err_t clk_enable_by_id(int gate_id) +{ +#ifdef HAL_CRU_MODULE_ENABLED + return (HAL_CRU_ClkEnable(gate_id) == HAL_OK) ? RT_EOK : -RT_ERROR; +#else + return RT_EOK; +#endif +} + +/** + * @brief clk set disable by id. + * @param gate_id: gate id. + * @retval RT_EOK: clk set disable success. + * @retval -RT_ERROR: clk set disable failed. + */ +static inline rt_err_t clk_disable_by_id(int gate_id) +{ +#ifdef HAL_CRU_MODULE_ENABLED + return (HAL_CRU_ClkDisable(gate_id) == HAL_OK) ? RT_EOK : -RT_ERROR; +#else + return RT_EOK; +#endif +} + +struct clk_gate *get_clk_gate_from_id(int gate_id); +void put_clk_gate(struct clk_gate *gate); +rt_err_t clk_enable(struct clk_gate *gate); +rt_err_t clk_disable(struct clk_gate *gate); +int clk_is_enabled(struct clk_gate *gate); +uint32_t clk_get_rate(eCLOCK_Name clk_id); +rt_err_t clk_set_rate(eCLOCK_Name clk_id, uint32_t rate); +#if defined(RT_USING_PMU) +struct pd *get_pd_from_id(ePD_Id pd_id); +void put_pd(struct pd *power); +rt_err_t pd_on(struct pd *power); +rt_err_t pd_off(struct pd *power); +#endif +void clk_init(const struct clk_init *clk_inits, bool clk_dump); +void clk_disable_unused(const struct clk_unused *clks_unused); + +#endif // _DRV_CLOCK_H_ diff --git a/bsp/rockchip/common/drivers/drv_gpio.c b/bsp/rockchip/common/drivers/drv_gpio.c new file mode 100644 index 00000000000..2fda98765a4 --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_gpio.c @@ -0,0 +1,361 @@ +/** + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_gpio.c + * @author Jay Xu + * @version V0.1 + * @date 2019/5/15 + * @brief GPIO Driver + * + ****************************************************************************** + */ + +/** @addtogroup RKBSP_Driver_Reference + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_How_To_Use How To Use + * @{ + + The GPIO driver use to configure or control GPIO pins on SoCs, it can be used in + the following three scenarios: + +- (A) The GPIO PIN APIs provide by pin component: + - 1) rt_pin_read - get pin level, pin number caculated by BANK_PIN(banknum, pinnum); + - 2) rt_pin_write- set pin level, pin number caculated by BANK_PIN(banknum, pinnum); + - 3) rt_pin_mode - set pin input/output, pin number caculated by BANK_PIN(banknum, pinnum); +- (B) The GPIO IRQ APIs provide by pin component: + - 1) pin_attach_irq; + - 2) pin_detach_irq; + - 3) pin_irq_enable; +- (C) The GPIO PIN NUMBER calculated by BANK_PIN(b,p), such as + BANK_PIN(0, 5) means GPIO0_A5 + BANK_PIN(1, 8) means GPIO1_B0 + + See more information, click [here](http://www.rt-thread.org/document/site/programming-manual/device/pin/pin/) + + @} */ + +#include +#include +#include + +#ifdef RT_USING_PIN + +#include "hal_base.h" +#include "drv_gpio.h" + +/********************* Private MACRO Definition ******************************/ +#define PIN_NUM(p) ((p & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT) +#define PIN_BANK(p) ((p & GPIO_BANK_MASK) >> GPIO_BANK_SHIFT) + +#define BANK_PIN_DEFAULT (-1) + +/********************* Private Structure Definition **************************/ + +static struct GPIO_REG *GPIO_GROUP[] = +{ +#ifdef GPIO0 + GPIO0, +#endif +#ifdef GPIO1 + GPIO1, +#endif +#ifdef GPIO2 + GPIO2, +#endif +#ifdef GPIO3 + GPIO3, +#endif +#ifdef GPIO4 + GPIO4, +#endif +}; + +#define GPIO_BANK_NUM HAL_ARRAY_SIZE(GPIO_GROUP) + +#define get_st_gpio(p) (GPIO_GROUP[PIN_BANK(p)]) +#define get_st_pin(p) (HAL_BIT(PIN_NUM(p))) + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[GPIO_BANK_NUM * PIN_NUMBER_PER_BANK]; + +/********************* Private Function Definition ***************************/ +/** @defgroup GPIO_Private_Function Private Function + * @{ + */ + +static rt_err_t pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + + if (pin < 0 || pin >= HAL_ARRAY_SIZE(pin_irq_hdr_tab)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[pin].pin == pin && + pin_irq_hdr_tab[pin].hdr == hdr && + pin_irq_hdr_tab[pin].mode == mode && + pin_irq_hdr_tab[pin].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + + if (pin_irq_hdr_tab[pin].pin != BANK_PIN_DEFAULT && pin_irq_hdr_tab[pin].hdr != RT_NULL) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + + pin_irq_hdr_tab[pin].pin = pin; + pin_irq_hdr_tab[pin].hdr = hdr; + pin_irq_hdr_tab[pin].mode = mode; + pin_irq_hdr_tab[pin].args = args; + + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + + if (pin < 0 || pin >= HAL_ARRAY_SIZE(pin_irq_hdr_tab)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[pin].pin == BANK_PIN_DEFAULT) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + + pin_irq_hdr_tab[pin].pin = BANK_PIN_DEFAULT; + pin_irq_hdr_tab[pin].hdr = RT_NULL; + pin_irq_hdr_tab[pin].mode = 0; + pin_irq_hdr_tab[pin].args = RT_NULL; + + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t pin_irq_enable(struct rt_device *dev, rt_base_t pin, rt_uint32_t enabled) +{ + rt_base_t level; + eGPIO_intType mode; + + RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM); + + if (enabled == PIN_IRQ_ENABLE) + { + if (pin < 0 || pin >= HAL_ARRAY_SIZE(pin_irq_hdr_tab)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[pin].pin == BANK_PIN_DEFAULT) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + switch (pin_irq_hdr_tab[pin].mode) + { + case PIN_IRQ_MODE_RISING: + mode = GPIO_INT_TYPE_EDGE_RISING; + break; + case PIN_IRQ_MODE_FALLING: + mode = GPIO_INT_TYPE_EDGE_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + mode = GPIO_INT_TYPE_EDGE_BOTH; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + mode = GPIO_INT_TYPE_LEVEL_LOW; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + mode = GPIO_INT_TYPE_LEVEL_HIGH; + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + + HAL_GPIO_SetIntType(get_st_gpio(pin), get_st_pin(pin), mode); + HAL_GPIO_EnableIRQ(get_st_gpio(pin), get_st_pin(pin)); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + HAL_GPIO_DisableIRQ(get_st_gpio(pin), get_st_pin(pin)); + } + else + { + return RT_ENOSYS; + } + + return RT_EOK; +} + +static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) +{ + RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM); + + switch (mode) + { + case PIN_MODE_OUTPUT: + case PIN_MODE_OUTPUT_OD: +#ifdef HAL_PINCTRL_MODULE_ENABLED +#ifdef RK_BSP_TEMP + HAL_PINCTRL_SetIOMUX(PIN_BANK(pin), HAL_BIT(pin), PIN_CONFIG_MUX_FUNC0); +#endif +#endif + HAL_GPIO_SetPinDirection(get_st_gpio(pin), get_st_pin(pin), GPIO_OUT); + break; + + case PIN_MODE_INPUT: + case PIN_MODE_INPUT_PULLUP: + case PIN_MODE_INPUT_PULLDOWN: +#ifdef HAL_PINCTRL_MODULE_ENABLED +#ifdef RK_BSP_TEMP + HAL_PINCTRL_SetIOMUX(PIN_BANK(pin), HAL_BIT(pin), PIN_CONFIG_MUX_FUNC0); +#endif +#endif + HAL_GPIO_SetPinDirection(get_st_gpio(pin), get_st_pin(pin), GPIO_IN); + break; + + default: + break; + } +} + +static void pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) +{ + RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM); + HAL_GPIO_SetPinLevel(get_st_gpio(pin), get_st_pin(pin), value); +} + +static int pin_read(struct rt_device *dev, rt_base_t pin) +{ + RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM); + return HAL_GPIO_GetPinLevel(get_st_gpio(pin), get_st_pin(pin));; +} +/** @} */ + +#ifdef GPIO0 +void pin_gpio0_handler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_IRQHandler(GPIO0, GPIO_BANK0); + rt_interrupt_leave(); +} +#endif +#ifdef GPIO1 +void pin_gpio1_handler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_IRQHandler(GPIO1, GPIO_BANK1); + rt_interrupt_leave(); +} +#endif +#ifdef GPIO2 +void pin_gpio2_handler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_IRQHandler(GPIO2, GPIO_BANK2); + rt_interrupt_leave(); +} +#endif +#ifdef GPIO3 +void pin_gpio3_handler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_IRQHandler(GPIO3, GPIO_BANK3); + rt_interrupt_leave(); +} +#endif +#ifdef GPIO4 +void pin_gpio4_handler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_IRQHandler(GPIO4, GPIO_BANK4); + rt_interrupt_leave(); +} +#endif + +static const struct rt_pin_ops pin_ops = +{ + pin_mode, + pin_write, + pin_read, + pin_attach_irq, + pin_detach_irq, + pin_irq_enable, +}; + +/** @defgroup GPIO_Public_Functions Public Functions + * @{ + */ +int rt_hw_gpio_init(void) +{ +#ifdef GPIO0 + rt_hw_interrupt_install(GPIO0_IRQn, (void *)pin_gpio0_handler, RT_NULL, RT_NULL); + rt_hw_interrupt_umask(GPIO0_IRQn); +#endif +#ifdef GPIO1 + rt_hw_interrupt_install(GPIO1_IRQn, (void *)pin_gpio1_handler, RT_NULL, RT_NULL); + rt_hw_interrupt_umask(GPIO1_IRQn); +#endif +#ifdef GPIO2 + rt_hw_interrupt_install(GPIO2_IRQn, (void *)pin_gpio2_handler, RT_NULL, RT_NULL); + rt_hw_interrupt_umask(GPIO2_IRQn); +#endif +#ifdef GPIO3 + rt_hw_interrupt_install(GPIO3_IRQn, (void *)pin_gpio3_handler, RT_NULL, RT_NULL); + rt_hw_interrupt_umask(GPIO3_IRQn); +#endif +#ifdef GPIO4 + rt_hw_interrupt_install(GPIO4_IRQn, (void *)pin_gpio4_handler, RT_NULL, RT_NULL); + rt_hw_interrupt_umask(GPIO4_IRQn); +#endif + + rt_device_pin_register("pin", &pin_ops, RT_NULL); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_gpio_init); +/** @} */ + +static void pin_irq_hdr(uint32_t pin) +{ + RT_ASSERT(pin >= 0); + RT_ASSERT(pin < HAL_ARRAY_SIZE(pin_irq_hdr_tab)); + RT_ASSERT(pin_irq_hdr_tab[pin].hdr != RT_NULL); + + pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args); +} + +void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin) +{ + RT_ASSERT(bank < GPIO_BANK_NUM); + + pin_irq_hdr(BANK_PIN(bank, pin)); +} + +#endif +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/drivers/drv_gpio.h b/bsp/rockchip/common/drivers/drv_gpio.h new file mode 100644 index 00000000000..17da80e5259 --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_gpio.h @@ -0,0 +1,15 @@ +/** + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-15 Jay first implementation. + * 2019-05-31 Jay optimize driver. + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/rockchip/common/drivers/drv_heap.c b/bsp/rockchip/common/drivers/drv_heap.c new file mode 100644 index 00000000000..4954e8d2a5e --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_heap.c @@ -0,0 +1,318 @@ +/** + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_heap.c + * @version V0.2 + * @brief heap interface + * + * Change Logs: + * Date Author Notes + * 2019-03-26 Cliff.Chen first implementation + * 2019-05-15 Cliff.Chen Add large heap + * + ****************************************************************************** + */ +#include +#include "drv_heap.h" + +#ifdef RT_USING_UNCACHE_HEAP +static struct rt_memheap _uncache_heap; + +rt_err_t rt_uncache_heap_init(void *begin_addr, void *end_addr) +{ + /* initialize a default heap in the system */ + return rt_memheap_init(&_uncache_heap, + "ucheap", + begin_addr, + (rt_uint32_t)end_addr - (rt_uint32_t)begin_addr); +} + +void *rt_malloc_uncache(rt_size_t size) +{ + return rt_memheap_alloc(&_uncache_heap, size); +} + +void rt_free_uncache(void *ptr) +{ + rt_memheap_free(ptr); +} +#endif + +#ifdef RT_USING_LARGE_HEAP +#include "hal_base.h" + +static struct rt_memheap _large_heap; + +rt_err_t rt_large_heap_init(void *begin_addr, void *end_addr) +{ + /* initialize a default heap in the system */ + return rt_memheap_init(&_large_heap, + "large", + begin_addr, + (rt_uint32_t)end_addr - (rt_uint32_t)begin_addr); +} + +void *rt_malloc_large(rt_size_t size) +{ + if (size < RT_LARGE_MALLOC_THRRESH) + return NULL; + + return rt_memheap_alloc(&_large_heap, size); +} +RTM_EXPORT(rt_malloc_large); + +void rt_free_large(void *ptr) +{ + rt_memheap_free(ptr); +} +RTM_EXPORT(rt_free_large); + +void *rt_dma_malloc_large(rt_size_t size) +{ + void *align_ptr; + void *ptr; + rt_size_t align, align_size; + + if (size < RT_LARGE_MALLOC_THRRESH) + return NULL; + + align = 4; + align_size = 0; + +#ifdef CACHE_LINE_SIZE + align = CACHE_LINE_SIZE; +#endif + +#ifdef DMA_ALIGN_SIZE + align = align > DMA_ALIGN_SIZE ? align : DMA_ALIGN_SIZE; +#endif + + align_size = RT_ALIGN(size, align) + align; + ptr = rt_memheap_alloc(&_large_heap, align_size); + if (ptr != RT_NULL) + { + /* the allocated memory block is aligned */ + if (((rt_uint32_t)ptr & (align - 1)) == 0) + { + align_ptr = (void *)((rt_uint32_t)ptr + align); + } + else + { + align_ptr = (void *)(((rt_uint32_t)ptr + (align - 1)) & ~(align - 1)); + } + + /* set the pointer before alignment pointer to the real pointer */ + *((rt_uint32_t *)((rt_uint32_t)align_ptr - sizeof(void *))) = (rt_uint32_t)ptr; + + ptr = align_ptr; + } + + return ptr; +} +RTM_EXPORT(rt_dma_malloc_large); + +void rt_dma_free_large(void *ptr) +{ + void *real_ptr; + + real_ptr = (void *) * (rt_uint32_t *)((rt_uint32_t)ptr - sizeof(void *)); + rt_memheap_free(real_ptr); +} +RTM_EXPORT(rt_dma_free_large); + +#endif + + +#ifdef RT_USING_DTCM_HEAP +#include "hal_base.h" + +static struct rt_memheap _dtcm_heap; +extern int __dtcm_start__, __dtcm_end__; + +#define RK_DTCM_BEGIN (&__dtcm_start__) +#define RK_DTCM_END (&__dtcm_end__) + +int rt_dtcm_heap_init(void) +{ + rt_err_t ret; + rt_device_t dsp; + + dsp = rt_device_find("dsp0"); + RT_ASSERT(dsp != RT_NULL); + + ret = rt_device_open(dsp, RT_DEVICE_FLAG_RDWR); + RT_ASSERT(ret == RT_EOK); + + return rt_memheap_init(&_dtcm_heap, + "dtcmheap", + RK_DTCM_BEGIN, + (rt_uint32_t)RK_DTCM_END - (rt_uint32_t)RK_DTCM_BEGIN); + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_dtcm_heap_init); + +void *rt_malloc_dtcm(rt_size_t size) +{ + //rt_kprintf("rt_malloc_dtcm: size = %d\n", size); + if (size < RT_DTCM_MALLOC_THRRESH) + return NULL; + + return rt_memheap_alloc(&_dtcm_heap, size); +} +RTM_EXPORT(rt_malloc_dtcm); + +void rt_free_dtcm(void *ptr) +{ + rt_memheap_free(ptr); +} +RTM_EXPORT(rt_free_dtcm); + +void *rt_dma_malloc_dtcm(rt_size_t size) +{ + void *align_ptr; + void *ptr; + rt_size_t align, align_size; + + //rt_kprintf("rt_dma_malloc_dtcm: size = %d\n", size); + if (size < RT_DTCM_MALLOC_THRRESH) + return NULL; + + align = 4; + align_size = 0; + +#ifdef CACHE_LINE_SIZE + align = CACHE_LINE_SIZE; +#endif + +#ifdef DMA_ALIGN_SIZE + align = align > DMA_ALIGN_SIZE ? align : DMA_ALIGN_SIZE; +#endif + + align_size = RT_ALIGN(size, align) + align; + ptr = rt_memheap_alloc(&_dtcm_heap, align_size); + if (ptr != RT_NULL) + { + /* the allocated memory block is aligned */ + if (((rt_uint32_t)ptr & (align - 1)) == 0) + { + align_ptr = (void *)((rt_uint32_t)ptr + align); + } + else + { + align_ptr = (void *)(((rt_uint32_t)ptr + (align - 1)) & ~(align - 1)); + } + + /* set the pointer before alignment pointer to the real pointer */ + *((rt_uint32_t *)((rt_uint32_t)align_ptr - sizeof(void *))) = (rt_uint32_t)ptr; + + ptr = align_ptr; + } + + return ptr; +} +RTM_EXPORT(rt_dma_malloc_dtcm); + +void rt_dma_free_dtcm(void *ptr) +{ + void *real_ptr; + + real_ptr = (void *) * (rt_uint32_t *)((rt_uint32_t)ptr - sizeof(void *)); + rt_memheap_free(real_ptr); +} +RTM_EXPORT(rt_dma_free_dtcm); + +#endif + + +#ifdef RT_USING_PSRAM_HEAP +#include "hal_base.h" + +static struct rt_memheap _psram_heap; +extern int __psramheap_start__, __psramheap_end__; + +#define RK_PSRAMHEAP_BEGIN (&__psramheap_start__) +#define RK_PSRAMHEAP_END (&__psramheap_end__) + +int rt_psram_heap_init(void) +{ + return rt_memheap_init(&_psram_heap, + "psramheap", + RK_PSRAMHEAP_BEGIN, + (rt_uint32_t)RK_PSRAMHEAP_END - (rt_uint32_t)RK_PSRAMHEAP_BEGIN); +} +INIT_COMPONENT_EXPORT(rt_psram_heap_init); + +void *rt_malloc_psram(rt_size_t size) +{ + //rt_kprintf("rt_malloc_dtcm: size = %d\n", size); + if (size < RT_PSRAM_MALLOC_THRRESH) + return NULL; + + return rt_memheap_alloc(&_psram_heap, size); +} +RTM_EXPORT(rt_malloc_psram); + +void rt_free_psram(void *ptr) +{ + rt_memheap_free(ptr); +} +RTM_EXPORT(rt_free_psram); + +void *rt_dma_malloc_psram(rt_size_t size) +{ + void *align_ptr; + void *ptr; + rt_size_t align, align_size; + + //rt_kprintf("rt_dma_malloc_dtcm: size = %d\n", size); + if (size < RT_PSRAM_MALLOC_THRRESH) + return NULL; + + align = 4; + align_size = 0; + +#ifdef CACHE_LINE_SIZE + align = CACHE_LINE_SIZE; +#endif + +#ifdef DMA_ALIGN_SIZE + align = align > DMA_ALIGN_SIZE ? align : DMA_ALIGN_SIZE; +#endif + + align_size = RT_ALIGN(size, align) + align; + ptr = rt_memheap_alloc(&_psram_heap, align_size); + if (ptr != RT_NULL) + { + /* the allocated memory block is aligned */ + if (((rt_uint32_t)ptr & (align - 1)) == 0) + { + align_ptr = (void *)((rt_uint32_t)ptr + align); + } + else + { + align_ptr = (void *)(((rt_uint32_t)ptr + (align - 1)) & ~(align - 1)); + } + + /* set the pointer before alignment pointer to the real pointer */ + *((rt_uint32_t *)((rt_uint32_t)align_ptr - sizeof(void *))) = (rt_uint32_t)ptr; + + ptr = align_ptr; + } + + return ptr; +} +RTM_EXPORT(rt_dma_malloc_psram); + +void rt_dma_free_psram(void *ptr) +{ + void *real_ptr; + + real_ptr = (void *) * (rt_uint32_t *)((rt_uint32_t)ptr - sizeof(void *)); + rt_memheap_free(real_ptr); +} +RTM_EXPORT(rt_dma_free_psram); + +#endif diff --git a/bsp/rockchip/common/drivers/drv_heap.h b/bsp/rockchip/common/drivers/drv_heap.h new file mode 100644 index 00000000000..075cee80e3a --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_heap.h @@ -0,0 +1,47 @@ +/** + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_heap.h + * @version V0.1 + * @brief heap interface + * + * Change Logs: + * Date Author Notes + * 2019-03-26 Cliff.Chen first implementation + * + ****************************************************************************** + */ +#ifndef __DRV_HEAP_H +#define __DRV_HEAP_H + +#ifdef RT_USING_UNCACHE_HEAP +rt_err_t rt_uncache_heap_init(void *begin_addr, void *end_addr); +void *rt_malloc_uncache(rt_size_t size); +void rt_free_uncache(void *ptr); +#endif + +#ifdef RT_USING_LARGE_HEAP +rt_err_t rt_large_heap_init(void *begin_addr, void *end_addr); +void *rt_malloc_large(rt_size_t size); +void rt_free_large(void *ptr); +void *rt_dma_malloc_large(rt_size_t size); +void rt_dma_free_large(void *ptr); +#endif + +#ifdef RT_USING_DTCM_HEAP +void *rt_malloc_dtcm(rt_size_t size); +void rt_free_dtcm(void *ptr); +void *rt_dma_malloc_dtcm(rt_size_t size); +void rt_dma_free_dtcm(void *ptr); +#endif + +#ifdef RT_USING_PSRAM_HEAP +void *rt_malloc_psram(rt_size_t size); +void rt_free_psram(void *ptr); +void *rt_dma_malloc_psram(rt_size_t size); +void rt_dma_free_psram(void *ptr); +#endif + +#endif diff --git a/bsp/rockchip/common/drivers/drv_uart.c b/bsp/rockchip/common/drivers/drv_uart.c new file mode 100644 index 00000000000..b3aebe627be --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_uart.c @@ -0,0 +1,575 @@ +/** + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_uart.c + * @author Huibin Hong + * @version V0.5 + * @date 10-Dec-2018 + * @brief serial driver + * + ****************************************************************************** + */ + +#include +#include +#include + +#ifdef RT_USING_UART + +#include "hal_base.h" +#include "hal_bsp.h" +#include "drv_uart.h" +#include "drv_clock.h" +#ifdef RK_BSP_TEMP +#include "drv_pm.h" +#endif +#include "board.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ +struct rockchip_uart +{ + const struct uart_board *uart_board; + /* HAL */ + const struct HAL_UART_DEV *dev; + + /* irq handler */ + rt_isr_handler_t irq_handler; +}; + +static int rockchip_uart_irq(rt_serial_t *serial); + +#define DEFINE_ROCKCHIP_UART(ID) \ +static void rockchip_uart##ID##_irq(int irq, void *param); \ +static struct rt_serial_device serial##ID; \ +static struct rockchip_uart rk_uart##ID = \ +{ \ + .uart_board = &g_uart##ID##_board, \ + .dev = &g_uart##ID##Dev, \ + .irq_handler = rockchip_uart##ID##_irq, \ +}; \ +static void rockchip_uart##ID##_irq(int irq, void *param) \ +{ \ + rockchip_uart_irq(&serial##ID); \ +} \ + +#if defined(RT_USING_UART0) +DEFINE_ROCKCHIP_UART(0); +#endif /* RT_USING_UART0 */ + +#if defined(RT_USING_UART1) +DEFINE_ROCKCHIP_UART(1); +#endif /* RT_USING_UART1 */ + +#if defined(RT_USING_UART2) +DEFINE_ROCKCHIP_UART(2); +#endif /* RT_USING_UART2 */ + +#if defined(RT_USING_UART3) +DEFINE_ROCKCHIP_UART(3); +#endif /* RT_USING_UART3 */ + +#if defined(RT_USING_UART4) +DEFINE_ROCKCHIP_UART(4); +#endif /* RT_USING_UART4 */ + +#if defined(RT_USING_UART5) +DEFINE_ROCKCHIP_UART(5); +#endif /* RT_USING_UART5 */ + +#if defined(RT_USING_UART6) +DEFINE_ROCKCHIP_UART(6); +#endif /* RT_USING_UART6 */ + +#if defined(RT_USING_UART7) +DEFINE_ROCKCHIP_UART(7); +#endif /* RT_USING_UART7 */ + +#if defined(RT_USING_UART8) +DEFINE_ROCKCHIP_UART(8); +#endif /* RT_USING_UART8 */ + +#if defined(RT_USING_UART9) +DEFINE_ROCKCHIP_UART(9); +#endif /* RT_USING_UART9 */ + +static struct rockchip_uart *rk_uart_table[] = +{ +#if defined(RT_USING_UART0) + &rk_uart0, +#endif +#if defined(RT_USING_UART1) + &rk_uart1, +#endif +#if defined(RT_USING_UART2) + &rk_uart2, +#endif +#if defined(RT_USING_UART3) + &rk_uart3, +#endif +#if defined(RT_USING_UART4) + &rk_uart4, +#endif +#if defined(RT_USING_UART5) + &rk_uart5, +#endif +#if defined(RT_USING_UART6) + &rk_uart6, +#endif +#if defined(RT_USING_UART7) + &rk_uart7, +#endif +#if defined(RT_USING_UART8) + &rk_uart8, +#endif +#if defined(RT_USING_UART9) + &rk_uart9, +#endif +}; + +static struct rt_serial_device *rt_serial_table[] = +{ +#if defined(RT_USING_UART0) + &serial0, +#endif +#if defined(RT_USING_UART1) + &serial1, +#endif +#if defined(RT_USING_UART2) + &serial2, +#endif +#if defined(RT_USING_UART3) + &serial3, +#endif +#if defined(RT_USING_UART4) + &serial4, +#endif +#if defined(RT_USING_UART5) + &serial5, +#endif +#if defined(RT_USING_UART6) + &serial6, +#endif +#if defined(RT_USING_UART7) + &serial7, +#endif +#if defined(RT_USING_UART8) + &serial8, +#endif +#if defined(RT_USING_UART9) + &serial9, +#endif +}; + +static int rockchip_uart_putc(rt_serial_t *serial, char c) +{ + struct rockchip_uart *uart = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + uart = (struct rockchip_uart *)serial->parent.user_data; + + HAL_UART_SerialOutChar(uart->dev->pReg, c); + return 1; +} + +static int rockchip_uart_getc(rt_serial_t *serial) +{ + rt_uint8_t c = 0; + int ret = -1; + + struct rockchip_uart *uart = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + uart = (struct rockchip_uart *)serial->parent.user_data; + + ret = HAL_UART_SerialIn(uart->dev->pReg, &c, 1); + + if (ret <= 0) + { + return -1; + } + else + { + ret = c; + return ret; + } +} + +int rt_hw_console_channel(void) +{ +#if defined(RT_CONSOLE_DEVICE_NAME) +#if defined(RT_USING_UART0) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart0")) + return 0; +#endif +#if defined(RT_USING_UART1) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart1")) + return 1; +#endif +#if defined(RT_USING_UART2) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart2")) + return 2; +#endif +#if defined(RT_USING_UART3) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart3")) + return 3; +#endif +#if defined(RT_USING_UART4) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart4")) + return 4; +#endif +#if defined(RT_USING_UART5) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart5")) + return 5; +#endif +#if defined(RT_USING_UART6) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart6")) + return 6; +#endif +#if defined(RT_USING_UART7) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart7")) + return 7; +#endif +#if defined(RT_USING_UART8) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart8")) + return 8; +#endif +#if defined(RT_USING_UART9) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart9")) + return 9; +#endif +#endif + + return -RT_EINVAL; +} + +void rt_hw_console_output(const char *str) +{ + struct rockchip_uart *uart = RT_NULL; + +#if defined(RT_CONSOLE_DEVICE_NAME) +#if defined(RT_USING_UART0) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart0")) + uart = &rk_uart0; +#endif +#if defined(RT_USING_UART1) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart1")) + uart = &rk_uart1; +#endif +#if defined(RT_USING_UART2) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart2")) + uart = &rk_uart2; +#endif +#if defined(RT_USING_UART3) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart3")) + uart = &rk_uart3; +#endif +#if defined(RT_USING_UART4) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart4")) + uart = &rk_uart4; +#endif +#if defined(RT_USING_UART5) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart5")) + uart = &rk_uart5; +#endif +#if defined(RT_USING_UART6) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart6")) + uart = &rk_uart6; +#endif +#if defined(RT_USING_UART7) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart7")) + uart = &rk_uart7; +#endif +#if defined(RT_USING_UART8) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart8")) + uart = &rk_uart8; +#endif +#if defined(RT_USING_UART9) + if (!strcmp(RT_CONSOLE_DEVICE_NAME, "uart9")) + uart = &rk_uart9; +#endif +#endif + + if (!uart) + return; + + while (*str) + { + if (*str == '\n') + HAL_UART_SerialOutChar(uart->dev->pReg, '\r'); + + HAL_UART_SerialOutChar(uart->dev->pReg, *str); + str++; + } +} + +static rt_err_t rockchip_uart_configure(rt_serial_t *serial, struct serial_configure *cfg) +{ + struct rockchip_uart *uart = RT_NULL; + struct HAL_UART_CONFIG hal_uart_config; + const struct HAL_UART_DEV *dev; + + RT_ASSERT(serial != RT_NULL); + uart = (struct rockchip_uart *)serial->parent.user_data; + dev = uart->dev; + + if (cfg->stop_bits == STOP_BITS_1) + hal_uart_config.stopBit = UART_ONE_STOPBIT; + else if (cfg->stop_bits == STOP_BITS_2) + hal_uart_config.stopBit = UART_ONE_AND_HALF_OR_TWO_STOPBIT; + else + rt_kprintf("STOP_BITS_3 and STOP_BITS_4 are not supported\n"); + + if (cfg->parity == PARITY_ODD) + hal_uart_config.parity = UART_ODD_PARITY; + else if (cfg->parity == PARITY_EVEN) + hal_uart_config.parity = UART_EVEN_PARITY; + else + hal_uart_config.parity = UART_PARITY_DISABLE; + + hal_uart_config.baudRate = cfg->baud_rate; + hal_uart_config.dataBit = cfg->data_bits; + + HAL_UART_Init(dev, &hal_uart_config); +#ifdef RK_BSP_TEMP + if (dev->isAutoFlow && (cfg->flow_ctrl == RT_SERIAL_AUTO_FLOW_ENABLE)) + HAL_UART_EnableAutoFlowControl(dev->pReg); + else + HAL_UART_DisableAutoFlowControl(dev->pReg); +#endif + rt_hw_interrupt_umask(dev->irqNum); + + return RT_EOK; +} + +static rt_err_t rockchip_uart_control(rt_serial_t *serial, int cmd, void *arg) +{ + struct rockchip_uart *uart = RT_NULL; + struct UART_REG *hw_base = RT_NULL; + const struct HAL_UART_DEV *dev; + rt_uint32_t flag = (rt_uint32_t)arg; + + RT_ASSERT(serial != RT_NULL); + uart = (struct rockchip_uart *)serial->parent.user_data; + hw_base = uart->dev->pReg; + dev = uart->dev; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + if (flag == RT_DEVICE_FLAG_INT_RX) + HAL_UART_DisableIrq(hw_base, UART_IER_RDI); + else if (flag == RT_DEVICE_FLAG_INT_TX) + HAL_UART_DisableIrq(hw_base, UART_IER_THRI); + break; + + case RT_DEVICE_CTRL_SET_INT: + if (flag == RT_DEVICE_FLAG_INT_RX) + HAL_UART_EnableIrq(hw_base, UART_IER_RDI); + else if (flag == RT_DEVICE_FLAG_INT_TX) + HAL_UART_EnableIrq(hw_base, UART_IER_THRI); + break; + case RT_DEVICE_CTRL_CONFIG: + if (flag == RT_DEVICE_FLAG_DMA_RX) + HAL_UART_EnableIrq(hw_base, UART_IER_RDI); + break; +#ifdef RK_BSP_TEMP + case RT_DEVICE_CTRL_HW_OPEN: + clk_enable_by_id(dev->sclkGateID); + break; + case RT_DEVICE_CTRL_HW_CLOSE: + clk_disable_by_id(dev->sclkGateID); + break; +#endif + } + + return RT_EOK; +} + +static int rockchip_uart_irq(rt_serial_t *serial) +{ + rt_uint32_t iir = 0; + struct rockchip_uart *uart = RT_NULL; + struct UART_REG *hw_base = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + uart = (struct rockchip_uart *)serial->parent.user_data; + hw_base = uart->dev->pReg; + + rt_interrupt_enter(); + + iir = HAL_UART_GetIrqID(hw_base); + + switch (iir) + { + case UART_IIR_RDI: + case UART_IIR_RX_TIMEOUT: + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + break; + + case UART_IIR_THRI: + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + break; + + default: + HAL_UART_HandleIrq(hw_base); + break; + } + + rt_interrupt_leave(); + return 0; +} + +static const struct rt_uart_ops rockchip_uart_ops = +{ + rockchip_uart_configure, + rockchip_uart_control, + rockchip_uart_putc, + rockchip_uart_getc, +}; + +#ifdef RT_USING_PM + +static struct UART_SAVE_CONFIG pUartSave; + +static int rockchip_uart_suspend(const struct rt_device *device) +{ + struct rockchip_uart *uart = RT_NULL; + const struct HAL_UART_DEV *dev; + + RT_ASSERT(device != RT_NULL); + uart = (struct rockchip_uart *)device->user_data; + dev = uart->dev; + + rt_hw_interrupt_mask(dev->irqNum); + HAL_UART_Suspend(dev->pReg, &pUartSave); + clk_disable_by_id(dev->pclkGateID); + clk_disable_by_id(dev->sclkGateID); + return RT_EOK; +} + +static void rockchip_uart_resume(const struct rt_device *device) +{ + struct rockchip_uart *uart = RT_NULL; + const struct HAL_UART_DEV *dev; + + RT_ASSERT(device != RT_NULL); + uart = (struct rockchip_uart *)device->user_data; + dev = uart->dev; + + clk_enable_by_id(dev->pclkGateID); + clk_enable_by_id(dev->sclkGateID); + HAL_UART_Reset(dev->pReg); + HAL_UART_Resume(dev->pReg, &pUartSave); + rt_hw_interrupt_umask(dev->irqNum); +} + +static const struct rt_device_pm_ops rockchip_uart_pm_ops = +{ + .suspend = rockchip_uart_suspend, + .resume = rockchip_uart_resume, +}; + +int rockchip_rt_hw_uart_pm_register(void) +{ + int i = 0; + struct rockchip_uart *uart; + struct rt_serial_device *serial; + const struct uart_board *uart_board; + + for (i = 0; i < HAL_ARRAY_SIZE(rk_uart_table); i++) + { + uart = rk_uart_table[i]; + if (uart) + { + rt_bool_t is_console; + uart_board = uart->uart_board; + +#ifdef RT_CONSOLE_DEVICE_NAME + if (!strcmp(RT_CONSOLE_DEVICE_NAME, uart_board->name)) + is_console = true; + else + is_console = false; +#else + is_console = false; +#endif + + serial = rt_serial_table[i]; + serial->ops = &rockchip_uart_ops; +#ifdef RK_BSP_TEMP + if (!is_console && !uart_board->en_irq_wake) + rt_pm_register_device(&serial->parent, &rockchip_uart_pm_ops); +#endif + } + } + + return 0; +} +INIT_PREV_EXPORT(rockchip_rt_hw_uart_pm_register); + +#endif + +void rt_hw_usart_init(void) +{ + int i = 0; + struct rockchip_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + struct rt_serial_device *serial; + const struct HAL_UART_DEV *dev; + const struct uart_board *uart_board; + + for (i = 0; i < HAL_ARRAY_SIZE(rk_uart_table); i++) + { + uart = rk_uart_table[i]; + if (uart) + { + rt_bool_t is_console; /* uart is used for console */ + + dev = uart->dev; + uart_board = uart->uart_board; + + if (uart_board->baud_rate) + { + config.baud_rate = uart_board->baud_rate; + } + +#ifdef RT_CONSOLE_DEVICE_NAME + if (!strcmp(RT_CONSOLE_DEVICE_NAME, uart_board->name)) + { + is_console = true; + } + else + { + is_console = false; + } +#else + is_console = false; +#endif + + config.bufsz = uart_board->bufer_size; + serial = rt_serial_table[i]; + serial->ops = &rockchip_uart_ops; + serial->config = config; + + /* enable uart clk here */ + clk_enable_by_id(dev->pclkGateID); + clk_enable_by_id(dev->sclkGateID); + + if (!is_console) + HAL_UART_Reset(dev->pReg); + + /* register UARTx device */ + rt_hw_serial_register(serial, uart_board->name, + uart_board->dev_flag, (void *)uart); + + /* enable interrupt */ + rt_hw_interrupt_install(dev->irqNum, uart->irq_handler, + RT_NULL, uart_board->name); + rt_hw_interrupt_mask(dev->irqNum); + } + } +} +#endif diff --git a/bsp/rockchip/common/drivers/drv_uart.h b/bsp/rockchip/common/drivers/drv_uart.h new file mode 100644 index 00000000000..e77cbf49eff --- /dev/null +++ b/bsp/rockchip/common/drivers/drv_uart.h @@ -0,0 +1,99 @@ +/** + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file drv_uart.h + * @author Huibin Hong + * @version V0.5 + * @date 10-Dec-2018 + * @brief serial driver + * + ****************************************************************************** + */ + +#ifndef __ARCH_ARM_SRC_ROCKCHIP_RK_SERIAL_H +#define __ARCH_ARM_SRC_ROCKCHIP_RK_SERIAL_H + +/******************************************************************************* + * Included Files + ******************************************************************************/ +#include "hal_def.h" + +/******************************************************************************* + * Pre-processor Definitions + ******************************************************************************/ +#define ROCKCHIP_UART_SUPPORT_FLAG_DEFAULT \ + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX +#define ROCKCHIP_UART_BAUD_RATE_DEFAULT UART_BR_115200 + +/******************************************************************************* + * Public Types + ******************************************************************************/ + +/* uart_board includes information on a board */ +struct uart_board +{ + rt_uint32_t baud_rate; /* for example 115200 */ + rt_uint32_t dev_flag; /* for example RT_DEVICE_FLAG_INT_RX */ + rt_uint32_t bufer_size; /* uart buffer size */ + rt_bool_t en_irq_wake; /* enable uart irq wake up */ + char name[8]; /* device name: /dev/xxxx */ +}; + +/******************************************************************************* + * Public Data + ******************************************************************************/ + +#if defined(RT_USING_UART0) +extern const struct uart_board g_uart0_board; +#endif /* RT_USING_UART0 */ + +#if defined(RT_USING_UART1) +extern const struct uart_board g_uart1_board; +#endif /* RT_USING_UART1 */ + +#if defined(RT_USING_UART2) +extern const struct uart_board g_uart2_board; +#endif /* RT_USING_UART2 */ + +#if defined(RT_USING_UART3) +extern const struct uart_board g_uart3_board; +#endif /* RT_USING_UART3 */ + +#if defined(RT_USING_UART4) +extern const struct uart_board g_uart4_board; +#endif /* RT_USING_UART4 */ + +#if defined(RT_USING_UART5) +extern const struct uart_board g_uart5_board; +#endif /* RT_USING_UART5 */ + +#if defined(RT_USING_UART6) +extern const struct uart_board g_uart6_board; +#endif /* RT_USING_UART6 */ + +#if defined(RT_USING_UART7) +extern const struct uart_board g_uart7_board; +#endif /* RT_USING_UART7 */ + +#if defined(RT_USING_UART8) +extern const struct uart_board g_uart8_board; +#endif /* RT_USING_UART8 */ + +#if defined(RT_USING_UART9) +extern const struct uart_board g_uart9_board; +#endif /* RT_USING_UART9 */ + +/******************************************************************************* + * Inline Functions + ******************************************************************************/ + +/******************************************************************************* + * Public Functions + ******************************************************************************/ + +void rt_hw_usart_init(void); +int rt_hw_console_channel(void); + +#endif /* __ARCH_ARM_SRC_ROCKCHIP_RK_SERIAL_H */ diff --git a/bsp/rockchip/common/drivers/interrupt.c b/bsp/rockchip/common/drivers/interrupt.c new file mode 100644 index 00000000000..7cc798d2de6 --- /dev/null +++ b/bsp/rockchip/common/drivers/interrupt.c @@ -0,0 +1,259 @@ +/** + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file interrupt.c + * @version V0.1 + * @brief interrupt interface for rt-thread + * + * Change Logs: + * Date Author Notes + * 2019-05-08 Cliff.Chen first implementation + * + ****************************************************************************** + */ + +#include +#include "hal_base.h" + +#if defined(ARCH_ARM_CORTEX_M0) || defined(ARCH_ARM_CORTEX_M3) || defined(ARCH_ARM_CORTEX_M4) || defined(ARCH_ARM_CORTEX_M7) + +#if EXT_INTERRUPT + +struct rk_intc +{ + void *intc_base; + rt_isr_handler_t irq_handler; +}; + +static rt_isr_handler_t ext_vector[NUM_EXT_INTERRUPTS]; + +static void intc_irq_dispatch(void *intc, uint32_t offset) +{ + uint32_t i, irq_no; + + for (i = 0; i < NUM_EXT_INTERRUPTS; i++) + { + if (HAL_INTC_GetFinalStatus(intc, i)) + { + irq_no = i + offset * NUM_INT_PER_CONTROLLER; + ext_vector[irq_no](NUM_INTERRUPTS + irq_no, NULL); + } + } +} + +#define DEFINE_RK_INTC_IRQ(ID) \ +static void rk_intc##ID##_irq_dispatch(int irq, void *param); \ +static struct rk_intc rk_intc##ID = \ +{ \ + .intc_base = INTC##ID, \ + .irq_handler = rk_intc##ID##_irq_dispatch, \ +}; \ +static void rk_intc##ID##_irq_dispatch(int irq, void *param) \ +{ \ + intc_irq_dispatch(INTC##ID, ID); \ +} + +#ifdef INTC0 +DEFINE_RK_INTC_IRQ(0); +#endif +#ifdef INTC1 +DEFINE_RK_INTC_IRQ(1); +#endif +#ifdef INTC2 +DEFINE_RK_INTC_IRQ(2); +#endif +#ifdef INTC3 +DEFINE_RK_INTC_IRQ(3); +#endif + +static struct rk_intc *rk_intc_table[] = +{ +#ifdef INTC0 + &rk_intc0, +#endif +#ifdef INTC1 + &rk_intc1, +#endif +#ifdef INTC2 + &rk_intc2, +#endif +#ifdef INTC3 + &rk_intc3, +#endif +}; + +static void rk_intc_init(void) +{ + uint32_t i; + + memset(ext_vector, 0, sizeof(ext_vector)); + for (i = 0; i < HAL_ARRAY_SIZE(rk_intc_table); i++) + { + HAL_NVIC_SetIRQHandler(INTC0_IRQn + i, (NVIC_IRQHandler)rk_intc_table[i]->irq_handler); + HAL_NVIC_EnableIRQ(INTC0_IRQn + i); + HAL_INTC_EnableAllRQ(rk_intc_table[i]->intc_base); + } +} + +static void rk_intc_mask(uint32_t vector) +{ + uint32_t intc, irq; + + if (vector >= TOTAL_INTERRUPTS) + return; + + if (vector < NUM_INTERRUPTS) + HAL_NVIC_DisableIRQ(vector); + else + { + intc = (vector - NUM_INTERRUPTS) / NUM_INT_PER_CONTROLLER; + irq = (vector - NUM_INTERRUPTS) % NUM_INT_PER_CONTROLLER; + if (intc >= HAL_ARRAY_SIZE(rk_intc_table)) + return; + HAL_INTC_MaskIRQ(rk_intc_table[intc]->intc_base, irq); + } +} + +static void rk_intc_unmask(uint32_t vector) +{ + uint32_t intc, irq; + + if (vector >= TOTAL_INTERRUPTS) + return; + + if (vector < NUM_INTERRUPTS) + HAL_NVIC_EnableIRQ(vector); + else + { + intc = (vector - NUM_INTERRUPTS) / NUM_INT_PER_CONTROLLER; + irq = (vector - NUM_INTERRUPTS) % NUM_INT_PER_CONTROLLER; + if (intc >= HAL_ARRAY_SIZE(rk_intc_table)) + return; + HAL_INTC_UnmaskIRQ(rk_intc_table[intc]->intc_base, irq); + } +} + + +#endif /* end of EXT_INTERRUPT */ + +#ifdef RT_USING_PROF_IRQ + +#define IRQ_AVG_COUNT 200 + +struct irq_summry +{ + uint32_t count; + uint32_t start; + uint32_t time_total; + uint32_t time_avg; + uint32_t time_max; +}; + +static struct irq_summry g_irq_prof[TOTAL_INTERRUPTS]; + +static void irq_enter_hook(void) +{ + uint32_t irq; + + irq = __get_IPSR() - 16; + g_irq_prof[irq].count++; + g_irq_prof[irq].start = HAL_TIMER_GetCount(SYS_TIMER); +} + +static void irq_leave_hook(void) +{ + uint32_t time_cur, end, irq; + + irq = __get_IPSR() - 16; + end = HAL_TIMER_GetCount(SYS_TIMER); + if (end < g_irq_prof[irq].start) + end += PLL_INPUT_OSC_RATE; + + time_cur = end - g_irq_prof[irq].start; + g_irq_prof[irq].time_total += time_cur; + g_irq_prof[irq].time_max = + g_irq_prof[irq].time_max > time_cur ? g_irq_prof[irq].time_max : time_cur; + if (g_irq_prof[irq].count > 0 && + g_irq_prof[irq].count % IRQ_AVG_COUNT == 0) + { + g_irq_prof[irq].time_avg = g_irq_prof[irq].time_total / IRQ_AVG_COUNT; + g_irq_prof[irq].time_total = 0; + } +} + +static void dump_irq_summry(int argc, char **argv) +{ + uint32_t i; + + rt_kprintf("IRQ COUNT AVG MAX\n"); + for (i = 0; i < NUM_INTERRUPTS; i++) + { + rt_kprintf("%03d %08d %08d %08d\n", i, g_irq_prof[i].count, + g_irq_prof[i].time_avg, + g_irq_prof[i].time_max); + } +} + +#ifdef RT_USING_FINSH +#include +MSH_CMD_EXPORT(dump_irq_summry, dump irq summry); +#endif + +#endif /* end of RT_USING_PROF_IRQ */ + +void rt_hw_interrupt_init(void) +{ + uint32_t i; + + for (i = 0; i < NUM_INTERRUPTS; i++) + { + HAL_NVIC_SetPriority(i, NVIC_PERIPH_PRIO_DEFAULT, NVIC_PERIPH_SUB_PRIO_DEFAULT); + } + +#if EXT_INTERRUPT + rk_intc_init(); +#endif + +#ifdef RT_USING_PROF_IRQ + rt_interrupt_enter_sethook(irq_enter_hook); + rt_interrupt_leave_sethook(irq_leave_hook); +#endif +} + +void rt_hw_interrupt_mask(int vector) +{ +#if EXT_INTERRUPT + rk_intc_mask(vector); +#else + HAL_NVIC_DisableIRQ(vector); +#endif +} + +void rt_hw_interrupt_umask(int vector) +{ +#if EXT_INTERRUPT + rk_intc_unmask(vector); +#else + HAL_NVIC_EnableIRQ(vector); +#endif +} + +rt_isr_handler_t rt_hw_interrupt_install(int vector, + rt_isr_handler_t handler, + void *param, + const char *name) +{ +#if EXT_INTERRUPT + if (vector < NUM_INTERRUPTS) + HAL_NVIC_SetIRQHandler(vector, (NVIC_IRQHandler)handler); + else + ext_vector[vector - NUM_INTERRUPTS] = handler; +#else + HAL_NVIC_SetIRQHandler(vector, (NVIC_IRQHandler)handler); +#endif + return handler; +} + +#endif /* end of defined(ARCH_ARM_CORTEX_M0) || defined(ARCH_ARM_CORTEX_M3) || defined(ARCH_ARM_CORTEX_M4) || defined(ARCH_ARM_CORTEX_M7) */ diff --git a/bsp/rockchip/common/drivers/io.c b/bsp/rockchip/common/drivers/io.c new file mode 100644 index 00000000000..fbe3e8a2461 --- /dev/null +++ b/bsp/rockchip/common/drivers/io.c @@ -0,0 +1,248 @@ +/** + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + ****************************************************************************** + * @file io.c + * @author + * @version V0.1 + * @date 10-Jun-2019 + * @brief read and write memory + * + ****************************************************************************** + */ + +#include + +#ifdef RT_DEBUG_USING_IO + +#include +#include +#include +#include + +#include "hal_base.h" + +static void usage(void) +{ + rt_kprintf("Raw memory i/o utility - $Revision: 1.5 $\n\n"); + rt_kprintf("io -v -1|2|4 -r|w [-l ] []\n\n"); + rt_kprintf(" -v Verbose, asks for confirmation\n"); + rt_kprintf(" -1|2|4 Sets memory access size in bytes (default byte)\n"); + rt_kprintf(" -l Length in bytes of area to access (defaults to\n"); + rt_kprintf(" one access, or whole file length)\n"); + rt_kprintf(" -r|w Read from or Write to memory (default read)\n"); + rt_kprintf(" The memory address to access\n"); + rt_kprintf(" The value to write (implies -w)\n\n"); + rt_kprintf("Examples:\n"); + rt_kprintf(" io 0x1000 Reads one byte from 0x1000\n"); + rt_kprintf(" io 0x1000 0x12 Writes 0x12 to location 0x1000\n"); + rt_kprintf(" io -2 -l 8 0x1000 Reads 8 words from 0x1000\n\n"); + rt_kprintf("Note access size (-1|2|4) does not apply to file based accesses.\n\n"); +} + +static void +read_memory(unsigned long phys_addr, uint8_t *addr, int len, int iosize) +{ + int i; + + while (len) + { + rt_kprintf("%08lx: ", phys_addr); + i = 0; + while (i < 16 && len) + { + switch (iosize) + { + case 1: + rt_kprintf(" %02x", *(uint8_t *)addr); + break; + case 2: + rt_kprintf(" %04x", *(uint16_t *)addr); + break; + case 4: + rt_kprintf(" %08lx", *(uint32_t *)addr); + break; + } + i += iosize; + addr += iosize; + len -= iosize; + } + phys_addr += 16; + rt_kprintf("\n"); + } +} + +static void +write_memory(uint8_t *addr, int len, int iosize, unsigned long value) +{ + switch (iosize) + { + case 1: + while (len) + { + *(uint8_t *)addr = value; + len -= iosize; + addr += iosize; + } + break; + case 2: + while (len) + { + *(uint16_t *)addr = value; + len -= iosize; + addr += iosize; + } + break; + case 4: + while (len) + { + *(uint32_t *)addr = value; + len -= iosize; + addr += iosize; + } + break; + } +} + +int io_mem(int argc, char **argv) +{ + int req_len = 0, opt; + uint8_t *real_io; + unsigned long req_addr, req_value = 0; + char *endptr; + int memread = 1; + int iosize = 1; + int verbose = 0; + + opterr = 0; + optind = 0; + + if (argc == 1) + { + usage(); + return 0; + } + + while ((opt = getopt(argc, argv, "hv124rwl:f:")) > 0) + { + switch (opt) + { + case 'h': + usage(); + case 'v': + verbose = 1; + break; + case '1': + case '2': + case '4': + iosize = opt - '0'; + break; + case 'r': + memread = 1; + break; + case 'w': + memread = 0; + break; + case 'l': + req_len = strtoul(optarg, &endptr, 0); + if (*endptr) + { + rt_kprintf("Bad value '%s'\n", optarg); + return 0; + } + break; + default: + rt_kprintf("Unknown option: %c\n", opt); + usage(); + } + } + + if (optind == argc) + { + rt_kprintf("No address given\n"); + return 0; + } + req_addr = strtoul(argv[optind], &endptr, 0); + if (*endptr) + { + rt_kprintf("Bad value '%s'\n", argv[optind]); + return 0; + } + optind++; + + if (optind < argc) + memread = 0; + + if (!memread && optind == argc) + { + rt_kprintf("No value given for WRITE\n"); + return 0; + } + if (!memread) + { + req_value = strtoul(argv[optind], &endptr, 0); + if (*endptr) + { + rt_kprintf("Bad value '%s'\n", argv[optind]); + return 0; + } + if ((iosize == 1 && (req_value & 0xffffff00)) || + (iosize == 2 && (req_value & 0xffff0000))) + { + rt_kprintf(" too large\n"); + return 0; + } + optind++; + } + + if (optind < argc) + { + rt_kprintf("Too many arguments '%s'...\n", argv[optind]); + return 0; + } + + if (!req_len) + req_len = iosize; + + if ((iosize == 2 && (req_addr & 1)) || + (iosize == 4 && (req_addr & 3))) + { + rt_kprintf("Badly aligned for access size\n"); + return 0; + } + + if ((iosize == 2 && (req_len & 1)) || + (iosize == 4 && (req_len & 3))) + { + rt_kprintf("Badly aligned for access size\n"); + return 0; + } + + if (!verbose) + /* Nothing */; + else if (memread) + rt_kprintf("Request to memread 0x%x bytes from address 0x%08lx\n" + "\tusing %d byte accesses\n", + req_len, req_addr, iosize); + else + rt_kprintf("Request to write 0x%x bytes to address 0x%08lx\n" + "\tusing %d byte accesses of value 0x%0*lx\n", + req_len, req_addr, iosize, iosize * 2, req_value); + + real_io = (uint8_t *)req_addr; + + if (memread) + read_memory(req_addr, real_io, req_len, iosize); + else + write_memory(real_io, req_len, iosize, req_value); + + return 0; +} + +#ifdef RT_USING_FINSH +#include +MSH_CMD_EXPORT_ALIAS(io_mem, io, memory read or write cmd); +#endif + +#endif /* RT_DEBUG_USING_IO */ diff --git a/bsp/rockchip/common/drivers/reset.c b/bsp/rockchip/common/drivers/reset.c new file mode 100644 index 00000000000..5621f351e86 --- /dev/null +++ b/bsp/rockchip/common/drivers/reset.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-30 Tao Huang The first version + */ + +#include +#include +#include "hal_base.h" +#include "hal_bsp.h" + +#ifdef RT_USING_RESET +void rt_hw_cpu_reset(void) +{ +#ifdef RT_USING_SND_GLB_RST + HAL_CRU_SetGlbSrst(GLB_SRST_SND); +#else + HAL_CRU_SetGlbSrst(GLB_SRST_FST); +#endif + + while (1); +} + +#ifdef RT_USING_FINSH +#include + +static void reboot(uint8_t argc, char **argv) +{ + if (argc >= 2 && !strncmp(argv[1], "loader", 6)) + { + BSP_SetLoaderFlag(); + } + + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, Reboot System); +#endif /* RT_USING_FINSH */ +#endif /* RT_USING_RESET */ diff --git a/bsp/rockchip/common/rk_hal/LAST_COMMIT b/bsp/rockchip/common/rk_hal/LAST_COMMIT new file mode 100644 index 00000000000..09fc68dc9d8 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/LAST_COMMIT @@ -0,0 +1,2 @@ +Last commit: a5b7b9a7b3d5617b3c03dd2d3e0fceebbeb8b0b1 +Last commit date: Tue Dec 7 11:35:11 2021 +0800 by Steven Liu \ No newline at end of file diff --git a/bsp/rockchip/common/rk_hal/LICENSE b/bsp/rockchip/common/rk_hal/LICENSE new file mode 100644 index 00000000000..c9397d67823 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/LICENSE @@ -0,0 +1,27 @@ +Copyright (c) 2020 Rockchip Electronics Co., Ltd. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation +and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cachel1_armv7.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 00000000000..abebc95f946 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_armcc.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 00000000000..a955d471391 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_armclang.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 00000000000..69114177477 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000000..1e255d5907f --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_compiler.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 00000000000..adbf296f15a --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_gcc.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 00000000000..67bda4ef3c3 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_iccarm.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 00000000000..65b824b009c --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_version.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 00000000000..eb9f7ca3b3f --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 5U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_armv81mml.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 00000000000..4a15992fb1f --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,4216 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.1 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_armv8mbl.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 00000000000..932d3d188bf --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_armv8mml.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 00000000000..2bd9e76064d --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,3197 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm0.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 00000000000..6441ff34190 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm0plus.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 00000000000..4e7179a6146 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm1.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 00000000000..76b4569743a --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm23.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 00000000000..55fff995096 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm3.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 00000000000..74fb87e5c56 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm33.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 00000000000..f9cf6ab183a --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3265 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm35p.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 00000000000..552c29464de --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3265 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm4.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 00000000000..e21cd149256 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm55.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 00000000000..51b68e6d8ca --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4277 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.1 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_CM55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; + __IOM uint32_t DPDLPSTATE; +} PwrModCtl_Type; + + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE CLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE RLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk 3UL /*!< PWRMODCTL DPDLPSTATE DLPSTATE Mask */ + +/*@}*/ /* end of group CMSIS_PWRMODCTL */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm7.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 00000000000..010506e9fa4 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_sc000.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 00000000000..dbc755fff39 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_sc300.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 00000000000..d66621031e0 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/mpu_armv7.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 00000000000..d9eedf81a64 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/mpu_armv8.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 00000000000..3de16efc86a --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/pmu_armv8.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/pmu_armv8.h new file mode 100644 index 00000000000..f8f3d8935b8 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/tz_context.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/tz_context.h new file mode 100644 index 00000000000..0d09749f3a5 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/rk2108.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/rk2108.h new file mode 100644 index 00000000000..dd16185f751 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/rk2108.h @@ -0,0 +1,11616 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __RK2108_H +#define __RK2108_H +#ifdef __cplusplus + extern "C" { +#endif +/****************************************************************************************/ +/* */ +/* Module Structure Section */ +/* */ +/****************************************************************************************/ +#ifndef __ASSEMBLY__ +/* ICACHE Register Structure Define */ +struct ICACHE_REG { + __IO uint32_t CACHE_CTRL; /* Address Offset: 0x0000 */ + __IO uint32_t CACHE_MAINTAIN[2]; /* Address Offset: 0x0004 */ + __IO uint32_t STB_TIMEOUT_CTRL; /* Address Offset: 0x000C */ + uint32_t RESERVED0010[4]; /* Address Offset: 0x0010 */ + __IO uint32_t CACHE_INT_EN; /* Address Offset: 0x0020 */ + __IO uint32_t CACHE_INT_ST; /* Address Offset: 0x0024 */ + __IO uint32_t CACHE_ERR_HADDR; /* Address Offset: 0x0028 */ + uint32_t RESERVED002C; /* Address Offset: 0x002C */ + __I uint32_t CACHE_STATUS; /* Address Offset: 0x0030 */ + uint32_t RESERVED0034[3]; /* Address Offset: 0x0034 */ + __I uint32_t PMU_RD_NUM_CNT; /* Address Offset: 0x0040 */ + __I uint32_t PMU_WR_NUM_CNT; /* Address Offset: 0x0044 */ + __I uint32_t PMU_SRAM_RD_HIT_CNT; /* Address Offset: 0x0048 */ + __I uint32_t PMU_HB_RD_HIT_CNT; /* Address Offset: 0x004C */ + __IO uint32_t PMU_STB_RD_HIT_CNT; /* Address Offset: 0x0050 */ + __I uint32_t PMU_RD_HIT_CNT; /* Address Offset: 0x0054 */ + __I uint32_t PMU_WR_HIT_CNT; /* Address Offset: 0x0058 */ + __I uint32_t PMU_RD_MISS_PENALTY_CNT; /* Address Offset: 0x005C */ + __I uint32_t PMU_WR_MISS_PENALTY_CNT; /* Address Offset: 0x0060 */ + __I uint32_t PMU_RD_LAT_CNT; /* Address Offset: 0x0064 */ + __I uint32_t PMU_WR_LAT_CNT; /* Address Offset: 0x0068 */ + uint32_t RESERVED006C[33]; /* Address Offset: 0x006C */ + __IO uint32_t REVISION; /* Address Offset: 0x00F0 */ +}; +/* DCACHE Register Structure Define */ +struct DCACHE_REG { + __IO uint32_t CACHE_CTRL; /* Address Offset: 0x0000 */ + __IO uint32_t CACHE_MAINTAIN[2]; /* Address Offset: 0x0004 */ + __IO uint32_t STB_TIMEOUT_CTRL; /* Address Offset: 0x000C */ + uint32_t RESERVED0010[4]; /* Address Offset: 0x0010 */ + __IO uint32_t CACHE_INT_EN; /* Address Offset: 0x0020 */ + __IO uint32_t CACHE_INT_ST; /* Address Offset: 0x0024 */ + __IO uint32_t CACHE_ERR_HADDR; /* Address Offset: 0x0028 */ + uint32_t RESERVED002C; /* Address Offset: 0x002C */ + __I uint32_t CACHE_STATUS; /* Address Offset: 0x0030 */ + uint32_t RESERVED0034[3]; /* Address Offset: 0x0034 */ + __I uint32_t PMU_RD_NUM_CNT; /* Address Offset: 0x0040 */ + __I uint32_t PMU_WR_NUM_CNT; /* Address Offset: 0x0044 */ + __I uint32_t PMU_SRAM_RD_HIT_CNT; /* Address Offset: 0x0048 */ + __I uint32_t PMU_HB_RD_HIT_CNT; /* Address Offset: 0x004C */ + __IO uint32_t PMU_STB_RD_HIT_CNT; /* Address Offset: 0x0050 */ + __I uint32_t PMU_RD_HIT_CNT; /* Address Offset: 0x0054 */ + __I uint32_t PMU_WR_HIT_CNT; /* Address Offset: 0x0058 */ + __I uint32_t PMU_RD_MISS_PENALTY_CNT; /* Address Offset: 0x005C */ + __I uint32_t PMU_WR_MISS_PENALTY_CNT; /* Address Offset: 0x0060 */ + __I uint32_t PMU_RD_LAT_CNT; /* Address Offset: 0x0064 */ + __I uint32_t PMU_WR_LAT_CNT; /* Address Offset: 0x0068 */ + uint32_t RESERVED006C[33]; /* Address Offset: 0x006C */ + __IO uint32_t REVISION; /* Address Offset: 0x00F0 */ +}; +/* CRU Register Structure Define */ +struct CRU_REG { + __IO uint32_t GPLL_CON[3]; /* Address Offset: 0x0000 */ + uint32_t RESERVED000C[5]; /* Address Offset: 0x000C */ + __IO uint32_t CPLL_CON[5]; /* Address Offset: 0x0020 */ + uint32_t RESERVED0034[3]; /* Address Offset: 0x0034 */ + __IO uint32_t SPLL_CON[4]; /* Address Offset: 0x0040 */ + uint32_t RESERVED0050[4]; /* Address Offset: 0x0050 */ + __IO uint32_t CRU_MODE_CON00; /* Address Offset: 0x0060 */ + uint32_t RESERVED0064[7]; /* Address Offset: 0x0064 */ + __IO uint32_t CRU_CLKSEL_CON[50]; /* Address Offset: 0x0080 */ + uint32_t RESERVED0148[14]; /* Address Offset: 0x0148 */ + __IO uint32_t CRU_CLKGATE_CON[15]; /* Address Offset: 0x0180 */ + uint32_t RESERVED01BC[17]; /* Address Offset: 0x01BC */ + __IO uint32_t CRU_SOFTRST_CON[16]; /* Address Offset: 0x0200 */ + uint32_t RESERVED0240[48]; /* Address Offset: 0x0240 */ + __IO uint32_t GLB_CNT_TH; /* Address Offset: 0x0300 */ + __IO uint32_t CRU_GLBRST_ST; /* Address Offset: 0x0304 */ + __IO uint32_t GLB_SRST_FST_VALUE; /* Address Offset: 0x0308 */ + __IO uint32_t GLB_SRST_SND_VALUE; /* Address Offset: 0x030C */ + __IO uint32_t GLB_RST_CON; /* Address Offset: 0x0310 */ + uint32_t RESERVED0314[3]; /* Address Offset: 0x0314 */ + __IO uint32_t CRU_SDIO_CON[2]; /* Address Offset: 0x0320 */ + uint32_t RESERVED0328[2]; /* Address Offset: 0x0328 */ + __IO uint32_t DCG_CON[2][8]; /* Address Offset: 0x0330 */ + uint32_t RESERVED0370[36]; /* Address Offset: 0x0370 */ + __IO uint32_t AS_CON[5][2]; /* Address Offset: 0x0400 */ +}; +/* GRF Register Structure Define */ +struct GRF_REG { + __IO uint32_t GPIO0A_IOMUX_L; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO0A_IOMUX_H; /* Address Offset: 0x0004 */ + __IO uint32_t GPIO0B_IOMUX_L; /* Address Offset: 0x0008 */ + __IO uint32_t GPIO0B_IOMUX_H; /* Address Offset: 0x000C */ + __IO uint32_t GPIO0C_IOMUX_L; /* Address Offset: 0x0010 */ + __IO uint32_t GPIO0C_IOMUX_H; /* Address Offset: 0x0014 */ + __IO uint32_t GPIO0D_IOMUX_L; /* Address Offset: 0x0018 */ + __IO uint32_t GPIO0D_IOMUX_H; /* Address Offset: 0x001C */ + __IO uint32_t GPIO1A_IOMUX_L; /* Address Offset: 0x0020 */ + __IO uint32_t GPIO1A_IOMUX_H; /* Address Offset: 0x0024 */ + __IO uint32_t GPIO1B_IOMUX_L; /* Address Offset: 0x0028 */ + __IO uint32_t GPIO1B_IOMUX_H; /* Address Offset: 0x002C */ + __IO uint32_t GPIO1C_IOMUX_L; /* Address Offset: 0x0030 */ + __IO uint32_t GPIO1C_IOMUX_H; /* Address Offset: 0x0034 */ + __IO uint32_t GPIO1D_IOMUX_L; /* Address Offset: 0x0038 */ + uint32_t RESERVED003C; /* Address Offset: 0x003C */ + __IO uint32_t GPIO0L_SR; /* Address Offset: 0x0040 */ + __IO uint32_t GPIO0H_SR; /* Address Offset: 0x0044 */ + __IO uint32_t GPIO1L_SR; /* Address Offset: 0x0048 */ + __IO uint32_t GPIO1H_SR; /* Address Offset: 0x004C */ + uint32_t RESERVED0050[12]; /* Address Offset: 0x0050 */ + __IO uint32_t GPIO0A_P; /* Address Offset: 0x0080 */ + __IO uint32_t GPIO0B_P; /* Address Offset: 0x0084 */ + __IO uint32_t GPIO0C_P; /* Address Offset: 0x0088 */ + __IO uint32_t GPIO0D_P; /* Address Offset: 0x008C */ + __IO uint32_t GPIO1A_P; /* Address Offset: 0x0090 */ + __IO uint32_t GPIO1B_P; /* Address Offset: 0x0094 */ + __IO uint32_t GPIO1C_P; /* Address Offset: 0x0098 */ + __IO uint32_t GPIO1D_P; /* Address Offset: 0x009C */ + uint32_t RESERVED00A0[8]; /* Address Offset: 0x00A0 */ + __IO uint32_t GPIO0A_E; /* Address Offset: 0x00C0 */ + __IO uint32_t GPIO0B_E; /* Address Offset: 0x00C4 */ + __IO uint32_t GPIO0C_E; /* Address Offset: 0x00C8 */ + __IO uint32_t GPIO0D_E; /* Address Offset: 0x00CC */ + __IO uint32_t GPIO1A_E; /* Address Offset: 0x00D0 */ + __IO uint32_t GPIO1B_E; /* Address Offset: 0x00D4 */ + __IO uint32_t GPIO1C_E; /* Address Offset: 0x00D8 */ + __IO uint32_t GPIO1D_E; /* Address Offset: 0x00DC */ + uint32_t RESERVED00E0[4]; /* Address Offset: 0x00E0 */ + __I uint32_t CHIP_VERSION_ID; /* Address Offset: 0x00F0 */ + __I uint32_t CHIP_IDL; /* Address Offset: 0x00F4 */ + __I uint32_t CHIP_IDH; /* Address Offset: 0x00F8 */ + uint32_t RESERVED00FC; /* Address Offset: 0x00FC */ + __IO uint32_t SOC_CON0; /* Address Offset: 0x0100 */ + __IO uint32_t SOC_CON1; /* Address Offset: 0x0104 */ + __IO uint32_t SOC_CON2; /* Address Offset: 0x0108 */ + __IO uint32_t SOC_CON3; /* Address Offset: 0x010C */ + __IO uint32_t SOC_CON4; /* Address Offset: 0x0110 */ + __IO uint32_t SOC_CON5; /* Address Offset: 0x0114 */ + uint32_t RESERVED0118[10]; /* Address Offset: 0x0118 */ + __I uint32_t SOC_STATUS0; /* Address Offset: 0x0140 */ + __I uint32_t SOC_STATUS1; /* Address Offset: 0x0144 */ + uint32_t RESERVED0148[6]; /* Address Offset: 0x0148 */ + __IO uint32_t DSP_CON0; /* Address Offset: 0x0160 */ + __IO uint32_t DSP_CON1; /* Address Offset: 0x0164 */ + __IO uint32_t DSP_CON2; /* Address Offset: 0x0168 */ + uint32_t RESERVED016C; /* Address Offset: 0x016C */ + __I uint32_t DSP_STAT0; /* Address Offset: 0x0170 */ + __I uint32_t DSP_STAT1; /* Address Offset: 0x0174 */ + uint32_t RESERVED0178[2]; /* Address Offset: 0x0178 */ + __IO uint32_t PVTM_CON0; /* Address Offset: 0x0180 */ + __IO uint32_t PVTM_CON1; /* Address Offset: 0x0184 */ + uint32_t RESERVED0188[2]; /* Address Offset: 0x0188 */ + __I uint32_t PVTM_STATUS0; /* Address Offset: 0x0190 */ + __I uint32_t PVTM_STATUS1; /* Address Offset: 0x0194 */ + uint32_t RESERVED0198[10]; /* Address Offset: 0x0198 */ + __IO uint32_t FW_CON0; /* Address Offset: 0x01C0 */ + __IO uint32_t FW_CON1; /* Address Offset: 0x01C4 */ + __IO uint32_t FW_CON2; /* Address Offset: 0x01C8 */ + uint32_t RESERVED01CC[13]; /* Address Offset: 0x01CC */ + __IO uint32_t MCU_CON0; /* Address Offset: 0x0200 */ + __IO uint32_t MCU_CON1; /* Address Offset: 0x0204 */ + __IO uint32_t MCU_CON2; /* Address Offset: 0x0208 */ + __IO uint32_t MCU_CON3; /* Address Offset: 0x020C */ + uint32_t RESERVED0210[4]; /* Address Offset: 0x0210 */ + __I uint32_t MCU_STAT0; /* Address Offset: 0x0220 */ + uint32_t RESERVED0224[7]; /* Address Offset: 0x0224 */ + __IO uint32_t DSI_CON0; /* Address Offset: 0x0240 */ + __IO uint32_t DSI_CON1; /* Address Offset: 0x0244 */ + __IO uint32_t DSI_CON2; /* Address Offset: 0x0248 */ + __IO uint32_t DSI_CON3; /* Address Offset: 0x024C */ + __IO uint32_t DSI_CON4; /* Address Offset: 0x0250 */ + __IO uint32_t DSI_CON5; /* Address Offset: 0x0254 */ + __IO uint32_t DSI_CON6; /* Address Offset: 0x0258 */ + __IO uint32_t DSI_CON7; /* Address Offset: 0x025C */ + __IO uint32_t DSI_CON8; /* Address Offset: 0x0260 */ + __IO uint32_t DSI_CON9; /* Address Offset: 0x0264 */ + __IO uint32_t DSI_CON10; /* Address Offset: 0x0268 */ + __IO uint32_t DSI_CON11; /* Address Offset: 0x026C */ + __IO uint32_t DSI_CON12; /* Address Offset: 0x0270 */ + __IO uint32_t DSI_CON13; /* Address Offset: 0x0274 */ + __IO uint32_t DSI_CON14; /* Address Offset: 0x0278 */ + __IO uint32_t DSI_CON15; /* Address Offset: 0x027C */ + __IO uint32_t DSI_CON16; /* Address Offset: 0x0280 */ + __IO uint32_t DSI_CON17; /* Address Offset: 0x0284 */ + __IO uint32_t DSI_CON18; /* Address Offset: 0x0288 */ + __IO uint32_t DSI_CON19; /* Address Offset: 0x028C */ + __IO uint32_t DSI_CON20; /* Address Offset: 0x0290 */ + __IO uint32_t DSI_CON21; /* Address Offset: 0x0294 */ + __IO uint32_t DSI_CON22; /* Address Offset: 0x0298 */ + __IO uint32_t DSI_CON23; /* Address Offset: 0x029C */ + __IO uint32_t DSI_CON24; /* Address Offset: 0x02A0 */ + __IO uint32_t DSI_CON25; /* Address Offset: 0x02A4 */ + __IO uint32_t DSI_CON26; /* Address Offset: 0x02A8 */ + __IO uint32_t DSI_CON27; /* Address Offset: 0x02AC */ + __IO uint32_t DSI_CON28; /* Address Offset: 0x02B0 */ + __IO uint32_t DSI_CON29; /* Address Offset: 0x02B4 */ + uint32_t RESERVED02B8[2]; /* Address Offset: 0x02B8 */ + __I uint32_t DSI_STATUS0; /* Address Offset: 0x02C0 */ + __I uint32_t DSI_STATUS1; /* Address Offset: 0x02C4 */ + __I uint32_t DSI_STATUS2; /* Address Offset: 0x02C8 */ + __I uint32_t DSI_STATUS3; /* Address Offset: 0x02CC */ + __I uint32_t DSI_STATUS4; /* Address Offset: 0x02D0 */ + __I uint32_t DSI_STATUS5; /* Address Offset: 0x02D4 */ + __I uint32_t DSI_STATUS6; /* Address Offset: 0x02D8 */ + __I uint32_t DSI_STATUS7; /* Address Offset: 0x02DC */ + __I uint32_t DSI_STATUS8; /* Address Offset: 0x02E0 */ + uint32_t RESERVED02E4[7]; /* Address Offset: 0x02E4 */ + __IO uint32_t MEM_CON0; /* Address Offset: 0x0300 */ + __IO uint32_t MEM_CON1; /* Address Offset: 0x0304 */ + __IO uint32_t MEM_CON2; /* Address Offset: 0x0308 */ + __IO uint32_t MEM_CON3; /* Address Offset: 0x030C */ + __IO uint32_t MEM_CON4; /* Address Offset: 0x0310 */ + __IO uint32_t MEM_CON5; /* Address Offset: 0x0314 */ + __IO uint32_t MEM_CON6; /* Address Offset: 0x0318 */ + uint32_t RESERVED031C[9]; /* Address Offset: 0x031C */ + __IO uint32_t USBPHY_CON0; /* Address Offset: 0x0340 */ + __IO uint32_t USBPHY_CON1; /* Address Offset: 0x0344 */ + __IO uint32_t USBPHY_CON2; /* Address Offset: 0x0348 */ + __IO uint32_t USBPHY_CON3; /* Address Offset: 0x034C */ + __IO uint32_t USBPHY_CON4; /* Address Offset: 0x0350 */ + __IO uint32_t USBPHY_CON5; /* Address Offset: 0x0354 */ + __IO uint32_t USBPHY_CON6; /* Address Offset: 0x0358 */ + __IO uint32_t USBPHY_CON7; /* Address Offset: 0x035C */ + __IO uint32_t USBPHY_CON8; /* Address Offset: 0x0360 */ + uint32_t RESERVED0364[3]; /* Address Offset: 0x0364 */ + __I uint32_t USBPHY_STATUS0; /* Address Offset: 0x0370 */ + __IO uint32_t USBPHY_STATUS1; /* Address Offset: 0x0374 */ + uint32_t RESERVED0378[5]; /* Address Offset: 0x0378 */ + __IO uint32_t DMAC_CON3; /* Address Offset: 0x038C */ + __IO uint32_t DMAC_CON4; /* Address Offset: 0x0390 */ + __IO uint32_t DMAC_CON5; /* Address Offset: 0x0394 */ + __IO uint32_t DMAC_CON6; /* Address Offset: 0x0398 */ + uint32_t RESERVED039C[9]; /* Address Offset: 0x039C */ + __IO uint32_t FAST_BOOT_EN; /* Address Offset: 0x03C0 */ + __IO uint32_t FAST_BOOT_ADDR; /* Address Offset: 0x03C4 */ + uint32_t RESERVED03C8[14]; /* Address Offset: 0x03C8 */ + __IO uint32_t OS_REG0; /* Address Offset: 0x0400 */ + __IO uint32_t OS_REG1; /* Address Offset: 0x0404 */ + __IO uint32_t OS_REG2; /* Address Offset: 0x0408 */ + __IO uint32_t OS_REG3; /* Address Offset: 0x040C */ + __IO uint32_t OS_REG4; /* Address Offset: 0x0410 */ + __IO uint32_t OS_REG5; /* Address Offset: 0x0414 */ + __IO uint32_t OS_REG6; /* Address Offset: 0x0418 */ + __IO uint32_t OS_REG7; /* Address Offset: 0x041C */ + uint32_t RESERVED0420[696]; /* Address Offset: 0x0420 */ + __I uint32_t CHIP_ID; /* Address Offset: 0x0F00 */ +}; +/* MBOX Register Structure Define */ +struct MBOX_CMD_DAT { + __IO uint32_t CMD; + __IO uint32_t DATA; +}; +struct MBOX_REG { + __IO uint32_t A2B_INTEN; /* Address Offset: 0x0000 */ + __IO uint32_t A2B_STATUS; /* Address Offset: 0x0004 */ + struct MBOX_CMD_DAT A2B[4]; /* Address Offset: 0x0008 */ + __IO uint32_t B2A_INTEN; /* Address Offset: 0x0028 */ + __IO uint32_t B2A_STATUS; /* Address Offset: 0x002C */ + struct MBOX_CMD_DAT B2A[4]; /* Address Offset: 0x0030 */ + uint32_t RESERVED0050[44]; /* Address Offset: 0x0050 */ + __IO uint32_t ATOMIC_LOCK[32]; /* Address Offset: 0x0100 */ +}; +/* PMU Register Structure Define */ +struct PMU_REG { + __IO uint32_t WAKEUP_CFG[4]; /* Address Offset: 0x0000 */ + uint32_t RESERVED0010[2]; /* Address Offset: 0x0010 */ + __IO uint32_t WAKEUP_CFG6; /* Address Offset: 0x0018 */ + uint32_t RESERVED001C[5]; /* Address Offset: 0x001C */ + __IO uint32_t PWRDN_CON; /* Address Offset: 0x0030 */ + __I uint32_t PWRDN_ST; /* Address Offset: 0x0034 */ + __IO uint32_t PLL_CON; /* Address Offset: 0x0038 */ + __IO uint32_t PWRMODE_CON; /* Address Offset: 0x003C */ + __IO uint32_t SFT_CON; /* Address Offset: 0x0040 */ + uint32_t RESERVED0044[3]; /* Address Offset: 0x0044 */ + __IO uint32_t LDO_CON[3]; /* Address Offset: 0x0050 */ + __I uint32_t LDO_STAT; /* Address Offset: 0x005C */ + __IO uint32_t INT_CON; /* Address Offset: 0x0060 */ + __IO uint32_t INT_ST; /* Address Offset: 0x0064 */ + __IO uint32_t PWRMODE_GPIO_POS_INT_CON; /* Address Offset: 0x0068 */ + __IO uint32_t PWRMODE_GPIO_NEG_INT_CON; /* Address Offset: 0x006C */ + __IO uint32_t DSP_GPIO_POS_INT_CON; /* Address Offset: 0x0070 */ + __IO uint32_t DSP_GPIO_NEG_INT_CON; /* Address Offset: 0x0074 */ + __IO uint32_t PWRMODE_GPIO_POS_INT_ST; /* Address Offset: 0x0078 */ + __IO uint32_t PWRMODE_GPIO_NEG_INT_ST; /* Address Offset: 0x007C */ + __IO uint32_t DSP_GPIO_POS_INT_ST; /* Address Offset: 0x0080 */ + __IO uint32_t DSP_GPIO_NEG_INT_ST; /* Address Offset: 0x0084 */ + __IO uint32_t PWRDN_INTEN; /* Address Offset: 0x0088 */ + __IO uint32_t PWRDN_INT_STATUS; /* Address Offset: 0x008C */ + __IO uint32_t WAKEUP_STATUS; /* Address Offset: 0x0090 */ + uint32_t RESERVED0094[3]; /* Address Offset: 0x0094 */ + __IO uint32_t BUS_CLR; /* Address Offset: 0x00A0 */ + __IO uint32_t BUS_IDLE_REQ; /* Address Offset: 0x00A4 */ + __I uint32_t BUS_IDLE_ST; /* Address Offset: 0x00A8 */ + __I uint32_t BUS_IDLE_ACK; /* Address Offset: 0x00AC */ + __I uint32_t POWER_ST; /* Address Offset: 0x00B0 */ + __I uint32_t CORE_PWR_ST; /* Address Offset: 0x00B4 */ + __IO uint32_t OSC_CNT; /* Address Offset: 0x00B8 */ + __IO uint32_t PLLLOCK_CNT; /* Address Offset: 0x00BC */ + __IO uint32_t PWRMODE_TIMEOUT_CNT; /* Address Offset: 0x00C0 */ + __IO uint32_t NOC_AUTO_ENA; /* Address Offset: 0x00C4 */ + uint32_t RESERVED00C8[2]; /* Address Offset: 0x00C8 */ + __IO uint32_t DSPAPM_CON; /* Address Offset: 0x00D0 */ + uint32_t RESERVED00D4; /* Address Offset: 0x00D4 */ + __IO uint32_t DSP_LDO_ADJ_CNT; /* Address Offset: 0x00D8 */ + __IO uint32_t DSP_TIMEOUT_CNT; /* Address Offset: 0x00DC */ + __IO uint32_t PWRMODE_LDO_ADJ_CNT; /* Address Offset: 0x00E0 */ + __IO uint32_t SHRM_CON0; /* Address Offset: 0x00E4 */ + __IO uint32_t DSPTCM_CON[2]; /* Address Offset: 0x00E8 */ + __IO uint32_t SYS_REG[4]; /* Address Offset: 0x00F0 */ + __IO uint32_t SHRM_CON1; /* Address Offset: 0x0100 */ + __IO uint32_t DSPTCM_CON1[2]; /* Address Offset: 0x0104 */ +}; +/* DMA Register Structure Define */ +struct DMA_CHANNEL_STATUS { + __I uint32_t CSR; + __I uint32_t CPC; +}; +struct DMA_CHANNEL_CONFIG { + __I uint32_t SAR; + __I uint32_t DAR; + __I uint32_t CCR; + __I uint32_t LC0; + __I uint32_t LC1; + uint32_t PADDING[3]; +}; +struct DMA_REG { + __I uint32_t DSR; /* Address Offset: 0x0000 */ + __I uint32_t DPC; /* Address Offset: 0x0004 */ + uint32_t RESERVED0008[6]; /* Address Offset: 0x0008 */ + __IO uint32_t INTEN; /* Address Offset: 0x0020 */ + __I uint32_t EVENT_RIS; /* Address Offset: 0x0024 */ + __I uint32_t INTMIS; /* Address Offset: 0x0028 */ + __O uint32_t INTCLR; /* Address Offset: 0x002C */ + __I uint32_t FSRD; /* Address Offset: 0x0030 */ + __I uint32_t FSRC; /* Address Offset: 0x0034 */ + __IO uint32_t FTRD; /* Address Offset: 0x0038 */ + uint32_t RESERVED003C; /* Address Offset: 0x003C */ + __I uint32_t FTR[6]; /* Address Offset: 0x0040 */ + uint32_t RESERVED0058[42]; /* Address Offset: 0x0058 */ + struct DMA_CHANNEL_STATUS CHAN_STS[6]; /* Address Offset: 0x0100 */ + uint32_t RESERVED0130[180]; /* Address Offset: 0x0130 */ + struct DMA_CHANNEL_CONFIG CHAN_CFG[6]; /* Address Offset: 0x0400 */ + uint32_t RESERVED04C0[528]; /* Address Offset: 0x04C0 */ + __I uint32_t DBGSTATUS; /* Address Offset: 0x0D00 */ + __O uint32_t DBGCMD; /* Address Offset: 0x0D04 */ + __O uint32_t DBGINST[2]; /* Address Offset: 0x0D08 */ + uint32_t RESERVED0D10[60]; /* Address Offset: 0x0D10 */ + __I uint32_t CR[5]; /* Address Offset: 0x0E00 */ + __I uint32_t CRDN; /* Address Offset: 0x0E14 */ + uint32_t RESERVED0E18[26]; /* Address Offset: 0x0E18 */ + __IO uint32_t WD; /* Address Offset: 0x0E80 */ +}; +/* ACDCDIG Register Structure Define */ +struct ACDCDIG_REG { + __IO uint32_t VUCTL; /* Address Offset: 0x0000 */ + __IO uint32_t VUCTIME; /* Address Offset: 0x0004 */ + __IO uint32_t DIGEN; /* Address Offset: 0x0008 */ + __IO uint32_t CLKCTRL; /* Address Offset: 0x000C */ + __IO uint32_t CLKDIV; /* Address Offset: 0x0010 */ + __IO uint32_t REFCFG; /* Address Offset: 0x0014 */ + __IO uint32_t ADCCFG0; /* Address Offset: 0x0018 */ + __IO uint32_t ADCCFG1; /* Address Offset: 0x001C */ + __IO uint32_t ADCCFG2; /* Address Offset: 0x0020 */ + __IO uint32_t ADCCFG3; /* Address Offset: 0x0024 */ + __IO uint32_t ADCVOLL; /* Address Offset: 0x0028 */ + __IO uint32_t ADCVOLR; /* Address Offset: 0x002C */ + __IO uint32_t ALC0; /* Address Offset: 0x0030 */ + __IO uint32_t ALC1; /* Address Offset: 0x0034 */ + __IO uint32_t ALC2; /* Address Offset: 0x0038 */ + __IO uint32_t ADCNG; /* Address Offset: 0x003C */ + __IO uint32_t HPFCTRL; /* Address Offset: 0x0040 */ + __I uint32_t ADCRVOLL; /* Address Offset: 0x0044 */ + __I uint32_t ADCRVOLR; /* Address Offset: 0x0048 */ + __IO uint32_t PGACFG; /* Address Offset: 0x004C */ + __IO uint32_t PGAGAINL; /* Address Offset: 0x0050 */ + __IO uint32_t PGAGAINR; /* Address Offset: 0x0054 */ + __IO uint32_t LILMT1; /* Address Offset: 0x0058 */ + __IO uint32_t LILMT2; /* Address Offset: 0x005C */ + __IO uint32_t LILMTNG1; /* Address Offset: 0x0060 */ + __I uint32_t LILMTNG2; /* Address Offset: 0x0064 */ + __IO uint32_t PDMCTRL; /* Address Offset: 0x0068 */ + __IO uint32_t I2SCKM; /* Address Offset: 0x006C */ + __IO uint32_t I2SDIV; /* Address Offset: 0x0070 */ + __IO uint32_t I2STXCR0; /* Address Offset: 0x0074 */ + __IO uint32_t I2STXCR1; /* Address Offset: 0x0078 */ + __IO uint32_t I2STXCR2; /* Address Offset: 0x007C */ + __IO uint32_t I2STXCMD; /* Address Offset: 0x0080 */ + __I uint32_t VERSION; /* Address Offset: 0x0084 */ +}; +/* UART Register Structure Define */ +struct UART_REG { + union { + __IO uint32_t RBR; /* Address Offset: 0x0000 */ + __IO uint32_t THR; /* Address Offset: 0x0000 */ + __IO uint32_t DLL; /* Address Offset: 0x0000 */ + }; + union { + __IO uint32_t DLH; /* Address Offset: 0x0004 */ + __IO uint32_t IER; /* Address Offset: 0x0004 */ + }; + union { + __I uint32_t IIR; /* Address Offset: 0x0008 */ + __O uint32_t FCR; /* Address Offset: 0x0008 */ + }; + __IO uint32_t LCR; /* Address Offset: 0x000C */ + __IO uint32_t MCR; /* Address Offset: 0x0010 */ + __I uint32_t LSR; /* Address Offset: 0x0014 */ + __I uint32_t MSR; /* Address Offset: 0x0018 */ + __IO uint32_t SCR; /* Address Offset: 0x001C */ + uint32_t RESERVED0020[4]; /* Address Offset: 0x0020 */ + union { + __I uint32_t SRBR; /* Address Offset: 0x0030 */ + __I uint32_t STHR; /* Address Offset: 0x0030 */ + }; + uint32_t RESERVED0034[15]; /* Address Offset: 0x0034 */ + __IO uint32_t FAR; /* Address Offset: 0x0070 */ + __I uint32_t TFR; /* Address Offset: 0x0074 */ + __O uint32_t RFW; /* Address Offset: 0x0078 */ + __I uint32_t USR; /* Address Offset: 0x007C */ + __IO uint32_t TFL; /* Address Offset: 0x0080 */ + __I uint32_t RFL; /* Address Offset: 0x0084 */ + __O uint32_t SRR; /* Address Offset: 0x0088 */ + __IO uint32_t SRTS; /* Address Offset: 0x008C */ + __IO uint32_t SBCR; /* Address Offset: 0x0090 */ + __IO uint32_t SDMAM; /* Address Offset: 0x0094 */ + __IO uint32_t SFE; /* Address Offset: 0x0098 */ + __IO uint32_t SRT; /* Address Offset: 0x009C */ + __IO uint32_t STET; /* Address Offset: 0x00A0 */ + __IO uint32_t HTX; /* Address Offset: 0x00A4 */ + __O uint32_t DMASA; /* Address Offset: 0x00A8 */ + uint32_t RESERVED00AC[18]; /* Address Offset: 0x00AC */ + __I uint32_t CPR; /* Address Offset: 0x00F4 */ + __I uint32_t UCV; /* Address Offset: 0x00F8 */ + __I uint32_t CTR; /* Address Offset: 0x00FC */ +}; +/* PWM Register Structure Define */ +struct PWM_CHANNEL { + __I uint32_t CNT; + __IO uint32_t PERIOD_HPR; + __IO uint32_t DUTY_LPR; + __IO uint32_t CTRL; +}; +struct PWM_REG { + struct PWM_CHANNEL CHANNELS[4]; /* Address Offset: 0x0000 */ + __IO uint32_t INTSTS; /* Address Offset: 0x0040 */ + __IO uint32_t INT_EN; /* Address Offset: 0x0044 */ + uint32_t RESERVED0048[2]; /* Address Offset: 0x0048 */ + __IO uint32_t FIFO_CTRL; /* Address Offset: 0x0050 */ + __IO uint32_t FIFO_INTSTS; /* Address Offset: 0x0054 */ + __IO uint32_t FIFO_TOUTTHR; /* Address Offset: 0x0058 */ + __IO uint32_t VERSION_ID; /* Address Offset: 0x005C */ + __I uint32_t FIFO; /* Address Offset: 0x0060 */ + uint32_t RESERVED0064[7]; /* Address Offset: 0x0064 */ + __IO uint32_t PWRMATCH_CTRL; /* Address Offset: 0x0080 */ + __IO uint32_t PWRMATCH_LPRE; /* Address Offset: 0x0084 */ + __IO uint32_t PWRMATCH_HPRE; /* Address Offset: 0x0088 */ + __IO uint32_t PWRMATCH_LD; /* Address Offset: 0x008C */ + __IO uint32_t PWRMATCH_HD_ZERO; /* Address Offset: 0x0090 */ + __IO uint32_t PWRMATCH_HD_ONE; /* Address Offset: 0x0094 */ + __IO uint32_t PWRMATCH_VALUE[10]; /* Address Offset: 0x0098 */ + uint32_t RESERVED00C0[3]; /* Address Offset: 0x00C0 */ + __I uint32_t PWM3_PWRCAPTURE_VALUE; /* Address Offset: 0x00CC */ + __IO uint32_t FILTER_CTRL; /* Address Offset: 0x00D0 */ +}; +/* TIMER Register Structure Define */ +struct TIMER_REG { + __IO uint32_t LOAD_COUNT[2]; /* Address Offset: 0x0000 */ + __I uint32_t CURRENT_VALUE[2]; /* Address Offset: 0x0008 */ + __IO uint32_t CONTROLREG; /* Address Offset: 0x0010 */ + uint32_t RESERVED0014; /* Address Offset: 0x0014 */ + __IO uint32_t INTSTATUS; /* Address Offset: 0x0018 */ +}; +/* WDT Register Structure Define */ +struct WDT_REG { + __IO uint32_t CR; /* Address Offset: 0x0000 */ + __IO uint32_t TORR; /* Address Offset: 0x0004 */ + __I uint32_t CCVR; /* Address Offset: 0x0008 */ + __O uint32_t CRR; /* Address Offset: 0x000C */ + __I uint32_t STAT; /* Address Offset: 0x0010 */ + __I uint32_t EOI; /* Address Offset: 0x0014 */ +}; +/* I2C Register Structure Define */ +struct I2C_REG { + __IO uint32_t CON; /* Address Offset: 0x0000 */ + __IO uint32_t CLKDIV; /* Address Offset: 0x0004 */ + __IO uint32_t MRXADDR; /* Address Offset: 0x0008 */ + __IO uint32_t MRXRADDR; /* Address Offset: 0x000C */ + __IO uint32_t MTXCNT; /* Address Offset: 0x0010 */ + __IO uint32_t MRXCNT; /* Address Offset: 0x0014 */ + __IO uint32_t IEN; /* Address Offset: 0x0018 */ + __IO uint32_t IPD; /* Address Offset: 0x001C */ + __I uint32_t FCNT; /* Address Offset: 0x0020 */ + __IO uint32_t SCL_OE_DB; /* Address Offset: 0x0024 */ + uint32_t RESERVED0028[54]; /* Address Offset: 0x0028 */ + __IO uint32_t TXDATA[8]; /* Address Offset: 0x0100 */ + uint32_t RESERVED0120[56]; /* Address Offset: 0x0120 */ + __I uint32_t RXDATA[8]; /* Address Offset: 0x0200 */ + __I uint32_t ST; /* Address Offset: 0x0220 */ + __IO uint32_t DBGCTRL; /* Address Offset: 0x0224 */ +}; +/* SPI2APB Register Structure Define */ +struct SPI2APB_REG { + __IO uint32_t CTRL0; /* Address Offset: 0x0000 */ + uint32_t RESERVED0004[8]; /* Address Offset: 0x0004 */ + __I uint32_t SR; /* Address Offset: 0x0024 */ + uint32_t RESERVED0028; /* Address Offset: 0x0028 */ + __IO uint32_t IMR; /* Address Offset: 0x002C */ + uint32_t RESERVED0030; /* Address Offset: 0x0030 */ + __IO uint32_t RISR; /* Address Offset: 0x0034 */ + __O uint32_t ICR; /* Address Offset: 0x0038 */ + uint32_t RESERVED003C[3]; /* Address Offset: 0x003C */ + __IO uint32_t VERSION; /* Address Offset: 0x0048 */ + uint32_t RESERVED004C; /* Address Offset: 0x004C */ + __IO uint32_t QUICK_REG[3]; /* Address Offset: 0x0050 */ +}; +/* SPI Register Structure Define */ +struct SPI_REG { + __IO uint32_t CTRLR[2]; /* Address Offset: 0x0000 */ + __IO uint32_t ENR; /* Address Offset: 0x0008 */ + __IO uint32_t SER; /* Address Offset: 0x000C */ + __IO uint32_t BAUDR; /* Address Offset: 0x0010 */ + __IO uint32_t TXFTLR; /* Address Offset: 0x0014 */ + __IO uint32_t RXFTLR; /* Address Offset: 0x0018 */ + __I uint32_t TXFLR; /* Address Offset: 0x001C */ + __I uint32_t RXFLR; /* Address Offset: 0x0020 */ + __IO uint32_t SR; /* Address Offset: 0x0024 */ + __IO uint32_t IPR; /* Address Offset: 0x0028 */ + __IO uint32_t IMR; /* Address Offset: 0x002C */ + __IO uint32_t ISR; /* Address Offset: 0x0030 */ + __IO uint32_t RISR; /* Address Offset: 0x0034 */ + __IO uint32_t ICR; /* Address Offset: 0x0038 */ + __IO uint32_t DMACR; /* Address Offset: 0x003C */ + __IO uint32_t DMATDLR; /* Address Offset: 0x0040 */ + __IO uint32_t DMARDLR; /* Address Offset: 0x0044 */ + uint32_t RESERVED0048; /* Address Offset: 0x0048 */ + __IO uint32_t TIMEOUT; /* Address Offset: 0x004C */ + __IO uint32_t BYPASS; /* Address Offset: 0x0050 */ + uint32_t RESERVED0054[235]; /* Address Offset: 0x0054 */ + __O uint32_t TXDR; /* Address Offset: 0x0400 */ + uint32_t RESERVED0404[255]; /* Address Offset: 0x0404 */ + __IO uint32_t RXDR; /* Address Offset: 0x0800 */ +}; +/* FSPI Register Structure Define */ +struct FSPI_REG { + __IO uint32_t CTRL0; /* Address Offset: 0x0000 */ + __IO uint32_t IMR; /* Address Offset: 0x0004 */ + __IO uint32_t ICLR; /* Address Offset: 0x0008 */ + __IO uint32_t FTLR; /* Address Offset: 0x000C */ + __IO uint32_t RCVR; /* Address Offset: 0x0010 */ + __IO uint32_t AX0; /* Address Offset: 0x0014 */ + __IO uint32_t ABIT0; /* Address Offset: 0x0018 */ + __IO uint32_t ISR; /* Address Offset: 0x001C */ + __IO uint32_t FSR; /* Address Offset: 0x0020 */ + __I uint32_t SR; /* Address Offset: 0x0024 */ + __I uint32_t RISR; /* Address Offset: 0x0028 */ + __I uint32_t VER; /* Address Offset: 0x002C */ + __IO uint32_t QOP; /* Address Offset: 0x0030 */ + __IO uint32_t EXT_CTRL; /* Address Offset: 0x0034 */ + __IO uint32_t POLL_CTRL; /* Address Offset: 0x0038 */ + __IO uint32_t DLL_CTRL0; /* Address Offset: 0x003C */ + __IO uint32_t HRDYMASK; /* Address Offset: 0x0040 */ + __IO uint32_t EXT_AX; /* Address Offset: 0x0044 */ + __IO uint32_t SCLK_INATM_CNT; /* Address Offset: 0x0048 */ + __IO uint32_t AUTO_RF_CNT; /* Address Offset: 0x004C */ + __O uint32_t XMMC_WCMD0; /* Address Offset: 0x0050 */ + __O uint32_t XMMC_RCMD0; /* Address Offset: 0x0054 */ + __IO uint32_t XMMC_CTRL; /* Address Offset: 0x0058 */ + __IO uint32_t MODE; /* Address Offset: 0x005C */ + __IO uint32_t DEVRGN; /* Address Offset: 0x0060 */ + __IO uint32_t DEVSIZE0; /* Address Offset: 0x0064 */ + __IO uint32_t TME0; /* Address Offset: 0x0068 */ + __IO uint32_t POLLDLY_CTRL; /* Address Offset: 0x006C */ + uint32_t RESERVED0070[4]; /* Address Offset: 0x0070 */ + __IO uint32_t DMATR; /* Address Offset: 0x0080 */ + __IO uint32_t DMAADDR; /* Address Offset: 0x0084 */ + uint32_t RESERVED0088[2]; /* Address Offset: 0x0088 */ + __I uint32_t POLL_DATA; /* Address Offset: 0x0090 */ + __IO uint32_t XMMCSR; /* Address Offset: 0x0094 */ + uint32_t RESERVED0098[26]; /* Address Offset: 0x0098 */ + __O uint32_t CMD; /* Address Offset: 0x0100 */ + __O uint32_t ADDR; /* Address Offset: 0x0104 */ + __IO uint32_t DATA; /* Address Offset: 0x0108 */ + uint32_t RESERVED010C[61]; /* Address Offset: 0x010C */ + __IO uint32_t CTRL1; /* Address Offset: 0x0200 */ + uint32_t RESERVED0204[4]; /* Address Offset: 0x0204 */ + __IO uint32_t AX1; /* Address Offset: 0x0214 */ + __IO uint32_t ABIT1; /* Address Offset: 0x0218 */ + uint32_t RESERVED021C[8]; /* Address Offset: 0x021C */ + __IO uint32_t DLL_CTRL1; /* Address Offset: 0x023C */ + uint32_t RESERVED0240[4]; /* Address Offset: 0x0240 */ + __O uint32_t XMMC_WCMD1; /* Address Offset: 0x0250 */ + __O uint32_t XMMC_RCMD1; /* Address Offset: 0x0254 */ + uint32_t RESERVED0258[3]; /* Address Offset: 0x0258 */ + __IO uint32_t DEVSIZE1; /* Address Offset: 0x0264 */ + __IO uint32_t TME1; /* Address Offset: 0x0268 */ +}; +/* MMC Register Structure Define */ +struct MMC_REG { + __IO uint32_t CTRL; /* Address Offset: 0x0000 */ + __IO uint32_t PWREN; /* Address Offset: 0x0004 */ + __IO uint32_t CLKDIV; /* Address Offset: 0x0008 */ + __IO uint32_t CLKSRC; /* Address Offset: 0x000C */ + __IO uint32_t CLKENA; /* Address Offset: 0x0010 */ + __IO uint32_t TMOUT; /* Address Offset: 0x0014 */ + __IO uint32_t CTYPE; /* Address Offset: 0x0018 */ + __IO uint32_t BLKSIZ; /* Address Offset: 0x001C */ + __IO uint32_t BYTCNT; /* Address Offset: 0x0020 */ + __IO uint32_t INTMASK; /* Address Offset: 0x0024 */ + __IO uint32_t CMDARG; /* Address Offset: 0x0028 */ + __IO uint32_t CMD; /* Address Offset: 0x002C */ + __I uint32_t RESP[4]; /* Address Offset: 0x0030 */ + __IO uint32_t MINTSTS; /* Address Offset: 0x0040 */ + __IO uint32_t RINTSTS; /* Address Offset: 0x0044 */ + __I uint32_t STATUS; /* Address Offset: 0x0048 */ + __IO uint32_t FIFOTH; /* Address Offset: 0x004C */ + __I uint32_t CDETECT; /* Address Offset: 0x0050 */ + __IO uint32_t WRTPRT; /* Address Offset: 0x0054 */ + uint32_t RESERVED0058; /* Address Offset: 0x0058 */ + __I uint32_t TCBCNT; /* Address Offset: 0x005C */ + __I uint32_t TBBCNT; /* Address Offset: 0x0060 */ + __IO uint32_t DEBNCE; /* Address Offset: 0x0064 */ + __IO uint32_t USRID; /* Address Offset: 0x0068 */ + __I uint32_t VERID; /* Address Offset: 0x006C */ + __I uint32_t HCON; /* Address Offset: 0x0070 */ + __IO uint32_t UHSREG; /* Address Offset: 0x0074 */ + __IO uint32_t RSTN; /* Address Offset: 0x0078 */ + uint32_t RESERVED007C; /* Address Offset: 0x007C */ + __IO uint32_t BMOD; /* Address Offset: 0x0080 */ + __O uint32_t PLDMND; /* Address Offset: 0x0084 */ + __IO uint32_t DBADDR; /* Address Offset: 0x0088 */ + __IO uint32_t IDSTS; /* Address Offset: 0x008C */ + __IO uint32_t IDINTEN; /* Address Offset: 0x0090 */ + __IO uint32_t DSCADDR; /* Address Offset: 0x0094 */ + __IO uint32_t BUFADDR; /* Address Offset: 0x0098 */ + uint32_t RESERVED009C[25]; /* Address Offset: 0x009C */ + __IO uint32_t CARDTHRCTL; /* Address Offset: 0x0100 */ + __IO uint32_t BACKEND_POWER; /* Address Offset: 0x0104 */ + uint32_t RESERVED0108; /* Address Offset: 0x0108 */ + __IO uint32_t EMMCDDR_REG; /* Address Offset: 0x010C */ + uint32_t RESERVED0110[4]; /* Address Offset: 0x0110 */ + __IO uint32_t RDYINT_GEN; /* Address Offset: 0x0120 */ + uint32_t RESERVED0124[55]; /* Address Offset: 0x0124 */ + __IO uint32_t FIFO_BASE; /* Address Offset: 0x0200 */ +}; +/* GPIO Register Structure Define */ +struct GPIO_REG { + __IO uint32_t SWPORT_DR_L; /* Address Offset: 0x0000 */ + __IO uint32_t SWPORT_DR_H; /* Address Offset: 0x0004 */ + __IO uint32_t SWPORT_DDR_L; /* Address Offset: 0x0008 */ + __IO uint32_t SWPORT_DDR_H; /* Address Offset: 0x000C */ + __IO uint32_t INT_EN_L; /* Address Offset: 0x0010 */ + __IO uint32_t INT_EN_H; /* Address Offset: 0x0014 */ + __IO uint32_t INT_MASK_L; /* Address Offset: 0x0018 */ + __IO uint32_t INT_MASK_H; /* Address Offset: 0x001C */ + __IO uint32_t INT_TYPE_L; /* Address Offset: 0x0020 */ + __IO uint32_t INT_TYPE_H; /* Address Offset: 0x0024 */ + __IO uint32_t INT_POLARITY_L; /* Address Offset: 0x0028 */ + __IO uint32_t INT_POLARITY_H; /* Address Offset: 0x002C */ + __IO uint32_t INT_BOTHEDGE_L; /* Address Offset: 0x0030 */ + __IO uint32_t INT_BOTHEDGE_H; /* Address Offset: 0x0034 */ + __IO uint32_t DEBOUNCE_L; /* Address Offset: 0x0038 */ + __IO uint32_t DEBOUNCE_H; /* Address Offset: 0x003C */ + __IO uint32_t DBCLK_DIV_EN_L; /* Address Offset: 0x0040 */ + __IO uint32_t DBCLK_DIV_EN_H; /* Address Offset: 0x0044 */ + __IO uint32_t DBCLK_DIV_CON; /* Address Offset: 0x0048 */ + uint32_t RESERVED004C; /* Address Offset: 0x004C */ + __I uint32_t INT_STATUS; /* Address Offset: 0x0050 */ + uint32_t RESERVED0054; /* Address Offset: 0x0054 */ + __I uint32_t INT_RAWSTATUS; /* Address Offset: 0x0058 */ + uint32_t RESERVED005C; /* Address Offset: 0x005C */ + __IO uint32_t PORT_EOI_L; /* Address Offset: 0x0060 */ + __IO uint32_t PORT_EOI_H; /* Address Offset: 0x0064 */ + uint32_t RESERVED0068[2]; /* Address Offset: 0x0068 */ + __I uint32_t EXT_PORT; /* Address Offset: 0x0070 */ + uint32_t RESERVED0074; /* Address Offset: 0x0074 */ + __I uint32_t VER_ID; /* Address Offset: 0x0078 */ +}; +/* KEY_CTRL Register Structure Define */ +struct KEY_CTRL_REG { + __IO uint32_t CON; /* Address Offset: 0x0000 */ + __IO uint32_t CAL_TH; /* Address Offset: 0x0004 */ + __I uint32_t DET_REC; /* Address Offset: 0x0008 */ + __IO uint32_t INT_CON; /* Address Offset: 0x000C */ + __IO uint32_t INT_ST; /* Address Offset: 0x0010 */ +}; +/* PDM Register Structure Define */ +struct PDM_REG { + __IO uint32_t SYSCONFIG; /* Address Offset: 0x0000 */ + __IO uint32_t CTRL[2]; /* Address Offset: 0x0004 */ + __IO uint32_t CLK_CTRL; /* Address Offset: 0x000C */ + __IO uint32_t HPF_CTRL; /* Address Offset: 0x0010 */ + __IO uint32_t FIFO_CTRL; /* Address Offset: 0x0014 */ + __IO uint32_t DMA_CTRL; /* Address Offset: 0x0018 */ + __IO uint32_t INT_EN; /* Address Offset: 0x001C */ + __IO uint32_t INT_CLR; /* Address Offset: 0x0020 */ + __I uint32_t INT_ST; /* Address Offset: 0x0024 */ + uint32_t RESERVED0028[2]; /* Address Offset: 0x0028 */ + __I uint32_t RXFIFO_DATA_REG; /* Address Offset: 0x0030 */ + __I uint32_t DATA0R_REG; /* Address Offset: 0x0034 */ + __I uint32_t DATA0L_REG; /* Address Offset: 0x0038 */ + __I uint32_t DATA1R_REG; /* Address Offset: 0x003C */ + __I uint32_t DATA1L_REG; /* Address Offset: 0x0040 */ + __I uint32_t DATA2R_REG; /* Address Offset: 0x0044 */ + __I uint32_t DATA2L_REG; /* Address Offset: 0x0048 */ + __I uint32_t DATA3R_REG; /* Address Offset: 0x004C */ + __I uint32_t DATA3L_REG; /* Address Offset: 0x0050 */ + __I uint32_t DATA_VALID; /* Address Offset: 0x0054 */ + __I uint32_t VERSION; /* Address Offset: 0x0058 */ + uint32_t RESERVED005C[233]; /* Address Offset: 0x005C */ + __I uint32_t INCR_RXDR; /* Address Offset: 0x0400 */ +}; +/* I2STDM Register Structure Define */ +struct I2STDM_REG { + __IO uint32_t TXCR; /* Address Offset: 0x0000 */ + __IO uint32_t RXCR; /* Address Offset: 0x0004 */ + __IO uint32_t CKR; /* Address Offset: 0x0008 */ + __IO uint32_t TXFIFOLR; /* Address Offset: 0x000C */ + __IO uint32_t DMACR; /* Address Offset: 0x0010 */ + __IO uint32_t INTCR; /* Address Offset: 0x0014 */ + __IO uint32_t INTSR; /* Address Offset: 0x0018 */ + __IO uint32_t XFER; /* Address Offset: 0x001C */ + __IO uint32_t CLR; /* Address Offset: 0x0020 */ + __IO uint32_t TXDR; /* Address Offset: 0x0024 */ + __IO uint32_t RXDR; /* Address Offset: 0x0028 */ + __IO uint32_t RXFIFOLR; /* Address Offset: 0x002C */ + __IO uint32_t TDM_TXCTRL; /* Address Offset: 0x0030 */ + __IO uint32_t TDM_RXCTRL; /* Address Offset: 0x0034 */ + __IO uint32_t CLKDIV; /* Address Offset: 0x0038 */ + __IO uint32_t VERSION; /* Address Offset: 0x003C */ +}; +/* VAD Register Structure Define */ +struct VAD_REG { + __IO uint32_t CONTROL; /* Address Offset: 0x0000 */ + __IO uint32_t VS_ADDR; /* Address Offset: 0x0004 */ + uint32_t RESERVED0008[17]; /* Address Offset: 0x0008 */ + __IO uint32_t TIMEOUT; /* Address Offset: 0x004C */ + __IO uint32_t RAM_START_ADDR; /* Address Offset: 0x0050 */ + __IO uint32_t RAM_END_ADDR; /* Address Offset: 0x0054 */ + __IO uint32_t RAM_CUR_ADDR; /* Address Offset: 0x0058 */ + __IO uint32_t DET_CON[6]; /* Address Offset: 0x005C */ + __IO uint32_t INT; /* Address Offset: 0x0074 */ + __IO uint32_t AUX_CON0; /* Address Offset: 0x0078 */ + __I uint32_t SAMPLE_CNT; /* Address Offset: 0x007C */ + __IO uint32_t RAM_START_ADDR_BUS; /* Address Offset: 0x0080 */ + __IO uint32_t RAM_END_ADDR_BUS; /* Address Offset: 0x0084 */ + __IO uint32_t RAM_CUR_ADDR_BUS; /* Address Offset: 0x0088 */ + __IO uint32_t AUX_CON1; /* Address Offset: 0x008C */ + uint32_t RESERVED0090[28]; /* Address Offset: 0x0090 */ + __IO uint32_t NOISE_FIRST_DATA; /* Address Offset: 0x0100 */ + uint32_t RESERVED0104[126]; /* Address Offset: 0x0104 */ + __IO uint32_t NOISE_LAST_DATA; /* Address Offset: 0x02FC */ +}; +/* VOP Register Structure Define */ +struct VOP_REG { + __IO uint32_t REG_CFG_DONE; /* Address Offset: 0x0000 */ + __I uint32_t VERSION; /* Address Offset: 0x0004 */ + __IO uint32_t DSP_BG; /* Address Offset: 0x0008 */ + __IO uint32_t MCU; /* Address Offset: 0x000C */ + __IO uint32_t SYS_CTRL0; /* Address Offset: 0x0010 */ + __IO uint32_t SYS_CTRL1; /* Address Offset: 0x0014 */ + __IO uint32_t SYS_CTRL2; /* Address Offset: 0x0018 */ + uint32_t RESERVED001C; /* Address Offset: 0x001C */ + __IO uint32_t DSP_CTRL0; /* Address Offset: 0x0020 */ + __IO uint32_t DSP_CTRL1; /* Address Offset: 0x0024 */ + __IO uint32_t DSP_CTRL2; /* Address Offset: 0x0028 */ + __IO uint32_t VOP_STATUS; /* Address Offset: 0x002C */ + __IO uint32_t LINE_FLAG; /* Address Offset: 0x0030 */ + __IO uint32_t INTR_EN; /* Address Offset: 0x0034 */ + __IO uint32_t INTR_CLEAR; /* Address Offset: 0x0038 */ + __IO uint32_t INTR_STATUS; /* Address Offset: 0x003C */ + __IO uint32_t WIN0_CTRL0; /* Address Offset: 0x0040 */ + __IO uint32_t WIN0_CTRL1; /* Address Offset: 0x0044 */ + __IO uint32_t WIN0_VIR; /* Address Offset: 0x0048 */ + uint32_t RESERVED004C; /* Address Offset: 0x004C */ + __IO uint32_t WIN0_YRGB_MST; /* Address Offset: 0x0050 */ + __IO uint32_t WIN0_DSP_INFO; /* Address Offset: 0x0054 */ + __IO uint32_t WIN0_DSP_ST; /* Address Offset: 0x0058 */ + __IO uint32_t WIN0_COLOR_KEY; /* Address Offset: 0x005C */ + uint32_t RESERVED0060[3]; /* Address Offset: 0x0060 */ + __IO uint32_t WIN0_ALPHA_CTRL; /* Address Offset: 0x006C */ + __IO uint32_t WIN0_CBCR_MST; /* Address Offset: 0x0070 */ + __IO uint32_t WIN0_YRGB_MST_RAW; /* Address Offset: 0x0074 */ + __IO uint32_t WIN0_CBCR_MST_RAW; /* Address Offset: 0x0078 */ + __IO uint32_t WIN0_LOOP_OFFSET; /* Address Offset: 0x007C */ + __IO uint32_t WIN1_CTRL0; /* Address Offset: 0x0080 */ + __IO uint32_t WIN1_CTRL1; /* Address Offset: 0x0084 */ + __IO uint32_t WIN1_VIR; /* Address Offset: 0x0088 */ + uint32_t RESERVED008C; /* Address Offset: 0x008C */ + __IO uint32_t WIN1_YRGB_MST; /* Address Offset: 0x0090 */ + __IO uint32_t WIN1_DSP_INFO; /* Address Offset: 0x0094 */ + __IO uint32_t WIN1_DSP_ST; /* Address Offset: 0x0098 */ + __IO uint32_t WIN1_COLOR_KEY; /* Address Offset: 0x009C */ + uint32_t RESERVED00A0[3]; /* Address Offset: 0x00A0 */ + __IO uint32_t WIN1_ALPHA_CTRL; /* Address Offset: 0x00AC */ + __IO uint32_t WIN1_CBCR_MST; /* Address Offset: 0x00B0 */ + __IO uint32_t WIN1_YRGB_MST_RAW; /* Address Offset: 0x00B4 */ + __IO uint32_t WIN1_CBCR_MST_RAW; /* Address Offset: 0x00B8 */ + __IO uint32_t WIN1_LOOP_OFFSET; /* Address Offset: 0x00BC */ + __IO uint32_t WIN2_CTRL0; /* Address Offset: 0x00C0 */ + __IO uint32_t WIN2_CTRL1; /* Address Offset: 0x00C4 */ + __IO uint32_t WIN2_VIR; /* Address Offset: 0x00C8 */ + uint32_t RESERVED00CC; /* Address Offset: 0x00CC */ + __IO uint32_t WIN2_YRGB_MST; /* Address Offset: 0x00D0 */ + __IO uint32_t WIN2_DSP_INFO; /* Address Offset: 0x00D4 */ + __IO uint32_t WIN2_DSP_ST; /* Address Offset: 0x00D8 */ + __IO uint32_t WIN2_COLOR_KEY; /* Address Offset: 0x00DC */ + uint32_t RESERVED00E0[3]; /* Address Offset: 0x00E0 */ + __IO uint32_t WIN2_ALPHA_CTRL; /* Address Offset: 0x00EC */ + __IO uint32_t WIN2_CBCR_MST; /* Address Offset: 0x00F0 */ + __IO uint32_t WIN2_YRGB_MST_RAW; /* Address Offset: 0x00F4 */ + __IO uint32_t WIN2_CBCR_MST_RAW; /* Address Offset: 0x00F8 */ + __IO uint32_t WIN2_LOOP_OFFSET; /* Address Offset: 0x00FC */ + __IO uint32_t DSP_HTOTAL_HS_END; /* Address Offset: 0x0100 */ + __IO uint32_t DSP_HACT_ST_END; /* Address Offset: 0x0104 */ + __IO uint32_t DSP_VTOTAL_VS_END; /* Address Offset: 0x0108 */ + __IO uint32_t DSP_VACT_ST_END; /* Address Offset: 0x010C */ + __IO uint32_t DSP_VS_ST_END_F1; /* Address Offset: 0x0110 */ + __IO uint32_t DSP_VACT_ST_END_F1; /* Address Offset: 0x0114 */ + __IO uint32_t PRE_HTOTAL_HS_END; /* Address Offset: 0x0118 */ + __IO uint32_t PRE_HACT_ST_END; /* Address Offset: 0x011C */ + __IO uint32_t PRE_VTOTAL_VS_END; /* Address Offset: 0x0120 */ + __IO uint32_t PRE_VACT_ST_END; /* Address Offset: 0x0124 */ + uint32_t RESERVED0128[14]; /* Address Offset: 0x0128 */ + __IO uint32_t BCSH_CTRL; /* Address Offset: 0x0160 */ + __IO uint32_t BCSH_COL_BAR; /* Address Offset: 0x0164 */ + __IO uint32_t BCSH_BCS; /* Address Offset: 0x0168 */ + __IO uint32_t BCSH_H; /* Address Offset: 0x016C */ + __IO uint32_t GAMMA_COE_WORD0; /* Address Offset: 0x0170 */ + __IO uint32_t GAMMA_COE_WORD1; /* Address Offset: 0x0174 */ + __IO uint32_t GAMMA_COE_WORD2; /* Address Offset: 0x0178 */ + __IO uint32_t GAMMA_COE_WORD3; /* Address Offset: 0x017C */ + __IO uint32_t POST_CTRL; /* Address Offset: 0x0180 */ + __IO uint32_t COLOR_MATRIX_COE0; /* Address Offset: 0x0184 */ + __IO uint32_t COLOR_MATRIX_COE1; /* Address Offset: 0x0188 */ + __IO uint32_t COLOR_MATRIX_COE2; /* Address Offset: 0x018C */ + __IO uint32_t MCU_WRITE_DATA; /* Address Offset: 0x0190 */ + uint32_t RESERVED0194[23]; /* Address Offset: 0x0194 */ + __I uint32_t DBG_REG_SCAN_LINE; /* Address Offset: 0x01F0 */ + __IO uint32_t BLANKING_VALUE; /* Address Offset: 0x01F4 */ + __I uint32_t FLAG_REG_FRM_VALID; /* Address Offset: 0x01F8 */ + __O uint32_t FLAG_REG; /* Address Offset: 0x01FC */ + uint32_t WIN0_BPP_LUT[256]; /* Address Offset: 0x0200 */ + uint32_t WIN1_BPP_LUT[256]; /* Address Offset: 0x0600 */ + __IO uint32_t DSC_SYS_CTRL0_IMD; /* Address Offset: 0x0A00 */ + __IO uint32_t DSC_SYS_CTRL1; /* Address Offset: 0x0A04 */ + __IO uint32_t DSC_SYS_CTRL2; /* Address Offset: 0x0A08 */ + __IO uint32_t DSC_SYS_CTRL3; /* Address Offset: 0x0A0C */ + __IO uint32_t DSC_CFG[21]; /* Address Offset: 0x0A10 */ + uint32_t RESERVED0A64[3]; /* Address Offset: 0x0A64 */ + __IO uint32_t DSC_INT_EN; /* Address Offset: 0x0A70 */ + __IO uint32_t DSC_INT_CLR; /* Address Offset: 0x0A74 */ + __IO uint32_t DSC_INT_STATUS; /* Address Offset: 0x0A78 */ + uint32_t RESERVED0A7C; /* Address Offset: 0x0A7C */ + __I uint32_t DSC_DBG_STATUS0; /* Address Offset: 0x0A80 */ + __I uint32_t DSC_DBG_STATUS1; /* Address Offset: 0x0A84 */ + __IO uint32_t DSC_DBG_STATUS2; /* Address Offset: 0x0A88 */ +}; +/* DSI Register Structure Define */ +struct DSI_REG { + __I uint32_t VERSION; /* Address Offset: 0x0000 */ + __IO uint32_t PWR_UP; /* Address Offset: 0x0004 */ + __IO uint32_t CLKMGR_CFG; /* Address Offset: 0x0008 */ + __IO uint32_t DPI_VCID; /* Address Offset: 0x000C */ + __IO uint32_t DPI_COLOR_CODING; /* Address Offset: 0x0010 */ + __IO uint32_t DPI_CFG_POL; /* Address Offset: 0x0014 */ + __IO uint32_t DPI_LP_CMD_TIM; /* Address Offset: 0x0018 */ + uint32_t RESERVED001C[4]; /* Address Offset: 0x001C */ + __IO uint32_t PCKHDL_CFG; /* Address Offset: 0x002C */ + __IO uint32_t GEN_VCID; /* Address Offset: 0x0030 */ + __IO uint32_t MODE_CFG; /* Address Offset: 0x0034 */ + __IO uint32_t VID_MODE_CFG; /* Address Offset: 0x0038 */ + __IO uint32_t VID_PKT_SIZE; /* Address Offset: 0x003C */ + __IO uint32_t VID_NUM_CHUNKS; /* Address Offset: 0x0040 */ + __IO uint32_t VID_NULL_SIZE; /* Address Offset: 0x0044 */ + __IO uint32_t VID_HSA_TIME; /* Address Offset: 0x0048 */ + __IO uint32_t VID_HBP_TIME; /* Address Offset: 0x004C */ + __IO uint32_t VID_HLINE_TIME; /* Address Offset: 0x0050 */ + __IO uint32_t VID_VSA_LINES; /* Address Offset: 0x0054 */ + __IO uint32_t VID_VBP_LINES; /* Address Offset: 0x0058 */ + __IO uint32_t VID_VFP_LINES; /* Address Offset: 0x005C */ + __IO uint32_t VID_VACTIVE_LINES; /* Address Offset: 0x0060 */ + __IO uint32_t EDPI_CMD_SIZE; /* Address Offset: 0x0064 */ + __IO uint32_t CMD_MODE_CFG; /* Address Offset: 0x0068 */ + __IO uint32_t GEN_HDR; /* Address Offset: 0x006C */ + __IO uint32_t GEN_PLD_DATA; /* Address Offset: 0x0070 */ + __I uint32_t CMD_PKT_STATUS; /* Address Offset: 0x0074 */ + __IO uint32_t TO_CNT_CFG; /* Address Offset: 0x0078 */ + __IO uint32_t HS_RD_TO_CNT; /* Address Offset: 0x007C */ + __IO uint32_t LP_RD_TO_CNT; /* Address Offset: 0x0080 */ + __IO uint32_t HS_WR_TO_CNT; /* Address Offset: 0x0084 */ + __IO uint32_t LP_WR_TO_CNT; /* Address Offset: 0x0088 */ + __IO uint32_t BTA_TO_CNT; /* Address Offset: 0x008C */ + __IO uint32_t SDF_3D; /* Address Offset: 0x0090 */ + __IO uint32_t LPCLK_CTRL; /* Address Offset: 0x0094 */ + __IO uint32_t PHY_TMR_LPCLK_CFG; /* Address Offset: 0x0098 */ + __IO uint32_t PHY_TMR_CFG; /* Address Offset: 0x009C */ + __IO uint32_t PHY_RSTZ; /* Address Offset: 0x00A0 */ + __IO uint32_t PHY_IF_CFG; /* Address Offset: 0x00A4 */ + uint32_t RESERVED00A8[2]; /* Address Offset: 0x00A8 */ + __I uint32_t PHY_STATUS; /* Address Offset: 0x00B0 */ + uint32_t RESERVED00B4[2]; /* Address Offset: 0x00B4 */ + __I uint32_t INT_ST0; /* Address Offset: 0x00BC */ + __I uint32_t INT_ST1; /* Address Offset: 0x00C0 */ + __IO uint32_t INT_MSK0; /* Address Offset: 0x00C4 */ + __IO uint32_t INT_MSK1; /* Address Offset: 0x00C8 */ + uint32_t RESERVED00CC[3]; /* Address Offset: 0x00CC */ + __O uint32_t INT_FORCE0; /* Address Offset: 0x00D8 */ + __O uint32_t INT_FORCE1; /* Address Offset: 0x00DC */ + uint32_t RESERVED00E0[8]; /* Address Offset: 0x00E0 */ + __IO uint32_t VID_SHADOW_CTRL; /* Address Offset: 0x0100 */ + uint32_t RESERVED0104[2]; /* Address Offset: 0x0104 */ + __I uint32_t DPI_VCID_ACT; /* Address Offset: 0x010C */ + __I uint32_t DPI_COLOR_CODING_ACT; /* Address Offset: 0x0110 */ + uint32_t RESERVED0114; /* Address Offset: 0x0114 */ + __I uint32_t DPI_LP_CMD_TIM_ACT; /* Address Offset: 0x0118 */ + uint32_t RESERVED011C[7]; /* Address Offset: 0x011C */ + __I uint32_t VID_MODE_CFG_ACT; /* Address Offset: 0x0138 */ + __I uint32_t VID_PKT_SIZE_ACT; /* Address Offset: 0x013C */ + __I uint32_t VID_NUM_CHUNKS_ACT; /* Address Offset: 0x0140 */ + __I uint32_t VID_NULL_SIZE_ACT; /* Address Offset: 0x0144 */ + __I uint32_t VID_HSA_TIME_ACT; /* Address Offset: 0x0148 */ + __I uint32_t VID_HBP_TIME_ACT; /* Address Offset: 0x014C */ + __I uint32_t VID_HLINE_TIME_ACT; /* Address Offset: 0x0150 */ + __I uint32_t VID_VSA_LINES_ACT; /* Address Offset: 0x0154 */ + __I uint32_t VID_VBP_LINES_ACT; /* Address Offset: 0x0158 */ + __I uint32_t VID_VFP_LINES_ACT; /* Address Offset: 0x015C */ + __I uint32_t VID_VACTIVE_LINES_ACT; /* Address Offset: 0x0160 */ + uint32_t RESERVED0164[11]; /* Address Offset: 0x0164 */ + __IO uint32_t SDF_3D_ACT; /* Address Offset: 0x0190 */ +}; +/* VICAP Register Structure Define */ +struct VICAP_REG { + __IO uint32_t DVP_CTRL; /* Address Offset: 0x0000 */ + __IO uint32_t DVP_INTEN; /* Address Offset: 0x0004 */ + __IO uint32_t DVP_INTSTAT; /* Address Offset: 0x0008 */ + __IO uint32_t DVP_FOR; /* Address Offset: 0x000C */ + __IO uint32_t DVP_DMA_IDLE_REQ; /* Address Offset: 0x0010 */ + __IO uint32_t DVP_FRM0_ADDR_Y; /* Address Offset: 0x0014 */ + __IO uint32_t DVP_FRM0_ADDR_UV; /* Address Offset: 0x0018 */ + __IO uint32_t DVP_FRM1_ADDR_Y; /* Address Offset: 0x001C */ + __IO uint32_t DVP_FRM1_ADDR_UV; /* Address Offset: 0x0020 */ + __IO uint32_t DVP_VIR_LINE_WIDTH; /* Address Offset: 0x0024 */ + __IO uint32_t DVP_SET_SIZE; /* Address Offset: 0x0028 */ + __IO uint32_t DVP_BLOCK_LINE_NUM; /* Address Offset: 0x002C */ + __IO uint32_t DVP_BLOCK0_ADDR_Y; /* Address Offset: 0x0030 */ + __IO uint32_t DVP_BLOCK0_ADDR_UV; /* Address Offset: 0x0034 */ + __IO uint32_t DVP_BLOCK1_ADDR_Y; /* Address Offset: 0x0038 */ + __IO uint32_t DVP_BLOCK1_ADDR_UV; /* Address Offset: 0x003C */ + __IO uint32_t DVP_BLOCK_STATUS; /* Address Offset: 0x0040 */ + __IO uint32_t DVP_CROP; /* Address Offset: 0x0044 */ + __IO uint32_t DVP_PATH_SEL; /* Address Offset: 0x0048 */ + __IO uint32_t DVP_LINE_INT_NUM; /* Address Offset: 0x004C */ + __IO uint32_t DVP_WATER_LINE; /* Address Offset: 0x0050 */ + __IO uint32_t DVP_FIFO_ENTRY; /* Address Offset: 0x0054 */ + uint32_t RESERVED0058[2]; /* Address Offset: 0x0058 */ + __I uint32_t DVP_FRAME_STATUS; /* Address Offset: 0x0060 */ + __I uint32_t DVP_CUR_DST; /* Address Offset: 0x0064 */ + __IO uint32_t DVP_LAST_LINE; /* Address Offset: 0x0068 */ + __IO uint32_t DVP_LAST_PIX; /* Address Offset: 0x006C */ +}; +/* AUDIOPWM Register Structure Define */ +struct AUDIOPWM_REG { + __I uint32_t VERSION; /* Address Offset: 0x0000 */ + __IO uint32_t XFER; /* Address Offset: 0x0004 */ + __IO uint32_t SRC_CFG; /* Address Offset: 0x0008 */ + uint32_t RESERVED000C; /* Address Offset: 0x000C */ + __IO uint32_t PWM_CFG; /* Address Offset: 0x0010 */ + __I uint32_t PWM_ST; /* Address Offset: 0x0014 */ + __I uint32_t PWM_BUF_01; /* Address Offset: 0x0018 */ + __I uint32_t PWM_BUF_23; /* Address Offset: 0x001C */ + __IO uint32_t FIFO_CFG; /* Address Offset: 0x0020 */ + __I uint32_t FIFO_LVL; /* Address Offset: 0x0024 */ + __IO uint32_t FIFO_INT_EN; /* Address Offset: 0x0028 */ + __IO uint32_t FIFO_INT_ST; /* Address Offset: 0x002C */ + uint32_t RESERVED0030[20]; /* Address Offset: 0x0030 */ + __O uint32_t FIFO_ENTRY; /* Address Offset: 0x0080 */ +}; +#endif /* __ASSEMBLY__ */ +/****************************************************************************************/ +/* */ +/* Module Address Section */ +/* */ +/****************************************************************************************/ +/* Memory Base */ +#define ICACHE_BASE 0x40000000U /* ICACHE base address */ +#define DCACHE_BASE 0x40004000U /* DCACHE base address */ +#define CRU_BASE 0x40050000U /* CRU base address */ +#define GRF_BASE 0x400B0000U /* GRF base address */ +#define MBOX0_BASE 0x40100000U /* MBOX0 base address */ +#define MBOX1_BASE 0x40110000U /* MBOX1 base address */ +#define MBOX2_BASE 0x40120000U /* MBOX2 base address */ +#define PMU_BASE 0x40130000U /* PMU base address */ +#define DMA_BASE 0x401C0000U /* DMA base address */ +#define ACDCDIG_BASE 0x40300000U /* ACDCDIG base address */ +#define UART0_BASE 0x40800000U /* UART0 base address */ +#define UART1_BASE 0x40810000U /* UART1 base address */ +#define UART2_BASE 0x40820000U /* UART2 base address */ +#define PWM0_BASE 0x40880000U /* PWM0 base address */ +#define TIMER0_BASE 0x40900000U /* TIMER0 base address */ +#define TIMER1_BASE 0x40900020U /* TIMER1 base address */ +#define TIMER2_BASE 0x40900040U /* TIMER2 base address */ +#define TIMER3_BASE 0x40900060U /* TIMER3 base address */ +#define TIMER4_BASE 0x40900080U /* TIMER4 base address */ +#define TIMER5_BASE 0x409000A0U /* TIMER5 base address */ +#define WDT_BASE 0x40A00000U /* WDT base address */ +#define I2C0_BASE 0x40B00000U /* I2C0 base address */ +#define I2C1_BASE 0x40B10000U /* I2C1 base address */ +#define I2C2_BASE 0x40B20000U /* I2C2 base address */ +#define SPI2APB_BASE 0x40C00000U /* SPI2APB base address */ +#define SPI1_BASE 0x40C10000U /* SPI1 base address */ +#define SPI2_BASE 0x40C20000U /* SPI2 base address */ +#define FSPI0_BASE 0x40C80000U /* FSPI0 base address */ +#define MMC_BASE 0x40C90000U /* MMC base address */ +#define FSPI1_BASE 0x40CA0000U /* FSPI1 base address */ +#define GPIO0_BASE 0x40D00000U /* GPIO0 base address */ +#define GPIO1_BASE 0x40D10000U /* GPIO1 base address */ +#define KEY_CTRL_BASE 0x40E00000U /* KEY_CTRL base address */ +#define PDM0_BASE 0x41000000U /* PDM0 base address */ +#define I2STDM0_BASE 0x41010000U /* I2STDM0 base address */ +#define VAD_BASE 0x41020000U /* VAD base address */ +#define I2STDM1_BASE 0x41030000U /* I2STDM1 base address */ +#define VOP_BASE 0x41100000U /* VOP base address */ +#define DSI_BASE 0x41110000U /* DSI base address */ +#define VICAP_BASE 0x41120000U /* VICAP base address */ +#define AUDIOPWM_BASE 0x41200000U /* AUDIOPWM base address */ +/****************************************************************************************/ +/* */ +/* Module Variable Section */ +/* */ +/****************************************************************************************/ +/* Module Variable Define */ + +#define ICACHE ((struct ICACHE_REG *) ICACHE_BASE) +#define DCACHE ((struct DCACHE_REG *) DCACHE_BASE) +#define CRU ((struct CRU_REG *) CRU_BASE) +#define GRF ((struct GRF_REG *) GRF_BASE) +#define MBOX0 ((struct MBOX_REG *) MBOX0_BASE) +#define MBOX1 ((struct MBOX_REG *) MBOX1_BASE) +#define MBOX2 ((struct MBOX_REG *) MBOX2_BASE) +#define PMU ((struct PMU_REG *) PMU_BASE) +#define DMA ((struct DMA_REG *) DMA_BASE) +#define ACDCDIG ((struct ACDCDIG_REG *) ACDCDIG_BASE) +#define UART0 ((struct UART_REG *) UART0_BASE) +#define UART1 ((struct UART_REG *) UART1_BASE) +#define UART2 ((struct UART_REG *) UART2_BASE) +#define PWM0 ((struct PWM_REG *) PWM0_BASE) +#define TIMER0 ((struct TIMER_REG *) TIMER0_BASE) +#define TIMER1 ((struct TIMER_REG *) TIMER1_BASE) +#define TIMER2 ((struct TIMER_REG *) TIMER2_BASE) +#define TIMER3 ((struct TIMER_REG *) TIMER3_BASE) +#define TIMER4 ((struct TIMER_REG *) TIMER4_BASE) +#define TIMER5 ((struct TIMER_REG *) TIMER5_BASE) +#define WDT ((struct WDT_REG *) WDT_BASE) +#define I2C0 ((struct I2C_REG *) I2C0_BASE) +#define I2C1 ((struct I2C_REG *) I2C1_BASE) +#define I2C2 ((struct I2C_REG *) I2C2_BASE) +#define SPI2APB ((struct SPI2APB_REG *) SPI2APB_BASE) +#define SPI1 ((struct SPI_REG *) SPI1_BASE) +#define SPI2 ((struct SPI_REG *) SPI2_BASE) +#define FSPI0 ((struct FSPI_REG *) FSPI0_BASE) +#define MMC ((struct MMC_REG *) MMC_BASE) +#define FSPI1 ((struct FSPI_REG *) FSPI1_BASE) +#define GPIO0 ((struct GPIO_REG *) GPIO0_BASE) +#define GPIO1 ((struct GPIO_REG *) GPIO1_BASE) +#define KEY_CTRL ((struct KEY_CTRL_REG *) KEY_CTRL_BASE) +#define PDM0 ((struct PDM_REG *) PDM0_BASE) +#define I2STDM0 ((struct I2STDM_REG *) I2STDM0_BASE) +#define VAD ((struct VAD_REG *) VAD_BASE) +#define I2STDM1 ((struct I2STDM_REG *) I2STDM1_BASE) +#define VOP ((struct VOP_REG *) VOP_BASE) +#define DSI ((struct DSI_REG *) DSI_BASE) +#define VICAP ((struct VICAP_REG *) VICAP_BASE) +#define AUDIOPWM ((struct AUDIOPWM_REG *) AUDIOPWM_BASE) + +#define IS_ICACHE_INSTANCE(instance) ((instance) == ICACHE) +#define IS_DCACHE_INSTANCE(instance) ((instance) == DCACHE) +#define IS_CRU_INSTANCE(instance) ((instance) == CRU) +#define IS_GRF_INSTANCE(instance) ((instance) == GRF) +#define IS_PMU_INSTANCE(instance) ((instance) == PMU) +#define IS_DMA_INSTANCE(instance) ((instance) == DMA) +#define IS_ACDCDIG_INSTANCE(instance) ((instance) == ACDCDIG) +#define IS_WDT_INSTANCE(instance) ((instance) == WDT) +#define IS_SPI2APB_INSTANCE(instance) ((instance) == SPI2APB) +#define IS_MMC_INSTANCE(instance) ((instance) == MMC) +#define IS_KEY_CTRL_INSTANCE(instance) ((instance) == KEY_CTRL) +#define IS_VAD_INSTANCE(instance) ((instance) == VAD) +#define IS_VOP_INSTANCE(instance) ((instance) == VOP) +#define IS_DSI_INSTANCE(instance) ((instance) == DSI) +#define IS_VICAP_INSTANCE(instance) ((instance) == VICAP) +#define IS_AUDIOPWM_INSTANCE(instance) ((instance) == AUDIOPWM) +#define IS_MBOX_INSTANCE(instance) (((instance) == MBOX0) || ((instance) == MBOX1) || ((instance) == MBOX2)) +#define IS_UART_INSTANCE(instance) (((instance) == UART0) || ((instance) == UART1) || ((instance) == UART2)) +#define IS_PWM_INSTANCE(instance) ((instance) == PWM0) +#define IS_TIMER_INSTANCE(instance) (((instance) == TIMER0) || ((instance) == TIMER1) || ((instance) == TIMER2) || ((instance) == TIMER3) || ((instance) == TIMER4) || ((instance) == TIMER5)) +#define IS_I2C_INSTANCE(instance) (((instance) == I2C0) || ((instance) == I2C1) || ((instance) == I2C2)) +#define IS_SPI_INSTANCE(instance) (((instance) == SPI1) || ((instance) == SPI2)) +#define IS_FSPI_INSTANCE(instance) (((instance) == FSPI0) || ((instance) == FSPI1)) +#define IS_GPIO_INSTANCE(instance) (((instance) == GPIO0) || ((instance) == GPIO1)) +#define IS_PDM_INSTANCE(instance) ((instance) == PDM0) +#define IS_I2STDM_INSTANCE(instance) (((instance) == I2STDM0) || ((instance) == I2STDM1)) +/****************************************************************************************/ +/* */ +/* Register Bitmap Section */ +/* */ +/****************************************************************************************/ +/*****************************************ICACHE*****************************************/ +/* CACHE_CTRL */ +#define ICACHE_CACHE_CTRL_OFFSET (0x0U) +#define ICACHE_CACHE_CTRL_CACHE_EN_SHIFT (0U) +#define ICACHE_CACHE_CTRL_CACHE_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_EN_SHIFT) /* 0x00000001 */ +#define ICACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT (1U) +#define ICACHE_CACHE_CTRL_CACHE_WT_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT) /* 0x00000002 */ +#define ICACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT (2U) +#define ICACHE_CACHE_CTRL_CACHE_HB_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT) /* 0x00000004 */ +#define ICACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT (3U) +#define ICACHE_CACHE_CTRL_CACHE_STB_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT) /* 0x00000008 */ +#define ICACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT (4U) +#define ICACHE_CACHE_CTRL_CACHE_FLUSH_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT) /* 0x00000010 */ +#define ICACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT (5U) +#define ICACHE_CACHE_CTRL_CACHE_PMU_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT) /* 0x00000020 */ +#define ICACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT (6U) +#define ICACHE_CACHE_CTRL_CACHE_BYPASS_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT) /* 0x00000040 */ +#define ICACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT (7U) +#define ICACHE_CACHE_CTRL_STB_TIMEOUT_EN_MASK (0x1U << ICACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT) /* 0x00000080 */ +#define ICACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT (8U) +#define ICACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_MASK (0x7U << ICACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT) /* 0x00000700 */ +#define ICACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT (12U) +#define ICACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT) /* 0x00001000 */ +#define ICACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT (13U) +#define ICACHE_CACHE_CTRL_CACHE_PF_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT) /* 0x00002000 */ +/* CACHE_MAINTAIN0 */ +#define ICACHE_CACHE_MAINTAIN0_OFFSET (0x4U) +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT (0U) +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK (0x1U << ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT) /* 0x00000001 */ +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT (1U) +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_CMD_MASK (0x3U << ICACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT) /* 0x00000006 */ +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT (5U) +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_MASK (0x7FFFFFFU << ICACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT) /* 0xFFFFFFE0 */ +/* CACHE_MAINTAIN1 */ +#define ICACHE_CACHE_MAINTAIN1_OFFSET (0x8U) +#define ICACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT (0U) +#define ICACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_MASK (0xFFFFU << ICACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT) /* 0x0000FFFF */ +/* STB_TIMEOUT_CTRL */ +#define ICACHE_STB_TIMEOUT_CTRL_OFFSET (0xCU) +#define ICACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT (0U) +#define ICACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_MASK (0x7FFFFU << ICACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT) /* 0x0007FFFF */ +/* CACHE_INT_EN */ +#define ICACHE_CACHE_INT_EN_OFFSET (0x20U) +#define ICACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT (0U) +#define ICACHE_CACHE_INT_EN_ERR_RECORD_EN_MASK (0x1U << ICACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT) /* 0x00000001 */ +/* CACHE_INT_ST */ +#define ICACHE_CACHE_INT_ST_OFFSET (0x24U) +#define ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT (0U) +#define ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_MASK (0x1U << ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT) /* 0x00000001 */ +/* CACHE_ERR_HADDR */ +#define ICACHE_CACHE_ERR_HADDR_OFFSET (0x28U) +#define ICACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT (0U) +#define ICACHE_CACHE_ERR_HADDR_STATUS_HADDR_MASK (0x1U << ICACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT) /* 0x00000001 */ +/* CACHE_STATUS */ +#define ICACHE_CACHE_STATUS_OFFSET (0x30U) +#define ICACHE_CACHE_STATUS (0x0U) +#define ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT (0U) +#define ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK (0x1U << ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT) /* 0x00000001 */ +#define ICACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT (1U) +#define ICACHE_CACHE_STATUS_CACHE_M_BUSY_MASK (0x1U << ICACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT) /* 0x00000002 */ +#define ICACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT (2U) +#define ICACHE_CACHE_STATUS_CACHE_FLUSH_DONE_MASK (0x1U << ICACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT) /* 0x00000004 */ +/* PMU_RD_NUM_CNT */ +#define ICACHE_PMU_RD_NUM_CNT_OFFSET (0x40U) +#define ICACHE_PMU_RD_NUM_CNT (0x0U) +#define ICACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT (0U) +#define ICACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_NUM_CNT */ +#define ICACHE_PMU_WR_NUM_CNT_OFFSET (0x44U) +#define ICACHE_PMU_WR_NUM_CNT (0x0U) +#define ICACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT (0U) +#define ICACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_SRAM_RD_HIT_CNT */ +#define ICACHE_PMU_SRAM_RD_HIT_CNT_OFFSET (0x48U) +#define ICACHE_PMU_SRAM_RD_HIT_CNT (0x0U) +#define ICACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT (0U) +#define ICACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_HB_RD_HIT_CNT */ +#define ICACHE_PMU_HB_RD_HIT_CNT_OFFSET (0x4CU) +#define ICACHE_PMU_HB_RD_HIT_CNT (0x0U) +#define ICACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT (0U) +#define ICACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_STB_RD_HIT_CNT */ +#define ICACHE_PMU_STB_RD_HIT_CNT_OFFSET (0x50U) +#define ICACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT (0U) +#define ICACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_HIT_CNT */ +#define ICACHE_PMU_RD_HIT_CNT_OFFSET (0x54U) +#define ICACHE_PMU_RD_HIT_CNT (0x0U) +#define ICACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT (0U) +#define ICACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_HIT_CNT */ +#define ICACHE_PMU_WR_HIT_CNT_OFFSET (0x58U) +#define ICACHE_PMU_WR_HIT_CNT (0x0U) +#define ICACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT (0U) +#define ICACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_MISS_PENALTY_CNT */ +#define ICACHE_PMU_RD_MISS_PENALTY_CNT_OFFSET (0x5CU) +#define ICACHE_PMU_RD_MISS_PENALTY_CNT (0x0U) +#define ICACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT (0U) +#define ICACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_MISS_PENALTY_CNT */ +#define ICACHE_PMU_WR_MISS_PENALTY_CNT_OFFSET (0x60U) +#define ICACHE_PMU_WR_MISS_PENALTY_CNT (0x0U) +#define ICACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT (0U) +#define ICACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_LAT_CNT */ +#define ICACHE_PMU_RD_LAT_CNT_OFFSET (0x64U) +#define ICACHE_PMU_RD_LAT_CNT (0x0U) +#define ICACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) +#define ICACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_LAT_CNT */ +#define ICACHE_PMU_WR_LAT_CNT_OFFSET (0x68U) +#define ICACHE_PMU_WR_LAT_CNT (0x0U) +#define ICACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) +#define ICACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* REVISION */ +#define ICACHE_REVISION_OFFSET (0xF0U) +#define ICACHE_REVISION_REVISION_SHIFT (0U) +#define ICACHE_REVISION_REVISION_MASK (0xFFFFFFFFU << ICACHE_REVISION_REVISION_SHIFT) /* 0xFFFFFFFF */ +/*****************************************DCACHE*****************************************/ +/* CACHE_CTRL */ +#define DCACHE_CACHE_CTRL_OFFSET (0x0U) +#define DCACHE_CACHE_CTRL_CACHE_EN_SHIFT (0U) +#define DCACHE_CACHE_CTRL_CACHE_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_EN_SHIFT) /* 0x00000001 */ +#define DCACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT (1U) +#define DCACHE_CACHE_CTRL_CACHE_WT_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT) /* 0x00000002 */ +#define DCACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT (2U) +#define DCACHE_CACHE_CTRL_CACHE_HB_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT) /* 0x00000004 */ +#define DCACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT (3U) +#define DCACHE_CACHE_CTRL_CACHE_STB_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT) /* 0x00000008 */ +#define DCACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT (4U) +#define DCACHE_CACHE_CTRL_CACHE_FLUSH_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT) /* 0x00000010 */ +#define DCACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT (5U) +#define DCACHE_CACHE_CTRL_CACHE_PMU_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT) /* 0x00000020 */ +#define DCACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT (6U) +#define DCACHE_CACHE_CTRL_CACHE_BYPASS_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT) /* 0x00000040 */ +#define DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT (7U) +#define DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_MASK (0x1U << DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT) /* 0x00000080 */ +#define DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT (8U) +#define DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_MASK (0x7U << DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT) /* 0x00000700 */ +#define DCACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT (12U) +#define DCACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT) /* 0x00001000 */ +#define DCACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT (13U) +#define DCACHE_CACHE_CTRL_CACHE_PF_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT) /* 0x00002000 */ +/* CACHE_MAINTAIN0 */ +#define DCACHE_CACHE_MAINTAIN0_OFFSET (0x4U) +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT (0U) +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK (0x1U << DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT) /* 0x00000001 */ +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT (1U) +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_CMD_MASK (0x3U << DCACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT) /* 0x00000006 */ +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT (5U) +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_MASK (0x7FFFFFFU << DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT) /* 0xFFFFFFE0 */ +/* CACHE_MAINTAIN1 */ +#define DCACHE_CACHE_MAINTAIN1_OFFSET (0x8U) +#define DCACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT (0U) +#define DCACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_MASK (0xFFFFU << DCACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT) /* 0x0000FFFF */ +/* STB_TIMEOUT_CTRL */ +#define DCACHE_STB_TIMEOUT_CTRL_OFFSET (0xCU) +#define DCACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT (0U) +#define DCACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_MASK (0x7FFFFU << DCACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT) /* 0x0007FFFF */ +/* CACHE_INT_EN */ +#define DCACHE_CACHE_INT_EN_OFFSET (0x20U) +#define DCACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT (0U) +#define DCACHE_CACHE_INT_EN_ERR_RECORD_EN_MASK (0x1U << DCACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT) /* 0x00000001 */ +/* CACHE_INT_ST */ +#define DCACHE_CACHE_INT_ST_OFFSET (0x24U) +#define DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT (0U) +#define DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_MASK (0x1U << DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT) /* 0x00000001 */ +/* CACHE_ERR_HADDR */ +#define DCACHE_CACHE_ERR_HADDR_OFFSET (0x28U) +#define DCACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT (0U) +#define DCACHE_CACHE_ERR_HADDR_STATUS_HADDR_MASK (0x1U << DCACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT) /* 0x00000001 */ +/* CACHE_STATUS */ +#define DCACHE_CACHE_STATUS_OFFSET (0x30U) +#define DCACHE_CACHE_STATUS (0x0U) +#define DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT (0U) +#define DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK (0x1U << DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT) /* 0x00000001 */ +#define DCACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT (1U) +#define DCACHE_CACHE_STATUS_CACHE_M_BUSY_MASK (0x1U << DCACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT) /* 0x00000002 */ +#define DCACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT (2U) +#define DCACHE_CACHE_STATUS_CACHE_FLUSH_DONE_MASK (0x1U << DCACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT) /* 0x00000004 */ +/* PMU_RD_NUM_CNT */ +#define DCACHE_PMU_RD_NUM_CNT_OFFSET (0x40U) +#define DCACHE_PMU_RD_NUM_CNT (0x0U) +#define DCACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT (0U) +#define DCACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_NUM_CNT */ +#define DCACHE_PMU_WR_NUM_CNT_OFFSET (0x44U) +#define DCACHE_PMU_WR_NUM_CNT (0x0U) +#define DCACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT (0U) +#define DCACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_SRAM_RD_HIT_CNT */ +#define DCACHE_PMU_SRAM_RD_HIT_CNT_OFFSET (0x48U) +#define DCACHE_PMU_SRAM_RD_HIT_CNT (0x0U) +#define DCACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT (0U) +#define DCACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_HB_RD_HIT_CNT */ +#define DCACHE_PMU_HB_RD_HIT_CNT_OFFSET (0x4CU) +#define DCACHE_PMU_HB_RD_HIT_CNT (0x0U) +#define DCACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT (0U) +#define DCACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_STB_RD_HIT_CNT */ +#define DCACHE_PMU_STB_RD_HIT_CNT_OFFSET (0x50U) +#define DCACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT (0U) +#define DCACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_HIT_CNT */ +#define DCACHE_PMU_RD_HIT_CNT_OFFSET (0x54U) +#define DCACHE_PMU_RD_HIT_CNT (0x0U) +#define DCACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT (0U) +#define DCACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_HIT_CNT */ +#define DCACHE_PMU_WR_HIT_CNT_OFFSET (0x58U) +#define DCACHE_PMU_WR_HIT_CNT (0x0U) +#define DCACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT (0U) +#define DCACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_MISS_PENALTY_CNT */ +#define DCACHE_PMU_RD_MISS_PENALTY_CNT_OFFSET (0x5CU) +#define DCACHE_PMU_RD_MISS_PENALTY_CNT (0x0U) +#define DCACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT (0U) +#define DCACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_MISS_PENALTY_CNT */ +#define DCACHE_PMU_WR_MISS_PENALTY_CNT_OFFSET (0x60U) +#define DCACHE_PMU_WR_MISS_PENALTY_CNT (0x0U) +#define DCACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT (0U) +#define DCACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_LAT_CNT */ +#define DCACHE_PMU_RD_LAT_CNT_OFFSET (0x64U) +#define DCACHE_PMU_RD_LAT_CNT (0x0U) +#define DCACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) +#define DCACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_LAT_CNT */ +#define DCACHE_PMU_WR_LAT_CNT_OFFSET (0x68U) +#define DCACHE_PMU_WR_LAT_CNT (0x0U) +#define DCACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) +#define DCACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* REVISION */ +#define DCACHE_REVISION_OFFSET (0xF0U) +#define DCACHE_REVISION_REVISION_SHIFT (0U) +#define DCACHE_REVISION_REVISION_MASK (0xFFFFFFFFU << DCACHE_REVISION_REVISION_SHIFT) /* 0xFFFFFFFF */ +/******************************************CRU*******************************************/ +/* GPLL_CON0 */ +#define CRU_GPLL_CON0_OFFSET (0x0) +#define CRU_GPLL_CON0_FBDIV_SHIFT (0U) +#define CRU_GPLL_CON0_FBDIV_MASK (0xFFFU << CRU_GPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */ +#define CRU_GPLL_CON0_POSTDIV1_SHIFT (12U) +#define CRU_GPLL_CON0_POSTDIV1_MASK (0x7U << CRU_GPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */ +#define CRU_GPLL_CON0_BYPASS_SHIFT (15U) +#define CRU_GPLL_CON0_BYPASS_MASK (0x1U << CRU_GPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */ +/* GPLL_CON1 */ +#define CRU_GPLL_CON1_OFFSET (0x4) +#define CRU_GPLL_CON1_REFDIV_SHIFT (0U) +#define CRU_GPLL_CON1_REFDIV_MASK (0x3FU << CRU_GPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */ +#define CRU_GPLL_CON1_POSTDIV2_SHIFT (6U) +#define CRU_GPLL_CON1_POSTDIV2_MASK (0x7U << CRU_GPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */ +#define CRU_GPLL_CON1_PLL_LOCK_SHIFT (10U) +#define CRU_GPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_GPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define CRU_GPLL_CON1_DSMPD_SHIFT (12U) +#define CRU_GPLL_CON1_DSMPD_MASK (0x1U << CRU_GPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */ +#define CRU_GPLL_CON1_PLLPD0_SHIFT (13U) +#define CRU_GPLL_CON1_PLLPD0_MASK (0x1U << CRU_GPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */ +#define CRU_GPLL_CON1_PLLPD1_SHIFT (14U) +#define CRU_GPLL_CON1_PLLPD1_MASK (0x1U << CRU_GPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */ +#define CRU_GPLL_CON1_PLLPDSEL_SHIFT (15U) +#define CRU_GPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_GPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */ +/* GPLL_CON2 */ +#define CRU_GPLL_CON2_OFFSET (0x8) +#define CRU_GPLL_CON2_FRACDIV_SHIFT (0U) +#define CRU_GPLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_GPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */ +#define CRU_GPLL_CON2_DACPD_SHIFT (24U) +#define CRU_GPLL_CON2_DACPD_MASK (0x1U << CRU_GPLL_CON2_DACPD_SHIFT) /* 0x01000000 */ +#define CRU_GPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U) +#define CRU_GPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_GPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */ +#define CRU_GPLL_CON2_FOUTVCOPD_SHIFT (26U) +#define CRU_GPLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_GPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */ +#define CRU_GPLL_CON2_FOUT4PHASEPD_SHIFT (27U) +#define CRU_GPLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_GPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */ +/* GPLL_CON3 */ +#define CRU_GPLL_CON3_OFFSET (0xC) +#define CRU_GPLL_CON3_SSMOD_BP_SHIFT (0U) +#define CRU_GPLL_CON3_SSMOD_BP_MASK (0x1U << CRU_GPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */ +#define CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U) +#define CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */ +#define CRU_GPLL_CON3_SSMOD_RESET_SHIFT (2U) +#define CRU_GPLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_GPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */ +#define CRU_GPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U) +#define CRU_GPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_GPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */ +#define CRU_GPLL_CON3_SSMOD_DIVVAL_SHIFT (4U) +#define CRU_GPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_GPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */ +#define CRU_GPLL_CON3_SSMOD_SPREAD_SHIFT (8U) +#define CRU_GPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_GPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */ +/* GPLL_CON4 */ +#define CRU_GPLL_CON4_OFFSET (0x10) +#define CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U) +#define CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */ +#define CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U) +#define CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */ +/* CPLL_CON0 */ +#define CRU_CPLL_CON0_OFFSET (0x20) +#define CRU_CPLL_CON0_FBDIV_SHIFT (0U) +#define CRU_CPLL_CON0_FBDIV_MASK (0xFFFU << CRU_CPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */ +#define CRU_CPLL_CON0_POSTDIV1_SHIFT (12U) +#define CRU_CPLL_CON0_POSTDIV1_MASK (0x7U << CRU_CPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */ +#define CRU_CPLL_CON0_BYPASS_SHIFT (15U) +#define CRU_CPLL_CON0_BYPASS_MASK (0x1U << CRU_CPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */ +/* CPLL_CON1 */ +#define CRU_CPLL_CON1_OFFSET (0x24) +#define CRU_CPLL_CON1_REFDIV_SHIFT (0U) +#define CRU_CPLL_CON1_REFDIV_MASK (0x3FU << CRU_CPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */ +#define CRU_CPLL_CON1_POSTDIV2_SHIFT (6U) +#define CRU_CPLL_CON1_POSTDIV2_MASK (0x7U << CRU_CPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */ +#define CRU_CPLL_CON1_PLL_LOCK_SHIFT (10U) +#define CRU_CPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_CPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define CRU_CPLL_CON1_DSMPD_SHIFT (12U) +#define CRU_CPLL_CON1_DSMPD_MASK (0x1U << CRU_CPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */ +#define CRU_CPLL_CON1_PLLPD0_SHIFT (13U) +#define CRU_CPLL_CON1_PLLPD0_MASK (0x1U << CRU_CPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */ +#define CRU_CPLL_CON1_PLLPD1_SHIFT (14U) +#define CRU_CPLL_CON1_PLLPD1_MASK (0x1U << CRU_CPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */ +#define CRU_CPLL_CON1_PLLPDSEL_SHIFT (15U) +#define CRU_CPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_CPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */ +/* CPLL_CON2 */ +#define CRU_CPLL_CON2_OFFSET (0x28) +#define CRU_CPLL_CON2_FRACDIV_SHIFT (0U) +#define CRU_CPLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_CPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */ +#define CRU_CPLL_CON2_DACPD_SHIFT (24U) +#define CRU_CPLL_CON2_DACPD_MASK (0x1U << CRU_CPLL_CON2_DACPD_SHIFT) /* 0x01000000 */ +#define CRU_CPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U) +#define CRU_CPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_CPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */ +#define CRU_CPLL_CON2_FOUTVCOPD_SHIFT (26U) +#define CRU_CPLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_CPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */ +#define CRU_CPLL_CON2_FOUT4PHASEPD_SHIFT (27U) +#define CRU_CPLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_CPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */ +/* SPLL_CON0 */ +#define CRU_SPLL_CON0_OFFSET (0x40) +#define CRU_SPLL_CON0_CLKOD_SHIFT (0U) +#define CRU_SPLL_CON0_CLKOD_MASK (0xFU << CRU_SPLL_CON0_CLKOD_SHIFT) /* 0x0000000F */ +#define CRU_SPLL_CON0_CLKR_SHIFT (8U) +#define CRU_SPLL_CON0_CLKR_MASK (0x3FU << CRU_SPLL_CON0_CLKR_SHIFT) /* 0x00003F00 */ +#define CRU_SPLL_CON0_CLKOD_MASK_SHIFT (16U) +#define CRU_SPLL_CON0_CLKOD_MASK_MASK (0xFU << CRU_SPLL_CON0_CLKOD_MASK_SHIFT) /* 0x000F0000 */ +#define CRU_SPLL_CON0_CLKR_MASK_SHIFT (24U) +#define CRU_SPLL_CON0_CLKR_MASK_MASK (0x3FU << CRU_SPLL_CON0_CLKR_MASK_SHIFT) /* 0x3F000000 */ +/* SPLL_CON1 */ +#define CRU_SPLL_CON1_OFFSET (0x44) +#define CRU_SPLL_CON1_CLKF_SHIFT (0U) +#define CRU_SPLL_CON1_CLKF_MASK (0x1FFFU << CRU_SPLL_CON1_CLKF_SHIFT) /* 0x00001FFF */ +#define CRU_SPLL_CON1_CLKF_MASK_SHIFT (16U) +#define CRU_SPLL_CON1_CLKF_MASK_MASK (0x1FFFU << CRU_SPLL_CON1_CLKF_MASK_SHIFT) /* 0x1FFF0000 */ +/* SPLL_CON2 */ +#define CRU_SPLL_CON2_OFFSET (0x48) +#define CRU_SPLL_CON2_BWADJ_SHIFT (0U) +#define CRU_SPLL_CON2_BWADJ_MASK (0xFFFU << CRU_SPLL_CON2_BWADJ_SHIFT) /* 0x00000FFF */ +#define CRU_SPLL_CON2_BWADJ_MASK_SHIFT (16U) +#define CRU_SPLL_CON2_BWADJ_MASK_MASK (0xFFFU << CRU_SPLL_CON2_BWADJ_MASK_SHIFT) /* 0x0FFF0000 */ +/* SPLL_CON3 */ +#define CRU_SPLL_CON3_OFFSET (0x4C) +#define CRU_SPLL_CON3_BYPASS_SHIFT (0U) +#define CRU_SPLL_CON3_BYPASS_MASK (0x1U << CRU_SPLL_CON3_BYPASS_SHIFT) /* 0x00000001 */ +#define CRU_SPLL_CON3_POWER_DOWN_SHIFT (1U) +#define CRU_SPLL_CON3_POWER_DOWN_MASK (0x1U << CRU_SPLL_CON3_POWER_DOWN_SHIFT) /* 0x00000002 */ +#define CRU_SPLL_CON3_FASTEN_SHIFT (2U) +#define CRU_SPLL_CON3_FASTEN_MASK (0x1U << CRU_SPLL_CON3_FASTEN_SHIFT) /* 0x00000004 */ +#define CRU_SPLL_CON3_ENSAT_SHIFT (3U) +#define CRU_SPLL_CON3_ENSAT_MASK (0x1U << CRU_SPLL_CON3_ENSAT_SHIFT) /* 0x00000008 */ +#define CRU_SPLL_CON3_TEST_SHIFT (4U) +#define CRU_SPLL_CON3_TEST_MASK (0x1U << CRU_SPLL_CON3_TEST_SHIFT) /* 0x00000010 */ +#define CRU_SPLL_CON3_RESET_SHIFT (5U) +#define CRU_SPLL_CON3_RESET_MASK (0x1U << CRU_SPLL_CON3_RESET_SHIFT) /* 0x00000020 */ +#define CRU_SPLL_CON3_LOCK_OUT_DISALBE_SHIFT (6U) +#define CRU_SPLL_CON3_LOCK_OUT_DISALBE_MASK (0x1U << CRU_SPLL_CON3_LOCK_OUT_DISALBE_SHIFT) /* 0x00000040 */ +#define CRU_SPLL_CON3_BYPASS_MASK_SHIFT (16U) +#define CRU_SPLL_CON3_BYPASS_MASK_MASK (0x1U << CRU_SPLL_CON3_BYPASS_MASK_SHIFT) /* 0x00010000 */ +#define CRU_SPLL_CON3_POWER_DOWN_MASK_SHIFT (17U) +#define CRU_SPLL_CON3_POWER_DOWN_MASK_MASK (0x1U << CRU_SPLL_CON3_POWER_DOWN_MASK_SHIFT) /* 0x00020000 */ +#define CRU_SPLL_CON3_FASTEN_MASK_SHIFT (18U) +#define CRU_SPLL_CON3_FASTEN_MASK_MASK (0x1U << CRU_SPLL_CON3_FASTEN_MASK_SHIFT) /* 0x00040000 */ +#define CRU_SPLL_CON3_ENSAT_MASK_SHIFT (19U) +#define CRU_SPLL_CON3_ENSAT_MASK_MASK (0x1U << CRU_SPLL_CON3_ENSAT_MASK_SHIFT) /* 0x00080000 */ +#define CRU_SPLL_CON3_TEST_MASK_SHIFT (20U) +#define CRU_SPLL_CON3_TEST_MASK_MASK (0x1U << CRU_SPLL_CON3_TEST_MASK_SHIFT) /* 0x00100000 */ +#define CRU_SPLL_CON3_RESET_MASK_SHIFT (21U) +#define CRU_SPLL_CON3_RESET_MASK_MASK (0x1U << CRU_SPLL_CON3_RESET_MASK_SHIFT) /* 0x00200000 */ +#define CRU_SPLL_CON3_LOCK_OUT_DISABLE_MASK_SHIFT (22U) +#define CRU_SPLL_CON3_LOCK_OUT_DISABLE_MASK_MASK (0x1U << CRU_SPLL_CON3_LOCK_OUT_DISABLE_MASK_SHIFT) /* 0x00400000 */ +/* CRU_MODE_CON00 */ +#define CRU_CRU_MODE_CON00_OFFSET (0x60) +#define CRU_CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT (0U) +#define CRU_CRU_MODE_CON00_CLK_GPLL_MODE_MASK (0x3U << CRU_CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT) /* 0x00000003 */ +#define CRU_CRU_MODE_CON00_CLK_CPLL_MODE_SHIFT (2U) +#define CRU_CRU_MODE_CON00_CLK_CPLL_MODE_MASK (0x3U << CRU_CRU_MODE_CON00_CLK_CPLL_MODE_SHIFT) /* 0x0000000C */ +/* CRU_CLKSEL_CON00 */ +#define CRU_CRU_CLKSEL_CON00_OFFSET (0x80) +#define CRU_CRU_CLKSEL_CON00_ACLK_DSP_S_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON00_ACLK_DSP_S_DIV_MASK (0x3FU << CRU_CRU_CLKSEL_CON00_ACLK_DSP_S_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CRU_CLKSEL_CON00_ACLK_DSP_S_SEL_SHIFT (6U) +#define CRU_CRU_CLKSEL_CON00_ACLK_DSP_S_SEL_MASK (0x3U << CRU_CRU_CLKSEL_CON00_ACLK_DSP_S_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CRU_CLKSEL_CON00_PCLK_DSP_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON00_PCLK_DSP_DIV_MASK (0x3FU << CRU_CRU_CLKSEL_CON00_PCLK_DSP_DIV_SHIFT) /* 0x00003F00 */ +/* CRU_CLKSEL_CON02 */ +#define CRU_CRU_CLKSEL_CON02_OFFSET (0x88) +#define CRU_CRU_CLKSEL_CON02_SCLK_SHRM_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON02_SCLK_SHRM_DIV_MASK (0xFU << CRU_CRU_CLKSEL_CON02_SCLK_SHRM_DIV_SHIFT) /* 0x0000000F */ +#define CRU_CRU_CLKSEL_CON02_SCLK_SHRM_SEL_SHIFT (4U) +#define CRU_CRU_CLKSEL_CON02_SCLK_SHRM_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON02_SCLK_SHRM_SEL_SHIFT) /* 0x00000010 */ +#define CRU_CRU_CLKSEL_CON02_PCLK_SHRM_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON02_PCLK_SHRM_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON02_PCLK_SHRM_DIV_SHIFT) /* 0x00001F00 */ +/* CRU_CLKSEL_CON03 */ +#define CRU_CRU_CLKSEL_CON03_OFFSET (0x8C) +#define CRU_CRU_CLKSEL_CON03_CLK_UART0_SRC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON03_CLK_UART0_SRC_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON03_CLK_UART0_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON03_CLK_UART0_SRC_SEL_SHIFT (5U) +#define CRU_CRU_CLKSEL_CON03_CLK_UART0_SRC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON03_CLK_UART0_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CRU_CLKSEL_CON03_SCLK_UART0_SEL_SHIFT (6U) +#define CRU_CRU_CLKSEL_CON03_SCLK_UART0_SEL_MASK (0x3U << CRU_CRU_CLKSEL_CON03_SCLK_UART0_SEL_SHIFT) /* 0x000000C0 */ +/* CRU_CLKSEL_CON04 */ +#define CRU_CRU_CLKSEL_CON04_OFFSET (0x90) +#define CRU_CRU_CLKSEL_CON04_CLK_UART0_FRAC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON04_CLK_UART0_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CRU_CLKSEL_CON04_CLK_UART0_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CRU_CLKSEL_CON05 */ +#define CRU_CRU_CLKSEL_CON05_OFFSET (0x94) +#define CRU_CRU_CLKSEL_CON05_CLK_UART1_SRC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON05_CLK_UART1_SRC_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON05_CLK_UART1_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON05_CLK_UART1_SRC_SEL_SHIFT (5U) +#define CRU_CRU_CLKSEL_CON05_CLK_UART1_SRC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON05_CLK_UART1_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CRU_CLKSEL_CON05_SCLK_UART1_SEL_SHIFT (6U) +#define CRU_CRU_CLKSEL_CON05_SCLK_UART1_SEL_MASK (0x3U << CRU_CRU_CLKSEL_CON05_SCLK_UART1_SEL_SHIFT) /* 0x000000C0 */ +/* CRU_CLKSEL_CON06 */ +#define CRU_CRU_CLKSEL_CON06_OFFSET (0x98) +#define CRU_CRU_CLKSEL_CON06_CLK_UART1_FRAC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON06_CLK_UART1_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CRU_CLKSEL_CON06_CLK_UART1_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CRU_CLKSEL_CON07 */ +#define CRU_CRU_CLKSEL_CON07_OFFSET (0x9C) +#define CRU_CRU_CLKSEL_CON07_CLK_UART2_SRC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON07_CLK_UART2_SRC_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON07_CLK_UART2_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON07_CLK_UART2_SRC_SEL_SHIFT (5U) +#define CRU_CRU_CLKSEL_CON07_CLK_UART2_SRC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON07_CLK_UART2_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CRU_CLKSEL_CON07_SCLK_UART2_SEL_SHIFT (6U) +#define CRU_CRU_CLKSEL_CON07_SCLK_UART2_SEL_MASK (0x3U << CRU_CRU_CLKSEL_CON07_SCLK_UART2_SEL_SHIFT) /* 0x000000C0 */ +/* CRU_CLKSEL_CON08 */ +#define CRU_CRU_CLKSEL_CON08_OFFSET (0xA0) +#define CRU_CRU_CLKSEL_CON08_CLK_UART2_FRAC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON08_CLK_UART2_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CRU_CLKSEL_CON08_CLK_UART2_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CRU_CLKSEL_CON13 */ +#define CRU_CRU_CLKSEL_CON13_OFFSET (0xB4) +#define CRU_CRU_CLKSEL_CON13_CLK_I2C0_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON13_CLK_I2C0_DIV_MASK (0xFU << CRU_CRU_CLKSEL_CON13_CLK_I2C0_DIV_SHIFT) /* 0x0000000F */ +#define CRU_CRU_CLKSEL_CON13_CLK_I2C1_DIV_SHIFT (4U) +#define CRU_CRU_CLKSEL_CON13_CLK_I2C1_DIV_MASK (0xFU << CRU_CRU_CLKSEL_CON13_CLK_I2C1_DIV_SHIFT) /* 0x000000F0 */ +#define CRU_CRU_CLKSEL_CON13_CLK_I2C2_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON13_CLK_I2C2_DIV_MASK (0xFU << CRU_CRU_CLKSEL_CON13_CLK_I2C2_DIV_SHIFT) /* 0x00000F00 */ +/* CRU_CLKSEL_CON14 */ +#define CRU_CRU_CLKSEL_CON14_OFFSET (0xB8) +#define CRU_CRU_CLKSEL_CON14_MCLK_PDM0_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON14_MCLK_PDM0_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON14_MCLK_PDM0_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON14_MCLK_PDM0_SEL_SHIFT (7U) +#define CRU_CRU_CLKSEL_CON14_MCLK_PDM0_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON14_MCLK_PDM0_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CRU_CLKSEL_CON14_HCLK_AUDIO_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON14_HCLK_AUDIO_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON14_HCLK_AUDIO_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CRU_CLKSEL_CON14_HCLK_AUDIO_SEL_SHIFT (15U) +#define CRU_CRU_CLKSEL_CON14_HCLK_AUDIO_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON14_HCLK_AUDIO_SEL_SHIFT) /* 0x00008000 */ +/* CRU_CLKSEL_CON15 */ +#define CRU_CRU_CLKSEL_CON15_OFFSET (0xBC) +#define CRU_CRU_CLKSEL_CON15_MCLK_PDM0_OUT_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON15_MCLK_PDM0_OUT_DIV_MASK (0xFFFFFFFFU << CRU_CRU_CLKSEL_CON15_MCLK_PDM0_OUT_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CRU_CLKSEL_CON16 */ +#define CRU_CRU_CLKSEL_CON16_OFFSET (0xC0) +#define CRU_CRU_CLKSEL_CON16_CLK_I2S8CH_SRC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON16_CLK_I2S8CH_SRC_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON16_CLK_I2S8CH_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON16_CLK_I2S8CH_SRC_SEL_SHIFT (5U) +#define CRU_CRU_CLKSEL_CON16_CLK_I2S8CH_SRC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON16_CLK_I2S8CH_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CRU_CLKSEL_CON16_MCLK_I2S8CH_SEL_SHIFT (6U) +#define CRU_CRU_CLKSEL_CON16_MCLK_I2S8CH_SEL_MASK (0x3U << CRU_CRU_CLKSEL_CON16_MCLK_I2S8CH_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CRU_CLKSEL_CON16_PCLK_AUDIO_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON16_PCLK_AUDIO_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON16_PCLK_AUDIO_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CRU_CLKSEL_CON16_PCLK_AUDIO_SEL_SHIFT (14U) +#define CRU_CRU_CLKSEL_CON16_PCLK_AUDIO_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON16_PCLK_AUDIO_SEL_SHIFT) /* 0x00004000 */ +#define CRU_CRU_CLKSEL_CON16_I2S_MCLKOUT_SEL_SHIFT (15U) +#define CRU_CRU_CLKSEL_CON16_I2S_MCLKOUT_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON16_I2S_MCLKOUT_SEL_SHIFT) /* 0x00008000 */ +/* CRU_CLKSEL_CON17 */ +#define CRU_CRU_CLKSEL_CON17_OFFSET (0xC4) +#define CRU_CRU_CLKSEL_CON17_CLK_I2S8CH_FRAC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON17_CLK_I2S8CH_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CRU_CLKSEL_CON17_CLK_I2S8CH_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CRU_CLKSEL_CON18 */ +#define CRU_CRU_CLKSEL_CON18_OFFSET (0xC8) +#define CRU_CRU_CLKSEL_CON18_ACLK_DMAC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON18_ACLK_DMAC_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON18_ACLK_DMAC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON18_ACLK_DMAC_SEL_SHIFT (7U) +#define CRU_CRU_CLKSEL_CON18_ACLK_DMAC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON18_ACLK_DMAC_SEL_SHIFT) /* 0x00000080 */ +/* CRU_CLKSEL_CON19 */ +#define CRU_CRU_CLKSEL_CON19_OFFSET (0xCC) +#define CRU_CRU_CLKSEL_CON19_ACLK_VOP_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON19_ACLK_VOP_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON19_ACLK_VOP_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON19_ACLK_VOP_SEL_SHIFT (7U) +#define CRU_CRU_CLKSEL_CON19_ACLK_VOP_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON19_ACLK_VOP_SEL_SHIFT) /* 0x00000080 */ +/* CRU_CLKSEL_CON20 */ +#define CRU_CRU_CLKSEL_CON20_OFFSET (0xD0) +#define CRU_CRU_CLKSEL_CON20_DCLK_VOP_S_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON20_DCLK_VOP_S_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON20_DCLK_VOP_S_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON20_DCLK_VOP_S_SEL_SHIFT (7U) +#define CRU_CRU_CLKSEL_CON20_DCLK_VOP_S_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON20_DCLK_VOP_S_SEL_SHIFT) /* 0x00000080 */ +/* CRU_CLKSEL_CON22 */ +#define CRU_CRU_CLKSEL_CON22_OFFSET (0xD8) +#define CRU_CRU_CLKSEL_CON22_OCC_SCAN_CLK_DPHYLANBYTE_SEL_SHIFT (6U) +#define CRU_CRU_CLKSEL_CON22_OCC_SCAN_CLK_DPHYLANBYTE_SEL_MASK (0x3U << CRU_CRU_CLKSEL_CON22_OCC_SCAN_CLK_DPHYLANBYTE_SEL_SHIFT) /* 0x000000C0 */ +/* CRU_CLKSEL_CON23 */ +#define CRU_CRU_CLKSEL_CON23_OFFSET (0xDC) +#define CRU_CRU_CLKSEL_CON23_OCC_SCAN_CLK_DPHYLANBYTE_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON23_OCC_SCAN_CLK_DPHYLANBYTE_DIV_MASK (0xFFU << CRU_CRU_CLKSEL_CON23_OCC_SCAN_CLK_DPHYLANBYTE_DIV_SHIFT) /* 0x000000FF */ +/* CRU_CLKSEL_CON24 */ +#define CRU_CRU_CLKSEL_CON24_OFFSET (0xE0) +#define CRU_CRU_CLKSEL_CON24_CLK_GPIO_DB0_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON24_CLK_GPIO_DB0_DIV_MASK (0x3FFU << CRU_CRU_CLKSEL_CON24_CLK_GPIO_DB0_DIV_SHIFT) /* 0x000003FF */ +/* CRU_CLKSEL_CON25 */ +#define CRU_CRU_CLKSEL_CON25_OFFSET (0xE4) +#define CRU_CRU_CLKSEL_CON25_CLK_GPIO_DB1_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON25_CLK_GPIO_DB1_DIV_MASK (0x3FFU << CRU_CRU_CLKSEL_CON25_CLK_GPIO_DB1_DIV_SHIFT) /* 0x000003FF */ +/* CRU_CLKSEL_CON27 */ +#define CRU_CRU_CLKSEL_CON27_OFFSET (0xEC) +#define CRU_CRU_CLKSEL_CON27_PCLK_ALIVE_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON27_PCLK_ALIVE_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON27_PCLK_ALIVE_DIV_SHIFT) /* 0x0000001F */ +/* CRU_CLKSEL_CON28 */ +#define CRU_CRU_CLKSEL_CON28_OFFSET (0xF0) +#define CRU_CRU_CLKSEL_CON28_HCLK_ALIVE_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON28_HCLK_ALIVE_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON28_HCLK_ALIVE_DIV_SHIFT) /* 0x0000001F */ +/* CRU_CLKSEL_CON30 */ +#define CRU_CRU_CLKSEL_CON30_OFFSET (0xF8) +#define CRU_CRU_CLKSEL_CON30_CLK_TESTOUT_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON30_CLK_TESTOUT_DIV_MASK (0xFFU << CRU_CRU_CLKSEL_CON30_CLK_TESTOUT_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CRU_CLKSEL_CON30_CLK_TESTOUT_SEL_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON30_CLK_TESTOUT_SEL_MASK (0xFU << CRU_CRU_CLKSEL_CON30_CLK_TESTOUT_SEL_SHIFT) /* 0x00000F00 */ +/* CRU_CLKSEL_CON31 */ +#define CRU_CRU_CLKSEL_CON31_OFFSET (0xFC) +#define CRU_CRU_CLKSEL_CON31_CLK_PDM_SAMP_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON31_CLK_PDM_SAMP_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON31_CLK_PDM_SAMP_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON31_CLK_PDM_SAMP_SEL_SHIFT (5U) +#define CRU_CRU_CLKSEL_CON31_CLK_PDM_SAMP_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON31_CLK_PDM_SAMP_SEL_SHIFT) /* 0x00000020 */ +/* CRU_CLKSEL_CON33 */ +#define CRU_CRU_CLKSEL_CON33_OFFSET (0x104) +#define CRU_CRU_CLKSEL_CON33_HCLK_M4_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON33_HCLK_M4_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON33_HCLK_M4_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON33_HCLK_M4_SEL_SHIFT (7U) +#define CRU_CRU_CLKSEL_CON33_HCLK_M4_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON33_HCLK_M4_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CRU_CLKSEL_CON33_CLK_SPI1_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON33_CLK_SPI1_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON33_CLK_SPI1_DIV_SHIFT) /* 0x00001F00 */ +/* CRU_CLKSEL_CON34 */ +#define CRU_CRU_CLKSEL_CON34_OFFSET (0x108) +#define CRU_CRU_CLKSEL_CON34_CLK_SPI2_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON34_CLK_SPI2_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON34_CLK_SPI2_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CRU_CLKSEL_CON34_SCLK_SFC_SEL_SHIFT (14U) +#define CRU_CRU_CLKSEL_CON34_SCLK_SFC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON34_SCLK_SFC_SEL_SHIFT) /* 0x00004000 */ +/* CRU_CLKSEL_CON35 */ +#define CRU_CRU_CLKSEL_CON35_OFFSET (0x10C) +#define CRU_CRU_CLKSEL_CON35_SCLK_SFC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON35_SCLK_SFC_DIV_MASK (0xFFU << CRU_CRU_CLKSEL_CON35_SCLK_SFC_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CRU_CLKSEL_CON35_CLK_SDIO_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON35_CLK_SDIO_DIV_MASK (0xFFU << CRU_CRU_CLKSEL_CON35_CLK_SDIO_DIV_SHIFT) /* 0x0000FF00 */ +/* CRU_CLKSEL_CON36 */ +#define CRU_CRU_CLKSEL_CON36_OFFSET (0x110) +#define CRU_CRU_CLKSEL_CON36_CLK_SDIO_SEL_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON36_CLK_SDIO_SEL_MASK (0x3U << CRU_CRU_CLKSEL_CON36_CLK_SDIO_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CRU_CLKSEL_CON36_PCLK_CIF_SRC_SEL_SHIFT (12U) +#define CRU_CRU_CLKSEL_CON36_PCLK_CIF_SRC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON36_PCLK_CIF_SRC_SEL_SHIFT) /* 0x00001000 */ +/* CRU_CLKSEL_CON37 */ +#define CRU_CRU_CLKSEL_CON37_OFFSET (0x114) +#define CRU_CRU_CLKSEL_CON37_CLK_AUDPWM_DF_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON37_CLK_AUDPWM_DF_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON37_CLK_AUDPWM_DF_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON37_CLK_AUDPWM_SEL_SHIFT (5U) +#define CRU_CRU_CLKSEL_CON37_CLK_AUDPWM_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON37_CLK_AUDPWM_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CRU_CLKSEL_CON37_CLK_AUDPWM_SRC_SEL_SHIFT (6U) +#define CRU_CRU_CLKSEL_CON37_CLK_AUDPWM_SRC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON37_CLK_AUDPWM_SRC_SEL_SHIFT) /* 0x00000040 */ +#define CRU_CRU_CLKSEL_CON37_I2S1_MCLKOUT_SEL_SHIFT (7U) +#define CRU_CRU_CLKSEL_CON37_I2S1_MCLKOUT_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON37_I2S1_MCLKOUT_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CRU_CLKSEL_CON37_CLK_I2S1_8CH_SRC_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON37_CLK_I2S1_8CH_SRC_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON37_CLK_I2S1_8CH_SRC_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CRU_CLKSEL_CON37_CLK_I2S1_8CH_SRC_SEL_SHIFT (13U) +#define CRU_CRU_CLKSEL_CON37_CLK_I2S1_8CH_SRC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON37_CLK_I2S1_8CH_SRC_SEL_SHIFT) /* 0x00002000 */ +#define CRU_CRU_CLKSEL_CON37_MCLK_I2S1_8CH_SEL_SHIFT (14U) +#define CRU_CRU_CLKSEL_CON37_MCLK_I2S1_8CH_SEL_MASK (0x3U << CRU_CRU_CLKSEL_CON37_MCLK_I2S1_8CH_SEL_SHIFT) /* 0x0000C000 */ +/* CRU_CLKSEL_CON38 */ +#define CRU_CRU_CLKSEL_CON38_OFFSET (0x118) +#define CRU_CRU_CLKSEL_CON38_CLK_I2S1_8CH_FRAC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON38_CLK_I2S1_8CH_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CRU_CLKSEL_CON38_CLK_I2S1_8CH_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CRU_CLKSEL_CON39 */ +#define CRU_CRU_CLKSEL_CON39_OFFSET (0x11C) +#define CRU_CRU_CLKSEL_CON39_CLK_PWM_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON39_CLK_PWM_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON39_CLK_PWM_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON39_CLK_PWM_SEL_SHIFT (5U) +#define CRU_CRU_CLKSEL_CON39_CLK_PWM_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON39_CLK_PWM_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CRU_CLKSEL_CON39_HCLK_LOGIC_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON39_HCLK_LOGIC_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON39_HCLK_LOGIC_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CRU_CLKSEL_CON39_HCLK_LOGIC_SEL_SHIFT (15U) +#define CRU_CRU_CLKSEL_CON39_HCLK_LOGIC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON39_HCLK_LOGIC_SEL_SHIFT) /* 0x00008000 */ +/* CRU_CLKSEL_CON40 */ +#define CRU_CRU_CLKSEL_CON40_OFFSET (0x120) +#define CRU_CRU_CLKSEL_CON40_PCLK_LOGIC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON40_PCLK_LOGIC_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON40_PCLK_LOGIC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON40_PCLK_LOGIC_SEL_SHIFT (7U) +#define CRU_CRU_CLKSEL_CON40_PCLK_LOGIC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON40_PCLK_LOGIC_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CRU_CLKSEL_CON40_ACLK_LOGIC_DIV_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON40_ACLK_LOGIC_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON40_ACLK_LOGIC_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CRU_CLKSEL_CON40_ACLK_LOGIC_SEL_SHIFT (15U) +#define CRU_CRU_CLKSEL_CON40_ACLK_LOGIC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON40_ACLK_LOGIC_SEL_SHIFT) /* 0x00008000 */ +/* CRU_CLKSEL_CON41 */ +#define CRU_CRU_CLKSEL_CON41_OFFSET (0x124) +#define CRU_CRU_CLKSEL_CON41_CLK_CIFOUT_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON41_CLK_CIFOUT_DIV_MASK (0x1FU << CRU_CRU_CLKSEL_CON41_CLK_CIFOUT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CRU_CLKSEL_CON41_CLK_CIFOUT_SEL_SHIFT (6U) +#define CRU_CRU_CLKSEL_CON41_CLK_CIFOUT_SEL_MASK (0x3U << CRU_CRU_CLKSEL_CON41_CLK_CIFOUT_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CRU_CLKSEL_CON41_CLK_USB2PHY_REF_FRAC_SEL_SHIFT (8U) +#define CRU_CRU_CLKSEL_CON41_CLK_USB2PHY_REF_FRAC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON41_CLK_USB2PHY_REF_FRAC_SEL_SHIFT) /* 0x00000100 */ +#define CRU_CRU_CLKSEL_CON41_CLK_USB2PHY_REF_SEL_SHIFT (9U) +#define CRU_CRU_CLKSEL_CON41_CLK_USB2PHY_REF_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON41_CLK_USB2PHY_REF_SEL_SHIFT) /* 0x00000200 */ +#define CRU_CRU_CLKSEL_CON41_CLK_DPHY_REF_FRAC_SEL_SHIFT (10U) +#define CRU_CRU_CLKSEL_CON41_CLK_DPHY_REF_FRAC_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON41_CLK_DPHY_REF_FRAC_SEL_SHIFT) /* 0x00000400 */ +#define CRU_CRU_CLKSEL_CON41_CLK_DPHY_REF_SEL_SHIFT (11U) +#define CRU_CRU_CLKSEL_CON41_CLK_DPHY_REF_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON41_CLK_DPHY_REF_SEL_SHIFT) /* 0x00000800 */ +/* CRU_CLKSEL_CON42 */ +#define CRU_CRU_CLKSEL_CON42_OFFSET (0x128) +#define CRU_CRU_CLKSEL_CON42_CLK_AUDPWM_FRAC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON42_CLK_AUDPWM_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CRU_CLKSEL_CON42_CLK_AUDPWM_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CRU_CLKSEL_CON43 */ +#define CRU_CRU_CLKSEL_CON43_OFFSET (0x12C) +#define CRU_CRU_CLKSEL_CON43_CLK_USB2PHY_REF_FRAC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON43_CLK_USB2PHY_REF_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CRU_CLKSEL_CON43_CLK_USB2PHY_REF_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CRU_CLKSEL_CON44 */ +#define CRU_CRU_CLKSEL_CON44_OFFSET (0x130) +#define CRU_CRU_CLKSEL_CON44_CLK_DPHY_REF_FRAC_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON44_CLK_DPHY_REF_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CRU_CLKSEL_CON44_CLK_DPHY_REF_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CRU_CLKSEL_CON46 */ +#define CRU_CRU_CLKSEL_CON46_OFFSET (0x138) +#define CRU_CRU_CLKSEL_CON46_SCLK_SFC1_SEL_SHIFT (14U) +#define CRU_CRU_CLKSEL_CON46_SCLK_SFC1_SEL_MASK (0x1U << CRU_CRU_CLKSEL_CON46_SCLK_SFC1_SEL_SHIFT) /* 0x00004000 */ +/* CRU_CLKSEL_CON47 */ +#define CRU_CRU_CLKSEL_CON47_OFFSET (0x13C) +#define CRU_CRU_CLKSEL_CON47_SCLK_SFC1_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON47_SCLK_SFC1_DIV_MASK (0xFFU << CRU_CRU_CLKSEL_CON47_SCLK_SFC1_DIV_SHIFT) /* 0x000000FF */ +/* CRU_CLKSEL_CON49 */ +#define CRU_CRU_CLKSEL_CON49_OFFSET (0x144) +#define CRU_CRU_CLKSEL_CON49_XIN_OSC0_DIV_DIV_SHIFT (0U) +#define CRU_CRU_CLKSEL_CON49_XIN_OSC0_DIV_DIV_MASK (0xFFFFFFFFU << CRU_CRU_CLKSEL_CON49_XIN_OSC0_DIV_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CRU_GATE_CON00 */ +#define CRU_CRU_GATE_CON00_OFFSET (0x180) +#define CRU_CRU_GATE_CON00_ACLK_DSP_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON00_ACLK_DSP_EN_MASK (0x1U << CRU_CRU_GATE_CON00_ACLK_DSP_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON00_ACLK_DSP_NIU_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON00_ACLK_DSP_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON00_ACLK_DSP_NIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON00_PCLK_DSP_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON00_PCLK_DSP_EN_MASK (0x1U << CRU_CRU_GATE_CON00_PCLK_DSP_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON00_PCLK_DSP_NIU_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON00_PCLK_DSP_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON00_PCLK_DSP_NIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON00_PCLK_DSP_GRF_EN_SHIFT (5U) +#define CRU_CRU_GATE_CON00_PCLK_DSP_GRF_EN_MASK (0x1U << CRU_CRU_GATE_CON00_PCLK_DSP_GRF_EN_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GATE_CON00_PCLK_WDT1_EN_SHIFT (6U) +#define CRU_CRU_GATE_CON00_PCLK_WDT1_EN_MASK (0x1U << CRU_CRU_GATE_CON00_PCLK_WDT1_EN_SHIFT) /* 0x00000040 */ +#define CRU_CRU_GATE_CON00_ACLK_DSP_S_EN_SHIFT (7U) +#define CRU_CRU_GATE_CON00_ACLK_DSP_S_EN_MASK (0x1U << CRU_CRU_GATE_CON00_ACLK_DSP_S_EN_SHIFT) /* 0x00000080 */ +/* CRU_GATE_CON01 */ +#define CRU_CRU_GATE_CON01_OFFSET (0x184) +#define CRU_CRU_GATE_CON01_SCLK_SHRM_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON01_SCLK_SHRM_EN_MASK (0x1U << CRU_CRU_GATE_CON01_SCLK_SHRM_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON01_ACLK_SHRM_NIU_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON01_ACLK_SHRM_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON01_ACLK_SHRM_NIU_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON01_PCLK_SHRM_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON01_PCLK_SHRM_EN_MASK (0x1U << CRU_CRU_GATE_CON01_PCLK_SHRM_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON01_PCLK_SHRM_NIU_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON01_PCLK_SHRM_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON01_PCLK_SHRM_NIU_EN_SHIFT) /* 0x00000008 */ +/* CRU_GATE_CON02 */ +#define CRU_CRU_GATE_CON02_OFFSET (0x188) +#define CRU_CRU_GATE_CON02_PCLK_UART0_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON02_PCLK_UART0_EN_MASK (0x1U << CRU_CRU_GATE_CON02_PCLK_UART0_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON02_PCLK_UART1_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON02_PCLK_UART1_EN_MASK (0x1U << CRU_CRU_GATE_CON02_PCLK_UART1_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON02_PCLK_UART2_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON02_PCLK_UART2_EN_MASK (0x1U << CRU_CRU_GATE_CON02_PCLK_UART2_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON02_CLK_UART0_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON02_CLK_UART0_EN_MASK (0x1U << CRU_CRU_GATE_CON02_CLK_UART0_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON02_CLK_UART0_FRAC_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON02_CLK_UART0_FRAC_EN_MASK (0x1U << CRU_CRU_GATE_CON02_CLK_UART0_FRAC_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON02_SCLK_UART0_EN_SHIFT (6U) +#define CRU_CRU_GATE_CON02_SCLK_UART0_EN_MASK (0x1U << CRU_CRU_GATE_CON02_SCLK_UART0_EN_SHIFT) /* 0x00000040 */ +#define CRU_CRU_GATE_CON02_CLK_UART1_EN_SHIFT (7U) +#define CRU_CRU_GATE_CON02_CLK_UART1_EN_MASK (0x1U << CRU_CRU_GATE_CON02_CLK_UART1_EN_SHIFT) /* 0x00000080 */ +#define CRU_CRU_GATE_CON02_CLK_UART1_FRAC_EN_SHIFT (8U) +#define CRU_CRU_GATE_CON02_CLK_UART1_FRAC_EN_MASK (0x1U << CRU_CRU_GATE_CON02_CLK_UART1_FRAC_EN_SHIFT) /* 0x00000100 */ +#define CRU_CRU_GATE_CON02_SCLK_UART1_EN_SHIFT (10U) +#define CRU_CRU_GATE_CON02_SCLK_UART1_EN_MASK (0x1U << CRU_CRU_GATE_CON02_SCLK_UART1_EN_SHIFT) /* 0x00000400 */ +#define CRU_CRU_GATE_CON02_CLK_UART2_EN_SHIFT (11U) +#define CRU_CRU_GATE_CON02_CLK_UART2_EN_MASK (0x1U << CRU_CRU_GATE_CON02_CLK_UART2_EN_SHIFT) /* 0x00000800 */ +#define CRU_CRU_GATE_CON02_CLK_UART2_FRAC_EN_SHIFT (12U) +#define CRU_CRU_GATE_CON02_CLK_UART2_FRAC_EN_MASK (0x1U << CRU_CRU_GATE_CON02_CLK_UART2_FRAC_EN_SHIFT) /* 0x00001000 */ +#define CRU_CRU_GATE_CON02_SCLK_UART2_EN_SHIFT (14U) +#define CRU_CRU_GATE_CON02_SCLK_UART2_EN_MASK (0x1U << CRU_CRU_GATE_CON02_SCLK_UART2_EN_SHIFT) /* 0x00004000 */ +/* CRU_GATE_CON04 */ +#define CRU_CRU_GATE_CON04_OFFSET (0x190) +#define CRU_CRU_GATE_CON04_PCLK_TIMER_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON04_PCLK_TIMER_EN_MASK (0x1U << CRU_CRU_GATE_CON04_PCLK_TIMER_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON04_CLK_TIMER0_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON04_CLK_TIMER0_EN_MASK (0x1U << CRU_CRU_GATE_CON04_CLK_TIMER0_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON04_CLK_TIMER1_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON04_CLK_TIMER1_EN_MASK (0x1U << CRU_CRU_GATE_CON04_CLK_TIMER1_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON04_CLK_TIMER2_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON04_CLK_TIMER2_EN_MASK (0x1U << CRU_CRU_GATE_CON04_CLK_TIMER2_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON04_CLK_TIMER3_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON04_CLK_TIMER3_EN_MASK (0x1U << CRU_CRU_GATE_CON04_CLK_TIMER3_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON04_CLK_TIMER4_EN_SHIFT (5U) +#define CRU_CRU_GATE_CON04_CLK_TIMER4_EN_MASK (0x1U << CRU_CRU_GATE_CON04_CLK_TIMER4_EN_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GATE_CON04_CLK_TIMER5_EN_SHIFT (6U) +#define CRU_CRU_GATE_CON04_CLK_TIMER5_EN_MASK (0x1U << CRU_CRU_GATE_CON04_CLK_TIMER5_EN_SHIFT) /* 0x00000040 */ +/* CRU_GATE_CON05 */ +#define CRU_CRU_GATE_CON05_OFFSET (0x194) +#define CRU_CRU_GATE_CON05_PCLK_I2C2APB_NIU_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON05_PCLK_I2C2APB_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON05_PCLK_I2C2APB_NIU_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON05_PCLK_I2C0_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON05_PCLK_I2C0_EN_MASK (0x1U << CRU_CRU_GATE_CON05_PCLK_I2C0_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON05_PCLK_I2C1_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON05_PCLK_I2C1_EN_MASK (0x1U << CRU_CRU_GATE_CON05_PCLK_I2C1_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON05_PCLK_I2C2_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON05_PCLK_I2C2_EN_MASK (0x1U << CRU_CRU_GATE_CON05_PCLK_I2C2_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON05_PCLK_I2C2APB_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON05_PCLK_I2C2APB_EN_MASK (0x1U << CRU_CRU_GATE_CON05_PCLK_I2C2APB_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON05_CLK_I2C0_EN_SHIFT (5U) +#define CRU_CRU_GATE_CON05_CLK_I2C0_EN_MASK (0x1U << CRU_CRU_GATE_CON05_CLK_I2C0_EN_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GATE_CON05_CLK_I2C1_EN_SHIFT (6U) +#define CRU_CRU_GATE_CON05_CLK_I2C1_EN_MASK (0x1U << CRU_CRU_GATE_CON05_CLK_I2C1_EN_SHIFT) /* 0x00000040 */ +#define CRU_CRU_GATE_CON05_CLK_I2C2_EN_SHIFT (7U) +#define CRU_CRU_GATE_CON05_CLK_I2C2_EN_MASK (0x1U << CRU_CRU_GATE_CON05_CLK_I2C2_EN_SHIFT) /* 0x00000080 */ +#define CRU_CRU_GATE_CON05_PCLK_ACDC_DIG_EN_SHIFT (14U) +#define CRU_CRU_GATE_CON05_PCLK_ACDC_DIG_EN_MASK (0x1U << CRU_CRU_GATE_CON05_PCLK_ACDC_DIG_EN_SHIFT) /* 0x00004000 */ +#define CRU_CRU_GATE_CON05_ACLK_DMAC_CORE_EN_SHIFT (15U) +#define CRU_CRU_GATE_CON05_ACLK_DMAC_CORE_EN_MASK (0x1U << CRU_CRU_GATE_CON05_ACLK_DMAC_CORE_EN_SHIFT) /* 0x00008000 */ +/* CRU_GATE_CON06 */ +#define CRU_CRU_GATE_CON06_OFFSET (0x198) +#define CRU_CRU_GATE_CON06_HCLK_PDM0_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON06_HCLK_PDM0_EN_MASK (0x1U << CRU_CRU_GATE_CON06_HCLK_PDM0_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON06_HCLK_AUDIO_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON06_HCLK_AUDIO_EN_MASK (0x1U << CRU_CRU_GATE_CON06_HCLK_AUDIO_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON06_HCLK_I2S_8CH_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON06_HCLK_I2S_8CH_EN_MASK (0x1U << CRU_CRU_GATE_CON06_HCLK_I2S_8CH_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON06_HCLK_VAD_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON06_HCLK_VAD_EN_MASK (0x1U << CRU_CRU_GATE_CON06_HCLK_VAD_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON06_HCLK_AUDIO_NIU_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON06_HCLK_AUDIO_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON06_HCLK_AUDIO_NIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON06_HCLK_AUDIO_AHB_ARB_EN_SHIFT (5U) +#define CRU_CRU_GATE_CON06_HCLK_AUDIO_AHB_ARB_EN_MASK (0x1U << CRU_CRU_GATE_CON06_HCLK_AUDIO_AHB_ARB_EN_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GATE_CON06_PCLK_AUDIO_NIU_EN_SHIFT (6U) +#define CRU_CRU_GATE_CON06_PCLK_AUDIO_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON06_PCLK_AUDIO_NIU_EN_SHIFT) /* 0x00000040 */ +#define CRU_CRU_GATE_CON06_MCLK_PDM0_EN_SHIFT (7U) +#define CRU_CRU_GATE_CON06_MCLK_PDM0_EN_MASK (0x1U << CRU_CRU_GATE_CON06_MCLK_PDM0_EN_SHIFT) /* 0x00000080 */ +#define CRU_CRU_GATE_CON06_MCLK_PDM0_OUT_EN_SHIFT (8U) +#define CRU_CRU_GATE_CON06_MCLK_PDM0_OUT_EN_MASK (0x1U << CRU_CRU_GATE_CON06_MCLK_PDM0_OUT_EN_SHIFT) /* 0x00000100 */ +#define CRU_CRU_GATE_CON06_PCLK_AUDIO_EN_SHIFT (9U) +#define CRU_CRU_GATE_CON06_PCLK_AUDIO_EN_MASK (0x1U << CRU_CRU_GATE_CON06_PCLK_AUDIO_EN_SHIFT) /* 0x00000200 */ +#define CRU_CRU_GATE_CON06_CLK_I2S8CH_EN_SHIFT (10U) +#define CRU_CRU_GATE_CON06_CLK_I2S8CH_EN_MASK (0x1U << CRU_CRU_GATE_CON06_CLK_I2S8CH_EN_SHIFT) /* 0x00000400 */ +#define CRU_CRU_GATE_CON06_CLK_I2S8CH_FRAC_EN_SHIFT (11U) +#define CRU_CRU_GATE_CON06_CLK_I2S8CH_FRAC_EN_MASK (0x1U << CRU_CRU_GATE_CON06_CLK_I2S8CH_FRAC_EN_SHIFT) /* 0x00000800 */ +#define CRU_CRU_GATE_CON06_MCLK_I2S8CH_EN_SHIFT (12U) +#define CRU_CRU_GATE_CON06_MCLK_I2S8CH_EN_MASK (0x1U << CRU_CRU_GATE_CON06_MCLK_I2S8CH_EN_SHIFT) /* 0x00001000 */ +#define CRU_CRU_GATE_CON06_I2S_MCLKOUT_EN_SHIFT (13U) +#define CRU_CRU_GATE_CON06_I2S_MCLKOUT_EN_MASK (0x1U << CRU_CRU_GATE_CON06_I2S_MCLKOUT_EN_SHIFT) /* 0x00002000 */ +#define CRU_CRU_GATE_CON06_ACLK_DMAC_EN_SHIFT (14U) +#define CRU_CRU_GATE_CON06_ACLK_DMAC_EN_MASK (0x1U << CRU_CRU_GATE_CON06_ACLK_DMAC_EN_SHIFT) /* 0x00004000 */ +#define CRU_CRU_GATE_CON06_ACLK_DMAC_NIU_EN_SHIFT (15U) +#define CRU_CRU_GATE_CON06_ACLK_DMAC_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON06_ACLK_DMAC_NIU_EN_SHIFT) /* 0x00008000 */ +/* CRU_GATE_CON07 */ +#define CRU_CRU_GATE_CON07_OFFSET (0x19C) +#define CRU_CRU_GATE_CON07_ACLK_VOP_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON07_ACLK_VOP_EN_MASK (0x1U << CRU_CRU_GATE_CON07_ACLK_VOP_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON07_DCLK_VOP_S_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON07_DCLK_VOP_S_EN_MASK (0x1U << CRU_CRU_GATE_CON07_DCLK_VOP_S_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON07_ACLK_VOP_NIU_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON07_ACLK_VOP_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON07_ACLK_VOP_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON07_DCLK_VOP_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON07_DCLK_VOP_EN_MASK (0x1U << CRU_CRU_GATE_CON07_DCLK_VOP_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON07_DCLK_MIPIDSI_HOST_EN_SHIFT (5U) +#define CRU_CRU_GATE_CON07_DCLK_MIPIDSI_HOST_EN_MASK (0x1U << CRU_CRU_GATE_CON07_DCLK_MIPIDSI_HOST_EN_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GATE_CON07_OCC_SCAN_CLK_DPHYLANBYTE_EN_SHIFT (8U) +#define CRU_CRU_GATE_CON07_OCC_SCAN_CLK_DPHYLANBYTE_EN_MASK (0x1U << CRU_CRU_GATE_CON07_OCC_SCAN_CLK_DPHYLANBYTE_EN_SHIFT) /* 0x00000100 */ +/* CRU_GATE_CON08 */ +#define CRU_CRU_GATE_CON08_OFFSET (0x1A0) +#define CRU_CRU_GATE_CON08_PCLK_GPIO0_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON08_PCLK_GPIO0_EN_MASK (0x1U << CRU_CRU_GATE_CON08_PCLK_GPIO0_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON08_PCLK_GPIO1_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON08_PCLK_GPIO1_EN_MASK (0x1U << CRU_CRU_GATE_CON08_PCLK_GPIO1_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON08_CLK_GPIO_DB0_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON08_CLK_GPIO_DB0_EN_MASK (0x1U << CRU_CRU_GATE_CON08_CLK_GPIO_DB0_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON08_CLK_GPIO_DB1_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON08_CLK_GPIO_DB1_EN_MASK (0x1U << CRU_CRU_GATE_CON08_CLK_GPIO_DB1_EN_SHIFT) /* 0x00000010 */ +/* CRU_GATE_CON09 */ +#define CRU_CRU_GATE_CON09_OFFSET (0x1A4) +#define CRU_CRU_GATE_CON09_PCLK_ALIVE_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON09_PCLK_ALIVE_EN_MASK (0x1U << CRU_CRU_GATE_CON09_PCLK_ALIVE_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON09_HCLK_ALIVE_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON09_HCLK_ALIVE_EN_MASK (0x1U << CRU_CRU_GATE_CON09_HCLK_ALIVE_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON09_HCLK_ALIVE_NIU_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON09_HCLK_ALIVE_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON09_HCLK_ALIVE_NIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON09_HCLK_ALIVEAHB_ARB_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON09_HCLK_ALIVEAHB_ARB_EN_MASK (0x1U << CRU_CRU_GATE_CON09_HCLK_ALIVEAHB_ARB_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON09_HCLK_INTC0_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON09_HCLK_INTC0_EN_MASK (0x1U << CRU_CRU_GATE_CON09_HCLK_INTC0_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON09_HCLK_INTC1_EN_SHIFT (5U) +#define CRU_CRU_GATE_CON09_HCLK_INTC1_EN_MASK (0x1U << CRU_CRU_GATE_CON09_HCLK_INTC1_EN_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GATE_CON09_PCLK_CRU_EN_SHIFT (8U) +#define CRU_CRU_GATE_CON09_PCLK_CRU_EN_MASK (0x1U << CRU_CRU_GATE_CON09_PCLK_CRU_EN_SHIFT) /* 0x00000100 */ +#define CRU_CRU_GATE_CON09_PCLK_ALIVE_NIU_EN_SHIFT (9U) +#define CRU_CRU_GATE_CON09_PCLK_ALIVE_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON09_PCLK_ALIVE_NIU_EN_SHIFT) /* 0x00000200 */ +#define CRU_CRU_GATE_CON09_PCLK_PMU_EN_SHIFT (10U) +#define CRU_CRU_GATE_CON09_PCLK_PMU_EN_MASK (0x1U << CRU_CRU_GATE_CON09_PCLK_PMU_EN_SHIFT) /* 0x00000400 */ +#define CRU_CRU_GATE_CON09_PCLK_GRF_EN_SHIFT (11U) +#define CRU_CRU_GATE_CON09_PCLK_GRF_EN_MASK (0x1U << CRU_CRU_GATE_CON09_PCLK_GRF_EN_SHIFT) /* 0x00000800 */ +#define CRU_CRU_GATE_CON09_CLK_PMU_EN_SHIFT (12U) +#define CRU_CRU_GATE_CON09_CLK_PMU_EN_MASK (0x1U << CRU_CRU_GATE_CON09_CLK_PMU_EN_SHIFT) /* 0x00001000 */ +#define CRU_CRU_GATE_CON09_CLK_TESTOUT_EN_SHIFT (13U) +#define CRU_CRU_GATE_CON09_CLK_TESTOUT_EN_MASK (0x1U << CRU_CRU_GATE_CON09_CLK_TESTOUT_EN_SHIFT) /* 0x00002000 */ +#define CRU_CRU_GATE_CON09_CLK_PVTM_EN_SHIFT (14U) +#define CRU_CRU_GATE_CON09_CLK_PVTM_EN_MASK (0x1U << CRU_CRU_GATE_CON09_CLK_PVTM_EN_SHIFT) /* 0x00004000 */ +#define CRU_CRU_GATE_CON09_CLK_PDM_SAMP_EN_SHIFT (15U) +#define CRU_CRU_GATE_CON09_CLK_PDM_SAMP_EN_MASK (0x1U << CRU_CRU_GATE_CON09_CLK_PDM_SAMP_EN_SHIFT) /* 0x00008000 */ +/* CRU_GATE_CON10 */ +#define CRU_CRU_GATE_CON10_OFFSET (0x1A8) +#define CRU_CRU_GATE_CON10_CLK_MEMSUBSYS0_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON10_CLK_MEMSUBSYS0_EN_MASK (0x1U << CRU_CRU_GATE_CON10_CLK_MEMSUBSYS0_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON10_CLK_MEMSUBSYS1_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON10_CLK_MEMSUBSYS1_EN_MASK (0x1U << CRU_CRU_GATE_CON10_CLK_MEMSUBSYS1_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON10_CLK_MEMSUBSYS2_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON10_CLK_MEMSUBSYS2_EN_MASK (0x1U << CRU_CRU_GATE_CON10_CLK_MEMSUBSYS2_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON10_CLK_MEMSUBSYS3_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON10_CLK_MEMSUBSYS3_EN_MASK (0x1U << CRU_CRU_GATE_CON10_CLK_MEMSUBSYS3_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON10_ACLK_MEMSUBSYS_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON10_ACLK_MEMSUBSYS_EN_MASK (0x1U << CRU_CRU_GATE_CON10_ACLK_MEMSUBSYS_EN_SHIFT) /* 0x00000010 */ +/* CRU_GATE_CON11 */ +#define CRU_CRU_GATE_CON11_OFFSET (0x1AC) +#define CRU_CRU_GATE_CON11_ACLK_LOGIC_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON11_ACLK_LOGIC_EN_MASK (0x1U << CRU_CRU_GATE_CON11_ACLK_LOGIC_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON11_ACLK_LOGIC_NIU_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON11_ACLK_LOGIC_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON11_ACLK_LOGIC_NIU_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON11_HCLK_LOGIC_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON11_HCLK_LOGIC_EN_MASK (0x1U << CRU_CRU_GATE_CON11_HCLK_LOGIC_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON11_PCLK_LOGIC_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON11_PCLK_LOGIC_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_LOGIC_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON11_PCLK_SPI2APB_NIU_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON11_PCLK_SPI2APB_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_SPI2APB_NIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON11_PCLK_PWM_EN_SHIFT (5U) +#define CRU_CRU_GATE_CON11_PCLK_PWM_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_PWM_EN_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GATE_CON11_PCLK_SPI1_EN_SHIFT (6U) +#define CRU_CRU_GATE_CON11_PCLK_SPI1_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_SPI1_EN_SHIFT) /* 0x00000040 */ +#define CRU_CRU_GATE_CON11_PCLK_SPI2_EN_SHIFT (7U) +#define CRU_CRU_GATE_CON11_PCLK_SPI2_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_SPI2_EN_SHIFT) /* 0x00000080 */ +#define CRU_CRU_GATE_CON11_PCLK_SPI2APB_EN_SHIFT (8U) +#define CRU_CRU_GATE_CON11_PCLK_SPI2APB_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_SPI2APB_EN_SHIFT) /* 0x00000100 */ +#define CRU_CRU_GATE_CON11_PCLK_MAILBOX0_EN_SHIFT (9U) +#define CRU_CRU_GATE_CON11_PCLK_MAILBOX0_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_MAILBOX0_EN_SHIFT) /* 0x00000200 */ +#define CRU_CRU_GATE_CON11_PCLK_MAILBOX1_EN_SHIFT (10U) +#define CRU_CRU_GATE_CON11_PCLK_MAILBOX1_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_MAILBOX1_EN_SHIFT) /* 0x00000400 */ +#define CRU_CRU_GATE_CON11_PCLK_MAILBOX2_EN_SHIFT (11U) +#define CRU_CRU_GATE_CON11_PCLK_MAILBOX2_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_MAILBOX2_EN_SHIFT) /* 0x00000800 */ +#define CRU_CRU_GATE_CON11_PCLK_WDT0_EN_SHIFT (12U) +#define CRU_CRU_GATE_CON11_PCLK_WDT0_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_WDT0_EN_SHIFT) /* 0x00001000 */ +#define CRU_CRU_GATE_CON11_PCLK_MIPIDSI_HOST_EN_SHIFT (13U) +#define CRU_CRU_GATE_CON11_PCLK_MIPIDSI_HOST_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_MIPIDSI_HOST_EN_SHIFT) /* 0x00002000 */ +#define CRU_CRU_GATE_CON11_PCLK_CIF_EN_SHIFT (14U) +#define CRU_CRU_GATE_CON11_PCLK_CIF_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_CIF_EN_SHIFT) /* 0x00004000 */ +#define CRU_CRU_GATE_CON11_PCLK_LOGIC_NIU_EN_SHIFT (15U) +#define CRU_CRU_GATE_CON11_PCLK_LOGIC_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON11_PCLK_LOGIC_NIU_EN_SHIFT) /* 0x00008000 */ +/* CRU_GATE_CON12 */ +#define CRU_CRU_GATE_CON12_OFFSET (0x1B0) +#define CRU_CRU_GATE_CON12_HCLK_M4_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON12_HCLK_M4_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_M4_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON12_HCLK_USB2CTRL_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON12_HCLK_USB2CTRL_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_USB2CTRL_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON12_HCLK_USB2_NIU_EN_SHIFT (2U) +#define CRU_CRU_GATE_CON12_HCLK_USB2_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_USB2_NIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_CRU_GATE_CON12_HCLK_BOOTROM_EN_SHIFT (3U) +#define CRU_CRU_GATE_CON12_HCLK_BOOTROM_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_BOOTROM_EN_SHIFT) /* 0x00000008 */ +#define CRU_CRU_GATE_CON12_HCLK_VOP_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON12_HCLK_VOP_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_VOP_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON12_HCLK_AUDPWM_EN_SHIFT (5U) +#define CRU_CRU_GATE_CON12_HCLK_AUDPWM_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_AUDPWM_EN_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GATE_CON12_HCLK_CIF_EN_SHIFT (6U) +#define CRU_CRU_GATE_CON12_HCLK_CIF_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_CIF_EN_SHIFT) /* 0x00000040 */ +#define CRU_CRU_GATE_CON12_HCLK_LOGIC_NIU_EN_SHIFT (7U) +#define CRU_CRU_GATE_CON12_HCLK_LOGIC_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_LOGIC_NIU_EN_SHIFT) /* 0x00000080 */ +#define CRU_CRU_GATE_CON12_HCLK_SFC_EN_SHIFT (8U) +#define CRU_CRU_GATE_CON12_HCLK_SFC_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_SFC_EN_SHIFT) /* 0x00000100 */ +#define CRU_CRU_GATE_CON12_HCLK_XIP_SFC_EN_SHIFT (9U) +#define CRU_CRU_GATE_CON12_HCLK_XIP_SFC_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_XIP_SFC_EN_SHIFT) /* 0x00000200 */ +#define CRU_CRU_GATE_CON12_HCLK_SDIO_EN_SHIFT (10U) +#define CRU_CRU_GATE_CON12_HCLK_SDIO_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_SDIO_EN_SHIFT) /* 0x00000400 */ +#define CRU_CRU_GATE_CON12_HCLK_LOGIC_AHB_ARB_EN_SHIFT (11U) +#define CRU_CRU_GATE_CON12_HCLK_LOGIC_AHB_ARB_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_LOGIC_AHB_ARB_EN_SHIFT) /* 0x00000800 */ +#define CRU_CRU_GATE_CON12_HCLK_I2S1_8CH_EN_SHIFT (12U) +#define CRU_CRU_GATE_CON12_HCLK_I2S1_8CH_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_I2S1_8CH_EN_SHIFT) /* 0x00001000 */ +#define CRU_CRU_GATE_CON12_HCLK_CM4_NIU_EN_SHIFT (13U) +#define CRU_CRU_GATE_CON12_HCLK_CM4_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_CM4_NIU_EN_SHIFT) /* 0x00002000 */ +#define CRU_CRU_GATE_CON12_HCLK_CM4_CORE_EN_SHIFT (14U) +#define CRU_CRU_GATE_CON12_HCLK_CM4_CORE_EN_MASK (0x1U << CRU_CRU_GATE_CON12_HCLK_CM4_CORE_EN_SHIFT) /* 0x00004000 */ +#define CRU_CRU_GATE_CON12_CLK_CIFOUT_EN_SHIFT (15U) +#define CRU_CRU_GATE_CON12_CLK_CIFOUT_EN_MASK (0x1U << CRU_CRU_GATE_CON12_CLK_CIFOUT_EN_SHIFT) /* 0x00008000 */ +/* CRU_GATE_CON13 */ +#define CRU_CRU_GATE_CON13_OFFSET (0x1B4) +#define CRU_CRU_GATE_CON13_CLK_SPI1_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON13_CLK_SPI1_EN_MASK (0x1U << CRU_CRU_GATE_CON13_CLK_SPI1_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON13_CLK_SPI2_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON13_CLK_SPI2_EN_MASK (0x1U << CRU_CRU_GATE_CON13_CLK_SPI2_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON13_SCLK_SFC_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON13_SCLK_SFC_EN_MASK (0x1U << CRU_CRU_GATE_CON13_SCLK_SFC_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON13_HCLK_SFC1_EN_SHIFT (5U) +#define CRU_CRU_GATE_CON13_HCLK_SFC1_EN_MASK (0x1U << CRU_CRU_GATE_CON13_HCLK_SFC1_EN_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GATE_CON13_HCLK_XIP_SFC1_EN_SHIFT (6U) +#define CRU_CRU_GATE_CON13_HCLK_XIP_SFC1_EN_MASK (0x1U << CRU_CRU_GATE_CON13_HCLK_XIP_SFC1_EN_SHIFT) /* 0x00000040 */ +#define CRU_CRU_GATE_CON13_CLK_SDIO_EN_SHIFT (8U) +#define CRU_CRU_GATE_CON13_CLK_SDIO_EN_MASK (0x1U << CRU_CRU_GATE_CON13_CLK_SDIO_EN_SHIFT) /* 0x00000100 */ +#define CRU_CRU_GATE_CON13_CLK_I2S1_8CH_EN_SHIFT (9U) +#define CRU_CRU_GATE_CON13_CLK_I2S1_8CH_EN_MASK (0x1U << CRU_CRU_GATE_CON13_CLK_I2S1_8CH_EN_SHIFT) /* 0x00000200 */ +#define CRU_CRU_GATE_CON13_CLK_I2S1_8CH_FRAC_EN_SHIFT (10U) +#define CRU_CRU_GATE_CON13_CLK_I2S1_8CH_FRAC_EN_MASK (0x1U << CRU_CRU_GATE_CON13_CLK_I2S1_8CH_FRAC_EN_SHIFT) /* 0x00000400 */ +#define CRU_CRU_GATE_CON13_MCLK_I2S1_8CH_EN_SHIFT (11U) +#define CRU_CRU_GATE_CON13_MCLK_I2S1_8CH_EN_MASK (0x1U << CRU_CRU_GATE_CON13_MCLK_I2S1_8CH_EN_SHIFT) /* 0x00000800 */ +#define CRU_CRU_GATE_CON13_I2S1_MCLKOUT_EN_SHIFT (12U) +#define CRU_CRU_GATE_CON13_I2S1_MCLKOUT_EN_MASK (0x1U << CRU_CRU_GATE_CON13_I2S1_MCLKOUT_EN_SHIFT) /* 0x00001000 */ +#define CRU_CRU_GATE_CON13_CLK_PWM_EN_SHIFT (13U) +#define CRU_CRU_GATE_CON13_CLK_PWM_EN_MASK (0x1U << CRU_CRU_GATE_CON13_CLK_PWM_EN_SHIFT) /* 0x00002000 */ +#define CRU_CRU_GATE_CON13_CLK_AUDPWM_DF_EN_SHIFT (14U) +#define CRU_CRU_GATE_CON13_CLK_AUDPWM_DF_EN_MASK (0x1U << CRU_CRU_GATE_CON13_CLK_AUDPWM_DF_EN_SHIFT) /* 0x00004000 */ +#define CRU_CRU_GATE_CON13_ACLK_CIF_EN_SHIFT (15U) +#define CRU_CRU_GATE_CON13_ACLK_CIF_EN_MASK (0x1U << CRU_CRU_GATE_CON13_ACLK_CIF_EN_SHIFT) /* 0x00008000 */ +/* CRU_GATE_CON14 */ +#define CRU_CRU_GATE_CON14_OFFSET (0x1B8) +#define CRU_CRU_GATE_CON14_CLK_AUDPWM_FRAC_EN_SHIFT (0U) +#define CRU_CRU_GATE_CON14_CLK_AUDPWM_FRAC_EN_MASK (0x1U << CRU_CRU_GATE_CON14_CLK_AUDPWM_FRAC_EN_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GATE_CON14_ACLK_CIF_NIU_EN_SHIFT (1U) +#define CRU_CRU_GATE_CON14_ACLK_CIF_NIU_EN_MASK (0x1U << CRU_CRU_GATE_CON14_ACLK_CIF_NIU_EN_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GATE_CON14_SCLK_SFC1_EN_SHIFT (4U) +#define CRU_CRU_GATE_CON14_SCLK_SFC1_EN_MASK (0x1U << CRU_CRU_GATE_CON14_SCLK_SFC1_EN_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GATE_CON14_CLK_USB2_ADP_EN_SHIFT (5U) +#define CRU_CRU_GATE_CON14_CLK_USB2_ADP_EN_MASK (0x1U << CRU_CRU_GATE_CON14_CLK_USB2_ADP_EN_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GATE_CON14_CLK_USB2PHY_REF_FRAC_EN_SHIFT (6U) +#define CRU_CRU_GATE_CON14_CLK_USB2PHY_REF_FRAC_EN_MASK (0x1U << CRU_CRU_GATE_CON14_CLK_USB2PHY_REF_FRAC_EN_SHIFT) /* 0x00000040 */ +#define CRU_CRU_GATE_CON14_CLK_DPHY_REF_FRAC_EN_SHIFT (7U) +#define CRU_CRU_GATE_CON14_CLK_DPHY_REF_FRAC_EN_MASK (0x1U << CRU_CRU_GATE_CON14_CLK_DPHY_REF_FRAC_EN_SHIFT) /* 0x00000080 */ +#define CRU_CRU_GATE_CON14_STCLK_M4_EN_SHIFT (8U) +#define CRU_CRU_GATE_CON14_STCLK_M4_EN_MASK (0x1U << CRU_CRU_GATE_CON14_STCLK_M4_EN_SHIFT) /* 0x00000100 */ +#define CRU_CRU_GATE_CON14_CLK_KEY_EN_SHIFT (9U) +#define CRU_CRU_GATE_CON14_CLK_KEY_EN_MASK (0x1U << CRU_CRU_GATE_CON14_CLK_KEY_EN_SHIFT) /* 0x00000200 */ +#define CRU_CRU_GATE_CON14_PCLK_KEY_EN_SHIFT (10U) +#define CRU_CRU_GATE_CON14_PCLK_KEY_EN_MASK (0x1U << CRU_CRU_GATE_CON14_PCLK_KEY_EN_SHIFT) /* 0x00000400 */ +#define CRU_CRU_GATE_CON14_CLK_USB2CTRL_EN_SHIFT (13U) +#define CRU_CRU_GATE_CON14_CLK_USB2CTRL_EN_MASK (0x1U << CRU_CRU_GATE_CON14_CLK_USB2CTRL_EN_SHIFT) /* 0x00002000 */ +#define CRU_CRU_GATE_CON14_CLK_BT32K_EN_SHIFT (15U) +#define CRU_CRU_GATE_CON14_CLK_BT32K_EN_MASK (0x1U << CRU_CRU_GATE_CON14_CLK_BT32K_EN_SHIFT) /* 0x00008000 */ +/* CRU_SOFTRST_CON00 */ +#define CRU_CRU_SOFTRST_CON00_OFFSET (0x200) +#define CRU_CRU_SOFTRST_CON00_DRESETN_DSP_SHIFT (0U) +#define CRU_CRU_SOFTRST_CON00_DRESETN_DSP_MASK (0x1U << CRU_CRU_SOFTRST_CON00_DRESETN_DSP_SHIFT) /* 0x00000001 */ +#define CRU_CRU_SOFTRST_CON00_BRESETN_DSP_SHIFT (1U) +#define CRU_CRU_SOFTRST_CON00_BRESETN_DSP_MASK (0x1U << CRU_CRU_SOFTRST_CON00_BRESETN_DSP_SHIFT) /* 0x00000002 */ +#define CRU_CRU_SOFTRST_CON00_ARESETN_DSP_NIU_SHIFT (2U) +#define CRU_CRU_SOFTRST_CON00_ARESETN_DSP_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON00_ARESETN_DSP_NIU_SHIFT) /* 0x00000004 */ +#define CRU_CRU_SOFTRST_CON00_PRESETN_DSP_NIU_SHIFT (4U) +#define CRU_CRU_SOFTRST_CON00_PRESETN_DSP_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON00_PRESETN_DSP_NIU_SHIFT) /* 0x00000010 */ +#define CRU_CRU_SOFTRST_CON00_PRESETN_DSP_GRF_SHIFT (5U) +#define CRU_CRU_SOFTRST_CON00_PRESETN_DSP_GRF_MASK (0x1U << CRU_CRU_SOFTRST_CON00_PRESETN_DSP_GRF_SHIFT) /* 0x00000020 */ +#define CRU_CRU_SOFTRST_CON00_PRESETN_WDT1_SHIFT (6U) +#define CRU_CRU_SOFTRST_CON00_PRESETN_WDT1_MASK (0x1U << CRU_CRU_SOFTRST_CON00_PRESETN_WDT1_SHIFT) /* 0x00000040 */ +/* CRU_SOFTRST_CON01 */ +#define CRU_CRU_SOFTRST_CON01_OFFSET (0x204) +#define CRU_CRU_SOFTRST_CON01_SRESETN_SHRM_SHIFT (0U) +#define CRU_CRU_SOFTRST_CON01_SRESETN_SHRM_MASK (0x1U << CRU_CRU_SOFTRST_CON01_SRESETN_SHRM_SHIFT) /* 0x00000001 */ +#define CRU_CRU_SOFTRST_CON01_ARESETN_SHRM_NIU_SHIFT (1U) +#define CRU_CRU_SOFTRST_CON01_ARESETN_SHRM_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON01_ARESETN_SHRM_NIU_SHIFT) /* 0x00000002 */ +#define CRU_CRU_SOFTRST_CON01_PRESETN_SHRM_SHIFT (2U) +#define CRU_CRU_SOFTRST_CON01_PRESETN_SHRM_MASK (0x1U << CRU_CRU_SOFTRST_CON01_PRESETN_SHRM_SHIFT) /* 0x00000004 */ +#define CRU_CRU_SOFTRST_CON01_PRESETN_SHRM_NIU_SHIFT (3U) +#define CRU_CRU_SOFTRST_CON01_PRESETN_SHRM_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON01_PRESETN_SHRM_NIU_SHIFT) /* 0x00000008 */ +/* CRU_SOFTRST_CON02 */ +#define CRU_CRU_SOFTRST_CON02_OFFSET (0x208) +#define CRU_CRU_SOFTRST_CON02_PRESETN_UART0_SHIFT (0U) +#define CRU_CRU_SOFTRST_CON02_PRESETN_UART0_MASK (0x1U << CRU_CRU_SOFTRST_CON02_PRESETN_UART0_SHIFT) /* 0x00000001 */ +#define CRU_CRU_SOFTRST_CON02_PRESETN_UART1_SHIFT (1U) +#define CRU_CRU_SOFTRST_CON02_PRESETN_UART1_MASK (0x1U << CRU_CRU_SOFTRST_CON02_PRESETN_UART1_SHIFT) /* 0x00000002 */ +#define CRU_CRU_SOFTRST_CON02_PRESETN_UART2_SHIFT (3U) +#define CRU_CRU_SOFTRST_CON02_PRESETN_UART2_MASK (0x1U << CRU_CRU_SOFTRST_CON02_PRESETN_UART2_SHIFT) /* 0x00000008 */ +#define CRU_CRU_SOFTRST_CON02_SRESETN_UART0_SHIFT (6U) +#define CRU_CRU_SOFTRST_CON02_SRESETN_UART0_MASK (0x1U << CRU_CRU_SOFTRST_CON02_SRESETN_UART0_SHIFT) /* 0x00000040 */ +#define CRU_CRU_SOFTRST_CON02_SRESETN_UART1_SHIFT (9U) +#define CRU_CRU_SOFTRST_CON02_SRESETN_UART1_MASK (0x1U << CRU_CRU_SOFTRST_CON02_SRESETN_UART1_SHIFT) /* 0x00000200 */ +#define CRU_CRU_SOFTRST_CON02_SRESETN_UART2_SHIFT (14U) +#define CRU_CRU_SOFTRST_CON02_SRESETN_UART2_MASK (0x1U << CRU_CRU_SOFTRST_CON02_SRESETN_UART2_SHIFT) /* 0x00004000 */ +/* CRU_SOFTRST_CON04 */ +#define CRU_CRU_SOFTRST_CON04_OFFSET (0x210) +#define CRU_CRU_SOFTRST_CON04_PRESETN_TIMER_SHIFT (0U) +#define CRU_CRU_SOFTRST_CON04_PRESETN_TIMER_MASK (0x1U << CRU_CRU_SOFTRST_CON04_PRESETN_TIMER_SHIFT) /* 0x00000001 */ +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER0_SHIFT (1U) +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER0_MASK (0x1U << CRU_CRU_SOFTRST_CON04_RESETN_TIMER0_SHIFT) /* 0x00000002 */ +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER1_SHIFT (2U) +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER1_MASK (0x1U << CRU_CRU_SOFTRST_CON04_RESETN_TIMER1_SHIFT) /* 0x00000004 */ +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER2_SHIFT (3U) +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER2_MASK (0x1U << CRU_CRU_SOFTRST_CON04_RESETN_TIMER2_SHIFT) /* 0x00000008 */ +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER3_SHIFT (4U) +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER3_MASK (0x1U << CRU_CRU_SOFTRST_CON04_RESETN_TIMER3_SHIFT) /* 0x00000010 */ +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER4_SHIFT (5U) +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER4_MASK (0x1U << CRU_CRU_SOFTRST_CON04_RESETN_TIMER4_SHIFT) /* 0x00000020 */ +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER5_SHIFT (6U) +#define CRU_CRU_SOFTRST_CON04_RESETN_TIMER5_MASK (0x1U << CRU_CRU_SOFTRST_CON04_RESETN_TIMER5_SHIFT) /* 0x00000040 */ +/* CRU_SOFTRST_CON05 */ +#define CRU_CRU_SOFTRST_CON05_OFFSET (0x214) +#define CRU_CRU_SOFTRST_CON05_PRESETN_I2C2APB_NIU_SHIFT (0U) +#define CRU_CRU_SOFTRST_CON05_PRESETN_I2C2APB_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON05_PRESETN_I2C2APB_NIU_SHIFT) /* 0x00000001 */ +#define CRU_CRU_SOFTRST_CON05_PRESETN_I2C0_SHIFT (1U) +#define CRU_CRU_SOFTRST_CON05_PRESETN_I2C0_MASK (0x1U << CRU_CRU_SOFTRST_CON05_PRESETN_I2C0_SHIFT) /* 0x00000002 */ +#define CRU_CRU_SOFTRST_CON05_PRESETN_I2C1_SHIFT (2U) +#define CRU_CRU_SOFTRST_CON05_PRESETN_I2C1_MASK (0x1U << CRU_CRU_SOFTRST_CON05_PRESETN_I2C1_SHIFT) /* 0x00000004 */ +#define CRU_CRU_SOFTRST_CON05_PRESETN_I2C2_SHIFT (3U) +#define CRU_CRU_SOFTRST_CON05_PRESETN_I2C2_MASK (0x1U << CRU_CRU_SOFTRST_CON05_PRESETN_I2C2_SHIFT) /* 0x00000008 */ +#define CRU_CRU_SOFTRST_CON05_PRESETN_I2C2APB_SHIFT (4U) +#define CRU_CRU_SOFTRST_CON05_PRESETN_I2C2APB_MASK (0x1U << CRU_CRU_SOFTRST_CON05_PRESETN_I2C2APB_SHIFT) /* 0x00000010 */ +#define CRU_CRU_SOFTRST_CON05_RESETN_I2C0_SHIFT (5U) +#define CRU_CRU_SOFTRST_CON05_RESETN_I2C0_MASK (0x1U << CRU_CRU_SOFTRST_CON05_RESETN_I2C0_SHIFT) /* 0x00000020 */ +#define CRU_CRU_SOFTRST_CON05_RESETN_I2C1_SHIFT (6U) +#define CRU_CRU_SOFTRST_CON05_RESETN_I2C1_MASK (0x1U << CRU_CRU_SOFTRST_CON05_RESETN_I2C1_SHIFT) /* 0x00000040 */ +#define CRU_CRU_SOFTRST_CON05_RESETN_I2C2_SHIFT (7U) +#define CRU_CRU_SOFTRST_CON05_RESETN_I2C2_MASK (0x1U << CRU_CRU_SOFTRST_CON05_RESETN_I2C2_SHIFT) /* 0x00000080 */ +#define CRU_CRU_SOFTRST_CON05_RESETN_CODEC_I2S_OUT_SHIFT (12U) +#define CRU_CRU_SOFTRST_CON05_RESETN_CODEC_I2S_OUT_MASK (0x1U << CRU_CRU_SOFTRST_CON05_RESETN_CODEC_I2S_OUT_SHIFT) /* 0x00001000 */ +#define CRU_CRU_SOFTRST_CON05_PRESETN_ACDC_DIG_SHIFT (14U) +#define CRU_CRU_SOFTRST_CON05_PRESETN_ACDC_DIG_MASK (0x1U << CRU_CRU_SOFTRST_CON05_PRESETN_ACDC_DIG_SHIFT) /* 0x00004000 */ +#define CRU_CRU_SOFTRST_CON05_ARESETN_DMAC_CORE_SHIFT (15U) +#define CRU_CRU_SOFTRST_CON05_ARESETN_DMAC_CORE_MASK (0x1U << CRU_CRU_SOFTRST_CON05_ARESETN_DMAC_CORE_SHIFT) /* 0x00008000 */ +/* CRU_SOFTRST_CON06 */ +#define CRU_CRU_SOFTRST_CON06_OFFSET (0x218) +#define CRU_CRU_SOFTRST_CON06_HRESETN_PDM0_SHIFT (0U) +#define CRU_CRU_SOFTRST_CON06_HRESETN_PDM0_MASK (0x1U << CRU_CRU_SOFTRST_CON06_HRESETN_PDM0_SHIFT) /* 0x00000001 */ +#define CRU_CRU_SOFTRST_CON06_HRESETN_I2S_8CH_SHIFT (2U) +#define CRU_CRU_SOFTRST_CON06_HRESETN_I2S_8CH_MASK (0x1U << CRU_CRU_SOFTRST_CON06_HRESETN_I2S_8CH_SHIFT) /* 0x00000004 */ +#define CRU_CRU_SOFTRST_CON06_HRESETN_VAD_SHIFT (3U) +#define CRU_CRU_SOFTRST_CON06_HRESETN_VAD_MASK (0x1U << CRU_CRU_SOFTRST_CON06_HRESETN_VAD_SHIFT) /* 0x00000008 */ +#define CRU_CRU_SOFTRST_CON06_HRESETN_AUDIO_NIU_SHIFT (4U) +#define CRU_CRU_SOFTRST_CON06_HRESETN_AUDIO_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON06_HRESETN_AUDIO_NIU_SHIFT) /* 0x00000010 */ +#define CRU_CRU_SOFTRST_CON06_HRESETN_AUDIO_AHB_ARB_SHIFT (5U) +#define CRU_CRU_SOFTRST_CON06_HRESETN_AUDIO_AHB_ARB_MASK (0x1U << CRU_CRU_SOFTRST_CON06_HRESETN_AUDIO_AHB_ARB_SHIFT) /* 0x00000020 */ +#define CRU_CRU_SOFTRST_CON06_PRESETN_AUDIO_NIU_SHIFT (6U) +#define CRU_CRU_SOFTRST_CON06_PRESETN_AUDIO_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON06_PRESETN_AUDIO_NIU_SHIFT) /* 0x00000040 */ +#define CRU_CRU_SOFTRST_CON06_MRESETN_PDM0_SHIFT (7U) +#define CRU_CRU_SOFTRST_CON06_MRESETN_PDM0_MASK (0x1U << CRU_CRU_SOFTRST_CON06_MRESETN_PDM0_SHIFT) /* 0x00000080 */ +#define CRU_CRU_SOFTRST_CON06_MRESETN_I2S8CH_SHIFT (12U) +#define CRU_CRU_SOFTRST_CON06_MRESETN_I2S8CH_MASK (0x1U << CRU_CRU_SOFTRST_CON06_MRESETN_I2S8CH_SHIFT) /* 0x00001000 */ +#define CRU_CRU_SOFTRST_CON06_ARESETN_DMAC_NIU_SHIFT (15U) +#define CRU_CRU_SOFTRST_CON06_ARESETN_DMAC_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON06_ARESETN_DMAC_NIU_SHIFT) /* 0x00008000 */ +/* CRU_SOFTRST_CON07 */ +#define CRU_CRU_SOFTRST_CON07_OFFSET (0x21C) +#define CRU_CRU_SOFTRST_CON07_ARESETN_VOP_SHIFT (0U) +#define CRU_CRU_SOFTRST_CON07_ARESETN_VOP_MASK (0x1U << CRU_CRU_SOFTRST_CON07_ARESETN_VOP_SHIFT) /* 0x00000001 */ +#define CRU_CRU_SOFTRST_CON07_DRESETN_VOP_S_SHIFT (2U) +#define CRU_CRU_SOFTRST_CON07_DRESETN_VOP_S_MASK (0x1U << CRU_CRU_SOFTRST_CON07_DRESETN_VOP_S_SHIFT) /* 0x00000004 */ +#define CRU_CRU_SOFTRST_CON07_ARESETN_VOP_NIU_SHIFT (3U) +#define CRU_CRU_SOFTRST_CON07_ARESETN_VOP_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON07_ARESETN_VOP_NIU_SHIFT) /* 0x00000008 */ +/* CRU_SOFTRST_CON08 */ +#define CRU_CRU_SOFTRST_CON08_OFFSET (0x220) +#define CRU_CRU_SOFTRST_CON08_PRESETN_GPIO0_SHIFT (0U) +#define CRU_CRU_SOFTRST_CON08_PRESETN_GPIO0_MASK (0x1U << CRU_CRU_SOFTRST_CON08_PRESETN_GPIO0_SHIFT) /* 0x00000001 */ +#define CRU_CRU_SOFTRST_CON08_PRESETN_GPIO1_SHIFT (1U) +#define CRU_CRU_SOFTRST_CON08_PRESETN_GPIO1_MASK (0x1U << CRU_CRU_SOFTRST_CON08_PRESETN_GPIO1_SHIFT) /* 0x00000002 */ +#define CRU_CRU_SOFTRST_CON08_RESETN_GPIO_DB0_SHIFT (3U) +#define CRU_CRU_SOFTRST_CON08_RESETN_GPIO_DB0_MASK (0x1U << CRU_CRU_SOFTRST_CON08_RESETN_GPIO_DB0_SHIFT) /* 0x00000008 */ +#define CRU_CRU_SOFTRST_CON08_RESETN_GPIO_DB1_SHIFT (4U) +#define CRU_CRU_SOFTRST_CON08_RESETN_GPIO_DB1_MASK (0x1U << CRU_CRU_SOFTRST_CON08_RESETN_GPIO_DB1_SHIFT) /* 0x00000010 */ +/* CRU_SOFTRST_CON09 */ +#define CRU_CRU_SOFTRST_CON09_OFFSET (0x224) +#define CRU_CRU_SOFTRST_CON09_HRESETN_ALIVE_NIU_SHIFT (2U) +#define CRU_CRU_SOFTRST_CON09_HRESETN_ALIVE_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON09_HRESETN_ALIVE_NIU_SHIFT) /* 0x00000004 */ +#define CRU_CRU_SOFTRST_CON09_HRESETN_ALIVEAHB_ARB_SHIFT (3U) +#define CRU_CRU_SOFTRST_CON09_HRESETN_ALIVEAHB_ARB_MASK (0x1U << CRU_CRU_SOFTRST_CON09_HRESETN_ALIVEAHB_ARB_SHIFT) /* 0x00000008 */ +#define CRU_CRU_SOFTRST_CON09_HRESETN_INTC0_SHIFT (4U) +#define CRU_CRU_SOFTRST_CON09_HRESETN_INTC0_MASK (0x1U << CRU_CRU_SOFTRST_CON09_HRESETN_INTC0_SHIFT) /* 0x00000010 */ +#define CRU_CRU_SOFTRST_CON09_HRESETN_INTC1_SHIFT (5U) +#define CRU_CRU_SOFTRST_CON09_HRESETN_INTC1_MASK (0x1U << CRU_CRU_SOFTRST_CON09_HRESETN_INTC1_SHIFT) /* 0x00000020 */ +#define CRU_CRU_SOFTRST_CON09_PRESETN_CRU_SHIFT (8U) +#define CRU_CRU_SOFTRST_CON09_PRESETN_CRU_MASK (0x1U << CRU_CRU_SOFTRST_CON09_PRESETN_CRU_SHIFT) /* 0x00000100 */ +#define CRU_CRU_SOFTRST_CON09_PRESETN_ALIVE_NIU_SHIFT (9U) +#define CRU_CRU_SOFTRST_CON09_PRESETN_ALIVE_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON09_PRESETN_ALIVE_NIU_SHIFT) /* 0x00000200 */ +#define CRU_CRU_SOFTRST_CON09_PRESETN_PMU_SHIFT (10U) +#define CRU_CRU_SOFTRST_CON09_PRESETN_PMU_MASK (0x1U << CRU_CRU_SOFTRST_CON09_PRESETN_PMU_SHIFT) /* 0x00000400 */ +#define CRU_CRU_SOFTRST_CON09_PRESETN_GRF_SHIFT (11U) +#define CRU_CRU_SOFTRST_CON09_PRESETN_GRF_MASK (0x1U << CRU_CRU_SOFTRST_CON09_PRESETN_GRF_SHIFT) /* 0x00000800 */ +#define CRU_CRU_SOFTRST_CON09_RESETN_PMU_SHIFT (12U) +#define CRU_CRU_SOFTRST_CON09_RESETN_PMU_MASK (0x1U << CRU_CRU_SOFTRST_CON09_RESETN_PMU_SHIFT) /* 0x00001000 */ +#define CRU_CRU_SOFTRST_CON09_RESETN_PVTM_SHIFT (14U) +#define CRU_CRU_SOFTRST_CON09_RESETN_PVTM_MASK (0x1U << CRU_CRU_SOFTRST_CON09_RESETN_PVTM_SHIFT) /* 0x00004000 */ +#define CRU_CRU_SOFTRST_CON09_RESETN_PDM_SAMP_SHIFT (15U) +#define CRU_CRU_SOFTRST_CON09_RESETN_PDM_SAMP_MASK (0x1U << CRU_CRU_SOFTRST_CON09_RESETN_PDM_SAMP_SHIFT) /* 0x00008000 */ +/* CRU_SOFTRST_CON11 */ +#define CRU_CRU_SOFTRST_CON11_OFFSET (0x22C) +#define CRU_CRU_SOFTRST_CON11_ARESETN_LOGIC_NIU_SHIFT (1U) +#define CRU_CRU_SOFTRST_CON11_ARESETN_LOGIC_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON11_ARESETN_LOGIC_NIU_SHIFT) /* 0x00000002 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_SPI2APB_NIU_SHIFT (4U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_SPI2APB_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_SPI2APB_NIU_SHIFT) /* 0x00000010 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_PWM_SHIFT (5U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_PWM_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_PWM_SHIFT) /* 0x00000020 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_SPI1_SHIFT (6U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_SPI1_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_SPI1_SHIFT) /* 0x00000040 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_SPI2_SHIFT (7U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_SPI2_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_SPI2_SHIFT) /* 0x00000080 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_SPI2APB_SHIFT (8U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_SPI2APB_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_SPI2APB_SHIFT) /* 0x00000100 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_MAILBOX0_SHIFT (9U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_MAILBOX0_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_MAILBOX0_SHIFT) /* 0x00000200 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_MAILBOX1_SHIFT (10U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_MAILBOX1_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_MAILBOX1_SHIFT) /* 0x00000400 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_MAILBOX2_SHIFT (11U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_MAILBOX2_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_MAILBOX2_SHIFT) /* 0x00000800 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_WDT0_SHIFT (12U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_WDT0_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_WDT0_SHIFT) /* 0x00001000 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_MIPIDSI_HOST_SHIFT (13U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_MIPIDSI_HOST_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_MIPIDSI_HOST_SHIFT) /* 0x00002000 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_CIF_SHIFT (14U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_CIF_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_CIF_SHIFT) /* 0x00004000 */ +#define CRU_CRU_SOFTRST_CON11_PRESETN_LOGIC_NIU_SHIFT (15U) +#define CRU_CRU_SOFTRST_CON11_PRESETN_LOGIC_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON11_PRESETN_LOGIC_NIU_SHIFT) /* 0x00008000 */ +/* CRU_SOFTRST_CON12 */ +#define CRU_CRU_SOFTRST_CON12_OFFSET (0x230) +#define CRU_CRU_SOFTRST_CON12_HRESETN_USB2CTRL_SHIFT (1U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_USB2CTRL_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_USB2CTRL_SHIFT) /* 0x00000002 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_USB2_NIU_SHIFT (2U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_USB2_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_USB2_NIU_SHIFT) /* 0x00000004 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_BOOTROM_SHIFT (3U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_BOOTROM_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_BOOTROM_SHIFT) /* 0x00000008 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_VOP_SHIFT (4U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_VOP_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_VOP_SHIFT) /* 0x00000010 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_AUDPWM_SHIFT (5U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_AUDPWM_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_AUDPWM_SHIFT) /* 0x00000020 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_CIF_SHIFT (6U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_CIF_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_CIF_SHIFT) /* 0x00000040 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_LOGIC_NIU_SHIFT (7U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_LOGIC_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_LOGIC_NIU_SHIFT) /* 0x00000080 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_SFC_SHIFT (8U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_SFC_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_SFC_SHIFT) /* 0x00000100 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_XIP_SFC_SHIFT (9U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_XIP_SFC_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_XIP_SFC_SHIFT) /* 0x00000200 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_SDIO_SHIFT (10U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_SDIO_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_SDIO_SHIFT) /* 0x00000400 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_LOGIC_AHB_ARB_SHIFT (11U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_LOGIC_AHB_ARB_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_LOGIC_AHB_ARB_SHIFT) /* 0x00000800 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_I2S1_8CH_SHIFT (12U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_I2S1_8CH_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_I2S1_8CH_SHIFT) /* 0x00001000 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_CM4_NIU_SHIFT (13U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_CM4_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_CM4_NIU_SHIFT) /* 0x00002000 */ +#define CRU_CRU_SOFTRST_CON12_HRESETN_CM4_CORE_SHIFT (14U) +#define CRU_CRU_SOFTRST_CON12_HRESETN_CM4_CORE_MASK (0x1U << CRU_CRU_SOFTRST_CON12_HRESETN_CM4_CORE_SHIFT) /* 0x00004000 */ +/* CRU_SOFTRST_CON13 */ +#define CRU_CRU_SOFTRST_CON13_OFFSET (0x234) +#define CRU_CRU_SOFTRST_CON13_RESETN_SPI1_SHIFT (0U) +#define CRU_CRU_SOFTRST_CON13_RESETN_SPI1_MASK (0x1U << CRU_CRU_SOFTRST_CON13_RESETN_SPI1_SHIFT) /* 0x00000001 */ +#define CRU_CRU_SOFTRST_CON13_RESETN_SPI2_SHIFT (1U) +#define CRU_CRU_SOFTRST_CON13_RESETN_SPI2_MASK (0x1U << CRU_CRU_SOFTRST_CON13_RESETN_SPI2_SHIFT) /* 0x00000002 */ +#define CRU_CRU_SOFTRST_CON13_SRESETN_SFC_SHIFT (4U) +#define CRU_CRU_SOFTRST_CON13_SRESETN_SFC_MASK (0x1U << CRU_CRU_SOFTRST_CON13_SRESETN_SFC_SHIFT) /* 0x00000010 */ +#define CRU_CRU_SOFTRST_CON13_HRESETN_SFC1_SHIFT (5U) +#define CRU_CRU_SOFTRST_CON13_HRESETN_SFC1_MASK (0x1U << CRU_CRU_SOFTRST_CON13_HRESETN_SFC1_SHIFT) /* 0x00000020 */ +#define CRU_CRU_SOFTRST_CON13_HRESETN_XIP_SFC1_SHIFT (6U) +#define CRU_CRU_SOFTRST_CON13_HRESETN_XIP_SFC1_MASK (0x1U << CRU_CRU_SOFTRST_CON13_HRESETN_XIP_SFC1_SHIFT) /* 0x00000040 */ +#define CRU_CRU_SOFTRST_CON13_RESETN_SDIO_SHIFT (8U) +#define CRU_CRU_SOFTRST_CON13_RESETN_SDIO_MASK (0x1U << CRU_CRU_SOFTRST_CON13_RESETN_SDIO_SHIFT) /* 0x00000100 */ +#define CRU_CRU_SOFTRST_CON13_MRESETN_I2S1_8CH_SHIFT (11U) +#define CRU_CRU_SOFTRST_CON13_MRESETN_I2S1_8CH_MASK (0x1U << CRU_CRU_SOFTRST_CON13_MRESETN_I2S1_8CH_SHIFT) /* 0x00000800 */ +#define CRU_CRU_SOFTRST_CON13_RESETN_PWM_SHIFT (13U) +#define CRU_CRU_SOFTRST_CON13_RESETN_PWM_MASK (0x1U << CRU_CRU_SOFTRST_CON13_RESETN_PWM_SHIFT) /* 0x00002000 */ +#define CRU_CRU_SOFTRST_CON13_RESETN_AUDPWM_SHIFT (14U) +#define CRU_CRU_SOFTRST_CON13_RESETN_AUDPWM_MASK (0x1U << CRU_CRU_SOFTRST_CON13_RESETN_AUDPWM_SHIFT) /* 0x00004000 */ +#define CRU_CRU_SOFTRST_CON13_ARESETN_CIF_SHIFT (15U) +#define CRU_CRU_SOFTRST_CON13_ARESETN_CIF_MASK (0x1U << CRU_CRU_SOFTRST_CON13_ARESETN_CIF_SHIFT) /* 0x00008000 */ +/* CRU_SOFTRST_CON14 */ +#define CRU_CRU_SOFTRST_CON14_OFFSET (0x238) +#define CRU_CRU_SOFTRST_CON14_ARESETN_CIF_NIU_SHIFT (1U) +#define CRU_CRU_SOFTRST_CON14_ARESETN_CIF_NIU_MASK (0x1U << CRU_CRU_SOFTRST_CON14_ARESETN_CIF_NIU_SHIFT) /* 0x00000002 */ +#define CRU_CRU_SOFTRST_CON14_SRESETN_SFC1_SHIFT (4U) +#define CRU_CRU_SOFTRST_CON14_SRESETN_SFC1_MASK (0x1U << CRU_CRU_SOFTRST_CON14_SRESETN_SFC1_SHIFT) /* 0x00000010 */ +#define CRU_CRU_SOFTRST_CON14_RESETN_USB2_ADP_SHIFT (5U) +#define CRU_CRU_SOFTRST_CON14_RESETN_USB2_ADP_MASK (0x1U << CRU_CRU_SOFTRST_CON14_RESETN_USB2_ADP_SHIFT) /* 0x00000020 */ +#define CRU_CRU_SOFTRST_CON14_RESETN_KEY_SHIFT (9U) +#define CRU_CRU_SOFTRST_CON14_RESETN_KEY_MASK (0x1U << CRU_CRU_SOFTRST_CON14_RESETN_KEY_SHIFT) /* 0x00000200 */ +#define CRU_CRU_SOFTRST_CON14_PRESETN_KEY_SHIFT (10U) +#define CRU_CRU_SOFTRST_CON14_PRESETN_KEY_MASK (0x1U << CRU_CRU_SOFTRST_CON14_PRESETN_KEY_SHIFT) /* 0x00000400 */ +#define CRU_CRU_SOFTRST_CON14_RESETN_USB2PHYUTMI_SHIFT (12U) +#define CRU_CRU_SOFTRST_CON14_RESETN_USB2PHYUTMI_MASK (0x1U << CRU_CRU_SOFTRST_CON14_RESETN_USB2PHYUTMI_SHIFT) /* 0x00001000 */ +#define CRU_CRU_SOFTRST_CON14_RESETN_USB2CTRL_SHIFT (13U) +#define CRU_CRU_SOFTRST_CON14_RESETN_USB2CTRL_MASK (0x1U << CRU_CRU_SOFTRST_CON14_RESETN_USB2CTRL_SHIFT) /* 0x00002000 */ +#define CRU_CRU_SOFTRST_CON14_RESETN_USB2PHYPO_SHIFT (14U) +#define CRU_CRU_SOFTRST_CON14_RESETN_USB2PHYPO_MASK (0x1U << CRU_CRU_SOFTRST_CON14_RESETN_USB2PHYPO_SHIFT) /* 0x00004000 */ +/* GLB_CNT_TH */ +#define CRU_GLB_CNT_TH_OFFSET (0x300) +#define CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_SHIFT (0U) +#define CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_MASK (0xFFFFU << CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_SHIFT) /* 0x0000FFFF */ +/* CRU_GLBRST_ST */ +#define CRU_CRU_GLBRST_ST_OFFSET (0x304) +#define CRU_CRU_GLBRST_ST_FST_GLB_RST_ST_SHIFT (0U) +#define CRU_CRU_GLBRST_ST_FST_GLB_RST_ST_MASK (0x1U << CRU_CRU_GLBRST_ST_FST_GLB_RST_ST_SHIFT) /* 0x00000001 */ +#define CRU_CRU_GLBRST_ST_SND_GLB_RST_ST_SHIFT (1U) +#define CRU_CRU_GLBRST_ST_SND_GLB_RST_ST_MASK (0x1U << CRU_CRU_GLBRST_ST_SND_GLB_RST_ST_SHIFT) /* 0x00000002 */ +#define CRU_CRU_GLBRST_ST_FST_GLB_WDT_RST_ST_SHIFT (4U) +#define CRU_CRU_GLBRST_ST_FST_GLB_WDT_RST_ST_MASK (0x1U << CRU_CRU_GLBRST_ST_FST_GLB_WDT_RST_ST_SHIFT) /* 0x00000010 */ +#define CRU_CRU_GLBRST_ST_SND_GLB_WDT_RST_ST_SHIFT (5U) +#define CRU_CRU_GLBRST_ST_SND_GLB_WDT_RST_ST_MASK (0x1U << CRU_CRU_GLBRST_ST_SND_GLB_WDT_RST_ST_SHIFT) /* 0x00000020 */ +#define CRU_CRU_GLBRST_ST_WDT0_GLBRST_SHIFT (6U) +#define CRU_CRU_GLBRST_ST_WDT0_GLBRST_MASK (0x1U << CRU_CRU_GLBRST_ST_WDT0_GLBRST_SHIFT) /* 0x00000040 */ +#define CRU_CRU_GLBRST_ST_WDT1_GLBRST_SHIFT (7U) +#define CRU_CRU_GLBRST_ST_WDT1_GLBRST_MASK (0x1U << CRU_CRU_GLBRST_ST_WDT1_GLBRST_SHIFT) /* 0x00000080 */ +#define CRU_CRU_GLBRST_ST_WDT2_GLBRST_SHIFT (8U) +#define CRU_CRU_GLBRST_ST_WDT2_GLBRST_MASK (0x1U << CRU_CRU_GLBRST_ST_WDT2_GLBRST_SHIFT) /* 0x00000100 */ +#define CRU_CRU_GLBRST_ST_WDT3_GLBRST_SHIFT (9U) +#define CRU_CRU_GLBRST_ST_WDT3_GLBRST_MASK (0x1U << CRU_CRU_GLBRST_ST_WDT3_GLBRST_SHIFT) /* 0x00000200 */ +/* GLB_SRST_FST_VALUE */ +#define CRU_GLB_SRST_FST_VALUE_OFFSET (0x308) +#define CRU_GLB_SRST_FST_VALUE_GLB_SRST_FST_SHIFT (0U) +#define CRU_GLB_SRST_FST_VALUE_GLB_SRST_FST_MASK (0xFFFFU << CRU_GLB_SRST_FST_VALUE_GLB_SRST_FST_SHIFT) /* 0x0000FFFF */ +/* GLB_SRST_SND_VALUE */ +#define CRU_GLB_SRST_SND_VALUE_OFFSET (0x30C) +#define CRU_GLB_SRST_SND_VALUE_GLB_SRST_SND_SHIFT (0U) +#define CRU_GLB_SRST_SND_VALUE_GLB_SRST_SND_MASK (0xFFFFU << CRU_GLB_SRST_SND_VALUE_GLB_SRST_SND_SHIFT) /* 0x0000FFFF */ +/* GLB_RST_CON */ +#define CRU_GLB_RST_CON_OFFSET (0x310) +#define CRU_GLB_RST_CON_WDT_RESET_EXT_EN_SHIFT (7U) +#define CRU_GLB_RST_CON_WDT_RESET_EXT_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT_RESET_EXT_EN_SHIFT) /* 0x00000080 */ +#define CRU_GLB_RST_CON_WDT0_GLBRST_EN_SHIFT (8U) +#define CRU_GLB_RST_CON_WDT0_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT0_GLBRST_EN_SHIFT) /* 0x00000100 */ +#define CRU_GLB_RST_CON_WDT1_GLBRST_EN_SHIFT (9U) +#define CRU_GLB_RST_CON_WDT1_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT1_GLBRST_EN_SHIFT) /* 0x00000200 */ +#define CRU_GLB_RST_CON_WDT2_GLBRST_EN_SHIFT (10U) +#define CRU_GLB_RST_CON_WDT2_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT2_GLBRST_EN_SHIFT) /* 0x00000400 */ +#define CRU_GLB_RST_CON_WDT3_GLBRST_EN_SHIFT (11U) +#define CRU_GLB_RST_CON_WDT3_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT3_GLBRST_EN_SHIFT) /* 0x00000800 */ +#define CRU_GLB_RST_CON_WDT0_FST_GLBRST_EN_SHIFT (12U) +#define CRU_GLB_RST_CON_WDT0_FST_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT0_FST_GLBRST_EN_SHIFT) /* 0x00001000 */ +#define CRU_GLB_RST_CON_WDT1_FST_GLBRST_EN_SHIFT (13U) +#define CRU_GLB_RST_CON_WDT1_FST_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT1_FST_GLBRST_EN_SHIFT) /* 0x00002000 */ +#define CRU_GLB_RST_CON_WDT2_FST_GLBRST_EN_SHIFT (14U) +#define CRU_GLB_RST_CON_WDT2_FST_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT2_FST_GLBRST_EN_SHIFT) /* 0x00004000 */ +#define CRU_GLB_RST_CON_WDT3_FST_GLBRST_EN_SHIFT (15U) +#define CRU_GLB_RST_CON_WDT3_FST_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT3_FST_GLBRST_EN_SHIFT) /* 0x00008000 */ +/* CRU_SDIO_CON0 */ +#define CRU_CRU_SDIO_CON0_OFFSET (0x320) +#define CRU_CRU_SDIO_CON0_SDIO_CON0_SHIFT (0U) +#define CRU_CRU_SDIO_CON0_SDIO_CON0_MASK (0xFFFFU << CRU_CRU_SDIO_CON0_SDIO_CON0_SHIFT) /* 0x0000FFFF */ +/* CRU_SDIO_CON1 */ +#define CRU_CRU_SDIO_CON1_OFFSET (0x324) +#define CRU_CRU_SDIO_CON1_SDIO_CON1_SHIFT (0U) +#define CRU_CRU_SDIO_CON1_SDIO_CON1_MASK (0xFFFFU << CRU_CRU_SDIO_CON1_SDIO_CON1_SHIFT) /* 0x0000FFFF */ +/* DCG0_CON0 */ +#define CRU_DCG0_CON0_OFFSET (0x330) +#define CRU_DCG0_CON0_CFG_PERIOD_SHIFT (0U) +#define CRU_DCG0_CON0_CFG_PERIOD_MASK (0xFFFFFFFFU << CRU_DCG0_CON0_CFG_PERIOD_SHIFT) /* 0xFFFFFFFF */ +/* DCG0_CON1 */ +#define CRU_DCG0_CON1_OFFSET (0x334) +#define CRU_DCG0_CON1_CFG_CNT_SHIFT (0U) +#define CRU_DCG0_CON1_CFG_CNT_MASK (0xFFFFFFFFU << CRU_DCG0_CON1_CFG_CNT_SHIFT) /* 0xFFFFFFFF */ +/* DCG0_CON2 */ +#define CRU_DCG0_CON2_OFFSET (0x338) +#define CRU_DCG0_CON2_CFG_PERIOD_SHIFT (0U) +#define CRU_DCG0_CON2_CFG_PERIOD_MASK (0xFFFFFFFFU << CRU_DCG0_CON2_CFG_PERIOD_SHIFT) /* 0xFFFFFFFF */ +/* DCG0_CON3 */ +#define CRU_DCG0_CON3_OFFSET (0x33C) +#define CRU_DCG0_CON3_CFG_CNT_SHIFT (0U) +#define CRU_DCG0_CON3_CFG_CNT_MASK (0xFFFFFFFFU << CRU_DCG0_CON3_CFG_CNT_SHIFT) /* 0xFFFFFFFF */ +/* DCG0_CON4 */ +#define CRU_DCG0_CON4_OFFSET (0x340) +#define CRU_DCG0_CON4_CFG_STEP1_SHIFT (0U) +#define CRU_DCG0_CON4_CFG_STEP1_MASK (0x7FU << CRU_DCG0_CON4_CFG_STEP1_SHIFT) /* 0x0000007F */ +#define CRU_DCG0_CON4_CFG_STEP2_SHIFT (8U) +#define CRU_DCG0_CON4_CFG_STEP2_MASK (0x7FU << CRU_DCG0_CON4_CFG_STEP2_SHIFT) /* 0x00007F00 */ +#define CRU_DCG0_CON4_CFG_EN_SHIFT (15U) +#define CRU_DCG0_CON4_CFG_EN_MASK (0x1U << CRU_DCG0_CON4_CFG_EN_SHIFT) /* 0x00008000 */ +/* DCG0_CON5 */ +#define CRU_DCG0_CON5_OFFSET (0x344) +#define CRU_DCG0_CON5_CFG_LMT_SHIFT (0U) +#define CRU_DCG0_CON5_CFG_LMT_MASK (0x7FU << CRU_DCG0_CON5_CFG_LMT_SHIFT) /* 0x0000007F */ +/* DCG0_CON6 */ +#define CRU_DCG0_CON6_OFFSET (0x348) +/* DCG0_CON7 */ +#define CRU_DCG0_CON7_OFFSET (0x34C) +/* DCG1_CON0 */ +#define CRU_DCG1_CON0_OFFSET (0x350) +#define CRU_DCG1_CON0_CFG_PERIOD_SHIFT (0U) +#define CRU_DCG1_CON0_CFG_PERIOD_MASK (0xFFFFFFFFU << CRU_DCG1_CON0_CFG_PERIOD_SHIFT) /* 0xFFFFFFFF */ +/* DCG1_CON1 */ +#define CRU_DCG1_CON1_OFFSET (0x354) +#define CRU_DCG1_CON1_CFG_CNT_SHIFT (0U) +#define CRU_DCG1_CON1_CFG_CNT_MASK (0xFFFFFFFFU << CRU_DCG1_CON1_CFG_CNT_SHIFT) /* 0xFFFFFFFF */ +/* DCG1_CON2 */ +#define CRU_DCG1_CON2_OFFSET (0x358) +#define CRU_DCG1_CON2_CFG_PERIOD_SHIFT (0U) +#define CRU_DCG1_CON2_CFG_PERIOD_MASK (0xFFFFFFFFU << CRU_DCG1_CON2_CFG_PERIOD_SHIFT) /* 0xFFFFFFFF */ +/* DCG1_CON3 */ +#define CRU_DCG1_CON3_OFFSET (0x35C) +#define CRU_DCG1_CON3_CFG_CNT_SHIFT (0U) +#define CRU_DCG1_CON3_CFG_CNT_MASK (0xFFFFFFFFU << CRU_DCG1_CON3_CFG_CNT_SHIFT) /* 0xFFFFFFFF */ +/* DCG1_CON4 */ +#define CRU_DCG1_CON4_OFFSET (0x360) +#define CRU_DCG1_CON4_CFG_STEP1_SHIFT (0U) +#define CRU_DCG1_CON4_CFG_STEP1_MASK (0x7FU << CRU_DCG1_CON4_CFG_STEP1_SHIFT) /* 0x0000007F */ +#define CRU_DCG1_CON4_CFG_STEP2_SHIFT (8U) +#define CRU_DCG1_CON4_CFG_STEP2_MASK (0x7FU << CRU_DCG1_CON4_CFG_STEP2_SHIFT) /* 0x00007F00 */ +#define CRU_DCG1_CON4_CFG_EN_SHIFT (15U) +#define CRU_DCG1_CON4_CFG_EN_MASK (0x1U << CRU_DCG1_CON4_CFG_EN_SHIFT) /* 0x00008000 */ +/* DCG1_CON5 */ +#define CRU_DCG1_CON5_OFFSET (0x364) +#define CRU_DCG1_CON5_CFG_LMT_SHIFT (0U) +#define CRU_DCG1_CON5_CFG_LMT_MASK (0x7FU << CRU_DCG1_CON5_CFG_LMT_SHIFT) /* 0x0000007F */ +/* DCG1_CON6 */ +#define CRU_DCG1_CON6_OFFSET (0x368) +/* DCG1_CON7 */ +#define CRU_DCG1_CON7_OFFSET (0x36C) +/* AS0_CON0 */ +#define CRU_AS0_CON0_OFFSET (0x400) +#define CRU_AS0_CON0_CNT_TH_SHIFT (0U) +#define CRU_AS0_CON0_CNT_TH_MASK (0xFFFFU << CRU_AS0_CON0_CNT_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AS0_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AS0_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AS0_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AS0_CON1 */ +#define CRU_AS0_CON1_OFFSET (0x404) +#define CRU_AS0_CON1_AS_CTRL_SHIFT (0U) +#define CRU_AS0_CON1_AS_CTRL_MASK (0xFFFU << CRU_AS0_CON1_AS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AS0_CON1_AS_EN_SHIFT (12U) +#define CRU_AS0_CON1_AS_EN_MASK (0x1U << CRU_AS0_CON1_AS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AS0_CON1_ASS_EN_SHIFT (13U) +#define CRU_AS0_CON1_ASS_EN_MASK (0x1U << CRU_AS0_CON1_ASS_EN_SHIFT) /* 0x00002000 */ +#define CRU_AS0_CON1_AS_CFG_SHIFT (14U) +#define CRU_AS0_CON1_AS_CFG_MASK (0x3U << CRU_AS0_CON1_AS_CFG_SHIFT) /* 0x0000C000 */ +/* AS1_CON0 */ +#define CRU_AS1_CON0_OFFSET (0x408) +#define CRU_AS1_CON0_CNT_TH_SHIFT (0U) +#define CRU_AS1_CON0_CNT_TH_MASK (0xFFFFU << CRU_AS1_CON0_CNT_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AS1_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AS1_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AS1_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AS1_CON1 */ +#define CRU_AS1_CON1_OFFSET (0x40C) +#define CRU_AS1_CON1_AS_CTRL_SHIFT (0U) +#define CRU_AS1_CON1_AS_CTRL_MASK (0xFFFU << CRU_AS1_CON1_AS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AS1_CON1_AS_EN_SHIFT (12U) +#define CRU_AS1_CON1_AS_EN_MASK (0x1U << CRU_AS1_CON1_AS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AS1_CON1_ASS_EN_SHIFT (13U) +#define CRU_AS1_CON1_ASS_EN_MASK (0x1U << CRU_AS1_CON1_ASS_EN_SHIFT) /* 0x00002000 */ +#define CRU_AS1_CON1_AS_CFG_SHIFT (14U) +#define CRU_AS1_CON1_AS_CFG_MASK (0x3U << CRU_AS1_CON1_AS_CFG_SHIFT) /* 0x0000C000 */ +/* AS2_CON0 */ +#define CRU_AS2_CON0_OFFSET (0x410) +#define CRU_AS2_CON0_CNT_TH_SHIFT (0U) +#define CRU_AS2_CON0_CNT_TH_MASK (0xFFFFU << CRU_AS2_CON0_CNT_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AS2_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AS2_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AS2_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AS2_CON1 */ +#define CRU_AS2_CON1_OFFSET (0x414) +#define CRU_AS2_CON1_AS_EN_SHIFT (12U) +#define CRU_AS2_CON1_AS_EN_MASK (0x1U << CRU_AS2_CON1_AS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AS2_CON1_ASS_EN_SHIFT (13U) +#define CRU_AS2_CON1_ASS_EN_MASK (0x1U << CRU_AS2_CON1_ASS_EN_SHIFT) /* 0x00002000 */ +#define CRU_AS2_CON1_AS_CFG_SHIFT (14U) +#define CRU_AS2_CON1_AS_CFG_MASK (0x3U << CRU_AS2_CON1_AS_CFG_SHIFT) /* 0x0000C000 */ +/* AS3_CON0 */ +#define CRU_AS3_CON0_OFFSET (0x418) +#define CRU_AS3_CON0_CNT_TH_SHIFT (0U) +#define CRU_AS3_CON0_CNT_TH_MASK (0xFFFFU << CRU_AS3_CON0_CNT_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AS3_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AS3_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AS3_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AS3_CON1 */ +#define CRU_AS3_CON1_OFFSET (0x41C) +#define CRU_AS3_CON1_AS_CTRL_SHIFT (0U) +#define CRU_AS3_CON1_AS_CTRL_MASK (0xFFFU << CRU_AS3_CON1_AS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AS3_CON1_AS_EN_SHIFT (12U) +#define CRU_AS3_CON1_AS_EN_MASK (0x1U << CRU_AS3_CON1_AS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AS3_CON1_ASS_EN_SHIFT (13U) +#define CRU_AS3_CON1_ASS_EN_MASK (0x1U << CRU_AS3_CON1_ASS_EN_SHIFT) /* 0x00002000 */ +#define CRU_AS3_CON1_AS_CFG_SHIFT (14U) +#define CRU_AS3_CON1_AS_CFG_MASK (0x3U << CRU_AS3_CON1_AS_CFG_SHIFT) /* 0x0000C000 */ +/* AS4_CON0 */ +#define CRU_AS4_CON0_OFFSET (0x420) +#define CRU_AS4_CON0_CNT_TH_SHIFT (0U) +#define CRU_AS4_CON0_CNT_TH_MASK (0xFFFFU << CRU_AS4_CON0_CNT_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AS4_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AS4_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AS4_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AS4_CON1 */ +#define CRU_AS4_CON1_OFFSET (0x424) +#define CRU_AS4_CON1_AS_CTRL_SHIFT (0U) +#define CRU_AS4_CON1_AS_CTRL_MASK (0xFFFU << CRU_AS4_CON1_AS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AS4_CON1_AS_EN_SHIFT (12U) +#define CRU_AS4_CON1_AS_EN_MASK (0x1U << CRU_AS4_CON1_AS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AS4_CON1_ASS_EN_SHIFT (13U) +#define CRU_AS4_CON1_ASS_EN_MASK (0x1U << CRU_AS4_CON1_ASS_EN_SHIFT) /* 0x00002000 */ +#define CRU_AS4_CON1_AS_CFG_SHIFT (14U) +#define CRU_AS4_CON1_AS_CFG_MASK (0x3U << CRU_AS4_CON1_AS_CFG_SHIFT) /* 0x0000C000 */ +/******************************************GRF*******************************************/ +/* GPIO0A_IOMUX_L */ +#define GRF_GPIO0A_IOMUX_L_OFFSET (0x0U) +#define GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_SHIFT (0U) +#define GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_SHIFT (4U) +#define GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_SHIFT (8U) +#define GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_SHIFT (12U) +#define GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0A_IOMUX_H */ +#define GRF_GPIO0A_IOMUX_H_OFFSET (0x4U) +#define GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_SHIFT (0U) +#define GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_SHIFT (4U) +#define GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_SHIFT (8U) +#define GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_SHIFT (12U) +#define GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0B_IOMUX_L */ +#define GRF_GPIO0B_IOMUX_L_OFFSET (0x8U) +#define GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_SHIFT (0U) +#define GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_MASK (0xFU << GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_SHIFT (4U) +#define GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_MASK (0xFU << GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_SHIFT (8U) +#define GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_MASK (0xFU << GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_SHIFT (12U) +#define GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_MASK (0xFU << GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0B_IOMUX_H */ +#define GRF_GPIO0B_IOMUX_H_OFFSET (0xCU) +#define GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_SHIFT (0U) +#define GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_MASK (0xFU << GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_SHIFT (4U) +#define GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_MASK (0xFU << GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_SHIFT (8U) +#define GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_MASK (0xFU << GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_SHIFT (12U) +#define GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_MASK (0xFU << GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0C_IOMUX_L */ +#define GRF_GPIO0C_IOMUX_L_OFFSET (0x10U) +#define GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_SHIFT (0U) +#define GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_SHIFT (4U) +#define GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_SHIFT (8U) +#define GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_SHIFT (12U) +#define GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0C_IOMUX_H */ +#define GRF_GPIO0C_IOMUX_H_OFFSET (0x14U) +#define GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_SHIFT (0U) +#define GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_SHIFT (4U) +#define GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_SHIFT (8U) +#define GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_SHIFT (12U) +#define GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0D_IOMUX_L */ +#define GRF_GPIO0D_IOMUX_L_OFFSET (0x18U) +#define GRF_GPIO0D_IOMUX_L_GPIO0D0_SEL_SHIFT (0U) +#define GRF_GPIO0D_IOMUX_L_GPIO0D0_SEL_MASK (0xFU << GRF_GPIO0D_IOMUX_L_GPIO0D0_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_SHIFT (4U) +#define GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_MASK (0xFU << GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO0D_IOMUX_L_GPIO0D2_SEL_SHIFT (8U) +#define GRF_GPIO0D_IOMUX_L_GPIO0D2_SEL_MASK (0xFU << GRF_GPIO0D_IOMUX_L_GPIO0D2_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_SHIFT (12U) +#define GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_MASK (0xFU << GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0D_IOMUX_H */ +#define GRF_GPIO0D_IOMUX_H_OFFSET (0x1CU) +#define GRF_GPIO0D_IOMUX_H_GPIO0D4_SEL_SHIFT (0U) +#define GRF_GPIO0D_IOMUX_H_GPIO0D4_SEL_MASK (0xFU << GRF_GPIO0D_IOMUX_H_GPIO0D4_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_SHIFT (4U) +#define GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_MASK (0xFU << GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_SHIFT (8U) +#define GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_MASK (0xFU << GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO0D_IOMUX_H_GPIO0D7_SEL_SHIFT (12U) +#define GRF_GPIO0D_IOMUX_H_GPIO0D7_SEL_MASK (0xFU << GRF_GPIO0D_IOMUX_H_GPIO0D7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1A_IOMUX_L */ +#define GRF_GPIO1A_IOMUX_L_OFFSET (0x20U) +#define GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_SHIFT (0U) +#define GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_MASK (0xFU << GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_SHIFT (4U) +#define GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_MASK (0xFU << GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_SHIFT (8U) +#define GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_MASK (0xFU << GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_SHIFT (12U) +#define GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_MASK (0xFU << GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1A_IOMUX_H */ +#define GRF_GPIO1A_IOMUX_H_OFFSET (0x24U) +#define GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_SHIFT (0U) +#define GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_MASK (0xFU << GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_SHIFT (4U) +#define GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_MASK (0xFU << GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO1A_IOMUX_H_GPIO1A6_SEL_SHIFT (8U) +#define GRF_GPIO1A_IOMUX_H_GPIO1A6_SEL_MASK (0xFU << GRF_GPIO1A_IOMUX_H_GPIO1A6_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO1A_IOMUX_H_GPIO1A7_SEL_SHIFT (12U) +#define GRF_GPIO1A_IOMUX_H_GPIO1A7_SEL_MASK (0xFU << GRF_GPIO1A_IOMUX_H_GPIO1A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1B_IOMUX_L */ +#define GRF_GPIO1B_IOMUX_L_OFFSET (0x28U) +#define GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_SHIFT (0U) +#define GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_MASK (0xFU << GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_SHIFT (4U) +#define GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_MASK (0xFU << GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_SHIFT (8U) +#define GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_MASK (0xFU << GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_SHIFT (12U) +#define GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_MASK (0xFU << GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1B_IOMUX_H */ +#define GRF_GPIO1B_IOMUX_H_OFFSET (0x2CU) +#define GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_SHIFT (0U) +#define GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_MASK (0xFU << GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_SHIFT (4U) +#define GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_MASK (0xFU << GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_SHIFT (8U) +#define GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_MASK (0xFU << GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_SHIFT (12U) +#define GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_MASK (0xFU << GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1C_IOMUX_L */ +#define GRF_GPIO1C_IOMUX_L_OFFSET (0x30U) +#define GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_SHIFT (0U) +#define GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_MASK (0xFU << GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_SHIFT (4U) +#define GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_MASK (0xFU << GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_SHIFT (8U) +#define GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_MASK (0xFU << GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_SHIFT (12U) +#define GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_MASK (0xFU << GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1C_IOMUX_H */ +#define GRF_GPIO1C_IOMUX_H_OFFSET (0x34U) +#define GRF_GPIO1C_IOMUX_H_GPIO1C4_SEL_SHIFT (0U) +#define GRF_GPIO1C_IOMUX_H_GPIO1C4_SEL_MASK (0xFU << GRF_GPIO1C_IOMUX_H_GPIO1C4_SEL_SHIFT) /* 0x0000000F */ +#define GRF_GPIO1C_IOMUX_H_GPIO1C5_SEL_SHIFT (4U) +#define GRF_GPIO1C_IOMUX_H_GPIO1C5_SEL_MASK (0xFU << GRF_GPIO1C_IOMUX_H_GPIO1C5_SEL_SHIFT) /* 0x000000F0 */ +#define GRF_GPIO1C_IOMUX_H_GPIO1C6_SEL_SHIFT (8U) +#define GRF_GPIO1C_IOMUX_H_GPIO1C6_SEL_MASK (0xFU << GRF_GPIO1C_IOMUX_H_GPIO1C6_SEL_SHIFT) /* 0x00000F00 */ +#define GRF_GPIO1C_IOMUX_H_GPIO1C7_SEL_SHIFT (12U) +#define GRF_GPIO1C_IOMUX_H_GPIO1C7_SEL_MASK (0xFU << GRF_GPIO1C_IOMUX_H_GPIO1C7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1D_IOMUX_L */ +#define GRF_GPIO1D_IOMUX_L_OFFSET (0x38U) +#define GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_SHIFT (0U) +#define GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_MASK (0xFU << GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_SHIFT) /* 0x0000000F */ +/* GPIO0L_SR */ +#define GRF_GPIO0L_SR_OFFSET (0x40U) +#define GRF_GPIO0L_SR_GPIO0A_SR_SHIFT (0U) +#define GRF_GPIO0L_SR_GPIO0A_SR_MASK (0xFFU << GRF_GPIO0L_SR_GPIO0A_SR_SHIFT) /* 0x000000FF */ +#define GRF_GPIO0L_SR_GPIO0B_SR_SHIFT (8U) +#define GRF_GPIO0L_SR_GPIO0B_SR_MASK (0xFFU << GRF_GPIO0L_SR_GPIO0B_SR_SHIFT) /* 0x0000FF00 */ +/* GPIO0H_SR */ +#define GRF_GPIO0H_SR_OFFSET (0x44U) +#define GRF_GPIO0H_SR_GPIO0C_SR_SHIFT (0U) +#define GRF_GPIO0H_SR_GPIO0C_SR_MASK (0xFFU << GRF_GPIO0H_SR_GPIO0C_SR_SHIFT) /* 0x000000FF */ +#define GRF_GPIO0H_SR_GPIO0D_SR_SHIFT (8U) +#define GRF_GPIO0H_SR_GPIO0D_SR_MASK (0xFFU << GRF_GPIO0H_SR_GPIO0D_SR_SHIFT) /* 0x0000FF00 */ +/* GPIO1L_SR */ +#define GRF_GPIO1L_SR_OFFSET (0x48U) +#define GRF_GPIO1L_SR_GPIO1A_SR_SHIFT (0U) +#define GRF_GPIO1L_SR_GPIO1A_SR_MASK (0xFFU << GRF_GPIO1L_SR_GPIO1A_SR_SHIFT) /* 0x000000FF */ +#define GRF_GPIO1L_SR_GPIO1B_SR_SHIFT (8U) +#define GRF_GPIO1L_SR_GPIO1B_SR_MASK (0xFFU << GRF_GPIO1L_SR_GPIO1B_SR_SHIFT) /* 0x0000FF00 */ +/* GPIO1H_SR */ +#define GRF_GPIO1H_SR_OFFSET (0x4CU) +#define GRF_GPIO1H_SR_GPIO1C_SR_SHIFT (0U) +#define GRF_GPIO1H_SR_GPIO1C_SR_MASK (0xFFU << GRF_GPIO1H_SR_GPIO1C_SR_SHIFT) /* 0x000000FF */ +#define GRF_GPIO1H_SR_GPIO1D_SR_SHIFT (8U) +#define GRF_GPIO1H_SR_GPIO1D_SR_MASK (0x1U << GRF_GPIO1H_SR_GPIO1D_SR_SHIFT) /* 0x00000100 */ +/* GPIO0A_P */ +#define GRF_GPIO0A_P_OFFSET (0x80U) +#define GRF_GPIO0A_P_GPIO0A_P_SHIFT (0U) +#define GRF_GPIO0A_P_GPIO0A_P_MASK (0xFFFFU << GRF_GPIO0A_P_GPIO0A_P_SHIFT) /* 0x0000FFFF */ +/* GPIO0B_P */ +#define GRF_GPIO0B_P_OFFSET (0x84U) +#define GRF_GPIO0B_P_GPIO0B_P_SHIFT (0U) +#define GRF_GPIO0B_P_GPIO0B_P_MASK (0xFFFFU << GRF_GPIO0B_P_GPIO0B_P_SHIFT) /* 0x0000FFFF */ +/* GPIO0C_P */ +#define GRF_GPIO0C_P_OFFSET (0x88U) +#define GRF_GPIO0C_P_GPIO0C_P_SHIFT (0U) +#define GRF_GPIO0C_P_GPIO0C_P_MASK (0xFFFFU << GRF_GPIO0C_P_GPIO0C_P_SHIFT) /* 0x0000FFFF */ +/* GPIO0D_P */ +#define GRF_GPIO0D_P_OFFSET (0x8CU) +#define GRF_GPIO0D_P_GPIO0D_P_SHIFT (0U) +#define GRF_GPIO0D_P_GPIO0D_P_MASK (0xFFFFU << GRF_GPIO0D_P_GPIO0D_P_SHIFT) /* 0x0000FFFF */ +/* GPIO1A_P */ +#define GRF_GPIO1A_P_OFFSET (0x90U) +#define GRF_GPIO1A_P_GPIO1A_P_SHIFT (0U) +#define GRF_GPIO1A_P_GPIO1A_P_MASK (0xFFFFU << GRF_GPIO1A_P_GPIO1A_P_SHIFT) /* 0x0000FFFF */ +/* GPIO1B_P */ +#define GRF_GPIO1B_P_OFFSET (0x94U) +#define GRF_GPIO1B_P_GPIO1B_P_SHIFT (0U) +#define GRF_GPIO1B_P_GPIO1B_P_MASK (0xFFFFU << GRF_GPIO1B_P_GPIO1B_P_SHIFT) /* 0x0000FFFF */ +/* GPIO1C_P */ +#define GRF_GPIO1C_P_OFFSET (0x98U) +#define GRF_GPIO1C_P_GPIO1C_P_SHIFT (0U) +#define GRF_GPIO1C_P_GPIO1C_P_MASK (0xFFFFU << GRF_GPIO1C_P_GPIO1C_P_SHIFT) /* 0x0000FFFF */ +/* GPIO1D_P */ +#define GRF_GPIO1D_P_OFFSET (0x9CU) +#define GRF_GPIO1D_P_GPIO1D_P_SHIFT (0U) +#define GRF_GPIO1D_P_GPIO1D_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D_P_SHIFT) /* 0x00000003 */ +/* GPIO0A_E */ +#define GRF_GPIO0A_E_OFFSET (0xC0U) +#define GRF_GPIO0A_E_GPIO0A_E_SHIFT (0U) +#define GRF_GPIO0A_E_GPIO0A_E_MASK (0xFFFFU << GRF_GPIO0A_E_GPIO0A_E_SHIFT) /* 0x0000FFFF */ +/* GPIO0B_E */ +#define GRF_GPIO0B_E_OFFSET (0xC4U) +#define GRF_GPIO0B_E_GPIO0B_E_SHIFT (0U) +#define GRF_GPIO0B_E_GPIO0B_E_MASK (0xFFFFU << GRF_GPIO0B_E_GPIO0B_E_SHIFT) /* 0x0000FFFF */ +/* GPIO0C_E */ +#define GRF_GPIO0C_E_OFFSET (0xC8U) +#define GRF_GPIO0C_E_GPIO0C_E_SHIFT (0U) +#define GRF_GPIO0C_E_GPIO0C_E_MASK (0xFFFFU << GRF_GPIO0C_E_GPIO0C_E_SHIFT) /* 0x0000FFFF */ +/* GPIO0D_E */ +#define GRF_GPIO0D_E_OFFSET (0xCCU) +#define GRF_GPIO0D_E_GPIO0D_E_SHIFT (0U) +#define GRF_GPIO0D_E_GPIO0D_E_MASK (0xFFFFU << GRF_GPIO0D_E_GPIO0D_E_SHIFT) /* 0x0000FFFF */ +/* GPIO1A_E */ +#define GRF_GPIO1A_E_OFFSET (0xD0U) +#define GRF_GPIO1A_E_GPIO1A_E_SHIFT (0U) +#define GRF_GPIO1A_E_GPIO1A_E_MASK (0xFFFFU << GRF_GPIO1A_E_GPIO1A_E_SHIFT) /* 0x0000FFFF */ +/* GPIO1B_E */ +#define GRF_GPIO1B_E_OFFSET (0xD4U) +#define GRF_GPIO1B_E_GPIO1B_E_SHIFT (0U) +#define GRF_GPIO1B_E_GPIO1B_E_MASK (0xFFFFU << GRF_GPIO1B_E_GPIO1B_E_SHIFT) /* 0x0000FFFF */ +/* GPIO1C_E */ +#define GRF_GPIO1C_E_OFFSET (0xD8U) +#define GRF_GPIO1C_E_GPIO1C_E_SHIFT (0U) +#define GRF_GPIO1C_E_GPIO1C_E_MASK (0xFFFFU << GRF_GPIO1C_E_GPIO1C_E_SHIFT) /* 0x0000FFFF */ +/* GPIO1D_E */ +#define GRF_GPIO1D_E_OFFSET (0xDCU) +#define GRF_GPIO1D_E_GPIO1D_E_SHIFT (0U) +#define GRF_GPIO1D_E_GPIO1D_E_MASK (0x3U << GRF_GPIO1D_E_GPIO1D_E_SHIFT) /* 0x00000003 */ +/* CHIP_VERSION_ID */ +#define GRF_CHIP_VERSION_ID_OFFSET (0xF0U) +#define GRF_CHIP_VERSION_ID (0x0U) +#define GRF_CHIP_VERSION_ID_CHIP_VERSION_ID_SHIFT (0U) +#define GRF_CHIP_VERSION_ID_CHIP_VERSION_ID_MASK (0xFFFFFFFFU << GRF_CHIP_VERSION_ID_CHIP_VERSION_ID_SHIFT) /* 0xFFFFFFFF */ +/* CHIP_IDL */ +#define GRF_CHIP_IDL_OFFSET (0xF4U) +#define GRF_CHIP_IDL (0x4F4C5043U) +#define GRF_CHIP_IDL_CHIP_IDL_SHIFT (0U) +#define GRF_CHIP_IDL_CHIP_IDL_MASK (0xFFFFFFFFU << GRF_CHIP_IDL_CHIP_IDL_SHIFT) /* 0xFFFFFFFF */ +/* CHIP_IDH */ +#define GRF_CHIP_IDH_OFFSET (0xF8U) +#define GRF_CHIP_IDH (0x6F70706FU) +#define GRF_CHIP_IDH_CHIP_IDH_SHIFT (0U) +#define GRF_CHIP_IDH_CHIP_IDH_MASK (0xFFFFFFFFU << GRF_CHIP_IDH_CHIP_IDH_SHIFT) /* 0xFFFFFFFF */ +/* SOC_CON0 */ +#define GRF_SOC_CON0_OFFSET (0x100U) +#define GRF_SOC_CON0_I2C_FLT_F_SHIFT (0U) +#define GRF_SOC_CON0_I2C_FLT_F_MASK (0xFU << GRF_SOC_CON0_I2C_FLT_F_SHIFT) /* 0x0000000F */ +#define GRF_SOC_CON0_I2C_FLT_R_SHIFT (4U) +#define GRF_SOC_CON0_I2C_FLT_R_MASK (0xFU << GRF_SOC_CON0_I2C_FLT_R_SHIFT) /* 0x000000F0 */ +#define GRF_SOC_CON0_UART0_RTS_SEL_SHIFT (8U) +#define GRF_SOC_CON0_UART0_RTS_SEL_MASK (0x1U << GRF_SOC_CON0_UART0_RTS_SEL_SHIFT) /* 0x00000100 */ +#define GRF_SOC_CON0_UART0_CTS_SEL_SHIFT (9U) +#define GRF_SOC_CON0_UART0_CTS_SEL_MASK (0x1U << GRF_SOC_CON0_UART0_CTS_SEL_SHIFT) /* 0x00000200 */ +#define GRF_SOC_CON0_UART2_RTS_SEL_SHIFT (12U) +#define GRF_SOC_CON0_UART2_RTS_SEL_MASK (0x1U << GRF_SOC_CON0_UART2_RTS_SEL_SHIFT) /* 0x00001000 */ +#define GRF_SOC_CON0_UART2_CTS_SEL_SHIFT (13U) +#define GRF_SOC_CON0_UART2_CTS_SEL_MASK (0x1U << GRF_SOC_CON0_UART2_CTS_SEL_SHIFT) /* 0x00002000 */ +#define GRF_SOC_CON0_VOP_TE_SEL_SHIFT (14U) +#define GRF_SOC_CON0_VOP_TE_SEL_MASK (0x3U << GRF_SOC_CON0_VOP_TE_SEL_SHIFT) /* 0x0000C000 */ +/* SOC_CON1 */ +#define GRF_SOC_CON1_OFFSET (0x104U) +#define GRF_SOC_CON1_TOP_FWD_DSP_STALL_SHIFT (0U) +#define GRF_SOC_CON1_TOP_FWD_DSP_STALL_MASK (0x1U << GRF_SOC_CON1_TOP_FWD_DSP_STALL_SHIFT) /* 0x00000001 */ +#define GRF_SOC_CON1_DSP_FWD_TOP_STALL_SHIFT (1U) +#define GRF_SOC_CON1_DSP_FWD_TOP_STALL_MASK (0x1U << GRF_SOC_CON1_DSP_FWD_TOP_STALL_SHIFT) /* 0x00000002 */ +#define GRF_SOC_CON1_TOP_FWD_SHRM0_STALL_SHIFT (2U) +#define GRF_SOC_CON1_TOP_FWD_SHRM0_STALL_MASK (0x1U << GRF_SOC_CON1_TOP_FWD_SHRM0_STALL_SHIFT) /* 0x00000004 */ +#define GRF_SOC_CON1_TOP_FWD_SHRM1_STALL_SHIFT (3U) +#define GRF_SOC_CON1_TOP_FWD_SHRM1_STALL_MASK (0x1U << GRF_SOC_CON1_TOP_FWD_SHRM1_STALL_SHIFT) /* 0x00000008 */ +#define GRF_SOC_CON1_TOP_FWD_SHRM2_STALL_SHIFT (4U) +#define GRF_SOC_CON1_TOP_FWD_SHRM2_STALL_MASK (0x1U << GRF_SOC_CON1_TOP_FWD_SHRM2_STALL_SHIFT) /* 0x00000010 */ +#define GRF_SOC_CON1_TOP_FWD_AUDIO_STALL_SHIFT (5U) +#define GRF_SOC_CON1_TOP_FWD_AUDIO_STALL_MASK (0x1U << GRF_SOC_CON1_TOP_FWD_AUDIO_STALL_SHIFT) /* 0x00000020 */ +#define GRF_SOC_CON1_TOP_FWD_ALIVE_STALL_SHIFT (6U) +#define GRF_SOC_CON1_TOP_FWD_ALIVE_STALL_MASK (0x1U << GRF_SOC_CON1_TOP_FWD_ALIVE_STALL_SHIFT) /* 0x00000040 */ +#define GRF_SOC_CON1_AUDIO_FWD_TOP_STALL_SHIFT (7U) +#define GRF_SOC_CON1_AUDIO_FWD_TOP_STALL_MASK (0x1U << GRF_SOC_CON1_AUDIO_FWD_TOP_STALL_SHIFT) /* 0x00000080 */ +#define GRF_SOC_CON1_AUDIO_FWD_DSP_STALL_SHIFT (8U) +#define GRF_SOC_CON1_AUDIO_FWD_DSP_STALL_MASK (0x1U << GRF_SOC_CON1_AUDIO_FWD_DSP_STALL_SHIFT) /* 0x00000100 */ +#define GRF_SOC_CON1_DSP_FWD_ALIVE_STALL_SHIFT (9U) +#define GRF_SOC_CON1_DSP_FWD_ALIVE_STALL_MASK (0x1U << GRF_SOC_CON1_DSP_FWD_ALIVE_STALL_SHIFT) /* 0x00000200 */ +#define GRF_SOC_CON1_DSP_FWD_AUDIO_STALL_SHIFT (10U) +#define GRF_SOC_CON1_DSP_FWD_AUDIO_STALL_MASK (0x1U << GRF_SOC_CON1_DSP_FWD_AUDIO_STALL_SHIFT) /* 0x00000400 */ +#define GRF_SOC_CON1_DPISHUTDN_SHIFT (12U) +#define GRF_SOC_CON1_DPISHUTDN_MASK (0x1U << GRF_SOC_CON1_DPISHUTDN_SHIFT) /* 0x00001000 */ +#define GRF_SOC_CON1_DPICOLORM_SHIFT (13U) +#define GRF_SOC_CON1_DPICOLORM_MASK (0x1U << GRF_SOC_CON1_DPICOLORM_SHIFT) /* 0x00002000 */ +#define GRF_SOC_CON1_DPIUPDATECFG_SHIFT (14U) +#define GRF_SOC_CON1_DPIUPDATECFG_MASK (0x1U << GRF_SOC_CON1_DPIUPDATECFG_SHIFT) /* 0x00004000 */ +#define GRF_SOC_CON1_PHYLOCK_SHIFT (15U) +#define GRF_SOC_CON1_PHYLOCK_MASK (0x1U << GRF_SOC_CON1_PHYLOCK_SHIFT) /* 0x00008000 */ +/* SOC_CON2 */ +#define GRF_SOC_CON2_OFFSET (0x108U) +#define GRF_SOC_CON2_GRF_CON_AUDIO_BYPASS_EN_SHIFT (0U) +#define GRF_SOC_CON2_GRF_CON_AUDIO_BYPASS_EN_MASK (0x1U << GRF_SOC_CON2_GRF_CON_AUDIO_BYPASS_EN_SHIFT) /* 0x00000001 */ +#define GRF_SOC_CON2_GRF_CON_I2S_BYPASS_MST_SHIFT (1U) +#define GRF_SOC_CON2_GRF_CON_I2S_BYPASS_MST_MASK (0x1U << GRF_SOC_CON2_GRF_CON_I2S_BYPASS_MST_SHIFT) /* 0x00000002 */ +#define GRF_SOC_CON2_GRF_CON_CODEC_SEL_SHIFT (2U) +#define GRF_SOC_CON2_GRF_CON_CODEC_SEL_MASK (0x1U << GRF_SOC_CON2_GRF_CON_CODEC_SEL_SHIFT) /* 0x00000004 */ +#define GRF_SOC_CON2_GRF_CON_I2S_LRCK_MUX_SHIFT (3U) +#define GRF_SOC_CON2_GRF_CON_I2S_LRCK_MUX_MASK (0x1U << GRF_SOC_CON2_GRF_CON_I2S_LRCK_MUX_SHIFT) /* 0x00000008 */ +#define GRF_SOC_CON2_GRF_CON_I2S_SCLK_MUX_SHIFT (4U) +#define GRF_SOC_CON2_GRF_CON_I2S_SCLK_MUX_MASK (0x1U << GRF_SOC_CON2_GRF_CON_I2S_SCLK_MUX_SHIFT) /* 0x00000010 */ +#define GRF_SOC_CON2_GRF_CON_I2S_IN_MCLK_SRC_SHIFT (5U) +#define GRF_SOC_CON2_GRF_CON_I2S_IN_MCLK_SRC_MASK (0x1U << GRF_SOC_CON2_GRF_CON_I2S_IN_MCLK_SRC_SHIFT) /* 0x00000020 */ +#define GRF_SOC_CON2_GRF_CON_I2S_IN_MCLK_OUT_EN_SHIFT (6U) +#define GRF_SOC_CON2_GRF_CON_I2S_IN_MCLK_OUT_EN_MASK (0x1U << GRF_SOC_CON2_GRF_CON_I2S_IN_MCLK_OUT_EN_SHIFT) /* 0x00000040 */ +#define GRF_SOC_CON2_GRF_CON_I2S_OUT_MCLK_OUT_EN_SHIFT (7U) +#define GRF_SOC_CON2_GRF_CON_I2S_OUT_MCLK_OUT_EN_MASK (0x1U << GRF_SOC_CON2_GRF_CON_I2S_OUT_MCLK_OUT_EN_SHIFT) /* 0x00000080 */ +#define GRF_SOC_CON2_GRF_CON_PDM_IN_CLK0_BY_CLK_SEL_SHIFT (8U) +#define GRF_SOC_CON2_GRF_CON_PDM_IN_CLK0_BY_CLK_SEL_MASK (0x1U << GRF_SOC_CON2_GRF_CON_PDM_IN_CLK0_BY_CLK_SEL_SHIFT) /* 0x00000100 */ +#define GRF_SOC_CON2_GRF_CON_PDM_IN_CLK1_BY_CLK_SEL_SHIFT (9U) +#define GRF_SOC_CON2_GRF_CON_PDM_IN_CLK1_BY_CLK_SEL_MASK (0x1U << GRF_SOC_CON2_GRF_CON_PDM_IN_CLK1_BY_CLK_SEL_SHIFT) /* 0x00000200 */ +#define GRF_SOC_CON2_GRF_CON_PDM_IN_CLK_BY_CLK_CRU_SEL_SHIFT (10U) +#define GRF_SOC_CON2_GRF_CON_PDM_IN_CLK_BY_CLK_CRU_SEL_MASK (0x1U << GRF_SOC_CON2_GRF_CON_PDM_IN_CLK_BY_CLK_CRU_SEL_SHIFT) /* 0x00000400 */ +#define GRF_SOC_CON2_GRF_CON_PDM_OUT_CLK_OE_SHIFT (11U) +#define GRF_SOC_CON2_GRF_CON_PDM_OUT_CLK_OE_MASK (0x1U << GRF_SOC_CON2_GRF_CON_PDM_OUT_CLK_OE_SHIFT) /* 0x00000800 */ +#define GRF_SOC_CON2_GRF_CON_PDM_COMB_EN_SHIFT (12U) +#define GRF_SOC_CON2_GRF_CON_PDM_COMB_EN_MASK (0x1U << GRF_SOC_CON2_GRF_CON_PDM_COMB_EN_SHIFT) /* 0x00001000 */ +#define GRF_SOC_CON2_GRF_CON_PDM_COMB_LR_SEL_SHIFT (13U) +#define GRF_SOC_CON2_GRF_CON_PDM_COMB_LR_SEL_MASK (0x1U << GRF_SOC_CON2_GRF_CON_PDM_COMB_LR_SEL_SHIFT) /* 0x00002000 */ +#define GRF_SOC_CON2_GRF_CON_PDM_COMB_BY_CLK_SEL_SHIFT (14U) +#define GRF_SOC_CON2_GRF_CON_PDM_COMB_BY_CLK_SEL_MASK (0x1U << GRF_SOC_CON2_GRF_CON_PDM_COMB_BY_CLK_SEL_SHIFT) /* 0x00004000 */ +#define GRF_SOC_CON2_GRF_CON_AUDIO_BYPASS_CTRL_SEL_SHIFT (15U) +#define GRF_SOC_CON2_GRF_CON_AUDIO_BYPASS_CTRL_SEL_MASK (0x1U << GRF_SOC_CON2_GRF_CON_AUDIO_BYPASS_CTRL_SEL_SHIFT) /* 0x00008000 */ +/* SOC_CON3 */ +#define GRF_SOC_CON3_OFFSET (0x10CU) +#define GRF_SOC_CON3_GRF_CON_MCLK_DIV2_SEL_SHIFT (0U) +#define GRF_SOC_CON3_GRF_CON_MCLK_DIV2_SEL_MASK (0x1U << GRF_SOC_CON3_GRF_CON_MCLK_DIV2_SEL_SHIFT) /* 0x00000001 */ +#define GRF_SOC_CON3_GRF_CON_MAINCLKIN_SMT_SHIFT (1U) +#define GRF_SOC_CON3_GRF_CON_MAINCLKIN_SMT_MASK (0x3U << GRF_SOC_CON3_GRF_CON_MAINCLKIN_SMT_SHIFT) /* 0x00000006 */ +#define GRF_SOC_CON3_GRF_CON_OSC_S_SHIFT (4U) +#define GRF_SOC_CON3_GRF_CON_OSC_S_MASK (0x1FU << GRF_SOC_CON3_GRF_CON_OSC_S_SHIFT) /* 0x000001F0 */ +#define GRF_SOC_CON3_GRF_CON_OSC_FEB_SHIFT (9U) +#define GRF_SOC_CON3_GRF_CON_OSC_FEB_MASK (0x1U << GRF_SOC_CON3_GRF_CON_OSC_FEB_SHIFT) /* 0x00000200 */ +#define GRF_SOC_CON3_GRF_CON_MIPI_SWITCH_EN_PRO_BYP_SHIFT (12U) +#define GRF_SOC_CON3_GRF_CON_MIPI_SWITCH_EN_PRO_BYP_MASK (0x1U << GRF_SOC_CON3_GRF_CON_MIPI_SWITCH_EN_PRO_BYP_SHIFT) /* 0x00001000 */ +/* SOC_CON4 */ +#define GRF_SOC_CON4_OFFSET (0x110U) +#define GRF_SOC_CON4_GRF_CON_MIPI_SWITCH_CTRL_SHIFT (0U) +#define GRF_SOC_CON4_GRF_CON_MIPI_SWITCH_CTRL_MASK (0x1U << GRF_SOC_CON4_GRF_CON_MIPI_SWITCH_CTRL_SHIFT) /* 0x00000001 */ +#define GRF_SOC_CON4_GRF_CON_LCD_RESET_TE_BYPASS_SHIFT (1U) +#define GRF_SOC_CON4_GRF_CON_LCD_RESET_TE_BYPASS_MASK (0x1U << GRF_SOC_CON4_GRF_CON_LCD_RESET_TE_BYPASS_SHIFT) /* 0x00000002 */ +#define GRF_SOC_CON4_GRF_CON_LCD_RESETN_SHIFT (2U) +#define GRF_SOC_CON4_GRF_CON_LCD_RESETN_MASK (0x1U << GRF_SOC_CON4_GRF_CON_LCD_RESETN_SHIFT) /* 0x00000004 */ +#define GRF_SOC_CON4_GRF_CON_LDO_OUT_PWR_EN_SHIFT (3U) +#define GRF_SOC_CON4_GRF_CON_LDO_OUT_PWR_EN_MASK (0x1U << GRF_SOC_CON4_GRF_CON_LDO_OUT_PWR_EN_SHIFT) /* 0x00000008 */ +#define GRF_SOC_CON4_GRF_CON_TP_RESETN_SHIFT (4U) +#define GRF_SOC_CON4_GRF_CON_TP_RESETN_MASK (0x1U << GRF_SOC_CON4_GRF_CON_TP_RESETN_SHIFT) /* 0x00000010 */ +#define GRF_SOC_CON4_GRF_CON_CLK_OUT_EN_SHIFT (5U) +#define GRF_SOC_CON4_GRF_CON_CLK_OUT_EN_MASK (0x1U << GRF_SOC_CON4_GRF_CON_CLK_OUT_EN_SHIFT) /* 0x00000020 */ +#define GRF_SOC_CON4_GRF_CON_MIPI_SWITCH_CTRL_SEL_SHIFT (6U) +#define GRF_SOC_CON4_GRF_CON_MIPI_SWITCH_CTRL_SEL_MASK (0x1U << GRF_SOC_CON4_GRF_CON_MIPI_SWITCH_CTRL_SEL_SHIFT) /* 0x00000040 */ +#define GRF_SOC_CON4_GRF_CON_I2S_BYPASS_PROC_EN_SHIFT (7U) +#define GRF_SOC_CON4_GRF_CON_I2S_BYPASS_PROC_EN_MASK (0x1U << GRF_SOC_CON4_GRF_CON_I2S_BYPASS_PROC_EN_SHIFT) /* 0x00000080 */ +#define GRF_SOC_CON4_GRF_CON_AUDIO_PRO_APP_PDM_SHIFT (8U) +#define GRF_SOC_CON4_GRF_CON_AUDIO_PRO_APP_PDM_MASK (0x1U << GRF_SOC_CON4_GRF_CON_AUDIO_PRO_APP_PDM_SHIFT) /* 0x00000100 */ +#define GRF_SOC_CON4_GRF_CON_AUDIO_PRO_APP_I2S1_SHIFT (9U) +#define GRF_SOC_CON4_GRF_CON_AUDIO_PRO_APP_I2S1_MASK (0x1U << GRF_SOC_CON4_GRF_CON_AUDIO_PRO_APP_I2S1_SHIFT) /* 0x00000200 */ +#define GRF_SOC_CON4_GRF_CON_I2S1_SDI2_FROM_IO_SHIFT (10U) +#define GRF_SOC_CON4_GRF_CON_I2S1_SDI2_FROM_IO_MASK (0x1U << GRF_SOC_CON4_GRF_CON_I2S1_SDI2_FROM_IO_SHIFT) /* 0x00000400 */ +#define GRF_SOC_CON4_GRF_CON_BT_PCM_I2S0_SHIFT (11U) +#define GRF_SOC_CON4_GRF_CON_BT_PCM_I2S0_MASK (0x1U << GRF_SOC_CON4_GRF_CON_BT_PCM_I2S0_SHIFT) /* 0x00000800 */ +#define GRF_SOC_CON4_GRF_CON_USB2_DBNCE_FLTR_BYPASS_SHIFT (13U) +#define GRF_SOC_CON4_GRF_CON_USB2_DBNCE_FLTR_BYPASS_MASK (0x1U << GRF_SOC_CON4_GRF_CON_USB2_DBNCE_FLTR_BYPASS_SHIFT) /* 0x00002000 */ +#define GRF_SOC_CON4_GRF_CON_USB2_SCALEDOWN_MODE_SHIFT (14U) +#define GRF_SOC_CON4_GRF_CON_USB2_SCALEDOWN_MODE_MASK (0x3U << GRF_SOC_CON4_GRF_CON_USB2_SCALEDOWN_MODE_SHIFT) /* 0x0000C000 */ +/* SOC_CON5 */ +#define GRF_SOC_CON5_OFFSET (0x114U) +#define GRF_SOC_CON5_GRF_CON_I2C_MST0_IOMUX_SEL_SHIFT (0U) +#define GRF_SOC_CON5_GRF_CON_I2C_MST0_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON5_GRF_CON_I2C_MST0_IOMUX_SEL_SHIFT) /* 0x00000003 */ +#define GRF_SOC_CON5_GRF_CON_I2C_MST1_IOMUX_SEL_SHIFT (2U) +#define GRF_SOC_CON5_GRF_CON_I2C_MST1_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON5_GRF_CON_I2C_MST1_IOMUX_SEL_SHIFT) /* 0x0000000C */ +#define GRF_SOC_CON5_GRF_CON_I2C_MST2_IOMUX_SEL_SHIFT (4U) +#define GRF_SOC_CON5_GRF_CON_I2C_MST2_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON5_GRF_CON_I2C_MST2_IOMUX_SEL_SHIFT) /* 0x00000030 */ +#define GRF_SOC_CON5_GRF_CON_PCM_IOMUX_SEL_SHIFT (6U) +#define GRF_SOC_CON5_GRF_CON_PCM_IOMUX_SEL_MASK (0x1U << GRF_SOC_CON5_GRF_CON_PCM_IOMUX_SEL_SHIFT) /* 0x00000040 */ +#define GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_SHIFT (7U) +#define GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_SHIFT) /* 0x00000180 */ +#define GRF_SOC_CON5_GRF_CON_SPI_MST1_IOMUX_SEL_SHIFT (9U) +#define GRF_SOC_CON5_GRF_CON_SPI_MST1_IOMUX_SEL_MASK (0x1U << GRF_SOC_CON5_GRF_CON_SPI_MST1_IOMUX_SEL_SHIFT) /* 0x00000200 */ +#define GRF_SOC_CON5_GRF_CON_SPI_MST2_IOMUX_SEL_SHIFT (10U) +#define GRF_SOC_CON5_GRF_CON_SPI_MST2_IOMUX_SEL_MASK (0x1U << GRF_SOC_CON5_GRF_CON_SPI_MST2_IOMUX_SEL_SHIFT) /* 0x00000400 */ +#define GRF_SOC_CON5_GRF_CON_I2S1_IOMUX_SEL_SHIFT (11U) +#define GRF_SOC_CON5_GRF_CON_I2S1_IOMUX_SEL_MASK (0x1U << GRF_SOC_CON5_GRF_CON_I2S1_IOMUX_SEL_SHIFT) /* 0x00000800 */ +#define GRF_SOC_CON5_GRF_CON_PCMCLK_IOMUX_SEL_SHIFT (12U) +#define GRF_SOC_CON5_GRF_CON_PCMCLK_IOMUX_SEL_MASK (0x1U << GRF_SOC_CON5_GRF_CON_PCMCLK_IOMUX_SEL_SHIFT) /* 0x00001000 */ +#define GRF_SOC_CON5_GRF_CON_KEY_IOMUX_SEL_SHIFT (13U) +#define GRF_SOC_CON5_GRF_CON_KEY_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON5_GRF_CON_KEY_IOMUX_SEL_SHIFT) /* 0x00006000 */ +/* SOC_STATUS0 */ +#define GRF_SOC_STATUS0_OFFSET (0x140U) +#define GRF_SOC_STATUS0 (0x0U) +#define GRF_SOC_STATUS0_DSP_FWD_TOP_PWRACT_SHIFT (0U) +#define GRF_SOC_STATUS0_DSP_FWD_TOP_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_DSP_FWD_TOP_PWRACT_SHIFT) /* 0x00000001 */ +#define GRF_SOC_STATUS0_TOP_FWD_DSP_PWRACT_SHIFT (1U) +#define GRF_SOC_STATUS0_TOP_FWD_DSP_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_TOP_FWD_DSP_PWRACT_SHIFT) /* 0x00000002 */ +#define GRF_SOC_STATUS0_TOP_FWD_SHRM0_PWRACT_SHIFT (2U) +#define GRF_SOC_STATUS0_TOP_FWD_SHRM0_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_TOP_FWD_SHRM0_PWRACT_SHIFT) /* 0x00000004 */ +#define GRF_SOC_STATUS0_TOP_FWD_SHRM1_PWRACT_SHIFT (3U) +#define GRF_SOC_STATUS0_TOP_FWD_SHRM1_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_TOP_FWD_SHRM1_PWRACT_SHIFT) /* 0x00000008 */ +#define GRF_SOC_STATUS0_TOP_FWD_SHRM2_PWRACT_SHIFT (4U) +#define GRF_SOC_STATUS0_TOP_FWD_SHRM2_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_TOP_FWD_SHRM2_PWRACT_SHIFT) /* 0x00000010 */ +#define GRF_SOC_STATUS0_TOP_FWD_AUDIO_PWRACT_SHIFT (5U) +#define GRF_SOC_STATUS0_TOP_FWD_AUDIO_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_TOP_FWD_AUDIO_PWRACT_SHIFT) /* 0x00000020 */ +#define GRF_SOC_STATUS0_TOP_FWD_ALIVE_PWRACT_SHIFT (6U) +#define GRF_SOC_STATUS0_TOP_FWD_ALIVE_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_TOP_FWD_ALIVE_PWRACT_SHIFT) /* 0x00000040 */ +#define GRF_SOC_STATUS0_AUDIO_FWD_TOP_PWRACT_SHIFT (7U) +#define GRF_SOC_STATUS0_AUDIO_FWD_TOP_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_AUDIO_FWD_TOP_PWRACT_SHIFT) /* 0x00000080 */ +#define GRF_SOC_STATUS0_AUDIO_FWD_DSP_PWRACT_SHIFT (8U) +#define GRF_SOC_STATUS0_AUDIO_FWD_DSP_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_AUDIO_FWD_DSP_PWRACT_SHIFT) /* 0x00000100 */ +#define GRF_SOC_STATUS0_DSP_FWD_ALIVE_PWRACT_SHIFT (9U) +#define GRF_SOC_STATUS0_DSP_FWD_ALIVE_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_DSP_FWD_ALIVE_PWRACT_SHIFT) /* 0x00000200 */ +#define GRF_SOC_STATUS0_DSP_FWD_AUDIO_PWRACT_SHIFT (10U) +#define GRF_SOC_STATUS0_DSP_FWD_AUDIO_PWRACT_MASK (0x1U << GRF_SOC_STATUS0_DSP_FWD_AUDIO_PWRACT_SHIFT) /* 0x00000400 */ +/* SOC_STATUS1 */ +#define GRF_SOC_STATUS1_OFFSET (0x144U) +#define GRF_SOC_STATUS1 (0x0U) +#define GRF_SOC_STATUS1_IO_LCD_IN_TE_SHIFT (0U) +#define GRF_SOC_STATUS1_IO_LCD_IN_TE_MASK (0x1U << GRF_SOC_STATUS1_IO_LCD_IN_TE_SHIFT) /* 0x00000001 */ +#define GRF_SOC_STATUS1_IO_LCD_IN_RESETN_SHIFT (1U) +#define GRF_SOC_STATUS1_IO_LCD_IN_RESETN_MASK (0x1U << GRF_SOC_STATUS1_IO_LCD_IN_RESETN_SHIFT) /* 0x00000002 */ +#define GRF_SOC_STATUS1_TP_INT_SHIFT (2U) +#define GRF_SOC_STATUS1_TP_INT_MASK (0x1U << GRF_SOC_STATUS1_TP_INT_SHIFT) /* 0x00000004 */ +#define GRF_SOC_STATUS1_CLK_SRC_SEL_SHIFT (3U) +#define GRF_SOC_STATUS1_CLK_SRC_SEL_MASK (0x1U << GRF_SOC_STATUS1_CLK_SRC_SEL_SHIFT) /* 0x00000008 */ +#define GRF_SOC_STATUS1_OSC_CLKSRC_SEL_SHIFT (4U) +#define GRF_SOC_STATUS1_OSC_CLKSRC_SEL_MASK (0x1U << GRF_SOC_STATUS1_OSC_CLKSRC_SEL_SHIFT) /* 0x00000010 */ +#define GRF_SOC_STATUS1_BOOT_SEL_SHIFT (5U) +#define GRF_SOC_STATUS1_BOOT_SEL_MASK (0x1U << GRF_SOC_STATUS1_BOOT_SEL_SHIFT) /* 0x00000020 */ +#define GRF_SOC_STATUS1_BOOT_DEVICE_SEL_SHIFT (6U) +#define GRF_SOC_STATUS1_BOOT_DEVICE_SEL_MASK (0x1U << GRF_SOC_STATUS1_BOOT_DEVICE_SEL_SHIFT) /* 0x00000040 */ +#define GRF_SOC_STATUS1_AP_WAKEUP_OLPC_SHIFT (7U) +#define GRF_SOC_STATUS1_AP_WAKEUP_OLPC_MASK (0x1U << GRF_SOC_STATUS1_AP_WAKEUP_OLPC_SHIFT) /* 0x00000080 */ +#define GRF_SOC_STATUS1_AUDIO_BYPASS_EN_POST_SHIFT (8U) +#define GRF_SOC_STATUS1_AUDIO_BYPASS_EN_POST_MASK (0x1U << GRF_SOC_STATUS1_AUDIO_BYPASS_EN_POST_SHIFT) /* 0x00000100 */ +/* DSP_CON0 */ +#define GRF_DSP_CON0_OFFSET (0x160U) +#define GRF_DSP_CON0_OCDHALTONRESET_SHIFT (0U) +#define GRF_DSP_CON0_OCDHALTONRESET_MASK (0x1U << GRF_DSP_CON0_OCDHALTONRESET_SHIFT) /* 0x00000001 */ +#define GRF_DSP_CON0_BREAKIN_SHIFT (1U) +#define GRF_DSP_CON0_BREAKIN_MASK (0x1U << GRF_DSP_CON0_BREAKIN_SHIFT) /* 0x00000002 */ +#define GRF_DSP_CON0_BREAKOUTACK_SHIFT (2U) +#define GRF_DSP_CON0_BREAKOUTACK_MASK (0x1U << GRF_DSP_CON0_BREAKOUTACK_SHIFT) /* 0x00000004 */ +#define GRF_DSP_CON0_STATVECTORSEL_SHIFT (4U) +#define GRF_DSP_CON0_STATVECTORSEL_MASK (0x1U << GRF_DSP_CON0_STATVECTORSEL_SHIFT) /* 0x00000010 */ +#define GRF_DSP_CON0_RUNSTALL_SHIFT (5U) +#define GRF_DSP_CON0_RUNSTALL_MASK (0x1U << GRF_DSP_CON0_RUNSTALL_SHIFT) /* 0x00000020 */ +/* DSP_CON1 */ +#define GRF_DSP_CON1_OFFSET (0x164U) +#define GRF_DSP_CON1_ALTRESETVEC_SHIFT (0U) +#define GRF_DSP_CON1_ALTRESETVEC_MASK (0xFFFFFFFFU << GRF_DSP_CON1_ALTRESETVEC_SHIFT) /* 0xFFFFFFFF */ +/* DSP_CON2 */ +#define GRF_DSP_CON2_OFFSET (0x168U) +#define GRF_DSP_CON2_ICACHE_MEM_AUTO_GATING_EN_SHIFT (0U) +#define GRF_DSP_CON2_ICACHE_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_ICACHE_MEM_AUTO_GATING_EN_SHIFT) /* 0x00000001 */ +#define GRF_DSP_CON2_ITAG_MEM_AUTO_GATING_EN_SHIFT (1U) +#define GRF_DSP_CON2_ITAG_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_ITAG_MEM_AUTO_GATING_EN_SHIFT) /* 0x00000002 */ +#define GRF_DSP_CON2_DCACHE_MEM_AUTO_GATING_EN_SHIFT (2U) +#define GRF_DSP_CON2_DCACHE_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_DCACHE_MEM_AUTO_GATING_EN_SHIFT) /* 0x00000004 */ +#define GRF_DSP_CON2_DTAG_MEM_AUTO_GATING_EN_SHIFT (3U) +#define GRF_DSP_CON2_DTAG_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_DTAG_MEM_AUTO_GATING_EN_SHIFT) /* 0x00000008 */ +#define GRF_DSP_CON2_PREFETCH_RAM_AUTO_GATING_EN_SHIFT (4U) +#define GRF_DSP_CON2_PREFETCH_RAM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_PREFETCH_RAM_AUTO_GATING_EN_SHIFT) /* 0x00000010 */ +#define GRF_DSP_CON2_DTCM_MEM_AUTO_GATING_EN_SHIFT (5U) +#define GRF_DSP_CON2_DTCM_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_DTCM_MEM_AUTO_GATING_EN_SHIFT) /* 0x00000020 */ +#define GRF_DSP_CON2_ITCM_MEM_AUTO_GATING_EN_SHIFT (6U) +#define GRF_DSP_CON2_ITCM_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_ITCM_MEM_AUTO_GATING_EN_SHIFT) /* 0x00000040 */ +#define GRF_DSP_CON2_VAD_DTCM_SPACE_SEL_SHIFT (8U) +#define GRF_DSP_CON2_VAD_DTCM_SPACE_SEL_MASK (0x3U << GRF_DSP_CON2_VAD_DTCM_SPACE_SEL_SHIFT) /* 0x00000300 */ +/* DSP_STAT0 */ +#define GRF_DSP_STAT0_OFFSET (0x170U) +#define GRF_DSP_STAT0 (0x0U) +#define GRF_DSP_STAT0_XOCDMODE_SHIFT (0U) +#define GRF_DSP_STAT0_XOCDMODE_MASK (0x1U << GRF_DSP_STAT0_XOCDMODE_SHIFT) /* 0x00000001 */ +#define GRF_DSP_STAT0_DEBUGMODE_SHIFT (1U) +#define GRF_DSP_STAT0_DEBUGMODE_MASK (0x1U << GRF_DSP_STAT0_DEBUGMODE_SHIFT) /* 0x00000002 */ +#define GRF_DSP_STAT0_BREAKINACK_SHIFT (2U) +#define GRF_DSP_STAT0_BREAKINACK_MASK (0x1U << GRF_DSP_STAT0_BREAKINACK_SHIFT) /* 0x00000004 */ +#define GRF_DSP_STAT0_BREAKOUT_SHIFT (3U) +#define GRF_DSP_STAT0_BREAKOUT_MASK (0x1U << GRF_DSP_STAT0_BREAKOUT_SHIFT) /* 0x00000008 */ +#define GRF_DSP_STAT0_DOUBLEEXCEPTIONERROR_SHIFT (4U) +#define GRF_DSP_STAT0_DOUBLEEXCEPTIONERROR_MASK (0x1U << GRF_DSP_STAT0_DOUBLEEXCEPTIONERROR_SHIFT) /* 0x00000010 */ +#define GRF_DSP_STAT0_PFATALERROR_SHIFT (5U) +#define GRF_DSP_STAT0_PFATALERROR_MASK (0x1U << GRF_DSP_STAT0_PFATALERROR_SHIFT) /* 0x00000020 */ +#define GRF_DSP_STAT0_PFAULTINFOVALID_SHIFT (6U) +#define GRF_DSP_STAT0_PFAULTINFOVALID_MASK (0x1U << GRF_DSP_STAT0_PFAULTINFOVALID_SHIFT) /* 0x00000040 */ +#define GRF_DSP_STAT0_PWAITMODE_SHIFT (7U) +#define GRF_DSP_STAT0_PWAITMODE_MASK (0x1U << GRF_DSP_STAT0_PWAITMODE_SHIFT) /* 0x00000080 */ +#define GRF_DSP_STAT0_IRAM0LOADSTORE_SHIFT (8U) +#define GRF_DSP_STAT0_IRAM0LOADSTORE_MASK (0x1U << GRF_DSP_STAT0_IRAM0LOADSTORE_SHIFT) /* 0x00000100 */ +/* DSP_STAT1 */ +#define GRF_DSP_STAT1_OFFSET (0x174U) +#define GRF_DSP_STAT1 (0x0U) +#define GRF_DSP_STAT1_PFAULTINFO_SHIFT (0U) +#define GRF_DSP_STAT1_PFAULTINFO_MASK (0xFFFFFFFFU << GRF_DSP_STAT1_PFAULTINFO_SHIFT) /* 0xFFFFFFFF */ +/* PVTM_CON0 */ +#define GRF_PVTM_CON0_OFFSET (0x180U) +#define GRF_PVTM_CON0_PVTM_START_SHIFT (0U) +#define GRF_PVTM_CON0_PVTM_START_MASK (0x1U << GRF_PVTM_CON0_PVTM_START_SHIFT) /* 0x00000001 */ +#define GRF_PVTM_CON0_PVTM_OSC_EN_SHIFT (1U) +#define GRF_PVTM_CON0_PVTM_OSC_EN_MASK (0x1U << GRF_PVTM_CON0_PVTM_OSC_EN_SHIFT) /* 0x00000002 */ +#define GRF_PVTM_CON0_PVTM_CLKOUT_DIV_SHIFT (2U) +#define GRF_PVTM_CON0_PVTM_CLKOUT_DIV_MASK (0xFFFU << GRF_PVTM_CON0_PVTM_CLKOUT_DIV_SHIFT) /* 0x00003FFC */ +/* PVTM_CON1 */ +#define GRF_PVTM_CON1_OFFSET (0x184U) +#define GRF_PVTM_CON1_PVTM_CAL_CNT_SHIFT (0U) +#define GRF_PVTM_CON1_PVTM_CAL_CNT_MASK (0xFFFFFFFFU << GRF_PVTM_CON1_PVTM_CAL_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PVTM_STATUS0 */ +#define GRF_PVTM_STATUS0_OFFSET (0x190U) +#define GRF_PVTM_STATUS0 (0x0U) +#define GRF_PVTM_STATUS0_PVTM_FREQ_DONE_SHIFT (0U) +#define GRF_PVTM_STATUS0_PVTM_FREQ_DONE_MASK (0x1U << GRF_PVTM_STATUS0_PVTM_FREQ_DONE_SHIFT) /* 0x00000001 */ +/* PVTM_STATUS1 */ +#define GRF_PVTM_STATUS1_OFFSET (0x194U) +#define GRF_PVTM_STATUS1 (0x0U) +#define GRF_PVTM_STATUS1_PVTM_FREQ_CNT_SHIFT (0U) +#define GRF_PVTM_STATUS1_PVTM_FREQ_CNT_MASK (0xFFFFFFFFU << GRF_PVTM_STATUS1_PVTM_FREQ_CNT_SHIFT) /* 0xFFFFFFFF */ +/* FW_CON0 */ +#define GRF_FW_CON0_OFFSET (0x1C0U) +#define GRF_FW_CON0_FWBYPASS_SHIFT (0U) +#define GRF_FW_CON0_FWBYPASS_MASK (0x1U << GRF_FW_CON0_FWBYPASS_SHIFT) /* 0x00000001 */ +#define GRF_FW_CON0_MEMEN_SHIFT (1U) +#define GRF_FW_CON0_MEMEN_MASK (0x1U << GRF_FW_CON0_MEMEN_SHIFT) /* 0x00000002 */ +#define GRF_FW_CON0_MBOXEN_SHIFT (2U) +#define GRF_FW_CON0_MBOXEN_MASK (0x1U << GRF_FW_CON0_MBOXEN_SHIFT) /* 0x00000004 */ +/* FW_CON1 */ +#define GRF_FW_CON1_OFFSET (0x1C4U) +#define GRF_FW_CON1_MEM_BASE_ADDRESS_SHIFT (0U) +#define GRF_FW_CON1_MEM_BASE_ADDRESS_MASK (0xFFFFFFFFU << GRF_FW_CON1_MEM_BASE_ADDRESS_SHIFT) /* 0xFFFFFFFF */ +/* FW_CON2 */ +#define GRF_FW_CON2_OFFSET (0x1C8U) +#define GRF_FW_CON2_MEM_TOP_ADDRESS_SHIFT (0U) +#define GRF_FW_CON2_MEM_TOP_ADDRESS_MASK (0xFFFFFFFFU << GRF_FW_CON2_MEM_TOP_ADDRESS_SHIFT) /* 0xFFFFFFFF */ +/* MCU_CON0 */ +#define GRF_MCU_CON0_OFFSET (0x200U) +#define GRF_MCU_CON0_M4_RXEV_SHIFT (0U) +#define GRF_MCU_CON0_M4_RXEV_MASK (0x1U << GRF_MCU_CON0_M4_RXEV_SHIFT) /* 0x00000001 */ +#define GRF_MCU_CON0_M4_NMI_SHIFT (1U) +#define GRF_MCU_CON0_M4_NMI_MASK (0x1U << GRF_MCU_CON0_M4_NMI_SHIFT) /* 0x00000002 */ +#define GRF_MCU_CON0_M4_EDBGRQ_SHIFT (2U) +#define GRF_MCU_CON0_M4_EDBGRQ_MASK (0x1U << GRF_MCU_CON0_M4_EDBGRQ_SHIFT) /* 0x00000004 */ +#define GRF_MCU_CON0_M4_DBGRESTART_SHIFT (3U) +#define GRF_MCU_CON0_M4_DBGRESTART_MASK (0x1U << GRF_MCU_CON0_M4_DBGRESTART_SHIFT) /* 0x00000008 */ +#define GRF_MCU_CON0_M4_DBGEN_SHIFT (4U) +#define GRF_MCU_CON0_M4_DBGEN_MASK (0x1U << GRF_MCU_CON0_M4_DBGEN_SHIFT) /* 0x00000010 */ +#define GRF_MCU_CON0_M4_MPU_DISABLE_SHIFT (6U) +#define GRF_MCU_CON0_M4_MPU_DISABLE_MASK (0x1U << GRF_MCU_CON0_M4_MPU_DISABLE_SHIFT) /* 0x00000040 */ +#define GRF_MCU_CON0_M4_FPU_DISABLE_SHIFT (7U) +#define GRF_MCU_CON0_M4_FPU_DISABLE_MASK (0x1U << GRF_MCU_CON0_M4_FPU_DISABLE_SHIFT) /* 0x00000080 */ +#define GRF_MCU_CON0_M4_DAP_FIXMASTER_SHIFT (8U) +#define GRF_MCU_CON0_M4_DAP_FIXMASTER_MASK (0x1U << GRF_MCU_CON0_M4_DAP_FIXMASTER_SHIFT) /* 0x00000100 */ +#define GRF_MCU_CON0_M4_DAP_DCACHE_SHIFT (9U) +#define GRF_MCU_CON0_M4_DAP_DCACHE_MASK (0x1U << GRF_MCU_CON0_M4_DAP_DCACHE_SHIFT) /* 0x00000200 */ +#define GRF_MCU_CON0_M4_SLEEP_DELAY_SHIFT (10U) +#define GRF_MCU_CON0_M4_SLEEP_DELAY_MASK (0x1U << GRF_MCU_CON0_M4_SLEEP_DELAY_SHIFT) /* 0x00000400 */ +/* MCU_CON1 */ +#define GRF_MCU_CON1_OFFSET (0x204U) +#define GRF_MCU_CON1_M4_TENMS_SHIFT (0U) +#define GRF_MCU_CON1_M4_TENMS_MASK (0xFFFFFFU << GRF_MCU_CON1_M4_TENMS_SHIFT) /* 0x00FFFFFF */ +#define GRF_MCU_CON1_M4_SKEW_SHIFT (24U) +#define GRF_MCU_CON1_M4_SKEW_MASK (0x1U << GRF_MCU_CON1_M4_SKEW_SHIFT) /* 0x01000000 */ +/* MCU_CON2 */ +#define GRF_MCU_CON2_OFFSET (0x208U) +#define GRF_MCU_CON2_M4_MEM_OFFSET_SHIFT (0U) +#define GRF_MCU_CON2_M4_MEM_OFFSET_MASK (0xFFFFFFFFU << GRF_MCU_CON2_M4_MEM_OFFSET_SHIFT) /* 0xFFFFFFFF */ +/* MCU_CON3 */ +#define GRF_MCU_CON3_OFFSET (0x20CU) +#define GRF_MCU_CON3_M4_FLASH_OFFSET_SHIFT (0U) +#define GRF_MCU_CON3_M4_FLASH_OFFSET_MASK (0xFFFFFFFFU << GRF_MCU_CON3_M4_FLASH_OFFSET_SHIFT) /* 0xFFFFFFFF */ +/* MCU_STAT0 */ +#define GRF_MCU_STAT0_OFFSET (0x220U) +#define GRF_MCU_STAT0 (0x0U) +#define GRF_MCU_STAT0_M4_SLEEPING_SHIFT (0U) +#define GRF_MCU_STAT0_M4_SLEEPING_MASK (0x1U << GRF_MCU_STAT0_M4_SLEEPING_SHIFT) /* 0x00000001 */ +#define GRF_MCU_STAT0_M4_SLEEPDEEP_SHIFT (1U) +#define GRF_MCU_STAT0_M4_SLEEPDEEP_MASK (0x1U << GRF_MCU_STAT0_M4_SLEEPDEEP_SHIFT) /* 0x00000002 */ +#define GRF_MCU_STAT0_M4_HALTED_SHIFT (2U) +#define GRF_MCU_STAT0_M4_HALTED_MASK (0x1U << GRF_MCU_STAT0_M4_HALTED_SHIFT) /* 0x00000004 */ +#define GRF_MCU_STAT0_M4_DBGRESTARTED_SHIFT (3U) +#define GRF_MCU_STAT0_M4_DBGRESTARTED_MASK (0x1U << GRF_MCU_STAT0_M4_DBGRESTARTED_SHIFT) /* 0x00000008 */ +#define GRF_MCU_STAT0_M4_GATEHCLK_SHIFT (4U) +#define GRF_MCU_STAT0_M4_GATEHCLK_MASK (0x1U << GRF_MCU_STAT0_M4_GATEHCLK_SHIFT) /* 0x00000010 */ +#define GRF_MCU_STAT0_M4_LOCKUP_SHIFT (5U) +#define GRF_MCU_STAT0_M4_LOCKUP_MASK (0x1U << GRF_MCU_STAT0_M4_LOCKUP_SHIFT) /* 0x00000020 */ +#define GRF_MCU_STAT0_M4_CURRPRI_SHIFT (8U) +#define GRF_MCU_STAT0_M4_CURRPRI_MASK (0xFFU << GRF_MCU_STAT0_M4_CURRPRI_SHIFT) /* 0x0000FF00 */ +#define GRF_MCU_STAT0_M4_FPIXC_SHIFT (16U) +#define GRF_MCU_STAT0_M4_FPIXC_MASK (0x1U << GRF_MCU_STAT0_M4_FPIXC_SHIFT) /* 0x00010000 */ +#define GRF_MCU_STAT0_M4_FPOFC_SHIFT (17U) +#define GRF_MCU_STAT0_M4_FPOFC_MASK (0x1U << GRF_MCU_STAT0_M4_FPOFC_SHIFT) /* 0x00020000 */ +#define GRF_MCU_STAT0_M4_FPUFC_SHIFT (18U) +#define GRF_MCU_STAT0_M4_FPUFC_MASK (0x1U << GRF_MCU_STAT0_M4_FPUFC_SHIFT) /* 0x00040000 */ +#define GRF_MCU_STAT0_M4_FPIOC_SHIFT (19U) +#define GRF_MCU_STAT0_M4_FPIOC_MASK (0x1U << GRF_MCU_STAT0_M4_FPIOC_SHIFT) /* 0x00080000 */ +#define GRF_MCU_STAT0_M4_FPDZC_SHIFT (20U) +#define GRF_MCU_STAT0_M4_FPDZC_MASK (0x1U << GRF_MCU_STAT0_M4_FPDZC_SHIFT) /* 0x00100000 */ +#define GRF_MCU_STAT0_M4_FPIDC_SHIFT (21U) +#define GRF_MCU_STAT0_M4_FPIDC_MASK (0x1U << GRF_MCU_STAT0_M4_FPIDC_SHIFT) /* 0x00200000 */ +/* DSI_CON0 */ +#define GRF_DSI_CON0_OFFSET (0x240U) +#define GRF_DSI_CON0_DPHY_PHYRSTZ_SHIFT (0U) +#define GRF_DSI_CON0_DPHY_PHYRSTZ_MASK (0x1U << GRF_DSI_CON0_DPHY_PHYRSTZ_SHIFT) /* 0x00000001 */ +#define GRF_DSI_CON0_DPHY_PLL_CLK_SEL_SHIFT (2U) +#define GRF_DSI_CON0_DPHY_PLL_CLK_SEL_MASK (0x3FFU << GRF_DSI_CON0_DPHY_PLL_CLK_SEL_SHIFT) /* 0x00000FFC */ +#define GRF_DSI_CON0_DPHY_REFCLK_IN_SEL_SHIFT (12U) +#define GRF_DSI_CON0_DPHY_REFCLK_IN_SEL_MASK (0x7U << GRF_DSI_CON0_DPHY_REFCLK_IN_SEL_SHIFT) /* 0x00007000 */ +/* DSI_CON1 */ +#define GRF_DSI_CON1_OFFSET (0x244U) +#define GRF_DSI_CON1_DPHY_TXSKEWCALHS_SHIFT (0U) +#define GRF_DSI_CON1_DPHY_TXSKEWCALHS_MASK (0xFU << GRF_DSI_CON1_DPHY_TXSKEWCALHS_SHIFT) /* 0x0000000F */ +#define GRF_DSI_CON1_DPHY_FORCETXSTOPMODE_SHIFT (4U) +#define GRF_DSI_CON1_DPHY_FORCETXSTOPMODE_MASK (0xFU << GRF_DSI_CON1_DPHY_FORCETXSTOPMODE_SHIFT) /* 0x000000F0 */ +#define GRF_DSI_CON1_DPHY_TURNDISABLE0_SHIFT (8U) +#define GRF_DSI_CON1_DPHY_TURNDISABLE0_MASK (0x1U << GRF_DSI_CON1_DPHY_TURNDISABLE0_SHIFT) /* 0x00000100 */ +#define GRF_DSI_CON1_DPHY_FORCERXMODE0_SHIFT (9U) +#define GRF_DSI_CON1_DPHY_FORCERXMODE0_MASK (0x1U << GRF_DSI_CON1_DPHY_FORCERXMODE0_SHIFT) /* 0x00000200 */ +#define GRF_DSI_CON1_DPHY_TXONLY_SHIFT (10U) +#define GRF_DSI_CON1_DPHY_TXONLY_MASK (0x1U << GRF_DSI_CON1_DPHY_TXONLY_SHIFT) /* 0x00000400 */ +#define GRF_DSI_CON1_DPHY_DEBUG_SEL_SHIFT (11U) +#define GRF_DSI_CON1_DPHY_DEBUG_SEL_MASK (0x1FU << GRF_DSI_CON1_DPHY_DEBUG_SEL_SHIFT) /* 0x0000F800 */ +/* DSI_CON2 */ +#define GRF_DSI_CON2_OFFSET (0x248U) +#define GRF_DSI_CON2_DPHY_LANE_SWAP0_SHIFT (0U) +#define GRF_DSI_CON2_DPHY_LANE_SWAP0_MASK (0x7U << GRF_DSI_CON2_DPHY_LANE_SWAP0_SHIFT) /* 0x00000007 */ +#define GRF_DSI_CON2_DPHY_LANE_SWAP1_SHIFT (3U) +#define GRF_DSI_CON2_DPHY_LANE_SWAP1_MASK (0x7U << GRF_DSI_CON2_DPHY_LANE_SWAP1_SHIFT) /* 0x00000038 */ +#define GRF_DSI_CON2_DPHY_LANE_SWAP2_SHIFT (6U) +#define GRF_DSI_CON2_DPHY_LANE_SWAP2_MASK (0x7U << GRF_DSI_CON2_DPHY_LANE_SWAP2_SHIFT) /* 0x000001C0 */ +#define GRF_DSI_CON2_DPHY_LANE_SWAP3_SHIFT (9U) +#define GRF_DSI_CON2_DPHY_LANE_SWAP3_MASK (0x7U << GRF_DSI_CON2_DPHY_LANE_SWAP3_SHIFT) /* 0x00000E00 */ +#define GRF_DSI_CON2_DPHY_LANE_SWAP_CLK_SHIFT (12U) +#define GRF_DSI_CON2_DPHY_LANE_SWAP_CLK_MASK (0x7U << GRF_DSI_CON2_DPHY_LANE_SWAP_CLK_SHIFT) /* 0x00007000 */ +/* DSI_CON3 */ +#define GRF_DSI_CON3_OFFSET (0x24CU) +#define GRF_DSI_CON3_DPHY_XCFGI_D0_SHIFT (0U) +#define GRF_DSI_CON3_DPHY_XCFGI_D0_MASK (0xFFFFFFFFU << GRF_DSI_CON3_DPHY_XCFGI_D0_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON4 */ +#define GRF_DSI_CON4_OFFSET (0x250U) +#define GRF_DSI_CON4_DPHY_XCFGI_D0_SHIFT (0U) +#define GRF_DSI_CON4_DPHY_XCFGI_D0_MASK (0xFFFFFFFFU << GRF_DSI_CON4_DPHY_XCFGI_D0_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON5 */ +#define GRF_DSI_CON5_OFFSET (0x254U) +#define GRF_DSI_CON5_DPHY_XCFGI_D0_SHIFT (0U) +#define GRF_DSI_CON5_DPHY_XCFGI_D0_MASK (0xFFFFFFU << GRF_DSI_CON5_DPHY_XCFGI_D0_SHIFT) /* 0x00FFFFFF */ +/* DSI_CON6 */ +#define GRF_DSI_CON6_OFFSET (0x258U) +#define GRF_DSI_CON6_DPHY_XCFGI_D1_SHIFT (0U) +#define GRF_DSI_CON6_DPHY_XCFGI_D1_MASK (0xFFFFFFFFU << GRF_DSI_CON6_DPHY_XCFGI_D1_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON7 */ +#define GRF_DSI_CON7_OFFSET (0x25CU) +#define GRF_DSI_CON7_DPHY_XCFGI_D1_SHIFT (0U) +#define GRF_DSI_CON7_DPHY_XCFGI_D1_MASK (0xFFFFFFFFU << GRF_DSI_CON7_DPHY_XCFGI_D1_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON8 */ +#define GRF_DSI_CON8_OFFSET (0x260U) +#define GRF_DSI_CON8_DPHY_XCFGI_D1_SHIFT (0U) +#define GRF_DSI_CON8_DPHY_XCFGI_D1_MASK (0xFFFFFFU << GRF_DSI_CON8_DPHY_XCFGI_D1_SHIFT) /* 0x00FFFFFF */ +/* DSI_CON9 */ +#define GRF_DSI_CON9_OFFSET (0x264U) +#define GRF_DSI_CON9_DPHY_XCFGI_D2_SHIFT (0U) +#define GRF_DSI_CON9_DPHY_XCFGI_D2_MASK (0xFFFFFFFFU << GRF_DSI_CON9_DPHY_XCFGI_D2_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON10 */ +#define GRF_DSI_CON10_OFFSET (0x268U) +#define GRF_DSI_CON10_DPHY_XCFGI_D2_SHIFT (0U) +#define GRF_DSI_CON10_DPHY_XCFGI_D2_MASK (0xFFFFFFFFU << GRF_DSI_CON10_DPHY_XCFGI_D2_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON11 */ +#define GRF_DSI_CON11_OFFSET (0x26CU) +#define GRF_DSI_CON11_DPHY_XCFGI_D2_SHIFT (0U) +#define GRF_DSI_CON11_DPHY_XCFGI_D2_MASK (0xFFFFFFU << GRF_DSI_CON11_DPHY_XCFGI_D2_SHIFT) /* 0x00FFFFFF */ +/* DSI_CON12 */ +#define GRF_DSI_CON12_OFFSET (0x270U) +#define GRF_DSI_CON12_DPHY_XCFGI_D3_SHIFT (0U) +#define GRF_DSI_CON12_DPHY_XCFGI_D3_MASK (0xFFFFFFFFU << GRF_DSI_CON12_DPHY_XCFGI_D3_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON13 */ +#define GRF_DSI_CON13_OFFSET (0x274U) +#define GRF_DSI_CON13_DPHY_XCFGI_D3_SHIFT (0U) +#define GRF_DSI_CON13_DPHY_XCFGI_D3_MASK (0xFFFFFFFFU << GRF_DSI_CON13_DPHY_XCFGI_D3_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON14 */ +#define GRF_DSI_CON14_OFFSET (0x278U) +#define GRF_DSI_CON14_DPHY_XCFGI_D3_SHIFT (0U) +#define GRF_DSI_CON14_DPHY_XCFGI_D3_MASK (0xFFFFFFU << GRF_DSI_CON14_DPHY_XCFGI_D3_SHIFT) /* 0x00FFFFFF */ +/* DSI_CON15 */ +#define GRF_DSI_CON15_OFFSET (0x27CU) +#define GRF_DSI_CON15_DPHY_XCFGI_CLK_SHIFT (0U) +#define GRF_DSI_CON15_DPHY_XCFGI_CLK_MASK (0xFFFFFFFFU << GRF_DSI_CON15_DPHY_XCFGI_CLK_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON16 */ +#define GRF_DSI_CON16_OFFSET (0x280U) +#define GRF_DSI_CON16_DPHY_XCFGI_CLK_SHIFT (0U) +#define GRF_DSI_CON16_DPHY_XCFGI_CLK_MASK (0xFFFFFFFFU << GRF_DSI_CON16_DPHY_XCFGI_CLK_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON17 */ +#define GRF_DSI_CON17_OFFSET (0x284U) +#define GRF_DSI_CON17_DPHY_XCFGI_CLK_SHIFT (0U) +#define GRF_DSI_CON17_DPHY_XCFGI_CLK_MASK (0xFFFFFFU << GRF_DSI_CON17_DPHY_XCFGI_CLK_SHIFT) /* 0x00FFFFFF */ +/* DSI_CON18 */ +#define GRF_DSI_CON18_OFFSET (0x288U) +#define GRF_DSI_CON18_DPHY_XCFGI_GLOBAL_SHIFT (0U) +#define GRF_DSI_CON18_DPHY_XCFGI_GLOBAL_MASK (0xFFFFFFFFU << GRF_DSI_CON18_DPHY_XCFGI_GLOBAL_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON19 */ +#define GRF_DSI_CON19_OFFSET (0x28CU) +#define GRF_DSI_CON19_DPHY_XCFGI_GLOBAL_SHIFT (0U) +#define GRF_DSI_CON19_DPHY_XCFGI_GLOBAL_MASK (0xFFFFFFFFU << GRF_DSI_CON19_DPHY_XCFGI_GLOBAL_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON20 */ +#define GRF_DSI_CON20_OFFSET (0x290U) +#define GRF_DSI_CON20_DPHY_XCFGI_GLOBAL_SHIFT (0U) +#define GRF_DSI_CON20_DPHY_XCFGI_GLOBAL_MASK (0xFFFFFFFFU << GRF_DSI_CON20_DPHY_XCFGI_GLOBAL_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON21 */ +#define GRF_DSI_CON21_OFFSET (0x294U) +#define GRF_DSI_CON21_DPHY_XCFGI_GLOBAL_SHIFT (0U) +#define GRF_DSI_CON21_DPHY_XCFGI_GLOBAL_MASK (0xFFFFFFFFU << GRF_DSI_CON21_DPHY_XCFGI_GLOBAL_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON22 */ +#define GRF_DSI_CON22_OFFSET (0x298U) +#define GRF_DSI_CON22_DPHY_XCFGI_GLOBAL_SHIFT (0U) +#define GRF_DSI_CON22_DPHY_XCFGI_GLOBAL_MASK (0xFFFFFFFFU << GRF_DSI_CON22_DPHY_XCFGI_GLOBAL_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON23 */ +#define GRF_DSI_CON23_OFFSET (0x29CU) +#define GRF_DSI_CON23_DPHY_XCFGI_GLOBAL_SHIFT (0U) +#define GRF_DSI_CON23_DPHY_XCFGI_GLOBAL_MASK (0xFFFFFFFFU << GRF_DSI_CON23_DPHY_XCFGI_GLOBAL_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON24 */ +#define GRF_DSI_CON24_OFFSET (0x2A0U) +#define GRF_DSI_CON24_DPHY_XCFGI_GLOBAL_SHIFT (0U) +#define GRF_DSI_CON24_DPHY_XCFGI_GLOBAL_MASK (0xFFFFFFFFU << GRF_DSI_CON24_DPHY_XCFGI_GLOBAL_SHIFT) /* 0xFFFFFFFF */ +/* DSI_CON25 */ +#define GRF_DSI_CON25_OFFSET (0x2A4U) +#define GRF_DSI_CON25_DPHY_XCFGI_GLOBAL_SHIFT (0U) +#define GRF_DSI_CON25_DPHY_XCFGI_GLOBAL_MASK (0xFFFFFFU << GRF_DSI_CON25_DPHY_XCFGI_GLOBAL_SHIFT) /* 0x00FFFFFF */ +/* DSI_CON26 */ +#define GRF_DSI_CON26_OFFSET (0x2A8U) +#define GRF_DSI_CON26_DPHY_FORCE_ODTCAL_SEL_SHIFT (0U) +#define GRF_DSI_CON26_DPHY_FORCE_ODTCAL_SEL_MASK (0xFFFU << GRF_DSI_CON26_DPHY_FORCE_ODTCAL_SEL_SHIFT) /* 0x00000FFF */ +/* DSI_CON27 */ +#define GRF_DSI_CON27_OFFSET (0x2ACU) +#define GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_0_SHIFT (0U) +#define GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_0_MASK (0xFU << GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_0_SHIFT) /* 0x0000000F */ +#define GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_1_SHIFT (4U) +#define GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_1_MASK (0xFU << GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_1_SHIFT) /* 0x000000F0 */ +#define GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_2_SHIFT (8U) +#define GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_2_MASK (0xFU << GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_2_SHIFT) /* 0x00000F00 */ +#define GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_3_SHIFT (12U) +#define GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_3_MASK (0xFU << GRF_DSI_CON27_DPHY_EXT_ODTCAL_SEL_3_SHIFT) /* 0x0000F000 */ +/* DSI_CON28 */ +#define GRF_DSI_CON28_OFFSET (0x2B0U) +#define GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_4_SHIFT (0U) +#define GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_4_MASK (0xFU << GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_4_SHIFT) /* 0x0000000F */ +#define GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_5_SHIFT (4U) +#define GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_5_MASK (0xFU << GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_5_SHIFT) /* 0x000000F0 */ +#define GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_6_SHIFT (8U) +#define GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_6_MASK (0xFU << GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_6_SHIFT) /* 0x00000F00 */ +#define GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_7_SHIFT (12U) +#define GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_7_MASK (0xFU << GRF_DSI_CON28_DPHY_EXT_ODTCAL_SEL_7_SHIFT) /* 0x0000F000 */ +/* DSI_CON29 */ +#define GRF_DSI_CON29_OFFSET (0x2B4U) +#define GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_8_SHIFT (0U) +#define GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_8_MASK (0xFU << GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_8_SHIFT) /* 0x0000000F */ +#define GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_9_SHIFT (4U) +#define GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_9_MASK (0xFU << GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_9_SHIFT) /* 0x000000F0 */ +#define GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_10_SHIFT (8U) +#define GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_10_MASK (0xFU << GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_10_SHIFT) /* 0x00000F00 */ +#define GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_11_SHIFT (12U) +#define GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_11_MASK (0xFU << GRF_DSI_CON29_DPHY_EXT_ODTCAL_SEL_11_SHIFT) /* 0x0000F000 */ +/* DSI_STATUS0 */ +#define GRF_DSI_STATUS0_OFFSET (0x2C0U) +#define GRF_DSI_STATUS0 (0x0U) +#define GRF_DSI_STATUS0_DPHY_PHYULPSACTIVENOTCLK_SHIFT (0U) +#define GRF_DSI_STATUS0_DPHY_PHYULPSACTIVENOTCLK_MASK (0x1U << GRF_DSI_STATUS0_DPHY_PHYULPSACTIVENOTCLK_SHIFT) /* 0x00000001 */ +#define GRF_DSI_STATUS0_DPHY_PHYSTOPSTATECLKLANE_SHIFT (1U) +#define GRF_DSI_STATUS0_DPHY_PHYSTOPSTATECLKLANE_MASK (0x1U << GRF_DSI_STATUS0_DPHY_PHYSTOPSTATECLKLANE_SHIFT) /* 0x00000002 */ +#define GRF_DSI_STATUS0_DPHY_STOPSTATE_SHIFT (2U) +#define GRF_DSI_STATUS0_DPHY_STOPSTATE_MASK (0xFU << GRF_DSI_STATUS0_DPHY_STOPSTATE_SHIFT) /* 0x0000003C */ +#define GRF_DSI_STATUS0_DPHY_ULPSACTIVENOT_SHIFT (6U) +#define GRF_DSI_STATUS0_DPHY_ULPSACTIVENOT_MASK (0xFU << GRF_DSI_STATUS0_DPHY_ULPSACTIVENOT_SHIFT) /* 0x000003C0 */ +#define GRF_DSI_STATUS0_DPHY_ERRESC_0_SHIFT (10U) +#define GRF_DSI_STATUS0_DPHY_ERRESC_0_MASK (0x1U << GRF_DSI_STATUS0_DPHY_ERRESC_0_SHIFT) /* 0x00000400 */ +#define GRF_DSI_STATUS0_DPHY_ERRSYNCESC_0_SHIFT (11U) +#define GRF_DSI_STATUS0_DPHY_ERRSYNCESC_0_MASK (0x1U << GRF_DSI_STATUS0_DPHY_ERRSYNCESC_0_SHIFT) /* 0x00000800 */ +#define GRF_DSI_STATUS0_DPHY_ERRCONTROL_0_SHIFT (12U) +#define GRF_DSI_STATUS0_DPHY_ERRCONTROL_0_MASK (0x1U << GRF_DSI_STATUS0_DPHY_ERRCONTROL_0_SHIFT) /* 0x00001000 */ +#define GRF_DSI_STATUS0_DPHY_ERRCONTENTIONLP0_0_SHIFT (13U) +#define GRF_DSI_STATUS0_DPHY_ERRCONTENTIONLP0_0_MASK (0x1U << GRF_DSI_STATUS0_DPHY_ERRCONTENTIONLP0_0_SHIFT) /* 0x00002000 */ +#define GRF_DSI_STATUS0_DPHY_ERRCONTENTIONLP1_0_SHIFT (14U) +#define GRF_DSI_STATUS0_DPHY_ERRCONTENTIONLP1_0_MASK (0x1U << GRF_DSI_STATUS0_DPHY_ERRCONTENTIONLP1_0_SHIFT) /* 0x00004000 */ +/* DSI_STATUS1 */ +#define GRF_DSI_STATUS1_OFFSET (0x2C4U) +#define GRF_DSI_STATUS1 (0x0U) +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_0_SHIFT (0U) +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_0_MASK (0xFU << GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_0_SHIFT) /* 0x0000000F */ +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_1_SHIFT (4U) +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_1_MASK (0xFU << GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_1_SHIFT) /* 0x000000F0 */ +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_2_SHIFT (8U) +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_2_MASK (0xFU << GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_2_SHIFT) /* 0x00000F00 */ +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_3_SHIFT (12U) +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_3_MASK (0xFU << GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_3_SHIFT) /* 0x0000F000 */ +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_4_SHIFT (16U) +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_4_MASK (0xFU << GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_4_SHIFT) /* 0x000F0000 */ +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_5_SHIFT (20U) +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_5_MASK (0xFU << GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_5_SHIFT) /* 0x00F00000 */ +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_6_SHIFT (24U) +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_6_MASK (0xFU << GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_6_SHIFT) /* 0x0F000000 */ +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_7_SHIFT (28U) +#define GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_7_MASK (0xFU << GRF_DSI_STATUS1_DPHY_DA_ODTCAL_SEL_7_SHIFT) /* 0xF0000000 */ +/* DSI_STATUS2 */ +#define GRF_DSI_STATUS2_OFFSET (0x2C8U) +#define GRF_DSI_STATUS2 (0x0U) +#define GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_8_SHIFT (0U) +#define GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_8_MASK (0xFU << GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_8_SHIFT) /* 0x0000000F */ +#define GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_9_SHIFT (4U) +#define GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_9_MASK (0xFU << GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_9_SHIFT) /* 0x000000F0 */ +#define GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_10_SHIFT (8U) +#define GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_10_MASK (0xFU << GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_10_SHIFT) /* 0x00000F00 */ +#define GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_11_SHIFT (12U) +#define GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_11_MASK (0xFU << GRF_DSI_STATUS2_DPHY_DA_ODTCAL_SEL_11_SHIFT) /* 0x0000F000 */ +/* DSI_STATUS3 */ +#define GRF_DSI_STATUS3_OFFSET (0x2CCU) +#define GRF_DSI_STATUS3 (0x0U) +#define GRF_DSI_STATUS3_DPHY_DEBUG_PORT_SHIFT (0U) +#define GRF_DSI_STATUS3_DPHY_DEBUG_PORT_MASK (0xFFFFFFFFU << GRF_DSI_STATUS3_DPHY_DEBUG_PORT_SHIFT) /* 0xFFFFFFFF */ +/* DSI_STATUS4 */ +#define GRF_DSI_STATUS4_OFFSET (0x2D0U) +#define GRF_DSI_STATUS4 (0x0U) +#define GRF_DSI_STATUS4_DPHY_XCFGO_SHIFT (0U) +#define GRF_DSI_STATUS4_DPHY_XCFGO_MASK (0xFFFFFFFFU << GRF_DSI_STATUS4_DPHY_XCFGO_SHIFT) /* 0xFFFFFFFF */ +/* DSI_STATUS5 */ +#define GRF_DSI_STATUS5_OFFSET (0x2D4U) +#define GRF_DSI_STATUS5 (0x0U) +#define GRF_DSI_STATUS5_DPHY_XCFGO_SHIFT (0U) +#define GRF_DSI_STATUS5_DPHY_XCFGO_MASK (0xFFFFFFFFU << GRF_DSI_STATUS5_DPHY_XCFGO_SHIFT) /* 0xFFFFFFFF */ +/* DSI_STATUS6 */ +#define GRF_DSI_STATUS6_OFFSET (0x2D8U) +#define GRF_DSI_STATUS6 (0x0U) +#define GRF_DSI_STATUS6_DPHY_XCFGO_SHIFT (0U) +#define GRF_DSI_STATUS6_DPHY_XCFGO_MASK (0x3FFFU << GRF_DSI_STATUS6_DPHY_XCFGO_SHIFT) /* 0x00003FFF */ +/* DSI_STATUS7 */ +#define GRF_DSI_STATUS7_OFFSET (0x2DCU) +#define GRF_DSI_STATUS7 (0x0U) +#define GRF_DSI_STATUS7_DPHY_MPOSV_SHIFT (0U) +#define GRF_DSI_STATUS7_DPHY_MPOSV_MASK (0xFFFFFFFFU << GRF_DSI_STATUS7_DPHY_MPOSV_SHIFT) /* 0xFFFFFFFF */ +/* DSI_STATUS8 */ +#define GRF_DSI_STATUS8_OFFSET (0x2E0U) +#define GRF_DSI_STATUS8 (0x0U) +#define GRF_DSI_STATUS8_DPHY_MPOSV_SHIFT (0U) +#define GRF_DSI_STATUS8_DPHY_MPOSV_MASK (0x3FFU << GRF_DSI_STATUS8_DPHY_MPOSV_SHIFT) /* 0x000003FF */ +/* MEM_CON0 */ +#define GRF_MEM_CON0_OFFSET (0x300U) +#define GRF_MEM_CON0_PDM_MEM_EMA_SHIFT (0U) +#define GRF_MEM_CON0_PDM_MEM_EMA_MASK (0x7U << GRF_MEM_CON0_PDM_MEM_EMA_SHIFT) /* 0x00000007 */ +#define GRF_MEM_CON0_PDM_MEM_EMAW_SHIFT (3U) +#define GRF_MEM_CON0_PDM_MEM_EMAW_MASK (0x3U << GRF_MEM_CON0_PDM_MEM_EMAW_SHIFT) /* 0x00000018 */ +#define GRF_MEM_CON0_M4_MEM_EMA_SHIFT (5U) +#define GRF_MEM_CON0_M4_MEM_EMA_MASK (0x7U << GRF_MEM_CON0_M4_MEM_EMA_SHIFT) /* 0x000000E0 */ +#define GRF_MEM_CON0_M4_MEM_EMAW_SHIFT (8U) +#define GRF_MEM_CON0_M4_MEM_EMAW_MASK (0x3U << GRF_MEM_CON0_M4_MEM_EMAW_SHIFT) /* 0x00000300 */ +#define GRF_MEM_CON0_SHRM_MEM_EMA_SHIFT (10U) +#define GRF_MEM_CON0_SHRM_MEM_EMA_MASK (0x7U << GRF_MEM_CON0_SHRM_MEM_EMA_SHIFT) /* 0x00001C00 */ +#define GRF_MEM_CON0_SHRM_MEM_EMAW_SHIFT (13U) +#define GRF_MEM_CON0_SHRM_MEM_EMAW_MASK (0x3U << GRF_MEM_CON0_SHRM_MEM_EMAW_SHIFT) /* 0x00006000 */ +#define GRF_MEM_CON0_SHRM_MEM_EMAS_SHIFT (15U) +#define GRF_MEM_CON0_SHRM_MEM_EMAS_MASK (0x1U << GRF_MEM_CON0_SHRM_MEM_EMAS_SHIFT) /* 0x00008000 */ +/* MEM_CON1 */ +#define GRF_MEM_CON1_OFFSET (0x304U) +#define GRF_MEM_CON1_VOP_DP_EMAA_SHIFT (0U) +#define GRF_MEM_CON1_VOP_DP_EMAA_MASK (0x7U << GRF_MEM_CON1_VOP_DP_EMAA_SHIFT) /* 0x00000007 */ +#define GRF_MEM_CON1_VOP_DP_EMASA_SHIFT (3U) +#define GRF_MEM_CON1_VOP_DP_EMASA_MASK (0x1U << GRF_MEM_CON1_VOP_DP_EMASA_SHIFT) /* 0x00000008 */ +#define GRF_MEM_CON1_VOP_DP_EMAB_SHIFT (4U) +#define GRF_MEM_CON1_VOP_DP_EMAB_MASK (0x7U << GRF_MEM_CON1_VOP_DP_EMAB_SHIFT) /* 0x00000070 */ +#define GRF_MEM_CON1_VOP_SP_EMA_SHIFT (7U) +#define GRF_MEM_CON1_VOP_SP_EMA_MASK (0x7U << GRF_MEM_CON1_VOP_SP_EMA_SHIFT) /* 0x00000380 */ +#define GRF_MEM_CON1_VOP_SP_EMAW_SHIFT (10U) +#define GRF_MEM_CON1_VOP_SP_EMAW_MASK (0x3U << GRF_MEM_CON1_VOP_SP_EMAW_SHIFT) /* 0x00000C00 */ +#define GRF_MEM_CON1_VOP_SP_EMAS_SHIFT (12U) +#define GRF_MEM_CON1_VOP_SP_EMAS_MASK (0x1U << GRF_MEM_CON1_VOP_SP_EMAS_SHIFT) /* 0x00001000 */ +/* MEM_CON2 */ +#define GRF_MEM_CON2_OFFSET (0x308U) +#define GRF_MEM_CON2_DSIHOST_MEM_EMAA_SHIFT (0U) +#define GRF_MEM_CON2_DSIHOST_MEM_EMAA_MASK (0x7U << GRF_MEM_CON2_DSIHOST_MEM_EMAA_SHIFT) /* 0x00000007 */ +#define GRF_MEM_CON2_DSIHOST_MEM_EMASA_SHIFT (3U) +#define GRF_MEM_CON2_DSIHOST_MEM_EMASA_MASK (0x1U << GRF_MEM_CON2_DSIHOST_MEM_EMASA_SHIFT) /* 0x00000008 */ +#define GRF_MEM_CON2_DSIHOST_MEM_EMAB_SHIFT (4U) +#define GRF_MEM_CON2_DSIHOST_MEM_EMAB_MASK (0x7U << GRF_MEM_CON2_DSIHOST_MEM_EMAB_SHIFT) /* 0x00000070 */ +#define GRF_MEM_CON2_VAD_MEM_EMA_SHIFT (7U) +#define GRF_MEM_CON2_VAD_MEM_EMA_MASK (0x7U << GRF_MEM_CON2_VAD_MEM_EMA_SHIFT) /* 0x00000380 */ +#define GRF_MEM_CON2_VAD_MEM_EMAW_SHIFT (10U) +#define GRF_MEM_CON2_VAD_MEM_EMAW_MASK (0x3U << GRF_MEM_CON2_VAD_MEM_EMAW_SHIFT) /* 0x00000C00 */ +#define GRF_MEM_CON2_ROM_EMA_SHIFT (12U) +#define GRF_MEM_CON2_ROM_EMA_MASK (0x7U << GRF_MEM_CON2_ROM_EMA_SHIFT) /* 0x00007000 */ +/* MEM_CON3 */ +#define GRF_MEM_CON3_OFFSET (0x30CU) +#define GRF_MEM_CON3_SDIO_MEM_EMA_SHIFT (0U) +#define GRF_MEM_CON3_SDIO_MEM_EMA_MASK (0x7U << GRF_MEM_CON3_SDIO_MEM_EMA_SHIFT) /* 0x00000007 */ +#define GRF_MEM_CON3_SDIO_MEM_EMAW_SHIFT (3U) +#define GRF_MEM_CON3_SDIO_MEM_EMAW_MASK (0x3U << GRF_MEM_CON3_SDIO_MEM_EMAW_SHIFT) /* 0x00000018 */ +#define GRF_MEM_CON3_SDIO_MEM_EMAS_SHIFT (5U) +#define GRF_MEM_CON3_SDIO_MEM_EMAS_MASK (0x1U << GRF_MEM_CON3_SDIO_MEM_EMAS_SHIFT) /* 0x00000020 */ +#define GRF_MEM_CON3_DSPTCM_MEM_EMA_SHIFT (6U) +#define GRF_MEM_CON3_DSPTCM_MEM_EMA_MASK (0x7U << GRF_MEM_CON3_DSPTCM_MEM_EMA_SHIFT) /* 0x000001C0 */ +#define GRF_MEM_CON3_DSPTCM_MEM_EMAW_SHIFT (9U) +#define GRF_MEM_CON3_DSPTCM_MEM_EMAW_MASK (0x3U << GRF_MEM_CON3_DSPTCM_MEM_EMAW_SHIFT) /* 0x00000600 */ +#define GRF_MEM_CON3_DSPCACHE_MEM_EMA_SHIFT (11U) +#define GRF_MEM_CON3_DSPCACHE_MEM_EMA_MASK (0x7U << GRF_MEM_CON3_DSPCACHE_MEM_EMA_SHIFT) /* 0x00003800 */ +#define GRF_MEM_CON3_DSPCACHE_MEM_EMAW_SHIFT (14U) +#define GRF_MEM_CON3_DSPCACHE_MEM_EMAW_MASK (0x3U << GRF_MEM_CON3_DSPCACHE_MEM_EMAW_SHIFT) /* 0x0000C000 */ +/* MEM_CON4 */ +#define GRF_MEM_CON4_OFFSET (0x310U) +#define GRF_MEM_CON4_CIF_DP_EMAA_SHIFT (0U) +#define GRF_MEM_CON4_CIF_DP_EMAA_MASK (0x7U << GRF_MEM_CON4_CIF_DP_EMAA_SHIFT) /* 0x00000007 */ +#define GRF_MEM_CON4_CIF_DP_EMASA_SHIFT (3U) +#define GRF_MEM_CON4_CIF_DP_EMASA_MASK (0x1U << GRF_MEM_CON4_CIF_DP_EMASA_SHIFT) /* 0x00000008 */ +#define GRF_MEM_CON4_CIF_DP_EMAB_SHIFT (4U) +#define GRF_MEM_CON4_CIF_DP_EMAB_MASK (0x7U << GRF_MEM_CON4_CIF_DP_EMAB_SHIFT) /* 0x00000070 */ +#define GRF_MEM_CON4_CIF_SP_EMA_SHIFT (7U) +#define GRF_MEM_CON4_CIF_SP_EMA_MASK (0x7U << GRF_MEM_CON4_CIF_SP_EMA_SHIFT) /* 0x00000380 */ +#define GRF_MEM_CON4_CIF_SP_EMAW_SHIFT (10U) +#define GRF_MEM_CON4_CIF_SP_EMAW_MASK (0x3U << GRF_MEM_CON4_CIF_SP_EMAW_SHIFT) /* 0x00000C00 */ +/* MEM_CON5 */ +#define GRF_MEM_CON5_OFFSET (0x314U) +#define GRF_MEM_CON5_USB2_SP_EMA_SHIFT (0U) +#define GRF_MEM_CON5_USB2_SP_EMA_MASK (0x7U << GRF_MEM_CON5_USB2_SP_EMA_SHIFT) /* 0x00000007 */ +#define GRF_MEM_CON5_USB2_SP_EMAW_SHIFT (3U) +#define GRF_MEM_CON5_USB2_SP_EMAW_MASK (0x3U << GRF_MEM_CON5_USB2_SP_EMAW_SHIFT) /* 0x00000018 */ +#define GRF_MEM_CON5_VOP_DPRA_EMA_SHIFT (5U) +#define GRF_MEM_CON5_VOP_DPRA_EMA_MASK (0x7U << GRF_MEM_CON5_VOP_DPRA_EMA_SHIFT) /* 0x000000E0 */ +#define GRF_MEM_CON5_VOP_DPRA_EMAW_SHIFT (8U) +#define GRF_MEM_CON5_VOP_DPRA_EMAW_MASK (0x3U << GRF_MEM_CON5_VOP_DPRA_EMAW_SHIFT) /* 0x00000300 */ +#define GRF_MEM_CON5_VOP_DPRA_EMAS_SHIFT (10U) +#define GRF_MEM_CON5_VOP_DPRA_EMAS_MASK (0x1U << GRF_MEM_CON5_VOP_DPRA_EMAS_SHIFT) /* 0x00000400 */ +#define GRF_MEM_CON5_VOP_DPRA_EMAP_SHIFT (11U) +#define GRF_MEM_CON5_VOP_DPRA_EMAP_MASK (0x1U << GRF_MEM_CON5_VOP_DPRA_EMAP_SHIFT) /* 0x00000800 */ +/* MEM_CON6 */ +#define GRF_MEM_CON6_OFFSET (0x318U) +#define GRF_MEM_CON6_ACODEC_SP_EMA_SHIFT (0U) +#define GRF_MEM_CON6_ACODEC_SP_EMA_MASK (0x7U << GRF_MEM_CON6_ACODEC_SP_EMA_SHIFT) /* 0x00000007 */ +#define GRF_MEM_CON6_ACODEC_SP_EMAW_SHIFT (3U) +#define GRF_MEM_CON6_ACODEC_SP_EMAW_MASK (0x3U << GRF_MEM_CON6_ACODEC_SP_EMAW_SHIFT) /* 0x00000018 */ +/* USBPHY_CON0 */ +#define GRF_USBPHY_CON0_OFFSET (0x340U) +#define GRF_USBPHY_CON0_UTMI_SEL_SHIFT (0U) +#define GRF_USBPHY_CON0_UTMI_SEL_MASK (0x1U << GRF_USBPHY_CON0_UTMI_SEL_SHIFT) /* 0x00000001 */ +#define GRF_USBPHY_CON0_UTMI_SUSPEND_N_SHIFT (1U) +#define GRF_USBPHY_CON0_UTMI_SUSPEND_N_MASK (0x1U << GRF_USBPHY_CON0_UTMI_SUSPEND_N_SHIFT) /* 0x00000002 */ +#define GRF_USBPHY_CON0_UTMI_OPMODE_SHIFT (2U) +#define GRF_USBPHY_CON0_UTMI_OPMODE_MASK (0x3U << GRF_USBPHY_CON0_UTMI_OPMODE_SHIFT) /* 0x0000000C */ +#define GRF_USBPHY_CON0_UTMI_XCVRSELECT_SHIFT (4U) +#define GRF_USBPHY_CON0_UTMI_XCVRSELECT_MASK (0x3U << GRF_USBPHY_CON0_UTMI_XCVRSELECT_SHIFT) /* 0x00000030 */ +#define GRF_USBPHY_CON0_UTMI_TERMSELECT_SHIFT (6U) +#define GRF_USBPHY_CON0_UTMI_TERMSELECT_MASK (0x1U << GRF_USBPHY_CON0_UTMI_TERMSELECT_SHIFT) /* 0x00000040 */ +#define GRF_USBPHY_CON0_UTMI_DPPULLDOWN_SHIFT (7U) +#define GRF_USBPHY_CON0_UTMI_DPPULLDOWN_MASK (0x1U << GRF_USBPHY_CON0_UTMI_DPPULLDOWN_SHIFT) /* 0x00000080 */ +#define GRF_USBPHY_CON0_UTMI_DMPULLDOWN_SHIFT (8U) +#define GRF_USBPHY_CON0_UTMI_DMPULLDOWN_MASK (0x1U << GRF_USBPHY_CON0_UTMI_DMPULLDOWN_SHIFT) /* 0x00000100 */ +/* USBPHY_CON1 */ +#define GRF_USBPHY_CON1_OFFSET (0x344U) +#define GRF_USBPHY_CON1_DATABUS16_SHIFT (0U) +#define GRF_USBPHY_CON1_DATABUS16_MASK (0x1U << GRF_USBPHY_CON1_DATABUS16_SHIFT) /* 0x00000001 */ +#define GRF_USBPHY_CON1_TX_ENABLE_N_SHIFT (1U) +#define GRF_USBPHY_CON1_TX_ENABLE_N_MASK (0x1U << GRF_USBPHY_CON1_TX_ENABLE_N_SHIFT) /* 0x00000002 */ +#define GRF_USBPHY_CON1_TX_DAT_SHIFT (2U) +#define GRF_USBPHY_CON1_TX_DAT_MASK (0x1U << GRF_USBPHY_CON1_TX_DAT_SHIFT) /* 0x00000004 */ +#define GRF_USBPHY_CON1_TX_SE0_SHIFT (3U) +#define GRF_USBPHY_CON1_TX_SE0_MASK (0x1U << GRF_USBPHY_CON1_TX_SE0_SHIFT) /* 0x00000008 */ +#define GRF_USBPHY_CON1_VCONTROL_SHIFT (4U) +#define GRF_USBPHY_CON1_VCONTROL_MASK (0xFU << GRF_USBPHY_CON1_VCONTROL_SHIFT) /* 0x000000F0 */ +#define GRF_USBPHY_CON1_VCONTROLLOADM_SHIFT (8U) +#define GRF_USBPHY_CON1_VCONTROLLOADM_MASK (0x1U << GRF_USBPHY_CON1_VCONTROLLOADM_SHIFT) /* 0x00000100 */ +#define GRF_USBPHY_CON1_TXBITSTUFFENABLE_SHIFT (9U) +#define GRF_USBPHY_CON1_TXBITSTUFFENABLE_MASK (0x1U << GRF_USBPHY_CON1_TXBITSTUFFENABLE_SHIFT) /* 0x00000200 */ +#define GRF_USBPHY_CON1_TXBITSTUFFENABLEH_SHIFT (10U) +#define GRF_USBPHY_CON1_TXBITSTUFFENABLEH_MASK (0x1U << GRF_USBPHY_CON1_TXBITSTUFFENABLEH_SHIFT) /* 0x00000400 */ +#define GRF_USBPHY_CON1_FSLSSERIALMODE_SHIFT (11U) +#define GRF_USBPHY_CON1_FSLSSERIALMODE_MASK (0x1U << GRF_USBPHY_CON1_FSLSSERIALMODE_SHIFT) /* 0x00000800 */ +#define GRF_USBPHY_CON1_PLL_EN_SHIFT (12U) +#define GRF_USBPHY_CON1_PLL_EN_MASK (0x1U << GRF_USBPHY_CON1_PLL_EN_SHIFT) /* 0x00001000 */ +#define GRF_USBPHY_CON1_LPM_ALIVE_SHIFT (13U) +#define GRF_USBPHY_CON1_LPM_ALIVE_MASK (0x1U << GRF_USBPHY_CON1_LPM_ALIVE_SHIFT) /* 0x00002000 */ +#define GRF_USBPHY_CON1_XTLSEL_SHIFT (14U) +#define GRF_USBPHY_CON1_XTLSEL_MASK (0x3U << GRF_USBPHY_CON1_XTLSEL_SHIFT) /* 0x0000C000 */ +/* USBPHY_CON2 */ +#define GRF_USBPHY_CON2_OFFSET (0x348U) +#define GRF_USBPHY_CON2_DEBUG_SEL_SHIFT (0U) +#define GRF_USBPHY_CON2_DEBUG_SEL_MASK (0xFU << GRF_USBPHY_CON2_DEBUG_SEL_SHIFT) /* 0x0000000F */ +#define GRF_USBPHY_CON2_LS_EN_SHIFT (4U) +#define GRF_USBPHY_CON2_LS_EN_MASK (0x1U << GRF_USBPHY_CON2_LS_EN_SHIFT) /* 0x00000010 */ +#define GRF_USBPHY_CON2_HS_BIST_MODE_SHIFT (5U) +#define GRF_USBPHY_CON2_HS_BIST_MODE_MASK (0x1U << GRF_USBPHY_CON2_HS_BIST_MODE_SHIFT) /* 0x00000020 */ +#define GRF_USBPHY_CON2_USB_LINESTATE_IRQ_EN_SHIFT (8U) +#define GRF_USBPHY_CON2_USB_LINESTATE_IRQ_EN_MASK (0x1U << GRF_USBPHY_CON2_USB_LINESTATE_IRQ_EN_SHIFT) /* 0x00000100 */ +#define GRF_USBPHY_CON2_USB_DISCONNECT_IRQ_EN_SHIFT (9U) +#define GRF_USBPHY_CON2_USB_DISCONNECT_IRQ_EN_MASK (0x3U << GRF_USBPHY_CON2_USB_DISCONNECT_IRQ_EN_SHIFT) /* 0x00000600 */ +/* USBPHY_CON3 */ +#define GRF_USBPHY_CON3_OFFSET (0x34CU) +#define GRF_USBPHY_CON3_XCFG_COARSE_TUNE_NUM_SHIFT (0U) +#define GRF_USBPHY_CON3_XCFG_COARSE_TUNE_NUM_MASK (0x7U << GRF_USBPHY_CON3_XCFG_COARSE_TUNE_NUM_SHIFT) /* 0x00000007 */ +#define GRF_USBPHY_CON3_XCFG_FINE_TUNE_NUM_SHIFT (3U) +#define GRF_USBPHY_CON3_XCFG_FINE_TUNE_NUM_MASK (0x7U << GRF_USBPHY_CON3_XCFG_FINE_TUNE_NUM_SHIFT) /* 0x00000038 */ +#define GRF_USBPHY_CON3_XCFG_LOCK_RANGE_MAX_SHIFT (6U) +#define GRF_USBPHY_CON3_XCFG_LOCK_RANGE_MAX_MASK (0x7U << GRF_USBPHY_CON3_XCFG_LOCK_RANGE_MAX_SHIFT) /* 0x000001C0 */ +#define GRF_USBPHY_CON3_XCFG_LOCK_RANGE_MIN_SHIFT (9U) +#define GRF_USBPHY_CON3_XCFG_LOCK_RANGE_MIN_MASK (0x7U << GRF_USBPHY_CON3_XCFG_LOCK_RANGE_MIN_SHIFT) /* 0x00000E00 */ +/* USBPHY_CON4 */ +#define GRF_USBPHY_CON4_OFFSET (0x350U) +#define GRF_USBPHY_CON4_XCFGI_SHIFT (0U) +#define GRF_USBPHY_CON4_XCFGI_MASK (0xFFFFFFFFU << GRF_USBPHY_CON4_XCFGI_SHIFT) /* 0xFFFFFFFF */ +/* USBPHY_CON5 */ +#define GRF_USBPHY_CON5_OFFSET (0x354U) +#define GRF_USBPHY_CON5_XCFGI_SHIFT (0U) +#define GRF_USBPHY_CON5_XCFGI_MASK (0xFFFFFFFFU << GRF_USBPHY_CON5_XCFGI_SHIFT) /* 0xFFFFFFFF */ +/* USBPHY_CON6 */ +#define GRF_USBPHY_CON6_OFFSET (0x358U) +#define GRF_USBPHY_CON6_XCFGI_SHIFT (0U) +#define GRF_USBPHY_CON6_XCFGI_MASK (0x3FU << GRF_USBPHY_CON6_XCFGI_SHIFT) /* 0x0000003F */ +/* USBPHY_CON7 */ +#define GRF_USBPHY_CON7_OFFSET (0x35CU) +#define GRF_USBPHY_CON7_LINESTATE_DET_CNT_SHIFT (0U) +#define GRF_USBPHY_CON7_LINESTATE_DET_CNT_MASK (0xFFFFFU << GRF_USBPHY_CON7_LINESTATE_DET_CNT_SHIFT) /* 0x000FFFFF */ +/* USBPHY_CON8 */ +#define GRF_USBPHY_CON8_OFFSET (0x360U) +#define GRF_USBPHY_CON8_DISCONNECT_DET_CNT_SHIFT (0U) +#define GRF_USBPHY_CON8_DISCONNECT_DET_CNT_MASK (0xFFFFFU << GRF_USBPHY_CON8_DISCONNECT_DET_CNT_SHIFT) /* 0x000FFFFF */ +/* USBPHY_STATUS0 */ +#define GRF_USBPHY_STATUS0_OFFSET (0x370U) +#define GRF_USBPHY_STATUS0 (0x0U) +#define GRF_USBPHY_STATUS0_XCFGO_SHIFT (0U) +#define GRF_USBPHY_STATUS0_XCFGO_MASK (0xFFU << GRF_USBPHY_STATUS0_XCFGO_SHIFT) /* 0x000000FF */ +#define GRF_USBPHY_STATUS0_DEBUG_OUT_SHIFT (8U) +#define GRF_USBPHY_STATUS0_DEBUG_OUT_MASK (0xFFFFU << GRF_USBPHY_STATUS0_DEBUG_OUT_SHIFT) /* 0x00FFFF00 */ +#define GRF_USBPHY_STATUS0_BIST_OK_SHIFT (24U) +#define GRF_USBPHY_STATUS0_BIST_OK_MASK (0x1U << GRF_USBPHY_STATUS0_BIST_OK_SHIFT) /* 0x01000000 */ +#define GRF_USBPHY_STATUS0_DATA_OE_SHIFT (25U) +#define GRF_USBPHY_STATUS0_DATA_OE_MASK (0x1U << GRF_USBPHY_STATUS0_DATA_OE_SHIFT) /* 0x02000000 */ +#define GRF_USBPHY_STATUS0_UTMI_HOSTDISCONNECT_SHIFT (26U) +#define GRF_USBPHY_STATUS0_UTMI_HOSTDISCONNECT_MASK (0x1U << GRF_USBPHY_STATUS0_UTMI_HOSTDISCONNECT_SHIFT) /* 0x04000000 */ +#define GRF_USBPHY_STATUS0_UTMI_LINESTATE_SHIFT (27U) +#define GRF_USBPHY_STATUS0_UTMI_LINESTATE_MASK (0x3U << GRF_USBPHY_STATUS0_UTMI_LINESTATE_SHIFT) /* 0x18000000 */ +#define GRF_USBPHY_STATUS0_RX_RCV_SHIFT (29U) +#define GRF_USBPHY_STATUS0_RX_RCV_MASK (0x1U << GRF_USBPHY_STATUS0_RX_RCV_SHIFT) /* 0x20000000 */ +#define GRF_USBPHY_STATUS0_RX_DP_SHIFT (30U) +#define GRF_USBPHY_STATUS0_RX_DP_MASK (0x1U << GRF_USBPHY_STATUS0_RX_DP_SHIFT) /* 0x40000000 */ +#define GRF_USBPHY_STATUS0_RX_DM_SHIFT (31U) +#define GRF_USBPHY_STATUS0_RX_DM_MASK (0x1U << GRF_USBPHY_STATUS0_RX_DM_SHIFT) /* 0x80000000 */ +/* USBPHY_STATUS1 */ +#define GRF_USBPHY_STATUS1_OFFSET (0x374U) +#define GRF_USBPHY_STATUS1_USB_LINESTATE_IRQ_SHIFT (8U) +#define GRF_USBPHY_STATUS1_USB_LINESTATE_IRQ_MASK (0x1U << GRF_USBPHY_STATUS1_USB_LINESTATE_IRQ_SHIFT) /* 0x00000100 */ +#define GRF_USBPHY_STATUS1_USB_DISCONNECT_IRQ_SHIFT (9U) +#define GRF_USBPHY_STATUS1_USB_DISCONNECT_IRQ_MASK (0x3U << GRF_USBPHY_STATUS1_USB_DISCONNECT_IRQ_SHIFT) /* 0x00000600 */ +/* DMAC_CON3 */ +#define GRF_DMAC_CON3_OFFSET (0x38CU) +#define GRF_DMAC_CON3_GRF_DRTYPE_DMAC_AUDIOPWM_SHIFT (12U) +#define GRF_DMAC_CON3_GRF_DRTYPE_DMAC_AUDIOPWM_MASK (0x3U << GRF_DMAC_CON3_GRF_DRTYPE_DMAC_AUDIOPWM_SHIFT) /* 0x00003000 */ +#define GRF_DMAC_CON3_GRF_CON_DMAC_REQ_MODIFY_DIS_AUDIOPWM_SHIFT (15U) +#define GRF_DMAC_CON3_GRF_CON_DMAC_REQ_MODIFY_DIS_AUDIOPWM_MASK (0x1U << GRF_DMAC_CON3_GRF_CON_DMAC_REQ_MODIFY_DIS_AUDIOPWM_SHIFT) /* 0x00008000 */ +/* DMAC_CON4 */ +#define GRF_DMAC_CON4_OFFSET (0x390U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART0TX_SHIFT (0U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART0TX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART0TX_SHIFT) /* 0x00000001 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART0RX_SHIFT (1U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART0RX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART0RX_SHIFT) /* 0x00000002 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART1TX_SHIFT (2U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART1TX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART1TX_SHIFT) /* 0x00000004 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART1RX_SHIFT (3U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART1RX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART1RX_SHIFT) /* 0x00000008 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART2TX_SHIFT (4U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART2TX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART2TX_SHIFT) /* 0x00000010 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART2RX_SHIFT (5U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART2RX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_UART2RX_SHIFT) /* 0x00000020 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2STX_SHIFT (6U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2STX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2STX_SHIFT) /* 0x00000040 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2SRX_SHIFT (7U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2SRX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2SRX_SHIFT) /* 0x00000080 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2S1TX_SHIFT (8U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2S1TX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2S1TX_SHIFT) /* 0x00000100 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2S1RX_SHIFT (9U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2S1RX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_I2S1RX_SHIFT) /* 0x00000200 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_PDM_SHIFT (10U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_PDM_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_PDM_SHIFT) /* 0x00000400 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI1TX_SHIFT (11U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI1TX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI1TX_SHIFT) /* 0x00000800 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI1RX_SHIFT (12U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI1RX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI1RX_SHIFT) /* 0x00001000 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI2TX_SHIFT (13U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI2TX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI2TX_SHIFT) /* 0x00002000 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI2RX_SHIFT (14U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI2RX_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_SPI2RX_SHIFT) /* 0x00004000 */ +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_PWM_SHIFT (15U) +#define GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_PWM_MASK (0x1U << GRF_DMAC_CON4_GRF_CON_DMAC_REQ_MODIFY_DIS_PWM_SHIFT) /* 0x00008000 */ +/* DMAC_CON5 */ +#define GRF_DMAC_CON5_OFFSET (0x394U) +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART0_TX_SHIFT (0U) +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART0_TX_MASK (0x3U << GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART0_TX_SHIFT) /* 0x00000003 */ +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART0_RX_SHIFT (2U) +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART0_RX_MASK (0x3U << GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART0_RX_SHIFT) /* 0x0000000C */ +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART1_TX_SHIFT (4U) +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART1_TX_MASK (0x3U << GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART1_TX_SHIFT) /* 0x00000030 */ +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART1_RX_SHIFT (6U) +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART1_RX_MASK (0x3U << GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART1_RX_SHIFT) /* 0x000000C0 */ +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART2_TX_SHIFT (8U) +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART2_TX_MASK (0x3U << GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART2_TX_SHIFT) /* 0x00000300 */ +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART2_RX_SHIFT (10U) +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART2_RX_MASK (0x3U << GRF_DMAC_CON5_GRF_DRTYPE_DMAC_UART2_RX_SHIFT) /* 0x00000C00 */ +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_I2S_TX_SHIFT (12U) +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_I2S_TX_MASK (0x3U << GRF_DMAC_CON5_GRF_DRTYPE_DMAC_I2S_TX_SHIFT) /* 0x00003000 */ +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_I2S_RX_SHIFT (14U) +#define GRF_DMAC_CON5_GRF_DRTYPE_DMAC_I2S_RX_MASK (0x3U << GRF_DMAC_CON5_GRF_DRTYPE_DMAC_I2S_RX_SHIFT) /* 0x0000C000 */ +/* DMAC_CON6 */ +#define GRF_DMAC_CON6_OFFSET (0x398U) +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_I2S1_TX_SHIFT (0U) +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_I2S1_TX_MASK (0x3U << GRF_DMAC_CON6_GRF_DRTYPE_DMAC_I2S1_TX_SHIFT) /* 0x00000003 */ +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_I2S1_RX_SHIFT (2U) +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_I2S1_RX_MASK (0x3U << GRF_DMAC_CON6_GRF_DRTYPE_DMAC_I2S1_RX_SHIFT) /* 0x0000000C */ +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_PDM_SHIFT (4U) +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_PDM_MASK (0x3U << GRF_DMAC_CON6_GRF_DRTYPE_DMAC_PDM_SHIFT) /* 0x00000030 */ +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI1_TX_SHIFT (6U) +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI1_TX_MASK (0x3U << GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI1_TX_SHIFT) /* 0x000000C0 */ +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI1_RX_SHIFT (8U) +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI1_RX_MASK (0x3U << GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI1_RX_SHIFT) /* 0x00000300 */ +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI2_TX_SHIFT (10U) +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI2_TX_MASK (0x3U << GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI2_TX_SHIFT) /* 0x00000C00 */ +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI2_RX_SHIFT (12U) +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI2_RX_MASK (0x3U << GRF_DMAC_CON6_GRF_DRTYPE_DMAC_SPI2_RX_SHIFT) /* 0x00003000 */ +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_PWM_SHIFT (14U) +#define GRF_DMAC_CON6_GRF_DRTYPE_DMAC_PWM_MASK (0x3U << GRF_DMAC_CON6_GRF_DRTYPE_DMAC_PWM_SHIFT) /* 0x0000C000 */ +/* FAST_BOOT_EN */ +#define GRF_FAST_BOOT_EN_OFFSET (0x3C0U) +#define GRF_FAST_BOOT_EN_GRF_CON_FAST_BOOT_EN_SHIFT (0U) +#define GRF_FAST_BOOT_EN_GRF_CON_FAST_BOOT_EN_MASK (0x1U << GRF_FAST_BOOT_EN_GRF_CON_FAST_BOOT_EN_SHIFT) /* 0x00000001 */ +/* FAST_BOOT_ADDR */ +#define GRF_FAST_BOOT_ADDR_OFFSET (0x3C4U) +#define GRF_FAST_BOOT_ADDR_GRF_CON_FAST_BOOT_ADDR_SHIFT (0U) +#define GRF_FAST_BOOT_ADDR_GRF_CON_FAST_BOOT_ADDR_MASK (0xFFFFFFFFU << GRF_FAST_BOOT_ADDR_GRF_CON_FAST_BOOT_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG0 */ +#define GRF_OS_REG0_OFFSET (0x400U) +#define GRF_OS_REG0_OS_REG_SHIFT (0U) +#define GRF_OS_REG0_OS_REG_MASK (0xFFFFFFFFU << GRF_OS_REG0_OS_REG_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG1 */ +#define GRF_OS_REG1_OFFSET (0x404U) +#define GRF_OS_REG1_OS_REG_SHIFT (0U) +#define GRF_OS_REG1_OS_REG_MASK (0xFFFFFFFFU << GRF_OS_REG1_OS_REG_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG2 */ +#define GRF_OS_REG2_OFFSET (0x408U) +#define GRF_OS_REG2_OS_REG_SHIFT (0U) +#define GRF_OS_REG2_OS_REG_MASK (0xFFFFFFFFU << GRF_OS_REG2_OS_REG_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG3 */ +#define GRF_OS_REG3_OFFSET (0x40CU) +#define GRF_OS_REG3_OS_REG_SHIFT (0U) +#define GRF_OS_REG3_OS_REG_MASK (0xFFFFFFFFU << GRF_OS_REG3_OS_REG_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG4 */ +#define GRF_OS_REG4_OFFSET (0x410U) +#define GRF_OS_REG4_OS_REG_SHIFT (0U) +#define GRF_OS_REG4_OS_REG_MASK (0xFFFFFFFFU << GRF_OS_REG4_OS_REG_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG5 */ +#define GRF_OS_REG5_OFFSET (0x414U) +#define GRF_OS_REG5_OS_REG_SHIFT (0U) +#define GRF_OS_REG5_OS_REG_MASK (0xFFFFFFFFU << GRF_OS_REG5_OS_REG_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG6 */ +#define GRF_OS_REG6_OFFSET (0x418U) +#define GRF_OS_REG6_OS_REG_SHIFT (0U) +#define GRF_OS_REG6_OS_REG_MASK (0xFFFFFFFFU << GRF_OS_REG6_OS_REG_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG7 */ +#define GRF_OS_REG7_OFFSET (0x41CU) +#define GRF_OS_REG7_OS_REG_SHIFT (0U) +#define GRF_OS_REG7_OS_REG_MASK (0xFFFFFFFFU << GRF_OS_REG7_OS_REG_SHIFT) /* 0xFFFFFFFF */ +/* CHIP_ID */ +#define GRF_CHIP_ID_OFFSET (0xF00U) +#define GRF_CHIP_ID (0x2108U) +#define GRF_CHIP_ID_CHIP_ID_SHIFT (0U) +#define GRF_CHIP_ID_CHIP_ID_MASK (0xFFFFFFFFU << GRF_CHIP_ID_CHIP_ID_SHIFT) /* 0xFFFFFFFF */ +/******************************************MBOX******************************************/ +/* A2B_INTEN */ +#define MBOX_A2B_INTEN_OFFSET (0x0U) +#define MBOX_A2B_INTEN_INT0_SHIFT (0U) +#define MBOX_A2B_INTEN_INT0_MASK (0x1U << MBOX_A2B_INTEN_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_A2B_INTEN_INT1_SHIFT (1U) +#define MBOX_A2B_INTEN_INT1_MASK (0x1U << MBOX_A2B_INTEN_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_A2B_INTEN_INT2_SHIFT (2U) +#define MBOX_A2B_INTEN_INT2_MASK (0x1U << MBOX_A2B_INTEN_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_A2B_INTEN_INT3_SHIFT (3U) +#define MBOX_A2B_INTEN_INT3_MASK (0x1U << MBOX_A2B_INTEN_INT3_SHIFT) /* 0x00000008 */ +/* A2B_STATUS */ +#define MBOX_A2B_STATUS_OFFSET (0x4U) +#define MBOX_A2B_STATUS_INT0_SHIFT (0U) +#define MBOX_A2B_STATUS_INT0_MASK (0x1U << MBOX_A2B_STATUS_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_A2B_STATUS_INT1_SHIFT (1U) +#define MBOX_A2B_STATUS_INT1_MASK (0x1U << MBOX_A2B_STATUS_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_A2B_STATUS_INT2_SHIFT (2U) +#define MBOX_A2B_STATUS_INT2_MASK (0x1U << MBOX_A2B_STATUS_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_A2B_STATUS_INT3_SHIFT (3U) +#define MBOX_A2B_STATUS_INT3_MASK (0x1U << MBOX_A2B_STATUS_INT3_SHIFT) /* 0x00000008 */ +/* A2B_CMD_0 */ +#define MBOX_A2B_CMD_0_OFFSET (0x8U) +#define MBOX_A2B_CMD_0_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_0_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_0 */ +#define MBOX_A2B_DAT_0_OFFSET (0xCU) +#define MBOX_A2B_DAT_0_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_0_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_1 */ +#define MBOX_A2B_CMD_1_OFFSET (0x10U) +#define MBOX_A2B_CMD_1_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_1_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_1 */ +#define MBOX_A2B_DAT_1_OFFSET (0x14U) +#define MBOX_A2B_DAT_1_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_1_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_2 */ +#define MBOX_A2B_CMD_2_OFFSET (0x18U) +#define MBOX_A2B_CMD_2_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_2_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_2 */ +#define MBOX_A2B_DAT_2_OFFSET (0x1CU) +#define MBOX_A2B_DAT_2_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_2_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_3 */ +#define MBOX_A2B_CMD_3_OFFSET (0x20U) +#define MBOX_A2B_CMD_3_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_3_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_3 */ +#define MBOX_A2B_DAT_3_OFFSET (0x24U) +#define MBOX_A2B_DAT_3_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_3_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_INTEN */ +#define MBOX_B2A_INTEN_OFFSET (0x28U) +#define MBOX_B2A_INTEN_INT0_SHIFT (0U) +#define MBOX_B2A_INTEN_INT0_MASK (0x1U << MBOX_B2A_INTEN_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_B2A_INTEN_INT1_SHIFT (1U) +#define MBOX_B2A_INTEN_INT1_MASK (0x1U << MBOX_B2A_INTEN_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_B2A_INTEN_INT2_SHIFT (2U) +#define MBOX_B2A_INTEN_INT2_MASK (0x1U << MBOX_B2A_INTEN_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_B2A_INTEN_INT3_SHIFT (3U) +#define MBOX_B2A_INTEN_INT3_MASK (0x1U << MBOX_B2A_INTEN_INT3_SHIFT) /* 0x00000008 */ +/* B2A_STATUS */ +#define MBOX_B2A_STATUS_OFFSET (0x2CU) +#define MBOX_B2A_STATUS_INT0_SHIFT (0U) +#define MBOX_B2A_STATUS_INT0_MASK (0x1U << MBOX_B2A_STATUS_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_B2A_STATUS_INT1_SHIFT (1U) +#define MBOX_B2A_STATUS_INT1_MASK (0x1U << MBOX_B2A_STATUS_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_B2A_STATUS_INT2_SHIFT (2U) +#define MBOX_B2A_STATUS_INT2_MASK (0x1U << MBOX_B2A_STATUS_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_B2A_STATUS_INT3_SHIFT (3U) +#define MBOX_B2A_STATUS_INT3_MASK (0x1U << MBOX_B2A_STATUS_INT3_SHIFT) /* 0x00000008 */ +/* B2A_CMD_0 */ +#define MBOX_B2A_CMD_0_OFFSET (0x30U) +#define MBOX_B2A_CMD_0_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_0_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_0 */ +#define MBOX_B2A_DAT_0_OFFSET (0x34U) +#define MBOX_B2A_DAT_0_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_0_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_1 */ +#define MBOX_B2A_CMD_1_OFFSET (0x38U) +#define MBOX_B2A_CMD_1_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_1_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_1 */ +#define MBOX_B2A_DAT_1_OFFSET (0x3CU) +#define MBOX_B2A_DAT_1_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_1_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_2 */ +#define MBOX_B2A_CMD_2_OFFSET (0x40U) +#define MBOX_B2A_CMD_2_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_2_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_2 */ +#define MBOX_B2A_DAT_2_OFFSET (0x44U) +#define MBOX_B2A_DAT_2_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_2_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_3 */ +#define MBOX_B2A_CMD_3_OFFSET (0x48U) +#define MBOX_B2A_CMD_3_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_3_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_3 */ +#define MBOX_B2A_DAT_3_OFFSET (0x4CU) +#define MBOX_B2A_DAT_3_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_3_DATA_SHIFT) /* 0xFFFFFFFF */ +/* ATOMIC_LOCK_00 */ +#define MBOX_ATOMIC_LOCK_00_OFFSET (0x100U) +#define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_MASK (0x1U << MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_01 */ +#define MBOX_ATOMIC_LOCK_01_OFFSET (0x104U) +#define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_MASK (0x1U << MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_02 */ +#define MBOX_ATOMIC_LOCK_02_OFFSET (0x108U) +#define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_MASK (0x1U << MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_03 */ +#define MBOX_ATOMIC_LOCK_03_OFFSET (0x10CU) +#define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_MASK (0x1U << MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_04 */ +#define MBOX_ATOMIC_LOCK_04_OFFSET (0x110U) +#define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_MASK (0x1U << MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_05 */ +#define MBOX_ATOMIC_LOCK_05_OFFSET (0x114U) +#define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_MASK (0x1U << MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_06 */ +#define MBOX_ATOMIC_LOCK_06_OFFSET (0x118U) +#define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_MASK (0x1U << MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_07 */ +#define MBOX_ATOMIC_LOCK_07_OFFSET (0x11CU) +#define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_MASK (0x1U << MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_08 */ +#define MBOX_ATOMIC_LOCK_08_OFFSET (0x120U) +#define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_MASK (0x1U << MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_09 */ +#define MBOX_ATOMIC_LOCK_09_OFFSET (0x124U) +#define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_MASK (0x1U << MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_10 */ +#define MBOX_ATOMIC_LOCK_10_OFFSET (0x128U) +#define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_MASK (0x1U << MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_11 */ +#define MBOX_ATOMIC_LOCK_11_OFFSET (0x12CU) +#define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_MASK (0x1U << MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_12 */ +#define MBOX_ATOMIC_LOCK_12_OFFSET (0x130U) +#define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_MASK (0x1U << MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_13 */ +#define MBOX_ATOMIC_LOCK_13_OFFSET (0x134U) +#define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_MASK (0x1U << MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_14 */ +#define MBOX_ATOMIC_LOCK_14_OFFSET (0x138U) +#define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_MASK (0x1U << MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_15 */ +#define MBOX_ATOMIC_LOCK_15_OFFSET (0x13CU) +#define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_MASK (0x1U << MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_16 */ +#define MBOX_ATOMIC_LOCK_16_OFFSET (0x140U) +#define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_MASK (0x1U << MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_17 */ +#define MBOX_ATOMIC_LOCK_17_OFFSET (0x144U) +#define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_MASK (0x1U << MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_18 */ +#define MBOX_ATOMIC_LOCK_18_OFFSET (0x148U) +#define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_MASK (0x1U << MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_19 */ +#define MBOX_ATOMIC_LOCK_19_OFFSET (0x14CU) +#define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_MASK (0x1U << MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_20 */ +#define MBOX_ATOMIC_LOCK_20_OFFSET (0x150U) +#define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_MASK (0x1U << MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_21 */ +#define MBOX_ATOMIC_LOCK_21_OFFSET (0x154U) +#define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_MASK (0x1U << MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_22 */ +#define MBOX_ATOMIC_LOCK_22_OFFSET (0x158U) +#define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_MASK (0x1U << MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_23 */ +#define MBOX_ATOMIC_LOCK_23_OFFSET (0x15CU) +#define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_MASK (0x1U << MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_24 */ +#define MBOX_ATOMIC_LOCK_24_OFFSET (0x160U) +#define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_MASK (0x1U << MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_25 */ +#define MBOX_ATOMIC_LOCK_25_OFFSET (0x164U) +#define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_MASK (0x1U << MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_26 */ +#define MBOX_ATOMIC_LOCK_26_OFFSET (0x168U) +#define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_MASK (0x1U << MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_27 */ +#define MBOX_ATOMIC_LOCK_27_OFFSET (0x16CU) +#define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_MASK (0x1U << MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_28 */ +#define MBOX_ATOMIC_LOCK_28_OFFSET (0x170U) +#define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_MASK (0x1U << MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_29 */ +#define MBOX_ATOMIC_LOCK_29_OFFSET (0x174U) +#define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_MASK (0x1U << MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_30 */ +#define MBOX_ATOMIC_LOCK_30_OFFSET (0x178U) +#define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_MASK (0x1U << MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_31 */ +#define MBOX_ATOMIC_LOCK_31_OFFSET (0x17CU) +#define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_MASK (0x1U << MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT) /* 0x00000001 */ +/******************************************PMU*******************************************/ +/* WAKEUP_CFG0 */ +#define PMU_WAKEUP_CFG0_OFFSET (0x0U) +#define PMU_WAKEUP_CFG0_GPIO0D_POSEDGE_EN_SHIFT (0U) +#define PMU_WAKEUP_CFG0_GPIO0D_POSEDGE_EN_MASK (0xFFU << PMU_WAKEUP_CFG0_GPIO0D_POSEDGE_EN_SHIFT) /* 0x000000FF */ +#define PMU_WAKEUP_CFG0_GPIO1B_POSEDGE_EN_SHIFT (8U) +#define PMU_WAKEUP_CFG0_GPIO1B_POSEDGE_EN_MASK (0xFFU << PMU_WAKEUP_CFG0_GPIO1B_POSEDGE_EN_SHIFT) /* 0x0000FF00 */ +/* WAKEUP_CFG1 */ +#define PMU_WAKEUP_CFG1_OFFSET (0x4U) +#define PMU_WAKEUP_CFG1_GPIO0D_NEGEDGE_EN_SHIFT (0U) +#define PMU_WAKEUP_CFG1_GPIO0D_NEGEDGE_EN_MASK (0xFFU << PMU_WAKEUP_CFG1_GPIO0D_NEGEDGE_EN_SHIFT) /* 0x000000FF */ +#define PMU_WAKEUP_CFG1_GPIO1B_NEGEDGE_EN_SHIFT (8U) +#define PMU_WAKEUP_CFG1_GPIO1B_NEGEDGE_EN_MASK (0xFFU << PMU_WAKEUP_CFG1_GPIO1B_NEGEDGE_EN_SHIFT) /* 0x0000FF00 */ +/* WAKEUP_CFG2 */ +#define PMU_WAKEUP_CFG2_OFFSET (0x8U) +#define PMU_WAKEUP_CFG2_GPIO0D_POSEDGE_EN_SHIFT (0U) +#define PMU_WAKEUP_CFG2_GPIO0D_POSEDGE_EN_MASK (0xFFU << PMU_WAKEUP_CFG2_GPIO0D_POSEDGE_EN_SHIFT) /* 0x000000FF */ +#define PMU_WAKEUP_CFG2_GPIO1B_POSEDGE_EN_SHIFT (8U) +#define PMU_WAKEUP_CFG2_GPIO1B_POSEDGE_EN_MASK (0xFFU << PMU_WAKEUP_CFG2_GPIO1B_POSEDGE_EN_SHIFT) /* 0x0000FF00 */ +/* WAKEUP_CFG3 */ +#define PMU_WAKEUP_CFG3_OFFSET (0xCU) +#define PMU_WAKEUP_CFG3_GPIO0D_NEGEDGE_EN_SHIFT (0U) +#define PMU_WAKEUP_CFG3_GPIO0D_NEGEDGE_EN_MASK (0xFFU << PMU_WAKEUP_CFG3_GPIO0D_NEGEDGE_EN_SHIFT) /* 0x000000FF */ +#define PMU_WAKEUP_CFG3_GPIO1B_NEGEDGE_EN_SHIFT (8U) +#define PMU_WAKEUP_CFG3_GPIO1B_NEGEDGE_EN_MASK (0xFFU << PMU_WAKEUP_CFG3_GPIO1B_NEGEDGE_EN_SHIFT) /* 0x0000FF00 */ +/* WAKEUP_CFG6 */ +#define PMU_WAKEUP_CFG6_OFFSET (0x18U) +#define PMU_WAKEUP_CFG6_PWRMODE_INT_WAKEUP_EN_SHIFT (0U) +#define PMU_WAKEUP_CFG6_PWRMODE_INT_WAKEUP_EN_MASK (0x1U << PMU_WAKEUP_CFG6_PWRMODE_INT_WAKEUP_EN_SHIFT) /* 0x00000001 */ +#define PMU_WAKEUP_CFG6_GPIO_INT_EN_SHIFT (1U) +#define PMU_WAKEUP_CFG6_GPIO_INT_EN_MASK (0x1U << PMU_WAKEUP_CFG6_GPIO_INT_EN_SHIFT) /* 0x00000002 */ +#define PMU_WAKEUP_CFG6_TIMEOUT_EN_SHIFT (2U) +#define PMU_WAKEUP_CFG6_TIMEOUT_EN_MASK (0x1U << PMU_WAKEUP_CFG6_TIMEOUT_EN_SHIFT) /* 0x00000004 */ +#define PMU_WAKEUP_CFG6_TIMER_EN_SHIFT (3U) +#define PMU_WAKEUP_CFG6_TIMER_EN_MASK (0x1U << PMU_WAKEUP_CFG6_TIMER_EN_SHIFT) /* 0x00000008 */ +#define PMU_WAKEUP_CFG6_VAD_EN_SHIFT (4U) +#define PMU_WAKEUP_CFG6_VAD_EN_MASK (0x1U << PMU_WAKEUP_CFG6_VAD_EN_SHIFT) /* 0x00000010 */ +#define PMU_WAKEUP_CFG6_PWRMODE_WAKEUP_SFT_INT_SHIFT (5U) +#define PMU_WAKEUP_CFG6_PWRMODE_WAKEUP_SFT_INT_MASK (0x1U << PMU_WAKEUP_CFG6_PWRMODE_WAKEUP_SFT_INT_SHIFT) /* 0x00000020 */ +/* PWRDN_CON */ +#define PMU_PWRDN_CON_OFFSET (0x30U) +#define PMU_PWRDN_CON_PD_DSP_PWRDWN_EN_SHIFT (0U) +#define PMU_PWRDN_CON_PD_DSP_PWRDWN_EN_MASK (0x1U << PMU_PWRDN_CON_PD_DSP_PWRDWN_EN_SHIFT) /* 0x00000001 */ +#define PMU_PWRDN_CON_PD_LOGIC_PWRDWN_EN_SHIFT (1U) +#define PMU_PWRDN_CON_PD_LOGIC_PWRDWN_EN_MASK (0x1U << PMU_PWRDN_CON_PD_LOGIC_PWRDWN_EN_SHIFT) /* 0x00000002 */ +#define PMU_PWRDN_CON_PD_SHRM_PWRDWN_EN_SHIFT (2U) +#define PMU_PWRDN_CON_PD_SHRM_PWRDWN_EN_MASK (0x1U << PMU_PWRDN_CON_PD_SHRM_PWRDWN_EN_SHIFT) /* 0x00000004 */ +#define PMU_PWRDN_CON_PD_AUDIO_PWRDWN_EN_SHIFT (3U) +#define PMU_PWRDN_CON_PD_AUDIO_PWRDWN_EN_MASK (0x1U << PMU_PWRDN_CON_PD_AUDIO_PWRDWN_EN_SHIFT) /* 0x00000008 */ +/* PWRDN_ST */ +#define PMU_PWRDN_ST_OFFSET (0x34U) +#define PMU_PWRDN_ST (0x0U) +#define PMU_PWRDN_ST_PD_DSP_PWR_STAT_SHIFT (0U) +#define PMU_PWRDN_ST_PD_DSP_PWR_STAT_MASK (0x1U << PMU_PWRDN_ST_PD_DSP_PWR_STAT_SHIFT) /* 0x00000001 */ +#define PMU_PWRDN_ST_PD_LOGIC_PWR_STAT_SHIFT (1U) +#define PMU_PWRDN_ST_PD_LOGIC_PWR_STAT_MASK (0x1U << PMU_PWRDN_ST_PD_LOGIC_PWR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_PWRDN_ST_PD_SHRM_PWR_STAT_SHIFT (2U) +#define PMU_PWRDN_ST_PD_SHRM_PWR_STAT_MASK (0x1U << PMU_PWRDN_ST_PD_SHRM_PWR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_PWRDN_ST_PD_AUDIO_PWR_STAT_SHIFT (3U) +#define PMU_PWRDN_ST_PD_AUDIO_PWR_STAT_MASK (0x1U << PMU_PWRDN_ST_PD_AUDIO_PWR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_PWRDN_ST_SHAREMEM_PWR_STAT_SHIFT (4U) +#define PMU_PWRDN_ST_SHAREMEM_PWR_STAT_MASK (0xFU << PMU_PWRDN_ST_SHAREMEM_PWR_STAT_SHIFT) /* 0x000000F0 */ +/* PLL_CON */ +#define PMU_PLL_CON_OFFSET (0x38U) +#define PMU_PLL_CON_PLL_PD_CFG_SHIFT (0U) +#define PMU_PLL_CON_PLL_PD_CFG_MASK (0x7U << PMU_PLL_CON_PLL_PD_CFG_SHIFT) /* 0x00000007 */ +#define PMU_PLL_CON_SFT_PLL_PD_SHIFT (3U) +#define PMU_PLL_CON_SFT_PLL_PD_MASK (0x7U << PMU_PLL_CON_SFT_PLL_PD_SHIFT) /* 0x00000038 */ +/* PWRMODE_CON */ +#define PMU_PWRMODE_CON_OFFSET (0x3CU) +#define PMU_PWRMODE_CON_POWER_MODE_EN_SHIFT (0U) +#define PMU_PWRMODE_CON_POWER_MODE_EN_MASK (0x1U << PMU_PWRMODE_CON_POWER_MODE_EN_SHIFT) /* 0x00000001 */ +#define PMU_PWRMODE_CON_OSC_DISABLE_SHIFT (1U) +#define PMU_PWRMODE_CON_OSC_DISABLE_MASK (0x1U << PMU_PWRMODE_CON_OSC_DISABLE_SHIFT) /* 0x00000002 */ +#define PMU_PWRMODE_CON_PMU_USE_LF_SHIFT (2U) +#define PMU_PWRMODE_CON_PMU_USE_LF_MASK (0x1U << PMU_PWRMODE_CON_PMU_USE_LF_SHIFT) /* 0x00000004 */ +#define PMU_PWRMODE_CON_PLL_PD_EN_SHIFT (3U) +#define PMU_PWRMODE_CON_PLL_PD_EN_MASK (0x1U << PMU_PWRMODE_CON_PLL_PD_EN_SHIFT) /* 0x00000008 */ +#define PMU_PWRMODE_CON_LOGIC_PD_EN_SHIFT (4U) +#define PMU_PWRMODE_CON_LOGIC_PD_EN_MASK (0x1U << PMU_PWRMODE_CON_LOGIC_PD_EN_SHIFT) /* 0x00000010 */ +#define PMU_PWRMODE_CON_PWRMODE_LDO_ADJ_EN_SHIFT (5U) +#define PMU_PWRMODE_CON_PWRMODE_LDO_ADJ_EN_MASK (0x1U << PMU_PWRMODE_CON_PWRMODE_LDO_ADJ_EN_SHIFT) /* 0x00000020 */ +#define PMU_PWRMODE_CON_BYPASS_PLL_LOCK_SHIFT (6U) +#define PMU_PWRMODE_CON_BYPASS_PLL_LOCK_MASK (0x1U << PMU_PWRMODE_CON_BYPASS_PLL_LOCK_SHIFT) /* 0x00000040 */ +#define PMU_PWRMODE_CON_BYPASS_HF_EN_SHIFT (7U) +#define PMU_PWRMODE_CON_BYPASS_HF_EN_MASK (0x1U << PMU_PWRMODE_CON_BYPASS_HF_EN_SHIFT) /* 0x00000080 */ +#define PMU_PWRMODE_CON_GLOBAL_INT_DISABLE_CFG_SHIFT (8U) +#define PMU_PWRMODE_CON_GLOBAL_INT_DISABLE_CFG_MASK (0x1U << PMU_PWRMODE_CON_GLOBAL_INT_DISABLE_CFG_SHIFT) /* 0x00000100 */ +#define PMU_PWRMODE_CON_SHRM_PD_EN_SHIFT (9U) +#define PMU_PWRMODE_CON_SHRM_PD_EN_MASK (0x1U << PMU_PWRMODE_CON_SHRM_PD_EN_SHIFT) /* 0x00000200 */ +#define PMU_PWRMODE_CON_SHRM_MEM_RETPD_EN_SHIFT (10U) +#define PMU_PWRMODE_CON_SHRM_MEM_RETPD_EN_MASK (0x1U << PMU_PWRMODE_CON_SHRM_MEM_RETPD_EN_SHIFT) /* 0x00000400 */ +#define PMU_PWRMODE_CON_PLLPD_WAIT_EN_SHIFT (11U) +#define PMU_PWRMODE_CON_PLLPD_WAIT_EN_MASK (0x1U << PMU_PWRMODE_CON_PLLPD_WAIT_EN_SHIFT) /* 0x00000800 */ +/* SFT_CON */ +#define PMU_SFT_CON_OFFSET (0x40U) +#define PMU_SFT_CON_OSC_DISABLE_CFG_SHIFT (0U) +#define PMU_SFT_CON_OSC_DISABLE_CFG_MASK (0x1U << PMU_SFT_CON_OSC_DISABLE_CFG_SHIFT) /* 0x00000001 */ +#define PMU_SFT_CON_PMU_LF_ENA_CFG_SHIFT (1U) +#define PMU_SFT_CON_PMU_LF_ENA_CFG_MASK (0x1U << PMU_SFT_CON_PMU_LF_ENA_CFG_SHIFT) /* 0x00000002 */ +#define PMU_SFT_CON_PMU_LF_MODE_CFG_SHIFT (2U) +#define PMU_SFT_CON_PMU_LF_MODE_CFG_MASK (0x1U << PMU_SFT_CON_PMU_LF_MODE_CFG_SHIFT) /* 0x00000004 */ +#define PMU_SFT_CON_PWRMODE_EN_SFT_SHIFT (3U) +#define PMU_SFT_CON_PWRMODE_EN_SFT_MASK (0x1U << PMU_SFT_CON_PWRMODE_EN_SFT_SHIFT) /* 0x00000008 */ +/* LDO_CON0 */ +#define PMU_LDO_CON0_OFFSET (0x50U) +#define PMU_LDO_CON0_LDO_MIPI_EN_SHIFT (0U) +#define PMU_LDO_CON0_LDO_MIPI_EN_MASK (0x1U << PMU_LDO_CON0_LDO_MIPI_EN_SHIFT) /* 0x00000001 */ +#define PMU_LDO_CON0_LDO_AUDIO_EN_SHIFT (1U) +#define PMU_LDO_CON0_LDO_AUDIO_EN_MASK (0x1U << PMU_LDO_CON0_LDO_AUDIO_EN_SHIFT) /* 0x00000002 */ +#define PMU_LDO_CON0_LDO_AUDIO_SFT_SHIFT (2U) +#define PMU_LDO_CON0_LDO_AUDIO_SFT_MASK (0x3U << PMU_LDO_CON0_LDO_AUDIO_SFT_SHIFT) /* 0x0000000C */ +#define PMU_LDO_CON0_LDO_BGADJ_SHIFT (4U) +#define PMU_LDO_CON0_LDO_BGADJ_MASK (0x7U << PMU_LDO_CON0_LDO_BGADJ_SHIFT) /* 0x00000070 */ +#define PMU_LDO_CON0_LDO_REFADJ_SHIFT (8U) +#define PMU_LDO_CON0_LDO_REFADJ_MASK (0xFU << PMU_LDO_CON0_LDO_REFADJ_SHIFT) /* 0x00000F00 */ +/* LDO_CON1 */ +#define PMU_LDO_CON1_OFFSET (0x54U) +#define PMU_LDO_CON1_MCU_LDOCORE_SFT_SHIFT (0U) +#define PMU_LDO_CON1_MCU_LDOCORE_SFT_MASK (0x7U << PMU_LDO_CON1_MCU_LDOCORE_SFT_SHIFT) /* 0x00000007 */ +#define PMU_LDO_CON1_PWRMODE_LDOCORE_ADJ_SHIFT (4U) +#define PMU_LDO_CON1_PWRMODE_LDOCORE_ADJ_MASK (0x7U << PMU_LDO_CON1_PWRMODE_LDOCORE_ADJ_SHIFT) /* 0x00000070 */ +#define PMU_LDO_CON1_MCU_LDOMIPI_SFT_SHIFT (8U) +#define PMU_LDO_CON1_MCU_LDOMIPI_SFT_MASK (0x7U << PMU_LDO_CON1_MCU_LDOMIPI_SFT_SHIFT) /* 0x00000700 */ +#define PMU_LDO_CON1_PWRMODE_LDOMIPI_ADJ_SHIFT (12U) +#define PMU_LDO_CON1_PWRMODE_LDOMIPI_ADJ_MASK (0x7U << PMU_LDO_CON1_PWRMODE_LDOMIPI_ADJ_SHIFT) /* 0x00007000 */ +/* LDO_CON2 */ +#define PMU_LDO_CON2_OFFSET (0x58U) +#define PMU_LDO_CON2_DSP_LDOCORE_SFT_SHIFT (0U) +#define PMU_LDO_CON2_DSP_LDOCORE_SFT_MASK (0x7U << PMU_LDO_CON2_DSP_LDOCORE_SFT_SHIFT) /* 0x00000007 */ +#define PMU_LDO_CON2_DSPAPM_LDOCORE_ADJ_SHIFT (4U) +#define PMU_LDO_CON2_DSPAPM_LDOCORE_ADJ_MASK (0x7U << PMU_LDO_CON2_DSPAPM_LDOCORE_ADJ_SHIFT) /* 0x00000070 */ +#define PMU_LDO_CON2_DSP_LDOMIPI_SFT_SHIFT (8U) +#define PMU_LDO_CON2_DSP_LDOMIPI_SFT_MASK (0x7U << PMU_LDO_CON2_DSP_LDOMIPI_SFT_SHIFT) /* 0x00000700 */ +#define PMU_LDO_CON2_DSPAPM_LDOMIPI_ADJ_SHIFT (12U) +#define PMU_LDO_CON2_DSPAPM_LDOMIPI_ADJ_MASK (0x7U << PMU_LDO_CON2_DSPAPM_LDOMIPI_ADJ_SHIFT) /* 0x00007000 */ +/* LDO_STAT */ +#define PMU_LDO_STAT_OFFSET (0x5CU) +#define PMU_LDO_STAT (0x0U) +#define PMU_LDO_STAT_LDO_CORE_ADJ_SHIFT (0U) +#define PMU_LDO_STAT_LDO_CORE_ADJ_MASK (0x7U << PMU_LDO_STAT_LDO_CORE_ADJ_SHIFT) /* 0x00000007 */ +#define PMU_LDO_STAT_LDO_MIPI_ADJ_SHIFT (4U) +#define PMU_LDO_STAT_LDO_MIPI_ADJ_MASK (0x7U << PMU_LDO_STAT_LDO_MIPI_ADJ_SHIFT) /* 0x00000070 */ +/* INT_CON */ +#define PMU_INT_CON_OFFSET (0x60U) +#define PMU_INT_CON_PMU_INT_EN_SHIFT (0U) +#define PMU_INT_CON_PMU_INT_EN_MASK (0x1U << PMU_INT_CON_PMU_INT_EN_SHIFT) /* 0x00000001 */ +#define PMU_INT_CON_PWRMODE_WAKEUP_INT_EN_SHIFT (1U) +#define PMU_INT_CON_PWRMODE_WAKEUP_INT_EN_MASK (0x1U << PMU_INT_CON_PWRMODE_WAKEUP_INT_EN_SHIFT) /* 0x00000002 */ +#define PMU_INT_CON_DSP_WAKEUP_INT_EN_SHIFT (2U) +#define PMU_INT_CON_DSP_WAKEUP_INT_EN_MASK (0x1U << PMU_INT_CON_DSP_WAKEUP_INT_EN_SHIFT) /* 0x00000004 */ +/* INT_ST */ +#define PMU_INT_ST_OFFSET (0x64U) +#define PMU_INT_ST_PWRMODE_WAKEUP_STATUS_SHIFT (0U) +#define PMU_INT_ST_PWRMODE_WAKEUP_STATUS_MASK (0x1U << PMU_INT_ST_PWRMODE_WAKEUP_STATUS_SHIFT) /* 0x00000001 */ +#define PMU_INT_ST_DSP_WAKEUP_STATUS_SHIFT (1U) +#define PMU_INT_ST_DSP_WAKEUP_STATUS_MASK (0x1U << PMU_INT_ST_DSP_WAKEUP_STATUS_SHIFT) /* 0x00000002 */ +#define PMU_INT_ST_PWRMODE_WAKEUP_GPIO_POS_STATUS_SHIFT (2U) +#define PMU_INT_ST_PWRMODE_WAKEUP_GPIO_POS_STATUS_MASK (0x1U << PMU_INT_ST_PWRMODE_WAKEUP_GPIO_POS_STATUS_SHIFT) /* 0x00000004 */ +#define PMU_INT_ST_PWRMODE_WAKEUP_GPIO_NEG_STATUS_SHIFT (3U) +#define PMU_INT_ST_PWRMODE_WAKEUP_GPIO_NEG_STATUS_MASK (0x1U << PMU_INT_ST_PWRMODE_WAKEUP_GPIO_NEG_STATUS_SHIFT) /* 0x00000008 */ +#define PMU_INT_ST_DSP_WAKEUP_GPIO_POS_STATUS_SHIFT (4U) +#define PMU_INT_ST_DSP_WAKEUP_GPIO_POS_STATUS_MASK (0x1U << PMU_INT_ST_DSP_WAKEUP_GPIO_POS_STATUS_SHIFT) /* 0x00000010 */ +#define PMU_INT_ST_DSP_WAKEUP_GPIO_NEG_STATUS_SHIFT (5U) +#define PMU_INT_ST_DSP_WAKEUP_GPIO_NEG_STATUS_MASK (0x1U << PMU_INT_ST_DSP_WAKEUP_GPIO_NEG_STATUS_SHIFT) /* 0x00000020 */ +/* PWRMODE_GPIO_POS_INT_CON */ +#define PMU_PWRMODE_GPIO_POS_INT_CON_OFFSET (0x68U) +#define PMU_PWRMODE_GPIO_POS_INT_CON_PWRMODE_GPIO0D_POS_INT_EN_SHIFT (0U) +#define PMU_PWRMODE_GPIO_POS_INT_CON_PWRMODE_GPIO0D_POS_INT_EN_MASK (0xFFU << PMU_PWRMODE_GPIO_POS_INT_CON_PWRMODE_GPIO0D_POS_INT_EN_SHIFT) /* 0x000000FF */ +#define PMU_PWRMODE_GPIO_POS_INT_CON_PWRMODE_GPIO1B_POS_INT_EN_SHIFT (8U) +#define PMU_PWRMODE_GPIO_POS_INT_CON_PWRMODE_GPIO1B_POS_INT_EN_MASK (0xFFU << PMU_PWRMODE_GPIO_POS_INT_CON_PWRMODE_GPIO1B_POS_INT_EN_SHIFT) /* 0x0000FF00 */ +/* PWRMODE_GPIO_NEG_INT_CON */ +#define PMU_PWRMODE_GPIO_NEG_INT_CON_OFFSET (0x6CU) +#define PMU_PWRMODE_GPIO_NEG_INT_CON_PWRMODE_GPIO0D_NEG_INT_EN_SHIFT (0U) +#define PMU_PWRMODE_GPIO_NEG_INT_CON_PWRMODE_GPIO0D_NEG_INT_EN_MASK (0xFFU << PMU_PWRMODE_GPIO_NEG_INT_CON_PWRMODE_GPIO0D_NEG_INT_EN_SHIFT) /* 0x000000FF */ +#define PMU_PWRMODE_GPIO_NEG_INT_CON_PWRMODE_GPIO1B_NEG_INT_EN_SHIFT (8U) +#define PMU_PWRMODE_GPIO_NEG_INT_CON_PWRMODE_GPIO1B_NEG_INT_EN_MASK (0xFFU << PMU_PWRMODE_GPIO_NEG_INT_CON_PWRMODE_GPIO1B_NEG_INT_EN_SHIFT) /* 0x0000FF00 */ +/* DSP_GPIO_POS_INT_CON */ +#define PMU_DSP_GPIO_POS_INT_CON_OFFSET (0x70U) +#define PMU_DSP_GPIO_POS_INT_CON_DSP_GPIO0D_POS_INT_EN_SHIFT (0U) +#define PMU_DSP_GPIO_POS_INT_CON_DSP_GPIO0D_POS_INT_EN_MASK (0xFFU << PMU_DSP_GPIO_POS_INT_CON_DSP_GPIO0D_POS_INT_EN_SHIFT) /* 0x000000FF */ +#define PMU_DSP_GPIO_POS_INT_CON_DSP_GPIO1B_POS_INT_EN_SHIFT (8U) +#define PMU_DSP_GPIO_POS_INT_CON_DSP_GPIO1B_POS_INT_EN_MASK (0xFFU << PMU_DSP_GPIO_POS_INT_CON_DSP_GPIO1B_POS_INT_EN_SHIFT) /* 0x0000FF00 */ +/* DSP_GPIO_NEG_INT_CON */ +#define PMU_DSP_GPIO_NEG_INT_CON_OFFSET (0x74U) +#define PMU_DSP_GPIO_NEG_INT_CON_DSP_GPIO0D_NEG_INT_EN_SHIFT (0U) +#define PMU_DSP_GPIO_NEG_INT_CON_DSP_GPIO0D_NEG_INT_EN_MASK (0xFFU << PMU_DSP_GPIO_NEG_INT_CON_DSP_GPIO0D_NEG_INT_EN_SHIFT) /* 0x000000FF */ +#define PMU_DSP_GPIO_NEG_INT_CON_DSP_GPIO1B_NEG_INT_EN_SHIFT (8U) +#define PMU_DSP_GPIO_NEG_INT_CON_DSP_GPIO1B_NEG_INT_EN_MASK (0xFFU << PMU_DSP_GPIO_NEG_INT_CON_DSP_GPIO1B_NEG_INT_EN_SHIFT) /* 0x0000FF00 */ +/* PWRMODE_GPIO_POS_INT_ST */ +#define PMU_PWRMODE_GPIO_POS_INT_ST_OFFSET (0x78U) +#define PMU_PWRMODE_GPIO_POS_INT_ST_PWRMODE_GPIO0D_POS_INT_STATUS_SHIFT (0U) +#define PMU_PWRMODE_GPIO_POS_INT_ST_PWRMODE_GPIO0D_POS_INT_STATUS_MASK (0xFFU << PMU_PWRMODE_GPIO_POS_INT_ST_PWRMODE_GPIO0D_POS_INT_STATUS_SHIFT) /* 0x000000FF */ +#define PMU_PWRMODE_GPIO_POS_INT_ST_PWRMODE_GPIO1B_POS_INT_STATUS_SHIFT (8U) +#define PMU_PWRMODE_GPIO_POS_INT_ST_PWRMODE_GPIO1B_POS_INT_STATUS_MASK (0xFFU << PMU_PWRMODE_GPIO_POS_INT_ST_PWRMODE_GPIO1B_POS_INT_STATUS_SHIFT) /* 0x0000FF00 */ +/* PWRMODE_GPIO_NEG_INT_ST */ +#define PMU_PWRMODE_GPIO_NEG_INT_ST_OFFSET (0x7CU) +#define PMU_PWRMODE_GPIO_NEG_INT_ST_PWRMODE_GPIO0D_NEG_INT_STATUS_SHIFT (0U) +#define PMU_PWRMODE_GPIO_NEG_INT_ST_PWRMODE_GPIO0D_NEG_INT_STATUS_MASK (0xFFU << PMU_PWRMODE_GPIO_NEG_INT_ST_PWRMODE_GPIO0D_NEG_INT_STATUS_SHIFT) /* 0x000000FF */ +#define PMU_PWRMODE_GPIO_NEG_INT_ST_PWRMODE_GPIO1B_NEG_INT_STATUS_SHIFT (8U) +#define PMU_PWRMODE_GPIO_NEG_INT_ST_PWRMODE_GPIO1B_NEG_INT_STATUS_MASK (0xFFU << PMU_PWRMODE_GPIO_NEG_INT_ST_PWRMODE_GPIO1B_NEG_INT_STATUS_SHIFT) /* 0x0000FF00 */ +/* DSP_GPIO_POS_INT_ST */ +#define PMU_DSP_GPIO_POS_INT_ST_OFFSET (0x80U) +#define PMU_DSP_GPIO_POS_INT_ST_DSP_GPIO0D_POS_INT_STATUS_SHIFT (0U) +#define PMU_DSP_GPIO_POS_INT_ST_DSP_GPIO0D_POS_INT_STATUS_MASK (0xFFU << PMU_DSP_GPIO_POS_INT_ST_DSP_GPIO0D_POS_INT_STATUS_SHIFT) /* 0x000000FF */ +#define PMU_DSP_GPIO_POS_INT_ST_DSP_GPIO1B_POS_INT_STATUS_SHIFT (8U) +#define PMU_DSP_GPIO_POS_INT_ST_DSP_GPIO1B_POS_INT_STATUS_MASK (0xFFU << PMU_DSP_GPIO_POS_INT_ST_DSP_GPIO1B_POS_INT_STATUS_SHIFT) /* 0x0000FF00 */ +/* DSP_GPIO_NEG_INT_ST */ +#define PMU_DSP_GPIO_NEG_INT_ST_OFFSET (0x84U) +#define PMU_DSP_GPIO_NEG_INT_ST_DSP_GPIO0D_NEG_INT_STATUS_SHIFT (0U) +#define PMU_DSP_GPIO_NEG_INT_ST_DSP_GPIO0D_NEG_INT_STATUS_MASK (0xFFU << PMU_DSP_GPIO_NEG_INT_ST_DSP_GPIO0D_NEG_INT_STATUS_SHIFT) /* 0x000000FF */ +#define PMU_DSP_GPIO_NEG_INT_ST_DSP_GPIO1B_NEG_INT_STATUS_SHIFT (8U) +#define PMU_DSP_GPIO_NEG_INT_ST_DSP_GPIO1B_NEG_INT_STATUS_MASK (0xFFU << PMU_DSP_GPIO_NEG_INT_ST_DSP_GPIO1B_NEG_INT_STATUS_SHIFT) /* 0x0000FF00 */ +/* PWRDN_INTEN */ +#define PMU_PWRDN_INTEN_OFFSET (0x88U) +#define PMU_PWRDN_INTEN_PD_DSP_PWR_SWITCH_INT_EN_SHIFT (0U) +#define PMU_PWRDN_INTEN_PD_DSP_PWR_SWITCH_INT_EN_MASK (0x1U << PMU_PWRDN_INTEN_PD_DSP_PWR_SWITCH_INT_EN_SHIFT) /* 0x00000001 */ +#define PMU_PWRDN_INTEN_PD_LOGIC_PWR_SWITCH_INT_EN_SHIFT (1U) +#define PMU_PWRDN_INTEN_PD_LOGIC_PWR_SWITCH_INT_EN_MASK (0x1U << PMU_PWRDN_INTEN_PD_LOGIC_PWR_SWITCH_INT_EN_SHIFT) /* 0x00000002 */ +#define PMU_PWRDN_INTEN_PD_SHRM_PWR_SWITCH_INT_EN_SHIFT (2U) +#define PMU_PWRDN_INTEN_PD_SHRM_PWR_SWITCH_INT_EN_MASK (0x1U << PMU_PWRDN_INTEN_PD_SHRM_PWR_SWITCH_INT_EN_SHIFT) /* 0x00000004 */ +#define PMU_PWRDN_INTEN_PD_AUDIO_PWR_SWITCH_INT_EN_SHIFT (3U) +#define PMU_PWRDN_INTEN_PD_AUDIO_PWR_SWITCH_INT_EN_MASK (0x1U << PMU_PWRDN_INTEN_PD_AUDIO_PWR_SWITCH_INT_EN_SHIFT) /* 0x00000008 */ +/* PWRDN_INT_STATUS */ +#define PMU_PWRDN_INT_STATUS_OFFSET (0x8CU) +#define PMU_PWRDN_INT_STATUS_PD_DSP_PD_SWT_SHIFT (0U) +#define PMU_PWRDN_INT_STATUS_PD_DSP_PD_SWT_MASK (0x1U << PMU_PWRDN_INT_STATUS_PD_DSP_PD_SWT_SHIFT) /* 0x00000001 */ +#define PMU_PWRDN_INT_STATUS_PD_LOGIC_PD_SWT_SHIFT (1U) +#define PMU_PWRDN_INT_STATUS_PD_LOGIC_PD_SWT_MASK (0x1U << PMU_PWRDN_INT_STATUS_PD_LOGIC_PD_SWT_SHIFT) /* 0x00000002 */ +#define PMU_PWRDN_INT_STATUS_PD_SHRM_PD_SWT_SHIFT (2U) +#define PMU_PWRDN_INT_STATUS_PD_SHRM_PD_SWT_MASK (0x1U << PMU_PWRDN_INT_STATUS_PD_SHRM_PD_SWT_SHIFT) /* 0x00000004 */ +#define PMU_PWRDN_INT_STATUS_PD_AUDIO_PD_SWT_SHIFT (3U) +#define PMU_PWRDN_INT_STATUS_PD_AUDIO_PD_SWT_MASK (0x1U << PMU_PWRDN_INT_STATUS_PD_AUDIO_PD_SWT_SHIFT) /* 0x00000008 */ +/* WAKEUP_STATUS */ +#define PMU_WAKEUP_STATUS_OFFSET (0x90U) +#define PMU_WAKEUP_STATUS_WAKEUP_PWRMODE_INT_STATUS_SHIFT (0U) +#define PMU_WAKEUP_STATUS_WAKEUP_PWRMODE_INT_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_WAKEUP_PWRMODE_INT_STATUS_SHIFT) /* 0x00000001 */ +#define PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_GPIO_INT_STATUS_SHIFT (1U) +#define PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_GPIO_INT_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_GPIO_INT_STATUS_SHIFT) /* 0x00000002 */ +#define PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_TIMEOUT_STATUS_SHIFT (2U) +#define PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_TIMEOUT_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_TIMEOUT_STATUS_SHIFT) /* 0x00000004 */ +#define PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_DSP_SFT_STATUS_SHIFT (3U) +#define PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_DSP_SFT_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_DSP_SFT_STATUS_SHIFT) /* 0x00000008 */ +#define PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_TIMER_STATUS_SHIFT (4U) +#define PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_TIMER_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_TIMER_STATUS_SHIFT) /* 0x00000010 */ +#define PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_VAD_STATUS_SHIFT (5U) +#define PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_VAD_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_VAD_STATUS_SHIFT) /* 0x00000020 */ +#define PMU_WAKEUP_STATUS_WAKEUP_DSP_INT_STATUS_SHIFT (6U) +#define PMU_WAKEUP_STATUS_WAKEUP_DSP_INT_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_WAKEUP_DSP_INT_STATUS_SHIFT) /* 0x00000040 */ +#define PMU_WAKEUP_STATUS_DSP_WAKEUP_GPIO_INT_STATUS_SHIFT (7U) +#define PMU_WAKEUP_STATUS_DSP_WAKEUP_GPIO_INT_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_DSP_WAKEUP_GPIO_INT_STATUS_SHIFT) /* 0x00000080 */ +#define PMU_WAKEUP_STATUS_DSP_WAKEUP_TIMEOUT_STATUS_SHIFT (8U) +#define PMU_WAKEUP_STATUS_DSP_WAKEUP_TIMEOUT_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_DSP_WAKEUP_TIMEOUT_STATUS_SHIFT) /* 0x00000100 */ +#define PMU_WAKEUP_STATUS_DSP_WAKEUP_SFT_STATUS_SHIFT (9U) +#define PMU_WAKEUP_STATUS_DSP_WAKEUP_SFT_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_DSP_WAKEUP_SFT_STATUS_SHIFT) /* 0x00000200 */ +#define PMU_WAKEUP_STATUS_DSP_WAKEUP_TIMER_STATUS_SHIFT (10U) +#define PMU_WAKEUP_STATUS_DSP_WAKEUP_TIMER_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_DSP_WAKEUP_TIMER_STATUS_SHIFT) /* 0x00000400 */ +#define PMU_WAKEUP_STATUS_DSP_WAKEUP_VAD_STATUS_SHIFT (11U) +#define PMU_WAKEUP_STATUS_DSP_WAKEUP_VAD_STATUS_MASK (0x1U << PMU_WAKEUP_STATUS_DSP_WAKEUP_VAD_STATUS_SHIFT) /* 0x00000800 */ +/* BUS_CLR */ +#define PMU_BUS_CLR_OFFSET (0xA0U) +#define PMU_BUS_CLR_CLR_DSP_SHIFT (0U) +#define PMU_BUS_CLR_CLR_DSP_MASK (0x1U << PMU_BUS_CLR_CLR_DSP_SHIFT) /* 0x00000001 */ +#define PMU_BUS_CLR_CLR_LOGIC_SHIFT (1U) +#define PMU_BUS_CLR_CLR_LOGIC_MASK (0x1U << PMU_BUS_CLR_CLR_LOGIC_SHIFT) /* 0x00000002 */ +#define PMU_BUS_CLR_CLR_SHRM_SHIFT (2U) +#define PMU_BUS_CLR_CLR_SHRM_MASK (0x1U << PMU_BUS_CLR_CLR_SHRM_SHIFT) /* 0x00000004 */ +#define PMU_BUS_CLR_CLR_AUDIO_SHIFT (3U) +#define PMU_BUS_CLR_CLR_AUDIO_MASK (0x1U << PMU_BUS_CLR_CLR_AUDIO_SHIFT) /* 0x00000008 */ +/* BUS_IDLE_REQ */ +#define PMU_BUS_IDLE_REQ_OFFSET (0xA4U) +#define PMU_BUS_IDLE_REQ_IDLE_REQ_DSP_SHIFT (0U) +#define PMU_BUS_IDLE_REQ_IDLE_REQ_DSP_MASK (0x1U << PMU_BUS_IDLE_REQ_IDLE_REQ_DSP_SHIFT) /* 0x00000001 */ +#define PMU_BUS_IDLE_REQ_IDLE_REQ_LOGIC_SHIFT (1U) +#define PMU_BUS_IDLE_REQ_IDLE_REQ_LOGIC_MASK (0x1U << PMU_BUS_IDLE_REQ_IDLE_REQ_LOGIC_SHIFT) /* 0x00000002 */ +#define PMU_BUS_IDLE_REQ_IDLE_REQ_SHRM_SHIFT (2U) +#define PMU_BUS_IDLE_REQ_IDLE_REQ_SHRM_MASK (0x1U << PMU_BUS_IDLE_REQ_IDLE_REQ_SHRM_SHIFT) /* 0x00000004 */ +#define PMU_BUS_IDLE_REQ_IDLE_REQ_AUDIO_SHIFT (3U) +#define PMU_BUS_IDLE_REQ_IDLE_REQ_AUDIO_MASK (0x1U << PMU_BUS_IDLE_REQ_IDLE_REQ_AUDIO_SHIFT) /* 0x00000008 */ +/* BUS_IDLE_ST */ +#define PMU_BUS_IDLE_ST_OFFSET (0xA8U) +#define PMU_BUS_IDLE_ST (0x0U) +#define PMU_BUS_IDLE_ST_IDLE_DSP_SHIFT (0U) +#define PMU_BUS_IDLE_ST_IDLE_DSP_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_DSP_SHIFT) /* 0x00000001 */ +#define PMU_BUS_IDLE_ST_IDLE_LOGIC_SHIFT (1U) +#define PMU_BUS_IDLE_ST_IDLE_LOGIC_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_LOGIC_SHIFT) /* 0x00000002 */ +#define PMU_BUS_IDLE_ST_IDLE_SHRM_SHIFT (2U) +#define PMU_BUS_IDLE_ST_IDLE_SHRM_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_SHRM_SHIFT) /* 0x00000004 */ +#define PMU_BUS_IDLE_ST_IDLE_AUDIO_SHIFT (3U) +#define PMU_BUS_IDLE_ST_IDLE_AUDIO_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_AUDIO_SHIFT) /* 0x00000008 */ +/* BUS_IDLE_ACK */ +#define PMU_BUS_IDLE_ACK_OFFSET (0xACU) +#define PMU_BUS_IDLE_ACK (0x0U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_DSP_SHIFT (0U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_DSP_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_DSP_SHIFT) /* 0x00000001 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_LOGIC_SHIFT (1U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_LOGIC_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_LOGIC_SHIFT) /* 0x00000002 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_SHRM_SHIFT (2U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_SHRM_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_SHRM_SHIFT) /* 0x00000004 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_AUDIO_SHIFT (3U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_AUDIO_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_AUDIO_SHIFT) /* 0x00000008 */ +/* POWER_ST */ +#define PMU_POWER_ST_OFFSET (0xB0U) +#define PMU_POWER_ST (0x0U) +#define PMU_POWER_ST_PWRMODE_POWER_STATE_SHIFT (0U) +#define PMU_POWER_ST_PWRMODE_POWER_STATE_MASK (0x1FU << PMU_POWER_ST_PWRMODE_POWER_STATE_SHIFT) /* 0x0000001F */ +#define PMU_POWER_ST_DSP_POWER_STATE_SHIFT (5U) +#define PMU_POWER_ST_DSP_POWER_STATE_MASK (0xFU << PMU_POWER_ST_DSP_POWER_STATE_SHIFT) /* 0x000001E0 */ +/* CORE_PWR_ST */ +#define PMU_CORE_PWR_ST_OFFSET (0xB4U) +#define PMU_CORE_PWR_ST (0x0U) +#define PMU_CORE_PWR_ST_STANDBYWFI_CM4_SHIFT (0U) +#define PMU_CORE_PWR_ST_STANDBYWFI_CM4_MASK (0x1U << PMU_CORE_PWR_ST_STANDBYWFI_CM4_SHIFT) /* 0x00000001 */ +#define PMU_CORE_PWR_ST_STANDBYWFI_DSP_SHIFT (1U) +#define PMU_CORE_PWR_ST_STANDBYWFI_DSP_MASK (0x1U << PMU_CORE_PWR_ST_STANDBYWFI_DSP_SHIFT) /* 0x00000002 */ +/* OSC_CNT */ +#define PMU_OSC_CNT_OFFSET (0xB8U) +#define PMU_OSC_CNT_PMU_OSC_CNT_SHIFT (0U) +#define PMU_OSC_CNT_PMU_OSC_CNT_MASK (0xFFFFFU << PMU_OSC_CNT_PMU_OSC_CNT_SHIFT) /* 0x000FFFFF */ +/* PLLLOCK_CNT */ +#define PMU_PLLLOCK_CNT_OFFSET (0xBCU) +#define PMU_PLLLOCK_CNT_PMU_PLLLOCK_CNT_SHIFT (0U) +#define PMU_PLLLOCK_CNT_PMU_PLLLOCK_CNT_MASK (0xFFFFFU << PMU_PLLLOCK_CNT_PMU_PLLLOCK_CNT_SHIFT) /* 0x000FFFFF */ +/* PWRMODE_TIMEOUT_CNT */ +#define PMU_PWRMODE_TIMEOUT_CNT_OFFSET (0xC0U) +#define PMU_PWRMODE_TIMEOUT_CNT_PWRMODE_TIMEOUT_COUNT_SHIFT (0U) +#define PMU_PWRMODE_TIMEOUT_CNT_PWRMODE_TIMEOUT_COUNT_MASK (0xFFFFFFFFU << PMU_PWRMODE_TIMEOUT_CNT_PWRMODE_TIMEOUT_COUNT_SHIFT) /* 0xFFFFFFFF */ +/* NOC_AUTO_ENA */ +#define PMU_NOC_AUTO_ENA_OFFSET (0xC4U) +#define PMU_NOC_AUTO_ENA_DSP_GATING_DISABLE_SHIFT (0U) +#define PMU_NOC_AUTO_ENA_DSP_GATING_DISABLE_MASK (0x1U << PMU_NOC_AUTO_ENA_DSP_GATING_DISABLE_SHIFT) /* 0x00000001 */ +#define PMU_NOC_AUTO_ENA_LOGIC_GATING_DISABLE_SHIFT (1U) +#define PMU_NOC_AUTO_ENA_LOGIC_GATING_DISABLE_MASK (0x1U << PMU_NOC_AUTO_ENA_LOGIC_GATING_DISABLE_SHIFT) /* 0x00000002 */ +#define PMU_NOC_AUTO_ENA_SHRM_GATING_DISABLE_SHIFT (2U) +#define PMU_NOC_AUTO_ENA_SHRM_GATING_DISABLE_MASK (0x1U << PMU_NOC_AUTO_ENA_SHRM_GATING_DISABLE_SHIFT) /* 0x00000004 */ +#define PMU_NOC_AUTO_ENA_AUDIO_GATING_DISABLE_SHIFT (3U) +#define PMU_NOC_AUTO_ENA_AUDIO_GATING_DISABLE_MASK (0x1U << PMU_NOC_AUTO_ENA_AUDIO_GATING_DISABLE_SHIFT) /* 0x00000008 */ +/* DSPAPM_CON */ +#define PMU_DSPAPM_CON_OFFSET (0xD0U) +#define PMU_DSPAPM_CON_PD_DSP_WFI_PWRDN_EN_SHIFT (0U) +#define PMU_DSPAPM_CON_PD_DSP_WFI_PWRDN_EN_MASK (0x1U << PMU_DSPAPM_CON_PD_DSP_WFI_PWRDN_EN_SHIFT) /* 0x00000001 */ +#define PMU_DSPAPM_CON_PD_DSP_IDLE_EN_SHIFT (1U) +#define PMU_DSPAPM_CON_PD_DSP_IDLE_EN_MASK (0x1U << PMU_DSPAPM_CON_PD_DSP_IDLE_EN_SHIFT) /* 0x00000002 */ +#define PMU_DSPAPM_CON_PD_DSP_LDO_ADJ_EN_SHIFT (2U) +#define PMU_DSPAPM_CON_PD_DSP_LDO_ADJ_EN_MASK (0x1U << PMU_DSPAPM_CON_PD_DSP_LDO_ADJ_EN_SHIFT) /* 0x00000004 */ +#define PMU_DSPAPM_CON_GLOBAL_INT_DISABLE_DSP_CFG_SHIFT (3U) +#define PMU_DSPAPM_CON_GLOBAL_INT_DISABLE_DSP_CFG_MASK (0x1U << PMU_DSPAPM_CON_GLOBAL_INT_DISABLE_DSP_CFG_SHIFT) /* 0x00000008 */ +#define PMU_DSPAPM_CON_PD_DSP_INT_WAKEUP_EN_SHIFT (4U) +#define PMU_DSPAPM_CON_PD_DSP_INT_WAKEUP_EN_MASK (0x1U << PMU_DSPAPM_CON_PD_DSP_INT_WAKEUP_EN_SHIFT) /* 0x00000010 */ +#define PMU_DSPAPM_CON_PD_DSP_GPIO_INT_WAKEUP_EN_SHIFT (5U) +#define PMU_DSPAPM_CON_PD_DSP_GPIO_INT_WAKEUP_EN_MASK (0x1U << PMU_DSPAPM_CON_PD_DSP_GPIO_INT_WAKEUP_EN_SHIFT) /* 0x00000020 */ +#define PMU_DSPAPM_CON_PD_DSP_TIMEOUT_WAKEUP_EN_SHIFT (6U) +#define PMU_DSPAPM_CON_PD_DSP_TIMEOUT_WAKEUP_EN_MASK (0x1U << PMU_DSPAPM_CON_PD_DSP_TIMEOUT_WAKEUP_EN_SHIFT) /* 0x00000040 */ +#define PMU_DSPAPM_CON_PD_DSP_TIMER_WAKEUP_EN_SHIFT (7U) +#define PMU_DSPAPM_CON_PD_DSP_TIMER_WAKEUP_EN_MASK (0x1U << PMU_DSPAPM_CON_PD_DSP_TIMER_WAKEUP_EN_SHIFT) /* 0x00000080 */ +#define PMU_DSPAPM_CON_PD_DSP_VAD_WAKEUP_EN_SHIFT (8U) +#define PMU_DSPAPM_CON_PD_DSP_VAD_WAKEUP_EN_MASK (0x1U << PMU_DSPAPM_CON_PD_DSP_VAD_WAKEUP_EN_SHIFT) /* 0x00000100 */ +#define PMU_DSPAPM_CON_PD_DSP_SFT_WAKEUP_SHIFT (9U) +#define PMU_DSPAPM_CON_PD_DSP_SFT_WAKEUP_MASK (0x1U << PMU_DSPAPM_CON_PD_DSP_SFT_WAKEUP_SHIFT) /* 0x00000200 */ +#define PMU_DSPAPM_CON_PD_DSP_TCM_RETPD_EN_SHIFT (10U) +#define PMU_DSPAPM_CON_PD_DSP_TCM_RETPD_EN_MASK (0x1U << PMU_DSPAPM_CON_PD_DSP_TCM_RETPD_EN_SHIFT) /* 0x00000400 */ +/* DSP_LDO_ADJ_CNT */ +#define PMU_DSP_LDO_ADJ_CNT_OFFSET (0xD8U) +#define PMU_DSP_LDO_ADJ_CNT_DSP_LDO_ADJ_CNT_SHIFT (0U) +#define PMU_DSP_LDO_ADJ_CNT_DSP_LDO_ADJ_CNT_MASK (0xFFFFFU << PMU_DSP_LDO_ADJ_CNT_DSP_LDO_ADJ_CNT_SHIFT) /* 0x000FFFFF */ +/* DSP_TIMEOUT_CNT */ +#define PMU_DSP_TIMEOUT_CNT_OFFSET (0xDCU) +#define PMU_DSP_TIMEOUT_CNT_DSP_TIMEOUT_COUNT_SHIFT (0U) +#define PMU_DSP_TIMEOUT_CNT_DSP_TIMEOUT_COUNT_MASK (0xFFFFFFFFU << PMU_DSP_TIMEOUT_CNT_DSP_TIMEOUT_COUNT_SHIFT) /* 0xFFFFFFFF */ +/* PWRMODE_LDO_ADJ_CNT */ +#define PMU_PWRMODE_LDO_ADJ_CNT_OFFSET (0xE0U) +#define PMU_PWRMODE_LDO_ADJ_CNT_PWRMODE_LDO_ADJ_CNT_SHIFT (0U) +#define PMU_PWRMODE_LDO_ADJ_CNT_PWRMODE_LDO_ADJ_CNT_MASK (0xFFFFFU << PMU_PWRMODE_LDO_ADJ_CNT_PWRMODE_LDO_ADJ_CNT_SHIFT) /* 0x000FFFFF */ +/* SHRM_CON0 */ +#define PMU_SHRM_CON0_OFFSET (0xE4U) +#define PMU_SHRM_CON0_SHAREMEM_PWRDWN_EN_SFT_SHIFT (0U) +#define PMU_SHRM_CON0_SHAREMEM_PWRDWN_EN_SFT_MASK (0xFU << PMU_SHRM_CON0_SHAREMEM_PWRDWN_EN_SFT_SHIFT) /* 0x0000000F */ +#define PMU_SHRM_CON0_SHAREMEM_RET1N_SFT_SHIFT (4U) +#define PMU_SHRM_CON0_SHAREMEM_RET1N_SFT_MASK (0xFU << PMU_SHRM_CON0_SHAREMEM_RET1N_SFT_SHIFT) /* 0x000000F0 */ +#define PMU_SHRM_CON0_SHAREMEM_RET2N_SFT_SHIFT (8U) +#define PMU_SHRM_CON0_SHAREMEM_RET2N_SFT_MASK (0xFU << PMU_SHRM_CON0_SHAREMEM_RET2N_SFT_SHIFT) /* 0x00000F00 */ +/* DSPTCM_CON0 */ +#define PMU_DSPTCM_CON0_OFFSET (0xE8U) +#define PMU_DSPTCM_CON0_DSPDTCM_PGEN_SFT_SHIFT (0U) +#define PMU_DSPTCM_CON0_DSPDTCM_PGEN_SFT_MASK (0xFFU << PMU_DSPTCM_CON0_DSPDTCM_PGEN_SFT_SHIFT) /* 0x000000FF */ +#define PMU_DSPTCM_CON0_DSPDTCM_RET1N_SFT_SHIFT (8U) +#define PMU_DSPTCM_CON0_DSPDTCM_RET1N_SFT_MASK (0xFFU << PMU_DSPTCM_CON0_DSPDTCM_RET1N_SFT_SHIFT) /* 0x0000FF00 */ +/* DSPTCM_CON1 */ +#define PMU_DSPTCM_CON1_OFFSET (0xECU) +#define PMU_DSPTCM_CON1_DSPDTCM_RET2N_SFT_SHIFT (0U) +#define PMU_DSPTCM_CON1_DSPDTCM_RET2N_SFT_MASK (0xFFU << PMU_DSPTCM_CON1_DSPDTCM_RET2N_SFT_SHIFT) /* 0x000000FF */ +#define PMU_DSPTCM_CON1_DSPITCM_PGEN_SFT_SHIFT (8U) +#define PMU_DSPTCM_CON1_DSPITCM_PGEN_SFT_MASK (0x1U << PMU_DSPTCM_CON1_DSPITCM_PGEN_SFT_SHIFT) /* 0x00000100 */ +#define PMU_DSPTCM_CON1_DSPITCM_RET1N_SFT_SHIFT (9U) +#define PMU_DSPTCM_CON1_DSPITCM_RET1N_SFT_MASK (0x1U << PMU_DSPTCM_CON1_DSPITCM_RET1N_SFT_SHIFT) /* 0x00000200 */ +#define PMU_DSPTCM_CON1_DSPITCM_RET2N_SFT_SHIFT (10U) +#define PMU_DSPTCM_CON1_DSPITCM_RET2N_SFT_MASK (0x1U << PMU_DSPTCM_CON1_DSPITCM_RET2N_SFT_SHIFT) /* 0x00000400 */ +/* SYS_REG0 */ +#define PMU_SYS_REG0_OFFSET (0xF0U) +#define PMU_SYS_REG0_PMU_SYS_REG0_SHIFT (0U) +#define PMU_SYS_REG0_PMU_SYS_REG0_MASK (0xFFFFFFFFU << PMU_SYS_REG0_PMU_SYS_REG0_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG1 */ +#define PMU_SYS_REG1_OFFSET (0xF4U) +#define PMU_SYS_REG1_PMU_SYS_REG1_SHIFT (0U) +#define PMU_SYS_REG1_PMU_SYS_REG1_MASK (0xFFFFFFFFU << PMU_SYS_REG1_PMU_SYS_REG1_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG2 */ +#define PMU_SYS_REG2_OFFSET (0xF8U) +#define PMU_SYS_REG2_PMU_SYS_REG2_SHIFT (0U) +#define PMU_SYS_REG2_PMU_SYS_REG2_MASK (0xFFFFFFFFU << PMU_SYS_REG2_PMU_SYS_REG2_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG3 */ +#define PMU_SYS_REG3_OFFSET (0xFCU) +#define PMU_SYS_REG3_PMU_SYS_REG3_SHIFT (0U) +#define PMU_SYS_REG3_PMU_SYS_REG3_MASK (0xFFFFFFFFU << PMU_SYS_REG3_PMU_SYS_REG3_SHIFT) /* 0xFFFFFFFF */ +/* SHRM_CON1 */ +#define PMU_SHRM_CON1_OFFSET (0x100U) +#define PMU_SHRM_CON1_PWRMODE_SHRM_PWRDWN_EN_SHIFT (0U) +#define PMU_SHRM_CON1_PWRMODE_SHRM_PWRDWN_EN_MASK (0xFU << PMU_SHRM_CON1_PWRMODE_SHRM_PWRDWN_EN_SHIFT) /* 0x0000000F */ +#define PMU_SHRM_CON1_PWRMODE_SHRM_RET1N_SHIFT (4U) +#define PMU_SHRM_CON1_PWRMODE_SHRM_RET1N_MASK (0xFU << PMU_SHRM_CON1_PWRMODE_SHRM_RET1N_SHIFT) /* 0x000000F0 */ +#define PMU_SHRM_CON1_PWRMODE_SHRM_RET2N_SHIFT (8U) +#define PMU_SHRM_CON1_PWRMODE_SHRM_RET2N_MASK (0xFU << PMU_SHRM_CON1_PWRMODE_SHRM_RET2N_SHIFT) /* 0x00000F00 */ +/* DSPTCM_CON2 */ +#define PMU_DSPTCM_CON2_OFFSET (0x104U) +#define PMU_DSPTCM_CON2_DSPAPM_DTCM_PGEN_SHIFT (0U) +#define PMU_DSPTCM_CON2_DSPAPM_DTCM_PGEN_MASK (0xFFU << PMU_DSPTCM_CON2_DSPAPM_DTCM_PGEN_SHIFT) /* 0x000000FF */ +#define PMU_DSPTCM_CON2_DSPAPM_DTCM_RET1N_SHIFT (8U) +#define PMU_DSPTCM_CON2_DSPAPM_DTCM_RET1N_MASK (0xFFU << PMU_DSPTCM_CON2_DSPAPM_DTCM_RET1N_SHIFT) /* 0x0000FF00 */ +/* DSPTCM_CON3 */ +#define PMU_DSPTCM_CON3_OFFSET (0x108U) +#define PMU_DSPTCM_CON3_DSPAPM_DTCM_RET2N_SHIFT (0U) +#define PMU_DSPTCM_CON3_DSPAPM_DTCM_RET2N_MASK (0xFFU << PMU_DSPTCM_CON3_DSPAPM_DTCM_RET2N_SHIFT) /* 0x000000FF */ +#define PMU_DSPTCM_CON3_DSPAPM_ITCM_PGEN_SHIFT (8U) +#define PMU_DSPTCM_CON3_DSPAPM_ITCM_PGEN_MASK (0x1U << PMU_DSPTCM_CON3_DSPAPM_ITCM_PGEN_SHIFT) /* 0x00000100 */ +#define PMU_DSPTCM_CON3_DSPAPM_ITCM_RET1N_SHIFT (9U) +#define PMU_DSPTCM_CON3_DSPAPM_ITCM_RET1N_MASK (0x1U << PMU_DSPTCM_CON3_DSPAPM_ITCM_RET1N_SHIFT) /* 0x00000200 */ +#define PMU_DSPTCM_CON3_DSPAPM_ITCM_RET2N_SHIFT (10U) +#define PMU_DSPTCM_CON3_DSPAPM_ITCM_RET2N_MASK (0x1U << PMU_DSPTCM_CON3_DSPAPM_ITCM_RET2N_SHIFT) /* 0x00000400 */ +/******************************************DMA*******************************************/ +/* DSR */ +#define DMA_DSR_OFFSET (0x0U) +#define DMA_DSR (0x0U) +#define DMA_DSR_FIELD0000_SHIFT (0U) +#define DMA_DSR_FIELD0000_MASK (0xFU << DMA_DSR_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_DSR_FIELD0002_SHIFT (4U) +#define DMA_DSR_FIELD0002_MASK (0x1FU << DMA_DSR_FIELD0002_SHIFT) /* 0x000001F0 */ +#define DMA_DSR_FIELD0001_SHIFT (9U) +#define DMA_DSR_FIELD0001_MASK (0x1U << DMA_DSR_FIELD0001_SHIFT) /* 0x00000200 */ +/* DPC */ +#define DMA_DPC_OFFSET (0x4U) +#define DMA_DPC (0x0U) +#define DMA_DPC_FIELD0000_SHIFT (0U) +#define DMA_DPC_FIELD0000_MASK (0xFFFFFFFFU << DMA_DPC_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* INTEN */ +#define DMA_INTEN_OFFSET (0x20U) +#define DMA_INTEN_FIELD0000_SHIFT (0U) +#define DMA_INTEN_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTEN_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* EVENT_RIS */ +#define DMA_EVENT_RIS_OFFSET (0x24U) +#define DMA_EVENT_RIS (0x0U) +#define DMA_EVENT_RIS_FIELD0000_SHIFT (0U) +#define DMA_EVENT_RIS_FIELD0000_MASK (0xFFFFFFFFU << DMA_EVENT_RIS_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* INTMIS */ +#define DMA_INTMIS_OFFSET (0x28U) +#define DMA_INTMIS (0x0U) +#define DMA_INTMIS_FIELD0000_SHIFT (0U) +#define DMA_INTMIS_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTMIS_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* INTCLR */ +#define DMA_INTCLR_OFFSET (0x2CU) +#define DMA_INTCLR_FIELD0000_SHIFT (0U) +#define DMA_INTCLR_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTCLR_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* FSRD */ +#define DMA_FSRD_OFFSET (0x30U) +#define DMA_FSRD (0x0U) +#define DMA_FSRD_FIELD0000_SHIFT (0U) +#define DMA_FSRD_FIELD0000_MASK (0xFFFFFFFFU << DMA_FSRD_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* FSRC */ +#define DMA_FSRC_OFFSET (0x34U) +#define DMA_FSRC (0x0U) +#define DMA_FSRC_FIELD0000_SHIFT (0U) +#define DMA_FSRC_FIELD0000_MASK (0xFFFFFFFFU << DMA_FSRC_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* FTRD */ +#define DMA_FTRD_OFFSET (0x38U) +#define DMA_FTRD_FIELD0000_SHIFT (0U) +#define DMA_FTRD_FIELD0000_MASK (0x1U << DMA_FTRD_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTRD_FIELD0005_SHIFT (1U) +#define DMA_FTRD_FIELD0005_MASK (0x1U << DMA_FTRD_FIELD0005_SHIFT) /* 0x00000002 */ +#define DMA_FTRD_FIELD0004_SHIFT (4U) +#define DMA_FTRD_FIELD0004_MASK (0x1U << DMA_FTRD_FIELD0004_SHIFT) /* 0x00000010 */ +#define DMA_FTRD_FIELD0003_SHIFT (5U) +#define DMA_FTRD_FIELD0003_MASK (0x1U << DMA_FTRD_FIELD0003_SHIFT) /* 0x00000020 */ +#define DMA_FTRD_FIELD0002_SHIFT (16U) +#define DMA_FTRD_FIELD0002_MASK (0x1U << DMA_FTRD_FIELD0002_SHIFT) /* 0x00010000 */ +#define DMA_FTRD_FIELD0001_SHIFT (30U) +#define DMA_FTRD_FIELD0001_MASK (0x1U << DMA_FTRD_FIELD0001_SHIFT) /* 0x40000000 */ +/* FTR0 */ +#define DMA_FTR0_OFFSET (0x40U) +#define DMA_FTR0 (0x0U) +#define DMA_FTR0_FIELD0000_SHIFT (0U) +#define DMA_FTR0_FIELD0000_MASK (0x1U << DMA_FTR0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR0_FIELD0011_SHIFT (1U) +#define DMA_FTR0_FIELD0011_MASK (0x1U << DMA_FTR0_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR0_FIELD0010_SHIFT (5U) +#define DMA_FTR0_FIELD0010_MASK (0x1U << DMA_FTR0_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR0_FIELD0009_SHIFT (6U) +#define DMA_FTR0_FIELD0009_MASK (0x1U << DMA_FTR0_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR0_FIELD0008_SHIFT (7U) +#define DMA_FTR0_FIELD0008_MASK (0x1U << DMA_FTR0_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR0_FIELD0007_SHIFT (12U) +#define DMA_FTR0_FIELD0007_MASK (0x1U << DMA_FTR0_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR0_FIELD0006_SHIFT (13U) +#define DMA_FTR0_FIELD0006_MASK (0x1U << DMA_FTR0_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR0_FIELD0005_SHIFT (16U) +#define DMA_FTR0_FIELD0005_MASK (0x1U << DMA_FTR0_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR0_FIELD0004_SHIFT (17U) +#define DMA_FTR0_FIELD0004_MASK (0x1U << DMA_FTR0_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR0_FIELD0003_SHIFT (18U) +#define DMA_FTR0_FIELD0003_MASK (0x1U << DMA_FTR0_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR0_FIELD0002_SHIFT (30U) +#define DMA_FTR0_FIELD0002_MASK (0x1U << DMA_FTR0_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR0_FIELD0001_SHIFT (31U) +#define DMA_FTR0_FIELD0001_MASK (0x1U << DMA_FTR0_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR1 */ +#define DMA_FTR1_OFFSET (0x44U) +#define DMA_FTR1 (0x0U) +#define DMA_FTR1_FIELD0000_SHIFT (0U) +#define DMA_FTR1_FIELD0000_MASK (0x1U << DMA_FTR1_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR1_FIELD0011_SHIFT (1U) +#define DMA_FTR1_FIELD0011_MASK (0x1U << DMA_FTR1_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR1_FIELD0010_SHIFT (5U) +#define DMA_FTR1_FIELD0010_MASK (0x1U << DMA_FTR1_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR1_FIELD0009_SHIFT (6U) +#define DMA_FTR1_FIELD0009_MASK (0x1U << DMA_FTR1_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR1_FIELD0008_SHIFT (7U) +#define DMA_FTR1_FIELD0008_MASK (0x1U << DMA_FTR1_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR1_FIELD0007_SHIFT (12U) +#define DMA_FTR1_FIELD0007_MASK (0x1U << DMA_FTR1_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR1_FIELD0006_SHIFT (13U) +#define DMA_FTR1_FIELD0006_MASK (0x1U << DMA_FTR1_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR1_FIELD0005_SHIFT (16U) +#define DMA_FTR1_FIELD0005_MASK (0x1U << DMA_FTR1_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR1_FIELD0004_SHIFT (17U) +#define DMA_FTR1_FIELD0004_MASK (0x1U << DMA_FTR1_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR1_FIELD0003_SHIFT (18U) +#define DMA_FTR1_FIELD0003_MASK (0x1U << DMA_FTR1_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR1_FIELD0002_SHIFT (30U) +#define DMA_FTR1_FIELD0002_MASK (0x1U << DMA_FTR1_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR1_FIELD0001_SHIFT (31U) +#define DMA_FTR1_FIELD0001_MASK (0x1U << DMA_FTR1_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR2 */ +#define DMA_FTR2_OFFSET (0x48U) +#define DMA_FTR2 (0x0U) +#define DMA_FTR2_FIELD0000_SHIFT (0U) +#define DMA_FTR2_FIELD0000_MASK (0x1U << DMA_FTR2_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR2_FIELD0011_SHIFT (1U) +#define DMA_FTR2_FIELD0011_MASK (0x1U << DMA_FTR2_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR2_FIELD0010_SHIFT (5U) +#define DMA_FTR2_FIELD0010_MASK (0x1U << DMA_FTR2_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR2_FIELD0009_SHIFT (6U) +#define DMA_FTR2_FIELD0009_MASK (0x1U << DMA_FTR2_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR2_FIELD0008_SHIFT (7U) +#define DMA_FTR2_FIELD0008_MASK (0x1U << DMA_FTR2_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR2_FIELD0007_SHIFT (12U) +#define DMA_FTR2_FIELD0007_MASK (0x1U << DMA_FTR2_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR2_FIELD0006_SHIFT (13U) +#define DMA_FTR2_FIELD0006_MASK (0x1U << DMA_FTR2_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR2_FIELD0005_SHIFT (16U) +#define DMA_FTR2_FIELD0005_MASK (0x1U << DMA_FTR2_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR2_FIELD0004_SHIFT (17U) +#define DMA_FTR2_FIELD0004_MASK (0x1U << DMA_FTR2_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR2_FIELD0003_SHIFT (18U) +#define DMA_FTR2_FIELD0003_MASK (0x1U << DMA_FTR2_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR2_FIELD0002_SHIFT (30U) +#define DMA_FTR2_FIELD0002_MASK (0x1U << DMA_FTR2_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR2_FIELD0001_SHIFT (31U) +#define DMA_FTR2_FIELD0001_MASK (0x1U << DMA_FTR2_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR3 */ +#define DMA_FTR3_OFFSET (0x4CU) +#define DMA_FTR3 (0x0U) +#define DMA_FTR3_FIELD0000_SHIFT (0U) +#define DMA_FTR3_FIELD0000_MASK (0x1U << DMA_FTR3_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR3_FIELD0011_SHIFT (1U) +#define DMA_FTR3_FIELD0011_MASK (0x1U << DMA_FTR3_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR3_FIELD0010_SHIFT (5U) +#define DMA_FTR3_FIELD0010_MASK (0x1U << DMA_FTR3_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR3_FIELD0009_SHIFT (6U) +#define DMA_FTR3_FIELD0009_MASK (0x1U << DMA_FTR3_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR3_FIELD0008_SHIFT (7U) +#define DMA_FTR3_FIELD0008_MASK (0x1U << DMA_FTR3_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR3_FIELD0007_SHIFT (12U) +#define DMA_FTR3_FIELD0007_MASK (0x1U << DMA_FTR3_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR3_FIELD0006_SHIFT (13U) +#define DMA_FTR3_FIELD0006_MASK (0x1U << DMA_FTR3_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR3_FIELD0005_SHIFT (16U) +#define DMA_FTR3_FIELD0005_MASK (0x1U << DMA_FTR3_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR3_FIELD0004_SHIFT (17U) +#define DMA_FTR3_FIELD0004_MASK (0x1U << DMA_FTR3_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR3_FIELD0003_SHIFT (18U) +#define DMA_FTR3_FIELD0003_MASK (0x1U << DMA_FTR3_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR3_FIELD0002_SHIFT (30U) +#define DMA_FTR3_FIELD0002_MASK (0x1U << DMA_FTR3_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR3_FIELD0001_SHIFT (31U) +#define DMA_FTR3_FIELD0001_MASK (0x1U << DMA_FTR3_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR4 */ +#define DMA_FTR4_OFFSET (0x50U) +#define DMA_FTR4 (0x0U) +#define DMA_FTR4_FIELD0000_SHIFT (0U) +#define DMA_FTR4_FIELD0000_MASK (0x1U << DMA_FTR4_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR4_FIELD0011_SHIFT (1U) +#define DMA_FTR4_FIELD0011_MASK (0x1U << DMA_FTR4_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR4_FIELD0010_SHIFT (5U) +#define DMA_FTR4_FIELD0010_MASK (0x1U << DMA_FTR4_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR4_FIELD0009_SHIFT (6U) +#define DMA_FTR4_FIELD0009_MASK (0x1U << DMA_FTR4_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR4_FIELD0008_SHIFT (7U) +#define DMA_FTR4_FIELD0008_MASK (0x1U << DMA_FTR4_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR4_FIELD0007_SHIFT (12U) +#define DMA_FTR4_FIELD0007_MASK (0x1U << DMA_FTR4_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR4_FIELD0006_SHIFT (13U) +#define DMA_FTR4_FIELD0006_MASK (0x1U << DMA_FTR4_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR4_FIELD0005_SHIFT (16U) +#define DMA_FTR4_FIELD0005_MASK (0x1U << DMA_FTR4_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR4_FIELD0004_SHIFT (17U) +#define DMA_FTR4_FIELD0004_MASK (0x1U << DMA_FTR4_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR4_FIELD0003_SHIFT (18U) +#define DMA_FTR4_FIELD0003_MASK (0x1U << DMA_FTR4_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR4_FIELD0002_SHIFT (30U) +#define DMA_FTR4_FIELD0002_MASK (0x1U << DMA_FTR4_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR4_FIELD0001_SHIFT (31U) +#define DMA_FTR4_FIELD0001_MASK (0x1U << DMA_FTR4_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR5 */ +#define DMA_FTR5_OFFSET (0x54U) +#define DMA_FTR5 (0x0U) +#define DMA_FTR5_FIELD0000_SHIFT (0U) +#define DMA_FTR5_FIELD0000_MASK (0x1U << DMA_FTR5_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR5_FIELD0011_SHIFT (1U) +#define DMA_FTR5_FIELD0011_MASK (0x1U << DMA_FTR5_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR5_FIELD0010_SHIFT (5U) +#define DMA_FTR5_FIELD0010_MASK (0x1U << DMA_FTR5_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR5_FIELD0009_SHIFT (6U) +#define DMA_FTR5_FIELD0009_MASK (0x1U << DMA_FTR5_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR5_FIELD0008_SHIFT (7U) +#define DMA_FTR5_FIELD0008_MASK (0x1U << DMA_FTR5_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR5_FIELD0007_SHIFT (12U) +#define DMA_FTR5_FIELD0007_MASK (0x1U << DMA_FTR5_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR5_FIELD0006_SHIFT (13U) +#define DMA_FTR5_FIELD0006_MASK (0x1U << DMA_FTR5_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR5_FIELD0005_SHIFT (16U) +#define DMA_FTR5_FIELD0005_MASK (0x1U << DMA_FTR5_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR5_FIELD0004_SHIFT (17U) +#define DMA_FTR5_FIELD0004_MASK (0x1U << DMA_FTR5_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR5_FIELD0003_SHIFT (18U) +#define DMA_FTR5_FIELD0003_MASK (0x1U << DMA_FTR5_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR5_FIELD0002_SHIFT (30U) +#define DMA_FTR5_FIELD0002_MASK (0x1U << DMA_FTR5_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR5_FIELD0001_SHIFT (31U) +#define DMA_FTR5_FIELD0001_MASK (0x1U << DMA_FTR5_FIELD0001_SHIFT) /* 0x80000000 */ +/* CSR0 */ +#define DMA_CSR0_OFFSET (0x100U) +#define DMA_CSR0 (0x0U) +#define DMA_CSR0_FIELD0000_SHIFT (0U) +#define DMA_CSR0_FIELD0000_MASK (0xFU << DMA_CSR0_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR0_FIELD0004_SHIFT (4U) +#define DMA_CSR0_FIELD0004_MASK (0x1FU << DMA_CSR0_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR0_FIELD0003_SHIFT (14U) +#define DMA_CSR0_FIELD0003_MASK (0x1U << DMA_CSR0_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR0_FIELD0002_SHIFT (15U) +#define DMA_CSR0_FIELD0002_MASK (0x1U << DMA_CSR0_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR0_FIELD0001_SHIFT (21U) +#define DMA_CSR0_FIELD0001_MASK (0x1U << DMA_CSR0_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC0 */ +#define DMA_CPC0_OFFSET (0x104U) +#define DMA_CPC0 (0x0U) +#define DMA_CPC0_FIELD0000_SHIFT (0U) +#define DMA_CPC0_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC0_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR1 */ +#define DMA_CSR1_OFFSET (0x108U) +#define DMA_CSR1 (0x0U) +#define DMA_CSR1_FIELD0000_SHIFT (0U) +#define DMA_CSR1_FIELD0000_MASK (0xFU << DMA_CSR1_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR1_FIELD0004_SHIFT (4U) +#define DMA_CSR1_FIELD0004_MASK (0x1FU << DMA_CSR1_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR1_FIELD0003_SHIFT (14U) +#define DMA_CSR1_FIELD0003_MASK (0x1U << DMA_CSR1_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR1_FIELD0002_SHIFT (15U) +#define DMA_CSR1_FIELD0002_MASK (0x1U << DMA_CSR1_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR1_FIELD0001_SHIFT (21U) +#define DMA_CSR1_FIELD0001_MASK (0x1U << DMA_CSR1_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC1 */ +#define DMA_CPC1_OFFSET (0x10CU) +#define DMA_CPC1 (0x0U) +#define DMA_CPC1_FIELD0000_SHIFT (0U) +#define DMA_CPC1_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC1_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR2 */ +#define DMA_CSR2_OFFSET (0x110U) +#define DMA_CSR2 (0x0U) +#define DMA_CSR2_FIELD0000_SHIFT (0U) +#define DMA_CSR2_FIELD0000_MASK (0xFU << DMA_CSR2_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR2_FIELD0004_SHIFT (4U) +#define DMA_CSR2_FIELD0004_MASK (0x1FU << DMA_CSR2_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR2_FIELD0003_SHIFT (14U) +#define DMA_CSR2_FIELD0003_MASK (0x1U << DMA_CSR2_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR2_FIELD0002_SHIFT (15U) +#define DMA_CSR2_FIELD0002_MASK (0x1U << DMA_CSR2_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR2_FIELD0001_SHIFT (21U) +#define DMA_CSR2_FIELD0001_MASK (0x1U << DMA_CSR2_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC2 */ +#define DMA_CPC2_OFFSET (0x114U) +#define DMA_CPC2 (0x0U) +#define DMA_CPC2_FIELD0000_SHIFT (0U) +#define DMA_CPC2_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR3 */ +#define DMA_CSR3_OFFSET (0x118U) +#define DMA_CSR3 (0x0U) +#define DMA_CSR3_FIELD0000_SHIFT (0U) +#define DMA_CSR3_FIELD0000_MASK (0xFU << DMA_CSR3_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR3_FIELD0004_SHIFT (4U) +#define DMA_CSR3_FIELD0004_MASK (0x1FU << DMA_CSR3_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR3_FIELD0003_SHIFT (14U) +#define DMA_CSR3_FIELD0003_MASK (0x1U << DMA_CSR3_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR3_FIELD0002_SHIFT (15U) +#define DMA_CSR3_FIELD0002_MASK (0x1U << DMA_CSR3_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR3_FIELD0001_SHIFT (21U) +#define DMA_CSR3_FIELD0001_MASK (0x1U << DMA_CSR3_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC3 */ +#define DMA_CPC3_OFFSET (0x11CU) +#define DMA_CPC3 (0x0U) +#define DMA_CPC3_FIELD0000_SHIFT (0U) +#define DMA_CPC3_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR4 */ +#define DMA_CSR4_OFFSET (0x120U) +#define DMA_CSR4 (0x0U) +#define DMA_CSR4_FIELD0000_SHIFT (0U) +#define DMA_CSR4_FIELD0000_MASK (0xFU << DMA_CSR4_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR4_FIELD0004_SHIFT (4U) +#define DMA_CSR4_FIELD0004_MASK (0x1FU << DMA_CSR4_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR4_FIELD0003_SHIFT (14U) +#define DMA_CSR4_FIELD0003_MASK (0x1U << DMA_CSR4_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR4_FIELD0002_SHIFT (15U) +#define DMA_CSR4_FIELD0002_MASK (0x1U << DMA_CSR4_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR4_FIELD0001_SHIFT (21U) +#define DMA_CSR4_FIELD0001_MASK (0x1U << DMA_CSR4_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC4 */ +#define DMA_CPC4_OFFSET (0x124U) +#define DMA_CPC4 (0x0U) +#define DMA_CPC4_FIELD0000_SHIFT (0U) +#define DMA_CPC4_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR5 */ +#define DMA_CSR5_OFFSET (0x128U) +#define DMA_CSR5 (0x0U) +#define DMA_CSR5_FIELD0000_SHIFT (0U) +#define DMA_CSR5_FIELD0000_MASK (0xFU << DMA_CSR5_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR5_FIELD0004_SHIFT (4U) +#define DMA_CSR5_FIELD0004_MASK (0x1FU << DMA_CSR5_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR5_FIELD0003_SHIFT (14U) +#define DMA_CSR5_FIELD0003_MASK (0x1U << DMA_CSR5_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR5_FIELD0002_SHIFT (15U) +#define DMA_CSR5_FIELD0002_MASK (0x1U << DMA_CSR5_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR5_FIELD0001_SHIFT (21U) +#define DMA_CSR5_FIELD0001_MASK (0x1U << DMA_CSR5_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC5 */ +#define DMA_CPC5_OFFSET (0x12CU) +#define DMA_CPC5 (0x0U) +#define DMA_CPC5_FIELD0000_SHIFT (0U) +#define DMA_CPC5_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC5_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* SAR0 */ +#define DMA_SAR0_OFFSET (0x400U) +#define DMA_SAR0 (0x0U) +#define DMA_SAR0_FIELD0000_SHIFT (0U) +#define DMA_SAR0_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR0_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR0 */ +#define DMA_DAR0_OFFSET (0x404U) +#define DMA_DAR0 (0x0U) +#define DMA_DAR0_FIELD0000_SHIFT (0U) +#define DMA_DAR0_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR0_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR0 */ +#define DMA_CCR0_OFFSET (0x408U) +#define DMA_CCR0 (0x0U) +#define DMA_CCR0_FIELD0000_SHIFT (0U) +#define DMA_CCR0_FIELD0000_MASK (0x1U << DMA_CCR0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR0_FIELD0009_SHIFT (1U) +#define DMA_CCR0_FIELD0009_MASK (0x7U << DMA_CCR0_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR0_FIELD0008_SHIFT (4U) +#define DMA_CCR0_FIELD0008_MASK (0xFU << DMA_CCR0_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR0_FIELD0007_SHIFT (8U) +#define DMA_CCR0_FIELD0007_MASK (0x7U << DMA_CCR0_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR0_FIELD0006_SHIFT (11U) +#define DMA_CCR0_FIELD0006_MASK (0x7U << DMA_CCR0_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR0_FIELD0005_SHIFT (14U) +#define DMA_CCR0_FIELD0005_MASK (0x1U << DMA_CCR0_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR0_FIELD0004_SHIFT (15U) +#define DMA_CCR0_FIELD0004_MASK (0x7U << DMA_CCR0_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR0_FIELD0003_SHIFT (18U) +#define DMA_CCR0_FIELD0003_MASK (0xFU << DMA_CCR0_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR0_FIELD0002_SHIFT (22U) +#define DMA_CCR0_FIELD0002_MASK (0x7U << DMA_CCR0_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR0_FIELD0001_SHIFT (25U) +#define DMA_CCR0_FIELD0001_MASK (0x7U << DMA_CCR0_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_0 */ +#define DMA_LC0_0_OFFSET (0x40CU) +#define DMA_LC0_0 (0x0U) +#define DMA_LC0_0_FIELD0000_SHIFT (0U) +#define DMA_LC0_0_FIELD0000_MASK (0xFFU << DMA_LC0_0_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_0 */ +#define DMA_LC1_0_OFFSET (0x410U) +#define DMA_LC1_0 (0x0U) +#define DMA_LC1_0_FIELD0000_SHIFT (0U) +#define DMA_LC1_0_FIELD0000_MASK (0xFFU << DMA_LC1_0_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING0 */ +#define DMA_PADDING0_OFFSET (0x0U) +/* PADDING1 */ +#define DMA_PADDING1_OFFSET (0x0U) +/* PADDING2 */ +#define DMA_PADDING2_OFFSET (0x0U) +/* SAR1 */ +#define DMA_SAR1_OFFSET (0x420U) +#define DMA_SAR1 (0x0U) +#define DMA_SAR1_FIELD0000_SHIFT (0U) +#define DMA_SAR1_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR1_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR1 */ +#define DMA_DAR1_OFFSET (0x424U) +#define DMA_DAR1 (0x0U) +#define DMA_DAR1_FIELD0000_SHIFT (0U) +#define DMA_DAR1_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR1_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR1 */ +#define DMA_CCR1_OFFSET (0x428U) +#define DMA_CCR1 (0x0U) +#define DMA_CCR1_FIELD0000_SHIFT (0U) +#define DMA_CCR1_FIELD0000_MASK (0x1U << DMA_CCR1_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR1_FIELD0009_SHIFT (1U) +#define DMA_CCR1_FIELD0009_MASK (0x7U << DMA_CCR1_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR1_FIELD0008_SHIFT (4U) +#define DMA_CCR1_FIELD0008_MASK (0xFU << DMA_CCR1_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR1_FIELD0007_SHIFT (8U) +#define DMA_CCR1_FIELD0007_MASK (0x7U << DMA_CCR1_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR1_FIELD0006_SHIFT (11U) +#define DMA_CCR1_FIELD0006_MASK (0x7U << DMA_CCR1_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR1_FIELD0005_SHIFT (14U) +#define DMA_CCR1_FIELD0005_MASK (0x1U << DMA_CCR1_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR1_FIELD0004_SHIFT (15U) +#define DMA_CCR1_FIELD0004_MASK (0x7U << DMA_CCR1_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR1_FIELD0003_SHIFT (18U) +#define DMA_CCR1_FIELD0003_MASK (0xFU << DMA_CCR1_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR1_FIELD0002_SHIFT (22U) +#define DMA_CCR1_FIELD0002_MASK (0x7U << DMA_CCR1_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR1_FIELD0001_SHIFT (25U) +#define DMA_CCR1_FIELD0001_MASK (0x7U << DMA_CCR1_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_1 */ +#define DMA_LC0_1_OFFSET (0x42CU) +#define DMA_LC0_1 (0x0U) +#define DMA_LC0_1_FIELD0000_SHIFT (0U) +#define DMA_LC0_1_FIELD0000_MASK (0xFFU << DMA_LC0_1_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_1 */ +#define DMA_LC1_1_OFFSET (0x430U) +#define DMA_LC1_1 (0x0U) +#define DMA_LC1_1_FIELD0000_SHIFT (0U) +#define DMA_LC1_1_FIELD0000_MASK (0xFFU << DMA_LC1_1_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING0 */ +#define DMA_PADDING0_OFFSET (0x0U) +/* PADDING1 */ +#define DMA_PADDING1_OFFSET (0x0U) +/* PADDING2 */ +#define DMA_PADDING2_OFFSET (0x0U) +/* SAR2 */ +#define DMA_SAR2_OFFSET (0x440U) +#define DMA_SAR2 (0x0U) +#define DMA_SAR2_FIELD0000_SHIFT (0U) +#define DMA_SAR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR2 */ +#define DMA_DAR2_OFFSET (0x444U) +#define DMA_DAR2 (0x0U) +#define DMA_DAR2_FIELD0000_SHIFT (0U) +#define DMA_DAR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR2 */ +#define DMA_CCR2_OFFSET (0x448U) +#define DMA_CCR2 (0x0U) +#define DMA_CCR2_FIELD0000_SHIFT (0U) +#define DMA_CCR2_FIELD0000_MASK (0x1U << DMA_CCR2_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR2_FIELD0009_SHIFT (1U) +#define DMA_CCR2_FIELD0009_MASK (0x7U << DMA_CCR2_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR2_FIELD0008_SHIFT (4U) +#define DMA_CCR2_FIELD0008_MASK (0xFU << DMA_CCR2_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR2_FIELD0007_SHIFT (8U) +#define DMA_CCR2_FIELD0007_MASK (0x7U << DMA_CCR2_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR2_FIELD0006_SHIFT (11U) +#define DMA_CCR2_FIELD0006_MASK (0x7U << DMA_CCR2_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR2_FIELD0005_SHIFT (14U) +#define DMA_CCR2_FIELD0005_MASK (0x1U << DMA_CCR2_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR2_FIELD0004_SHIFT (15U) +#define DMA_CCR2_FIELD0004_MASK (0x7U << DMA_CCR2_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR2_FIELD0003_SHIFT (18U) +#define DMA_CCR2_FIELD0003_MASK (0xFU << DMA_CCR2_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR2_FIELD0002_SHIFT (22U) +#define DMA_CCR2_FIELD0002_MASK (0x7U << DMA_CCR2_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR2_FIELD0001_SHIFT (25U) +#define DMA_CCR2_FIELD0001_MASK (0x7U << DMA_CCR2_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_2 */ +#define DMA_LC0_2_OFFSET (0x44CU) +#define DMA_LC0_2 (0x0U) +#define DMA_LC0_2_FIELD0000_SHIFT (0U) +#define DMA_LC0_2_FIELD0000_MASK (0xFFU << DMA_LC0_2_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_2 */ +#define DMA_LC1_2_OFFSET (0x450U) +#define DMA_LC1_2 (0x0U) +#define DMA_LC1_2_FIELD0000_SHIFT (0U) +#define DMA_LC1_2_FIELD0000_MASK (0xFFU << DMA_LC1_2_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING0 */ +#define DMA_PADDING0_OFFSET (0x0U) +/* PADDING1 */ +#define DMA_PADDING1_OFFSET (0x0U) +/* PADDING2 */ +#define DMA_PADDING2_OFFSET (0x0U) +/* SAR3 */ +#define DMA_SAR3_OFFSET (0x460U) +#define DMA_SAR3 (0x0U) +#define DMA_SAR3_FIELD0000_SHIFT (0U) +#define DMA_SAR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR3 */ +#define DMA_DAR3_OFFSET (0x464U) +#define DMA_DAR3 (0x0U) +#define DMA_DAR3_FIELD0000_SHIFT (0U) +#define DMA_DAR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR3 */ +#define DMA_CCR3_OFFSET (0x468U) +#define DMA_CCR3 (0x0U) +#define DMA_CCR3_FIELD0000_SHIFT (0U) +#define DMA_CCR3_FIELD0000_MASK (0x1U << DMA_CCR3_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR3_FIELD0009_SHIFT (1U) +#define DMA_CCR3_FIELD0009_MASK (0x7U << DMA_CCR3_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR3_FIELD0008_SHIFT (4U) +#define DMA_CCR3_FIELD0008_MASK (0xFU << DMA_CCR3_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR3_FIELD0007_SHIFT (8U) +#define DMA_CCR3_FIELD0007_MASK (0x7U << DMA_CCR3_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR3_FIELD0006_SHIFT (11U) +#define DMA_CCR3_FIELD0006_MASK (0x7U << DMA_CCR3_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR3_FIELD0005_SHIFT (14U) +#define DMA_CCR3_FIELD0005_MASK (0x1U << DMA_CCR3_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR3_FIELD0004_SHIFT (15U) +#define DMA_CCR3_FIELD0004_MASK (0x7U << DMA_CCR3_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR3_FIELD0003_SHIFT (18U) +#define DMA_CCR3_FIELD0003_MASK (0xFU << DMA_CCR3_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR3_FIELD0002_SHIFT (22U) +#define DMA_CCR3_FIELD0002_MASK (0x7U << DMA_CCR3_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR3_FIELD0001_SHIFT (25U) +#define DMA_CCR3_FIELD0001_MASK (0x7U << DMA_CCR3_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_3 */ +#define DMA_LC0_3_OFFSET (0x46CU) +#define DMA_LC0_3 (0x0U) +#define DMA_LC0_3_FIELD0000_SHIFT (0U) +#define DMA_LC0_3_FIELD0000_MASK (0xFFU << DMA_LC0_3_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_3 */ +#define DMA_LC1_3_OFFSET (0x470U) +#define DMA_LC1_3 (0x0U) +#define DMA_LC1_3_FIELD0000_SHIFT (0U) +#define DMA_LC1_3_FIELD0000_MASK (0xFFU << DMA_LC1_3_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING0 */ +#define DMA_PADDING0_OFFSET (0x0U) +/* PADDING1 */ +#define DMA_PADDING1_OFFSET (0x0U) +/* PADDING2 */ +#define DMA_PADDING2_OFFSET (0x0U) +/* SAR4 */ +#define DMA_SAR4_OFFSET (0x480U) +#define DMA_SAR4 (0x0U) +#define DMA_SAR4_FIELD0000_SHIFT (0U) +#define DMA_SAR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR4 */ +#define DMA_DAR4_OFFSET (0x484U) +#define DMA_DAR4 (0x0U) +#define DMA_DAR4_FIELD0000_SHIFT (0U) +#define DMA_DAR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR4 */ +#define DMA_CCR4_OFFSET (0x488U) +#define DMA_CCR4 (0x0U) +#define DMA_CCR4_FIELD0000_SHIFT (0U) +#define DMA_CCR4_FIELD0000_MASK (0x1U << DMA_CCR4_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR4_FIELD0009_SHIFT (1U) +#define DMA_CCR4_FIELD0009_MASK (0x7U << DMA_CCR4_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR4_FIELD0008_SHIFT (4U) +#define DMA_CCR4_FIELD0008_MASK (0xFU << DMA_CCR4_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR4_FIELD0007_SHIFT (8U) +#define DMA_CCR4_FIELD0007_MASK (0x7U << DMA_CCR4_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR4_FIELD0006_SHIFT (11U) +#define DMA_CCR4_FIELD0006_MASK (0x7U << DMA_CCR4_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR4_FIELD0005_SHIFT (14U) +#define DMA_CCR4_FIELD0005_MASK (0x1U << DMA_CCR4_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR4_FIELD0004_SHIFT (15U) +#define DMA_CCR4_FIELD0004_MASK (0x7U << DMA_CCR4_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR4_FIELD0003_SHIFT (18U) +#define DMA_CCR4_FIELD0003_MASK (0xFU << DMA_CCR4_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR4_FIELD0002_SHIFT (22U) +#define DMA_CCR4_FIELD0002_MASK (0x7U << DMA_CCR4_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR4_FIELD0001_SHIFT (25U) +#define DMA_CCR4_FIELD0001_MASK (0x7U << DMA_CCR4_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_4 */ +#define DMA_LC0_4_OFFSET (0x48CU) +#define DMA_LC0_4 (0x0U) +#define DMA_LC0_4_FIELD0000_SHIFT (0U) +#define DMA_LC0_4_FIELD0000_MASK (0xFFU << DMA_LC0_4_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_4 */ +#define DMA_LC1_4_OFFSET (0x490U) +#define DMA_LC1_4 (0x0U) +#define DMA_LC1_4_FIELD0000_SHIFT (0U) +#define DMA_LC1_4_FIELD0000_MASK (0xFFU << DMA_LC1_4_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING0 */ +#define DMA_PADDING0_OFFSET (0x0U) +/* PADDING1 */ +#define DMA_PADDING1_OFFSET (0x0U) +/* PADDING2 */ +#define DMA_PADDING2_OFFSET (0x0U) +/* SAR5 */ +#define DMA_SAR5_OFFSET (0x4A0U) +#define DMA_SAR5 (0x0U) +#define DMA_SAR5_FIELD0000_SHIFT (0U) +#define DMA_SAR5_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR5_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR5 */ +#define DMA_DAR5_OFFSET (0x4A4U) +#define DMA_DAR5 (0x0U) +#define DMA_DAR5_FIELD0000_SHIFT (0U) +#define DMA_DAR5_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR5_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR5 */ +#define DMA_CCR5_OFFSET (0x4A8U) +#define DMA_CCR5 (0x0U) +#define DMA_CCR5_FIELD0000_SHIFT (0U) +#define DMA_CCR5_FIELD0000_MASK (0x1U << DMA_CCR5_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR5_FIELD0009_SHIFT (1U) +#define DMA_CCR5_FIELD0009_MASK (0x7U << DMA_CCR5_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR5_FIELD0008_SHIFT (4U) +#define DMA_CCR5_FIELD0008_MASK (0xFU << DMA_CCR5_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR5_FIELD0007_SHIFT (8U) +#define DMA_CCR5_FIELD0007_MASK (0x7U << DMA_CCR5_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR5_FIELD0006_SHIFT (11U) +#define DMA_CCR5_FIELD0006_MASK (0x7U << DMA_CCR5_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR5_FIELD0005_SHIFT (14U) +#define DMA_CCR5_FIELD0005_MASK (0x1U << DMA_CCR5_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR5_FIELD0004_SHIFT (15U) +#define DMA_CCR5_FIELD0004_MASK (0x7U << DMA_CCR5_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR5_FIELD0003_SHIFT (18U) +#define DMA_CCR5_FIELD0003_MASK (0xFU << DMA_CCR5_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR5_FIELD0002_SHIFT (22U) +#define DMA_CCR5_FIELD0002_MASK (0x7U << DMA_CCR5_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR5_FIELD0001_SHIFT (25U) +#define DMA_CCR5_FIELD0001_MASK (0x7U << DMA_CCR5_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_5 */ +#define DMA_LC0_5_OFFSET (0x4ACU) +#define DMA_LC0_5 (0x0U) +#define DMA_LC0_5_FIELD0000_SHIFT (0U) +#define DMA_LC0_5_FIELD0000_MASK (0xFFU << DMA_LC0_5_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_5 */ +#define DMA_LC1_5_OFFSET (0x4B0U) +#define DMA_LC1_5 (0x0U) +#define DMA_LC1_5_FIELD0000_SHIFT (0U) +#define DMA_LC1_5_FIELD0000_MASK (0xFFU << DMA_LC1_5_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING0 */ +#define DMA_PADDING0_OFFSET (0x0U) +/* PADDING1 */ +#define DMA_PADDING1_OFFSET (0x0U) +/* PADDING2 */ +#define DMA_PADDING2_OFFSET (0x0U) +/* DBGSTATUS */ +#define DMA_DBGSTATUS_OFFSET (0xD00U) +#define DMA_DBGSTATUS (0x0U) +#define DMA_DBGSTATUS_FIELD0000_SHIFT (0U) +#define DMA_DBGSTATUS_FIELD0000_MASK (0x3U << DMA_DBGSTATUS_FIELD0000_SHIFT) /* 0x00000003 */ +/* DBGCMD */ +#define DMA_DBGCMD_OFFSET (0xD04U) +#define DMA_DBGCMD_FIELD0000_SHIFT (0U) +#define DMA_DBGCMD_FIELD0000_MASK (0x3U << DMA_DBGCMD_FIELD0000_SHIFT) /* 0x00000003 */ +/* DBGINST0 */ +#define DMA_DBGINST0_OFFSET (0xD08U) +#define DMA_DBGINST0_FIELD0000_SHIFT (0U) +#define DMA_DBGINST0_FIELD0000_MASK (0x1U << DMA_DBGINST0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_DBGINST0_FIELD0003_SHIFT (8U) +#define DMA_DBGINST0_FIELD0003_MASK (0x7U << DMA_DBGINST0_FIELD0003_SHIFT) /* 0x00000700 */ +#define DMA_DBGINST0_FIELD0002_SHIFT (16U) +#define DMA_DBGINST0_FIELD0002_MASK (0xFFU << DMA_DBGINST0_FIELD0002_SHIFT) /* 0x00FF0000 */ +#define DMA_DBGINST0_FIELD0001_SHIFT (24U) +#define DMA_DBGINST0_FIELD0001_MASK (0xFFU << DMA_DBGINST0_FIELD0001_SHIFT) /* 0xFF000000 */ +/* DBGINST1 */ +#define DMA_DBGINST1_OFFSET (0xD0CU) +#define DMA_DBGINST1_FIELD0000_SHIFT (0U) +#define DMA_DBGINST1_FIELD0000_MASK (0xFFU << DMA_DBGINST1_FIELD0000_SHIFT) /* 0x000000FF */ +#define DMA_DBGINST1_FIELD0003_SHIFT (8U) +#define DMA_DBGINST1_FIELD0003_MASK (0xFFU << DMA_DBGINST1_FIELD0003_SHIFT) /* 0x0000FF00 */ +#define DMA_DBGINST1_FIELD0002_SHIFT (16U) +#define DMA_DBGINST1_FIELD0002_MASK (0xFFU << DMA_DBGINST1_FIELD0002_SHIFT) /* 0x00FF0000 */ +#define DMA_DBGINST1_FIELD0001_SHIFT (24U) +#define DMA_DBGINST1_FIELD0001_MASK (0xFFU << DMA_DBGINST1_FIELD0001_SHIFT) /* 0xFF000000 */ +/* CR0 */ +#define DMA_CR0_OFFSET (0xE00U) +#define DMA_CR0 (0x47051U) +#define DMA_CR0_FIELD0000_SHIFT (0U) +#define DMA_CR0_FIELD0000_MASK (0x1U << DMA_CR0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CR0_FIELD0005_SHIFT (1U) +#define DMA_CR0_FIELD0005_MASK (0x1U << DMA_CR0_FIELD0005_SHIFT) /* 0x00000002 */ +#define DMA_CR0_FIELD0004_SHIFT (2U) +#define DMA_CR0_FIELD0004_MASK (0x1U << DMA_CR0_FIELD0004_SHIFT) /* 0x00000004 */ +#define DMA_CR0_FIELD0003_SHIFT (4U) +#define DMA_CR0_FIELD0003_MASK (0x7U << DMA_CR0_FIELD0003_SHIFT) /* 0x00000070 */ +#define DMA_CR0_FIELD0002_SHIFT (12U) +#define DMA_CR0_FIELD0002_MASK (0x1FU << DMA_CR0_FIELD0002_SHIFT) /* 0x0001F000 */ +#define DMA_CR0_FIELD0001_SHIFT (17U) +#define DMA_CR0_FIELD0001_MASK (0x1FU << DMA_CR0_FIELD0001_SHIFT) /* 0x003E0000 */ +/* CR1 */ +#define DMA_CR1_OFFSET (0xE04U) +#define DMA_CR1 (0x57U) +#define DMA_CR1_FIELD0000_SHIFT (0U) +#define DMA_CR1_FIELD0000_MASK (0x7U << DMA_CR1_FIELD0000_SHIFT) /* 0x00000007 */ +#define DMA_CR1_FIELD0001_SHIFT (4U) +#define DMA_CR1_FIELD0001_MASK (0xFU << DMA_CR1_FIELD0001_SHIFT) /* 0x000000F0 */ +/* CR2 */ +#define DMA_CR2_OFFSET (0xE08U) +#define DMA_CR2 (0x0U) +#define DMA_CR2_FIELD0000_SHIFT (0U) +#define DMA_CR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CR3 */ +#define DMA_CR3_OFFSET (0xE0CU) +#define DMA_CR3 (0x0U) +#define DMA_CR3_FIELD0000_SHIFT (0U) +#define DMA_CR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CR4 */ +#define DMA_CR4_OFFSET (0xE10U) +#define DMA_CR4 (0x6U) +#define DMA_CR4_FIELD0000_SHIFT (0U) +#define DMA_CR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CRDN */ +#define DMA_CRDN_OFFSET (0xE14U) +#define DMA_CRDN (0x2094733U) +#define DMA_CRDN_FIELD0000_SHIFT (0U) +#define DMA_CRDN_FIELD0000_MASK (0x7U << DMA_CRDN_FIELD0000_SHIFT) /* 0x00000007 */ +#define DMA_CRDN_FIELD0005_SHIFT (4U) +#define DMA_CRDN_FIELD0005_MASK (0x7U << DMA_CRDN_FIELD0005_SHIFT) /* 0x00000070 */ +#define DMA_CRDN_FIELD0004_SHIFT (8U) +#define DMA_CRDN_FIELD0004_MASK (0xFU << DMA_CRDN_FIELD0004_SHIFT) /* 0x00000F00 */ +#define DMA_CRDN_FIELD0003_SHIFT (12U) +#define DMA_CRDN_FIELD0003_MASK (0x7U << DMA_CRDN_FIELD0003_SHIFT) /* 0x00007000 */ +#define DMA_CRDN_FIELD0002_SHIFT (16U) +#define DMA_CRDN_FIELD0002_MASK (0xFU << DMA_CRDN_FIELD0002_SHIFT) /* 0x000F0000 */ +#define DMA_CRDN_FIELD0001_SHIFT (20U) +#define DMA_CRDN_FIELD0001_MASK (0x3FFU << DMA_CRDN_FIELD0001_SHIFT) /* 0x3FF00000 */ +/* WD */ +#define DMA_WD_OFFSET (0xE80U) +#define DMA_WD_FIELD0000_SHIFT (0U) +#define DMA_WD_FIELD0000_MASK (0x1U << DMA_WD_FIELD0000_SHIFT) /* 0x00000001 */ +/****************************************ACDCDIG*****************************************/ +/* VUCTL */ +#define ACDCDIG_VUCTL_OFFSET (0x0U) +#define ACDCDIG_VUCTL_ADCZDT_SHIFT (0U) +#define ACDCDIG_VUCTL_ADCZDT_MASK (0x1U << ACDCDIG_VUCTL_ADCZDT_SHIFT) /* 0x00000001 */ +#define ACDCDIG_VUCTL_ADCFADE_SHIFT (1U) +#define ACDCDIG_VUCTL_ADCFADE_MASK (0x1U << ACDCDIG_VUCTL_ADCFADE_SHIFT) /* 0x00000002 */ +#define ACDCDIG_VUCTL_ADC_BYPS_SHIFT (2U) +#define ACDCDIG_VUCTL_ADC_BYPS_MASK (0x1U << ACDCDIG_VUCTL_ADC_BYPS_SHIFT) /* 0x00000004 */ +/* VUCTIME */ +#define ACDCDIG_VUCTIME_OFFSET (0x4U) +#define ACDCDIG_VUCTIME_VUCT_SHIFT (0U) +#define ACDCDIG_VUCTIME_VUCT_MASK (0xFFU << ACDCDIG_VUCTIME_VUCT_SHIFT) /* 0x000000FF */ +/* DIGEN */ +#define ACDCDIG_DIGEN_OFFSET (0x8U) +#define ACDCDIG_DIGEN_I2STX_EN_SHIFT (0U) +#define ACDCDIG_DIGEN_I2STX_EN_MASK (0x1U << ACDCDIG_DIGEN_I2STX_EN_SHIFT) /* 0x00000001 */ +#define ACDCDIG_DIGEN_ADC_EN_SHIFT (1U) +#define ACDCDIG_DIGEN_ADC_EN_MASK (0x1U << ACDCDIG_DIGEN_ADC_EN_SHIFT) /* 0x00000002 */ +/* CLKCTRL */ +#define ACDCDIG_CLKCTRL_OFFSET (0xCU) +#define ACDCDIG_CLKCTRL_FILTER_GATE_EN_SHIFT (2U) +#define ACDCDIG_CLKCTRL_FILTER_GATE_EN_MASK (0x1U << ACDCDIG_CLKCTRL_FILTER_GATE_EN_SHIFT) /* 0x00000004 */ +#define ACDCDIG_CLKCTRL_CKE_BCLK_SHIFT (3U) +#define ACDCDIG_CLKCTRL_CKE_BCLK_MASK (0x1U << ACDCDIG_CLKCTRL_CKE_BCLK_SHIFT) /* 0x00000008 */ +#define ACDCDIG_CLKCTRL_I2STX_CKE_SHIFT (4U) +#define ACDCDIG_CLKCTRL_I2STX_CKE_MASK (0x1U << ACDCDIG_CLKCTRL_I2STX_CKE_SHIFT) /* 0x00000010 */ +#define ACDCDIG_CLKCTRL_ADC_CKE_SHIFT (5U) +#define ACDCDIG_CLKCTRL_ADC_CKE_MASK (0x1U << ACDCDIG_CLKCTRL_ADC_CKE_SHIFT) /* 0x00000020 */ +#define ACDCDIG_CLKCTRL_CIC_DS_RATIO_SHIFT (6U) +#define ACDCDIG_CLKCTRL_CIC_DS_RATIO_MASK (0x3U << ACDCDIG_CLKCTRL_CIC_DS_RATIO_SHIFT) /* 0x000000C0 */ +/* CLKDIV */ +#define ACDCDIG_CLKDIV_OFFSET (0x10U) +#define ACDCDIG_CLKDIV_INT_DIV_CON_SHIFT (0U) +#define ACDCDIG_CLKDIV_INT_DIV_CON_MASK (0xFU << ACDCDIG_CLKDIV_INT_DIV_CON_SHIFT) /* 0x0000000F */ +/* REFCFG */ +#define ACDCDIG_REFCFG_OFFSET (0x14U) +#define ACDCDIG_REFCFG_REF_TOP_TRIM_SHIFT (0U) +#define ACDCDIG_REFCFG_REF_TOP_TRIM_MASK (0xFU << ACDCDIG_REFCFG_REF_TOP_TRIM_SHIFT) /* 0x0000000F */ +#define ACDCDIG_REFCFG_REF_ANA_TRIM_SHIFT (4U) +#define ACDCDIG_REFCFG_REF_ANA_TRIM_MASK (0x3U << ACDCDIG_REFCFG_REF_ANA_TRIM_SHIFT) /* 0x00000030 */ +#define ACDCDIG_REFCFG_REF_TOP_PWD_SHIFT (6U) +#define ACDCDIG_REFCFG_REF_TOP_PWD_MASK (0x1U << ACDCDIG_REFCFG_REF_TOP_PWD_SHIFT) /* 0x00000040 */ +/* ADCCFG0 */ +#define ACDCDIG_ADCCFG0_OFFSET (0x18U) +#define ACDCDIG_ADCCFG0_ADC_DITH_SEL_SHIFT (0U) +#define ACDCDIG_ADCCFG0_ADC_DITH_SEL_MASK (0x7U << ACDCDIG_ADCCFG0_ADC_DITH_SEL_SHIFT) /* 0x00000007 */ +#define ACDCDIG_ADCCFG0_ADC_DITH_EN_SHIFT (3U) +#define ACDCDIG_ADCCFG0_ADC_DITH_EN_MASK (0x1U << ACDCDIG_ADCCFG0_ADC_DITH_EN_SHIFT) /* 0x00000008 */ +#define ACDCDIG_ADCCFG0_ADC_CHOP_CLK_SEL_SHIFT (4U) +#define ACDCDIG_ADCCFG0_ADC_CHOP_CLK_SEL_MASK (0x1U << ACDCDIG_ADCCFG0_ADC_CHOP_CLK_SEL_SHIFT) /* 0x00000010 */ +#define ACDCDIG_ADCCFG0_ADC_CHOP_EN_SHIFT (5U) +#define ACDCDIG_ADCCFG0_ADC_CHOP_EN_MASK (0x1U << ACDCDIG_ADCCFG0_ADC_CHOP_EN_SHIFT) /* 0x00000020 */ +#define ACDCDIG_ADCCFG0_ADC_PWD_R_SHIFT (6U) +#define ACDCDIG_ADCCFG0_ADC_PWD_R_MASK (0x1U << ACDCDIG_ADCCFG0_ADC_PWD_R_SHIFT) /* 0x00000040 */ +#define ACDCDIG_ADCCFG0_ADC_PWD_L_SHIFT (7U) +#define ACDCDIG_ADCCFG0_ADC_PWD_L_MASK (0x1U << ACDCDIG_ADCCFG0_ADC_PWD_L_SHIFT) /* 0x00000080 */ +/* ADCCFG1 */ +#define ACDCDIG_ADCCFG1_OFFSET (0x1CU) +#define ACDCDIG_ADCCFG1_ADC_BOOST_VAGOP_SHIFT (0U) +#define ACDCDIG_ADCCFG1_ADC_BOOST_VAGOP_MASK (0x1U << ACDCDIG_ADCCFG1_ADC_BOOST_VAGOP_SHIFT) /* 0x00000001 */ +#define ACDCDIG_ADCCFG1_ADC_BOOST_OPAMP_SHIFT (1U) +#define ACDCDIG_ADCCFG1_ADC_BOOST_OPAMP_MASK (0x1U << ACDCDIG_ADCCFG1_ADC_BOOST_OPAMP_SHIFT) /* 0x00000002 */ +#define ACDCDIG_ADCCFG1_ADC_ATTN_OPBIAS_SHIFT (2U) +#define ACDCDIG_ADCCFG1_ADC_ATTN_OPBIAS_MASK (0x1U << ACDCDIG_ADCCFG1_ADC_ATTN_OPBIAS_SHIFT) /* 0x00000004 */ +#define ACDCDIG_ADCCFG1_ADC_ATTN_ALLIBIAS_SHIFT (3U) +#define ACDCDIG_ADCCFG1_ADC_ATTN_ALLIBIAS_MASK (0x1U << ACDCDIG_ADCCFG1_ADC_ATTN_ALLIBIAS_SHIFT) /* 0x00000008 */ +/* ADCCFG2 */ +#define ACDCDIG_ADCCFG2_OFFSET (0x20U) +#define ACDCDIG_ADCCFG2_CT_ADC_BOOST_SHIFT (0U) +#define ACDCDIG_ADCCFG2_CT_ADC_BOOST_MASK (0x1U << ACDCDIG_ADCCFG2_CT_ADC_BOOST_SHIFT) /* 0x00000001 */ +#define ACDCDIG_ADCCFG2_CT_ADC_ATTN_SHIFT (1U) +#define ACDCDIG_ADCCFG2_CT_ADC_ATTN_MASK (0x1U << ACDCDIG_ADCCFG2_CT_ADC_ATTN_SHIFT) /* 0x00000002 */ +#define ACDCDIG_ADCCFG2_CT_ADC_ATTN_OP_SHIFT (2U) +#define ACDCDIG_ADCCFG2_CT_ADC_ATTN_OP_MASK (0x1U << ACDCDIG_ADCCFG2_CT_ADC_ATTN_OP_SHIFT) /* 0x00000004 */ +#define ACDCDIG_ADCCFG2_ADC_OUT_SEL_SHIFT (3U) +#define ACDCDIG_ADCCFG2_ADC_OUT_SEL_MASK (0x1U << ACDCDIG_ADCCFG2_ADC_OUT_SEL_SHIFT) /* 0x00000008 */ +#define ACDCDIG_ADCCFG2_CT_ADC_ZERO_SHIFT (4U) +#define ACDCDIG_ADCCFG2_CT_ADC_ZERO_MASK (0x1U << ACDCDIG_ADCCFG2_CT_ADC_ZERO_SHIFT) /* 0x00000010 */ +#define ACDCDIG_ADCCFG2_CT_ADC_PWD_SHIFT (5U) +#define ACDCDIG_ADCCFG2_CT_ADC_PWD_MASK (0x1U << ACDCDIG_ADCCFG2_CT_ADC_PWD_SHIFT) /* 0x00000020 */ +/* ADCCFG3 */ +#define ACDCDIG_ADCCFG3_OFFSET (0x24U) +#define ACDCDIG_ADCCFG3_FIR_COM_BPS_SHIFT (0U) +#define ACDCDIG_ADCCFG3_FIR_COM_BPS_MASK (0x1U << ACDCDIG_ADCCFG3_FIR_COM_BPS_SHIFT) /* 0x00000001 */ +#define ACDCDIG_ADCCFG3_SIG_SCALE_MODE_SHIFT (1U) +#define ACDCDIG_ADCCFG3_SIG_SCALE_MODE_MASK (0x1U << ACDCDIG_ADCCFG3_SIG_SCALE_MODE_SHIFT) /* 0x00000002 */ +#define ACDCDIG_ADCCFG3_ADCSRT_SHIFT (2U) +#define ACDCDIG_ADCCFG3_ADCSRT_MASK (0x7U << ACDCDIG_ADCCFG3_ADCSRT_SHIFT) /* 0x0000001C */ +/* ADCVOLL */ +#define ACDCDIG_ADCVOLL_OFFSET (0x28U) +#define ACDCDIG_ADCVOLL_ADCLV_SHIFT (0U) +#define ACDCDIG_ADCVOLL_ADCLV_MASK (0xFFU << ACDCDIG_ADCVOLL_ADCLV_SHIFT) /* 0x000000FF */ +/* ADCVOLR */ +#define ACDCDIG_ADCVOLR_OFFSET (0x2CU) +#define ACDCDIG_ADCVOLR_ADCRV_SHIFT (0U) +#define ACDCDIG_ADCVOLR_ADCRV_MASK (0xFFU << ACDCDIG_ADCVOLR_ADCRV_SHIFT) /* 0x000000FF */ +/* ALC0 */ +#define ACDCDIG_ALC0_OFFSET (0x30U) +#define ACDCDIG_ALC0_ADCRV_GAIN_POL_SHIFT (4U) +#define ACDCDIG_ALC0_ADCRV_GAIN_POL_MASK (0x1U << ACDCDIG_ALC0_ADCRV_GAIN_POL_SHIFT) /* 0x00000010 */ +#define ACDCDIG_ALC0_ADCLV_GAIN_POL_SHIFT (5U) +#define ACDCDIG_ALC0_ADCLV_GAIN_POL_MASK (0x1U << ACDCDIG_ALC0_ADCLV_GAIN_POL_SHIFT) /* 0x00000020 */ +#define ACDCDIG_ALC0_ALCR_SHIFT (6U) +#define ACDCDIG_ALC0_ALCR_MASK (0x1U << ACDCDIG_ALC0_ALCR_SHIFT) /* 0x00000040 */ +#define ACDCDIG_ALC0_ALCL_SHIFT (7U) +#define ACDCDIG_ALC0_ALCL_MASK (0x1U << ACDCDIG_ALC0_ALCL_SHIFT) /* 0x00000080 */ +/* ALC1 */ +#define ACDCDIG_ALC1_OFFSET (0x34U) +#define ACDCDIG_ALC1_ALCRRATE_SHIFT (0U) +#define ACDCDIG_ALC1_ALCRRATE_MASK (0xFU << ACDCDIG_ALC1_ALCRRATE_SHIFT) /* 0x0000000F */ +#define ACDCDIG_ALC1_ALCARATE_SHIFT (4U) +#define ACDCDIG_ALC1_ALCARATE_MASK (0xFU << ACDCDIG_ALC1_ALCARATE_SHIFT) /* 0x000000F0 */ +/* ALC2 */ +#define ACDCDIG_ALC2_OFFSET (0x38U) +#define ACDCDIG_ALC2_ALCMIN_SHIFT (0U) +#define ACDCDIG_ALC2_ALCMIN_MASK (0x7U << ACDCDIG_ALC2_ALCMIN_SHIFT) /* 0x00000007 */ +#define ACDCDIG_ALC2_ALCMAX_SHIFT (4U) +#define ACDCDIG_ALC2_ALCMAX_MASK (0x7U << ACDCDIG_ALC2_ALCMAX_SHIFT) /* 0x00000070 */ +#define ACDCDIG_ALC2_NGVALID_SHIFT (7U) +#define ACDCDIG_ALC2_NGVALID_MASK (0x1U << ACDCDIG_ALC2_NGVALID_SHIFT) /* 0x00000080 */ +/* ADCNG */ +#define ACDCDIG_ADCNG_OFFSET (0x3CU) +#define ACDCDIG_ADCNG_NGDLY_SHIFT (0U) +#define ACDCDIG_ADCNG_NGDLY_MASK (0x3U << ACDCDIG_ADCNG_NGDLY_SHIFT) /* 0x00000003 */ +#define ACDCDIG_ADCNG_NGGATE_SHIFT (2U) +#define ACDCDIG_ADCNG_NGGATE_MASK (0x7U << ACDCDIG_ADCNG_NGGATE_SHIFT) /* 0x0000001C */ +#define ACDCDIG_ADCNG_NGBOOST_SHIFT (5U) +#define ACDCDIG_ADCNG_NGBOOST_MASK (0x1U << ACDCDIG_ADCNG_NGBOOST_SHIFT) /* 0x00000020 */ +#define ACDCDIG_ADCNG_NGEN_SHIFT (6U) +#define ACDCDIG_ADCNG_NGEN_MASK (0x1U << ACDCDIG_ADCNG_NGEN_SHIFT) /* 0x00000040 */ +#define ACDCDIG_ADCNG_NGCHL_SHIFT (7U) +#define ACDCDIG_ADCNG_NGCHL_MASK (0x1U << ACDCDIG_ADCNG_NGCHL_SHIFT) /* 0x00000080 */ +/* HPFCTRL */ +#define ACDCDIG_HPFCTRL_OFFSET (0x40U) +#define ACDCDIG_HPFCTRL_HPFCF_SHIFT (4U) +#define ACDCDIG_HPFCTRL_HPFCF_MASK (0x3U << ACDCDIG_HPFCTRL_HPFCF_SHIFT) /* 0x00000030 */ +#define ACDCDIG_HPFCTRL_HPFRE_SHIFT (6U) +#define ACDCDIG_HPFCTRL_HPFRE_MASK (0x1U << ACDCDIG_HPFCTRL_HPFRE_SHIFT) /* 0x00000040 */ +#define ACDCDIG_HPFCTRL_HPFLE_SHIFT (7U) +#define ACDCDIG_HPFCTRL_HPFLE_MASK (0x1U << ACDCDIG_HPFCTRL_HPFLE_SHIFT) /* 0x00000080 */ +/* ADCRVOLL */ +#define ACDCDIG_ADCRVOLL_OFFSET (0x44U) +#define ACDCDIG_ADCRVOLL (0x0U) +#define ACDCDIG_ADCRVOLL_ADCRLV_SHIFT (0U) +#define ACDCDIG_ADCRVOLL_ADCRLV_MASK (0x1U << ACDCDIG_ADCRVOLL_ADCRLV_SHIFT) /* 0x00000001 */ +/* ADCRVOLR */ +#define ACDCDIG_ADCRVOLR_OFFSET (0x48U) +#define ACDCDIG_ADCRVOLR (0x0U) +#define ACDCDIG_ADCRVOLR_ADCRRV_SHIFT (0U) +#define ACDCDIG_ADCRVOLR_ADCRRV_MASK (0x1U << ACDCDIG_ADCRVOLR_ADCRRV_SHIFT) /* 0x00000001 */ +/* PGACFG */ +#define ACDCDIG_PGACFG_OFFSET (0x4CU) +#define ACDCDIG_PGACFG_PGA_R_DEC_SHIFT (0U) +#define ACDCDIG_PGACFG_PGA_R_DEC_MASK (0x3U << ACDCDIG_PGACFG_PGA_R_DEC_SHIFT) /* 0x00000003 */ +#define ACDCDIG_PGACFG_PGA_L_DEC_SHIFT (2U) +#define ACDCDIG_PGACFG_PGA_L_DEC_MASK (0x3U << ACDCDIG_PGACFG_PGA_L_DEC_SHIFT) /* 0x0000000C */ +#define ACDCDIG_PGACFG_PGA_R_PD_SHIFT (4U) +#define ACDCDIG_PGACFG_PGA_R_PD_MASK (0x1U << ACDCDIG_PGACFG_PGA_R_PD_SHIFT) /* 0x00000010 */ +#define ACDCDIG_PGACFG_PGA_L_PD_SHIFT (5U) +#define ACDCDIG_PGACFG_PGA_L_PD_MASK (0x1U << ACDCDIG_PGACFG_PGA_L_PD_SHIFT) /* 0x00000020 */ +#define ACDCDIG_PGACFG_PGA_CHOP_EN_SHIFT (6U) +#define ACDCDIG_PGACFG_PGA_CHOP_EN_MASK (0x1U << ACDCDIG_PGACFG_PGA_CHOP_EN_SHIFT) /* 0x00000040 */ +/* PGAGAINL */ +#define ACDCDIG_PGAGAINL_OFFSET (0x50U) +#define ACDCDIG_PGAGAINL_PGA_GAIN_L_SHIFT (0U) +#define ACDCDIG_PGAGAINL_PGA_GAIN_L_MASK (0x1FU << ACDCDIG_PGAGAINL_PGA_GAIN_L_SHIFT) /* 0x0000001F */ +/* PGAGAINR */ +#define ACDCDIG_PGAGAINR_OFFSET (0x54U) +#define ACDCDIG_PGAGAINR_PGA_GAIN_R_SHIFT (0U) +#define ACDCDIG_PGAGAINR_PGA_GAIN_R_MASK (0x1FU << ACDCDIG_PGAGAINR_PGA_GAIN_R_SHIFT) /* 0x0000001F */ +/* LILMT1 */ +#define ACDCDIG_LILMT1_OFFSET (0x58U) +#define ACDCDIG_LILMT1_MIN_LILMT_SHIFT (0U) +#define ACDCDIG_LILMT1_MIN_LILMT_MASK (0x7U << ACDCDIG_LILMT1_MIN_LILMT_SHIFT) /* 0x00000007 */ +#define ACDCDIG_LILMT1_MAX_LILMT_SHIFT (4U) +#define ACDCDIG_LILMT1_MAX_LILMT_MASK (0x7U << ACDCDIG_LILMT1_MAX_LILMT_SHIFT) /* 0x00000070 */ +#define ACDCDIG_LILMT1_LMT_EN_SHIFT (7U) +#define ACDCDIG_LILMT1_LMT_EN_MASK (0x1U << ACDCDIG_LILMT1_LMT_EN_SHIFT) /* 0x00000080 */ +/* LILMT2 */ +#define ACDCDIG_LILMT2_OFFSET (0x5CU) +#define ACDCDIG_LILMT2_RLS_RATE_SHIFT (0U) +#define ACDCDIG_LILMT2_RLS_RATE_MASK (0xFU << ACDCDIG_LILMT2_RLS_RATE_SHIFT) /* 0x0000000F */ +#define ACDCDIG_LILMT2_ATK_RATE_SHIFT (4U) +#define ACDCDIG_LILMT2_ATK_RATE_MASK (0xFU << ACDCDIG_LILMT2_ATK_RATE_SHIFT) /* 0x000000F0 */ +/* LILMTNG1 */ +#define ACDCDIG_LILMTNG1_OFFSET (0x60U) +#define ACDCDIG_LILMTNG1_NGDLY_LI_SHIFT (0U) +#define ACDCDIG_LILMTNG1_NGDLY_LI_MASK (0x3U << ACDCDIG_LILMTNG1_NGDLY_LI_SHIFT) /* 0x00000003 */ +#define ACDCDIG_LILMTNG1_NGGATE_LI_SHIFT (2U) +#define ACDCDIG_LILMTNG1_NGGATE_LI_MASK (0x7U << ACDCDIG_LILMTNG1_NGGATE_LI_SHIFT) /* 0x0000001C */ +#define ACDCDIG_LILMTNG1_NGBOOST_LI_SHIFT (5U) +#define ACDCDIG_LILMTNG1_NGBOOST_LI_MASK (0x1U << ACDCDIG_LILMTNG1_NGBOOST_LI_SHIFT) /* 0x00000020 */ +#define ACDCDIG_LILMTNG1_NGEN_LI_SHIFT (6U) +#define ACDCDIG_LILMTNG1_NGEN_LI_MASK (0x1U << ACDCDIG_LILMTNG1_NGEN_LI_SHIFT) /* 0x00000040 */ +#define ACDCDIG_LILMTNG1_NGCHL_LI_SHIFT (7U) +#define ACDCDIG_LILMTNG1_NGCHL_LI_MASK (0x1U << ACDCDIG_LILMTNG1_NGCHL_LI_SHIFT) /* 0x00000080 */ +/* LILMTNG2 */ +#define ACDCDIG_LILMTNG2_OFFSET (0x64U) +#define ACDCDIG_LILMTNG2 (0x0U) +#define ACDCDIG_LILMTNG2_NGVALID_LI_SHIFT (0U) +#define ACDCDIG_LILMTNG2_NGVALID_LI_MASK (0x1U << ACDCDIG_LILMTNG2_NGVALID_LI_SHIFT) /* 0x00000001 */ +/* PDMCTRL */ +#define ACDCDIG_PDMCTRL_OFFSET (0x68U) +#define ACDCDIG_PDMCTRL_PDM_LR_SEL_SHIFT (0U) +#define ACDCDIG_PDMCTRL_PDM_LR_SEL_MASK (0x1U << ACDCDIG_PDMCTRL_PDM_LR_SEL_SHIFT) /* 0x00000001 */ +#define ACDCDIG_PDMCTRL_PDM_MODE_SHIFT (1U) +#define ACDCDIG_PDMCTRL_PDM_MODE_MASK (0x1U << ACDCDIG_PDMCTRL_PDM_MODE_SHIFT) /* 0x00000002 */ +#define ACDCDIG_PDMCTRL_PDM_EN_SHIFT (2U) +#define ACDCDIG_PDMCTRL_PDM_EN_MASK (0x1U << ACDCDIG_PDMCTRL_PDM_EN_SHIFT) /* 0x00000004 */ +/* I2SCKM */ +#define ACDCDIG_I2SCKM_OFFSET (0x6CU) +#define ACDCDIG_I2SCKM_I2SMST_SHIFT (0U) +#define ACDCDIG_I2SCKM_I2SMST_MASK (0x1U << ACDCDIG_I2SCKM_I2SMST_SHIFT) /* 0x00000001 */ +#define ACDCDIG_I2SCKM_SCK_P_SHIFT (1U) +#define ACDCDIG_I2SCKM_SCK_P_MASK (0x1U << ACDCDIG_I2SCKM_SCK_P_SHIFT) /* 0x00000002 */ +/* I2SDIV */ +#define ACDCDIG_I2SDIV_OFFSET (0x70U) +#define ACDCDIG_I2SDIV_SCKDIV_SHIFT (0U) +#define ACDCDIG_I2SDIV_SCKDIV_MASK (0xFFU << ACDCDIG_I2SDIV_SCKDIV_SHIFT) /* 0x000000FF */ +/* I2STXCR0 */ +#define ACDCDIG_I2STXCR0_OFFSET (0x74U) +#define ACDCDIG_I2STXCR0_TXRL_P_SHIFT (0U) +#define ACDCDIG_I2STXCR0_TXRL_P_MASK (0x1U << ACDCDIG_I2STXCR0_TXRL_P_SHIFT) /* 0x00000001 */ +#define ACDCDIG_I2STXCR0_SCKDTX_SHIFT (1U) +#define ACDCDIG_I2STXCR0_SCKDTX_MASK (0x3U << ACDCDIG_I2STXCR0_SCKDTX_SHIFT) /* 0x00000006 */ +/* I2STXCR1 */ +#define ACDCDIG_I2STXCR1_OFFSET (0x78U) +#define ACDCDIG_I2STXCR1_LSB_SHIFT (0U) +#define ACDCDIG_I2STXCR1_LSB_MASK (0x1U << ACDCDIG_I2STXCR1_LSB_SHIFT) /* 0x00000001 */ +#define ACDCDIG_I2STXCR1_EXRL_SHIFT (1U) +#define ACDCDIG_I2STXCR1_EXRL_MASK (0x1U << ACDCDIG_I2STXCR1_EXRL_SHIFT) /* 0x00000002 */ +#define ACDCDIG_I2STXCR1_IBM_SHIFT (2U) +#define ACDCDIG_I2STXCR1_IBM_MASK (0x3U << ACDCDIG_I2STXCR1_IBM_SHIFT) /* 0x0000000C */ +#define ACDCDIG_I2STXCR1_PBM_SHIFT (4U) +#define ACDCDIG_I2STXCR1_PBM_MASK (0x3U << ACDCDIG_I2STXCR1_PBM_SHIFT) /* 0x00000030 */ +#define ACDCDIG_I2STXCR1_TFS_SHIFT (6U) +#define ACDCDIG_I2STXCR1_TFS_MASK (0x1U << ACDCDIG_I2STXCR1_TFS_SHIFT) /* 0x00000040 */ +/* I2STXCR2 */ +#define ACDCDIG_I2STXCR2_OFFSET (0x7CU) +#define ACDCDIG_I2STXCR2_VDW_SHIFT (0U) +#define ACDCDIG_I2STXCR2_VDW_MASK (0x1FU << ACDCDIG_I2STXCR2_VDW_SHIFT) /* 0x0000001F */ +/* I2STXCMD */ +#define ACDCDIG_I2STXCMD_OFFSET (0x80U) +#define ACDCDIG_I2STXCMD_RCNT_SHIFT (0U) +#define ACDCDIG_I2STXCMD_RCNT_MASK (0x3FU << ACDCDIG_I2STXCMD_RCNT_SHIFT) /* 0x0000003F */ +#define ACDCDIG_I2STXCMD_TXC_SHIFT (6U) +#define ACDCDIG_I2STXCMD_TXC_MASK (0x1U << ACDCDIG_I2STXCMD_TXC_SHIFT) /* 0x00000040 */ +#define ACDCDIG_I2STXCMD_TXS_SHIFT (7U) +#define ACDCDIG_I2STXCMD_TXS_MASK (0x1U << ACDCDIG_I2STXCMD_TXS_SHIFT) /* 0x00000080 */ +/* VERSION */ +#define ACDCDIG_VERSION_OFFSET (0x84U) +#define ACDCDIG_VERSION (0x1U) +#define ACDCDIG_VERSION_VER_SHIFT (0U) +#define ACDCDIG_VERSION_VER_MASK (0xFFU << ACDCDIG_VERSION_VER_SHIFT) /* 0x000000FF */ +/******************************************UART******************************************/ +/* RBR */ +#define UART_RBR_OFFSET (0x0U) +#define UART_RBR_DATA_INPUT_SHIFT (0U) +#define UART_RBR_DATA_INPUT_MASK (0xFFU << UART_RBR_DATA_INPUT_SHIFT) /* 0x000000FF */ +/* THR */ +#define UART_THR_OFFSET (0x0U) +#define UART_THR_DATA_OUTPUT_SHIFT (0U) +#define UART_THR_DATA_OUTPUT_MASK (0xFFU << UART_THR_DATA_OUTPUT_SHIFT) /* 0x000000FF */ +/* DLL */ +#define UART_DLL_OFFSET (0x0U) +#define UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT (0U) +#define UART_DLL_BAUD_RATE_DIVISOR_L_MASK (0xFFU << UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT) /* 0x000000FF */ +/* DLH */ +#define UART_DLH_OFFSET (0x4U) +#define UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT (0U) +#define UART_DLH_BAUD_RATE_DIVISOR_H_MASK (0xFFU << UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT) /* 0x000000FF */ +/* IER */ +#define UART_IER_OFFSET (0x4U) +#define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT (0U) +#define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_MASK (0x1U << UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT) /* 0x00000001 */ +#define UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT (1U) +#define UART_IER_TRANS_HOLD_EMPTY_INT_EN_MASK (0x1U << UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT) /* 0x00000002 */ +#define UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT (2U) +#define UART_IER_RECEIVE_LINE_STATUS_INT_EN_MASK (0x1U << UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT) /* 0x00000004 */ +#define UART_IER_MODEM_STATUS_INT_EN_SHIFT (3U) +#define UART_IER_MODEM_STATUS_INT_EN_MASK (0x1U << UART_IER_MODEM_STATUS_INT_EN_SHIFT) /* 0x00000008 */ +#define UART_IER_PROG_THRE_INT_EN_SHIFT (7U) +#define UART_IER_PROG_THRE_INT_EN_MASK (0x1U << UART_IER_PROG_THRE_INT_EN_SHIFT) /* 0x00000080 */ +/* IIR */ +#define UART_IIR_OFFSET (0x8U) +#define UART_IIR (0x0U) +#define UART_IIR_INT_ID_SHIFT (0U) +#define UART_IIR_INT_ID_MASK (0xFU << UART_IIR_INT_ID_SHIFT) /* 0x0000000F */ +#define UART_IIR_FIFOS_EN_SHIFT (6U) +#define UART_IIR_FIFOS_EN_MASK (0x3U << UART_IIR_FIFOS_EN_SHIFT) /* 0x000000C0 */ +/* FCR */ +#define UART_FCR_OFFSET (0x8U) +#define UART_FCR_FIFO_EN_SHIFT (0U) +#define UART_FCR_FIFO_EN_MASK (0x1U << UART_FCR_FIFO_EN_SHIFT) /* 0x00000001 */ +#define UART_FCR_RCVR_FIFO_RESET_SHIFT (1U) +#define UART_FCR_RCVR_FIFO_RESET_MASK (0x1U << UART_FCR_RCVR_FIFO_RESET_SHIFT) /* 0x00000002 */ +#define UART_FCR_XMIT_FIFO_RESET_SHIFT (2U) +#define UART_FCR_XMIT_FIFO_RESET_MASK (0x1U << UART_FCR_XMIT_FIFO_RESET_SHIFT) /* 0x00000004 */ +#define UART_FCR_DMA_MODE_SHIFT (3U) +#define UART_FCR_DMA_MODE_MASK (0x1U << UART_FCR_DMA_MODE_SHIFT) /* 0x00000008 */ +#define UART_FCR_TX_EMPTY_TRIGGER_SHIFT (4U) +#define UART_FCR_TX_EMPTY_TRIGGER_MASK (0x3U << UART_FCR_TX_EMPTY_TRIGGER_SHIFT) /* 0x00000030 */ +#define UART_FCR_RCVR_TRIGGER_SHIFT (6U) +#define UART_FCR_RCVR_TRIGGER_MASK (0x3U << UART_FCR_RCVR_TRIGGER_SHIFT) /* 0x000000C0 */ +/* LCR */ +#define UART_LCR_OFFSET (0xCU) +#define UART_LCR_DATA_LENGTH_SEL_SHIFT (0U) +#define UART_LCR_DATA_LENGTH_SEL_MASK (0x3U << UART_LCR_DATA_LENGTH_SEL_SHIFT) /* 0x00000003 */ +#define UART_LCR_STOP_BITS_NUM_SHIFT (2U) +#define UART_LCR_STOP_BITS_NUM_MASK (0x1U << UART_LCR_STOP_BITS_NUM_SHIFT) /* 0x00000004 */ +#define UART_LCR_PARITY_EN_SHIFT (3U) +#define UART_LCR_PARITY_EN_MASK (0x1U << UART_LCR_PARITY_EN_SHIFT) /* 0x00000008 */ +#define UART_LCR_EVEN_PARITY_SEL_SHIFT (4U) +#define UART_LCR_EVEN_PARITY_SEL_MASK (0x1U << UART_LCR_EVEN_PARITY_SEL_SHIFT) /* 0x00000010 */ +#define UART_LCR_BREAK_CTRL_SHIFT (6U) +#define UART_LCR_BREAK_CTRL_MASK (0x1U << UART_LCR_BREAK_CTRL_SHIFT) /* 0x00000040 */ +#define UART_LCR_DIV_LAT_ACCESS_SHIFT (7U) +#define UART_LCR_DIV_LAT_ACCESS_MASK (0x1U << UART_LCR_DIV_LAT_ACCESS_SHIFT) /* 0x00000080 */ +/* MCR */ +#define UART_MCR_OFFSET (0x10U) +#define UART_MCR_DATA_TERMINAL_READY_SHIFT (0U) +#define UART_MCR_DATA_TERMINAL_READY_MASK (0x1U << UART_MCR_DATA_TERMINAL_READY_SHIFT) /* 0x00000001 */ +#define UART_MCR_REQ_TO_SEND_SHIFT (1U) +#define UART_MCR_REQ_TO_SEND_MASK (0x1U << UART_MCR_REQ_TO_SEND_SHIFT) /* 0x00000002 */ +#define UART_MCR_OUT1_SHIFT (2U) +#define UART_MCR_OUT1_MASK (0x1U << UART_MCR_OUT1_SHIFT) /* 0x00000004 */ +#define UART_MCR_OUT2_SHIFT (3U) +#define UART_MCR_OUT2_MASK (0x1U << UART_MCR_OUT2_SHIFT) /* 0x00000008 */ +#define UART_MCR_LOOPBACK_SHIFT (4U) +#define UART_MCR_LOOPBACK_MASK (0x1U << UART_MCR_LOOPBACK_SHIFT) /* 0x00000010 */ +#define UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT (5U) +#define UART_MCR_AUTO_FLOW_CTRL_EN_MASK (0x1U << UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT) /* 0x00000020 */ +#define UART_MCR_SIR_MODE_EN_SHIFT (6U) +#define UART_MCR_SIR_MODE_EN_MASK (0x1U << UART_MCR_SIR_MODE_EN_SHIFT) /* 0x00000040 */ +/* LSR */ +#define UART_LSR_OFFSET (0x14U) +#define UART_LSR (0x0U) +#define UART_LSR_DATA_READY_SHIFT (0U) +#define UART_LSR_DATA_READY_MASK (0x1U << UART_LSR_DATA_READY_SHIFT) /* 0x00000001 */ +#define UART_LSR_OVERRUN_ERROR_SHIFT (1U) +#define UART_LSR_OVERRUN_ERROR_MASK (0x1U << UART_LSR_OVERRUN_ERROR_SHIFT) /* 0x00000002 */ +#define UART_LSR_PARITY_EROR_SHIFT (2U) +#define UART_LSR_PARITY_EROR_MASK (0x1U << UART_LSR_PARITY_EROR_SHIFT) /* 0x00000004 */ +#define UART_LSR_FRAMING_ERROR_SHIFT (3U) +#define UART_LSR_FRAMING_ERROR_MASK (0x1U << UART_LSR_FRAMING_ERROR_SHIFT) /* 0x00000008 */ +#define UART_LSR_BREAK_INT_SHIFT (4U) +#define UART_LSR_BREAK_INT_MASK (0x1U << UART_LSR_BREAK_INT_SHIFT) /* 0x00000010 */ +#define UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT (5U) +#define UART_LSR_TRANS_HOLD_REG_EMPTY_MASK (0x1U << UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT) /* 0x00000020 */ +#define UART_LSR_TRANS_EMPTY_SHIFT (6U) +#define UART_LSR_TRANS_EMPTY_MASK (0x1U << UART_LSR_TRANS_EMPTY_SHIFT) /* 0x00000040 */ +#define UART_LSR_RECEIVER_FIFO_ERROR_SHIFT (7U) +#define UART_LSR_RECEIVER_FIFO_ERROR_MASK (0x1U << UART_LSR_RECEIVER_FIFO_ERROR_SHIFT) /* 0x00000080 */ +/* MSR */ +#define UART_MSR_OFFSET (0x18U) +#define UART_MSR (0x0U) +#define UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT (0U) +#define UART_MSR_DELTA_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT) /* 0x00000001 */ +#define UART_MSR_DELTA_DATA_SET_READY_SHIFT (1U) +#define UART_MSR_DELTA_DATA_SET_READY_MASK (0x1U << UART_MSR_DELTA_DATA_SET_READY_SHIFT) /* 0x00000002 */ +#define UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT (2U) +#define UART_MSR_TRAILING_EDGE_RING_INDICATOR_MASK (0x1U << UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT) /* 0x00000004 */ +#define UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT (3U) +#define UART_MSR_DELTA_DATA_CARRIER_DETECT_MASK (0x1U << UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT) /* 0x00000008 */ +#define UART_MSR_CLEAR_TO_SEND_SHIFT (4U) +#define UART_MSR_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_CLEAR_TO_SEND_SHIFT) /* 0x00000010 */ +#define UART_MSR_DATA_SET_READY_SHIFT (5U) +#define UART_MSR_DATA_SET_READY_MASK (0x1U << UART_MSR_DATA_SET_READY_SHIFT) /* 0x00000020 */ +#define UART_MSR_RING_INDICATOR_SHIFT (6U) +#define UART_MSR_RING_INDICATOR_MASK (0x1U << UART_MSR_RING_INDICATOR_SHIFT) /* 0x00000040 */ +#define UART_MSR_DATA_CARRIOR_DETECT_SHIFT (7U) +#define UART_MSR_DATA_CARRIOR_DETECT_MASK (0x1U << UART_MSR_DATA_CARRIOR_DETECT_SHIFT) /* 0x00000080 */ +/* SCR */ +#define UART_SCR_OFFSET (0x1CU) +#define UART_SCR_TEMP_STORE_SPACE_SHIFT (0U) +#define UART_SCR_TEMP_STORE_SPACE_MASK (0xFFU << UART_SCR_TEMP_STORE_SPACE_SHIFT) /* 0x000000FF */ +/* SRBR */ +#define UART_SRBR_OFFSET (0x30U) +#define UART_SRBR (0x0U) +#define UART_SRBR_SHADOW_RBR_SHIFT (0U) +#define UART_SRBR_SHADOW_RBR_MASK (0xFFU << UART_SRBR_SHADOW_RBR_SHIFT) /* 0x000000FF */ +/* STHR */ +#define UART_STHR_OFFSET (0x30U) +#define UART_STHR (0x0U) +#define UART_STHR_SHADOW_THR_SHIFT (0U) +#define UART_STHR_SHADOW_THR_MASK (0xFFU << UART_STHR_SHADOW_THR_SHIFT) /* 0x000000FF */ +/* FAR */ +#define UART_FAR_OFFSET (0x70U) +#define UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT (0U) +#define UART_FAR_FIFO_ACCESS_TEST_EN_MASK (0x1U << UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT) /* 0x00000001 */ +/* TFR */ +#define UART_TFR_OFFSET (0x74U) +#define UART_TFR (0x0U) +#define UART_TFR_TRANS_FIFO_READ_SHIFT (0U) +#define UART_TFR_TRANS_FIFO_READ_MASK (0xFFU << UART_TFR_TRANS_FIFO_READ_SHIFT) /* 0x000000FF */ +/* RFW */ +#define UART_RFW_OFFSET (0x78U) +#define UART_RFW_RECEIVE_FIFO_WRITE_SHIFT (0U) +#define UART_RFW_RECEIVE_FIFO_WRITE_MASK (0xFFU << UART_RFW_RECEIVE_FIFO_WRITE_SHIFT) /* 0x000000FF */ +#define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT (8U) +#define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT) /* 0x00000100 */ +#define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT (9U) +#define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT) /* 0x00000200 */ +/* USR */ +#define UART_USR_OFFSET (0x7CU) +#define UART_USR (0x0U) +#define UART_USR_UART_BUSY_SHIFT (0U) +#define UART_USR_UART_BUSY_MASK (0x1U << UART_USR_UART_BUSY_SHIFT) /* 0x00000001 */ +#define UART_USR_TRANS_FIFO_NOT_FULL_SHIFT (1U) +#define UART_USR_TRANS_FIFO_NOT_FULL_MASK (0x1U << UART_USR_TRANS_FIFO_NOT_FULL_SHIFT) /* 0x00000002 */ +#define UART_USR_TRASN_FIFO_EMPTY_SHIFT (2U) +#define UART_USR_TRASN_FIFO_EMPTY_MASK (0x1U << UART_USR_TRASN_FIFO_EMPTY_SHIFT) /* 0x00000004 */ +#define UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT (3U) +#define UART_USR_RECEIVE_FIFO_NOT_EMPTY_MASK (0x1U << UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT) /* 0x00000008 */ +#define UART_USR_RECEIVE_FIFO_FULL_SHIFT (4U) +#define UART_USR_RECEIVE_FIFO_FULL_MASK (0x1U << UART_USR_RECEIVE_FIFO_FULL_SHIFT) /* 0x00000010 */ +/* TFL */ +#define UART_TFL_OFFSET (0x80U) +#define UART_TFL_TRANS_FIFO_LEVEL_SHIFT (0U) +#define UART_TFL_TRANS_FIFO_LEVEL_MASK (0x1FU << UART_TFL_TRANS_FIFO_LEVEL_SHIFT) /* 0x0000001F */ +/* RFL */ +#define UART_RFL_OFFSET (0x84U) +#define UART_RFL (0x0U) +#define UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT (0U) +#define UART_RFL_RECEIVE_FIFO_LEVEL_MASK (0x1FU << UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT) /* 0x0000001F */ +/* SRR */ +#define UART_SRR_OFFSET (0x88U) +#define UART_SRR_UART_RESET_SHIFT (0U) +#define UART_SRR_UART_RESET_MASK (0x1U << UART_SRR_UART_RESET_SHIFT) /* 0x00000001 */ +#define UART_SRR_RCVR_FIFO_RESET_SHIFT (1U) +#define UART_SRR_RCVR_FIFO_RESET_MASK (0x1U << UART_SRR_RCVR_FIFO_RESET_SHIFT) /* 0x00000002 */ +#define UART_SRR_XMIT_FIFO_RESET_SHIFT (2U) +#define UART_SRR_XMIT_FIFO_RESET_MASK (0x1U << UART_SRR_XMIT_FIFO_RESET_SHIFT) /* 0x00000004 */ +/* SRTS */ +#define UART_SRTS_OFFSET (0x8CU) +#define UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT (0U) +#define UART_SRTS_SHADOW_REQ_TO_SEND_MASK (0x1U << UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT) /* 0x00000001 */ +/* SBCR */ +#define UART_SBCR_OFFSET (0x90U) +#define UART_SBCR_SHADOW_BREAK_CTRL_SHIFT (0U) +#define UART_SBCR_SHADOW_BREAK_CTRL_MASK (0x1U << UART_SBCR_SHADOW_BREAK_CTRL_SHIFT) /* 0x00000001 */ +/* SDMAM */ +#define UART_SDMAM_OFFSET (0x94U) +#define UART_SDMAM_SHADOW_DMA_MODE_SHIFT (0U) +#define UART_SDMAM_SHADOW_DMA_MODE_MASK (0x1U << UART_SDMAM_SHADOW_DMA_MODE_SHIFT) /* 0x00000001 */ +/* SFE */ +#define UART_SFE_OFFSET (0x98U) +#define UART_SFE_SHADOW_FIFO_EN_SHIFT (0U) +#define UART_SFE_SHADOW_FIFO_EN_MASK (0x1U << UART_SFE_SHADOW_FIFO_EN_SHIFT) /* 0x00000001 */ +/* SRT */ +#define UART_SRT_OFFSET (0x9CU) +#define UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT (0U) +#define UART_SRT_SHADOW_RCVR_TRIGGER_MASK (0x1U << UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT) /* 0x00000001 */ +/* STET */ +#define UART_STET_OFFSET (0xA0U) +#define UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT (0U) +#define UART_STET_SHADOW_TX_EMPTY_TRIGGER_MASK (0x1U << UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT) /* 0x00000001 */ +/* HTX */ +#define UART_HTX_OFFSET (0xA4U) +#define UART_HTX_HALT_TX_EN_SHIFT (0U) +#define UART_HTX_HALT_TX_EN_MASK (0x1U << UART_HTX_HALT_TX_EN_SHIFT) /* 0x00000001 */ +/* DMASA */ +#define UART_DMASA_OFFSET (0xA8U) +#define UART_DMASA_DMA_SOFTWARE_ACK_SHIFT (0U) +#define UART_DMASA_DMA_SOFTWARE_ACK_MASK (0x1U << UART_DMASA_DMA_SOFTWARE_ACK_SHIFT) /* 0x00000001 */ +/* CPR */ +#define UART_CPR_OFFSET (0xF4U) +#define UART_CPR (0x0U) +#define UART_CPR_APB_DATA_WIDTH_SHIFT (0U) +#define UART_CPR_APB_DATA_WIDTH_MASK (0x3U << UART_CPR_APB_DATA_WIDTH_SHIFT) /* 0x00000003 */ +#define UART_CPR_AFCE_MODE_SHIFT (4U) +#define UART_CPR_AFCE_MODE_MASK (0x1U << UART_CPR_AFCE_MODE_SHIFT) /* 0x00000010 */ +#define UART_CPR_THRE_MODE_SHIFT (5U) +#define UART_CPR_THRE_MODE_MASK (0x1U << UART_CPR_THRE_MODE_SHIFT) /* 0x00000020 */ +#define UART_CPR_SIR_MODE_SHIFT (6U) +#define UART_CPR_SIR_MODE_MASK (0x1U << UART_CPR_SIR_MODE_SHIFT) /* 0x00000040 */ +#define UART_CPR_SIR_LP_MODE_SHIFT (7U) +#define UART_CPR_SIR_LP_MODE_MASK (0x1U << UART_CPR_SIR_LP_MODE_SHIFT) /* 0x00000080 */ +#define UART_CPR_NEW_FEAT_SHIFT (8U) +#define UART_CPR_NEW_FEAT_MASK (0x1U << UART_CPR_NEW_FEAT_SHIFT) /* 0x00000100 */ +#define UART_CPR_FIFO_ACCESS_SHIFT (9U) +#define UART_CPR_FIFO_ACCESS_MASK (0x1U << UART_CPR_FIFO_ACCESS_SHIFT) /* 0x00000200 */ +#define UART_CPR_FIFO_STAT_SHIFT (10U) +#define UART_CPR_FIFO_STAT_MASK (0x1U << UART_CPR_FIFO_STAT_SHIFT) /* 0x00000400 */ +#define UART_CPR_SHADOW_SHIFT (11U) +#define UART_CPR_SHADOW_MASK (0x1U << UART_CPR_SHADOW_SHIFT) /* 0x00000800 */ +#define UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT (12U) +#define UART_CPR_UART_ADD_ENCODED_PARAMS_MASK (0x1U << UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT) /* 0x00001000 */ +#define UART_CPR_DMA_EXTRA_SHIFT (13U) +#define UART_CPR_DMA_EXTRA_MASK (0x1U << UART_CPR_DMA_EXTRA_SHIFT) /* 0x00002000 */ +#define UART_CPR_FIFO_MODE_SHIFT (16U) +#define UART_CPR_FIFO_MODE_MASK (0xFFU << UART_CPR_FIFO_MODE_SHIFT) /* 0x00FF0000 */ +/* UCV */ +#define UART_UCV_OFFSET (0xF8U) +#define UART_UCV (0x330372AU) +#define UART_UCV_VER_SHIFT (0U) +#define UART_UCV_VER_MASK (0xFFFFFFFFU << UART_UCV_VER_SHIFT) /* 0xFFFFFFFF */ +/* CTR */ +#define UART_CTR_OFFSET (0xFCU) +#define UART_CTR (0x44570110U) +#define UART_CTR_PERIPHERAL_ID_SHIFT (0U) +#define UART_CTR_PERIPHERAL_ID_MASK (0xFFFFFFFFU << UART_CTR_PERIPHERAL_ID_SHIFT) /* 0xFFFFFFFF */ +/******************************************PWM*******************************************/ +/* PWM0_CNT */ +#define PWM_PWM0_CNT_OFFSET (0x0U) +#define PWM_PWM0_CNT (0x0U) +#define PWM_PWM0_CNT_CNT_SHIFT (0U) +#define PWM_PWM0_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM0_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM0_PERIOD_HPR */ +#define PWM_PWM0_PERIOD_HPR_OFFSET (0x4U) +#define PWM_PWM0_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM0_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM0_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM0_DUTY_LPR */ +#define PWM_PWM0_DUTY_LPR_OFFSET (0x8U) +#define PWM_PWM0_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM0_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM0_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM0_CTRL */ +#define PWM_PWM0_CTRL_OFFSET (0xCU) +#define PWM_PWM0_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM0_CTRL_PWM_EN_MASK (0x1U << PWM_PWM0_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM0_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM0_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM0_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM0_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM0_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM0_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM0_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM0_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM0_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM0_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM0_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM0_CTRL_CONLOCK_MASK (0x1U << PWM_PWM0_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM0_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM0_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM0_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM0_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM0_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM0_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM0_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM0_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM0_CTRL_PRESCALE_MASK (0x7U << PWM_PWM0_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM0_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM0_CTRL_SCALE_MASK (0xFFU << PWM_PWM0_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM0_CTRL_RPT_SHIFT (24U) +#define PWM_PWM0_CTRL_RPT_MASK (0xFFU << PWM_PWM0_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* PWM1_CNT */ +#define PWM_PWM1_CNT_OFFSET (0x10U) +#define PWM_PWM1_CNT (0x0U) +#define PWM_PWM1_CNT_CNT_SHIFT (0U) +#define PWM_PWM1_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM1_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM1_PERIOD_HPR */ +#define PWM_PWM1_PERIOD_HPR_OFFSET (0x14U) +#define PWM_PWM1_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM1_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM1_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM1_DUTY_LPR */ +#define PWM_PWM1_DUTY_LPR_OFFSET (0x18U) +#define PWM_PWM1_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM1_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM1_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM1_CTRL */ +#define PWM_PWM1_CTRL_OFFSET (0x1CU) +#define PWM_PWM1_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM1_CTRL_PWM_EN_MASK (0x1U << PWM_PWM1_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM1_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM1_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM1_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM1_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM1_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM1_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM1_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM1_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM1_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM1_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM1_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM1_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM1_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM1_CTRL_CONLOCK_MASK (0x1U << PWM_PWM1_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM1_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM1_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM1_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM1_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM1_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM1_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM1_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM1_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM1_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM1_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM1_CTRL_PRESCALE_MASK (0x7U << PWM_PWM1_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM1_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM1_CTRL_SCALE_MASK (0xFFU << PWM_PWM1_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM1_CTRL_RPT_SHIFT (24U) +#define PWM_PWM1_CTRL_RPT_MASK (0xFFU << PWM_PWM1_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* PWM2_CNT */ +#define PWM_PWM2_CNT_OFFSET (0x20U) +#define PWM_PWM2_CNT (0x0U) +#define PWM_PWM2_CNT_CNT_SHIFT (0U) +#define PWM_PWM2_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM2_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM2_PERIOD_HPR */ +#define PWM_PWM2_PERIOD_HPR_OFFSET (0x24U) +#define PWM_PWM2_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM2_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM2_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM2_DUTY_LPR */ +#define PWM_PWM2_DUTY_LPR_OFFSET (0x28U) +#define PWM_PWM2_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM2_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM2_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM2_CTRL */ +#define PWM_PWM2_CTRL_OFFSET (0x2CU) +#define PWM_PWM2_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM2_CTRL_PWM_EN_MASK (0x1U << PWM_PWM2_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM2_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM2_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM2_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM2_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM2_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM2_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM2_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM2_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM2_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM2_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM2_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM2_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM2_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM2_CTRL_CONLOCK_MASK (0x1U << PWM_PWM2_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM2_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM2_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM2_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM2_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM2_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM2_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM2_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM2_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM2_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM2_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM2_CTRL_PRESCALE_MASK (0x7U << PWM_PWM2_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM2_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM2_CTRL_SCALE_MASK (0xFFU << PWM_PWM2_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM2_CTRL_RPT_SHIFT (24U) +#define PWM_PWM2_CTRL_RPT_MASK (0xFFU << PWM_PWM2_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* PWM3_CNT */ +#define PWM_PWM3_CNT_OFFSET (0x30U) +#define PWM_PWM3_CNT (0x0U) +#define PWM_PWM3_CNT_CNT_SHIFT (0U) +#define PWM_PWM3_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM3_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_PERIOD_HPR */ +#define PWM_PWM3_PERIOD_HPR_OFFSET (0x34U) +#define PWM_PWM3_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM3_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM3_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_DUTY_LPR */ +#define PWM_PWM3_DUTY_LPR_OFFSET (0x38U) +#define PWM_PWM3_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM3_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM3_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_CTRL */ +#define PWM_PWM3_CTRL_OFFSET (0x3CU) +#define PWM_PWM3_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM3_CTRL_PWM_EN_MASK (0x1U << PWM_PWM3_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM3_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM3_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM3_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM3_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM3_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM3_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM3_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM3_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM3_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM3_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM3_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM3_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM3_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM3_CTRL_CONLOCK_MASK (0x1U << PWM_PWM3_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM3_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM3_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM3_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM3_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM3_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM3_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM3_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM3_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM3_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM3_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM3_CTRL_PRESCALE_MASK (0x7U << PWM_PWM3_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM3_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM3_CTRL_SCALE_MASK (0xFFU << PWM_PWM3_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM3_CTRL_RPT_SHIFT (24U) +#define PWM_PWM3_CTRL_RPT_MASK (0xFFU << PWM_PWM3_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* INTSTS */ +#define PWM_INTSTS_OFFSET (0x40U) +#define PWM_INTSTS_CH0_INTSTS_SHIFT (0U) +#define PWM_INTSTS_CH0_INTSTS_MASK (0x1U << PWM_INTSTS_CH0_INTSTS_SHIFT) /* 0x00000001 */ +#define PWM_INTSTS_CH1_INTSTS_SHIFT (1U) +#define PWM_INTSTS_CH1_INTSTS_MASK (0x1U << PWM_INTSTS_CH1_INTSTS_SHIFT) /* 0x00000002 */ +#define PWM_INTSTS_CH2_INTSTS_SHIFT (2U) +#define PWM_INTSTS_CH2_INTSTS_MASK (0x1U << PWM_INTSTS_CH2_INTSTS_SHIFT) /* 0x00000004 */ +#define PWM_INTSTS_CH3_INTSTS_SHIFT (3U) +#define PWM_INTSTS_CH3_INTSTS_MASK (0x1U << PWM_INTSTS_CH3_INTSTS_SHIFT) /* 0x00000008 */ +#define PWM_INTSTS_CH0_PWR_INTSTS_SHIFT (4U) +#define PWM_INTSTS_CH0_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH0_PWR_INTSTS_SHIFT) /* 0x00000010 */ +#define PWM_INTSTS_CH1_PWR_INTSTS_SHIFT (5U) +#define PWM_INTSTS_CH1_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH1_PWR_INTSTS_SHIFT) /* 0x00000020 */ +#define PWM_INTSTS_CH2_PWR_INTSTS_SHIFT (6U) +#define PWM_INTSTS_CH2_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH2_PWR_INTSTS_SHIFT) /* 0x00000040 */ +#define PWM_INTSTS_CH3_PWR_INTSTS_SHIFT (7U) +#define PWM_INTSTS_CH3_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH3_PWR_INTSTS_SHIFT) /* 0x00000080 */ +#define PWM_INTSTS_CH0_POL_SHIFT (8U) +#define PWM_INTSTS_CH0_POL_MASK (0x1U << PWM_INTSTS_CH0_POL_SHIFT) /* 0x00000100 */ +#define PWM_INTSTS_CH1_POL_SHIFT (9U) +#define PWM_INTSTS_CH1_POL_MASK (0x1U << PWM_INTSTS_CH1_POL_SHIFT) /* 0x00000200 */ +#define PWM_INTSTS_CH2_POL_SHIFT (10U) +#define PWM_INTSTS_CH2_POL_MASK (0x1U << PWM_INTSTS_CH2_POL_SHIFT) /* 0x00000400 */ +#define PWM_INTSTS_CH3_POL_SHIFT (11U) +#define PWM_INTSTS_CH3_POL_MASK (0x1U << PWM_INTSTS_CH3_POL_SHIFT) /* 0x00000800 */ +/* INT_EN */ +#define PWM_INT_EN_OFFSET (0x44U) +#define PWM_INT_EN_CH0_INT_EN_SHIFT (0U) +#define PWM_INT_EN_CH0_INT_EN_MASK (0x1U << PWM_INT_EN_CH0_INT_EN_SHIFT) /* 0x00000001 */ +#define PWM_INT_EN_CH1_INT_EN_SHIFT (1U) +#define PWM_INT_EN_CH1_INT_EN_MASK (0x1U << PWM_INT_EN_CH1_INT_EN_SHIFT) /* 0x00000002 */ +#define PWM_INT_EN_CH2_INT_EN_SHIFT (2U) +#define PWM_INT_EN_CH2_INT_EN_MASK (0x1U << PWM_INT_EN_CH2_INT_EN_SHIFT) /* 0x00000004 */ +#define PWM_INT_EN_CH3_INT_EN_SHIFT (3U) +#define PWM_INT_EN_CH3_INT_EN_MASK (0x1U << PWM_INT_EN_CH3_INT_EN_SHIFT) /* 0x00000008 */ +#define PWM_INT_EN_CH0_PWR_INT_EN_SHIFT (4U) +#define PWM_INT_EN_CH0_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH0_PWR_INT_EN_SHIFT) /* 0x00000010 */ +#define PWM_INT_EN_CH1_PWR_INT_EN_SHIFT (5U) +#define PWM_INT_EN_CH1_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH1_PWR_INT_EN_SHIFT) /* 0x00000020 */ +#define PWM_INT_EN_CH2_PWR_INT_EN_SHIFT (6U) +#define PWM_INT_EN_CH2_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH2_PWR_INT_EN_SHIFT) /* 0x00000040 */ +#define PWM_INT_EN_CH3_PWR_INT_EN_SHIFT (7U) +#define PWM_INT_EN_CH3_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH3_PWR_INT_EN_SHIFT) /* 0x00000080 */ +/* FIFO_CTRL */ +#define PWM_FIFO_CTRL_OFFSET (0x50U) +#define PWM_FIFO_CTRL_FIFO_MODE_SEL_SHIFT (0U) +#define PWM_FIFO_CTRL_FIFO_MODE_SEL_MASK (0x1U << PWM_FIFO_CTRL_FIFO_MODE_SEL_SHIFT) /* 0x00000001 */ +#define PWM_FIFO_CTRL_FULL_INT_EN_SHIFT (1U) +#define PWM_FIFO_CTRL_FULL_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_FULL_INT_EN_SHIFT) /* 0x00000002 */ +#define PWM_FIFO_CTRL_OVERFLOW_INT_EN_SHIFT (2U) +#define PWM_FIFO_CTRL_OVERFLOW_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_OVERFLOW_INT_EN_SHIFT) /* 0x00000004 */ +#define PWM_FIFO_CTRL_WATERMARK_INT_EN_SHIFT (3U) +#define PWM_FIFO_CTRL_WATERMARK_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_WATERMARK_INT_EN_SHIFT) /* 0x00000008 */ +#define PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_SHIFT (4U) +#define PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_MASK (0x7U << PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_SHIFT) /* 0x00000070 */ +#define PWM_FIFO_CTRL_DMA_MODE_EN_SHIFT (8U) +#define PWM_FIFO_CTRL_DMA_MODE_EN_MASK (0x1U << PWM_FIFO_CTRL_DMA_MODE_EN_SHIFT) /* 0x00000100 */ +#define PWM_FIFO_CTRL_TIMEOUT_EN_SHIFT (9U) +#define PWM_FIFO_CTRL_TIMEOUT_EN_MASK (0x1U << PWM_FIFO_CTRL_TIMEOUT_EN_SHIFT) /* 0x00000200 */ +#define PWM_FIFO_CTRL_DMA_CH_SEL_EN_SHIFT (10U) +#define PWM_FIFO_CTRL_DMA_CH_SEL_EN_MASK (0x1U << PWM_FIFO_CTRL_DMA_CH_SEL_EN_SHIFT) /* 0x00000400 */ +#define PWM_FIFO_CTRL_DMA_CH_SEL_SHIFT (12U) +#define PWM_FIFO_CTRL_DMA_CH_SEL_MASK (0x3U << PWM_FIFO_CTRL_DMA_CH_SEL_SHIFT) /* 0x00003000 */ +/* FIFO_INTSTS */ +#define PWM_FIFO_INTSTS_OFFSET (0x54U) +#define PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_SHIFT (0U) +#define PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_SHIFT) /* 0x00000001 */ +#define PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_SHIFT (1U) +#define PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_SHIFT) /* 0x00000002 */ +#define PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_SHIFT (2U) +#define PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_SHIFT) /* 0x00000004 */ +#define PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_SHIFT (3U) +#define PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_SHIFT) /* 0x00000008 */ +#define PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_SHIFT (4U) +#define PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_SHIFT) /* 0x00000010 */ +/* FIFO_TOUTTHR */ +#define PWM_FIFO_TOUTTHR_OFFSET (0x58U) +#define PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_SHIFT (0U) +#define PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_MASK (0xFFFFFU << PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_SHIFT) /* 0x000FFFFF */ +/* VERSION_ID */ +#define PWM_VERSION_ID_OFFSET (0x5CU) +#define PWM_VERSION_ID_SVN_VERSION_SHIFT (0U) +#define PWM_VERSION_ID_SVN_VERSION_MASK (0xFFFFU << PWM_VERSION_ID_SVN_VERSION_SHIFT) /* 0x0000FFFF */ +#define PWM_VERSION_ID_MINOR_VERSION_SHIFT (16U) +#define PWM_VERSION_ID_MINOR_VERSION_MASK (0xFFU << PWM_VERSION_ID_MINOR_VERSION_SHIFT) /* 0x00FF0000 */ +#define PWM_VERSION_ID_MAIN_VERSION_SHIFT (24U) +#define PWM_VERSION_ID_MAIN_VERSION_MASK (0xFFU << PWM_VERSION_ID_MAIN_VERSION_SHIFT) /* 0xFF000000 */ +/* FIFO */ +#define PWM_FIFO_OFFSET (0x60U) +#define PWM_FIFO (0x0U) +#define PWM_FIFO_CYCLE_CNT_SHIFT (0U) +#define PWM_FIFO_CYCLE_CNT_MASK (0x7FFFFFFFU << PWM_FIFO_CYCLE_CNT_SHIFT) /* 0x7FFFFFFF */ +#define PWM_FIFO_POL_SHIFT (31U) +#define PWM_FIFO_POL_MASK (0x1U << PWM_FIFO_POL_SHIFT) /* 0x80000000 */ +/* PWRMATCH_CTRL */ +#define PWM_PWRMATCH_CTRL_OFFSET (0x80U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_SHIFT (3U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_SHIFT) /* 0x00000008 */ +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_SHIFT (7U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_SHIFT) /* 0x00000080 */ +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_SHIFT (11U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_SHIFT) /* 0x00000800 */ +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_SHIFT (15U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_SHIFT) /* 0x00008000 */ +/* PWRMATCH_LPRE */ +#define PWM_PWRMATCH_LPRE_OFFSET (0x84U) +#define PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_LPRE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_LPRE_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_LPRE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_LPRE_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_HPRE */ +#define PWM_PWRMATCH_HPRE_OFFSET (0x88U) +#define PWM_PWRMATCH_HPRE_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_HPRE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HPRE_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_HPRE_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_HPRE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HPRE_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_LD */ +#define PWM_PWRMATCH_LD_OFFSET (0x8CU) +#define PWM_PWRMATCH_LD_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_LD_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_LD_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_LD_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_LD_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_LD_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_HD_ZERO */ +#define PWM_PWRMATCH_HD_ZERO_OFFSET (0x90U) +#define PWM_PWRMATCH_HD_ZERO_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_HD_ZERO_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HD_ZERO_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_HD_ZERO_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_HD_ZERO_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HD_ZERO_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_HD_ONE */ +#define PWM_PWRMATCH_HD_ONE_OFFSET (0x94U) +#define PWM_PWRMATCH_HD_ONE_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_HD_ONE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HD_ONE_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_HD_ONE_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_HD_ONE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HD_ONE_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_VALUE0 */ +#define PWM_PWRMATCH_VALUE0_OFFSET (0x98U) +#define PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE1 */ +#define PWM_PWRMATCH_VALUE1_OFFSET (0x9CU) +#define PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE2 */ +#define PWM_PWRMATCH_VALUE2_OFFSET (0xA0U) +#define PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE3 */ +#define PWM_PWRMATCH_VALUE3_OFFSET (0xA4U) +#define PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE4 */ +#define PWM_PWRMATCH_VALUE4_OFFSET (0xA8U) +#define PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE5 */ +#define PWM_PWRMATCH_VALUE5_OFFSET (0xACU) +#define PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE6 */ +#define PWM_PWRMATCH_VALUE6_OFFSET (0xB0U) +#define PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE7 */ +#define PWM_PWRMATCH_VALUE7_OFFSET (0xB4U) +#define PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE8 */ +#define PWM_PWRMATCH_VALUE8_OFFSET (0xB8U) +#define PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE9 */ +#define PWM_PWRMATCH_VALUE9_OFFSET (0xBCU) +#define PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_PWRCAPTURE_VALUE */ +#define PWM_PWM3_PWRCAPTURE_VALUE_OFFSET (0xCCU) +#define PWM_PWM3_PWRCAPTURE_VALUE (0x0U) +#define PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_SHIFT (0U) +#define PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_MASK (0xFFFFFFFFU << PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* FILTER_CTRL */ +#define PWM_FILTER_CTRL_OFFSET (0xD0U) +#define PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_SHIFT (0U) +#define PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000001 */ +#define PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_SHIFT (1U) +#define PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000002 */ +#define PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_SHIFT (2U) +#define PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000004 */ +#define PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_SHIFT (3U) +#define PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000008 */ +#define PWM_FILTER_CTRL_FILTER_NUMBER_SHIFT (4U) +#define PWM_FILTER_CTRL_FILTER_NUMBER_MASK (0x1FFU << PWM_FILTER_CTRL_FILTER_NUMBER_SHIFT) /* 0x00001FF0 */ +/*****************************************TIMER******************************************/ +/* LOAD_COUNT0 */ +#define TIMER_LOAD_COUNT0_OFFSET (0x0U) +#define TIMER_LOAD_COUNT0_COUNT0_SHIFT (0U) +#define TIMER_LOAD_COUNT0_COUNT0_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT0_COUNT0_SHIFT) /* 0xFFFFFFFF */ +/* LOAD_COUNT1 */ +#define TIMER_LOAD_COUNT1_OFFSET (0x4U) +#define TIMER_LOAD_COUNT1_COUNT1_SHIFT (0U) +#define TIMER_LOAD_COUNT1_COUNT1_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT1_COUNT1_SHIFT) /* 0xFFFFFFFF */ +/* CURRENT_VALUE0 */ +#define TIMER_CURRENT_VALUE0_OFFSET (0x8U) +#define TIMER_CURRENT_VALUE0 (0x0U) +#define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT (0U) +#define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT) /* 0xFFFFFFFF */ +/* CURRENT_VALUE1 */ +#define TIMER_CURRENT_VALUE1_OFFSET (0xCU) +#define TIMER_CURRENT_VALUE1 (0x0U) +#define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT (0U) +#define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT) /* 0xFFFFFFFF */ +/* CONTROLREG */ +#define TIMER_CONTROLREG_OFFSET (0x10U) +#define TIMER_CONTROLREG_TIMER_ENABLE_SHIFT (0U) +#define TIMER_CONTROLREG_TIMER_ENABLE_MASK (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) /* 0x00000001 */ +#define TIMER_CONTROLREG_TIMER_MODE_SHIFT (1U) +#define TIMER_CONTROLREG_TIMER_MODE_MASK (0x1U << TIMER_CONTROLREG_TIMER_MODE_SHIFT) /* 0x00000002 */ +#define TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT (2U) +#define TIMER_CONTROLREG_TIMER_INT_MASK_MASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT) /* 0x00000004 */ +/* INTSTATUS */ +#define TIMER_INTSTATUS_OFFSET (0x18U) +#define TIMER_INTSTATUS_INT_PD_SHIFT (0U) +#define TIMER_INTSTATUS_INT_PD_MASK (0x1U << TIMER_INTSTATUS_INT_PD_SHIFT) /* 0x00000001 */ +/******************************************WDT*******************************************/ +/* WDT_CR */ +#define WDT_CR_OFFSET (0x0) +#define WDT_CR_WDT_EN_SHIFT (0U) +#define WDT_CR_WDT_EN_MASK (0x1U << WDT_CR_WDT_EN_SHIFT) /* 0x00000001 */ +#define WDT_CR_RESP_MODE_SHIFT (1U) +#define WDT_CR_RESP_MODE_MASK (0x1U << WDT_CR_RESP_MODE_SHIFT) /* 0x00000002 */ +#define WDT_CR_RST_PLUSE_LENTH_SHIFT (2U) +#define WDT_CR_RST_PLUSE_LENTH_MASK (0x3U << WDT_CR_RST_PLUSE_LENTH_SHIFT) /* 0x0000000C */ +/* WDT_TORR */ +#define WDT_TORR_OFFSET (0x4) +#define WDT_TORR_TIMEOUT_PERIOD_SHIFT (0U) +#define WDT_TORR_TIMEOUT_PERIOD_MASK (0xFU << WDT_TORR_TIMEOUT_PERIOD_SHIFT) /* 0x0000000F */ +/* WDT_CCVR */ +#define WDT_CCVR_OFFSET (0x8) +#define WDT_CCVR_CUR_CNT_SHIFT (0U) +#define WDT_CCVR_CUR_CNT_MASK (0xFFFFFFFFU << WDT_CCVR_CUR_CNT_SHIFT) /* 0xFFFFFFFF */ +/* WDT_CRR */ +#define WDT_CRR_OFFSET (0xC) +#define WDT_CRR_CNT_RESTART_SHIFT (0U) +#define WDT_CRR_CNT_RESTART_MASK (0xFFU << WDT_CRR_CNT_RESTART_SHIFT) /* 0x000000FF */ +/* WDT_STAT */ +#define WDT_STAT_OFFSET (0x10) +#define WDT_STAT_WDT_STATUS_SHIFT (0U) +#define WDT_STAT_WDT_STATUS_MASK (0x1U << WDT_STAT_WDT_STATUS_SHIFT) /* 0x00000001 */ +/* WDT_EOI */ +#define WDT_EOI_OFFSET (0x14) +#define WDT_EOI_WDT_INT_CLR_SHIFT (0U) +#define WDT_EOI_WDT_INT_CLR_MASK (0x1U << WDT_EOI_WDT_INT_CLR_SHIFT) /* 0x00000001 */ +/******************************************I2C*******************************************/ +/* CON */ +#define I2C_CON_OFFSET (0x0U) +#define I2C_CON_I2C_EN_SHIFT (0U) +#define I2C_CON_I2C_EN_MASK (0x1U << I2C_CON_I2C_EN_SHIFT) /* 0x00000001 */ +#define I2C_CON_I2C_MODE_SHIFT (1U) +#define I2C_CON_I2C_MODE_MASK (0x3U << I2C_CON_I2C_MODE_SHIFT) /* 0x00000006 */ +#define I2C_CON_START_SHIFT (3U) +#define I2C_CON_START_MASK (0x1U << I2C_CON_START_SHIFT) /* 0x00000008 */ +#define I2C_CON_STOP_SHIFT (4U) +#define I2C_CON_STOP_MASK (0x1U << I2C_CON_STOP_SHIFT) /* 0x00000010 */ +#define I2C_CON_ACK_SHIFT (5U) +#define I2C_CON_ACK_MASK (0x1U << I2C_CON_ACK_SHIFT) /* 0x00000020 */ +#define I2C_CON_ACT2NAK_SHIFT (6U) +#define I2C_CON_ACT2NAK_MASK (0x1U << I2C_CON_ACT2NAK_SHIFT) /* 0x00000040 */ +#define I2C_CON_DATA_UPD_ST_SHIFT (8U) +#define I2C_CON_DATA_UPD_ST_MASK (0x7U << I2C_CON_DATA_UPD_ST_SHIFT) /* 0x00000700 */ +#define I2C_CON_START_SETUP_SHIFT (12U) +#define I2C_CON_START_SETUP_MASK (0x3U << I2C_CON_START_SETUP_SHIFT) /* 0x00003000 */ +#define I2C_CON_STOP_SETUP_SHIFT (14U) +#define I2C_CON_STOP_SETUP_MASK (0x3U << I2C_CON_STOP_SETUP_SHIFT) /* 0x0000C000 */ +#define I2C_CON_VERSION_SHIFT (16U) +#define I2C_CON_VERSION_MASK (0xFFFFU << I2C_CON_VERSION_SHIFT) /* 0xFFFF0000 */ +/* CLKDIV */ +#define I2C_CLKDIV_OFFSET (0x4U) +#define I2C_CLKDIV_CLKDIVL_SHIFT (0U) +#define I2C_CLKDIV_CLKDIVL_MASK (0xFFFFU << I2C_CLKDIV_CLKDIVL_SHIFT) /* 0x0000FFFF */ +#define I2C_CLKDIV_CLKDIVH_SHIFT (16U) +#define I2C_CLKDIV_CLKDIVH_MASK (0xFFFFU << I2C_CLKDIV_CLKDIVH_SHIFT) /* 0xFFFF0000 */ +/* MRXADDR */ +#define I2C_MRXADDR_OFFSET (0x8U) +#define I2C_MRXADDR_SADDR_SHIFT (0U) +#define I2C_MRXADDR_SADDR_MASK (0xFFFFFFU << I2C_MRXADDR_SADDR_SHIFT) /* 0x00FFFFFF */ +#define I2C_MRXADDR_ADDLVLD_SHIFT (24U) +#define I2C_MRXADDR_ADDLVLD_MASK (0x1U << I2C_MRXADDR_ADDLVLD_SHIFT) /* 0x01000000 */ +#define I2C_MRXADDR_ADDMVLD_SHIFT (25U) +#define I2C_MRXADDR_ADDMVLD_MASK (0x1U << I2C_MRXADDR_ADDMVLD_SHIFT) /* 0x02000000 */ +#define I2C_MRXADDR_ADDHVLD_SHIFT (26U) +#define I2C_MRXADDR_ADDHVLD_MASK (0x1U << I2C_MRXADDR_ADDHVLD_SHIFT) /* 0x04000000 */ +/* MRXRADDR */ +#define I2C_MRXRADDR_OFFSET (0xCU) +#define I2C_MRXRADDR_SRADDR_SHIFT (0U) +#define I2C_MRXRADDR_SRADDR_MASK (0xFFFFFFU << I2C_MRXRADDR_SRADDR_SHIFT) /* 0x00FFFFFF */ +#define I2C_MRXRADDR_SRADDLVLD_SHIFT (24U) +#define I2C_MRXRADDR_SRADDLVLD_MASK (0x1U << I2C_MRXRADDR_SRADDLVLD_SHIFT) /* 0x01000000 */ +#define I2C_MRXRADDR_SRADDMVLD_SHIFT (25U) +#define I2C_MRXRADDR_SRADDMVLD_MASK (0x1U << I2C_MRXRADDR_SRADDMVLD_SHIFT) /* 0x02000000 */ +#define I2C_MRXRADDR_SRADDHVLD_SHIFT (26U) +#define I2C_MRXRADDR_SRADDHVLD_MASK (0x1U << I2C_MRXRADDR_SRADDHVLD_SHIFT) /* 0x04000000 */ +/* MTXCNT */ +#define I2C_MTXCNT_OFFSET (0x10U) +#define I2C_MTXCNT_MTXCNT_SHIFT (0U) +#define I2C_MTXCNT_MTXCNT_MASK (0x3FU << I2C_MTXCNT_MTXCNT_SHIFT) /* 0x0000003F */ +/* MRXCNT */ +#define I2C_MRXCNT_OFFSET (0x14U) +#define I2C_MRXCNT_MRXCNT_SHIFT (0U) +#define I2C_MRXCNT_MRXCNT_MASK (0x3FU << I2C_MRXCNT_MRXCNT_SHIFT) /* 0x0000003F */ +/* IEN */ +#define I2C_IEN_OFFSET (0x18U) +#define I2C_IEN_BTFIEN_SHIFT (0U) +#define I2C_IEN_BTFIEN_MASK (0x1U << I2C_IEN_BTFIEN_SHIFT) /* 0x00000001 */ +#define I2C_IEN_BRFIEN_SHIFT (1U) +#define I2C_IEN_BRFIEN_MASK (0x1U << I2C_IEN_BRFIEN_SHIFT) /* 0x00000002 */ +#define I2C_IEN_MBTFIEN_SHIFT (2U) +#define I2C_IEN_MBTFIEN_MASK (0x1U << I2C_IEN_MBTFIEN_SHIFT) /* 0x00000004 */ +#define I2C_IEN_MBRFIEN_SHIFT (3U) +#define I2C_IEN_MBRFIEN_MASK (0x1U << I2C_IEN_MBRFIEN_SHIFT) /* 0x00000008 */ +#define I2C_IEN_STARTIEN_SHIFT (4U) +#define I2C_IEN_STARTIEN_MASK (0x1U << I2C_IEN_STARTIEN_SHIFT) /* 0x00000010 */ +#define I2C_IEN_STOPIEN_SHIFT (5U) +#define I2C_IEN_STOPIEN_MASK (0x1U << I2C_IEN_STOPIEN_SHIFT) /* 0x00000020 */ +#define I2C_IEN_NAKRCVIEN_SHIFT (6U) +#define I2C_IEN_NAKRCVIEN_MASK (0x1U << I2C_IEN_NAKRCVIEN_SHIFT) /* 0x00000040 */ +#define I2C_IEN_SLAVEHDSCLEN_SHIFT (7U) +#define I2C_IEN_SLAVEHDSCLEN_MASK (0x1U << I2C_IEN_SLAVEHDSCLEN_SHIFT) /* 0x00000080 */ +/* IPD */ +#define I2C_IPD_OFFSET (0x1CU) +#define I2C_IPD_BTFIPD_SHIFT (0U) +#define I2C_IPD_BTFIPD_MASK (0x1U << I2C_IPD_BTFIPD_SHIFT) /* 0x00000001 */ +#define I2C_IPD_BRFIPD_SHIFT (1U) +#define I2C_IPD_BRFIPD_MASK (0x1U << I2C_IPD_BRFIPD_SHIFT) /* 0x00000002 */ +#define I2C_IPD_MBTFIPD_SHIFT (2U) +#define I2C_IPD_MBTFIPD_MASK (0x1U << I2C_IPD_MBTFIPD_SHIFT) /* 0x00000004 */ +#define I2C_IPD_MBRFIPD_SHIFT (3U) +#define I2C_IPD_MBRFIPD_MASK (0x1U << I2C_IPD_MBRFIPD_SHIFT) /* 0x00000008 */ +#define I2C_IPD_STARTIPD_SHIFT (4U) +#define I2C_IPD_STARTIPD_MASK (0x1U << I2C_IPD_STARTIPD_SHIFT) /* 0x00000010 */ +#define I2C_IPD_STOPIPD_SHIFT (5U) +#define I2C_IPD_STOPIPD_MASK (0x1U << I2C_IPD_STOPIPD_SHIFT) /* 0x00000020 */ +#define I2C_IPD_NAKRCVIPD_SHIFT (6U) +#define I2C_IPD_NAKRCVIPD_MASK (0x1U << I2C_IPD_NAKRCVIPD_SHIFT) /* 0x00000040 */ +#define I2C_IPD_SLAVEHDSCLIPD_SHIFT (7U) +#define I2C_IPD_SLAVEHDSCLIPD_MASK (0x1U << I2C_IPD_SLAVEHDSCLIPD_SHIFT) /* 0x00000080 */ +/* FCNT */ +#define I2C_FCNT_OFFSET (0x20U) +#define I2C_FCNT (0x0U) +#define I2C_FCNT_FCNT_SHIFT (0U) +#define I2C_FCNT_FCNT_MASK (0x3FU << I2C_FCNT_FCNT_SHIFT) /* 0x0000003F */ +/* SCL_OE_DB */ +#define I2C_SCL_OE_DB_OFFSET (0x24U) +#define I2C_SCL_OE_DB_SCL_OE_DB_SHIFT (0U) +#define I2C_SCL_OE_DB_SCL_OE_DB_MASK (0xFFU << I2C_SCL_OE_DB_SCL_OE_DB_SHIFT) /* 0x000000FF */ +/* TXDATA0 */ +#define I2C_TXDATA0_OFFSET (0x100U) +#define I2C_TXDATA0_TXDATA0_SHIFT (0U) +#define I2C_TXDATA0_TXDATA0_MASK (0xFFFFFFFFU << I2C_TXDATA0_TXDATA0_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA1 */ +#define I2C_TXDATA1_OFFSET (0x104U) +#define I2C_TXDATA1_TXDATA1_SHIFT (0U) +#define I2C_TXDATA1_TXDATA1_MASK (0xFFFFFFFFU << I2C_TXDATA1_TXDATA1_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA2 */ +#define I2C_TXDATA2_OFFSET (0x108U) +#define I2C_TXDATA2_TXDATA2_SHIFT (0U) +#define I2C_TXDATA2_TXDATA2_MASK (0xFFFFFFFFU << I2C_TXDATA2_TXDATA2_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA3 */ +#define I2C_TXDATA3_OFFSET (0x10CU) +#define I2C_TXDATA3_TXDATA3_SHIFT (0U) +#define I2C_TXDATA3_TXDATA3_MASK (0xFFFFFFFFU << I2C_TXDATA3_TXDATA3_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA4 */ +#define I2C_TXDATA4_OFFSET (0x110U) +#define I2C_TXDATA4_TXDATA4_SHIFT (0U) +#define I2C_TXDATA4_TXDATA4_MASK (0xFFFFFFFFU << I2C_TXDATA4_TXDATA4_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA5 */ +#define I2C_TXDATA5_OFFSET (0x114U) +#define I2C_TXDATA5_TXDATA5_SHIFT (0U) +#define I2C_TXDATA5_TXDATA5_MASK (0xFFFFFFFFU << I2C_TXDATA5_TXDATA5_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA6 */ +#define I2C_TXDATA6_OFFSET (0x118U) +#define I2C_TXDATA6_TXDATA6_SHIFT (0U) +#define I2C_TXDATA6_TXDATA6_MASK (0xFFFFFFFFU << I2C_TXDATA6_TXDATA6_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA7 */ +#define I2C_TXDATA7_OFFSET (0x11CU) +#define I2C_TXDATA7_TXDATA7_SHIFT (0U) +#define I2C_TXDATA7_TXDATA7_MASK (0xFFFFFFFFU << I2C_TXDATA7_TXDATA7_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA0 */ +#define I2C_RXDATA0_OFFSET (0x200U) +#define I2C_RXDATA0 (0x0U) +#define I2C_RXDATA0_RXDATA0_SHIFT (0U) +#define I2C_RXDATA0_RXDATA0_MASK (0xFFFFFFFFU << I2C_RXDATA0_RXDATA0_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA1 */ +#define I2C_RXDATA1_OFFSET (0x204U) +#define I2C_RXDATA1 (0x0U) +#define I2C_RXDATA1_RXDATA1_SHIFT (0U) +#define I2C_RXDATA1_RXDATA1_MASK (0xFFFFFFFFU << I2C_RXDATA1_RXDATA1_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA2 */ +#define I2C_RXDATA2_OFFSET (0x208U) +#define I2C_RXDATA2 (0x0U) +#define I2C_RXDATA2_RXDATA2_SHIFT (0U) +#define I2C_RXDATA2_RXDATA2_MASK (0xFFFFFFFFU << I2C_RXDATA2_RXDATA2_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA3 */ +#define I2C_RXDATA3_OFFSET (0x20CU) +#define I2C_RXDATA3 (0x0U) +#define I2C_RXDATA3_RXDATA3_SHIFT (0U) +#define I2C_RXDATA3_RXDATA3_MASK (0xFFFFFFFFU << I2C_RXDATA3_RXDATA3_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA4 */ +#define I2C_RXDATA4_OFFSET (0x210U) +#define I2C_RXDATA4 (0x0U) +#define I2C_RXDATA4_RXDATA4_SHIFT (0U) +#define I2C_RXDATA4_RXDATA4_MASK (0xFFFFFFFFU << I2C_RXDATA4_RXDATA4_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA5 */ +#define I2C_RXDATA5_OFFSET (0x214U) +#define I2C_RXDATA5 (0x0U) +#define I2C_RXDATA5_RXDATA5_SHIFT (0U) +#define I2C_RXDATA5_RXDATA5_MASK (0xFFFFFFFFU << I2C_RXDATA5_RXDATA5_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA6 */ +#define I2C_RXDATA6_OFFSET (0x218U) +#define I2C_RXDATA6 (0x0U) +#define I2C_RXDATA6_RXDATA6_SHIFT (0U) +#define I2C_RXDATA6_RXDATA6_MASK (0xFFFFFFFFU << I2C_RXDATA6_RXDATA6_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA7 */ +#define I2C_RXDATA7_OFFSET (0x21CU) +#define I2C_RXDATA7 (0x0U) +#define I2C_RXDATA7_RXDATA7_SHIFT (0U) +#define I2C_RXDATA7_RXDATA7_MASK (0xFFFFFFFFU << I2C_RXDATA7_RXDATA7_SHIFT) /* 0xFFFFFFFF */ +/* ST */ +#define I2C_ST_OFFSET (0x220U) +#define I2C_ST (0x0U) +#define I2C_ST_SDA_ST_SHIFT (0U) +#define I2C_ST_SDA_ST_MASK (0x1U << I2C_ST_SDA_ST_SHIFT) /* 0x00000001 */ +#define I2C_ST_SCL_ST_SHIFT (1U) +#define I2C_ST_SCL_ST_MASK (0x1U << I2C_ST_SCL_ST_SHIFT) /* 0x00000002 */ +/* DBGCTRL */ +#define I2C_DBGCTRL_OFFSET (0x224U) +#define I2C_DBGCTRL_FLT_F_SHIFT (0U) +#define I2C_DBGCTRL_FLT_F_MASK (0xFU << I2C_DBGCTRL_FLT_F_SHIFT) /* 0x0000000F */ +#define I2C_DBGCTRL_FLT_R_SHIFT (4U) +#define I2C_DBGCTRL_FLT_R_MASK (0xFU << I2C_DBGCTRL_FLT_R_SHIFT) /* 0x000000F0 */ +#define I2C_DBGCTRL_SLV_HOLD_SCL_TH_SHIFT (8U) +#define I2C_DBGCTRL_SLV_HOLD_SCL_TH_MASK (0xFU << I2C_DBGCTRL_SLV_HOLD_SCL_TH_SHIFT) /* 0x00000F00 */ +#define I2C_DBGCTRL_FLT_EN_SHIFT (12U) +#define I2C_DBGCTRL_FLT_EN_MASK (0x1U << I2C_DBGCTRL_FLT_EN_SHIFT) /* 0x00001000 */ +#define I2C_DBGCTRL_NAK_RELEASE_SCL_SHIFT (13U) +#define I2C_DBGCTRL_NAK_RELEASE_SCL_MASK (0x1U << I2C_DBGCTRL_NAK_RELEASE_SCL_SHIFT) /* 0x00002000 */ +#define I2C_DBGCTRL_H0_CHECK_SCL_SHIFT (14U) +#define I2C_DBGCTRL_H0_CHECK_SCL_MASK (0x1U << I2C_DBGCTRL_H0_CHECK_SCL_SHIFT) /* 0x00004000 */ +/****************************************SPI2APB*****************************************/ +/* CTRL0 */ +#define SPI2APB_CTRL0_OFFSET (0x0U) +#define SPI2APB_CTRL0_FBM_SHIFT (0U) +#define SPI2APB_CTRL0_FBM_MASK (0x1U << SPI2APB_CTRL0_FBM_SHIFT) /* 0x00000001 */ +#define SPI2APB_CTRL0_EM_SHIFT (1U) +#define SPI2APB_CTRL0_EM_MASK (0x1U << SPI2APB_CTRL0_EM_SHIFT) /* 0x00000002 */ +#define SPI2APB_CTRL0_RXCP_SHIFT (2U) +#define SPI2APB_CTRL0_RXCP_MASK (0x1U << SPI2APB_CTRL0_RXCP_SHIFT) /* 0x00000004 */ +#define SPI2APB_CTRL0_TXCP_SHIFT (3U) +#define SPI2APB_CTRL0_TXCP_MASK (0x1U << SPI2APB_CTRL0_TXCP_SHIFT) /* 0x00000008 */ +/* SR */ +#define SPI2APB_SR_OFFSET (0x24U) +#define SPI2APB_SR (0x0U) +#define SPI2APB_SR_BSF_SHIFT (0U) +#define SPI2APB_SR_BSF_MASK (0x1U << SPI2APB_SR_BSF_SHIFT) /* 0x00000001 */ +#define SPI2APB_SR_TFF_SHIFT (1U) +#define SPI2APB_SR_TFF_MASK (0x1U << SPI2APB_SR_TFF_SHIFT) /* 0x00000002 */ +#define SPI2APB_SR_TFE_SHIFT (2U) +#define SPI2APB_SR_TFE_MASK (0x1U << SPI2APB_SR_TFE_SHIFT) /* 0x00000004 */ +#define SPI2APB_SR_RFF_SHIFT (3U) +#define SPI2APB_SR_RFF_MASK (0x1U << SPI2APB_SR_RFF_SHIFT) /* 0x00000008 */ +#define SPI2APB_SR_RFE_SHIFT (4U) +#define SPI2APB_SR_RFE_MASK (0x1U << SPI2APB_SR_RFE_SHIFT) /* 0x00000010 */ +/* IMR */ +#define SPI2APB_IMR_OFFSET (0x2CU) +#define SPI2APB_IMR_QWIM_SHIFT (0U) +#define SPI2APB_IMR_QWIM_MASK (0x1U << SPI2APB_IMR_QWIM_SHIFT) /* 0x00000001 */ +/* RISR */ +#define SPI2APB_RISR_OFFSET (0x34U) +#define SPI2APB_RISR_QWRIS_SHIFT (0U) +#define SPI2APB_RISR_QWRIS_MASK (0x1U << SPI2APB_RISR_QWRIS_SHIFT) /* 0x00000001 */ +/* ICR */ +#define SPI2APB_ICR_OFFSET (0x38U) +#define SPI2APB_ICR_CQWI_SHIFT (0U) +#define SPI2APB_ICR_CQWI_MASK (0x1U << SPI2APB_ICR_CQWI_SHIFT) /* 0x00000001 */ +/* VERSION */ +#define SPI2APB_VERSION_OFFSET (0x48U) +#define SPI2APB_VERSION_VERSION_SHIFT (0U) +#define SPI2APB_VERSION_VERSION_MASK (0xFFFFFFFFU << SPI2APB_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */ +/* QUICK_REG0 */ +#define SPI2APB_QUICK_REG0_OFFSET (0x50U) +#define SPI2APB_QUICK_REG0_QWV0_SHIFT (0U) +#define SPI2APB_QUICK_REG0_QWV0_MASK (0xFFFFFFFFU << SPI2APB_QUICK_REG0_QWV0_SHIFT) /* 0xFFFFFFFF */ +/* QUICK_REG1 */ +#define SPI2APB_QUICK_REG1_OFFSET (0x54U) +#define SPI2APB_QUICK_REG1_QWV1_SHIFT (0U) +#define SPI2APB_QUICK_REG1_QWV1_MASK (0xFFFFFFFFU << SPI2APB_QUICK_REG1_QWV1_SHIFT) /* 0xFFFFFFFF */ +/* QUICK_REG2 */ +#define SPI2APB_QUICK_REG2_OFFSET (0x58U) +#define SPI2APB_QUICK_REG2_QRV_SHIFT (0U) +#define SPI2APB_QUICK_REG2_QRV_MASK (0xFFFFFFFFU << SPI2APB_QUICK_REG2_QRV_SHIFT) /* 0xFFFFFFFF */ +/******************************************SPI*******************************************/ +/* CTRLR0 */ +#define SPI_CTRLR0_OFFSET (0x0U) +#define SPI_CTRLR0_DFS_SHIFT (0U) +#define SPI_CTRLR0_DFS_MASK (0x3U << SPI_CTRLR0_DFS_SHIFT) /* 0x00000003 */ +#define SPI_CTRLR0_CFS_SHIFT (2U) +#define SPI_CTRLR0_CFS_MASK (0xFU << SPI_CTRLR0_CFS_SHIFT) /* 0x0000003C */ +#define SPI_CTRLR0_SCPH_SHIFT (6U) +#define SPI_CTRLR0_SCPH_MASK (0x1U << SPI_CTRLR0_SCPH_SHIFT) /* 0x00000040 */ +#define SPI_CTRLR0_SCPOL_SHIFT (7U) +#define SPI_CTRLR0_SCPOL_MASK (0x1U << SPI_CTRLR0_SCPOL_SHIFT) /* 0x00000080 */ +#define SPI_CTRLR0_CSM_SHIFT (8U) +#define SPI_CTRLR0_CSM_MASK (0x3U << SPI_CTRLR0_CSM_SHIFT) /* 0x00000300 */ +#define SPI_CTRLR0_SSD_SHIFT (10U) +#define SPI_CTRLR0_SSD_MASK (0x1U << SPI_CTRLR0_SSD_SHIFT) /* 0x00000400 */ +#define SPI_CTRLR0_EM_SHIFT (11U) +#define SPI_CTRLR0_EM_MASK (0x1U << SPI_CTRLR0_EM_SHIFT) /* 0x00000800 */ +#define SPI_CTRLR0_FBM_SHIFT (12U) +#define SPI_CTRLR0_FBM_MASK (0x1U << SPI_CTRLR0_FBM_SHIFT) /* 0x00001000 */ +#define SPI_CTRLR0_BHT_SHIFT (13U) +#define SPI_CTRLR0_BHT_MASK (0x1U << SPI_CTRLR0_BHT_SHIFT) /* 0x00002000 */ +#define SPI_CTRLR0_RSD_SHIFT (14U) +#define SPI_CTRLR0_RSD_MASK (0x3U << SPI_CTRLR0_RSD_SHIFT) /* 0x0000C000 */ +#define SPI_CTRLR0_FRF_SHIFT (16U) +#define SPI_CTRLR0_FRF_MASK (0x3U << SPI_CTRLR0_FRF_SHIFT) /* 0x00030000 */ +#define SPI_CTRLR0_XFM_SHIFT (18U) +#define SPI_CTRLR0_XFM_MASK (0x3U << SPI_CTRLR0_XFM_SHIFT) /* 0x000C0000 */ +#define SPI_CTRLR0_OPM_SHIFT (20U) +#define SPI_CTRLR0_OPM_MASK (0x1U << SPI_CTRLR0_OPM_SHIFT) /* 0x00100000 */ +#define SPI_CTRLR0_MTM_SHIFT (21U) +#define SPI_CTRLR0_MTM_MASK (0x1U << SPI_CTRLR0_MTM_SHIFT) /* 0x00200000 */ +#define SPI_CTRLR0_SOI_SHIFT (23U) +#define SPI_CTRLR0_SOI_MASK (0x3U << SPI_CTRLR0_SOI_SHIFT) /* 0x01800000 */ +#define SPI_CTRLR0_LBK_SHIFT (25U) +#define SPI_CTRLR0_LBK_MASK (0x1U << SPI_CTRLR0_LBK_SHIFT) /* 0x02000000 */ +/* CTRLR1 */ +#define SPI_CTRLR1_OFFSET (0x4U) +#define SPI_CTRLR1_NDM_SHIFT (0U) +#define SPI_CTRLR1_NDM_MASK (0xFFFFFFFFU << SPI_CTRLR1_NDM_SHIFT) /* 0xFFFFFFFF */ +/* ENR */ +#define SPI_ENR_OFFSET (0x8U) +#define SPI_ENR_ENR_SHIFT (0U) +#define SPI_ENR_ENR_MASK (0x1U << SPI_ENR_ENR_SHIFT) /* 0x00000001 */ +/* SER */ +#define SPI_SER_OFFSET (0xCU) +#define SPI_SER_SER_SHIFT (0U) +#define SPI_SER_SER_MASK (0x3U << SPI_SER_SER_SHIFT) /* 0x00000003 */ +/* BAUDR */ +#define SPI_BAUDR_OFFSET (0x10U) +#define SPI_BAUDR_BAUDR_SHIFT (0U) +#define SPI_BAUDR_BAUDR_MASK (0xFFFFU << SPI_BAUDR_BAUDR_SHIFT) /* 0x0000FFFF */ +/* TXFTLR */ +#define SPI_TXFTLR_OFFSET (0x14U) +#define SPI_TXFTLR_TXFTLR_SHIFT (0U) +#define SPI_TXFTLR_TXFTLR_MASK (0x3FU << SPI_TXFTLR_TXFTLR_SHIFT) /* 0x0000003F */ +/* RXFTLR */ +#define SPI_RXFTLR_OFFSET (0x18U) +#define SPI_RXFTLR_RXFTLR_SHIFT (0U) +#define SPI_RXFTLR_RXFTLR_MASK (0x3FU << SPI_RXFTLR_RXFTLR_SHIFT) /* 0x0000003F */ +/* TXFLR */ +#define SPI_TXFLR_OFFSET (0x1CU) +#define SPI_TXFLR (0x0U) +#define SPI_TXFLR_TXFLR_SHIFT (0U) +#define SPI_TXFLR_TXFLR_MASK (0x7FU << SPI_TXFLR_TXFLR_SHIFT) /* 0x0000007F */ +/* RXFLR */ +#define SPI_RXFLR_OFFSET (0x20U) +#define SPI_RXFLR (0x0U) +#define SPI_RXFLR_RXFLR_SHIFT (0U) +#define SPI_RXFLR_RXFLR_MASK (0x7FU << SPI_RXFLR_RXFLR_SHIFT) /* 0x0000007F */ +/* SR */ +#define SPI_SR_OFFSET (0x24U) +#define SPI_SR_BSF_SHIFT (0U) +#define SPI_SR_BSF_MASK (0x1U << SPI_SR_BSF_SHIFT) /* 0x00000001 */ +#define SPI_SR_TFF_SHIFT (1U) +#define SPI_SR_TFF_MASK (0x1U << SPI_SR_TFF_SHIFT) /* 0x00000002 */ +#define SPI_SR_TFE_SHIFT (2U) +#define SPI_SR_TFE_MASK (0x1U << SPI_SR_TFE_SHIFT) /* 0x00000004 */ +#define SPI_SR_RFE_SHIFT (3U) +#define SPI_SR_RFE_MASK (0x1U << SPI_SR_RFE_SHIFT) /* 0x00000008 */ +#define SPI_SR_RFF_SHIFT (4U) +#define SPI_SR_RFF_MASK (0x1U << SPI_SR_RFF_SHIFT) /* 0x00000010 */ +#define SPI_SR_STB_SHIFT (5U) +#define SPI_SR_STB_MASK (0x1U << SPI_SR_STB_SHIFT) /* 0x00000020 */ +#define SPI_SR_SSI_SHIFT (6U) +#define SPI_SR_SSI_MASK (0x1U << SPI_SR_SSI_SHIFT) /* 0x00000040 */ +/* IPR */ +#define SPI_IPR_OFFSET (0x28U) +#define SPI_IPR_IPR_SHIFT (0U) +#define SPI_IPR_IPR_MASK (0x1U << SPI_IPR_IPR_SHIFT) /* 0x00000001 */ +/* IMR */ +#define SPI_IMR_OFFSET (0x2CU) +#define SPI_IMR_TFEIM_SHIFT (0U) +#define SPI_IMR_TFEIM_MASK (0x1U << SPI_IMR_TFEIM_SHIFT) /* 0x00000001 */ +#define SPI_IMR_TFOIM_SHIFT (1U) +#define SPI_IMR_TFOIM_MASK (0x1U << SPI_IMR_TFOIM_SHIFT) /* 0x00000002 */ +#define SPI_IMR_RFUIM_SHIFT (2U) +#define SPI_IMR_RFUIM_MASK (0x1U << SPI_IMR_RFUIM_SHIFT) /* 0x00000004 */ +#define SPI_IMR_RFOIM_SHIFT (3U) +#define SPI_IMR_RFOIM_MASK (0x1U << SPI_IMR_RFOIM_SHIFT) /* 0x00000008 */ +#define SPI_IMR_RFFIM_SHIFT (4U) +#define SPI_IMR_RFFIM_MASK (0x1U << SPI_IMR_RFFIM_SHIFT) /* 0x00000010 */ +#define SPI_IMR_TOIM_SHIFT (5U) +#define SPI_IMR_TOIM_MASK (0x1U << SPI_IMR_TOIM_SHIFT) /* 0x00000020 */ +#define SPI_IMR_SSPIM_SHIFT (6U) +#define SPI_IMR_SSPIM_MASK (0x1U << SPI_IMR_SSPIM_SHIFT) /* 0x00000040 */ +#define SPI_IMR_TXFIM_SHIFT (7U) +#define SPI_IMR_TXFIM_MASK (0x1U << SPI_IMR_TXFIM_SHIFT) /* 0x00000080 */ +/* ISR */ +#define SPI_ISR_OFFSET (0x30U) +#define SPI_ISR_TFEIS_SHIFT (0U) +#define SPI_ISR_TFEIS_MASK (0x1U << SPI_ISR_TFEIS_SHIFT) /* 0x00000001 */ +#define SPI_ISR_TFOIS_SHIFT (1U) +#define SPI_ISR_TFOIS_MASK (0x1U << SPI_ISR_TFOIS_SHIFT) /* 0x00000002 */ +#define SPI_ISR_RFUIS_SHIFT (2U) +#define SPI_ISR_RFUIS_MASK (0x1U << SPI_ISR_RFUIS_SHIFT) /* 0x00000004 */ +#define SPI_ISR_RFOIS_SHIFT (3U) +#define SPI_ISR_RFOIS_MASK (0x1U << SPI_ISR_RFOIS_SHIFT) /* 0x00000008 */ +#define SPI_ISR_RFFIS_SHIFT (4U) +#define SPI_ISR_RFFIS_MASK (0x1U << SPI_ISR_RFFIS_SHIFT) /* 0x00000010 */ +#define SPI_ISR_TOIS_SHIFT (5U) +#define SPI_ISR_TOIS_MASK (0x1U << SPI_ISR_TOIS_SHIFT) /* 0x00000020 */ +#define SPI_ISR_SSPIS_SHIFT (6U) +#define SPI_ISR_SSPIS_MASK (0x1U << SPI_ISR_SSPIS_SHIFT) /* 0x00000040 */ +#define SPI_ISR_TXFIS_SHIFT (7U) +#define SPI_ISR_TXFIS_MASK (0x1U << SPI_ISR_TXFIS_SHIFT) /* 0x00000080 */ +/* RISR */ +#define SPI_RISR_OFFSET (0x34U) +#define SPI_RISR_TFERIS_SHIFT (0U) +#define SPI_RISR_TFERIS_MASK (0x1U << SPI_RISR_TFERIS_SHIFT) /* 0x00000001 */ +#define SPI_RISR_TFORIS_SHIFT (1U) +#define SPI_RISR_TFORIS_MASK (0x1U << SPI_RISR_TFORIS_SHIFT) /* 0x00000002 */ +#define SPI_RISR_RFURIS_SHIFT (2U) +#define SPI_RISR_RFURIS_MASK (0x1U << SPI_RISR_RFURIS_SHIFT) /* 0x00000004 */ +#define SPI_RISR_RFORIS_SHIFT (3U) +#define SPI_RISR_RFORIS_MASK (0x1U << SPI_RISR_RFORIS_SHIFT) /* 0x00000008 */ +#define SPI_RISR_RFFRIS_SHIFT (4U) +#define SPI_RISR_RFFRIS_MASK (0x1U << SPI_RISR_RFFRIS_SHIFT) /* 0x00000010 */ +#define SPI_RISR_TORIS_SHIFT (5U) +#define SPI_RISR_TORIS_MASK (0x1U << SPI_RISR_TORIS_SHIFT) /* 0x00000020 */ +#define SPI_RISR_SSPRIS_SHIFT (6U) +#define SPI_RISR_SSPRIS_MASK (0x1U << SPI_RISR_SSPRIS_SHIFT) /* 0x00000040 */ +#define SPI_RISR_TXFRIS_SHIFT (7U) +#define SPI_RISR_TXFRIS_MASK (0x1U << SPI_RISR_TXFRIS_SHIFT) /* 0x00000080 */ +/* ICR */ +#define SPI_ICR_OFFSET (0x38U) +#define SPI_ICR_CCI_SHIFT (0U) +#define SPI_ICR_CCI_MASK (0x1U << SPI_ICR_CCI_SHIFT) /* 0x00000001 */ +#define SPI_ICR_CRFUI_SHIFT (1U) +#define SPI_ICR_CRFUI_MASK (0x1U << SPI_ICR_CRFUI_SHIFT) /* 0x00000002 */ +#define SPI_ICR_CRFOI_SHIFT (2U) +#define SPI_ICR_CRFOI_MASK (0x1U << SPI_ICR_CRFOI_SHIFT) /* 0x00000004 */ +#define SPI_ICR_CTFOI_SHIFT (3U) +#define SPI_ICR_CTFOI_MASK (0x1U << SPI_ICR_CTFOI_SHIFT) /* 0x00000008 */ +#define SPI_ICR_CTOI_SHIFT (4U) +#define SPI_ICR_CTOI_MASK (0x1U << SPI_ICR_CTOI_SHIFT) /* 0x00000010 */ +#define SPI_ICR_CSSPI_SHIFT (5U) +#define SPI_ICR_CSSPI_MASK (0x1U << SPI_ICR_CSSPI_SHIFT) /* 0x00000020 */ +#define SPI_ICR_CTXFI_SHIFT (6U) +#define SPI_ICR_CTXFI_MASK (0x1U << SPI_ICR_CTXFI_SHIFT) /* 0x00000040 */ +/* DMACR */ +#define SPI_DMACR_OFFSET (0x3CU) +#define SPI_DMACR_RDE_SHIFT (0U) +#define SPI_DMACR_RDE_MASK (0x1U << SPI_DMACR_RDE_SHIFT) /* 0x00000001 */ +#define SPI_DMACR_TDE_SHIFT (1U) +#define SPI_DMACR_TDE_MASK (0x1U << SPI_DMACR_TDE_SHIFT) /* 0x00000002 */ +/* DMATDLR */ +#define SPI_DMATDLR_OFFSET (0x40U) +#define SPI_DMATDLR_TDL_SHIFT (0U) +#define SPI_DMATDLR_TDL_MASK (0x3FU << SPI_DMATDLR_TDL_SHIFT) /* 0x0000003F */ +/* DMARDLR */ +#define SPI_DMARDLR_OFFSET (0x44U) +#define SPI_DMARDLR_RDL_SHIFT (0U) +#define SPI_DMARDLR_RDL_MASK (0x3FU << SPI_DMARDLR_RDL_SHIFT) /* 0x0000003F */ +/* TIMEOUT */ +#define SPI_TIMEOUT_OFFSET (0x4CU) +#define SPI_TIMEOUT_TOV_SHIFT (0U) +#define SPI_TIMEOUT_TOV_MASK (0xFFFFU << SPI_TIMEOUT_TOV_SHIFT) /* 0x0000FFFF */ +#define SPI_TIMEOUT_TOE_SHIFT (16U) +#define SPI_TIMEOUT_TOE_MASK (0x1U << SPI_TIMEOUT_TOE_SHIFT) /* 0x00010000 */ +/* BYPASS */ +#define SPI_BYPASS_OFFSET (0x50U) +#define SPI_BYPASS_BYEN_SHIFT (0U) +#define SPI_BYPASS_BYEN_MASK (0x1U << SPI_BYPASS_BYEN_SHIFT) /* 0x00000001 */ +#define SPI_BYPASS_FBM_SHIFT (1U) +#define SPI_BYPASS_FBM_MASK (0x1U << SPI_BYPASS_FBM_SHIFT) /* 0x00000002 */ +#define SPI_BYPASS_END_SHIFT (2U) +#define SPI_BYPASS_END_MASK (0x1U << SPI_BYPASS_END_SHIFT) /* 0x00000004 */ +#define SPI_BYPASS_RXCP_SHIFT (3U) +#define SPI_BYPASS_RXCP_MASK (0x1U << SPI_BYPASS_RXCP_SHIFT) /* 0x00000008 */ +#define SPI_BYPASS_TXCP_SHIFT (4U) +#define SPI_BYPASS_TXCP_MASK (0x1U << SPI_BYPASS_TXCP_SHIFT) /* 0x00000010 */ +/* TXDR */ +#define SPI_TXDR_OFFSET (0x400U) +#define SPI_TXDR_TXDR_SHIFT (0U) +#define SPI_TXDR_TXDR_MASK (0xFFFFU << SPI_TXDR_TXDR_SHIFT) /* 0x0000FFFF */ +/* RXDR */ +#define SPI_RXDR_OFFSET (0x800U) +#define SPI_RXDR_RXDR_SHIFT (0U) +#define SPI_RXDR_RXDR_MASK (0xFFFFU << SPI_RXDR_RXDR_SHIFT) /* 0x0000FFFF */ +/******************************************FSPI******************************************/ +/* CTRL0 */ +#define FSPI_CTRL0_OFFSET (0x0U) +#define FSPI_CTRL0_SPIM_SHIFT (0U) +#define FSPI_CTRL0_SPIM_MASK (0x1U << FSPI_CTRL0_SPIM_SHIFT) /* 0x00000001 */ +#define FSPI_CTRL0_SHIFTPHASE_SHIFT (1U) +#define FSPI_CTRL0_SHIFTPHASE_MASK (0x1U << FSPI_CTRL0_SHIFTPHASE_SHIFT) /* 0x00000002 */ +#define FSPI_CTRL0_IDLE_CYCLE_SHIFT (4U) +#define FSPI_CTRL0_IDLE_CYCLE_MASK (0xFU << FSPI_CTRL0_IDLE_CYCLE_SHIFT) /* 0x000000F0 */ +#define FSPI_CTRL0_CMDB_SHIFT (8U) +#define FSPI_CTRL0_CMDB_MASK (0x3U << FSPI_CTRL0_CMDB_SHIFT) /* 0x00000300 */ +#define FSPI_CTRL0_ADRB_SHIFT (10U) +#define FSPI_CTRL0_ADRB_MASK (0x3U << FSPI_CTRL0_ADRB_SHIFT) /* 0x00000C00 */ +#define FSPI_CTRL0_DATB_SHIFT (12U) +#define FSPI_CTRL0_DATB_MASK (0x3U << FSPI_CTRL0_DATB_SHIFT) /* 0x00003000 */ +/* IMR */ +#define FSPI_IMR_OFFSET (0x4U) +#define FSPI_IMR_RXFM_SHIFT (0U) +#define FSPI_IMR_RXFM_MASK (0x1U << FSPI_IMR_RXFM_SHIFT) /* 0x00000001 */ +#define FSPI_IMR_RXUM_SHIFT (1U) +#define FSPI_IMR_RXUM_MASK (0x1U << FSPI_IMR_RXUM_SHIFT) /* 0x00000002 */ +#define FSPI_IMR_TXOM_SHIFT (2U) +#define FSPI_IMR_TXOM_MASK (0x1U << FSPI_IMR_TXOM_SHIFT) /* 0x00000004 */ +#define FSPI_IMR_TXEM_SHIFT (3U) +#define FSPI_IMR_TXEM_MASK (0x1U << FSPI_IMR_TXEM_SHIFT) /* 0x00000008 */ +#define FSPI_IMR_TRANSM_SHIFT (4U) +#define FSPI_IMR_TRANSM_MASK (0x1U << FSPI_IMR_TRANSM_SHIFT) /* 0x00000010 */ +#define FSPI_IMR_AHBM_SHIFT (5U) +#define FSPI_IMR_AHBM_MASK (0x1U << FSPI_IMR_AHBM_SHIFT) /* 0x00000020 */ +#define FSPI_IMR_NSPIM_SHIFT (6U) +#define FSPI_IMR_NSPIM_MASK (0x1U << FSPI_IMR_NSPIM_SHIFT) /* 0x00000040 */ +#define FSPI_IMR_DMAM_SHIFT (7U) +#define FSPI_IMR_DMAM_MASK (0x1U << FSPI_IMR_DMAM_SHIFT) /* 0x00000080 */ +#define FSPI_IMR_STPOLLM_SHIFT (8U) +#define FSPI_IMR_STPOLLM_MASK (0x1U << FSPI_IMR_STPOLLM_SHIFT) /* 0x00000100 */ +/* ICLR */ +#define FSPI_ICLR_OFFSET (0x8U) +#define FSPI_ICLR_RXFC_SHIFT (0U) +#define FSPI_ICLR_RXFC_MASK (0x1U << FSPI_ICLR_RXFC_SHIFT) /* 0x00000001 */ +#define FSPI_ICLR_RXUC_SHIFT (1U) +#define FSPI_ICLR_RXUC_MASK (0x1U << FSPI_ICLR_RXUC_SHIFT) /* 0x00000002 */ +#define FSPI_ICLR_TXOC_SHIFT (2U) +#define FSPI_ICLR_TXOC_MASK (0x1U << FSPI_ICLR_TXOC_SHIFT) /* 0x00000004 */ +#define FSPI_ICLR_TXEC_SHIFT (3U) +#define FSPI_ICLR_TXEC_MASK (0x1U << FSPI_ICLR_TXEC_SHIFT) /* 0x00000008 */ +#define FSPI_ICLR_TRANSC_SHIFT (4U) +#define FSPI_ICLR_TRANSC_MASK (0x1U << FSPI_ICLR_TRANSC_SHIFT) /* 0x00000010 */ +#define FSPI_ICLR_AHBC_SHIFT (5U) +#define FSPI_ICLR_AHBC_MASK (0x1U << FSPI_ICLR_AHBC_SHIFT) /* 0x00000020 */ +#define FSPI_ICLR_NSPIC_SHIFT (6U) +#define FSPI_ICLR_NSPIC_MASK (0x1U << FSPI_ICLR_NSPIC_SHIFT) /* 0x00000040 */ +#define FSPI_ICLR_DMAC_SHIFT (7U) +#define FSPI_ICLR_DMAC_MASK (0x1U << FSPI_ICLR_DMAC_SHIFT) /* 0x00000080 */ +#define FSPI_ICLR_STPOLLC_SHIFT (8U) +#define FSPI_ICLR_STPOLLC_MASK (0x1U << FSPI_ICLR_STPOLLC_SHIFT) /* 0x00000100 */ +/* FTLR */ +#define FSPI_FTLR_OFFSET (0xCU) +#define FSPI_FTLR_TXFTLR_SHIFT (0U) +#define FSPI_FTLR_TXFTLR_MASK (0xFFU << FSPI_FTLR_TXFTLR_SHIFT) /* 0x000000FF */ +#define FSPI_FTLR_RXFTLR_SHIFT (8U) +#define FSPI_FTLR_RXFTLR_MASK (0xFFU << FSPI_FTLR_RXFTLR_SHIFT) /* 0x0000FF00 */ +/* RCVR */ +#define FSPI_RCVR_OFFSET (0x10U) +#define FSPI_RCVR_RCVR_SHIFT (0U) +#define FSPI_RCVR_RCVR_MASK (0x1U << FSPI_RCVR_RCVR_SHIFT) /* 0x00000001 */ +/* AX0 */ +#define FSPI_AX0_OFFSET (0x14U) +#define FSPI_AX0_AX_SHIFT (0U) +#define FSPI_AX0_AX_MASK (0xFFU << FSPI_AX0_AX_SHIFT) /* 0x000000FF */ +/* ABIT0 */ +#define FSPI_ABIT0_OFFSET (0x18U) +#define FSPI_ABIT0_ABIT_SHIFT (0U) +#define FSPI_ABIT0_ABIT_MASK (0x1FU << FSPI_ABIT0_ABIT_SHIFT) /* 0x0000001F */ +/* ISR */ +#define FSPI_ISR_OFFSET (0x1CU) +#define FSPI_ISR_RXFS_SHIFT (0U) +#define FSPI_ISR_RXFS_MASK (0x1U << FSPI_ISR_RXFS_SHIFT) /* 0x00000001 */ +#define FSPI_ISR_RXUS_SHIFT (1U) +#define FSPI_ISR_RXUS_MASK (0x1U << FSPI_ISR_RXUS_SHIFT) /* 0x00000002 */ +#define FSPI_ISR_TXOS_SHIFT (2U) +#define FSPI_ISR_TXOS_MASK (0x1U << FSPI_ISR_TXOS_SHIFT) /* 0x00000004 */ +#define FSPI_ISR_TXES_SHIFT (3U) +#define FSPI_ISR_TXES_MASK (0x1U << FSPI_ISR_TXES_SHIFT) /* 0x00000008 */ +#define FSPI_ISR_TRANSS_SHIFT (4U) +#define FSPI_ISR_TRANSS_MASK (0x1U << FSPI_ISR_TRANSS_SHIFT) /* 0x00000010 */ +#define FSPI_ISR_AHBS_SHIFT (5U) +#define FSPI_ISR_AHBS_MASK (0x1U << FSPI_ISR_AHBS_SHIFT) /* 0x00000020 */ +#define FSPI_ISR_NSPIS_SHIFT (6U) +#define FSPI_ISR_NSPIS_MASK (0x1U << FSPI_ISR_NSPIS_SHIFT) /* 0x00000040 */ +#define FSPI_ISR_DMAS_SHIFT (7U) +#define FSPI_ISR_DMAS_MASK (0x1U << FSPI_ISR_DMAS_SHIFT) /* 0x00000080 */ +#define FSPI_ISR_STPOLLS_SHIFT (8U) +#define FSPI_ISR_STPOLLS_MASK (0x1U << FSPI_ISR_STPOLLS_SHIFT) /* 0x00000100 */ +/* FSR */ +#define FSPI_FSR_OFFSET (0x20U) +#define FSPI_FSR_TXFS_SHIFT (0U) +#define FSPI_FSR_TXFS_MASK (0x1U << FSPI_FSR_TXFS_SHIFT) /* 0x00000001 */ +#define FSPI_FSR_TXES_SHIFT (1U) +#define FSPI_FSR_TXES_MASK (0x1U << FSPI_FSR_TXES_SHIFT) /* 0x00000002 */ +#define FSPI_FSR_RXES_SHIFT (2U) +#define FSPI_FSR_RXES_MASK (0x1U << FSPI_FSR_RXES_SHIFT) /* 0x00000004 */ +#define FSPI_FSR_RXFS_SHIFT (3U) +#define FSPI_FSR_RXFS_MASK (0x1U << FSPI_FSR_RXFS_SHIFT) /* 0x00000008 */ +#define FSPI_FSR_TXWLVL_SHIFT (8U) +#define FSPI_FSR_TXWLVL_MASK (0x1FU << FSPI_FSR_TXWLVL_SHIFT) /* 0x00001F00 */ +#define FSPI_FSR_RXWLVL_SHIFT (16U) +#define FSPI_FSR_RXWLVL_MASK (0x1FU << FSPI_FSR_RXWLVL_SHIFT) /* 0x001F0000 */ +/* SR */ +#define FSPI_SR_OFFSET (0x24U) +#define FSPI_SR (0x0U) +#define FSPI_SR_SR_SHIFT (0U) +#define FSPI_SR_SR_MASK (0x1U << FSPI_SR_SR_SHIFT) /* 0x00000001 */ +/* RISR */ +#define FSPI_RISR_OFFSET (0x28U) +#define FSPI_RISR (0x0U) +#define FSPI_RISR_RXFS_SHIFT (0U) +#define FSPI_RISR_RXFS_MASK (0x1U << FSPI_RISR_RXFS_SHIFT) /* 0x00000001 */ +#define FSPI_RISR_RXUS_SHIFT (1U) +#define FSPI_RISR_RXUS_MASK (0x1U << FSPI_RISR_RXUS_SHIFT) /* 0x00000002 */ +#define FSPI_RISR_TXOS_SHIFT (2U) +#define FSPI_RISR_TXOS_MASK (0x1U << FSPI_RISR_TXOS_SHIFT) /* 0x00000004 */ +#define FSPI_RISR_TXES_SHIFT (3U) +#define FSPI_RISR_TXES_MASK (0x1U << FSPI_RISR_TXES_SHIFT) /* 0x00000008 */ +#define FSPI_RISR_TRANSS_SHIFT (4U) +#define FSPI_RISR_TRANSS_MASK (0x1U << FSPI_RISR_TRANSS_SHIFT) /* 0x00000010 */ +#define FSPI_RISR_AHBS_SHIFT (5U) +#define FSPI_RISR_AHBS_MASK (0x1U << FSPI_RISR_AHBS_SHIFT) /* 0x00000020 */ +#define FSPI_RISR_NSPIS_SHIFT (6U) +#define FSPI_RISR_NSPIS_MASK (0x1U << FSPI_RISR_NSPIS_SHIFT) /* 0x00000040 */ +#define FSPI_RISR_DMAS_SHIFT (7U) +#define FSPI_RISR_DMAS_MASK (0x1U << FSPI_RISR_DMAS_SHIFT) /* 0x00000080 */ +#define FSPI_RISR_STPOLLS_SHIFT (8U) +#define FSPI_RISR_STPOLLS_MASK (0x1U << FSPI_RISR_STPOLLS_SHIFT) /* 0x00000100 */ +/* VER */ +#define FSPI_VER_OFFSET (0x2CU) +#define FSPI_VER (0x3U) +#define FSPI_VER_VER_SHIFT (0U) +#define FSPI_VER_VER_MASK (0xFFFFU << FSPI_VER_VER_SHIFT) /* 0x0000FFFF */ +/* QOP */ +#define FSPI_QOP_OFFSET (0x30U) +#define FSPI_QOP_SO123_SHIFT (0U) +#define FSPI_QOP_SO123_MASK (0x1U << FSPI_QOP_SO123_SHIFT) /* 0x00000001 */ +#define FSPI_QOP_SO123BP_SHIFT (1U) +#define FSPI_QOP_SO123BP_MASK (0x1U << FSPI_QOP_SO123BP_SHIFT) /* 0x00000002 */ +/* EXT_CTRL */ +#define FSPI_EXT_CTRL_OFFSET (0x34U) +#define FSPI_EXT_CTRL_CS_DESEL_CTRL_SHIFT (0U) +#define FSPI_EXT_CTRL_CS_DESEL_CTRL_MASK (0xFU << FSPI_EXT_CTRL_CS_DESEL_CTRL_SHIFT) /* 0x0000000F */ +#define FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_SHIFT (4U) +#define FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_MASK (0xFU << FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_SHIFT) /* 0x000000F0 */ +#define FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_SHIFT (8U) +#define FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_MASK (0xFU << FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_SHIFT) /* 0x00000F00 */ +#define FSPI_EXT_CTRL_TRANS_INT_MODE_SHIFT (13U) +#define FSPI_EXT_CTRL_TRANS_INT_MODE_MASK (0x1U << FSPI_EXT_CTRL_TRANS_INT_MODE_SHIFT) /* 0x00002000 */ +#define FSPI_EXT_CTRL_SR_GEN_MODE_SHIFT (14U) +#define FSPI_EXT_CTRL_SR_GEN_MODE_MASK (0x1U << FSPI_EXT_CTRL_SR_GEN_MODE_SHIFT) /* 0x00004000 */ +/* POLL_CTRL */ +#define FSPI_POLL_CTRL_OFFSET (0x38U) +#define FSPI_POLL_CTRL_ST_POLL_EN_SHIFT (0U) +#define FSPI_POLL_CTRL_ST_POLL_EN_MASK (0x1U << FSPI_POLL_CTRL_ST_POLL_EN_SHIFT) /* 0x00000001 */ +#define FSPI_POLL_CTRL_POLL_DLY_EN_SHIFT (1U) +#define FSPI_POLL_CTRL_POLL_DLY_EN_MASK (0x1U << FSPI_POLL_CTRL_POLL_DLY_EN_SHIFT) /* 0x00000002 */ +#define FSPI_POLL_CTRL_ST_POLL_CMD_PARA_SHIFT (8U) +#define FSPI_POLL_CTRL_ST_POLL_CMD_PARA_MASK (0xFFU << FSPI_POLL_CTRL_ST_POLL_CMD_PARA_SHIFT) /* 0x0000FF00 */ +#define FSPI_POLL_CTRL_ST_POLL_EXPECT_DATA_SHIFT (16U) +#define FSPI_POLL_CTRL_ST_POLL_EXPECT_DATA_MASK (0xFFU << FSPI_POLL_CTRL_ST_POLL_EXPECT_DATA_SHIFT) /* 0x00FF0000 */ +#define FSPI_POLL_CTRL_ST_POLL_BIT_COMP_EN_SHIFT (24U) +#define FSPI_POLL_CTRL_ST_POLL_BIT_COMP_EN_MASK (0xFFU << FSPI_POLL_CTRL_ST_POLL_BIT_COMP_EN_SHIFT) /* 0xFF000000 */ +/* DLL_CTRL0 */ +#define FSPI_DLL_CTRL0_OFFSET (0x3CU) +#define FSPI_DLL_CTRL0_SMP_DLL_CFG_SHIFT (0U) +#define FSPI_DLL_CTRL0_SMP_DLL_CFG_MASK (0xFFU << FSPI_DLL_CTRL0_SMP_DLL_CFG_SHIFT) /* 0x000000FF */ +#define FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT (8U) +#define FSPI_DLL_CTRL0_SCLK_SMP_SEL_MASK (0x1U << FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT) /* 0x00000100 */ +/* HRDYMASK */ +#define FSPI_HRDYMASK_OFFSET (0x40U) +#define FSPI_HRDYMASK_HRDYMASK_SHIFT (0U) +#define FSPI_HRDYMASK_HRDYMASK_MASK (0x1U << FSPI_HRDYMASK_HRDYMASK_SHIFT) /* 0x00000001 */ +/* EXT_AX */ +#define FSPI_EXT_AX_OFFSET (0x44U) +#define FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT (0U) +#define FSPI_EXT_AX_AX_CANCEL_PAT_MASK (0xFFU << FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT) /* 0x000000FF */ +#define FSPI_EXT_AX_AX_SETUP_PAT_SHIFT (8U) +#define FSPI_EXT_AX_AX_SETUP_PAT_MASK (0xFFU << FSPI_EXT_AX_AX_SETUP_PAT_SHIFT) /* 0x0000FF00 */ +/* SCLK_INATM_CNT */ +#define FSPI_SCLK_INATM_CNT_OFFSET (0x48U) +#define FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_SHIFT (0U) +#define FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_MASK (0xFFFFFFFFU << FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* AUTO_RF_CNT */ +#define FSPI_AUTO_RF_CNT_OFFSET (0x4CU) +#define FSPI_AUTO_RF_CNT_AUTO_RF_CNT_SHIFT (0U) +#define FSPI_AUTO_RF_CNT_AUTO_RF_CNT_MASK (0xFFFFFFFFU << FSPI_AUTO_RF_CNT_AUTO_RF_CNT_SHIFT) /* 0xFFFFFFFF */ +/* XMMC_WCMD0 */ +#define FSPI_XMMC_WCMD0_OFFSET (0x50U) +#define FSPI_XMMC_WCMD0_CMD_SHIFT (0U) +#define FSPI_XMMC_WCMD0_CMD_MASK (0xFFU << FSPI_XMMC_WCMD0_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_WCMD0_DUMM_SHIFT (8U) +#define FSPI_XMMC_WCMD0_DUMM_MASK (0xFU << FSPI_XMMC_WCMD0_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_WCMD0_CONT_SHIFT (13U) +#define FSPI_XMMC_WCMD0_CONT_MASK (0x1U << FSPI_XMMC_WCMD0_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_WCMD0_ADDRB_SHIFT (14U) +#define FSPI_XMMC_WCMD0_ADDRB_MASK (0x3U << FSPI_XMMC_WCMD0_ADDRB_SHIFT) /* 0x0000C000 */ +/* XMMC_RCMD0 */ +#define FSPI_XMMC_RCMD0_OFFSET (0x54U) +#define FSPI_XMMC_RCMD0_CMD_SHIFT (0U) +#define FSPI_XMMC_RCMD0_CMD_MASK (0xFFU << FSPI_XMMC_RCMD0_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_RCMD0_DUMM_SHIFT (8U) +#define FSPI_XMMC_RCMD0_DUMM_MASK (0xFU << FSPI_XMMC_RCMD0_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_RCMD0_CONT_SHIFT (13U) +#define FSPI_XMMC_RCMD0_CONT_MASK (0x1U << FSPI_XMMC_RCMD0_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_RCMD0_ADDRB_SHIFT (14U) +#define FSPI_XMMC_RCMD0_ADDRB_MASK (0x3U << FSPI_XMMC_RCMD0_ADDRB_SHIFT) /* 0x0000C000 */ +/* XMMC_CTRL */ +#define FSPI_XMMC_CTRL_OFFSET (0x58U) +#define FSPI_XMMC_CTRL_DEV_HWEN_SHIFT (5U) +#define FSPI_XMMC_CTRL_DEV_HWEN_MASK (0x1U << FSPI_XMMC_CTRL_DEV_HWEN_SHIFT) /* 0x00000020 */ +#define FSPI_XMMC_CTRL_PFT_EN_SHIFT (6U) +#define FSPI_XMMC_CTRL_PFT_EN_MASK (0x1U << FSPI_XMMC_CTRL_PFT_EN_SHIFT) /* 0x00000040 */ +/* MODE */ +#define FSPI_MODE_OFFSET (0x5CU) +#define FSPI_MODE_XMMC_MODE_EN_SHIFT (0U) +#define FSPI_MODE_XMMC_MODE_EN_MASK (0x1U << FSPI_MODE_XMMC_MODE_EN_SHIFT) /* 0x00000001 */ +/* DEVRGN */ +#define FSPI_DEVRGN_OFFSET (0x60U) +#define FSPI_DEVRGN_RSIZE_SHIFT (0U) +#define FSPI_DEVRGN_RSIZE_MASK (0x1FU << FSPI_DEVRGN_RSIZE_SHIFT) /* 0x0000001F */ +/* DEVSIZE0 */ +#define FSPI_DEVSIZE0_OFFSET (0x64U) +#define FSPI_DEVSIZE0_DSIZE_SHIFT (0U) +#define FSPI_DEVSIZE0_DSIZE_MASK (0x1FU << FSPI_DEVSIZE0_DSIZE_SHIFT) /* 0x0000001F */ +/* TME0 */ +#define FSPI_TME0_OFFSET (0x68U) +#define FSPI_TME0_AUTO_RF_EN_SHIFT (0U) +#define FSPI_TME0_AUTO_RF_EN_MASK (0x1U << FSPI_TME0_AUTO_RF_EN_SHIFT) /* 0x00000001 */ +#define FSPI_TME0_SCLK_INATM_EN_SHIFT (1U) +#define FSPI_TME0_SCLK_INATM_EN_MASK (0x1U << FSPI_TME0_SCLK_INATM_EN_SHIFT) /* 0x00000002 */ +/* POLLDLY_CTRL */ +#define FSPI_POLLDLY_CTRL_OFFSET (0x6CU) +#define FSPI_POLLDLY_CTRL_CNT_SHIFT (0U) +#define FSPI_POLLDLY_CTRL_CNT_MASK (0x7FFFFFFFU << FSPI_POLLDLY_CTRL_CNT_SHIFT) /* 0x7FFFFFFF */ +#define FSPI_POLLDLY_CTRL_POLLDLY_IP_SHIFT (31U) +#define FSPI_POLLDLY_CTRL_POLLDLY_IP_MASK (0x1U << FSPI_POLLDLY_CTRL_POLLDLY_IP_SHIFT) /* 0x80000000 */ +/* DMATR */ +#define FSPI_DMATR_OFFSET (0x80U) +#define FSPI_DMATR_DMATR_SHIFT (0U) +#define FSPI_DMATR_DMATR_MASK (0x1U << FSPI_DMATR_DMATR_SHIFT) /* 0x00000001 */ +/* DMAADDR */ +#define FSPI_DMAADDR_OFFSET (0x84U) +#define FSPI_DMAADDR_DMAADDR_SHIFT (0U) +#define FSPI_DMAADDR_DMAADDR_MASK (0xFFFFFFFFU << FSPI_DMAADDR_DMAADDR_SHIFT) /* 0xFFFFFFFF */ +/* POLL_DATA */ +#define FSPI_POLL_DATA_OFFSET (0x90U) +#define FSPI_POLL_DATA (0x0U) +#define FSPI_POLL_DATA_POLL_DATA_SHIFT (0U) +#define FSPI_POLL_DATA_POLL_DATA_MASK (0xFFU << FSPI_POLL_DATA_POLL_DATA_SHIFT) /* 0x000000FF */ +#define FSPI_POLL_DATA_POLL_STA_SHIFT (8U) +#define FSPI_POLL_DATA_POLL_STA_MASK (0x1U << FSPI_POLL_DATA_POLL_STA_SHIFT) /* 0x00000100 */ +/* XMMCSR */ +#define FSPI_XMMCSR_OFFSET (0x94U) +#define FSPI_XMMCSR_SLOPOVER0_SHIFT (0U) +#define FSPI_XMMCSR_SLOPOVER0_MASK (0x1U << FSPI_XMMCSR_SLOPOVER0_SHIFT) /* 0x00000001 */ +#define FSPI_XMMCSR_SLOPOVER1_SHIFT (1U) +#define FSPI_XMMCSR_SLOPOVER1_MASK (0x1U << FSPI_XMMCSR_SLOPOVER1_SHIFT) /* 0x00000002 */ +/* CMD */ +#define FSPI_CMD_OFFSET (0x100U) +#define FSPI_CMD_CMD_SHIFT (0U) +#define FSPI_CMD_CMD_MASK (0xFFU << FSPI_CMD_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_CMD_DUMM_SHIFT (8U) +#define FSPI_CMD_DUMM_MASK (0xFU << FSPI_CMD_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_CMD_WR_SHIFT (12U) +#define FSPI_CMD_WR_MASK (0x1U << FSPI_CMD_WR_SHIFT) /* 0x00001000 */ +#define FSPI_CMD_CONT_SHIFT (13U) +#define FSPI_CMD_CONT_MASK (0x1U << FSPI_CMD_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_CMD_ADDRB_SHIFT (14U) +#define FSPI_CMD_ADDRB_MASK (0x3U << FSPI_CMD_ADDRB_SHIFT) /* 0x0000C000 */ +#define FSPI_CMD_TRB_SHIFT (16U) +#define FSPI_CMD_TRB_MASK (0x3FFFU << FSPI_CMD_TRB_SHIFT) /* 0x3FFF0000 */ +#define FSPI_CMD_CS_SHIFT (30U) +#define FSPI_CMD_CS_MASK (0x3U << FSPI_CMD_CS_SHIFT) /* 0xC0000000 */ +/* ADDR */ +#define FSPI_ADDR_OFFSET (0x104U) +#define FSPI_ADDR_ADDR_SHIFT (0U) +#define FSPI_ADDR_ADDR_MASK (0xFFFFFFFFU << FSPI_ADDR_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* DATA */ +#define FSPI_DATA_OFFSET (0x108U) +#define FSPI_DATA_DATA_SHIFT (0U) +#define FSPI_DATA_DATA_MASK (0xFFFFFFFFU << FSPI_DATA_DATA_SHIFT) /* 0xFFFFFFFF */ +/* CTRL1 */ +#define FSPI_CTRL1_OFFSET (0x200U) +#define FSPI_CTRL1_SPIM_SHIFT (0U) +#define FSPI_CTRL1_SPIM_MASK (0x1U << FSPI_CTRL1_SPIM_SHIFT) /* 0x00000001 */ +#define FSPI_CTRL1_SHIFTPHASE_SHIFT (1U) +#define FSPI_CTRL1_SHIFTPHASE_MASK (0x1U << FSPI_CTRL1_SHIFTPHASE_SHIFT) /* 0x00000002 */ +#define FSPI_CTRL1_IDLE_CYCLE_SHIFT (4U) +#define FSPI_CTRL1_IDLE_CYCLE_MASK (0xFU << FSPI_CTRL1_IDLE_CYCLE_SHIFT) /* 0x000000F0 */ +#define FSPI_CTRL1_CMDB_SHIFT (8U) +#define FSPI_CTRL1_CMDB_MASK (0x3U << FSPI_CTRL1_CMDB_SHIFT) /* 0x00000300 */ +#define FSPI_CTRL1_ADRB_SHIFT (10U) +#define FSPI_CTRL1_ADRB_MASK (0x3U << FSPI_CTRL1_ADRB_SHIFT) /* 0x00000C00 */ +#define FSPI_CTRL1_DATB_SHIFT (12U) +#define FSPI_CTRL1_DATB_MASK (0x3U << FSPI_CTRL1_DATB_SHIFT) /* 0x00003000 */ +/* AX1 */ +#define FSPI_AX1_OFFSET (0x214U) +#define FSPI_AX1_AX_SHIFT (0U) +#define FSPI_AX1_AX_MASK (0xFFU << FSPI_AX1_AX_SHIFT) /* 0x000000FF */ +/* ABIT1 */ +#define FSPI_ABIT1_OFFSET (0x218U) +#define FSPI_ABIT1_ABIT_SHIFT (0U) +#define FSPI_ABIT1_ABIT_MASK (0x1FU << FSPI_ABIT1_ABIT_SHIFT) /* 0x0000001F */ +/* DLL_CTRL1 */ +#define FSPI_DLL_CTRL1_OFFSET (0x23CU) +#define FSPI_DLL_CTRL1_SMP_DLL_CFG_SHIFT (0U) +#define FSPI_DLL_CTRL1_SMP_DLL_CFG_MASK (0xFFU << FSPI_DLL_CTRL1_SMP_DLL_CFG_SHIFT) /* 0x000000FF */ +#define FSPI_DLL_CTRL1_SCLK_SMP_SEL_SHIFT (8U) +#define FSPI_DLL_CTRL1_SCLK_SMP_SEL_MASK (0x1U << FSPI_DLL_CTRL1_SCLK_SMP_SEL_SHIFT) /* 0x00000100 */ +/* XMMC_WCMD1 */ +#define FSPI_XMMC_WCMD1_OFFSET (0x250U) +#define FSPI_XMMC_WCMD1_CMD_SHIFT (0U) +#define FSPI_XMMC_WCMD1_CMD_MASK (0xFFU << FSPI_XMMC_WCMD1_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_WCMD1_DUMM_SHIFT (8U) +#define FSPI_XMMC_WCMD1_DUMM_MASK (0xFU << FSPI_XMMC_WCMD1_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_WCMD1_CONT_SHIFT (13U) +#define FSPI_XMMC_WCMD1_CONT_MASK (0x1U << FSPI_XMMC_WCMD1_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_WCMD1_ADDRB_SHIFT (14U) +#define FSPI_XMMC_WCMD1_ADDRB_MASK (0x3U << FSPI_XMMC_WCMD1_ADDRB_SHIFT) /* 0x0000C000 */ +/* XMMC_RCMD1 */ +#define FSPI_XMMC_RCMD1_OFFSET (0x254U) +#define FSPI_XMMC_RCMD1_CMD_SHIFT (0U) +#define FSPI_XMMC_RCMD1_CMD_MASK (0xFFU << FSPI_XMMC_RCMD1_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_RCMD1_DUMM_SHIFT (8U) +#define FSPI_XMMC_RCMD1_DUMM_MASK (0xFU << FSPI_XMMC_RCMD1_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_RCMD1_CONT_SHIFT (13U) +#define FSPI_XMMC_RCMD1_CONT_MASK (0x1U << FSPI_XMMC_RCMD1_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_RCMD1_ADDRB_SHIFT (14U) +#define FSPI_XMMC_RCMD1_ADDRB_MASK (0x3U << FSPI_XMMC_RCMD1_ADDRB_SHIFT) /* 0x0000C000 */ +/* DEVSIZE1 */ +#define FSPI_DEVSIZE1_OFFSET (0x264U) +#define FSPI_DEVSIZE1_DSIZE_SHIFT (0U) +#define FSPI_DEVSIZE1_DSIZE_MASK (0x1FU << FSPI_DEVSIZE1_DSIZE_SHIFT) /* 0x0000001F */ +/* TME1 */ +#define FSPI_TME1_OFFSET (0x268U) +#define FSPI_TME1_AUTO_RF_EN_SHIFT (0U) +#define FSPI_TME1_AUTO_RF_EN_MASK (0x1U << FSPI_TME1_AUTO_RF_EN_SHIFT) /* 0x00000001 */ +#define FSPI_TME1_SCLK_INATM_EN_SHIFT (1U) +#define FSPI_TME1_SCLK_INATM_EN_MASK (0x1U << FSPI_TME1_SCLK_INATM_EN_SHIFT) /* 0x00000002 */ +/******************************************MMC*******************************************/ +/* CTRL */ +#define MMC_CTRL_OFFSET (0x0U) +#define MMC_CTRL_CONTROLLER_RESET_SHIFT (0U) +#define MMC_CTRL_CONTROLLER_RESET_MASK (0x1U << MMC_CTRL_CONTROLLER_RESET_SHIFT) /* 0x00000001 */ +#define MMC_CTRL_FIFO_RESET_SHIFT (1U) +#define MMC_CTRL_FIFO_RESET_MASK (0x1U << MMC_CTRL_FIFO_RESET_SHIFT) /* 0x00000002 */ +#define MMC_CTRL_DMA_RESET_SHIFT (2U) +#define MMC_CTRL_DMA_RESET_MASK (0x1U << MMC_CTRL_DMA_RESET_SHIFT) /* 0x00000004 */ +#define MMC_CTRL_INT_ENABLE_SHIFT (4U) +#define MMC_CTRL_INT_ENABLE_MASK (0x1U << MMC_CTRL_INT_ENABLE_SHIFT) /* 0x00000010 */ +#define MMC_CTRL_DMA_ENABLE_SHIFT (5U) +#define MMC_CTRL_DMA_ENABLE_MASK (0x1U << MMC_CTRL_DMA_ENABLE_SHIFT) /* 0x00000020 */ +#define MMC_CTRL_READ_WAIT_SHIFT (6U) +#define MMC_CTRL_READ_WAIT_MASK (0x1U << MMC_CTRL_READ_WAIT_SHIFT) /* 0x00000040 */ +#define MMC_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +#define MMC_CTRL_SEND_IRQ_RESPONSE_MASK (0x1U << MMC_CTRL_SEND_IRQ_RESPONSE_SHIFT) /* 0x00000080 */ +#define MMC_CTRL_ABORT_READ_DATA_SHIFT (8U) +#define MMC_CTRL_ABORT_READ_DATA_MASK (0x1U << MMC_CTRL_ABORT_READ_DATA_SHIFT) /* 0x00000100 */ +#define MMC_CTRL_SEND_CCSD_SHIFT (9U) +#define MMC_CTRL_SEND_CCSD_MASK (0x1U << MMC_CTRL_SEND_CCSD_SHIFT) /* 0x00000200 */ +#define MMC_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +#define MMC_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x1U << MMC_CTRL_SEND_AUTO_STOP_CCSD_SHIFT) /* 0x00000400 */ +#define MMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +#define MMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x1U << MMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT) /* 0x00000800 */ +#define MMC_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +#define MMC_CTRL_USE_INTERNAL_DMAC_MASK (0x1U << MMC_CTRL_USE_INTERNAL_DMAC_SHIFT) /* 0x02000000 */ +/* PWREN */ +#define MMC_PWREN_OFFSET (0x4U) +#define MMC_PWREN_POWER_ENABLE_SHIFT (0U) +#define MMC_PWREN_POWER_ENABLE_MASK (0x1U << MMC_PWREN_POWER_ENABLE_SHIFT) /* 0x00000001 */ +/* CLKDIV */ +#define MMC_CLKDIV_OFFSET (0x8U) +#define MMC_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +#define MMC_CLKDIV_CLK_DIVIDER0_MASK (0xFFU << MMC_CLKDIV_CLK_DIVIDER0_SHIFT) /* 0x000000FF */ +/* CLKSRC */ +#define MMC_CLKSRC_OFFSET (0xCU) +#define MMC_CLKSRC_CLK_SOURCE_SHIFT (0U) +#define MMC_CLKSRC_CLK_SOURCE_MASK (0x3U << MMC_CLKSRC_CLK_SOURCE_SHIFT) /* 0x00000003 */ +/* CLKENA */ +#define MMC_CLKENA_OFFSET (0x10U) +#define MMC_CLKENA_CCLK_ENABLE_SHIFT (0U) +#define MMC_CLKENA_CCLK_ENABLE_MASK (0x1U << MMC_CLKENA_CCLK_ENABLE_SHIFT) /* 0x00000001 */ +#define MMC_CLKENA_CCLK_LOW_POWER_SHIFT (16U) +#define MMC_CLKENA_CCLK_LOW_POWER_MASK (0x1U << MMC_CLKENA_CCLK_LOW_POWER_SHIFT) /* 0x00010000 */ +/* TMOUT */ +#define MMC_TMOUT_OFFSET (0x14U) +#define MMC_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +#define MMC_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU << MMC_TMOUT_RESPONSE_TIMEOUT_SHIFT) /* 0x000000FF */ +#define MMC_TMOUT_DATA_TIMEOUT_SHIFT (8U) +#define MMC_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFFU << MMC_TMOUT_DATA_TIMEOUT_SHIFT) /* 0xFFFFFF00 */ +/* CTYPE */ +#define MMC_CTYPE_OFFSET (0x18U) +#define MMC_CTYPE_CARD_WIDTH_SHIFT (0U) +#define MMC_CTYPE_CARD_WIDTH_MASK (0x1U << MMC_CTYPE_CARD_WIDTH_SHIFT) /* 0x00000001 */ +#define MMC_CTYPE_CARD_WIDTH_8_SHIFT (16U) +#define MMC_CTYPE_CARD_WIDTH_8_MASK (0x1U << MMC_CTYPE_CARD_WIDTH_8_SHIFT) /* 0x00010000 */ +/* BLKSIZ */ +#define MMC_BLKSIZ_OFFSET (0x1CU) +#define MMC_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +#define MMC_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU << MMC_BLKSIZ_BLOCK_SIZE_SHIFT) /* 0x0000FFFF */ +/* BYTCNT */ +#define MMC_BYTCNT_OFFSET (0x20U) +#define MMC_BYTCNT_BYTE_COUNT_SHIFT (0U) +#define MMC_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU << MMC_BYTCNT_BYTE_COUNT_SHIFT) /* 0xFFFFFFFF */ +/* INTMASK */ +#define MMC_INTMASK_OFFSET (0x24U) +#define MMC_INTMASK_INT_MASK_SHIFT (0U) +#define MMC_INTMASK_INT_MASK_MASK (0xFFFFU << MMC_INTMASK_INT_MASK_SHIFT) /* 0x0000FFFF */ +#define MMC_INTMASK_DATA_NOBUSY_INT_MASK_SHIFT (16U) +#define MMC_INTMASK_DATA_NOBUSY_INT_MASK_MASK (0x1U << MMC_INTMASK_DATA_NOBUSY_INT_MASK_SHIFT) /* 0x00010000 */ +#define MMC_INTMASK_SDIO_INT_MASK_SHIFT (24U) +#define MMC_INTMASK_SDIO_INT_MASK_MASK (0x1U << MMC_INTMASK_SDIO_INT_MASK_SHIFT) /* 0x01000000 */ +/* CMDARG */ +#define MMC_CMDARG_OFFSET (0x28U) +#define MMC_CMDARG_CMD_ARG_SHIFT (0U) +#define MMC_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU << MMC_CMDARG_CMD_ARG_SHIFT) /* 0xFFFFFFFF */ +/* CMD */ +#define MMC_CMD_OFFSET (0x2CU) +#define MMC_CMD_CMD_INDEX_SHIFT (0U) +#define MMC_CMD_CMD_INDEX_MASK (0x3FU << MMC_CMD_CMD_INDEX_SHIFT) /* 0x0000003F */ +#define MMC_CMD_RESPONSE_EXPECT_SHIFT (6U) +#define MMC_CMD_RESPONSE_EXPECT_MASK (0x1U << MMC_CMD_RESPONSE_EXPECT_SHIFT) /* 0x00000040 */ +#define MMC_CMD_RESPONSE_LENGTH_SHIFT (7U) +#define MMC_CMD_RESPONSE_LENGTH_MASK (0x1U << MMC_CMD_RESPONSE_LENGTH_SHIFT) /* 0x00000080 */ +#define MMC_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +#define MMC_CMD_CHECK_RESPONSE_CRC_MASK (0x1U << MMC_CMD_CHECK_RESPONSE_CRC_SHIFT) /* 0x00000100 */ +#define MMC_CMD_DATA_EXPECTED_SHIFT (9U) +#define MMC_CMD_DATA_EXPECTED_MASK (0x1U << MMC_CMD_DATA_EXPECTED_SHIFT) /* 0x00000200 */ +#define MMC_CMD_WR_SHIFT (10U) +#define MMC_CMD_WR_MASK (0x1U << MMC_CMD_WR_SHIFT) /* 0x00000400 */ +#define MMC_CMD_TRANSFER_MODE_SHIFT (11U) +#define MMC_CMD_TRANSFER_MODE_MASK (0x1U << MMC_CMD_TRANSFER_MODE_SHIFT) /* 0x00000800 */ +#define MMC_CMD_SEND_AUTO_STOP_SHIFT (12U) +#define MMC_CMD_SEND_AUTO_STOP_MASK (0x1U << MMC_CMD_SEND_AUTO_STOP_SHIFT) /* 0x00001000 */ +#define MMC_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +#define MMC_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x1U << MMC_CMD_WAIT_PRVDATA_COMPLETE_SHIFT) /* 0x00002000 */ +#define MMC_CMD_STOP_ABORT_CMD_SHIFT (14U) +#define MMC_CMD_STOP_ABORT_CMD_MASK (0x1U << MMC_CMD_STOP_ABORT_CMD_SHIFT) /* 0x00004000 */ +#define MMC_CMD_SEND_INITIALIZATION_SHIFT (15U) +#define MMC_CMD_SEND_INITIALIZATION_MASK (0x1U << MMC_CMD_SEND_INITIALIZATION_SHIFT) /* 0x00008000 */ +#define MMC_CMD_UPDATE_CLOCK_REGS_ONLY_SHIFT (21U) +#define MMC_CMD_UPDATE_CLOCK_REGS_ONLY_MASK (0x1U << MMC_CMD_UPDATE_CLOCK_REGS_ONLY_SHIFT) /* 0x00200000 */ +#define MMC_CMD_READ_CEATA_DEVICE_SHIFT (22U) +#define MMC_CMD_READ_CEATA_DEVICE_MASK (0x1U << MMC_CMD_READ_CEATA_DEVICE_SHIFT) /* 0x00400000 */ +#define MMC_CMD_CCS_EXPECTED_SHIFT (23U) +#define MMC_CMD_CCS_EXPECTED_MASK (0x1U << MMC_CMD_CCS_EXPECTED_SHIFT) /* 0x00800000 */ +#define MMC_CMD_ENABLE_BOOT_SHIFT (24U) +#define MMC_CMD_ENABLE_BOOT_MASK (0x1U << MMC_CMD_ENABLE_BOOT_SHIFT) /* 0x01000000 */ +#define MMC_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +#define MMC_CMD_EXPECT_BOOT_ACK_MASK (0x1U << MMC_CMD_EXPECT_BOOT_ACK_SHIFT) /* 0x02000000 */ +#define MMC_CMD_DISABLE_BOOT_SHIFT (26U) +#define MMC_CMD_DISABLE_BOOT_MASK (0x1U << MMC_CMD_DISABLE_BOOT_SHIFT) /* 0x04000000 */ +#define MMC_CMD_BOOT_MODE_SHIFT (27U) +#define MMC_CMD_BOOT_MODE_MASK (0x1U << MMC_CMD_BOOT_MODE_SHIFT) /* 0x08000000 */ +#define MMC_CMD_VOLT_SWITCH_SHIFT (28U) +#define MMC_CMD_VOLT_SWITCH_MASK (0x1U << MMC_CMD_VOLT_SWITCH_SHIFT) /* 0x10000000 */ +#define MMC_CMD_USE_HOLD_REG_SHIFT (29U) +#define MMC_CMD_USE_HOLD_REG_MASK (0x1U << MMC_CMD_USE_HOLD_REG_SHIFT) /* 0x20000000 */ +#define MMC_CMD_START_CMD_SHIFT (31U) +#define MMC_CMD_START_CMD_MASK (0x1U << MMC_CMD_START_CMD_SHIFT) /* 0x80000000 */ +/* RESP0 */ +#define MMC_RESP0_OFFSET (0x30U) +#define MMC_RESP0 (0x0U) +#define MMC_RESP0_RESPONSE0_SHIFT (0U) +#define MMC_RESP0_RESPONSE0_MASK (0xFFFFFFFFU << MMC_RESP0_RESPONSE0_SHIFT) /* 0xFFFFFFFF */ +/* RESP1 */ +#define MMC_RESP1_OFFSET (0x34U) +#define MMC_RESP1 (0x0U) +#define MMC_RESP1_RESPONSE_SHIFT (0U) +#define MMC_RESP1_RESPONSE_MASK (0xFFFFFFFFU << MMC_RESP1_RESPONSE_SHIFT) /* 0xFFFFFFFF */ +/* RESP2 */ +#define MMC_RESP2_OFFSET (0x38U) +#define MMC_RESP2 (0x0U) +#define MMC_RESP2_RESPONSE2_SHIFT (0U) +#define MMC_RESP2_RESPONSE2_MASK (0xFFFFFFFFU << MMC_RESP2_RESPONSE2_SHIFT) /* 0xFFFFFFFF */ +/* RESP3 */ +#define MMC_RESP3_OFFSET (0x3CU) +#define MMC_RESP3 (0x0U) +#define MMC_RESP3_RESPONSE3_SHIFT (0U) +#define MMC_RESP3_RESPONSE3_MASK (0xFFFFFFFFU << MMC_RESP3_RESPONSE3_SHIFT) /* 0xFFFFFFFF */ +/* MINTSTS */ +#define MMC_MINTSTS_OFFSET (0x40U) +#define MMC_MINTSTS_INT_STATUS_SHIFT (0U) +#define MMC_MINTSTS_INT_STATUS_MASK (0xFFFFU << MMC_MINTSTS_INT_STATUS_SHIFT) /* 0x0000FFFF */ +#define MMC_MINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT (16U) +#define MMC_MINTSTS_DATA_NOBUSY_INT_STATUS_MASK (0x1U << MMC_MINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT) /* 0x00010000 */ +#define MMC_MINTSTS_SDIO_INTERRUPT_SHIFT (24U) +#define MMC_MINTSTS_SDIO_INTERRUPT_MASK (0x1U << MMC_MINTSTS_SDIO_INTERRUPT_SHIFT) /* 0x01000000 */ +/* RINTSTS */ +#define MMC_RINTSTS_OFFSET (0x44U) +#define MMC_RINTSTS_INT_STATUS_SHIFT (0U) +#define MMC_RINTSTS_INT_STATUS_MASK (0xFFFFU << MMC_RINTSTS_INT_STATUS_SHIFT) /* 0x0000FFFF */ +#define MMC_RINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT (16U) +#define MMC_RINTSTS_DATA_NOBUSY_INT_STATUS_MASK (0x1U << MMC_RINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT) /* 0x00010000 */ +#define MMC_RINTSTS_SDIO_INTERRUPT_SHIFT (24U) +#define MMC_RINTSTS_SDIO_INTERRUPT_MASK (0x1U << MMC_RINTSTS_SDIO_INTERRUPT_SHIFT) /* 0x01000000 */ +/* STATUS */ +#define MMC_STATUS_OFFSET (0x48U) +#define MMC_STATUS (0x506U) +#define MMC_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +#define MMC_STATUS_FIFO_RX_WATERMARK_MASK (0x1U << MMC_STATUS_FIFO_RX_WATERMARK_SHIFT) /* 0x00000001 */ +#define MMC_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +#define MMC_STATUS_FIFO_TX_WATERMARK_MASK (0x1U << MMC_STATUS_FIFO_TX_WATERMARK_SHIFT) /* 0x00000002 */ +#define MMC_STATUS_FIFO_EMPTY_SHIFT (2U) +#define MMC_STATUS_FIFO_EMPTY_MASK (0x1U << MMC_STATUS_FIFO_EMPTY_SHIFT) /* 0x00000004 */ +#define MMC_STATUS_FIFO_FULL_SHIFT (3U) +#define MMC_STATUS_FIFO_FULL_MASK (0x1U << MMC_STATUS_FIFO_FULL_SHIFT) /* 0x00000008 */ +#define MMC_STATUS_COMMAND_FSM_STATES_SHIFT (4U) +#define MMC_STATUS_COMMAND_FSM_STATES_MASK (0xFU << MMC_STATUS_COMMAND_FSM_STATES_SHIFT) /* 0x000000F0 */ +#define MMC_STATUS_DATA_3_STATUS_SHIFT (8U) +#define MMC_STATUS_DATA_3_STATUS_MASK (0x1U << MMC_STATUS_DATA_3_STATUS_SHIFT) /* 0x00000100 */ +#define MMC_STATUS_DATA_BUSY_SHIFT (9U) +#define MMC_STATUS_DATA_BUSY_MASK (0x1U << MMC_STATUS_DATA_BUSY_SHIFT) /* 0x00000200 */ +#define MMC_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +#define MMC_STATUS_DATA_STATE_MC_BUSY_MASK (0x1U << MMC_STATUS_DATA_STATE_MC_BUSY_SHIFT) /* 0x00000400 */ +#define MMC_STATUS_RESPONSE_INDEX_SHIFT (11U) +#define MMC_STATUS_RESPONSE_INDEX_MASK (0x3FU << MMC_STATUS_RESPONSE_INDEX_SHIFT) /* 0x0001F800 */ +#define MMC_STATUS_FIFO_COUNT_SHIFT (17U) +#define MMC_STATUS_FIFO_COUNT_MASK (0x1FFFU << MMC_STATUS_FIFO_COUNT_SHIFT) /* 0x3FFE0000 */ +#define MMC_STATUS_DMA_ACK_SHIFT (30U) +#define MMC_STATUS_DMA_ACK_MASK (0x1U << MMC_STATUS_DMA_ACK_SHIFT) /* 0x40000000 */ +#define MMC_STATUS_DMA_REQ_SHIFT (31U) +#define MMC_STATUS_DMA_REQ_MASK (0x1U << MMC_STATUS_DMA_REQ_SHIFT) /* 0x80000000 */ +/* FIFOTH */ +#define MMC_FIFOTH_OFFSET (0x4CU) +#define MMC_FIFOTH_TX_WMARK_SHIFT (0U) +#define MMC_FIFOTH_TX_WMARK_MASK (0xFFFU << MMC_FIFOTH_TX_WMARK_SHIFT) /* 0x00000FFF */ +#define MMC_FIFOTH_RX_WMARK_SHIFT (16U) +#define MMC_FIFOTH_RX_WMARK_MASK (0xFFFU << MMC_FIFOTH_RX_WMARK_SHIFT) /* 0x0FFF0000 */ +#define MMC_FIFOTH_DMA_MUTIPLE_TRANSACTION_SIZE_SHIFT (28U) +#define MMC_FIFOTH_DMA_MUTIPLE_TRANSACTION_SIZE_MASK (0x7U << MMC_FIFOTH_DMA_MUTIPLE_TRANSACTION_SIZE_SHIFT) /* 0x70000000 */ +/* CDETECT */ +#define MMC_CDETECT_OFFSET (0x50U) +#define MMC_CDETECT (0x0U) +#define MMC_CDETECT_CARD_DETECT_N_SHIFT (0U) +#define MMC_CDETECT_CARD_DETECT_N_MASK (0x1U << MMC_CDETECT_CARD_DETECT_N_SHIFT) /* 0x00000001 */ +/* WRTPRT */ +#define MMC_WRTPRT_OFFSET (0x54U) +#define MMC_WRTPRT_WRITE_PROTECT_SHIFT (0U) +#define MMC_WRTPRT_WRITE_PROTECT_MASK (0x1U << MMC_WRTPRT_WRITE_PROTECT_SHIFT) /* 0x00000001 */ +/* TCBCNT */ +#define MMC_TCBCNT_OFFSET (0x5CU) +#define MMC_TCBCNT (0x0U) +#define MMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +#define MMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU << MMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT) /* 0xFFFFFFFF */ +/* TBBCNT */ +#define MMC_TBBCNT_OFFSET (0x60U) +#define MMC_TBBCNT (0x0U) +#define MMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +#define MMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU << MMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT) /* 0xFFFFFFFF */ +/* DEBNCE */ +#define MMC_DEBNCE_OFFSET (0x64U) +#define MMC_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +#define MMC_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU << MMC_DEBNCE_DEBOUNCE_COUNT_SHIFT) /* 0x00FFFFFF */ +/* USRID */ +#define MMC_USRID_OFFSET (0x68U) +#define MMC_USRID_USRID_SHIFT (0U) +#define MMC_USRID_USRID_MASK (0xFFFFFFFFU << MMC_USRID_USRID_SHIFT) /* 0xFFFFFFFF */ +/* VERID */ +#define MMC_VERID_OFFSET (0x6CU) +#define MMC_VERID (0x5342270AU) +#define MMC_VERID_VERID_SHIFT (0U) +#define MMC_VERID_VERID_MASK (0xFFFFFFFFU << MMC_VERID_VERID_SHIFT) /* 0xFFFFFFFF */ +/* HCON */ +#define MMC_HCON_OFFSET (0x70U) +#define MMC_HCON (0x4C47CC1U) +#define MMC_HCON_CARD_TYPE_SHIFT (0U) +#define MMC_HCON_CARD_TYPE_MASK (0x1U << MMC_HCON_CARD_TYPE_SHIFT) /* 0x00000001 */ +#define MMC_HCON_CARD_NUM_SHIFT (1U) +#define MMC_HCON_CARD_NUM_MASK (0x1FU << MMC_HCON_CARD_NUM_SHIFT) /* 0x0000003E */ +#define MMC_HCON_H_BUS_TYPE_SHIFT (6U) +#define MMC_HCON_H_BUS_TYPE_MASK (0x1U << MMC_HCON_H_BUS_TYPE_SHIFT) /* 0x00000040 */ +#define MMC_HCON_H_DATA_WIDTH_SHIFT (7U) +#define MMC_HCON_H_DATA_WIDTH_MASK (0x7U << MMC_HCON_H_DATA_WIDTH_SHIFT) /* 0x00000380 */ +#define MMC_HCON_H_ADDR_WIDTH_SHIFT (10U) +#define MMC_HCON_H_ADDR_WIDTH_MASK (0x3FU << MMC_HCON_H_ADDR_WIDTH_SHIFT) /* 0x0000FC00 */ +#define MMC_HCON_DMA_INTERFACE_SHIFT (16U) +#define MMC_HCON_DMA_INTERFACE_MASK (0x3U << MMC_HCON_DMA_INTERFACE_SHIFT) /* 0x00030000 */ +#define MMC_HCON_GE_DMA_DATA_WIDTH_SHIFT (18U) +#define MMC_HCON_GE_DMA_DATA_WIDTH_MASK (0x7U << MMC_HCON_GE_DMA_DATA_WIDTH_SHIFT) /* 0x001C0000 */ +#define MMC_HCON_FIFO_RAM_INSIDE_SHIFT (21U) +#define MMC_HCON_FIFO_RAM_INSIDE_MASK (0x1U << MMC_HCON_FIFO_RAM_INSIDE_SHIFT) /* 0x00200000 */ +#define MMC_HCON_IMPL_HOLD_REG_SHIFT (22U) +#define MMC_HCON_IMPL_HOLD_REG_MASK (0x1U << MMC_HCON_IMPL_HOLD_REG_SHIFT) /* 0x00400000 */ +#define MMC_HCON_SET_CLK_FALSE_PATH_SHIFT (23U) +#define MMC_HCON_SET_CLK_FALSE_PATH_MASK (0x1U << MMC_HCON_SET_CLK_FALSE_PATH_SHIFT) /* 0x00800000 */ +#define MMC_HCON_NUM_CLK_DIV_SHIFT (24U) +#define MMC_HCON_NUM_CLK_DIV_MASK (0x3U << MMC_HCON_NUM_CLK_DIV_SHIFT) /* 0x03000000 */ +#define MMC_HCON_AREA_OPTIMIZED_SHIFT (26U) +#define MMC_HCON_AREA_OPTIMIZED_MASK (0x1U << MMC_HCON_AREA_OPTIMIZED_SHIFT) /* 0x04000000 */ +/* UHSREG */ +#define MMC_UHSREG_OFFSET (0x74U) +#define MMC_UHSREG_DDR_REG_SHIFT (16U) +#define MMC_UHSREG_DDR_REG_MASK (0x1U << MMC_UHSREG_DDR_REG_SHIFT) /* 0x00010000 */ +/* RSTN */ +#define MMC_RSTN_OFFSET (0x78U) +#define MMC_RSTN_CARD_RESET_SHIFT (0U) +#define MMC_RSTN_CARD_RESET_MASK (0x1U << MMC_RSTN_CARD_RESET_SHIFT) /* 0x00000001 */ +/* BMOD */ +#define MMC_BMOD_OFFSET (0x80U) +#define MMC_BMOD_SWR_SHIFT (0U) +#define MMC_BMOD_SWR_MASK (0x1U << MMC_BMOD_SWR_SHIFT) /* 0x00000001 */ +#define MMC_BMOD_FB_SHIFT (1U) +#define MMC_BMOD_FB_MASK (0x1U << MMC_BMOD_FB_SHIFT) /* 0x00000002 */ +#define MMC_BMOD_DSL_SHIFT (2U) +#define MMC_BMOD_DSL_MASK (0x1FU << MMC_BMOD_DSL_SHIFT) /* 0x0000007C */ +#define MMC_BMOD_DE_SHIFT (7U) +#define MMC_BMOD_DE_MASK (0x1U << MMC_BMOD_DE_SHIFT) /* 0x00000080 */ +#define MMC_BMOD_PBL_SHIFT (8U) +#define MMC_BMOD_PBL_MASK (0x7U << MMC_BMOD_PBL_SHIFT) /* 0x00000700 */ +/* PLDMND */ +#define MMC_PLDMND_OFFSET (0x84U) +#define MMC_PLDMND_PD_SHIFT (0U) +#define MMC_PLDMND_PD_MASK (0xFFFFFFFFU << MMC_PLDMND_PD_SHIFT) /* 0xFFFFFFFF */ +/* DBADDR */ +#define MMC_DBADDR_OFFSET (0x88U) +#define MMC_DBADDR_SBL_SHIFT (0U) +#define MMC_DBADDR_SBL_MASK (0xFFFFFFFFU << MMC_DBADDR_SBL_SHIFT) /* 0xFFFFFFFF */ +/* IDSTS */ +#define MMC_IDSTS_OFFSET (0x8CU) +#define MMC_IDSTS_TI_SHIFT (0U) +#define MMC_IDSTS_TI_MASK (0x1U << MMC_IDSTS_TI_SHIFT) /* 0x00000001 */ +#define MMC_IDSTS_RI_SHIFT (1U) +#define MMC_IDSTS_RI_MASK (0x1U << MMC_IDSTS_RI_SHIFT) /* 0x00000002 */ +#define MMC_IDSTS_FBE_SHIFT (2U) +#define MMC_IDSTS_FBE_MASK (0x1U << MMC_IDSTS_FBE_SHIFT) /* 0x00000004 */ +#define MMC_IDSTS_DUI_SHIFT (4U) +#define MMC_IDSTS_DUI_MASK (0x1U << MMC_IDSTS_DUI_SHIFT) /* 0x00000010 */ +#define MMC_IDSTS_CES_SHIFT (5U) +#define MMC_IDSTS_CES_MASK (0x1U << MMC_IDSTS_CES_SHIFT) /* 0x00000020 */ +#define MMC_IDSTS_NIS_SHIFT (8U) +#define MMC_IDSTS_NIS_MASK (0x1U << MMC_IDSTS_NIS_SHIFT) /* 0x00000100 */ +#define MMC_IDSTS_AIS_SHIFT (9U) +#define MMC_IDSTS_AIS_MASK (0x1U << MMC_IDSTS_AIS_SHIFT) /* 0x00000200 */ +#define MMC_IDSTS_EB_SHIFT (10U) +#define MMC_IDSTS_EB_MASK (0x7U << MMC_IDSTS_EB_SHIFT) /* 0x00001C00 */ +#define MMC_IDSTS_FSM_SHIFT (13U) +#define MMC_IDSTS_FSM_MASK (0xFU << MMC_IDSTS_FSM_SHIFT) /* 0x0001E000 */ +/* IDINTEN */ +#define MMC_IDINTEN_OFFSET (0x90U) +#define MMC_IDINTEN_TI_SHIFT (0U) +#define MMC_IDINTEN_TI_MASK (0x1U << MMC_IDINTEN_TI_SHIFT) /* 0x00000001 */ +#define MMC_IDINTEN_RI_SHIFT (1U) +#define MMC_IDINTEN_RI_MASK (0x1U << MMC_IDINTEN_RI_SHIFT) /* 0x00000002 */ +#define MMC_IDINTEN_FBE_SHIFT (2U) +#define MMC_IDINTEN_FBE_MASK (0x1U << MMC_IDINTEN_FBE_SHIFT) /* 0x00000004 */ +#define MMC_IDINTEN_DU_SHIFT (4U) +#define MMC_IDINTEN_DU_MASK (0x1U << MMC_IDINTEN_DU_SHIFT) /* 0x00000010 */ +#define MMC_IDINTEN_CES_SHIFT (5U) +#define MMC_IDINTEN_CES_MASK (0x1U << MMC_IDINTEN_CES_SHIFT) /* 0x00000020 */ +#define MMC_IDINTEN_NI_SHIFT (8U) +#define MMC_IDINTEN_NI_MASK (0x1U << MMC_IDINTEN_NI_SHIFT) /* 0x00000100 */ +#define MMC_IDINTEN_AI_SHIFT (9U) +#define MMC_IDINTEN_AI_MASK (0x1U << MMC_IDINTEN_AI_SHIFT) /* 0x00000200 */ +/* DSCADDR */ +#define MMC_DSCADDR_OFFSET (0x94U) +#define MMC_DSCADDR_HDA_SHIFT (0U) +#define MMC_DSCADDR_HDA_MASK (0xFFFFFFFFU << MMC_DSCADDR_HDA_SHIFT) /* 0xFFFFFFFF */ +/* BUFADDR */ +#define MMC_BUFADDR_OFFSET (0x98U) +#define MMC_BUFADDR_HBA_SHIFT (0U) +#define MMC_BUFADDR_HBA_MASK (0xFFFFFFFFU << MMC_BUFADDR_HBA_SHIFT) /* 0xFFFFFFFF */ +/* CARDTHRCTL */ +#define MMC_CARDTHRCTL_OFFSET (0x100U) +#define MMC_CARDTHRCTL_CARD_RD_THRES_EN_SHIFT (0U) +#define MMC_CARDTHRCTL_CARD_RD_THRES_EN_MASK (0x1U << MMC_CARDTHRCTL_CARD_RD_THRES_EN_SHIFT) /* 0x00000001 */ +#define MMC_CARDTHRCTL_BUSY_CLR_INT_EN_SHIFT (1U) +#define MMC_CARDTHRCTL_BUSY_CLR_INT_EN_MASK (0x1U << MMC_CARDTHRCTL_BUSY_CLR_INT_EN_SHIFT) /* 0x00000002 */ +#define MMC_CARDTHRCTL_CARD_RD_THRES_SHIFT (16U) +#define MMC_CARDTHRCTL_CARD_RD_THRES_MASK (0xFFFU << MMC_CARDTHRCTL_CARD_RD_THRES_SHIFT) /* 0x0FFF0000 */ +/* BACKEND_POWER */ +#define MMC_BACKEND_POWER_OFFSET (0x104U) +#define MMC_BACKEND_POWER_BACK_END_POWER_SHIFT (0U) +#define MMC_BACKEND_POWER_BACK_END_POWER_MASK (0x1U << MMC_BACKEND_POWER_BACK_END_POWER_SHIFT) /* 0x00000001 */ +/* EMMCDDR_REG */ +#define MMC_EMMCDDR_REG_OFFSET (0x10CU) +#define MMC_EMMCDDR_REG_HALF_START_BIT_SHIFT (0U) +#define MMC_EMMCDDR_REG_HALF_START_BIT_MASK (0x1U << MMC_EMMCDDR_REG_HALF_START_BIT_SHIFT) /* 0x00000001 */ +/* RDYINT_GEN */ +#define MMC_RDYINT_GEN_OFFSET (0x120U) +#define MMC_RDYINT_GEN_RDYINT_GEN_MAXVAL_SHIFT (0U) +#define MMC_RDYINT_GEN_RDYINT_GEN_MAXVAL_MASK (0xFFU << MMC_RDYINT_GEN_RDYINT_GEN_MAXVAL_SHIFT) /* 0x000000FF */ +#define MMC_RDYINT_GEN_RDYINT_GEN_WORKING_SHIFT (8U) +#define MMC_RDYINT_GEN_RDYINT_GEN_WORKING_MASK (0x1U << MMC_RDYINT_GEN_RDYINT_GEN_WORKING_SHIFT) /* 0x00000100 */ +#define MMC_RDYINT_GEN_RDYINT_CNT_STATUS_SHIFT (16U) +#define MMC_RDYINT_GEN_RDYINT_CNT_STATUS_MASK (0xFFU << MMC_RDYINT_GEN_RDYINT_CNT_STATUS_SHIFT) /* 0x00FF0000 */ +#define MMC_RDYINT_GEN_RDYINT_CNT_FINISH_SHIFT (24U) +#define MMC_RDYINT_GEN_RDYINT_CNT_FINISH_MASK (0x1U << MMC_RDYINT_GEN_RDYINT_CNT_FINISH_SHIFT) /* 0x01000000 */ +/* FIFO_BASE */ +#define MMC_FIFO_BASE_OFFSET (0x200U) +#define MMC_FIFO_BASE_FIFO_BASE_ADDR_SHIFT (0U) +#define MMC_FIFO_BASE_FIFO_BASE_ADDR_MASK (0xFFFFFFFFU << MMC_FIFO_BASE_FIFO_BASE_ADDR_SHIFT) /* 0xFFFFFFFF */ +/******************************************GPIO******************************************/ +/* SWPORT_DR_L */ +#define GPIO_SWPORT_DR_L_OFFSET (0x0U) +#define GPIO_SWPORT_DR_L_GPIO_SWPORT_DR_LOW_SHIFT (0U) +#define GPIO_SWPORT_DR_L_GPIO_SWPORT_DR_LOW_MASK (0xFFFFU << GPIO_SWPORT_DR_L_GPIO_SWPORT_DR_LOW_SHIFT) /* 0x0000FFFF */ +/* SWPORT_DR_H */ +#define GPIO_SWPORT_DR_H_OFFSET (0x4U) +#define GPIO_SWPORT_DR_H_GPIO_SWPORT_DR_HIGH_SHIFT (0U) +#define GPIO_SWPORT_DR_H_GPIO_SWPORT_DR_HIGH_MASK (0xFFFFU << GPIO_SWPORT_DR_H_GPIO_SWPORT_DR_HIGH_SHIFT) /* 0x0000FFFF */ +/* SWPORT_DDR_L */ +#define GPIO_SWPORT_DDR_L_OFFSET (0x8U) +#define GPIO_SWPORT_DDR_L_GPIO_SWPORT_DDR_LOW_SHIFT (0U) +#define GPIO_SWPORT_DDR_L_GPIO_SWPORT_DDR_LOW_MASK (0xFFFFU << GPIO_SWPORT_DDR_L_GPIO_SWPORT_DDR_LOW_SHIFT) /* 0x0000FFFF */ +/* SWPORT_DDR_H */ +#define GPIO_SWPORT_DDR_H_OFFSET (0xCU) +#define GPIO_SWPORT_DDR_H_GPIO_SWPORT_DDR_HIGH_SHIFT (0U) +#define GPIO_SWPORT_DDR_H_GPIO_SWPORT_DDR_HIGH_MASK (0xFFFFU << GPIO_SWPORT_DDR_H_GPIO_SWPORT_DDR_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_EN_L */ +#define GPIO_INT_EN_L_OFFSET (0x10U) +#define GPIO_INT_EN_L_GPIO_INT_EN_LOW_SHIFT (0U) +#define GPIO_INT_EN_L_GPIO_INT_EN_LOW_MASK (0xFFFFU << GPIO_INT_EN_L_GPIO_INT_EN_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_EN_H */ +#define GPIO_INT_EN_H_OFFSET (0x14U) +#define GPIO_INT_EN_H_GPIO_INT_EN_HIGH_SHIFT (0U) +#define GPIO_INT_EN_H_GPIO_INT_EN_HIGH_MASK (0xFFFFU << GPIO_INT_EN_H_GPIO_INT_EN_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_MASK_L */ +#define GPIO_INT_MASK_L_OFFSET (0x18U) +#define GPIO_INT_MASK_L_GPIO_INT_MASK_LOW_SHIFT (0U) +#define GPIO_INT_MASK_L_GPIO_INT_MASK_LOW_MASK (0xFFFFU << GPIO_INT_MASK_L_GPIO_INT_MASK_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_MASK_H */ +#define GPIO_INT_MASK_H_OFFSET (0x1CU) +#define GPIO_INT_MASK_H_GPIO_INT_MASK_HIGH_SHIFT (0U) +#define GPIO_INT_MASK_H_GPIO_INT_MASK_HIGH_MASK (0xFFFFU << GPIO_INT_MASK_H_GPIO_INT_MASK_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_TYPE_L */ +#define GPIO_INT_TYPE_L_OFFSET (0x20U) +#define GPIO_INT_TYPE_L_GPIO_INT_TYPE_LOW_SHIFT (0U) +#define GPIO_INT_TYPE_L_GPIO_INT_TYPE_LOW_MASK (0xFFFFU << GPIO_INT_TYPE_L_GPIO_INT_TYPE_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_TYPE_H */ +#define GPIO_INT_TYPE_H_OFFSET (0x24U) +#define GPIO_INT_TYPE_H_GPIO_INT_TYPE_HIGH_SHIFT (0U) +#define GPIO_INT_TYPE_H_GPIO_INT_TYPE_HIGH_MASK (0xFFFFU << GPIO_INT_TYPE_H_GPIO_INT_TYPE_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_POLARITY_L */ +#define GPIO_INT_POLARITY_L_OFFSET (0x28U) +#define GPIO_INT_POLARITY_L_GPIO_INT_POLARITY_LOW_SHIFT (0U) +#define GPIO_INT_POLARITY_L_GPIO_INT_POLARITY_LOW_MASK (0xFFFFU << GPIO_INT_POLARITY_L_GPIO_INT_POLARITY_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_POLARITY_H */ +#define GPIO_INT_POLARITY_H_OFFSET (0x2CU) +#define GPIO_INT_POLARITY_H_GPIO_INT_POLARITY_HIGH_SHIFT (0U) +#define GPIO_INT_POLARITY_H_GPIO_INT_POLARITY_HIGH_MASK (0xFFFFU << GPIO_INT_POLARITY_H_GPIO_INT_POLARITY_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_BOTHEDGE_L */ +#define GPIO_INT_BOTHEDGE_L_OFFSET (0x30U) +#define GPIO_INT_BOTHEDGE_L_GPIO_INT_BOTHEDGE_LOW_SHIFT (0U) +#define GPIO_INT_BOTHEDGE_L_GPIO_INT_BOTHEDGE_LOW_MASK (0xFFFFU << GPIO_INT_BOTHEDGE_L_GPIO_INT_BOTHEDGE_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_BOTHEDGE_H */ +#define GPIO_INT_BOTHEDGE_H_OFFSET (0x34U) +#define GPIO_INT_BOTHEDGE_H_GPIO_INT_BOTHEDGE_HIGH_SHIFT (0U) +#define GPIO_INT_BOTHEDGE_H_GPIO_INT_BOTHEDGE_HIGH_MASK (0xFFFFU << GPIO_INT_BOTHEDGE_H_GPIO_INT_BOTHEDGE_HIGH_SHIFT) /* 0x0000FFFF */ +/* DEBOUNCE_L */ +#define GPIO_DEBOUNCE_L_OFFSET (0x38U) +#define GPIO_DEBOUNCE_L_GPIO_DEBOUNCE_LOW_SHIFT (0U) +#define GPIO_DEBOUNCE_L_GPIO_DEBOUNCE_LOW_MASK (0xFFFFU << GPIO_DEBOUNCE_L_GPIO_DEBOUNCE_LOW_SHIFT) /* 0x0000FFFF */ +/* DEBOUNCE_H */ +#define GPIO_DEBOUNCE_H_OFFSET (0x3CU) +#define GPIO_DEBOUNCE_H_GPIO_DEBOUNCE_HIGH_SHIFT (0U) +#define GPIO_DEBOUNCE_H_GPIO_DEBOUNCE_HIGH_MASK (0xFFFFU << GPIO_DEBOUNCE_H_GPIO_DEBOUNCE_HIGH_SHIFT) /* 0x0000FFFF */ +/* DBCLK_DIV_EN_L */ +#define GPIO_DBCLK_DIV_EN_L_OFFSET (0x40U) +#define GPIO_DBCLK_DIV_EN_L_GPIO_DBCLK_DIV_EN_LOW_SHIFT (0U) +#define GPIO_DBCLK_DIV_EN_L_GPIO_DBCLK_DIV_EN_LOW_MASK (0xFFFFU << GPIO_DBCLK_DIV_EN_L_GPIO_DBCLK_DIV_EN_LOW_SHIFT) /* 0x0000FFFF */ +/* DBCLK_DIV_EN_H */ +#define GPIO_DBCLK_DIV_EN_H_OFFSET (0x44U) +#define GPIO_DBCLK_DIV_EN_H_GPIO_DBCLK_DIV_EN_HIGH_SHIFT (0U) +#define GPIO_DBCLK_DIV_EN_H_GPIO_DBCLK_DIV_EN_HIGH_MASK (0xFFFFU << GPIO_DBCLK_DIV_EN_H_GPIO_DBCLK_DIV_EN_HIGH_SHIFT) /* 0x0000FFFF */ +/* DBCLK_DIV_CON */ +#define GPIO_DBCLK_DIV_CON_OFFSET (0x48U) +#define GPIO_DBCLK_DIV_CON_GPIO_DBCLK_DIV_CON_SHIFT (0U) +#define GPIO_DBCLK_DIV_CON_GPIO_DBCLK_DIV_CON_MASK (0xFFFFFFU << GPIO_DBCLK_DIV_CON_GPIO_DBCLK_DIV_CON_SHIFT) /* 0x00FFFFFF */ +/* INT_STATUS */ +#define GPIO_INT_STATUS_OFFSET (0x50U) +#define GPIO_INT_STATUS (0x0U) +#define GPIO_INT_STATUS_GPIO_INT_STATUS_SHIFT (0U) +#define GPIO_INT_STATUS_GPIO_INT_STATUS_MASK (0xFFFFFFFFU << GPIO_INT_STATUS_GPIO_INT_STATUS_SHIFT) /* 0xFFFFFFFF */ +/* INT_RAWSTATUS */ +#define GPIO_INT_RAWSTATUS_OFFSET (0x58U) +#define GPIO_INT_RAWSTATUS (0x0U) +#define GPIO_INT_RAWSTATUS_GPIO_INT_RAWSTATUS_SHIFT (0U) +#define GPIO_INT_RAWSTATUS_GPIO_INT_RAWSTATUS_MASK (0xFFFFFFFFU << GPIO_INT_RAWSTATUS_GPIO_INT_RAWSTATUS_SHIFT) /* 0xFFFFFFFF */ +/* PORT_EOI_L */ +#define GPIO_PORT_EOI_L_OFFSET (0x60U) +#define GPIO_PORT_EOI_L_GPIO_PORT_EOI_LOW_SHIFT (0U) +#define GPIO_PORT_EOI_L_GPIO_PORT_EOI_LOW_MASK (0xFFFFU << GPIO_PORT_EOI_L_GPIO_PORT_EOI_LOW_SHIFT) /* 0x0000FFFF */ +/* PORT_EOI_H */ +#define GPIO_PORT_EOI_H_OFFSET (0x64U) +#define GPIO_PORT_EOI_H_GPIO_PORT_EOI_HIGH_SHIFT (0U) +#define GPIO_PORT_EOI_H_GPIO_PORT_EOI_HIGH_MASK (0xFFFFU << GPIO_PORT_EOI_H_GPIO_PORT_EOI_HIGH_SHIFT) /* 0x0000FFFF */ +/* EXT_PORT */ +#define GPIO_EXT_PORT_OFFSET (0x70U) +#define GPIO_EXT_PORT (0x0U) +#define GPIO_EXT_PORT_GPIO_EXT_PORT_SHIFT (0U) +#define GPIO_EXT_PORT_GPIO_EXT_PORT_MASK (0xFFFFFFFFU << GPIO_EXT_PORT_GPIO_EXT_PORT_SHIFT) /* 0xFFFFFFFF */ +/* VER_ID */ +#define GPIO_VER_ID_OFFSET (0x78U) +#define GPIO_VER_ID (0x1000C2BU) +#define GPIO_VER_ID_GPIO_VER_ID_SHIFT (0U) +#define GPIO_VER_ID_GPIO_VER_ID_MASK (0xFFFFFFFFU << GPIO_VER_ID_GPIO_VER_ID_SHIFT) /* 0xFFFFFFFF */ +/****************************************KEY_CTRL****************************************/ +/* CON */ +#define KEY_CTRL_CON_OFFSET (0x0U) +#define KEY_CTRL_CON_ENABLE_SHIFT (0U) +#define KEY_CTRL_CON_ENABLE_MASK (0x1U << KEY_CTRL_CON_ENABLE_SHIFT) /* 0x00000001 */ +#define KEY_CTRL_CON_KEY_DET_TH_SHIFT (4U) +#define KEY_CTRL_CON_KEY_DET_TH_MASK (0xFFFFFFFU << KEY_CTRL_CON_KEY_DET_TH_SHIFT) /* 0xFFFFFFF0 */ +/* CAL_TH */ +#define KEY_CTRL_CAL_TH_OFFSET (0x4U) +#define KEY_CTRL_CAL_TH_KEY_CAL_TH_SHIFT (0U) +#define KEY_CTRL_CAL_TH_KEY_CAL_TH_MASK (0xFFFFFFFFU << KEY_CTRL_CAL_TH_KEY_CAL_TH_SHIFT) /* 0xFFFFFFFF */ +/* DET_REC */ +#define KEY_CTRL_DET_REC_OFFSET (0x8U) +#define KEY_CTRL_DET_REC (0x0U) +#define KEY_CTRL_DET_REC_KEY_DET_REC_SHIFT (0U) +#define KEY_CTRL_DET_REC_KEY_DET_REC_MASK (0xFFFFFFFFU << KEY_CTRL_DET_REC_KEY_DET_REC_SHIFT) /* 0xFFFFFFFF */ +/* INT_CON */ +#define KEY_CTRL_INT_CON_OFFSET (0xCU) +#define KEY_CTRL_INT_CON_KEY_INT_EN_SHIFT (0U) +#define KEY_CTRL_INT_CON_KEY_INT_EN_MASK (0x1U << KEY_CTRL_INT_CON_KEY_INT_EN_SHIFT) /* 0x00000001 */ +#define KEY_CTRL_INT_CON_KEY_INT_MASK_DIS_SHIFT (1U) +#define KEY_CTRL_INT_CON_KEY_INT_MASK_DIS_MASK (0x1U << KEY_CTRL_INT_CON_KEY_INT_MASK_DIS_SHIFT) /* 0x00000002 */ +#define KEY_CTRL_INT_CON_KEY_INT_MASK_TH_SHIFT (16U) +#define KEY_CTRL_INT_CON_KEY_INT_MASK_TH_MASK (0xFFFFU << KEY_CTRL_INT_CON_KEY_INT_MASK_TH_SHIFT) /* 0xFFFF0000 */ +/* INT_ST */ +#define KEY_CTRL_INT_ST_OFFSET (0x10U) +#define KEY_CTRL_INT_ST_KEY_INT_ST_SHIFT (0U) +#define KEY_CTRL_INT_ST_KEY_INT_ST_MASK (0x1U << KEY_CTRL_INT_ST_KEY_INT_ST_SHIFT) /* 0x00000001 */ +/******************************************PDM*******************************************/ +/* SYSCONFIG */ +#define PDM_SYSCONFIG_OFFSET (0x0U) +#define PDM_SYSCONFIG_RX_CLR_SHIFT (0U) +#define PDM_SYSCONFIG_RX_CLR_MASK (0x1U << PDM_SYSCONFIG_RX_CLR_SHIFT) /* 0x00000001 */ +#define PDM_SYSCONFIG_RX_START_SHIFT (2U) +#define PDM_SYSCONFIG_RX_START_MASK (0x1U << PDM_SYSCONFIG_RX_START_SHIFT) /* 0x00000004 */ +/* CTRL0 */ +#define PDM_CTRL0_OFFSET (0x4U) +#define PDM_CTRL0_DATA_VLD_WIDTH_SHIFT (0U) +#define PDM_CTRL0_DATA_VLD_WIDTH_MASK (0x1FU << PDM_CTRL0_DATA_VLD_WIDTH_SHIFT) /* 0x0000001F */ +#define PDM_CTRL0_SAMPLE_RATE_SEL_SHIFT (5U) +#define PDM_CTRL0_SAMPLE_RATE_SEL_MASK (0x7U << PDM_CTRL0_SAMPLE_RATE_SEL_SHIFT) /* 0x000000E0 */ +#define PDM_CTRL0_INT_DIV_CON_SHIFT (8U) +#define PDM_CTRL0_INT_DIV_CON_MASK (0xFFU << PDM_CTRL0_INT_DIV_CON_SHIFT) /* 0x0000FF00 */ +#define PDM_CTRL0_SIG_SCALE_MODE_SHIFT (24U) +#define PDM_CTRL0_SIG_SCALE_MODE_MASK (0x1U << PDM_CTRL0_SIG_SCALE_MODE_SHIFT) /* 0x01000000 */ +#define PDM_CTRL0_FILTER_GATE_EN_SHIFT (25U) +#define PDM_CTRL0_FILTER_GATE_EN_MASK (0x1U << PDM_CTRL0_FILTER_GATE_EN_SHIFT) /* 0x02000000 */ +#define PDM_CTRL0_HWT_EN_SHIFT (26U) +#define PDM_CTRL0_HWT_EN_MASK (0x1U << PDM_CTRL0_HWT_EN_SHIFT) /* 0x04000000 */ +#define PDM_CTRL0_PATH0_EN_SHIFT (27U) +#define PDM_CTRL0_PATH0_EN_MASK (0x1U << PDM_CTRL0_PATH0_EN_SHIFT) /* 0x08000000 */ +#define PDM_CTRL0_PATH1_EN_SHIFT (28U) +#define PDM_CTRL0_PATH1_EN_MASK (0x1U << PDM_CTRL0_PATH1_EN_SHIFT) /* 0x10000000 */ +#define PDM_CTRL0_PATH2_EN_SHIFT (29U) +#define PDM_CTRL0_PATH2_EN_MASK (0x1U << PDM_CTRL0_PATH2_EN_SHIFT) /* 0x20000000 */ +#define PDM_CTRL0_PATH3_EN_SHIFT (30U) +#define PDM_CTRL0_PATH3_EN_MASK (0x1U << PDM_CTRL0_PATH3_EN_SHIFT) /* 0x40000000 */ +#define PDM_CTRL0_SJM_SEL_SHIFT (31U) +#define PDM_CTRL0_SJM_SEL_MASK (0x1U << PDM_CTRL0_SJM_SEL_SHIFT) /* 0x80000000 */ +/* CTRL1 */ +#define PDM_CTRL1_OFFSET (0x8U) +#define PDM_CTRL1_FRAC_DIV_DENOMONATOR_SHIFT (0U) +#define PDM_CTRL1_FRAC_DIV_DENOMONATOR_MASK (0xFFFFU << PDM_CTRL1_FRAC_DIV_DENOMONATOR_SHIFT) /* 0x0000FFFF */ +#define PDM_CTRL1_FRAC_DIV_NUMERATOR_SHIFT (16U) +#define PDM_CTRL1_FRAC_DIV_NUMERATOR_MASK (0xFFFFU << PDM_CTRL1_FRAC_DIV_NUMERATOR_SHIFT) /* 0xFFFF0000 */ +/* CLK_CTRL */ +#define PDM_CLK_CTRL_OFFSET (0xCU) +#define PDM_CLK_CTRL_CIC_DS_RATIO_SHIFT (0U) +#define PDM_CLK_CTRL_CIC_DS_RATIO_MASK (0x3U << PDM_CLK_CTRL_CIC_DS_RATIO_SHIFT) /* 0x00000003 */ +#define PDM_CLK_CTRL_FIR_COM_BPS_SHIFT (2U) +#define PDM_CLK_CTRL_FIR_COM_BPS_MASK (0x1U << PDM_CLK_CTRL_FIR_COM_BPS_SHIFT) /* 0x00000004 */ +#define PDM_CLK_CTRL_LR_CH_EX_SHIFT (3U) +#define PDM_CLK_CTRL_LR_CH_EX_MASK (0x1U << PDM_CLK_CTRL_LR_CH_EX_SHIFT) /* 0x00000008 */ +#define PDM_CLK_CTRL_DIV_TYPE_SEL_SHIFT (4U) +#define PDM_CLK_CTRL_DIV_TYPE_SEL_MASK (0x1U << PDM_CLK_CTRL_DIV_TYPE_SEL_SHIFT) /* 0x00000010 */ +#define PDM_CLK_CTRL_PDM_CLK_EN_SHIFT (5U) +#define PDM_CLK_CTRL_PDM_CLK_EN_MASK (0x1U << PDM_CLK_CTRL_PDM_CLK_EN_SHIFT) /* 0x00000020 */ +/* HPF_CTRL */ +#define PDM_HPF_CTRL_OFFSET (0x10U) +#define PDM_HPF_CTRL_HPF_CF_SHIFT (0U) +#define PDM_HPF_CTRL_HPF_CF_MASK (0x3U << PDM_HPF_CTRL_HPF_CF_SHIFT) /* 0x00000003 */ +#define PDM_HPF_CTRL_HPFRE_SHIFT (2U) +#define PDM_HPF_CTRL_HPFRE_MASK (0x1U << PDM_HPF_CTRL_HPFRE_SHIFT) /* 0x00000004 */ +#define PDM_HPF_CTRL_HPFLE_SHIFT (3U) +#define PDM_HPF_CTRL_HPFLE_MASK (0x1U << PDM_HPF_CTRL_HPFLE_SHIFT) /* 0x00000008 */ +/* FIFO_CTRL */ +#define PDM_FIFO_CTRL_OFFSET (0x14U) +#define PDM_FIFO_CTRL_RFL_SHIFT (0U) +#define PDM_FIFO_CTRL_RFL_MASK (0xFFU << PDM_FIFO_CTRL_RFL_SHIFT) /* 0x000000FF */ +#define PDM_FIFO_CTRL_RFT_SHIFT (8U) +#define PDM_FIFO_CTRL_RFT_MASK (0x7FU << PDM_FIFO_CTRL_RFT_SHIFT) /* 0x00007F00 */ +/* DMA_CTRL */ +#define PDM_DMA_CTRL_OFFSET (0x18U) +#define PDM_DMA_CTRL_RDL_SHIFT (0U) +#define PDM_DMA_CTRL_RDL_MASK (0x7FU << PDM_DMA_CTRL_RDL_SHIFT) /* 0x0000007F */ +#define PDM_DMA_CTRL_RDE_SHIFT (8U) +#define PDM_DMA_CTRL_RDE_MASK (0x1U << PDM_DMA_CTRL_RDE_SHIFT) /* 0x00000100 */ +/* INT_EN */ +#define PDM_INT_EN_OFFSET (0x1CU) +#define PDM_INT_EN_RXTIE_SHIFT (0U) +#define PDM_INT_EN_RXTIE_MASK (0x1U << PDM_INT_EN_RXTIE_SHIFT) /* 0x00000001 */ +#define PDM_INT_EN_RXOIE_SHIFT (1U) +#define PDM_INT_EN_RXOIE_MASK (0x1U << PDM_INT_EN_RXOIE_SHIFT) /* 0x00000002 */ +/* INT_CLR */ +#define PDM_INT_CLR_OFFSET (0x20U) +#define PDM_INT_CLR_RXOIC_SHIFT (1U) +#define PDM_INT_CLR_RXOIC_MASK (0x1U << PDM_INT_CLR_RXOIC_SHIFT) /* 0x00000002 */ +/* INT_ST */ +#define PDM_INT_ST_OFFSET (0x24U) +#define PDM_INT_ST (0x0U) +#define PDM_INT_ST_RXFI_SHIFT (0U) +#define PDM_INT_ST_RXFI_MASK (0x1U << PDM_INT_ST_RXFI_SHIFT) /* 0x00000001 */ +#define PDM_INT_ST_RXOI_SHIFT (1U) +#define PDM_INT_ST_RXOI_MASK (0x1U << PDM_INT_ST_RXOI_SHIFT) /* 0x00000002 */ +/* RXFIFO_DATA_REG */ +#define PDM_RXFIFO_DATA_REG_OFFSET (0x30U) +#define PDM_RXFIFO_DATA_REG (0x0U) +#define PDM_RXFIFO_DATA_REG_RXDR_SHIFT (0U) +#define PDM_RXFIFO_DATA_REG_RXDR_MASK (0xFFFFFFFFU << PDM_RXFIFO_DATA_REG_RXDR_SHIFT) /* 0xFFFFFFFF */ +/* DATA0R_REG */ +#define PDM_DATA0R_REG_OFFSET (0x34U) +#define PDM_DATA0R_REG (0x0U) +#define PDM_DATA0R_REG_DATA0R_SHIFT (0U) +#define PDM_DATA0R_REG_DATA0R_MASK (0xFFFFFFFFU << PDM_DATA0R_REG_DATA0R_SHIFT) /* 0xFFFFFFFF */ +/* DATA0L_REG */ +#define PDM_DATA0L_REG_OFFSET (0x38U) +#define PDM_DATA0L_REG (0x0U) +#define PDM_DATA0L_REG_DATA0L_SHIFT (0U) +#define PDM_DATA0L_REG_DATA0L_MASK (0xFFFFFFFFU << PDM_DATA0L_REG_DATA0L_SHIFT) /* 0xFFFFFFFF */ +/* DATA1R_REG */ +#define PDM_DATA1R_REG_OFFSET (0x3CU) +#define PDM_DATA1R_REG (0x0U) +#define PDM_DATA1R_REG_DATA1R_SHIFT (0U) +#define PDM_DATA1R_REG_DATA1R_MASK (0x1U << PDM_DATA1R_REG_DATA1R_SHIFT) /* 0x00000001 */ +/* DATA1L_REG */ +#define PDM_DATA1L_REG_OFFSET (0x40U) +#define PDM_DATA1L_REG (0x0U) +#define PDM_DATA1L_REG_DATA1L_SHIFT (0U) +#define PDM_DATA1L_REG_DATA1L_MASK (0xFFFFFFFFU << PDM_DATA1L_REG_DATA1L_SHIFT) /* 0xFFFFFFFF */ +/* DATA2R_REG */ +#define PDM_DATA2R_REG_OFFSET (0x44U) +#define PDM_DATA2R_REG (0x0U) +#define PDM_DATA2R_REG_DATA2R_SHIFT (0U) +#define PDM_DATA2R_REG_DATA2R_MASK (0xFFFFFFFFU << PDM_DATA2R_REG_DATA2R_SHIFT) /* 0xFFFFFFFF */ +/* DATA2L_REG */ +#define PDM_DATA2L_REG_OFFSET (0x48U) +#define PDM_DATA2L_REG (0x0U) +#define PDM_DATA2L_REG_DATA2L_SHIFT (0U) +#define PDM_DATA2L_REG_DATA2L_MASK (0xFFFFFFFFU << PDM_DATA2L_REG_DATA2L_SHIFT) /* 0xFFFFFFFF */ +/* DATA3R_REG */ +#define PDM_DATA3R_REG_OFFSET (0x4CU) +#define PDM_DATA3R_REG (0x0U) +#define PDM_DATA3R_REG_DATA3R_SHIFT (0U) +#define PDM_DATA3R_REG_DATA3R_MASK (0xFFFFFFFFU << PDM_DATA3R_REG_DATA3R_SHIFT) /* 0xFFFFFFFF */ +/* DATA3L_REG */ +#define PDM_DATA3L_REG_OFFSET (0x50U) +#define PDM_DATA3L_REG (0x0U) +#define PDM_DATA3L_REG_DATA3L_SHIFT (0U) +#define PDM_DATA3L_REG_DATA3L_MASK (0xFFFFFFFFU << PDM_DATA3L_REG_DATA3L_SHIFT) /* 0xFFFFFFFF */ +/* DATA_VALID */ +#define PDM_DATA_VALID_OFFSET (0x54U) +#define PDM_DATA_VALID (0x0U) +#define PDM_DATA_VALID_PATH3_VLD_SHIFT (0U) +#define PDM_DATA_VALID_PATH3_VLD_MASK (0x1U << PDM_DATA_VALID_PATH3_VLD_SHIFT) /* 0x00000001 */ +#define PDM_DATA_VALID_PATH2_VLD_SHIFT (1U) +#define PDM_DATA_VALID_PATH2_VLD_MASK (0x1U << PDM_DATA_VALID_PATH2_VLD_SHIFT) /* 0x00000002 */ +#define PDM_DATA_VALID_PATH1_VLD_SHIFT (2U) +#define PDM_DATA_VALID_PATH1_VLD_MASK (0x1U << PDM_DATA_VALID_PATH1_VLD_SHIFT) /* 0x00000004 */ +#define PDM_DATA_VALID_PATH0_VLD_SHIFT (3U) +#define PDM_DATA_VALID_PATH0_VLD_MASK (0x1U << PDM_DATA_VALID_PATH0_VLD_SHIFT) /* 0x00000008 */ +/* VERSION */ +#define PDM_VERSION_OFFSET (0x58U) +#define PDM_VERSION (0x59313030U) +#define PDM_VERSION_VERSION_SHIFT (0U) +#define PDM_VERSION_VERSION_MASK (0xFFFFFFFFU << PDM_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */ +/* INCR_RXDR */ +#define PDM_INCR_RXDR_OFFSET (0x400U) +#define PDM_INCR_RXDR (0x0U) +#define PDM_INCR_RXDR_RECEIVE_FIFO_DATA_SHIFT (0U) +#define PDM_INCR_RXDR_RECEIVE_FIFO_DATA_MASK (0xFFFFFFFFU << PDM_INCR_RXDR_RECEIVE_FIFO_DATA_SHIFT) /* 0xFFFFFFFF */ +/*****************************************I2STDM*****************************************/ +/* TXCR */ +#define I2STDM_TXCR_OFFSET (0x0U) +#define I2STDM_TXCR_VDW_SHIFT (0U) +#define I2STDM_TXCR_VDW_MASK (0x1FU << I2STDM_TXCR_VDW_SHIFT) /* 0x0000001F */ +#define I2STDM_TXCR_TFS_SHIFT (5U) +#define I2STDM_TXCR_TFS_MASK (0x3U << I2STDM_TXCR_TFS_SHIFT) /* 0x00000060 */ +#define I2STDM_TXCR_PBM_SHIFT (7U) +#define I2STDM_TXCR_PBM_MASK (0x3U << I2STDM_TXCR_PBM_SHIFT) /* 0x00000180 */ +#define I2STDM_TXCR_IBM_SHIFT (9U) +#define I2STDM_TXCR_IBM_MASK (0x3U << I2STDM_TXCR_IBM_SHIFT) /* 0x00000600 */ +#define I2STDM_TXCR_FBM_SHIFT (11U) +#define I2STDM_TXCR_FBM_MASK (0x1U << I2STDM_TXCR_FBM_SHIFT) /* 0x00000800 */ +#define I2STDM_TXCR_SJM_SHIFT (12U) +#define I2STDM_TXCR_SJM_MASK (0x1U << I2STDM_TXCR_SJM_SHIFT) /* 0x00001000 */ +#define I2STDM_TXCR_HWT_SHIFT (14U) +#define I2STDM_TXCR_HWT_MASK (0x1U << I2STDM_TXCR_HWT_SHIFT) /* 0x00004000 */ +#define I2STDM_TXCR_TCSR_SHIFT (15U) +#define I2STDM_TXCR_TCSR_MASK (0x3U << I2STDM_TXCR_TCSR_SHIFT) /* 0x00018000 */ +#define I2STDM_TXCR_RCNT_SHIFT (17U) +#define I2STDM_TXCR_RCNT_MASK (0x3FU << I2STDM_TXCR_RCNT_SHIFT) /* 0x007E0000 */ +#define I2STDM_TXCR_TX_PATH_SELECT0_SHIFT (23U) +#define I2STDM_TXCR_TX_PATH_SELECT0_MASK (0x3U << I2STDM_TXCR_TX_PATH_SELECT0_SHIFT) /* 0x01800000 */ +#define I2STDM_TXCR_TX_PATH_SELECT1_SHIFT (25U) +#define I2STDM_TXCR_TX_PATH_SELECT1_MASK (0x3U << I2STDM_TXCR_TX_PATH_SELECT1_SHIFT) /* 0x06000000 */ +#define I2STDM_TXCR_TX_PATH_SELECT2_SHIFT (27U) +#define I2STDM_TXCR_TX_PATH_SELECT2_MASK (0x3U << I2STDM_TXCR_TX_PATH_SELECT2_SHIFT) /* 0x18000000 */ +#define I2STDM_TXCR_TX_PATH_SELECT3_SHIFT (29U) +#define I2STDM_TXCR_TX_PATH_SELECT3_MASK (0x3U << I2STDM_TXCR_TX_PATH_SELECT3_SHIFT) /* 0x60000000 */ +/* RXCR */ +#define I2STDM_RXCR_OFFSET (0x4U) +#define I2STDM_RXCR_VDW_SHIFT (0U) +#define I2STDM_RXCR_VDW_MASK (0x1FU << I2STDM_RXCR_VDW_SHIFT) /* 0x0000001F */ +#define I2STDM_RXCR_TFS_SHIFT (5U) +#define I2STDM_RXCR_TFS_MASK (0x3U << I2STDM_RXCR_TFS_SHIFT) /* 0x00000060 */ +#define I2STDM_RXCR_PBM_SHIFT (7U) +#define I2STDM_RXCR_PBM_MASK (0x3U << I2STDM_RXCR_PBM_SHIFT) /* 0x00000180 */ +#define I2STDM_RXCR_IBM_SHIFT (9U) +#define I2STDM_RXCR_IBM_MASK (0x3U << I2STDM_RXCR_IBM_SHIFT) /* 0x00000600 */ +#define I2STDM_RXCR_FBM_SHIFT (11U) +#define I2STDM_RXCR_FBM_MASK (0x1U << I2STDM_RXCR_FBM_SHIFT) /* 0x00000800 */ +#define I2STDM_RXCR_SJM_SHIFT (12U) +#define I2STDM_RXCR_SJM_MASK (0x1U << I2STDM_RXCR_SJM_SHIFT) /* 0x00001000 */ +#define I2STDM_RXCR_HWT_SHIFT (14U) +#define I2STDM_RXCR_HWT_MASK (0x1U << I2STDM_RXCR_HWT_SHIFT) /* 0x00004000 */ +#define I2STDM_RXCR_RCSR_SHIFT (15U) +#define I2STDM_RXCR_RCSR_MASK (0x3U << I2STDM_RXCR_RCSR_SHIFT) /* 0x00018000 */ +#define I2STDM_RXCR_RX_PATH_SELECT0_SHIFT (17U) +#define I2STDM_RXCR_RX_PATH_SELECT0_MASK (0x3U << I2STDM_RXCR_RX_PATH_SELECT0_SHIFT) /* 0x00060000 */ +#define I2STDM_RXCR_RX_PATH_SELECT1_SHIFT (19U) +#define I2STDM_RXCR_RX_PATH_SELECT1_MASK (0x3U << I2STDM_RXCR_RX_PATH_SELECT1_SHIFT) /* 0x00180000 */ +#define I2STDM_RXCR_RX_PATH_SELECT2_SHIFT (21U) +#define I2STDM_RXCR_RX_PATH_SELECT2_MASK (0x3U << I2STDM_RXCR_RX_PATH_SELECT2_SHIFT) /* 0x00600000 */ +#define I2STDM_RXCR_RX_PATH_SELECT3_SHIFT (23U) +#define I2STDM_RXCR_RX_PATH_SELECT3_MASK (0x3U << I2STDM_RXCR_RX_PATH_SELECT3_SHIFT) /* 0x01800000 */ +/* CKR */ +#define I2STDM_CKR_OFFSET (0x8U) +#define I2STDM_CKR_TSD_SHIFT (0U) +#define I2STDM_CKR_TSD_MASK (0xFFU << I2STDM_CKR_TSD_SHIFT) /* 0x000000FF */ +#define I2STDM_CKR_RSD_SHIFT (8U) +#define I2STDM_CKR_RSD_MASK (0xFFU << I2STDM_CKR_RSD_SHIFT) /* 0x0000FF00 */ +#define I2STDM_CKR_TLP_SHIFT (24U) +#define I2STDM_CKR_TLP_MASK (0x1U << I2STDM_CKR_TLP_SHIFT) /* 0x01000000 */ +#define I2STDM_CKR_RLP_SHIFT (25U) +#define I2STDM_CKR_RLP_MASK (0x1U << I2STDM_CKR_RLP_SHIFT) /* 0x02000000 */ +#define I2STDM_CKR_CKP_SHIFT (26U) +#define I2STDM_CKR_CKP_MASK (0x1U << I2STDM_CKR_CKP_SHIFT) /* 0x04000000 */ +#define I2STDM_CKR_MSS_SHIFT (27U) +#define I2STDM_CKR_MSS_MASK (0x1U << I2STDM_CKR_MSS_SHIFT) /* 0x08000000 */ +#define I2STDM_CKR_LRCK_COMMON_SHIFT (28U) +#define I2STDM_CKR_LRCK_COMMON_MASK (0x3U << I2STDM_CKR_LRCK_COMMON_SHIFT) /* 0x30000000 */ +/* TXFIFOLR */ +#define I2STDM_TXFIFOLR_OFFSET (0xCU) +#define I2STDM_TXFIFOLR_TFL0_SHIFT (0U) +#define I2STDM_TXFIFOLR_TFL0_MASK (0x3FU << I2STDM_TXFIFOLR_TFL0_SHIFT) /* 0x0000003F */ +#define I2STDM_TXFIFOLR_TFL1_SHIFT (6U) +#define I2STDM_TXFIFOLR_TFL1_MASK (0x3FU << I2STDM_TXFIFOLR_TFL1_SHIFT) /* 0x00000FC0 */ +#define I2STDM_TXFIFOLR_TFL2_SHIFT (12U) +#define I2STDM_TXFIFOLR_TFL2_MASK (0x3FU << I2STDM_TXFIFOLR_TFL2_SHIFT) /* 0x0003F000 */ +#define I2STDM_TXFIFOLR_TFL3_SHIFT (18U) +#define I2STDM_TXFIFOLR_TFL3_MASK (0x3FU << I2STDM_TXFIFOLR_TFL3_SHIFT) /* 0x00FC0000 */ +/* DMACR */ +#define I2STDM_DMACR_OFFSET (0x10U) +#define I2STDM_DMACR_TDL_SHIFT (0U) +#define I2STDM_DMACR_TDL_MASK (0x1FU << I2STDM_DMACR_TDL_SHIFT) /* 0x0000001F */ +#define I2STDM_DMACR_TDE_SHIFT (8U) +#define I2STDM_DMACR_TDE_MASK (0x1U << I2STDM_DMACR_TDE_SHIFT) /* 0x00000100 */ +#define I2STDM_DMACR_RDL_SHIFT (16U) +#define I2STDM_DMACR_RDL_MASK (0x1FU << I2STDM_DMACR_RDL_SHIFT) /* 0x001F0000 */ +#define I2STDM_DMACR_RDE_SHIFT (24U) +#define I2STDM_DMACR_RDE_MASK (0x1U << I2STDM_DMACR_RDE_SHIFT) /* 0x01000000 */ +/* INTCR */ +#define I2STDM_INTCR_OFFSET (0x14U) +#define I2STDM_INTCR_TXEIE_SHIFT (0U) +#define I2STDM_INTCR_TXEIE_MASK (0x1U << I2STDM_INTCR_TXEIE_SHIFT) /* 0x00000001 */ +#define I2STDM_INTCR_TXUIE_SHIFT (1U) +#define I2STDM_INTCR_TXUIE_MASK (0x1U << I2STDM_INTCR_TXUIE_SHIFT) /* 0x00000002 */ +#define I2STDM_INTCR_TXUIC_SHIFT (2U) +#define I2STDM_INTCR_TXUIC_MASK (0x1U << I2STDM_INTCR_TXUIC_SHIFT) /* 0x00000004 */ +#define I2STDM_INTCR_TFT_SHIFT (4U) +#define I2STDM_INTCR_TFT_MASK (0x1FU << I2STDM_INTCR_TFT_SHIFT) /* 0x000001F0 */ +#define I2STDM_INTCR_RXFIE_SHIFT (16U) +#define I2STDM_INTCR_RXFIE_MASK (0x1U << I2STDM_INTCR_RXFIE_SHIFT) /* 0x00010000 */ +#define I2STDM_INTCR_RXOIE_SHIFT (17U) +#define I2STDM_INTCR_RXOIE_MASK (0x1U << I2STDM_INTCR_RXOIE_SHIFT) /* 0x00020000 */ +#define I2STDM_INTCR_RXOIC_SHIFT (18U) +#define I2STDM_INTCR_RXOIC_MASK (0x1U << I2STDM_INTCR_RXOIC_SHIFT) /* 0x00040000 */ +#define I2STDM_INTCR_RFT_SHIFT (20U) +#define I2STDM_INTCR_RFT_MASK (0x1FU << I2STDM_INTCR_RFT_SHIFT) /* 0x01F00000 */ +/* INTSR */ +#define I2STDM_INTSR_OFFSET (0x18U) +#define I2STDM_INTSR_TXEI_SHIFT (0U) +#define I2STDM_INTSR_TXEI_MASK (0x1U << I2STDM_INTSR_TXEI_SHIFT) /* 0x00000001 */ +#define I2STDM_INTSR_TXUI_SHIFT (1U) +#define I2STDM_INTSR_TXUI_MASK (0x1U << I2STDM_INTSR_TXUI_SHIFT) /* 0x00000002 */ +#define I2STDM_INTSR_RXFI_SHIFT (16U) +#define I2STDM_INTSR_RXFI_MASK (0x1U << I2STDM_INTSR_RXFI_SHIFT) /* 0x00010000 */ +#define I2STDM_INTSR_RXOI_SHIFT (17U) +#define I2STDM_INTSR_RXOI_MASK (0x1U << I2STDM_INTSR_RXOI_SHIFT) /* 0x00020000 */ +/* XFER */ +#define I2STDM_XFER_OFFSET (0x1CU) +#define I2STDM_XFER_TXS_SHIFT (0U) +#define I2STDM_XFER_TXS_MASK (0x1U << I2STDM_XFER_TXS_SHIFT) /* 0x00000001 */ +#define I2STDM_XFER_RXS_SHIFT (1U) +#define I2STDM_XFER_RXS_MASK (0x1U << I2STDM_XFER_RXS_SHIFT) /* 0x00000002 */ +/* CLR */ +#define I2STDM_CLR_OFFSET (0x20U) +#define I2STDM_CLR_TXC_SHIFT (0U) +#define I2STDM_CLR_TXC_MASK (0x1U << I2STDM_CLR_TXC_SHIFT) /* 0x00000001 */ +#define I2STDM_CLR_RXC_SHIFT (1U) +#define I2STDM_CLR_RXC_MASK (0x1U << I2STDM_CLR_RXC_SHIFT) /* 0x00000002 */ +/* TXDR */ +#define I2STDM_TXDR_OFFSET (0x24U) +#define I2STDM_TXDR_TXDR_SHIFT (0U) +#define I2STDM_TXDR_TXDR_MASK (0xFFFFFFFFU << I2STDM_TXDR_TXDR_SHIFT) /* 0xFFFFFFFF */ +/* RXDR */ +#define I2STDM_RXDR_OFFSET (0x28U) +#define I2STDM_RXDR_RXDR_SHIFT (0U) +#define I2STDM_RXDR_RXDR_MASK (0xFFFFFFFFU << I2STDM_RXDR_RXDR_SHIFT) /* 0xFFFFFFFF */ +/* RXFIFOLR */ +#define I2STDM_RXFIFOLR_OFFSET (0x2CU) +#define I2STDM_RXFIFOLR_RFL0_SHIFT (0U) +#define I2STDM_RXFIFOLR_RFL0_MASK (0x3FU << I2STDM_RXFIFOLR_RFL0_SHIFT) /* 0x0000003F */ +#define I2STDM_RXFIFOLR_RFL1_SHIFT (6U) +#define I2STDM_RXFIFOLR_RFL1_MASK (0x3FU << I2STDM_RXFIFOLR_RFL1_SHIFT) /* 0x00000FC0 */ +#define I2STDM_RXFIFOLR_RFL2_SHIFT (12U) +#define I2STDM_RXFIFOLR_RFL2_MASK (0x3FU << I2STDM_RXFIFOLR_RFL2_SHIFT) /* 0x0003F000 */ +#define I2STDM_RXFIFOLR_RFL3_SHIFT (18U) +#define I2STDM_RXFIFOLR_RFL3_MASK (0x3FU << I2STDM_RXFIFOLR_RFL3_SHIFT) /* 0x00FC0000 */ +/* TDM_TXCTRL */ +#define I2STDM_TDM_TXCTRL_OFFSET (0x30U) +#define I2STDM_TDM_TXCTRL_TDM_TX_FRAME_WIDTH_SHIFT (0U) +#define I2STDM_TDM_TXCTRL_TDM_TX_FRAME_WIDTH_MASK (0x1FFU << I2STDM_TDM_TXCTRL_TDM_TX_FRAME_WIDTH_SHIFT) /* 0x000001FF */ +#define I2STDM_TDM_TXCTRL_TDM_TX_SLOT_BIT_WIDTH_SHIFT (9U) +#define I2STDM_TDM_TXCTRL_TDM_TX_SLOT_BIT_WIDTH_MASK (0x1FU << I2STDM_TDM_TXCTRL_TDM_TX_SLOT_BIT_WIDTH_SHIFT) /* 0x00003E00 */ +#define I2STDM_TDM_TXCTRL_TDM_TX_SHIFT_CTRL_SHIFT (14U) +#define I2STDM_TDM_TXCTRL_TDM_TX_SHIFT_CTRL_MASK (0x7U << I2STDM_TDM_TXCTRL_TDM_TX_SHIFT_CTRL_SHIFT) /* 0x0001C000 */ +#define I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL0_SHIFT (17U) +#define I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL0_MASK (0x1U << I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL0_SHIFT) /* 0x00020000 */ +#define I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL1_SHIFT (18U) +#define I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL1_MASK (0x7U << I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL1_SHIFT) /* 0x001C0000 */ +/* TDM_RXCTRL */ +#define I2STDM_TDM_RXCTRL_OFFSET (0x34U) +#define I2STDM_TDM_RXCTRL_TDM_RX_FRAME_WIDTH_SHIFT (0U) +#define I2STDM_TDM_RXCTRL_TDM_RX_FRAME_WIDTH_MASK (0x1FFU << I2STDM_TDM_RXCTRL_TDM_RX_FRAME_WIDTH_SHIFT) /* 0x000001FF */ +#define I2STDM_TDM_RXCTRL_TDM_RX_SLOT_BIT_WIDTH_SHIFT (9U) +#define I2STDM_TDM_RXCTRL_TDM_RX_SLOT_BIT_WIDTH_MASK (0x1FU << I2STDM_TDM_RXCTRL_TDM_RX_SLOT_BIT_WIDTH_SHIFT) /* 0x00003E00 */ +#define I2STDM_TDM_RXCTRL_TDM_RX_SHIFT_CTRL_SHIFT (14U) +#define I2STDM_TDM_RXCTRL_TDM_RX_SHIFT_CTRL_MASK (0x7U << I2STDM_TDM_RXCTRL_TDM_RX_SHIFT_CTRL_SHIFT) /* 0x0001C000 */ +#define I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL0_SHIFT (17U) +#define I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL0_MASK (0x1U << I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL0_SHIFT) /* 0x00020000 */ +#define I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL1_SHIFT (18U) +#define I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL1_MASK (0x7U << I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL1_SHIFT) /* 0x001C0000 */ +/* CLKDIV */ +#define I2STDM_CLKDIV_OFFSET (0x38U) +#define I2STDM_CLKDIV_TX_MDIV_SHIFT (0U) +#define I2STDM_CLKDIV_TX_MDIV_MASK (0xFFU << I2STDM_CLKDIV_TX_MDIV_SHIFT) /* 0x000000FF */ +#define I2STDM_CLKDIV_RX_MDIV_SHIFT (8U) +#define I2STDM_CLKDIV_RX_MDIV_MASK (0xFFU << I2STDM_CLKDIV_RX_MDIV_SHIFT) /* 0x0000FF00 */ +/* VERSION */ +#define I2STDM_VERSION_OFFSET (0x3CU) +#define I2STDM_VERSION_I2S_VERSION_SHIFT (0U) +#define I2STDM_VERSION_I2S_VERSION_MASK (0xFFFFFFFFU << I2STDM_VERSION_I2S_VERSION_SHIFT) /* 0xFFFFFFFF */ +/******************************************VAD*******************************************/ +/* CONTROL */ +#define VAD_CONTROL_OFFSET (0x0U) +#define VAD_CONTROL_VAD_EN_SHIFT (0U) +#define VAD_CONTROL_VAD_EN_MASK (0x1U << VAD_CONTROL_VAD_EN_SHIFT) /* 0x00000001 */ +#define VAD_CONTROL_SOURCE_SELECT_SHIFT (1U) +#define VAD_CONTROL_SOURCE_SELECT_MASK (0x7U << VAD_CONTROL_SOURCE_SELECT_SHIFT) /* 0x0000000E */ +#define VAD_CONTROL_SOURCE_BURST_SHIFT (4U) +#define VAD_CONTROL_SOURCE_BURST_MASK (0x7U << VAD_CONTROL_SOURCE_BURST_SHIFT) /* 0x00000070 */ +#define VAD_CONTROL_SOURCE_BURST_NUM_SHIFT (7U) +#define VAD_CONTROL_SOURCE_BURST_NUM_MASK (0x7U << VAD_CONTROL_SOURCE_BURST_NUM_SHIFT) /* 0x00000380 */ +#define VAD_CONTROL_INCR_LENGTH_SHIFT (10U) +#define VAD_CONTROL_INCR_LENGTH_MASK (0xFU << VAD_CONTROL_INCR_LENGTH_SHIFT) /* 0x00003C00 */ +#define VAD_CONTROL_SOURCE_FIXADDR_EN_SHIFT (14U) +#define VAD_CONTROL_SOURCE_FIXADDR_EN_MASK (0x1U << VAD_CONTROL_SOURCE_FIXADDR_EN_SHIFT) /* 0x00004000 */ +#define VAD_CONTROL_VAD_MODE_SHIFT (20U) +#define VAD_CONTROL_VAD_MODE_MASK (0x3U << VAD_CONTROL_VAD_MODE_SHIFT) /* 0x00300000 */ +#define VAD_CONTROL_VOICE_CHANNEL_NUM_SHIFT (23U) +#define VAD_CONTROL_VOICE_CHANNEL_NUM_MASK (0x7U << VAD_CONTROL_VOICE_CHANNEL_NUM_SHIFT) /* 0x03800000 */ +#define VAD_CONTROL_VOICE_CHANNEL_BITWIDTH_SHIFT (26U) +#define VAD_CONTROL_VOICE_CHANNEL_BITWIDTH_MASK (0x1U << VAD_CONTROL_VOICE_CHANNEL_BITWIDTH_SHIFT) /* 0x04000000 */ +#define VAD_CONTROL_VOICE_24BIT_ALIGN_MODE_SHIFT (27U) +#define VAD_CONTROL_VOICE_24BIT_ALIGN_MODE_MASK (0x1U << VAD_CONTROL_VOICE_24BIT_ALIGN_MODE_SHIFT) /* 0x08000000 */ +#define VAD_CONTROL_VOICE_24BIT_SAT_SHIFT (28U) +#define VAD_CONTROL_VOICE_24BIT_SAT_MASK (0x1U << VAD_CONTROL_VOICE_24BIT_SAT_SHIFT) /* 0x10000000 */ +#define VAD_CONTROL_VAD_DET_CHANNEL_SHIFT (29U) +#define VAD_CONTROL_VAD_DET_CHANNEL_MASK (0x7U << VAD_CONTROL_VAD_DET_CHANNEL_SHIFT) /* 0xE0000000 */ +/* VS_ADDR */ +#define VAD_VS_ADDR_OFFSET (0x4U) +#define VAD_VS_ADDR_VS_ADDR_SHIFT (0U) +#define VAD_VS_ADDR_VS_ADDR_MASK (0xFFFFFFFFU << VAD_VS_ADDR_VS_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* TIMEOUT */ +#define VAD_TIMEOUT_OFFSET (0x4CU) +#define VAD_TIMEOUT_IDLE_TIMEOUT_THD_SHIFT (0U) +#define VAD_TIMEOUT_IDLE_TIMEOUT_THD_MASK (0xFFFFFU << VAD_TIMEOUT_IDLE_TIMEOUT_THD_SHIFT) /* 0x000FFFFF */ +#define VAD_TIMEOUT_WORK_TIMEOUT_THD_SHIFT (20U) +#define VAD_TIMEOUT_WORK_TIMEOUT_THD_MASK (0x3FFU << VAD_TIMEOUT_WORK_TIMEOUT_THD_SHIFT) /* 0x3FF00000 */ +#define VAD_TIMEOUT_IDLE_TIMEOUT_EN_SHIFT (30U) +#define VAD_TIMEOUT_IDLE_TIMEOUT_EN_MASK (0x1U << VAD_TIMEOUT_IDLE_TIMEOUT_EN_SHIFT) /* 0x40000000 */ +#define VAD_TIMEOUT_WORK_TIMEOUT_EN_SHIFT (31U) +#define VAD_TIMEOUT_WORK_TIMEOUT_EN_MASK (0x1U << VAD_TIMEOUT_WORK_TIMEOUT_EN_SHIFT) /* 0x80000000 */ +/* RAM_START_ADDR */ +#define VAD_RAM_START_ADDR_OFFSET (0x50U) +#define VAD_RAM_START_ADDR_RAM_START_ADDR_SHIFT (0U) +#define VAD_RAM_START_ADDR_RAM_START_ADDR_MASK (0xFFFFFFFFU << VAD_RAM_START_ADDR_RAM_START_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* RAM_END_ADDR */ +#define VAD_RAM_END_ADDR_OFFSET (0x54U) +#define VAD_RAM_END_ADDR_RAM_END_ADDR_SHIFT (0U) +#define VAD_RAM_END_ADDR_RAM_END_ADDR_MASK (0xFFFFFFFFU << VAD_RAM_END_ADDR_RAM_END_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* RAM_CUR_ADDR */ +#define VAD_RAM_CUR_ADDR_OFFSET (0x58U) +#define VAD_RAM_CUR_ADDR_RAM_CUR_ADDR_SHIFT (0U) +#define VAD_RAM_CUR_ADDR_RAM_CUR_ADDR_MASK (0xFFFFFFFFU << VAD_RAM_CUR_ADDR_RAM_CUR_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* DET_CON0 */ +#define VAD_DET_CON0_OFFSET (0x5CU) +#define VAD_DET_CON0_GAIN_SHIFT (0U) +#define VAD_DET_CON0_GAIN_MASK (0xFFFU << VAD_DET_CON0_GAIN_SHIFT) /* 0x00000FFF */ +#define VAD_DET_CON0_NOISE_LEVEL_SHIFT (12U) +#define VAD_DET_CON0_NOISE_LEVEL_MASK (0x7U << VAD_DET_CON0_NOISE_LEVEL_SHIFT) /* 0x00007000 */ +#define VAD_DET_CON0_VAD_CON_THD_SHIFT (16U) +#define VAD_DET_CON0_VAD_CON_THD_MASK (0xFFU << VAD_DET_CON0_VAD_CON_THD_SHIFT) /* 0x00FF0000 */ +#define VAD_DET_CON0_DIS_VAD_CON_THD_SHIFT (24U) +#define VAD_DET_CON0_DIS_VAD_CON_THD_MASK (0xFU << VAD_DET_CON0_DIS_VAD_CON_THD_SHIFT) /* 0x0F000000 */ +#define VAD_DET_CON0_VAD_THD_MODE_SHIFT (28U) +#define VAD_DET_CON0_VAD_THD_MODE_MASK (0x3U << VAD_DET_CON0_VAD_THD_MODE_SHIFT) /* 0x30000000 */ +/* DET_CON1 */ +#define VAD_DET_CON1_OFFSET (0x60U) +#define VAD_DET_CON1_SOUND_THD_SHIFT (0U) +#define VAD_DET_CON1_SOUND_THD_MASK (0xFFFFU << VAD_DET_CON1_SOUND_THD_SHIFT) /* 0x0000FFFF */ +#define VAD_DET_CON1_NOISE_SAMPLE_NUM_SHIFT (16U) +#define VAD_DET_CON1_NOISE_SAMPLE_NUM_MASK (0x3FFU << VAD_DET_CON1_NOISE_SAMPLE_NUM_SHIFT) /* 0x03FF0000 */ +#define VAD_DET_CON1_CLEAN_IIR_EN_SHIFT (26U) +#define VAD_DET_CON1_CLEAN_IIR_EN_MASK (0x1U << VAD_DET_CON1_CLEAN_IIR_EN_SHIFT) /* 0x04000000 */ +#define VAD_DET_CON1_FORCE_NOISE_CLK_EN_SHIFT (28U) +#define VAD_DET_CON1_FORCE_NOISE_CLK_EN_MASK (0x1U << VAD_DET_CON1_FORCE_NOISE_CLK_EN_SHIFT) /* 0x10000000 */ +#define VAD_DET_CON1_CLEAN_NOISE_AT_BEGIN_SHIFT (29U) +#define VAD_DET_CON1_CLEAN_NOISE_AT_BEGIN_MASK (0x1U << VAD_DET_CON1_CLEAN_NOISE_AT_BEGIN_SHIFT) /* 0x20000000 */ +#define VAD_DET_CON1_MIN_NOISE_FIND_MODE_SHIFT (30U) +#define VAD_DET_CON1_MIN_NOISE_FIND_MODE_MASK (0x1U << VAD_DET_CON1_MIN_NOISE_FIND_MODE_SHIFT) /* 0x40000000 */ +/* DET_CON2 */ +#define VAD_DET_CON2_OFFSET (0x64U) +#define VAD_DET_CON2_NOISE_FRM_NUM_SHIFT (0U) +#define VAD_DET_CON2_NOISE_FRM_NUM_MASK (0x7FU << VAD_DET_CON2_NOISE_FRM_NUM_SHIFT) /* 0x0000007F */ +#define VAD_DET_CON2_NOISE_ALPHA_SHIFT (8U) +#define VAD_DET_CON2_NOISE_ALPHA_MASK (0xFFU << VAD_DET_CON2_NOISE_ALPHA_SHIFT) /* 0x0000FF00 */ +#define VAD_DET_CON2_IIR_ANUM_0_SHIFT (16U) +#define VAD_DET_CON2_IIR_ANUM_0_MASK (0xFFFFU << VAD_DET_CON2_IIR_ANUM_0_SHIFT) /* 0xFFFF0000 */ +/* DET_CON3 */ +#define VAD_DET_CON3_OFFSET (0x68U) +#define VAD_DET_CON3_IIR_ANUM_1_SHIFT (0U) +#define VAD_DET_CON3_IIR_ANUM_1_MASK (0xFFFFU << VAD_DET_CON3_IIR_ANUM_1_SHIFT) /* 0x0000FFFF */ +#define VAD_DET_CON3_IIR_ANUM_2_SHIFT (16U) +#define VAD_DET_CON3_IIR_ANUM_2_MASK (0xFFFFU << VAD_DET_CON3_IIR_ANUM_2_SHIFT) /* 0xFFFF0000 */ +/* DET_CON4 */ +#define VAD_DET_CON4_OFFSET (0x6CU) +#define VAD_DET_CON4_IIR_ADEN_1_SHIFT (0U) +#define VAD_DET_CON4_IIR_ADEN_1_MASK (0xFFFFU << VAD_DET_CON4_IIR_ADEN_1_SHIFT) /* 0x0000FFFF */ +#define VAD_DET_CON4_IIR_ADEN_2_SHIFT (16U) +#define VAD_DET_CON4_IIR_ADEN_2_MASK (0xFFFFU << VAD_DET_CON4_IIR_ADEN_2_SHIFT) /* 0xFFFF0000 */ +/* DET_CON5 */ +#define VAD_DET_CON5_OFFSET (0x70U) +#define VAD_DET_CON5_NOISE_ABS_SHIFT (0U) +#define VAD_DET_CON5_NOISE_ABS_MASK (0xFFFFU << VAD_DET_CON5_NOISE_ABS_SHIFT) /* 0x0000FFFF */ +#define VAD_DET_CON5_IIR_RESULT_SHIFT (16U) +#define VAD_DET_CON5_IIR_RESULT_MASK (0xFFFFU << VAD_DET_CON5_IIR_RESULT_SHIFT) /* 0xFFFF0000 */ +/* INT */ +#define VAD_INT_OFFSET (0x74U) +#define VAD_INT_VAD_DET_INT_EN_SHIFT (0U) +#define VAD_INT_VAD_DET_INT_EN_MASK (0x1U << VAD_INT_VAD_DET_INT_EN_SHIFT) /* 0x00000001 */ +#define VAD_INT_ERROR_INT_EN_SHIFT (1U) +#define VAD_INT_ERROR_INT_EN_MASK (0x1U << VAD_INT_ERROR_INT_EN_SHIFT) /* 0x00000002 */ +#define VAD_INT_IDLE_TIMEOUT_INT_EN_SHIFT (2U) +#define VAD_INT_IDLE_TIMEOUT_INT_EN_MASK (0x1U << VAD_INT_IDLE_TIMEOUT_INT_EN_SHIFT) /* 0x00000004 */ +#define VAD_INT_WORK_TIMEOUT_INT_EN_SHIFT (3U) +#define VAD_INT_WORK_TIMEOUT_INT_EN_MASK (0x1U << VAD_INT_WORK_TIMEOUT_INT_EN_SHIFT) /* 0x00000008 */ +#define VAD_INT_VAD_DET_INT_SHIFT (4U) +#define VAD_INT_VAD_DET_INT_MASK (0x1U << VAD_INT_VAD_DET_INT_SHIFT) /* 0x00000010 */ +#define VAD_INT_ERROR_INT_SHIFT (5U) +#define VAD_INT_ERROR_INT_MASK (0x1U << VAD_INT_ERROR_INT_SHIFT) /* 0x00000020 */ +#define VAD_INT_IDLE_TIMEOUT_INT_SHIFT (6U) +#define VAD_INT_IDLE_TIMEOUT_INT_MASK (0x1U << VAD_INT_IDLE_TIMEOUT_INT_SHIFT) /* 0x00000040 */ +#define VAD_INT_WORK_TIMEOUT_INT_SHIFT (7U) +#define VAD_INT_WORK_TIMEOUT_INT_MASK (0x1U << VAD_INT_WORK_TIMEOUT_INT_SHIFT) /* 0x00000080 */ +#define VAD_INT_RAMP_LOOP_FLAG_SHIFT (8U) +#define VAD_INT_RAMP_LOOP_FLAG_MASK (0x1U << VAD_INT_RAMP_LOOP_FLAG_SHIFT) /* 0x00000100 */ +#define VAD_INT_VAD_IDLE_SHIFT (9U) +#define VAD_INT_VAD_IDLE_MASK (0x1U << VAD_INT_VAD_IDLE_SHIFT) /* 0x00000200 */ +#define VAD_INT_VAD_DATA_TRANS_INT_EN_SHIFT (10U) +#define VAD_INT_VAD_DATA_TRANS_INT_EN_MASK (0x1U << VAD_INT_VAD_DATA_TRANS_INT_EN_SHIFT) /* 0x00000400 */ +#define VAD_INT_VAD_DATA_TRANS_INT_SHIFT (11U) +#define VAD_INT_VAD_DATA_TRANS_INT_MASK (0x1U << VAD_INT_VAD_DATA_TRANS_INT_SHIFT) /* 0x00000800 */ +#define VAD_INT_RAMP_LOOP_FLAG_BUS_SHIFT (12U) +#define VAD_INT_RAMP_LOOP_FLAG_BUS_MASK (0x1U << VAD_INT_RAMP_LOOP_FLAG_BUS_SHIFT) /* 0x00001000 */ +/* AUX_CON0 */ +#define VAD_AUX_CON0_OFFSET (0x78U) +#define VAD_AUX_CON0_BUS_WRITE_EN_SHIFT (0U) +#define VAD_AUX_CON0_BUS_WRITE_EN_MASK (0x1U << VAD_AUX_CON0_BUS_WRITE_EN_SHIFT) /* 0x00000001 */ +#define VAD_AUX_CON0_DIS_RAM_ITF_SHIFT (1U) +#define VAD_AUX_CON0_DIS_RAM_ITF_MASK (0x1U << VAD_AUX_CON0_DIS_RAM_ITF_SHIFT) /* 0x00000002 */ +#define VAD_AUX_CON0_DATA_TRANS_TRIG_INT_EN_SHIFT (2U) +#define VAD_AUX_CON0_DATA_TRANS_TRIG_INT_EN_MASK (0x1U << VAD_AUX_CON0_DATA_TRANS_TRIG_INT_EN_SHIFT) /* 0x00000004 */ +#define VAD_AUX_CON0_DATA_TRANS_KBYTE_THD_SHIFT (4U) +#define VAD_AUX_CON0_DATA_TRANS_KBYTE_THD_MASK (0xFFU << VAD_AUX_CON0_DATA_TRANS_KBYTE_THD_SHIFT) /* 0x00000FF0 */ +#define VAD_AUX_CON0_BUS_WRITE_ADDR_MODE_SHIFT (12U) +#define VAD_AUX_CON0_BUS_WRITE_ADDR_MODE_MASK (0x1U << VAD_AUX_CON0_BUS_WRITE_ADDR_MODE_SHIFT) /* 0x00001000 */ +#define VAD_AUX_CON0_BUS_WRITE_REWORK_ADDR_MODE_SHIFT (13U) +#define VAD_AUX_CON0_BUS_WRITE_REWORK_ADDR_MODE_MASK (0x1U << VAD_AUX_CON0_BUS_WRITE_REWORK_ADDR_MODE_SHIFT) /* 0x00002000 */ +#define VAD_AUX_CON0_RAM_WRITE_REWORK_ADDR_MODE_SHIFT (14U) +#define VAD_AUX_CON0_RAM_WRITE_REWORK_ADDR_MODE_MASK (0x1U << VAD_AUX_CON0_RAM_WRITE_REWORK_ADDR_MODE_SHIFT) /* 0x00004000 */ +#define VAD_AUX_CON0_INT_TRIG_VALID_THD_SHIFT (16U) +#define VAD_AUX_CON0_INT_TRIG_VALID_THD_MASK (0xFFFU << VAD_AUX_CON0_INT_TRIG_VALID_THD_SHIFT) /* 0x0FFF0000 */ +#define VAD_AUX_CON0_INT_TRIG_CTRL_EN_SHIFT (28U) +#define VAD_AUX_CON0_INT_TRIG_CTRL_EN_MASK (0x1U << VAD_AUX_CON0_INT_TRIG_CTRL_EN_SHIFT) /* 0x10000000 */ +#define VAD_AUX_CON0_SAMPLE_CNT_EN_SHIFT (29U) +#define VAD_AUX_CON0_SAMPLE_CNT_EN_MASK (0x1U << VAD_AUX_CON0_SAMPLE_CNT_EN_SHIFT) /* 0x20000000 */ +/* SAMPLE_CNT */ +#define VAD_SAMPLE_CNT_OFFSET (0x7CU) +#define VAD_SAMPLE_CNT (0x0U) +#define VAD_SAMPLE_CNT_SAMPLE_CNT_SHIFT (0U) +#define VAD_SAMPLE_CNT_SAMPLE_CNT_MASK (0xFFFFFFFFU << VAD_SAMPLE_CNT_SAMPLE_CNT_SHIFT) /* 0xFFFFFFFF */ +/* RAM_START_ADDR_BUS */ +#define VAD_RAM_START_ADDR_BUS_OFFSET (0x80U) +#define VAD_RAM_START_ADDR_BUS_RAM_START_ADDR_BUS_SHIFT (0U) +#define VAD_RAM_START_ADDR_BUS_RAM_START_ADDR_BUS_MASK (0xFFFFFFFFU << VAD_RAM_START_ADDR_BUS_RAM_START_ADDR_BUS_SHIFT) /* 0xFFFFFFFF */ +/* RAM_END_ADDR_BUS */ +#define VAD_RAM_END_ADDR_BUS_OFFSET (0x84U) +#define VAD_RAM_END_ADDR_BUS_RAM_BEGIN_ADDR_BUS_SHIFT (0U) +#define VAD_RAM_END_ADDR_BUS_RAM_BEGIN_ADDR_BUS_MASK (0xFFFFFFFFU << VAD_RAM_END_ADDR_BUS_RAM_BEGIN_ADDR_BUS_SHIFT) /* 0xFFFFFFFF */ +/* RAM_CUR_ADDR_BUS */ +#define VAD_RAM_CUR_ADDR_BUS_OFFSET (0x88U) +#define VAD_RAM_CUR_ADDR_BUS_RAM_CUR_ADDR_BUS_SHIFT (0U) +#define VAD_RAM_CUR_ADDR_BUS_RAM_CUR_ADDR_BUS_MASK (0xFFFFFFFFU << VAD_RAM_CUR_ADDR_BUS_RAM_CUR_ADDR_BUS_SHIFT) /* 0xFFFFFFFF */ +/* AUX_CON1 */ +#define VAD_AUX_CON1_OFFSET (0x8CU) +#define VAD_AUX_CON1_DATA_TRANS_WORD_THD_SHIFT (0U) +#define VAD_AUX_CON1_DATA_TRANS_WORD_THD_MASK (0xFFFFU << VAD_AUX_CON1_DATA_TRANS_WORD_THD_SHIFT) /* 0x0000FFFF */ +#define VAD_AUX_CON1_DATA_TRANS_INT_MODE_SEL_SHIFT (16U) +#define VAD_AUX_CON1_DATA_TRANS_INT_MODE_SEL_MASK (0x1U << VAD_AUX_CON1_DATA_TRANS_INT_MODE_SEL_SHIFT) /* 0x00010000 */ +/* NOISE_FIRST_DATA */ +#define VAD_NOISE_FIRST_DATA_OFFSET (0x100U) +#define VAD_NOISE_FIRST_DATA_NOISE_FIRST_DATA_SHIFT (0U) +#define VAD_NOISE_FIRST_DATA_NOISE_FIRST_DATA_MASK (0xFFFFU << VAD_NOISE_FIRST_DATA_NOISE_FIRST_DATA_SHIFT) /* 0x0000FFFF */ +/* NOISE_LAST_DATA */ +#define VAD_NOISE_LAST_DATA_OFFSET (0x2FCU) +#define VAD_NOISE_LAST_DATA_NOISE_LAST_DATA_SHIFT (0U) +#define VAD_NOISE_LAST_DATA_NOISE_LAST_DATA_MASK (0xFFFFU << VAD_NOISE_LAST_DATA_NOISE_LAST_DATA_SHIFT) /* 0x0000FFFF */ +/******************************************VOP*******************************************/ +/* REG_CFG_DONE */ +#define VOP_REG_CFG_DONE_OFFSET (0x0U) +#define VOP_REG_CFG_DONE_REG_LOAD_GLOBAL_EN_SHIFT (0U) +#define VOP_REG_CFG_DONE_REG_LOAD_GLOBAL_EN_MASK (0x1U << VOP_REG_CFG_DONE_REG_LOAD_GLOBAL_EN_SHIFT) /* 0x00000001 */ +#define VOP_REG_CFG_DONE_REG_LOAD_WIN0_EN_SHIFT (1U) +#define VOP_REG_CFG_DONE_REG_LOAD_WIN0_EN_MASK (0x1U << VOP_REG_CFG_DONE_REG_LOAD_WIN0_EN_SHIFT) /* 0x00000002 */ +#define VOP_REG_CFG_DONE_REG_LOAD_WIN1_EN_SHIFT (2U) +#define VOP_REG_CFG_DONE_REG_LOAD_WIN1_EN_MASK (0x1U << VOP_REG_CFG_DONE_REG_LOAD_WIN1_EN_SHIFT) /* 0x00000004 */ +#define VOP_REG_CFG_DONE_REG_LOAD_WIN2_EN_SHIFT (3U) +#define VOP_REG_CFG_DONE_REG_LOAD_WIN2_EN_MASK (0x1U << VOP_REG_CFG_DONE_REG_LOAD_WIN2_EN_SHIFT) /* 0x00000008 */ +#define VOP_REG_CFG_DONE_REG_LOAD_WIN3_EN_SHIFT (4U) +#define VOP_REG_CFG_DONE_REG_LOAD_WIN3_EN_MASK (0x1U << VOP_REG_CFG_DONE_REG_LOAD_WIN3_EN_SHIFT) /* 0x00000010 */ +#define VOP_REG_CFG_DONE_REG_LOAD_SYS_EN_SHIFT (5U) +#define VOP_REG_CFG_DONE_REG_LOAD_SYS_EN_MASK (0x1U << VOP_REG_CFG_DONE_REG_LOAD_SYS_EN_SHIFT) /* 0x00000020 */ +/* VERSION */ +#define VOP_VERSION_OFFSET (0x4U) +#define VOP_VERSION (0x0U) +#define VOP_VERSION_BUILD_SHIFT (0U) +#define VOP_VERSION_BUILD_MASK (0xFFFFU << VOP_VERSION_BUILD_SHIFT) /* 0x0000FFFF */ +#define VOP_VERSION_MINOR_SHIFT (16U) +#define VOP_VERSION_MINOR_MASK (0xFFU << VOP_VERSION_MINOR_SHIFT) /* 0x00FF0000 */ +#define VOP_VERSION_MAJOR_SHIFT (24U) +#define VOP_VERSION_MAJOR_MASK (0xFFU << VOP_VERSION_MAJOR_SHIFT) /* 0xFF000000 */ +/* DSP_BG */ +#define VOP_DSP_BG_OFFSET (0x8U) +#define VOP_DSP_BG_DSP_BG_BLUE_SHIFT (0U) +#define VOP_DSP_BG_DSP_BG_BLUE_MASK (0xFFU << VOP_DSP_BG_DSP_BG_BLUE_SHIFT) /* 0x000000FF */ +#define VOP_DSP_BG_DSP_BG_GREEN_SHIFT (8U) +#define VOP_DSP_BG_DSP_BG_GREEN_MASK (0xFFU << VOP_DSP_BG_DSP_BG_GREEN_SHIFT) /* 0x0000FF00 */ +#define VOP_DSP_BG_DSP_BG_RED_SHIFT (16U) +#define VOP_DSP_BG_DSP_BG_RED_MASK (0xFFU << VOP_DSP_BG_DSP_BG_RED_SHIFT) /* 0x00FF0000 */ +/* MCU */ +#define VOP_MCU_OFFSET (0xCU) +#define VOP_MCU_MCU_PIX_TOTAL_SHIFT (0U) +#define VOP_MCU_MCU_PIX_TOTAL_MASK (0x3FU << VOP_MCU_MCU_PIX_TOTAL_SHIFT) /* 0x0000003F */ +#define VOP_MCU_MCU_CS_PST_SHIFT (6U) +#define VOP_MCU_MCU_CS_PST_MASK (0xFU << VOP_MCU_MCU_CS_PST_SHIFT) /* 0x000003C0 */ +#define VOP_MCU_MCU_CS_PEND_SHIFT (10U) +#define VOP_MCU_MCU_CS_PEND_MASK (0x3FU << VOP_MCU_MCU_CS_PEND_SHIFT) /* 0x0000FC00 */ +#define VOP_MCU_MCU_RW_PST_SHIFT (16U) +#define VOP_MCU_MCU_RW_PST_MASK (0xFU << VOP_MCU_MCU_RW_PST_SHIFT) /* 0x000F0000 */ +#define VOP_MCU_MCU_RW_PEND_SHIFT (20U) +#define VOP_MCU_MCU_RW_PEND_MASK (0x3FU << VOP_MCU_MCU_RW_PEND_SHIFT) /* 0x03F00000 */ +#define VOP_MCU_MCU_CLK_SEL_SHIFT (26U) +#define VOP_MCU_MCU_CLK_SEL_MASK (0x1U << VOP_MCU_MCU_CLK_SEL_SHIFT) /* 0x04000000 */ +#define VOP_MCU_MCU_HOLD_MODE_SHIFT (27U) +#define VOP_MCU_MCU_HOLD_MODE_MASK (0x1U << VOP_MCU_MCU_HOLD_MODE_SHIFT) /* 0x08000000 */ +#define VOP_MCU_MCU_FRAME_ST_SHIFT (28U) +#define VOP_MCU_MCU_FRAME_ST_MASK (0x1U << VOP_MCU_MCU_FRAME_ST_SHIFT) /* 0x10000000 */ +#define VOP_MCU_MCU_RS_SHIFT (29U) +#define VOP_MCU_MCU_RS_MASK (0x1U << VOP_MCU_MCU_RS_SHIFT) /* 0x20000000 */ +#define VOP_MCU_MCU_BYPASS_SHIFT (30U) +#define VOP_MCU_MCU_BYPASS_MASK (0x1U << VOP_MCU_MCU_BYPASS_SHIFT) /* 0x40000000 */ +#define VOP_MCU_MCU_TYPE_SHIFT (31U) +#define VOP_MCU_MCU_TYPE_MASK (0x1U << VOP_MCU_MCU_TYPE_SHIFT) /* 0x80000000 */ +/* SYS_CTRL0 */ +#define VOP_SYS_CTRL0_OFFSET (0x10U) +#define VOP_SYS_CTRL0_RESERVED_SHIFT (0U) +#define VOP_SYS_CTRL0_RESERVED_MASK (0xFFFFFFFFU << VOP_SYS_CTRL0_RESERVED_SHIFT) /* 0xFFFFFFFF */ +/* SYS_CTRL1 */ +#define VOP_SYS_CTRL1_OFFSET (0x14U) +#define VOP_SYS_CTRL1_SW_NOC_QOS_EN_SHIFT (0U) +#define VOP_SYS_CTRL1_SW_NOC_QOS_EN_MASK (0x1U << VOP_SYS_CTRL1_SW_NOC_QOS_EN_SHIFT) /* 0x00000001 */ +#define VOP_SYS_CTRL1_SW_NOC_QOS_VALUE_SHIFT (1U) +#define VOP_SYS_CTRL1_SW_NOC_QOS_VALUE_MASK (0x3U << VOP_SYS_CTRL1_SW_NOC_QOS_VALUE_SHIFT) /* 0x00000006 */ +#define VOP_SYS_CTRL1_SW_NOC_HURRY_EN_SHIFT (4U) +#define VOP_SYS_CTRL1_SW_NOC_HURRY_EN_MASK (0x1U << VOP_SYS_CTRL1_SW_NOC_HURRY_EN_SHIFT) /* 0x00000010 */ +#define VOP_SYS_CTRL1_SW_NOC_HURRY_VALUE_SHIFT (5U) +#define VOP_SYS_CTRL1_SW_NOC_HURRY_VALUE_MASK (0x3U << VOP_SYS_CTRL1_SW_NOC_HURRY_VALUE_SHIFT) /* 0x00000060 */ +#define VOP_SYS_CTRL1_SW_NOC_HURRY_THRESHOLD_SHIFT (8U) +#define VOP_SYS_CTRL1_SW_NOC_HURRY_THRESHOLD_MASK (0xFU << VOP_SYS_CTRL1_SW_NOC_HURRY_THRESHOLD_SHIFT) /* 0x00000F00 */ +#define VOP_SYS_CTRL1_SW_AXI_MAX_OUTSTAND_EN_SHIFT (12U) +#define VOP_SYS_CTRL1_SW_AXI_MAX_OUTSTAND_EN_MASK (0x1U << VOP_SYS_CTRL1_SW_AXI_MAX_OUTSTAND_EN_SHIFT) /* 0x00001000 */ +#define VOP_SYS_CTRL1_SW_AXI_MAX_OUTSTAND_NUM_SHIFT (16U) +#define VOP_SYS_CTRL1_SW_AXI_MAX_OUTSTAND_NUM_MASK (0x1FU << VOP_SYS_CTRL1_SW_AXI_MAX_OUTSTAND_NUM_SHIFT) /* 0x001F0000 */ +/* SYS_CTRL2 */ +#define VOP_SYS_CTRL2_OFFSET (0x18U) +#define VOP_SYS_CTRL2_IMD_AUTO_GATING_EN_SHIFT (0U) +#define VOP_SYS_CTRL2_IMD_AUTO_GATING_EN_MASK (0x1U << VOP_SYS_CTRL2_IMD_AUTO_GATING_EN_SHIFT) /* 0x00000001 */ +#define VOP_SYS_CTRL2_IMD_VOP_STANDBY_EN_SHIFT (1U) +#define VOP_SYS_CTRL2_IMD_VOP_STANDBY_EN_MASK (0x1U << VOP_SYS_CTRL2_IMD_VOP_STANDBY_EN_SHIFT) /* 0x00000002 */ +#define VOP_SYS_CTRL2_IMD_VOP_DMA_STOP_SHIFT (2U) +#define VOP_SYS_CTRL2_IMD_VOP_DMA_STOP_MASK (0x1U << VOP_SYS_CTRL2_IMD_VOP_DMA_STOP_SHIFT) /* 0x00000004 */ +#define VOP_SYS_CTRL2_IMD_DSP_OUT_ZERO_SHIFT (3U) +#define VOP_SYS_CTRL2_IMD_DSP_OUT_ZERO_MASK (0x1U << VOP_SYS_CTRL2_IMD_DSP_OUT_ZERO_SHIFT) /* 0x00000008 */ +#define VOP_SYS_CTRL2_IMD_YUV_CLIP_SHIFT (4U) +#define VOP_SYS_CTRL2_IMD_YUV_CLIP_MASK (0x1U << VOP_SYS_CTRL2_IMD_YUV_CLIP_SHIFT) /* 0x00000010 */ +#define VOP_SYS_CTRL2_IMD_DSP_DATA_OUT_MODE_SHIFT (6U) +#define VOP_SYS_CTRL2_IMD_DSP_DATA_OUT_MODE_MASK (0x1U << VOP_SYS_CTRL2_IMD_DSP_DATA_OUT_MODE_SHIFT) /* 0x00000040 */ +#define VOP_SYS_CTRL2_SW_IO_PAD_CLK_SEL_SHIFT (7U) +#define VOP_SYS_CTRL2_SW_IO_PAD_CLK_SEL_MASK (0x1U << VOP_SYS_CTRL2_SW_IO_PAD_CLK_SEL_SHIFT) /* 0x00000080 */ +#define VOP_SYS_CTRL2_IMD_EDPI_TE_EN_SHIFT (9U) +#define VOP_SYS_CTRL2_IMD_EDPI_TE_EN_MASK (0x1U << VOP_SYS_CTRL2_IMD_EDPI_TE_EN_SHIFT) /* 0x00000200 */ +#define VOP_SYS_CTRL2_IMD_EDPI_CTRL_MODE_SHIFT (10U) +#define VOP_SYS_CTRL2_IMD_EDPI_CTRL_MODE_MASK (0x1U << VOP_SYS_CTRL2_IMD_EDPI_CTRL_MODE_SHIFT) /* 0x00000400 */ +#define VOP_SYS_CTRL2_IMD_EDPI_WMS_FS_SHIFT (11U) +#define VOP_SYS_CTRL2_IMD_EDPI_WMS_FS_MASK (0x1U << VOP_SYS_CTRL2_IMD_EDPI_WMS_FS_SHIFT) /* 0x00000800 */ +#define VOP_SYS_CTRL2_IMD_DSP_TIMING_IMD_SHIFT (12U) +#define VOP_SYS_CTRL2_IMD_DSP_TIMING_IMD_MASK (0x1U << VOP_SYS_CTRL2_IMD_DSP_TIMING_IMD_SHIFT) /* 0x00001000 */ +#define VOP_SYS_CTRL2_IMD_GLOBAL_REGDONE_EN_SHIFT (13U) +#define VOP_SYS_CTRL2_IMD_GLOBAL_REGDONE_EN_MASK (0x1U << VOP_SYS_CTRL2_IMD_GLOBAL_REGDONE_EN_SHIFT) /* 0x00002000 */ +#define VOP_SYS_CTRL2_FS_ADDR_MASK_EN_SHIFT (14U) +#define VOP_SYS_CTRL2_FS_ADDR_MASK_EN_MASK (0x1U << VOP_SYS_CTRL2_FS_ADDR_MASK_EN_SHIFT) /* 0x00004000 */ +#define VOP_SYS_CTRL2_DCF_IDLE_EN_SHIFT (15U) +#define VOP_SYS_CTRL2_DCF_IDLE_EN_MASK (0x1U << VOP_SYS_CTRL2_DCF_IDLE_EN_SHIFT) /* 0x00008000 */ +#define VOP_SYS_CTRL2_POST_EMPTY_HOLD_EN_SHIFT (27U) +#define VOP_SYS_CTRL2_POST_EMPTY_HOLD_EN_MASK (0x1U << VOP_SYS_CTRL2_POST_EMPTY_HOLD_EN_SHIFT) /* 0x08000000 */ +#define VOP_SYS_CTRL2_DSC_EN_SHIFT (28U) +#define VOP_SYS_CTRL2_DSC_EN_MASK (0x1U << VOP_SYS_CTRL2_DSC_EN_SHIFT) /* 0x10000000 */ +#define VOP_SYS_CTRL2_DSC_BYPASS_EN_SHIFT (29U) +#define VOP_SYS_CTRL2_DSC_BYPASS_EN_MASK (0x1U << VOP_SYS_CTRL2_DSC_BYPASS_EN_SHIFT) /* 0x20000000 */ +#define VOP_SYS_CTRL2_DPHY_FRM_SWITCH_EN_SHIFT (30U) +#define VOP_SYS_CTRL2_DPHY_FRM_SWITCH_EN_MASK (0x1U << VOP_SYS_CTRL2_DPHY_FRM_SWITCH_EN_SHIFT) /* 0x40000000 */ +#define VOP_SYS_CTRL2_IMD_EDPI_WMS_MODE_SHIFT (31U) +#define VOP_SYS_CTRL2_IMD_EDPI_WMS_MODE_MASK (0x1U << VOP_SYS_CTRL2_IMD_EDPI_WMS_MODE_SHIFT) /* 0x80000000 */ +/* DSP_CTRL0 */ +#define VOP_DSP_CTRL0_OFFSET (0x20U) +#define VOP_DSP_CTRL0_RGB_DCLK_EN_SHIFT (0U) +#define VOP_DSP_CTRL0_RGB_DCLK_EN_MASK (0x1U << VOP_DSP_CTRL0_RGB_DCLK_EN_SHIFT) /* 0x00000001 */ +#define VOP_DSP_CTRL0_RGB_DCLK_POL_SHIFT (1U) +#define VOP_DSP_CTRL0_RGB_DCLK_POL_MASK (0x1U << VOP_DSP_CTRL0_RGB_DCLK_POL_SHIFT) /* 0x00000002 */ +#define VOP_DSP_CTRL0_RGB_HSYNC_POL_SHIFT (2U) +#define VOP_DSP_CTRL0_RGB_HSYNC_POL_MASK (0x1U << VOP_DSP_CTRL0_RGB_HSYNC_POL_SHIFT) /* 0x00000004 */ +#define VOP_DSP_CTRL0_RGB_VSYNC_POL_SHIFT (3U) +#define VOP_DSP_CTRL0_RGB_VSYNC_POL_MASK (0x1U << VOP_DSP_CTRL0_RGB_VSYNC_POL_SHIFT) /* 0x00000008 */ +#define VOP_DSP_CTRL0_RGB_DEN_POL_SHIFT (4U) +#define VOP_DSP_CTRL0_RGB_DEN_POL_MASK (0x1U << VOP_DSP_CTRL0_RGB_DEN_POL_SHIFT) /* 0x00000010 */ +#define VOP_DSP_CTRL0_MIPI_DCLK_EN_SHIFT (24U) +#define VOP_DSP_CTRL0_MIPI_DCLK_EN_MASK (0x1U << VOP_DSP_CTRL0_MIPI_DCLK_EN_SHIFT) /* 0x01000000 */ +#define VOP_DSP_CTRL0_MIPI_DCLK_POL_SHIFT (25U) +#define VOP_DSP_CTRL0_MIPI_DCLK_POL_MASK (0x1U << VOP_DSP_CTRL0_MIPI_DCLK_POL_SHIFT) /* 0x02000000 */ +#define VOP_DSP_CTRL0_MIPI_HSYNC_POL_SHIFT (26U) +#define VOP_DSP_CTRL0_MIPI_HSYNC_POL_MASK (0x1U << VOP_DSP_CTRL0_MIPI_HSYNC_POL_SHIFT) /* 0x04000000 */ +#define VOP_DSP_CTRL0_MIPI_VSYNC_POL_SHIFT (27U) +#define VOP_DSP_CTRL0_MIPI_VSYNC_POL_MASK (0x1U << VOP_DSP_CTRL0_MIPI_VSYNC_POL_SHIFT) /* 0x08000000 */ +#define VOP_DSP_CTRL0_MIPI_DEN_POL_SHIFT (28U) +#define VOP_DSP_CTRL0_MIPI_DEN_POL_MASK (0x1U << VOP_DSP_CTRL0_MIPI_DEN_POL_SHIFT) /* 0x10000000 */ +/* DSP_CTRL1 */ +#define VOP_DSP_CTRL1_OFFSET (0x24U) +#define VOP_DSP_CTRL1_RESERVED_SHIFT (0U) +#define VOP_DSP_CTRL1_RESERVED_MASK (0xFFFFFFFFU << VOP_DSP_CTRL1_RESERVED_SHIFT) /* 0xFFFFFFFF */ +/* DSP_CTRL2 */ +#define VOP_DSP_CTRL2_OFFSET (0x28U) +#define VOP_DSP_CTRL2_DITHER_UP_SHIFT (2U) +#define VOP_DSP_CTRL2_DITHER_UP_MASK (0x1U << VOP_DSP_CTRL2_DITHER_UP_SHIFT) /* 0x00000004 */ +#define VOP_DSP_CTRL2_SW_OVERLAY_MODE_SHIFT (4U) +#define VOP_DSP_CTRL2_SW_OVERLAY_MODE_MASK (0x1U << VOP_DSP_CTRL2_SW_OVERLAY_MODE_SHIFT) /* 0x00000010 */ +#define VOP_DSP_CTRL2_DSP_LUT_EN_SHIFT (5U) +#define VOP_DSP_CTRL2_DSP_LUT_EN_MASK (0x1U << VOP_DSP_CTRL2_DSP_LUT_EN_SHIFT) /* 0x00000020 */ +#define VOP_DSP_CTRL2_DITHER_DOWN_MODE_SHIFT (6U) +#define VOP_DSP_CTRL2_DITHER_DOWN_MODE_MASK (0x1U << VOP_DSP_CTRL2_DITHER_DOWN_MODE_SHIFT) /* 0x00000040 */ +#define VOP_DSP_CTRL2_DITHER_DOWN_SEL_SHIFT (7U) +#define VOP_DSP_CTRL2_DITHER_DOWN_SEL_MASK (0x1U << VOP_DSP_CTRL2_DITHER_DOWN_SEL_SHIFT) /* 0x00000080 */ +#define VOP_DSP_CTRL2_DITHER_DOWN_SHIFT (8U) +#define VOP_DSP_CTRL2_DITHER_DOWN_MASK (0x1U << VOP_DSP_CTRL2_DITHER_DOWN_SHIFT) /* 0x00000100 */ +#define VOP_DSP_CTRL2_DSP_BG_SWAP_SHIFT (9U) +#define VOP_DSP_CTRL2_DSP_BG_SWAP_MASK (0x1U << VOP_DSP_CTRL2_DSP_BG_SWAP_SHIFT) /* 0x00000200 */ +#define VOP_DSP_CTRL2_DSP_RB_SWAP_SHIFT (11U) +#define VOP_DSP_CTRL2_DSP_RB_SWAP_MASK (0x1U << VOP_DSP_CTRL2_DSP_RB_SWAP_SHIFT) /* 0x00000800 */ +#define VOP_DSP_CTRL2_DSP_RG_SWAP_SHIFT (12U) +#define VOP_DSP_CTRL2_DSP_RG_SWAP_MASK (0x1U << VOP_DSP_CTRL2_DSP_RG_SWAP_SHIFT) /* 0x00001000 */ +#define VOP_DSP_CTRL2_DSP_BLANK_EN_SHIFT (14U) +#define VOP_DSP_CTRL2_DSP_BLANK_EN_MASK (0x1U << VOP_DSP_CTRL2_DSP_BLANK_EN_SHIFT) /* 0x00004000 */ +#define VOP_DSP_CTRL2_DSP_BLACK_EN_SHIFT (15U) +#define VOP_DSP_CTRL2_DSP_BLACK_EN_MASK (0x1U << VOP_DSP_CTRL2_DSP_BLACK_EN_SHIFT) /* 0x00008000 */ +#define VOP_DSP_CTRL2_DSP_OUT_MODE_SHIFT (16U) +#define VOP_DSP_CTRL2_DSP_OUT_MODE_MASK (0xFU << VOP_DSP_CTRL2_DSP_OUT_MODE_SHIFT) /* 0x000F0000 */ +#define VOP_DSP_CTRL2_DSP_LAYER1_SEL_SHIFT (22U) +#define VOP_DSP_CTRL2_DSP_LAYER1_SEL_MASK (0x3U << VOP_DSP_CTRL2_DSP_LAYER1_SEL_SHIFT) /* 0x00C00000 */ +#define VOP_DSP_CTRL2_DSP_LAYER2_SEL_SHIFT (24U) +#define VOP_DSP_CTRL2_DSP_LAYER2_SEL_MASK (0x3U << VOP_DSP_CTRL2_DSP_LAYER2_SEL_SHIFT) /* 0x03000000 */ +#define VOP_DSP_CTRL2_DSP_LAYER3_SEL_SHIFT (26U) +#define VOP_DSP_CTRL2_DSP_LAYER3_SEL_MASK (0x3U << VOP_DSP_CTRL2_DSP_LAYER3_SEL_SHIFT) /* 0x0C000000 */ +/* VOP_STATUS */ +#define VOP_VOP_STATUS_OFFSET (0x2CU) +#define VOP_VOP_STATUS_DSP_BLANKING_EN_ASYNC_AFF2_SHIFT (0U) +#define VOP_VOP_STATUS_DSP_BLANKING_EN_ASYNC_AFF2_MASK (0x1U << VOP_VOP_STATUS_DSP_BLANKING_EN_ASYNC_AFF2_SHIFT) /* 0x00000001 */ +#define VOP_VOP_STATUS_DPHY_SWITCH_STATUS_SHIFT (1U) +#define VOP_VOP_STATUS_DPHY_SWITCH_STATUS_MASK (0x1U << VOP_VOP_STATUS_DPHY_SWITCH_STATUS_SHIFT) /* 0x00000002 */ +#define VOP_VOP_STATUS_INT_RAW_DMA_FINISH_SHIFT (2U) +#define VOP_VOP_STATUS_INT_RAW_DMA_FINISH_MASK (0x1U << VOP_VOP_STATUS_INT_RAW_DMA_FINISH_SHIFT) /* 0x00000004 */ +#define VOP_VOP_STATUS_DMA_STOP_VALID_SHIFT (4U) +#define VOP_VOP_STATUS_DMA_STOP_VALID_MASK (0x1U << VOP_VOP_STATUS_DMA_STOP_VALID_SHIFT) /* 0x00000010 */ +#define VOP_VOP_STATUS_INTR_DMA_FINISH_MUX_SHIFT (8U) +#define VOP_VOP_STATUS_INTR_DMA_FINISH_MUX_MASK (0x1U << VOP_VOP_STATUS_INTR_DMA_FINISH_MUX_SHIFT) /* 0x00000100 */ +#define VOP_VOP_STATUS_INTR_LINE_FLAG0_MUX_SHIFT (9U) +#define VOP_VOP_STATUS_INTR_LINE_FLAG0_MUX_MASK (0x1U << VOP_VOP_STATUS_INTR_LINE_FLAG0_MUX_SHIFT) /* 0x00000200 */ +#define VOP_VOP_STATUS_INTR_LINE_FLAG1_MUX_SHIFT (10U) +#define VOP_VOP_STATUS_INTR_LINE_FLAG1_MUX_MASK (0x1U << VOP_VOP_STATUS_INTR_LINE_FLAG1_MUX_SHIFT) /* 0x00000400 */ +/* LINE_FLAG */ +#define VOP_LINE_FLAG_OFFSET (0x30U) +#define VOP_LINE_FLAG_DSP_LINE_FLAG0_NUM_SHIFT (0U) +#define VOP_LINE_FLAG_DSP_LINE_FLAG0_NUM_MASK (0xFFFU << VOP_LINE_FLAG_DSP_LINE_FLAG0_NUM_SHIFT) /* 0x00000FFF */ +#define VOP_LINE_FLAG_DSP_LINE_FLAG1_NUM_SHIFT (16U) +#define VOP_LINE_FLAG_DSP_LINE_FLAG1_NUM_MASK (0xFFFU << VOP_LINE_FLAG_DSP_LINE_FLAG1_NUM_SHIFT) /* 0x0FFF0000 */ +/* INTR_EN */ +#define VOP_INTR_EN_OFFSET (0x34U) +#define VOP_INTR_EN_FS0_INTR_EN_SHIFT (0U) +#define VOP_INTR_EN_FS0_INTR_EN_MASK (0x1U << VOP_INTR_EN_FS0_INTR_EN_SHIFT) /* 0x00000001 */ +#define VOP_INTR_EN_FS1_INTR_EN_SHIFT (1U) +#define VOP_INTR_EN_FS1_INTR_EN_MASK (0x1U << VOP_INTR_EN_FS1_INTR_EN_SHIFT) /* 0x00000002 */ +#define VOP_INTR_EN_ADDR_SAME_INTR_EN_SHIFT (2U) +#define VOP_INTR_EN_ADDR_SAME_INTR_EN_MASK (0x1U << VOP_INTR_EN_ADDR_SAME_INTR_EN_SHIFT) /* 0x00000004 */ +#define VOP_INTR_EN_LINE_FLAG0_INTR_EN_SHIFT (3U) +#define VOP_INTR_EN_LINE_FLAG0_INTR_EN_MASK (0x1U << VOP_INTR_EN_LINE_FLAG0_INTR_EN_SHIFT) /* 0x00000008 */ +#define VOP_INTR_EN_LINE_FLAG1_INTR_EN_SHIFT (4U) +#define VOP_INTR_EN_LINE_FLAG1_INTR_EN_MASK (0x1U << VOP_INTR_EN_LINE_FLAG1_INTR_EN_SHIFT) /* 0x00000010 */ +#define VOP_INTR_EN_BUS_ERROR_INTR_EN_SHIFT (5U) +#define VOP_INTR_EN_BUS_ERROR_INTR_EN_MASK (0x1U << VOP_INTR_EN_BUS_ERROR_INTR_EN_SHIFT) /* 0x00000020 */ +#define VOP_INTR_EN_WIN0_EMPTY_INTR_EN_SHIFT (7U) +#define VOP_INTR_EN_WIN0_EMPTY_INTR_EN_MASK (0x1U << VOP_INTR_EN_WIN0_EMPTY_INTR_EN_SHIFT) /* 0x00000080 */ +#define VOP_INTR_EN_WIN1_EMPTY_INTR_EN_SHIFT (8U) +#define VOP_INTR_EN_WIN1_EMPTY_INTR_EN_MASK (0x1U << VOP_INTR_EN_WIN1_EMPTY_INTR_EN_SHIFT) /* 0x00000100 */ +#define VOP_INTR_EN_WIN2_EMPTY_INTR_EN_SHIFT (9U) +#define VOP_INTR_EN_WIN2_EMPTY_INTR_EN_MASK (0x1U << VOP_INTR_EN_WIN2_EMPTY_INTR_EN_SHIFT) /* 0x00000200 */ +#define VOP_INTR_EN_DSP_HOLD_VALID_INTR_EN_SHIFT (10U) +#define VOP_INTR_EN_DSP_HOLD_VALID_INTR_EN_MASK (0x1U << VOP_INTR_EN_DSP_HOLD_VALID_INTR_EN_SHIFT) /* 0x00000400 */ +#define VOP_INTR_EN_DMA_FRM_FSH_INTR_EN_SHIFT (11U) +#define VOP_INTR_EN_DMA_FRM_FSH_INTR_EN_MASK (0x1U << VOP_INTR_EN_DMA_FRM_FSH_INTR_EN_SHIFT) /* 0x00000800 */ +#define VOP_INTR_EN_POST_EMPTY_INTR_EN_SHIFT (12U) +#define VOP_INTR_EN_POST_EMPTY_INTR_EN_MASK (0x1U << VOP_INTR_EN_POST_EMPTY_INTR_EN_SHIFT) /* 0x00001000 */ +#define VOP_INTR_EN_POST_LB_ALMOST_FULL_INTR_EN_SHIFT (13U) +#define VOP_INTR_EN_POST_LB_ALMOST_FULL_INTR_EN_MASK (0x1U << VOP_INTR_EN_POST_LB_ALMOST_FULL_INTR_EN_SHIFT) /* 0x00002000 */ +#define VOP_INTR_EN_POST_LB_ALMOST_EMPTY_INTR_EN_SHIFT (14U) +#define VOP_INTR_EN_POST_LB_ALMOST_EMPTY_INTR_EN_MASK (0x1U << VOP_INTR_EN_POST_LB_ALMOST_EMPTY_INTR_EN_SHIFT) /* 0x00004000 */ +/* INTR_CLEAR */ +#define VOP_INTR_CLEAR_OFFSET (0x38U) +#define VOP_INTR_CLEAR_FS0_INTR_CLR_SHIFT (0U) +#define VOP_INTR_CLEAR_FS0_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_FS0_INTR_CLR_SHIFT) /* 0x00000001 */ +#define VOP_INTR_CLEAR_FS1_INTR_CLR_SHIFT (1U) +#define VOP_INTR_CLEAR_FS1_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_FS1_INTR_CLR_SHIFT) /* 0x00000002 */ +#define VOP_INTR_CLEAR_ADDR_SAME_INTR_CLR_SHIFT (2U) +#define VOP_INTR_CLEAR_ADDR_SAME_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_ADDR_SAME_INTR_CLR_SHIFT) /* 0x00000004 */ +#define VOP_INTR_CLEAR_LINE_FLAG0_INTR_CLR_SHIFT (3U) +#define VOP_INTR_CLEAR_LINE_FLAG0_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_LINE_FLAG0_INTR_CLR_SHIFT) /* 0x00000008 */ +#define VOP_INTR_CLEAR_LINE_FLAG1_INTR_CLR_SHIFT (4U) +#define VOP_INTR_CLEAR_LINE_FLAG1_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_LINE_FLAG1_INTR_CLR_SHIFT) /* 0x00000010 */ +#define VOP_INTR_CLEAR_BUS_ERROR_INTR_CLR_SHIFT (5U) +#define VOP_INTR_CLEAR_BUS_ERROR_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_BUS_ERROR_INTR_CLR_SHIFT) /* 0x00000020 */ +#define VOP_INTR_CLEAR_WIN0_EMPTY_INTR_CLR_SHIFT (7U) +#define VOP_INTR_CLEAR_WIN0_EMPTY_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_WIN0_EMPTY_INTR_CLR_SHIFT) /* 0x00000080 */ +#define VOP_INTR_CLEAR_WIN1_EMPTY_INTR_CLR_SHIFT (8U) +#define VOP_INTR_CLEAR_WIN1_EMPTY_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_WIN1_EMPTY_INTR_CLR_SHIFT) /* 0x00000100 */ +#define VOP_INTR_CLEAR_WIN2_EMPTY_INTR_CLR_SHIFT (9U) +#define VOP_INTR_CLEAR_WIN2_EMPTY_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_WIN2_EMPTY_INTR_CLR_SHIFT) /* 0x00000200 */ +#define VOP_INTR_CLEAR_DSP_HOLD_VALID_INTR_CLR_SHIFT (10U) +#define VOP_INTR_CLEAR_DSP_HOLD_VALID_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_DSP_HOLD_VALID_INTR_CLR_SHIFT) /* 0x00000400 */ +#define VOP_INTR_CLEAR_DMA_FRM_FSH_INTR_CLR_SHIFT (11U) +#define VOP_INTR_CLEAR_DMA_FRM_FSH_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_DMA_FRM_FSH_INTR_CLR_SHIFT) /* 0x00000800 */ +#define VOP_INTR_CLEAR_POST_EMPTY_INTR_CLR_SHIFT (12U) +#define VOP_INTR_CLEAR_POST_EMPTY_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_POST_EMPTY_INTR_CLR_SHIFT) /* 0x00001000 */ +#define VOP_INTR_CLEAR_POST_LB_ALMOST_FULL_INTR_CLR_SHIFT (13U) +#define VOP_INTR_CLEAR_POST_LB_ALMOST_FULL_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_POST_LB_ALMOST_FULL_INTR_CLR_SHIFT) /* 0x00002000 */ +#define VOP_INTR_CLEAR_POST_LB_ALMOST_EMPTY_INTR_CLR_SHIFT (14U) +#define VOP_INTR_CLEAR_POST_LB_ALMOST_EMPTY_INTR_CLR_MASK (0x1U << VOP_INTR_CLEAR_POST_LB_ALMOST_EMPTY_INTR_CLR_SHIFT) /* 0x00004000 */ +/* INTR_STATUS */ +#define VOP_INTR_STATUS_OFFSET (0x3CU) +#define VOP_INTR_STATUS_FS0_INTR_STS_SHIFT (0U) +#define VOP_INTR_STATUS_FS0_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_FS0_INTR_STS_SHIFT) /* 0x00000001 */ +#define VOP_INTR_STATUS_FS1_INTR_STS_SHIFT (1U) +#define VOP_INTR_STATUS_FS1_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_FS1_INTR_STS_SHIFT) /* 0x00000002 */ +#define VOP_INTR_STATUS_ADDR_SAME_INTR_STS_SHIFT (2U) +#define VOP_INTR_STATUS_ADDR_SAME_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_ADDR_SAME_INTR_STS_SHIFT) /* 0x00000004 */ +#define VOP_INTR_STATUS_LINE_FLAG0_INTR_STS_SHIFT (3U) +#define VOP_INTR_STATUS_LINE_FLAG0_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_LINE_FLAG0_INTR_STS_SHIFT) /* 0x00000008 */ +#define VOP_INTR_STATUS_LINE_FLAG1_INTR_STS_SHIFT (4U) +#define VOP_INTR_STATUS_LINE_FLAG1_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_LINE_FLAG1_INTR_STS_SHIFT) /* 0x00000010 */ +#define VOP_INTR_STATUS_BUS_ERROR_INTR_STS_SHIFT (5U) +#define VOP_INTR_STATUS_BUS_ERROR_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_BUS_ERROR_INTR_STS_SHIFT) /* 0x00000020 */ +#define VOP_INTR_STATUS_WIN0_EMPTY_INTR_STS_SHIFT (7U) +#define VOP_INTR_STATUS_WIN0_EMPTY_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_WIN0_EMPTY_INTR_STS_SHIFT) /* 0x00000080 */ +#define VOP_INTR_STATUS_WIN1_EMPTY_INTR_STS_SHIFT (8U) +#define VOP_INTR_STATUS_WIN1_EMPTY_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_WIN1_EMPTY_INTR_STS_SHIFT) /* 0x00000100 */ +#define VOP_INTR_STATUS_WIN2_EMPTY_INTR_STS_SHIFT (9U) +#define VOP_INTR_STATUS_WIN2_EMPTY_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_WIN2_EMPTY_INTR_STS_SHIFT) /* 0x00000200 */ +#define VOP_INTR_STATUS_DSP_HOLD_VALID_INTR_STS_SHIFT (10U) +#define VOP_INTR_STATUS_DSP_HOLD_VALID_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_DSP_HOLD_VALID_INTR_STS_SHIFT) /* 0x00000400 */ +#define VOP_INTR_STATUS_DMA_FRM_FSH_INTR_STS_SHIFT (11U) +#define VOP_INTR_STATUS_DMA_FRM_FSH_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_DMA_FRM_FSH_INTR_STS_SHIFT) /* 0x00000800 */ +#define VOP_INTR_STATUS_POST_EMPTY_INTR_STS_SHIFT (12U) +#define VOP_INTR_STATUS_POST_EMPTY_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_POST_EMPTY_INTR_STS_SHIFT) /* 0x00001000 */ +#define VOP_INTR_STATUS_POST_LB_ALMOST_FULL_INTR_SHIFT (13U) +#define VOP_INTR_STATUS_POST_LB_ALMOST_FULL_INTR_MASK (0x1U << VOP_INTR_STATUS_POST_LB_ALMOST_FULL_INTR_SHIFT) /* 0x00002000 */ +#define VOP_INTR_STATUS_POST_LB_ALMOST_EMPTY_INTR_STS_SHIFT (14U) +#define VOP_INTR_STATUS_POST_LB_ALMOST_EMPTY_INTR_STS_MASK (0x1U << VOP_INTR_STATUS_POST_LB_ALMOST_EMPTY_INTR_STS_SHIFT) /* 0x00004000 */ +#define VOP_INTR_STATUS_FS0_INTR_RAW_STS_SHIFT (16U) +#define VOP_INTR_STATUS_FS0_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_FS0_INTR_RAW_STS_SHIFT) /* 0x00010000 */ +#define VOP_INTR_STATUS_FS1_INTR_RAW_STS_SHIFT (17U) +#define VOP_INTR_STATUS_FS1_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_FS1_INTR_RAW_STS_SHIFT) /* 0x00020000 */ +#define VOP_INTR_STATUS_ADDR_SAME_INTR_RAW_STS_SHIFT (18U) +#define VOP_INTR_STATUS_ADDR_SAME_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_ADDR_SAME_INTR_RAW_STS_SHIFT) /* 0x00040000 */ +#define VOP_INTR_STATUS_LINE_FLAG0_INTR_RAW_STS_SHIFT (19U) +#define VOP_INTR_STATUS_LINE_FLAG0_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_LINE_FLAG0_INTR_RAW_STS_SHIFT) /* 0x00080000 */ +#define VOP_INTR_STATUS_LINE_FLAG1_INTR_RAW_STS_SHIFT (20U) +#define VOP_INTR_STATUS_LINE_FLAG1_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_LINE_FLAG1_INTR_RAW_STS_SHIFT) /* 0x00100000 */ +#define VOP_INTR_STATUS_BUS_ERROR_INTR_RAW_STS_SHIFT (21U) +#define VOP_INTR_STATUS_BUS_ERROR_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_BUS_ERROR_INTR_RAW_STS_SHIFT) /* 0x00200000 */ +#define VOP_INTR_STATUS_WIN0_EMPTY_INTR_RAW_STS_SHIFT (23U) +#define VOP_INTR_STATUS_WIN0_EMPTY_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_WIN0_EMPTY_INTR_RAW_STS_SHIFT) /* 0x00800000 */ +#define VOP_INTR_STATUS_WIN1_EMPTY_INTR_RAW_STS_SHIFT (24U) +#define VOP_INTR_STATUS_WIN1_EMPTY_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_WIN1_EMPTY_INTR_RAW_STS_SHIFT) /* 0x01000000 */ +#define VOP_INTR_STATUS_WIN2_EMPTY_INTR_RAW_STS_SHIFT (25U) +#define VOP_INTR_STATUS_WIN2_EMPTY_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_WIN2_EMPTY_INTR_RAW_STS_SHIFT) /* 0x02000000 */ +#define VOP_INTR_STATUS_DSP_HOLD_VALID_INTR_RAW_STS_SHIFT (26U) +#define VOP_INTR_STATUS_DSP_HOLD_VALID_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_DSP_HOLD_VALID_INTR_RAW_STS_SHIFT) /* 0x04000000 */ +#define VOP_INTR_STATUS_DMA_FRM_FSH_INTR_RAW_STS_SHIFT (27U) +#define VOP_INTR_STATUS_DMA_FRM_FSH_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_DMA_FRM_FSH_INTR_RAW_STS_SHIFT) /* 0x08000000 */ +#define VOP_INTR_STATUS_POST_EMPTY_INTR_RAW_SHIFT (28U) +#define VOP_INTR_STATUS_POST_EMPTY_INTR_RAW_MASK (0x1U << VOP_INTR_STATUS_POST_EMPTY_INTR_RAW_SHIFT) /* 0x10000000 */ +#define VOP_INTR_STATUS_POST_LB_ALMOST_FULL_INTR_RAW_SHIFT (29U) +#define VOP_INTR_STATUS_POST_LB_ALMOST_FULL_INTR_RAW_MASK (0x1U << VOP_INTR_STATUS_POST_LB_ALMOST_FULL_INTR_RAW_SHIFT) /* 0x20000000 */ +#define VOP_INTR_STATUS_POST_LB_ALMOST_EMPTY_INTR_RAW_STS_SHIFT (30U) +#define VOP_INTR_STATUS_POST_LB_ALMOST_EMPTY_INTR_RAW_STS_MASK (0x1U << VOP_INTR_STATUS_POST_LB_ALMOST_EMPTY_INTR_RAW_STS_SHIFT) /* 0x40000000 */ +/* WIN0_CTRL0 */ +#define VOP_WIN0_CTRL0_OFFSET (0x40U) +#define VOP_WIN0_CTRL0_WIN0_EN_SHIFT (0U) +#define VOP_WIN0_CTRL0_WIN0_EN_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_EN_SHIFT) /* 0x00000001 */ +#define VOP_WIN0_CTRL0_WIN0_LUT_EN_SHIFT (1U) +#define VOP_WIN0_CTRL0_WIN0_LUT_EN_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_LUT_EN_SHIFT) /* 0x00000002 */ +#define VOP_WIN0_CTRL0_WIN0_DATA_FMT_SHIFT (4U) +#define VOP_WIN0_CTRL0_WIN0_DATA_FMT_MASK (0xFU << VOP_WIN0_CTRL0_WIN0_DATA_FMT_SHIFT) /* 0x000000F0 */ +#define VOP_WIN0_CTRL0_WIN0_BPP_SWAP_SHIFT (8U) +#define VOP_WIN0_CTRL0_WIN0_BPP_SWAP_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_BPP_SWAP_SHIFT) /* 0x00000100 */ +#define VOP_WIN0_CTRL0_WIN0_NO_OUTSTANDING_SHIFT (9U) +#define VOP_WIN0_CTRL0_WIN0_NO_OUTSTANDING_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_NO_OUTSTANDING_SHIFT) /* 0x00000200 */ +#define VOP_WIN0_CTRL0_WIN0_YUV_4BIT_EN_SHIFT (10U) +#define VOP_WIN0_CTRL0_WIN0_YUV_4BIT_EN_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_YUV_4BIT_EN_SHIFT) /* 0x00000400 */ +#define VOP_WIN0_CTRL0_WIN0_BPP_EN_SHIFT (11U) +#define VOP_WIN0_CTRL0_WIN0_BPP_EN_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_BPP_EN_SHIFT) /* 0x00000800 */ +#define VOP_WIN0_CTRL0_WIN0_RB_SWAP_SHIFT (12U) +#define VOP_WIN0_CTRL0_WIN0_RB_SWAP_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_RB_SWAP_SHIFT) /* 0x00001000 */ +#define VOP_WIN0_CTRL0_WIN0_ALPHA_SWAP_SHIFT (13U) +#define VOP_WIN0_CTRL0_WIN0_ALPHA_SWAP_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_ALPHA_SWAP_SHIFT) /* 0x00002000 */ +#define VOP_WIN0_CTRL0_WIN0_ENDIAN_SWAP_SHIFT (14U) +#define VOP_WIN0_CTRL0_WIN0_ENDIAN_SWAP_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_ENDIAN_SWAP_SHIFT) /* 0x00004000 */ +#define VOP_WIN0_CTRL0_WIN0_UV_SWAP_SHIFT (15U) +#define VOP_WIN0_CTRL0_WIN0_UV_SWAP_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_UV_SWAP_SHIFT) /* 0x00008000 */ +#define VOP_WIN0_CTRL0_WIN0_R2Y_EN_SHIFT (16U) +#define VOP_WIN0_CTRL0_WIN0_R2Y_EN_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_R2Y_EN_SHIFT) /* 0x00010000 */ +#define VOP_WIN0_CTRL0_WIN0_Y2R_EN_SHIFT (17U) +#define VOP_WIN0_CTRL0_WIN0_Y2R_EN_MASK (0x1U << VOP_WIN0_CTRL0_WIN0_Y2R_EN_SHIFT) /* 0x00020000 */ +#define VOP_WIN0_CTRL0_WIN0_CSC_MODE_SHIFT (18U) +#define VOP_WIN0_CTRL0_WIN0_CSC_MODE_MASK (0x3U << VOP_WIN0_CTRL0_WIN0_CSC_MODE_SHIFT) /* 0x000C0000 */ +/* WIN0_CTRL1 */ +#define VOP_WIN0_CTRL1_OFFSET (0x44U) +#define VOP_WIN0_CTRL1_WIN0_YRGB_GATHER_EN_SHIFT (0U) +#define VOP_WIN0_CTRL1_WIN0_YRGB_GATHER_EN_MASK (0x1U << VOP_WIN0_CTRL1_WIN0_YRGB_GATHER_EN_SHIFT) /* 0x00000001 */ +#define VOP_WIN0_CTRL1_WIN0_CBCR_GATHER_EN_SHIFT (1U) +#define VOP_WIN0_CTRL1_WIN0_CBCR_GATHER_EN_MASK (0x1U << VOP_WIN0_CTRL1_WIN0_CBCR_GATHER_EN_SHIFT) /* 0x00000002 */ +#define VOP_WIN0_CTRL1_WIN0_DMA_BURST_LENGTH_SHIFT (2U) +#define VOP_WIN0_CTRL1_WIN0_DMA_BURST_LENGTH_MASK (0x3U << VOP_WIN0_CTRL1_WIN0_DMA_BURST_LENGTH_SHIFT) /* 0x0000000C */ +#define VOP_WIN0_CTRL1_WIN0_YRGB_GATHER_NUM_SHIFT (4U) +#define VOP_WIN0_CTRL1_WIN0_YRGB_GATHER_NUM_MASK (0x3U << VOP_WIN0_CTRL1_WIN0_YRGB_GATHER_NUM_SHIFT) /* 0x00000030 */ +#define VOP_WIN0_CTRL1_WIN0_CBCR_GATHER_NUM_SHIFT (6U) +#define VOP_WIN0_CTRL1_WIN0_CBCR_GATHER_NUM_MASK (0x3U << VOP_WIN0_CTRL1_WIN0_CBCR_GATHER_NUM_SHIFT) /* 0x000000C0 */ +#define VOP_WIN0_CTRL1_SW_WIN0_YRGB_RID_SHIFT (8U) +#define VOP_WIN0_CTRL1_SW_WIN0_YRGB_RID_MASK (0xFU << VOP_WIN0_CTRL1_SW_WIN0_YRGB_RID_SHIFT) /* 0x00000F00 */ +#define VOP_WIN0_CTRL1_SW_WIN0_CBCR_RID_SHIFT (12U) +#define VOP_WIN0_CTRL1_SW_WIN0_CBCR_RID_MASK (0xFU << VOP_WIN0_CTRL1_SW_WIN0_CBCR_RID_SHIFT) /* 0x0000F000 */ +/* WIN0_VIR */ +#define VOP_WIN0_VIR_OFFSET (0x48U) +#define VOP_WIN0_VIR_WIN0_YRGB_VIR_STRIDE_SHIFT (0U) +#define VOP_WIN0_VIR_WIN0_YRGB_VIR_STRIDE_MASK (0xFFFFU << VOP_WIN0_VIR_WIN0_YRGB_VIR_STRIDE_SHIFT) /* 0x0000FFFF */ +#define VOP_WIN0_VIR_WIN0_CBCR_VIR_STRIDE_SHIFT (16U) +#define VOP_WIN0_VIR_WIN0_CBCR_VIR_STRIDE_MASK (0xFFFFU << VOP_WIN0_VIR_WIN0_CBCR_VIR_STRIDE_SHIFT) /* 0xFFFF0000 */ +/* WIN0_YRGB_MST */ +#define VOP_WIN0_YRGB_MST_OFFSET (0x50U) +#define VOP_WIN0_YRGB_MST_WIN0_YRGB_MST_SHIFT (0U) +#define VOP_WIN0_YRGB_MST_WIN0_YRGB_MST_MASK (0xFFFFFFFFU << VOP_WIN0_YRGB_MST_WIN0_YRGB_MST_SHIFT) /* 0xFFFFFFFF */ +/* WIN0_DSP_INFO */ +#define VOP_WIN0_DSP_INFO_OFFSET (0x54U) +#define VOP_WIN0_DSP_INFO_DSP_WIN0_WIDTH_SHIFT (0U) +#define VOP_WIN0_DSP_INFO_DSP_WIN0_WIDTH_MASK (0x1FFFU << VOP_WIN0_DSP_INFO_DSP_WIN0_WIDTH_SHIFT) /* 0x00001FFF */ +#define VOP_WIN0_DSP_INFO_DSP_WIN0_HEIGHT_SHIFT (16U) +#define VOP_WIN0_DSP_INFO_DSP_WIN0_HEIGHT_MASK (0x1FFFU << VOP_WIN0_DSP_INFO_DSP_WIN0_HEIGHT_SHIFT) /* 0x1FFF0000 */ +/* WIN0_DSP_ST */ +#define VOP_WIN0_DSP_ST_OFFSET (0x58U) +#define VOP_WIN0_DSP_ST_DSP_WIN0_XST_SHIFT (0U) +#define VOP_WIN0_DSP_ST_DSP_WIN0_XST_MASK (0x1FFFU << VOP_WIN0_DSP_ST_DSP_WIN0_XST_SHIFT) /* 0x00001FFF */ +#define VOP_WIN0_DSP_ST_DSP_WIN0_YST_SHIFT (16U) +#define VOP_WIN0_DSP_ST_DSP_WIN0_YST_MASK (0x1FFFU << VOP_WIN0_DSP_ST_DSP_WIN0_YST_SHIFT) /* 0x1FFF0000 */ +/* WIN0_COLOR_KEY */ +#define VOP_WIN0_COLOR_KEY_OFFSET (0x5CU) +#define VOP_WIN0_COLOR_KEY_WIN0_KEY_COLOR_SHIFT (0U) +#define VOP_WIN0_COLOR_KEY_WIN0_KEY_COLOR_MASK (0xFFFFFFU << VOP_WIN0_COLOR_KEY_WIN0_KEY_COLOR_SHIFT) /* 0x00FFFFFF */ +#define VOP_WIN0_COLOR_KEY_WIN0_KEY_EN_SHIFT (24U) +#define VOP_WIN0_COLOR_KEY_WIN0_KEY_EN_MASK (0x1U << VOP_WIN0_COLOR_KEY_WIN0_KEY_EN_SHIFT) /* 0x01000000 */ +/* WIN0_ALPHA_CTRL */ +#define VOP_WIN0_ALPHA_CTRL_OFFSET (0x6CU) +#define VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_EN_SHIFT (0U) +#define VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_EN_MASK (0x1U << VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_EN_SHIFT) /* 0x00000001 */ +#define VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_MODE_SHIFT (1U) +#define VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_MODE_MASK (0x1U << VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_MODE_SHIFT) /* 0x00000002 */ +#define VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_PRE_MUL_SHIFT (2U) +#define VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_PRE_MUL_MASK (0x1U << VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_PRE_MUL_SHIFT) /* 0x00000004 */ +#define VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_SAT_MODE_SHIFT (3U) +#define VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_SAT_MODE_MASK (0x1U << VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_SAT_MODE_SHIFT) /* 0x00000008 */ +#define VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_VALUE_SHIFT (4U) +#define VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_VALUE_MASK (0xFFU << VOP_WIN0_ALPHA_CTRL_WIN0_ALPHA_VALUE_SHIFT) /* 0x00000FF0 */ +/* WIN0_CBCR_MST */ +#define VOP_WIN0_CBCR_MST_OFFSET (0x70U) +#define VOP_WIN0_CBCR_MST_WIN0_CBCR_MST_SHIFT (0U) +#define VOP_WIN0_CBCR_MST_WIN0_CBCR_MST_MASK (0xFFFFFFFFU << VOP_WIN0_CBCR_MST_WIN0_CBCR_MST_SHIFT) /* 0xFFFFFFFF */ +/* WIN0_YRGB_MST_RAW */ +#define VOP_WIN0_YRGB_MST_RAW_OFFSET (0x74U) +#define VOP_WIN0_YRGB_MST_RAW_WIN0_YRGB_MST_RAW_SHIFT (0U) +#define VOP_WIN0_YRGB_MST_RAW_WIN0_YRGB_MST_RAW_MASK (0xFFFFFFFFU << VOP_WIN0_YRGB_MST_RAW_WIN0_YRGB_MST_RAW_SHIFT) /* 0xFFFFFFFF */ +/* WIN0_CBCR_MST_RAW */ +#define VOP_WIN0_CBCR_MST_RAW_OFFSET (0x78U) +#define VOP_WIN0_CBCR_MST_RAW_WIN0_CBCR_MST_RAW_SHIFT (0U) +#define VOP_WIN0_CBCR_MST_RAW_WIN0_CBCR_MST_RAW_MASK (0xFFFFFFFFU << VOP_WIN0_CBCR_MST_RAW_WIN0_CBCR_MST_RAW_SHIFT) /* 0xFFFFFFFF */ +/* WIN0_LOOP_OFFSET */ +#define VOP_WIN0_LOOP_OFFSET_OFFSET (0x7CU) +#define VOP_WIN0_LOOP_OFFSET_WIN0_XLOOP_OFFSET_SHIFT (0U) +#define VOP_WIN0_LOOP_OFFSET_WIN0_XLOOP_OFFSET_MASK (0x1FFFU << VOP_WIN0_LOOP_OFFSET_WIN0_XLOOP_OFFSET_SHIFT) /* 0x00001FFF */ +#define VOP_WIN0_LOOP_OFFSET_WIN0_XLOOP_EN_SHIFT (15U) +#define VOP_WIN0_LOOP_OFFSET_WIN0_XLOOP_EN_MASK (0x1U << VOP_WIN0_LOOP_OFFSET_WIN0_XLOOP_EN_SHIFT) /* 0x00008000 */ +#define VOP_WIN0_LOOP_OFFSET_WIN0_YLOOP_OFFSET_SHIFT (16U) +#define VOP_WIN0_LOOP_OFFSET_WIN0_YLOOP_OFFSET_MASK (0x1FFFU << VOP_WIN0_LOOP_OFFSET_WIN0_YLOOP_OFFSET_SHIFT) /* 0x1FFF0000 */ +#define VOP_WIN0_LOOP_OFFSET_WIN0_YLOOP_EN_SHIFT (31U) +#define VOP_WIN0_LOOP_OFFSET_WIN0_YLOOP_EN_MASK (0x1U << VOP_WIN0_LOOP_OFFSET_WIN0_YLOOP_EN_SHIFT) /* 0x80000000 */ +/* WIN1_CTRL0 */ +#define VOP_WIN1_CTRL0_OFFSET (0x80U) +#define VOP_WIN1_CTRL0_WIN1_EN_SHIFT (0U) +#define VOP_WIN1_CTRL0_WIN1_EN_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_EN_SHIFT) /* 0x00000001 */ +#define VOP_WIN1_CTRL0_WIN1_DATA_FMT_SHIFT (4U) +#define VOP_WIN1_CTRL0_WIN1_DATA_FMT_MASK (0xFU << VOP_WIN1_CTRL0_WIN1_DATA_FMT_SHIFT) /* 0x000000F0 */ +#define VOP_WIN1_CTRL0_WIN1_BPP_SWAP_SHIFT (8U) +#define VOP_WIN1_CTRL0_WIN1_BPP_SWAP_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_BPP_SWAP_SHIFT) /* 0x00000100 */ +#define VOP_WIN1_CTRL0_WIN1_NO_OUTSTANDING_SHIFT (9U) +#define VOP_WIN1_CTRL0_WIN1_NO_OUTSTANDING_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_NO_OUTSTANDING_SHIFT) /* 0x00000200 */ +#define VOP_WIN1_CTRL0_WIN1_YUV_4BIT_EN_SHIFT (10U) +#define VOP_WIN1_CTRL0_WIN1_YUV_4BIT_EN_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_YUV_4BIT_EN_SHIFT) /* 0x00000400 */ +#define VOP_WIN1_CTRL0_WIN1_BPP_EN_SHIFT (11U) +#define VOP_WIN1_CTRL0_WIN1_BPP_EN_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_BPP_EN_SHIFT) /* 0x00000800 */ +#define VOP_WIN1_CTRL0_WIN1_RB_SWAP_SHIFT (12U) +#define VOP_WIN1_CTRL0_WIN1_RB_SWAP_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_RB_SWAP_SHIFT) /* 0x00001000 */ +#define VOP_WIN1_CTRL0_WIN1_ALPHA_SWAP_SHIFT (13U) +#define VOP_WIN1_CTRL0_WIN1_ALPHA_SWAP_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_ALPHA_SWAP_SHIFT) /* 0x00002000 */ +#define VOP_WIN1_CTRL0_WIN1_ENDIAN_SWAP_SHIFT (14U) +#define VOP_WIN1_CTRL0_WIN1_ENDIAN_SWAP_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_ENDIAN_SWAP_SHIFT) /* 0x00004000 */ +#define VOP_WIN1_CTRL0_WIN1_UV_SWAP_SHIFT (15U) +#define VOP_WIN1_CTRL0_WIN1_UV_SWAP_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_UV_SWAP_SHIFT) /* 0x00008000 */ +#define VOP_WIN1_CTRL0_WIN1_R2Y_EN_SHIFT (16U) +#define VOP_WIN1_CTRL0_WIN1_R2Y_EN_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_R2Y_EN_SHIFT) /* 0x00010000 */ +#define VOP_WIN1_CTRL0_WIN1_Y2R_EN_SHIFT (17U) +#define VOP_WIN1_CTRL0_WIN1_Y2R_EN_MASK (0x1U << VOP_WIN1_CTRL0_WIN1_Y2R_EN_SHIFT) /* 0x00020000 */ +#define VOP_WIN1_CTRL0_WIN1_CSC_MODE_SHIFT (18U) +#define VOP_WIN1_CTRL0_WIN1_CSC_MODE_MASK (0x3U << VOP_WIN1_CTRL0_WIN1_CSC_MODE_SHIFT) /* 0x000C0000 */ +/* WIN1_CTRL1 */ +#define VOP_WIN1_CTRL1_OFFSET (0x84U) +#define VOP_WIN1_CTRL1_WIN1_YRGB_GATHER_EN_SHIFT (0U) +#define VOP_WIN1_CTRL1_WIN1_YRGB_GATHER_EN_MASK (0x1U << VOP_WIN1_CTRL1_WIN1_YRGB_GATHER_EN_SHIFT) /* 0x00000001 */ +#define VOP_WIN1_CTRL1_WIN1_CBCR_GATHER_EN_SHIFT (1U) +#define VOP_WIN1_CTRL1_WIN1_CBCR_GATHER_EN_MASK (0x1U << VOP_WIN1_CTRL1_WIN1_CBCR_GATHER_EN_SHIFT) /* 0x00000002 */ +#define VOP_WIN1_CTRL1_WIN1_DMA_BURST_LENGTH_SHIFT (2U) +#define VOP_WIN1_CTRL1_WIN1_DMA_BURST_LENGTH_MASK (0x3U << VOP_WIN1_CTRL1_WIN1_DMA_BURST_LENGTH_SHIFT) /* 0x0000000C */ +#define VOP_WIN1_CTRL1_WIN1_YRGB_GATHER_NUM_SHIFT (4U) +#define VOP_WIN1_CTRL1_WIN1_YRGB_GATHER_NUM_MASK (0x3U << VOP_WIN1_CTRL1_WIN1_YRGB_GATHER_NUM_SHIFT) /* 0x00000030 */ +#define VOP_WIN1_CTRL1_WIN1_CBCR_GATHER_NUM_SHIFT (6U) +#define VOP_WIN1_CTRL1_WIN1_CBCR_GATHER_NUM_MASK (0x3U << VOP_WIN1_CTRL1_WIN1_CBCR_GATHER_NUM_SHIFT) /* 0x000000C0 */ +#define VOP_WIN1_CTRL1_SW_WIN1_YRGB_RID_SHIFT (8U) +#define VOP_WIN1_CTRL1_SW_WIN1_YRGB_RID_MASK (0xFU << VOP_WIN1_CTRL1_SW_WIN1_YRGB_RID_SHIFT) /* 0x00000F00 */ +#define VOP_WIN1_CTRL1_SW_WIN1_CBCR_RID_SHIFT (12U) +#define VOP_WIN1_CTRL1_SW_WIN1_CBCR_RID_MASK (0xFU << VOP_WIN1_CTRL1_SW_WIN1_CBCR_RID_SHIFT) /* 0x0000F000 */ +/* WIN1_VIR */ +#define VOP_WIN1_VIR_OFFSET (0x88U) +#define VOP_WIN1_VIR_WIN1_YRGB_VIR_STRIDE_SHIFT (0U) +#define VOP_WIN1_VIR_WIN1_YRGB_VIR_STRIDE_MASK (0xFFFFU << VOP_WIN1_VIR_WIN1_YRGB_VIR_STRIDE_SHIFT) /* 0x0000FFFF */ +#define VOP_WIN1_VIR_WIN1_CBCR_VIR_STRIDE_SHIFT (16U) +#define VOP_WIN1_VIR_WIN1_CBCR_VIR_STRIDE_MASK (0xFFFFU << VOP_WIN1_VIR_WIN1_CBCR_VIR_STRIDE_SHIFT) /* 0xFFFF0000 */ +/* WIN1_YRGB_MST */ +#define VOP_WIN1_YRGB_MST_OFFSET (0x90U) +#define VOP_WIN1_YRGB_MST_WIN1_YRGB_MST_SHIFT (0U) +#define VOP_WIN1_YRGB_MST_WIN1_YRGB_MST_MASK (0xFFFFFFFFU << VOP_WIN1_YRGB_MST_WIN1_YRGB_MST_SHIFT) /* 0xFFFFFFFF */ +/* WIN1_DSP_INFO */ +#define VOP_WIN1_DSP_INFO_OFFSET (0x94U) +#define VOP_WIN1_DSP_INFO_DSP_WIN1_WIDTH_SHIFT (0U) +#define VOP_WIN1_DSP_INFO_DSP_WIN1_WIDTH_MASK (0x1FFFU << VOP_WIN1_DSP_INFO_DSP_WIN1_WIDTH_SHIFT) /* 0x00001FFF */ +#define VOP_WIN1_DSP_INFO_DSP_WIN1_HEIGHT_SHIFT (16U) +#define VOP_WIN1_DSP_INFO_DSP_WIN1_HEIGHT_MASK (0x1FFFU << VOP_WIN1_DSP_INFO_DSP_WIN1_HEIGHT_SHIFT) /* 0x1FFF0000 */ +/* WIN1_DSP_ST */ +#define VOP_WIN1_DSP_ST_OFFSET (0x98U) +#define VOP_WIN1_DSP_ST_DSP_WIN1_XST_SHIFT (0U) +#define VOP_WIN1_DSP_ST_DSP_WIN1_XST_MASK (0x1FFFU << VOP_WIN1_DSP_ST_DSP_WIN1_XST_SHIFT) /* 0x00001FFF */ +#define VOP_WIN1_DSP_ST_DSP_WIN1_YST_SHIFT (16U) +#define VOP_WIN1_DSP_ST_DSP_WIN1_YST_MASK (0x1FFFU << VOP_WIN1_DSP_ST_DSP_WIN1_YST_SHIFT) /* 0x1FFF0000 */ +/* WIN1_COLOR_KEY */ +#define VOP_WIN1_COLOR_KEY_OFFSET (0x9CU) +#define VOP_WIN1_COLOR_KEY_WIN1_KEY_COLOR_SHIFT (0U) +#define VOP_WIN1_COLOR_KEY_WIN1_KEY_COLOR_MASK (0xFFFFFFU << VOP_WIN1_COLOR_KEY_WIN1_KEY_COLOR_SHIFT) /* 0x00FFFFFF */ +#define VOP_WIN1_COLOR_KEY_WIN1_KEY_EN_SHIFT (24U) +#define VOP_WIN1_COLOR_KEY_WIN1_KEY_EN_MASK (0x1U << VOP_WIN1_COLOR_KEY_WIN1_KEY_EN_SHIFT) /* 0x01000000 */ +/* WIN1_ALPHA_CTRL */ +#define VOP_WIN1_ALPHA_CTRL_OFFSET (0xACU) +#define VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_EN_SHIFT (0U) +#define VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_EN_MASK (0x1U << VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_EN_SHIFT) /* 0x00000001 */ +#define VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_MODE_SHIFT (1U) +#define VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_MODE_MASK (0x1U << VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_MODE_SHIFT) /* 0x00000002 */ +#define VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_PRE_MUL_SHIFT (2U) +#define VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_PRE_MUL_MASK (0x1U << VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_PRE_MUL_SHIFT) /* 0x00000004 */ +#define VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_SAT_MODE_SHIFT (3U) +#define VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_SAT_MODE_MASK (0x1U << VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_SAT_MODE_SHIFT) /* 0x00000008 */ +#define VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_VALUE_SHIFT (4U) +#define VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_VALUE_MASK (0xFFU << VOP_WIN1_ALPHA_CTRL_WIN1_ALPHA_VALUE_SHIFT) /* 0x00000FF0 */ +/* WIN1_CBCR_MST */ +#define VOP_WIN1_CBCR_MST_OFFSET (0xB0U) +#define VOP_WIN1_CBCR_MST_WIN1_CBCR_MST_SHIFT (0U) +#define VOP_WIN1_CBCR_MST_WIN1_CBCR_MST_MASK (0xFFFFFFFFU << VOP_WIN1_CBCR_MST_WIN1_CBCR_MST_SHIFT) /* 0xFFFFFFFF */ +/* WIN1_YRGB_MST_RAW */ +#define VOP_WIN1_YRGB_MST_RAW_OFFSET (0xB4U) +#define VOP_WIN1_YRGB_MST_RAW_WIN1_YRGB_MST_RAW_SHIFT (0U) +#define VOP_WIN1_YRGB_MST_RAW_WIN1_YRGB_MST_RAW_MASK (0xFFFFFFFFU << VOP_WIN1_YRGB_MST_RAW_WIN1_YRGB_MST_RAW_SHIFT) /* 0xFFFFFFFF */ +/* WIN1_CBCR_MST_RAW */ +#define VOP_WIN1_CBCR_MST_RAW_OFFSET (0xB8U) +#define VOP_WIN1_CBCR_MST_RAW_WIN1_CBCR_MST_RAW_SHIFT (0U) +#define VOP_WIN1_CBCR_MST_RAW_WIN1_CBCR_MST_RAW_MASK (0xFFFFFFFFU << VOP_WIN1_CBCR_MST_RAW_WIN1_CBCR_MST_RAW_SHIFT) /* 0xFFFFFFFF */ +/* WIN1_LOOP_OFFSET */ +#define VOP_WIN1_LOOP_OFFSET_OFFSET (0xBCU) +#define VOP_WIN1_LOOP_OFFSET_WIN1_XLOOP_OFFSET_SHIFT (0U) +#define VOP_WIN1_LOOP_OFFSET_WIN1_XLOOP_OFFSET_MASK (0x1FFFU << VOP_WIN1_LOOP_OFFSET_WIN1_XLOOP_OFFSET_SHIFT) /* 0x00001FFF */ +#define VOP_WIN1_LOOP_OFFSET_WIN1_XLOOP_EN_SHIFT (15U) +#define VOP_WIN1_LOOP_OFFSET_WIN1_XLOOP_EN_MASK (0x1U << VOP_WIN1_LOOP_OFFSET_WIN1_XLOOP_EN_SHIFT) /* 0x00008000 */ +#define VOP_WIN1_LOOP_OFFSET_WIN1_YLOOP_OFFSET_SHIFT (16U) +#define VOP_WIN1_LOOP_OFFSET_WIN1_YLOOP_OFFSET_MASK (0x1FFFU << VOP_WIN1_LOOP_OFFSET_WIN1_YLOOP_OFFSET_SHIFT) /* 0x1FFF0000 */ +#define VOP_WIN1_LOOP_OFFSET_WIN1_YLOOP_EN_SHIFT (31U) +#define VOP_WIN1_LOOP_OFFSET_WIN1_YLOOP_EN_MASK (0x1U << VOP_WIN1_LOOP_OFFSET_WIN1_YLOOP_EN_SHIFT) /* 0x80000000 */ +/* WIN2_CTRL0 */ +#define VOP_WIN2_CTRL0_OFFSET (0xC0U) +#define VOP_WIN2_CTRL0_WIN2_EN_SHIFT (0U) +#define VOP_WIN2_CTRL0_WIN2_EN_MASK (0x1U << VOP_WIN2_CTRL0_WIN2_EN_SHIFT) /* 0x00000001 */ +#define VOP_WIN2_CTRL0_WIN2_DATA_FMT_SHIFT (4U) +#define VOP_WIN2_CTRL0_WIN2_DATA_FMT_MASK (0xFU << VOP_WIN2_CTRL0_WIN2_DATA_FMT_SHIFT) /* 0x000000F0 */ +#define VOP_WIN2_CTRL0_WIN2_BPP_SWAP_SHIFT (8U) +#define VOP_WIN2_CTRL0_WIN2_BPP_SWAP_MASK (0x1U << VOP_WIN2_CTRL0_WIN2_BPP_SWAP_SHIFT) /* 0x00000100 */ +#define VOP_WIN2_CTRL0_WIN2_NO_OUTSTANDING_SHIFT (9U) +#define VOP_WIN2_CTRL0_WIN2_NO_OUTSTANDING_MASK (0x1U << VOP_WIN2_CTRL0_WIN2_NO_OUTSTANDING_SHIFT) /* 0x00000200 */ +#define VOP_WIN2_CTRL0_WIN2_YUV_4BIT_EN_SHIFT (10U) +#define VOP_WIN2_CTRL0_WIN2_YUV_4BIT_EN_MASK (0x1U << VOP_WIN2_CTRL0_WIN2_YUV_4BIT_EN_SHIFT) /* 0x00000400 */ +#define VOP_WIN2_CTRL0_WIN2_RB_SWAP_SHIFT (12U) +#define VOP_WIN2_CTRL0_WIN2_RB_SWAP_MASK (0x1U << VOP_WIN2_CTRL0_WIN2_RB_SWAP_SHIFT) /* 0x00001000 */ +#define VOP_WIN2_CTRL0_WIN2_ALPHA_SWAP_SHIFT (13U) +#define VOP_WIN2_CTRL0_WIN2_ALPHA_SWAP_MASK (0x1U << VOP_WIN2_CTRL0_WIN2_ALPHA_SWAP_SHIFT) /* 0x00002000 */ +#define VOP_WIN2_CTRL0_WIN2_ENDIAN_SWAP_SHIFT (14U) +#define VOP_WIN2_CTRL0_WIN2_ENDIAN_SWAP_MASK (0x1U << VOP_WIN2_CTRL0_WIN2_ENDIAN_SWAP_SHIFT) /* 0x00004000 */ +#define VOP_WIN2_CTRL0_WIN2_UV_SWAP_SHIFT (15U) +#define VOP_WIN2_CTRL0_WIN2_UV_SWAP_MASK (0x1U << VOP_WIN2_CTRL0_WIN2_UV_SWAP_SHIFT) /* 0x00008000 */ +#define VOP_WIN2_CTRL0_WIN2_R2Y_EN_SHIFT (16U) +#define VOP_WIN2_CTRL0_WIN2_R2Y_EN_MASK (0x1U << VOP_WIN2_CTRL0_WIN2_R2Y_EN_SHIFT) /* 0x00010000 */ +#define VOP_WIN2_CTRL0_WIN2_Y2R_EN_SHIFT (17U) +#define VOP_WIN2_CTRL0_WIN2_Y2R_EN_MASK (0x1U << VOP_WIN2_CTRL0_WIN2_Y2R_EN_SHIFT) /* 0x00020000 */ +#define VOP_WIN2_CTRL0_WIN2_CSC_MODE_SHIFT (18U) +#define VOP_WIN2_CTRL0_WIN2_CSC_MODE_MASK (0x3U << VOP_WIN2_CTRL0_WIN2_CSC_MODE_SHIFT) /* 0x000C0000 */ +/* WIN2_CTRL1 */ +#define VOP_WIN2_CTRL1_OFFSET (0xC4U) +#define VOP_WIN2_CTRL1_WIN2_YRGB_GATHER_EN_SHIFT (0U) +#define VOP_WIN2_CTRL1_WIN2_YRGB_GATHER_EN_MASK (0x1U << VOP_WIN2_CTRL1_WIN2_YRGB_GATHER_EN_SHIFT) /* 0x00000001 */ +#define VOP_WIN2_CTRL1_WIN2_CBCR_GATHER_EN_SHIFT (1U) +#define VOP_WIN2_CTRL1_WIN2_CBCR_GATHER_EN_MASK (0x1U << VOP_WIN2_CTRL1_WIN2_CBCR_GATHER_EN_SHIFT) /* 0x00000002 */ +#define VOP_WIN2_CTRL1_WIN2_DMA_BURST_LENGTH_SHIFT (2U) +#define VOP_WIN2_CTRL1_WIN2_DMA_BURST_LENGTH_MASK (0x3U << VOP_WIN2_CTRL1_WIN2_DMA_BURST_LENGTH_SHIFT) /* 0x0000000C */ +#define VOP_WIN2_CTRL1_WIN2_YRGB_GATHER_NUM_SHIFT (4U) +#define VOP_WIN2_CTRL1_WIN2_YRGB_GATHER_NUM_MASK (0x3U << VOP_WIN2_CTRL1_WIN2_YRGB_GATHER_NUM_SHIFT) /* 0x00000030 */ +#define VOP_WIN2_CTRL1_WIN2_CBCR_GATHER_NUM_SHIFT (6U) +#define VOP_WIN2_CTRL1_WIN2_CBCR_GATHER_NUM_MASK (0x3U << VOP_WIN2_CTRL1_WIN2_CBCR_GATHER_NUM_SHIFT) /* 0x000000C0 */ +#define VOP_WIN2_CTRL1_SW_WIN2_YRGB_RID_SHIFT (8U) +#define VOP_WIN2_CTRL1_SW_WIN2_YRGB_RID_MASK (0xFU << VOP_WIN2_CTRL1_SW_WIN2_YRGB_RID_SHIFT) /* 0x00000F00 */ +#define VOP_WIN2_CTRL1_SW_WIN2_CBCR_RID_SHIFT (12U) +#define VOP_WIN2_CTRL1_SW_WIN2_CBCR_RID_MASK (0xFU << VOP_WIN2_CTRL1_SW_WIN2_CBCR_RID_SHIFT) /* 0x0000F000 */ +/* WIN2_VIR */ +#define VOP_WIN2_VIR_OFFSET (0xC8U) +#define VOP_WIN2_VIR_WIN2_YRGB_VIR_STRIDE_SHIFT (0U) +#define VOP_WIN2_VIR_WIN2_YRGB_VIR_STRIDE_MASK (0xFFFFU << VOP_WIN2_VIR_WIN2_YRGB_VIR_STRIDE_SHIFT) /* 0x0000FFFF */ +#define VOP_WIN2_VIR_WIN2_CBCR_VIR_STRIDE_SHIFT (16U) +#define VOP_WIN2_VIR_WIN2_CBCR_VIR_STRIDE_MASK (0xFFFFU << VOP_WIN2_VIR_WIN2_CBCR_VIR_STRIDE_SHIFT) /* 0xFFFF0000 */ +/* WIN2_YRGB_MST */ +#define VOP_WIN2_YRGB_MST_OFFSET (0xD0U) +#define VOP_WIN2_YRGB_MST_WIN2_YRGB_MST_SHIFT (0U) +#define VOP_WIN2_YRGB_MST_WIN2_YRGB_MST_MASK (0xFFFFFFFFU << VOP_WIN2_YRGB_MST_WIN2_YRGB_MST_SHIFT) /* 0xFFFFFFFF */ +/* WIN2_DSP_INFO */ +#define VOP_WIN2_DSP_INFO_OFFSET (0xD4U) +#define VOP_WIN2_DSP_INFO_DSP_WIN2_WIDTH_SHIFT (0U) +#define VOP_WIN2_DSP_INFO_DSP_WIN2_WIDTH_MASK (0x1FFFU << VOP_WIN2_DSP_INFO_DSP_WIN2_WIDTH_SHIFT) /* 0x00001FFF */ +#define VOP_WIN2_DSP_INFO_DSP_WIN2_HEIGHT_SHIFT (16U) +#define VOP_WIN2_DSP_INFO_DSP_WIN2_HEIGHT_MASK (0x1FFFU << VOP_WIN2_DSP_INFO_DSP_WIN2_HEIGHT_SHIFT) /* 0x1FFF0000 */ +/* WIN2_DSP_ST */ +#define VOP_WIN2_DSP_ST_OFFSET (0xD8U) +#define VOP_WIN2_DSP_ST_DSP_WIN2_XST_SHIFT (0U) +#define VOP_WIN2_DSP_ST_DSP_WIN2_XST_MASK (0x1FFFU << VOP_WIN2_DSP_ST_DSP_WIN2_XST_SHIFT) /* 0x00001FFF */ +#define VOP_WIN2_DSP_ST_DSP_WIN2_YST_SHIFT (16U) +#define VOP_WIN2_DSP_ST_DSP_WIN2_YST_MASK (0x1FFFU << VOP_WIN2_DSP_ST_DSP_WIN2_YST_SHIFT) /* 0x1FFF0000 */ +/* WIN2_COLOR_KEY */ +#define VOP_WIN2_COLOR_KEY_OFFSET (0xDCU) +#define VOP_WIN2_COLOR_KEY_WIN2_KEY_COLOR_SHIFT (0U) +#define VOP_WIN2_COLOR_KEY_WIN2_KEY_COLOR_MASK (0xFFFFFFU << VOP_WIN2_COLOR_KEY_WIN2_KEY_COLOR_SHIFT) /* 0x00FFFFFF */ +#define VOP_WIN2_COLOR_KEY_WIN2_KEY_EN_SHIFT (24U) +#define VOP_WIN2_COLOR_KEY_WIN2_KEY_EN_MASK (0x1U << VOP_WIN2_COLOR_KEY_WIN2_KEY_EN_SHIFT) /* 0x01000000 */ +/* WIN2_ALPHA_CTRL */ +#define VOP_WIN2_ALPHA_CTRL_OFFSET (0xECU) +#define VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_EN_SHIFT (0U) +#define VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_EN_MASK (0x1U << VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_EN_SHIFT) /* 0x00000001 */ +#define VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_MODE_SHIFT (1U) +#define VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_MODE_MASK (0x1U << VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_MODE_SHIFT) /* 0x00000002 */ +#define VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_PRE_MUL_SHIFT (2U) +#define VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_PRE_MUL_MASK (0x1U << VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_PRE_MUL_SHIFT) /* 0x00000004 */ +#define VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_SAT_MODE_SHIFT (3U) +#define VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_SAT_MODE_MASK (0x1U << VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_SAT_MODE_SHIFT) /* 0x00000008 */ +#define VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_VALUE_SHIFT (4U) +#define VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_VALUE_MASK (0xFFU << VOP_WIN2_ALPHA_CTRL_WIN2_ALPHA_VALUE_SHIFT) /* 0x00000FF0 */ +/* WIN2_CBCR_MST */ +#define VOP_WIN2_CBCR_MST_OFFSET (0xF0U) +#define VOP_WIN2_CBCR_MST_WIN2_CBCR_MST_SHIFT (0U) +#define VOP_WIN2_CBCR_MST_WIN2_CBCR_MST_MASK (0xFFFFFFFFU << VOP_WIN2_CBCR_MST_WIN2_CBCR_MST_SHIFT) /* 0xFFFFFFFF */ +/* WIN2_YRGB_MST_RAW */ +#define VOP_WIN2_YRGB_MST_RAW_OFFSET (0xF4U) +#define VOP_WIN2_YRGB_MST_RAW_WIN2_YRGB_MST_RAW_SHIFT (0U) +#define VOP_WIN2_YRGB_MST_RAW_WIN2_YRGB_MST_RAW_MASK (0xFFFFFFFFU << VOP_WIN2_YRGB_MST_RAW_WIN2_YRGB_MST_RAW_SHIFT) /* 0xFFFFFFFF */ +/* WIN2_CBCR_MST_RAW */ +#define VOP_WIN2_CBCR_MST_RAW_OFFSET (0xF8U) +#define VOP_WIN2_CBCR_MST_RAW_WIN2_CBCR_MST_RAW_SHIFT (0U) +#define VOP_WIN2_CBCR_MST_RAW_WIN2_CBCR_MST_RAW_MASK (0xFFFFFFFFU << VOP_WIN2_CBCR_MST_RAW_WIN2_CBCR_MST_RAW_SHIFT) /* 0xFFFFFFFF */ +/* WIN2_LOOP_OFFSET */ +#define VOP_WIN2_LOOP_OFFSET_OFFSET (0xFCU) +#define VOP_WIN2_LOOP_OFFSET_WIN2_XLOOP_OFFSET_SHIFT (0U) +#define VOP_WIN2_LOOP_OFFSET_WIN2_XLOOP_OFFSET_MASK (0x1FFFU << VOP_WIN2_LOOP_OFFSET_WIN2_XLOOP_OFFSET_SHIFT) /* 0x00001FFF */ +#define VOP_WIN2_LOOP_OFFSET_WIN2_XLOOP_EN_SHIFT (15U) +#define VOP_WIN2_LOOP_OFFSET_WIN2_XLOOP_EN_MASK (0x1U << VOP_WIN2_LOOP_OFFSET_WIN2_XLOOP_EN_SHIFT) /* 0x00008000 */ +#define VOP_WIN2_LOOP_OFFSET_WIN2_YLOOP_OFFSET_SHIFT (16U) +#define VOP_WIN2_LOOP_OFFSET_WIN2_YLOOP_OFFSET_MASK (0x1FFFU << VOP_WIN2_LOOP_OFFSET_WIN2_YLOOP_OFFSET_SHIFT) /* 0x1FFF0000 */ +#define VOP_WIN2_LOOP_OFFSET_WIN2_YLOOP_EN_SHIFT (31U) +#define VOP_WIN2_LOOP_OFFSET_WIN2_YLOOP_EN_MASK (0x1U << VOP_WIN2_LOOP_OFFSET_WIN2_YLOOP_EN_SHIFT) /* 0x80000000 */ +/* DSP_HTOTAL_HS_END */ +#define VOP_DSP_HTOTAL_HS_END_OFFSET (0x100U) +#define VOP_DSP_HTOTAL_HS_END_DSP_HS_END_SHIFT (0U) +#define VOP_DSP_HTOTAL_HS_END_DSP_HS_END_MASK (0xFFFU << VOP_DSP_HTOTAL_HS_END_DSP_HS_END_SHIFT) /* 0x00000FFF */ +#define VOP_DSP_HTOTAL_HS_END_DSP_HTOTAL_SHIFT (16U) +#define VOP_DSP_HTOTAL_HS_END_DSP_HTOTAL_MASK (0xFFFU << VOP_DSP_HTOTAL_HS_END_DSP_HTOTAL_SHIFT) /* 0x0FFF0000 */ +/* DSP_HACT_ST_END */ +#define VOP_DSP_HACT_ST_END_OFFSET (0x104U) +#define VOP_DSP_HACT_ST_END_DSP_HACT_END_SHIFT (0U) +#define VOP_DSP_HACT_ST_END_DSP_HACT_END_MASK (0xFFFU << VOP_DSP_HACT_ST_END_DSP_HACT_END_SHIFT) /* 0x00000FFF */ +#define VOP_DSP_HACT_ST_END_DSP_HACT_ST_SHIFT (16U) +#define VOP_DSP_HACT_ST_END_DSP_HACT_ST_MASK (0xFFFU << VOP_DSP_HACT_ST_END_DSP_HACT_ST_SHIFT) /* 0x0FFF0000 */ +/* DSP_VTOTAL_VS_END */ +#define VOP_DSP_VTOTAL_VS_END_OFFSET (0x108U) +#define VOP_DSP_VTOTAL_VS_END_DSP_VS_END_SHIFT (0U) +#define VOP_DSP_VTOTAL_VS_END_DSP_VS_END_MASK (0xFFFU << VOP_DSP_VTOTAL_VS_END_DSP_VS_END_SHIFT) /* 0x00000FFF */ +#define VOP_DSP_VTOTAL_VS_END_DSP_VTOTAL_SHIFT (16U) +#define VOP_DSP_VTOTAL_VS_END_DSP_VTOTAL_MASK (0xFFFU << VOP_DSP_VTOTAL_VS_END_DSP_VTOTAL_SHIFT) /* 0x0FFF0000 */ +/* DSP_VACT_ST_END */ +#define VOP_DSP_VACT_ST_END_OFFSET (0x10CU) +#define VOP_DSP_VACT_ST_END_DSP_VACT_END_SHIFT (0U) +#define VOP_DSP_VACT_ST_END_DSP_VACT_END_MASK (0xFFFU << VOP_DSP_VACT_ST_END_DSP_VACT_END_SHIFT) /* 0x00000FFF */ +#define VOP_DSP_VACT_ST_END_DSP_VACT_ST_SHIFT (16U) +#define VOP_DSP_VACT_ST_END_DSP_VACT_ST_MASK (0xFFFU << VOP_DSP_VACT_ST_END_DSP_VACT_ST_SHIFT) /* 0x0FFF0000 */ +/* DSP_VS_ST_END_F1 */ +#define VOP_DSP_VS_ST_END_F1_OFFSET (0x110U) +#define VOP_DSP_VS_ST_END_F1_DSP_VS_END_F1_SHIFT (0U) +#define VOP_DSP_VS_ST_END_F1_DSP_VS_END_F1_MASK (0xFFFU << VOP_DSP_VS_ST_END_F1_DSP_VS_END_F1_SHIFT) /* 0x00000FFF */ +#define VOP_DSP_VS_ST_END_F1_DSP_VS_ST_F1_SHIFT (16U) +#define VOP_DSP_VS_ST_END_F1_DSP_VS_ST_F1_MASK (0xFFFU << VOP_DSP_VS_ST_END_F1_DSP_VS_ST_F1_SHIFT) /* 0x0FFF0000 */ +/* DSP_VACT_ST_END_F1 */ +#define VOP_DSP_VACT_ST_END_F1_OFFSET (0x114U) +#define VOP_DSP_VACT_ST_END_F1_DSP_VACT_END_F1_SHIFT (0U) +#define VOP_DSP_VACT_ST_END_F1_DSP_VACT_END_F1_MASK (0xFFFU << VOP_DSP_VACT_ST_END_F1_DSP_VACT_END_F1_SHIFT) /* 0x00000FFF */ +#define VOP_DSP_VACT_ST_END_F1_DSP_VACT_ST_F1_SHIFT (16U) +#define VOP_DSP_VACT_ST_END_F1_DSP_VACT_ST_F1_MASK (0xFFFU << VOP_DSP_VACT_ST_END_F1_DSP_VACT_ST_F1_SHIFT) /* 0x0FFF0000 */ +/* PRE_HTOTAL_HS_END */ +#define VOP_PRE_HTOTAL_HS_END_OFFSET (0x118U) +#define VOP_PRE_HTOTAL_HS_END_DSP_HS_END_SHIFT (0U) +#define VOP_PRE_HTOTAL_HS_END_DSP_HS_END_MASK (0xFFFU << VOP_PRE_HTOTAL_HS_END_DSP_HS_END_SHIFT) /* 0x00000FFF */ +#define VOP_PRE_HTOTAL_HS_END_DSP_HTOTAL_SHIFT (16U) +#define VOP_PRE_HTOTAL_HS_END_DSP_HTOTAL_MASK (0xFFFU << VOP_PRE_HTOTAL_HS_END_DSP_HTOTAL_SHIFT) /* 0x0FFF0000 */ +/* PRE_HACT_ST_END */ +#define VOP_PRE_HACT_ST_END_OFFSET (0x11CU) +#define VOP_PRE_HACT_ST_END_DSP_HACT_END_SHIFT (0U) +#define VOP_PRE_HACT_ST_END_DSP_HACT_END_MASK (0xFFFU << VOP_PRE_HACT_ST_END_DSP_HACT_END_SHIFT) /* 0x00000FFF */ +#define VOP_PRE_HACT_ST_END_DSP_HACT_ST_SHIFT (16U) +#define VOP_PRE_HACT_ST_END_DSP_HACT_ST_MASK (0xFFFU << VOP_PRE_HACT_ST_END_DSP_HACT_ST_SHIFT) /* 0x0FFF0000 */ +/* PRE_VTOTAL_VS_END */ +#define VOP_PRE_VTOTAL_VS_END_OFFSET (0x120U) +#define VOP_PRE_VTOTAL_VS_END_DSP_VS_END_SHIFT (0U) +#define VOP_PRE_VTOTAL_VS_END_DSP_VS_END_MASK (0xFFFU << VOP_PRE_VTOTAL_VS_END_DSP_VS_END_SHIFT) /* 0x00000FFF */ +#define VOP_PRE_VTOTAL_VS_END_DSP_VTOTAL_SHIFT (16U) +#define VOP_PRE_VTOTAL_VS_END_DSP_VTOTAL_MASK (0xFFFU << VOP_PRE_VTOTAL_VS_END_DSP_VTOTAL_SHIFT) /* 0x0FFF0000 */ +/* PRE_VACT_ST_END */ +#define VOP_PRE_VACT_ST_END_OFFSET (0x124U) +#define VOP_PRE_VACT_ST_END_DSP_VACT_END_SHIFT (0U) +#define VOP_PRE_VACT_ST_END_DSP_VACT_END_MASK (0xFFFU << VOP_PRE_VACT_ST_END_DSP_VACT_END_SHIFT) /* 0x00000FFF */ +#define VOP_PRE_VACT_ST_END_DSP_VACT_ST_SHIFT (16U) +#define VOP_PRE_VACT_ST_END_DSP_VACT_ST_MASK (0xFFFU << VOP_PRE_VACT_ST_END_DSP_VACT_ST_SHIFT) /* 0x0FFF0000 */ +/* BCSH_CTRL */ +#define VOP_BCSH_CTRL_OFFSET (0x160U) +#define VOP_BCSH_CTRL_BCSH_EN_SHIFT (0U) +#define VOP_BCSH_CTRL_BCSH_EN_MASK (0x1U << VOP_BCSH_CTRL_BCSH_EN_SHIFT) /* 0x00000001 */ +#define VOP_BCSH_CTRL_SW_BCSH_R2Y_CSC_MODE_SHIFT (1U) +#define VOP_BCSH_CTRL_SW_BCSH_R2Y_CSC_MODE_MASK (0x1U << VOP_BCSH_CTRL_SW_BCSH_R2Y_CSC_MODE_SHIFT) /* 0x00000002 */ +#define VOP_BCSH_CTRL_VIDEO_MODE_SHIFT (2U) +#define VOP_BCSH_CTRL_VIDEO_MODE_MASK (0x3U << VOP_BCSH_CTRL_VIDEO_MODE_SHIFT) /* 0x0000000C */ +#define VOP_BCSH_CTRL_SW_BCSH_Y2R_CSC_MODE_SHIFT (4U) +#define VOP_BCSH_CTRL_SW_BCSH_Y2R_CSC_MODE_MASK (0x3U << VOP_BCSH_CTRL_SW_BCSH_Y2R_CSC_MODE_SHIFT) /* 0x00000030 */ +#define VOP_BCSH_CTRL_SW_BCSH_Y2R_EN_SHIFT (6U) +#define VOP_BCSH_CTRL_SW_BCSH_Y2R_EN_MASK (0x1U << VOP_BCSH_CTRL_SW_BCSH_Y2R_EN_SHIFT) /* 0x00000040 */ +#define VOP_BCSH_CTRL_SW_BCSH_R2Y_EN_SHIFT (7U) +#define VOP_BCSH_CTRL_SW_BCSH_R2Y_EN_MASK (0x1U << VOP_BCSH_CTRL_SW_BCSH_R2Y_EN_SHIFT) /* 0x00000080 */ +/* BCSH_COL_BAR */ +#define VOP_BCSH_COL_BAR_OFFSET (0x164U) +#define VOP_BCSH_COL_BAR_COLOR_BAR_Y_SHIFT (0U) +#define VOP_BCSH_COL_BAR_COLOR_BAR_Y_MASK (0xFFU << VOP_BCSH_COL_BAR_COLOR_BAR_Y_SHIFT) /* 0x000000FF */ +#define VOP_BCSH_COL_BAR_COLOR_BAR_U_SHIFT (8U) +#define VOP_BCSH_COL_BAR_COLOR_BAR_U_MASK (0xFFU << VOP_BCSH_COL_BAR_COLOR_BAR_U_SHIFT) /* 0x0000FF00 */ +#define VOP_BCSH_COL_BAR_COLOR_BAR_V_SHIFT (16U) +#define VOP_BCSH_COL_BAR_COLOR_BAR_V_MASK (0xFFU << VOP_BCSH_COL_BAR_COLOR_BAR_V_SHIFT) /* 0x00FF0000 */ +/* BCSH_BCS */ +#define VOP_BCSH_BCS_OFFSET (0x168U) +#define VOP_BCSH_BCS_BRIGHTNESS_SHIFT (0U) +#define VOP_BCSH_BCS_BRIGHTNESS_MASK (0x7FU << VOP_BCSH_BCS_BRIGHTNESS_SHIFT) /* 0x0000007F */ +#define VOP_BCSH_BCS_CONTRAST_SHIFT (8U) +#define VOP_BCSH_BCS_CONTRAST_MASK (0x1FFU << VOP_BCSH_BCS_CONTRAST_SHIFT) /* 0x0001FF00 */ +#define VOP_BCSH_BCS_SAT_CON_SHIFT (20U) +#define VOP_BCSH_BCS_SAT_CON_MASK (0x3FFU << VOP_BCSH_BCS_SAT_CON_SHIFT) /* 0x3FF00000 */ +/* BCSH_H */ +#define VOP_BCSH_H_OFFSET (0x16CU) +#define VOP_BCSH_H_SIN_HUE_SHIFT (0U) +#define VOP_BCSH_H_SIN_HUE_MASK (0x1FFU << VOP_BCSH_H_SIN_HUE_SHIFT) /* 0x000001FF */ +#define VOP_BCSH_H_COS_HUE_SHIFT (16U) +#define VOP_BCSH_H_COS_HUE_MASK (0x1FFU << VOP_BCSH_H_COS_HUE_SHIFT) /* 0x01FF0000 */ +/* GAMMA_COE_WORD0 */ +#define VOP_GAMMA_COE_WORD0_OFFSET (0x170U) +#define VOP_GAMMA_COE_WORD0_GAMMA_COE_WORD0_SHIFT (0U) +#define VOP_GAMMA_COE_WORD0_GAMMA_COE_WORD0_MASK (0xFFFFFFFFU << VOP_GAMMA_COE_WORD0_GAMMA_COE_WORD0_SHIFT) /* 0xFFFFFFFF */ +/* GAMMA_COE_WORD1 */ +#define VOP_GAMMA_COE_WORD1_OFFSET (0x174U) +#define VOP_GAMMA_COE_WORD1_GAMMA_COE_WORD1_SHIFT (0U) +#define VOP_GAMMA_COE_WORD1_GAMMA_COE_WORD1_MASK (0xFFFFFFFFU << VOP_GAMMA_COE_WORD1_GAMMA_COE_WORD1_SHIFT) /* 0xFFFFFFFF */ +/* GAMMA_COE_WORD2 */ +#define VOP_GAMMA_COE_WORD2_OFFSET (0x178U) +#define VOP_GAMMA_COE_WORD2_GAMMA_COE_WORD2_SHIFT (0U) +#define VOP_GAMMA_COE_WORD2_GAMMA_COE_WORD2_MASK (0xFFFFFFFFU << VOP_GAMMA_COE_WORD2_GAMMA_COE_WORD2_SHIFT) /* 0xFFFFFFFF */ +/* GAMMA_COE_WORD3 */ +#define VOP_GAMMA_COE_WORD3_OFFSET (0x17CU) +#define VOP_GAMMA_COE_WORD3_GAMMA_COE_WORD3_SHIFT (0U) +#define VOP_GAMMA_COE_WORD3_GAMMA_COE_WORD3_MASK (0xFFFFFFFFU << VOP_GAMMA_COE_WORD3_GAMMA_COE_WORD3_SHIFT) /* 0xFFFFFFFF */ +/* POST_CTRL */ +#define VOP_POST_CTRL_OFFSET (0x180U) +#define VOP_POST_CTRL_Y_GAMMA_EN_SHIFT (0U) +#define VOP_POST_CTRL_Y_GAMMA_EN_MASK (0x1U << VOP_POST_CTRL_Y_GAMMA_EN_SHIFT) /* 0x00000001 */ +#define VOP_POST_CTRL_POST_SCL_EN_SHIFT (4U) +#define VOP_POST_CTRL_POST_SCL_EN_MASK (0x1U << VOP_POST_CTRL_POST_SCL_EN_SHIFT) /* 0x00000010 */ +#define VOP_POST_CTRL_POST_SCL_HMODE_SHIFT (8U) +#define VOP_POST_CTRL_POST_SCL_HMODE_MASK (0x3U << VOP_POST_CTRL_POST_SCL_HMODE_SHIFT) /* 0x00000300 */ +#define VOP_POST_CTRL_POST_SCL_VMODE_SHIFT (10U) +#define VOP_POST_CTRL_POST_SCL_VMODE_MASK (0x3U << VOP_POST_CTRL_POST_SCL_VMODE_SHIFT) /* 0x00000C00 */ +#define VOP_POST_CTRL_POST_CSC_EN_SHIFT (12U) +#define VOP_POST_CTRL_POST_CSC_EN_MASK (0x1U << VOP_POST_CTRL_POST_CSC_EN_SHIFT) /* 0x00001000 */ +#define VOP_POST_CTRL_POST_CSC_MODE_SHIFT (14U) +#define VOP_POST_CTRL_POST_CSC_MODE_MASK (0x3U << VOP_POST_CTRL_POST_CSC_MODE_SHIFT) /* 0x0000C000 */ +#define VOP_POST_CTRL_COLOR_MATRIX_EN_SHIFT (16U) +#define VOP_POST_CTRL_COLOR_MATRIX_EN_MASK (0x1U << VOP_POST_CTRL_COLOR_MATRIX_EN_SHIFT) /* 0x00010000 */ +#define VOP_POST_CTRL_COLOR_MATRIX_COE_MODE_SHIFT (17U) +#define VOP_POST_CTRL_COLOR_MATRIX_COE_MODE_MASK (0x1U << VOP_POST_CTRL_COLOR_MATRIX_COE_MODE_SHIFT) /* 0x00020000 */ +#define VOP_POST_CTRL_CLIP_EN_SHIFT (20U) +#define VOP_POST_CTRL_CLIP_EN_MASK (0x1U << VOP_POST_CTRL_CLIP_EN_SHIFT) /* 0x00100000 */ +#define VOP_POST_CTRL_Y_THRES_SHIFT (24U) +#define VOP_POST_CTRL_Y_THRES_MASK (0xFFU << VOP_POST_CTRL_Y_THRES_SHIFT) /* 0xFF000000 */ +/* COLOR_MATRIX_COE0 */ +#define VOP_COLOR_MATRIX_COE0_OFFSET (0x184U) +#define VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_COE00_SHIFT (0U) +#define VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_COE00_MASK (0xFFU << VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_COE00_SHIFT) /* 0x000000FF */ +#define VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_COE01_SHIFT (8U) +#define VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_COE01_MASK (0xFFU << VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_COE01_SHIFT) /* 0x0000FF00 */ +#define VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_COE02_SHIFT (16U) +#define VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_COE02_MASK (0xFFU << VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_COE02_SHIFT) /* 0x00FF0000 */ +#define VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_OFFSET0_SHIFT (24U) +#define VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_OFFSET0_MASK (0xFFU << VOP_COLOR_MATRIX_COE0_COLOR_MATRIX_OFFSET0_SHIFT) /* 0xFF000000 */ +/* COLOR_MATRIX_COE1 */ +#define VOP_COLOR_MATRIX_COE1_OFFSET (0x188U) +#define VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_COE10_SHIFT (0U) +#define VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_COE10_MASK (0xFFU << VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_COE10_SHIFT) /* 0x000000FF */ +#define VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_COE11_SHIFT (8U) +#define VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_COE11_MASK (0xFFU << VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_COE11_SHIFT) /* 0x0000FF00 */ +#define VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_COE12_SHIFT (16U) +#define VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_COE12_MASK (0xFFU << VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_COE12_SHIFT) /* 0x00FF0000 */ +#define VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_OFFSET1_SHIFT (24U) +#define VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_OFFSET1_MASK (0xFFU << VOP_COLOR_MATRIX_COE1_COLOR_MATRIX_OFFSET1_SHIFT) /* 0xFF000000 */ +/* COLOR_MATRIX_COE2 */ +#define VOP_COLOR_MATRIX_COE2_OFFSET (0x18CU) +#define VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_COE20_SHIFT (0U) +#define VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_COE20_MASK (0xFFU << VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_COE20_SHIFT) /* 0x000000FF */ +#define VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_COE21_SHIFT (8U) +#define VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_COE21_MASK (0xFFU << VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_COE21_SHIFT) /* 0x0000FF00 */ +#define VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_COE22_SHIFT (16U) +#define VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_COE22_MASK (0xFFU << VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_COE22_SHIFT) /* 0x00FF0000 */ +#define VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_OFFSET2_SHIFT (24U) +#define VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_OFFSET2_MASK (0xFFU << VOP_COLOR_MATRIX_COE2_COLOR_MATRIX_OFFSET2_SHIFT) /* 0xFF000000 */ +/* MCU_WRITE_DATA */ +#define VOP_MCU_WRITE_DATA_OFFSET (0x190U) +#define VOP_MCU_WRITE_DATA_FIELD0000_SHIFT (0U) +#define VOP_MCU_WRITE_DATA_FIELD0000_MASK (0x1U << VOP_MCU_WRITE_DATA_FIELD0000_SHIFT) /* 0x00000001 */ +/* DBG_REG_SCAN_LINE */ +#define VOP_DBG_REG_SCAN_LINE_OFFSET (0x1F0U) +#define VOP_DBG_REG_SCAN_LINE (0x0U) +#define VOP_DBG_REG_SCAN_LINE_SCAN_LINE_NUM_SHIFT (0U) +#define VOP_DBG_REG_SCAN_LINE_SCAN_LINE_NUM_MASK (0xFFFU << VOP_DBG_REG_SCAN_LINE_SCAN_LINE_NUM_SHIFT) /* 0x00000FFF */ +/* BLANKING_VALUE */ +#define VOP_BLANKING_VALUE_OFFSET (0x1F4U) +#define VOP_BLANKING_VALUE_SW_BLANKING_VALUE_SHIFT (0U) +#define VOP_BLANKING_VALUE_SW_BLANKING_VALUE_MASK (0xFFFFFFU << VOP_BLANKING_VALUE_SW_BLANKING_VALUE_SHIFT) /* 0x00FFFFFF */ +#define VOP_BLANKING_VALUE_BLANKING_VALUE_CONFIG_EN_SHIFT (24U) +#define VOP_BLANKING_VALUE_BLANKING_VALUE_CONFIG_EN_MASK (0x1U << VOP_BLANKING_VALUE_BLANKING_VALUE_CONFIG_EN_SHIFT) /* 0x01000000 */ +/* FLAG_REG_FRM_VALID */ +#define VOP_FLAG_REG_FRM_VALID_OFFSET (0x1F8U) +#define VOP_FLAG_REG_FRM_VALID (0x0U) +#define VOP_FLAG_REG_FRM_VALID_FLAG_REG_FRM_VALID_SHIFT (0U) +#define VOP_FLAG_REG_FRM_VALID_FLAG_REG_FRM_VALID_MASK (0xFFFFFFFFU << VOP_FLAG_REG_FRM_VALID_FLAG_REG_FRM_VALID_SHIFT) /* 0xFFFFFFFF */ +/* FLAG_REG */ +#define VOP_FLAG_REG_OFFSET (0x1FCU) +#define VOP_FLAG_REG_FLAG_REG_SHIFT (0U) +#define VOP_FLAG_REG_FLAG_REG_MASK (0xFFFFFFFFU << VOP_FLAG_REG_FLAG_REG_SHIFT) /* 0xFFFFFFFF */ +/* WIN0_BPP_LUT000 */ +#define VOP_WIN0_BPP_LUT000_OFFSET (0x200U) +/* WIN0_BPP_LUT001 */ +#define VOP_WIN0_BPP_LUT001_OFFSET (0x204U) +/* WIN0_BPP_LUT002 */ +#define VOP_WIN0_BPP_LUT002_OFFSET (0x208U) +/* WIN0_BPP_LUT003 */ +#define VOP_WIN0_BPP_LUT003_OFFSET (0x20CU) +/* WIN0_BPP_LUT004 */ +#define VOP_WIN0_BPP_LUT004_OFFSET (0x210U) +/* WIN0_BPP_LUT005 */ +#define VOP_WIN0_BPP_LUT005_OFFSET (0x214U) +/* WIN0_BPP_LUT006 */ +#define VOP_WIN0_BPP_LUT006_OFFSET (0x218U) +/* WIN0_BPP_LUT007 */ +#define VOP_WIN0_BPP_LUT007_OFFSET (0x21CU) +/* WIN0_BPP_LUT008 */ +#define VOP_WIN0_BPP_LUT008_OFFSET (0x220U) +/* WIN0_BPP_LUT009 */ +#define VOP_WIN0_BPP_LUT009_OFFSET (0x224U) +/* WIN0_BPP_LUT010 */ +#define VOP_WIN0_BPP_LUT010_OFFSET (0x228U) +/* WIN0_BPP_LUT011 */ +#define VOP_WIN0_BPP_LUT011_OFFSET (0x22CU) +/* WIN0_BPP_LUT012 */ +#define VOP_WIN0_BPP_LUT012_OFFSET (0x230U) +/* WIN0_BPP_LUT013 */ +#define VOP_WIN0_BPP_LUT013_OFFSET (0x234U) +/* WIN0_BPP_LUT014 */ +#define VOP_WIN0_BPP_LUT014_OFFSET (0x238U) +/* WIN0_BPP_LUT015 */ +#define VOP_WIN0_BPP_LUT015_OFFSET (0x23CU) +/* WIN0_BPP_LUT016 */ +#define VOP_WIN0_BPP_LUT016_OFFSET (0x240U) +/* WIN0_BPP_LUT017 */ +#define VOP_WIN0_BPP_LUT017_OFFSET (0x244U) +/* WIN0_BPP_LUT018 */ +#define VOP_WIN0_BPP_LUT018_OFFSET (0x248U) +/* WIN0_BPP_LUT019 */ +#define VOP_WIN0_BPP_LUT019_OFFSET (0x24CU) +/* WIN0_BPP_LUT020 */ +#define VOP_WIN0_BPP_LUT020_OFFSET (0x250U) +/* WIN0_BPP_LUT021 */ +#define VOP_WIN0_BPP_LUT021_OFFSET (0x254U) +/* WIN0_BPP_LUT022 */ +#define VOP_WIN0_BPP_LUT022_OFFSET (0x258U) +/* WIN0_BPP_LUT023 */ +#define VOP_WIN0_BPP_LUT023_OFFSET (0x25CU) +/* WIN0_BPP_LUT024 */ +#define VOP_WIN0_BPP_LUT024_OFFSET (0x260U) +/* WIN0_BPP_LUT025 */ +#define VOP_WIN0_BPP_LUT025_OFFSET (0x264U) +/* WIN0_BPP_LUT026 */ +#define VOP_WIN0_BPP_LUT026_OFFSET (0x268U) +/* WIN0_BPP_LUT027 */ +#define VOP_WIN0_BPP_LUT027_OFFSET (0x26CU) +/* WIN0_BPP_LUT028 */ +#define VOP_WIN0_BPP_LUT028_OFFSET (0x270U) +/* WIN0_BPP_LUT029 */ +#define VOP_WIN0_BPP_LUT029_OFFSET (0x274U) +/* WIN0_BPP_LUT030 */ +#define VOP_WIN0_BPP_LUT030_OFFSET (0x278U) +/* WIN0_BPP_LUT031 */ +#define VOP_WIN0_BPP_LUT031_OFFSET (0x27CU) +/* WIN0_BPP_LUT032 */ +#define VOP_WIN0_BPP_LUT032_OFFSET (0x280U) +/* WIN0_BPP_LUT033 */ +#define VOP_WIN0_BPP_LUT033_OFFSET (0x284U) +/* WIN0_BPP_LUT034 */ +#define VOP_WIN0_BPP_LUT034_OFFSET (0x288U) +/* WIN0_BPP_LUT035 */ +#define VOP_WIN0_BPP_LUT035_OFFSET (0x28CU) +/* WIN0_BPP_LUT036 */ +#define VOP_WIN0_BPP_LUT036_OFFSET (0x290U) +/* WIN0_BPP_LUT037 */ +#define VOP_WIN0_BPP_LUT037_OFFSET (0x294U) +/* WIN0_BPP_LUT038 */ +#define VOP_WIN0_BPP_LUT038_OFFSET (0x298U) +/* WIN0_BPP_LUT039 */ +#define VOP_WIN0_BPP_LUT039_OFFSET (0x29CU) +/* WIN0_BPP_LUT040 */ +#define VOP_WIN0_BPP_LUT040_OFFSET (0x2A0U) +/* WIN0_BPP_LUT041 */ +#define VOP_WIN0_BPP_LUT041_OFFSET (0x2A4U) +/* WIN0_BPP_LUT042 */ +#define VOP_WIN0_BPP_LUT042_OFFSET (0x2A8U) +/* WIN0_BPP_LUT043 */ +#define VOP_WIN0_BPP_LUT043_OFFSET (0x2ACU) +/* WIN0_BPP_LUT044 */ +#define VOP_WIN0_BPP_LUT044_OFFSET (0x2B0U) +/* WIN0_BPP_LUT045 */ +#define VOP_WIN0_BPP_LUT045_OFFSET (0x2B4U) +/* WIN0_BPP_LUT046 */ +#define VOP_WIN0_BPP_LUT046_OFFSET (0x2B8U) +/* WIN0_BPP_LUT047 */ +#define VOP_WIN0_BPP_LUT047_OFFSET (0x2BCU) +/* WIN0_BPP_LUT048 */ +#define VOP_WIN0_BPP_LUT048_OFFSET (0x2C0U) +/* WIN0_BPP_LUT049 */ +#define VOP_WIN0_BPP_LUT049_OFFSET (0x2C4U) +/* WIN0_BPP_LUT050 */ +#define VOP_WIN0_BPP_LUT050_OFFSET (0x2C8U) +/* WIN0_BPP_LUT051 */ +#define VOP_WIN0_BPP_LUT051_OFFSET (0x2CCU) +/* WIN0_BPP_LUT052 */ +#define VOP_WIN0_BPP_LUT052_OFFSET (0x2D0U) +/* WIN0_BPP_LUT053 */ +#define VOP_WIN0_BPP_LUT053_OFFSET (0x2D4U) +/* WIN0_BPP_LUT054 */ +#define VOP_WIN0_BPP_LUT054_OFFSET (0x2D8U) +/* WIN0_BPP_LUT055 */ +#define VOP_WIN0_BPP_LUT055_OFFSET (0x2DCU) +/* WIN0_BPP_LUT056 */ +#define VOP_WIN0_BPP_LUT056_OFFSET (0x2E0U) +/* WIN0_BPP_LUT057 */ +#define VOP_WIN0_BPP_LUT057_OFFSET (0x2E4U) +/* WIN0_BPP_LUT058 */ +#define VOP_WIN0_BPP_LUT058_OFFSET (0x2E8U) +/* WIN0_BPP_LUT059 */ +#define VOP_WIN0_BPP_LUT059_OFFSET (0x2ECU) +/* WIN0_BPP_LUT060 */ +#define VOP_WIN0_BPP_LUT060_OFFSET (0x2F0U) +/* WIN0_BPP_LUT061 */ +#define VOP_WIN0_BPP_LUT061_OFFSET (0x2F4U) +/* WIN0_BPP_LUT062 */ +#define VOP_WIN0_BPP_LUT062_OFFSET (0x2F8U) +/* WIN0_BPP_LUT063 */ +#define VOP_WIN0_BPP_LUT063_OFFSET (0x2FCU) +/* WIN0_BPP_LUT064 */ +#define VOP_WIN0_BPP_LUT064_OFFSET (0x300U) +/* WIN0_BPP_LUT065 */ +#define VOP_WIN0_BPP_LUT065_OFFSET (0x304U) +/* WIN0_BPP_LUT066 */ +#define VOP_WIN0_BPP_LUT066_OFFSET (0x308U) +/* WIN0_BPP_LUT067 */ +#define VOP_WIN0_BPP_LUT067_OFFSET (0x30CU) +/* WIN0_BPP_LUT068 */ +#define VOP_WIN0_BPP_LUT068_OFFSET (0x310U) +/* WIN0_BPP_LUT069 */ +#define VOP_WIN0_BPP_LUT069_OFFSET (0x314U) +/* WIN0_BPP_LUT070 */ +#define VOP_WIN0_BPP_LUT070_OFFSET (0x318U) +/* WIN0_BPP_LUT071 */ +#define VOP_WIN0_BPP_LUT071_OFFSET (0x31CU) +/* WIN0_BPP_LUT072 */ +#define VOP_WIN0_BPP_LUT072_OFFSET (0x320U) +/* WIN0_BPP_LUT073 */ +#define VOP_WIN0_BPP_LUT073_OFFSET (0x324U) +/* WIN0_BPP_LUT074 */ +#define VOP_WIN0_BPP_LUT074_OFFSET (0x328U) +/* WIN0_BPP_LUT075 */ +#define VOP_WIN0_BPP_LUT075_OFFSET (0x32CU) +/* WIN0_BPP_LUT076 */ +#define VOP_WIN0_BPP_LUT076_OFFSET (0x330U) +/* WIN0_BPP_LUT077 */ +#define VOP_WIN0_BPP_LUT077_OFFSET (0x334U) +/* WIN0_BPP_LUT078 */ +#define VOP_WIN0_BPP_LUT078_OFFSET (0x338U) +/* WIN0_BPP_LUT079 */ +#define VOP_WIN0_BPP_LUT079_OFFSET (0x33CU) +/* WIN0_BPP_LUT080 */ +#define VOP_WIN0_BPP_LUT080_OFFSET (0x340U) +/* WIN0_BPP_LUT081 */ +#define VOP_WIN0_BPP_LUT081_OFFSET (0x344U) +/* WIN0_BPP_LUT082 */ +#define VOP_WIN0_BPP_LUT082_OFFSET (0x348U) +/* WIN0_BPP_LUT083 */ +#define VOP_WIN0_BPP_LUT083_OFFSET (0x34CU) +/* WIN0_BPP_LUT084 */ +#define VOP_WIN0_BPP_LUT084_OFFSET (0x350U) +/* WIN0_BPP_LUT085 */ +#define VOP_WIN0_BPP_LUT085_OFFSET (0x354U) +/* WIN0_BPP_LUT086 */ +#define VOP_WIN0_BPP_LUT086_OFFSET (0x358U) +/* WIN0_BPP_LUT087 */ +#define VOP_WIN0_BPP_LUT087_OFFSET (0x35CU) +/* WIN0_BPP_LUT088 */ +#define VOP_WIN0_BPP_LUT088_OFFSET (0x360U) +/* WIN0_BPP_LUT089 */ +#define VOP_WIN0_BPP_LUT089_OFFSET (0x364U) +/* WIN0_BPP_LUT090 */ +#define VOP_WIN0_BPP_LUT090_OFFSET (0x368U) +/* WIN0_BPP_LUT091 */ +#define VOP_WIN0_BPP_LUT091_OFFSET (0x36CU) +/* WIN0_BPP_LUT092 */ +#define VOP_WIN0_BPP_LUT092_OFFSET (0x370U) +/* WIN0_BPP_LUT093 */ +#define VOP_WIN0_BPP_LUT093_OFFSET (0x374U) +/* WIN0_BPP_LUT094 */ +#define VOP_WIN0_BPP_LUT094_OFFSET (0x378U) +/* WIN0_BPP_LUT095 */ +#define VOP_WIN0_BPP_LUT095_OFFSET (0x37CU) +/* WIN0_BPP_LUT096 */ +#define VOP_WIN0_BPP_LUT096_OFFSET (0x380U) +/* WIN0_BPP_LUT097 */ +#define VOP_WIN0_BPP_LUT097_OFFSET (0x384U) +/* WIN0_BPP_LUT098 */ +#define VOP_WIN0_BPP_LUT098_OFFSET (0x388U) +/* WIN0_BPP_LUT099 */ +#define VOP_WIN0_BPP_LUT099_OFFSET (0x38CU) +/* WIN0_BPP_LUT100 */ +#define VOP_WIN0_BPP_LUT100_OFFSET (0x390U) +/* WIN0_BPP_LUT101 */ +#define VOP_WIN0_BPP_LUT101_OFFSET (0x394U) +/* WIN0_BPP_LUT102 */ +#define VOP_WIN0_BPP_LUT102_OFFSET (0x398U) +/* WIN0_BPP_LUT103 */ +#define VOP_WIN0_BPP_LUT103_OFFSET (0x39CU) +/* WIN0_BPP_LUT104 */ +#define VOP_WIN0_BPP_LUT104_OFFSET (0x3A0U) +/* WIN0_BPP_LUT105 */ +#define VOP_WIN0_BPP_LUT105_OFFSET (0x3A4U) +/* WIN0_BPP_LUT106 */ +#define VOP_WIN0_BPP_LUT106_OFFSET (0x3A8U) +/* WIN0_BPP_LUT107 */ +#define VOP_WIN0_BPP_LUT107_OFFSET (0x3ACU) +/* WIN0_BPP_LUT108 */ +#define VOP_WIN0_BPP_LUT108_OFFSET (0x3B0U) +/* WIN0_BPP_LUT109 */ +#define VOP_WIN0_BPP_LUT109_OFFSET (0x3B4U) +/* WIN0_BPP_LUT110 */ +#define VOP_WIN0_BPP_LUT110_OFFSET (0x3B8U) +/* WIN0_BPP_LUT111 */ +#define VOP_WIN0_BPP_LUT111_OFFSET (0x3BCU) +/* WIN0_BPP_LUT112 */ +#define VOP_WIN0_BPP_LUT112_OFFSET (0x3C0U) +/* WIN0_BPP_LUT113 */ +#define VOP_WIN0_BPP_LUT113_OFFSET (0x3C4U) +/* WIN0_BPP_LUT114 */ +#define VOP_WIN0_BPP_LUT114_OFFSET (0x3C8U) +/* WIN0_BPP_LUT115 */ +#define VOP_WIN0_BPP_LUT115_OFFSET (0x3CCU) +/* WIN0_BPP_LUT116 */ +#define VOP_WIN0_BPP_LUT116_OFFSET (0x3D0U) +/* WIN0_BPP_LUT117 */ +#define VOP_WIN0_BPP_LUT117_OFFSET (0x3D4U) +/* WIN0_BPP_LUT118 */ +#define VOP_WIN0_BPP_LUT118_OFFSET (0x3D8U) +/* WIN0_BPP_LUT119 */ +#define VOP_WIN0_BPP_LUT119_OFFSET (0x3DCU) +/* WIN0_BPP_LUT120 */ +#define VOP_WIN0_BPP_LUT120_OFFSET (0x3E0U) +/* WIN0_BPP_LUT121 */ +#define VOP_WIN0_BPP_LUT121_OFFSET (0x3E4U) +/* WIN0_BPP_LUT122 */ +#define VOP_WIN0_BPP_LUT122_OFFSET (0x3E8U) +/* WIN0_BPP_LUT123 */ +#define VOP_WIN0_BPP_LUT123_OFFSET (0x3ECU) +/* WIN0_BPP_LUT124 */ +#define VOP_WIN0_BPP_LUT124_OFFSET (0x3F0U) +/* WIN0_BPP_LUT125 */ +#define VOP_WIN0_BPP_LUT125_OFFSET (0x3F4U) +/* WIN0_BPP_LUT126 */ +#define VOP_WIN0_BPP_LUT126_OFFSET (0x3F8U) +/* WIN0_BPP_LUT127 */ +#define VOP_WIN0_BPP_LUT127_OFFSET (0x3FCU) +/* WIN0_BPP_LUT128 */ +#define VOP_WIN0_BPP_LUT128_OFFSET (0x400U) +/* WIN0_BPP_LUT129 */ +#define VOP_WIN0_BPP_LUT129_OFFSET (0x404U) +/* WIN0_BPP_LUT130 */ +#define VOP_WIN0_BPP_LUT130_OFFSET (0x408U) +/* WIN0_BPP_LUT131 */ +#define VOP_WIN0_BPP_LUT131_OFFSET (0x40CU) +/* WIN0_BPP_LUT132 */ +#define VOP_WIN0_BPP_LUT132_OFFSET (0x410U) +/* WIN0_BPP_LUT133 */ +#define VOP_WIN0_BPP_LUT133_OFFSET (0x414U) +/* WIN0_BPP_LUT134 */ +#define VOP_WIN0_BPP_LUT134_OFFSET (0x418U) +/* WIN0_BPP_LUT135 */ +#define VOP_WIN0_BPP_LUT135_OFFSET (0x41CU) +/* WIN0_BPP_LUT136 */ +#define VOP_WIN0_BPP_LUT136_OFFSET (0x420U) +/* WIN0_BPP_LUT137 */ +#define VOP_WIN0_BPP_LUT137_OFFSET (0x424U) +/* WIN0_BPP_LUT138 */ +#define VOP_WIN0_BPP_LUT138_OFFSET (0x428U) +/* WIN0_BPP_LUT139 */ +#define VOP_WIN0_BPP_LUT139_OFFSET (0x42CU) +/* WIN0_BPP_LUT140 */ +#define VOP_WIN0_BPP_LUT140_OFFSET (0x430U) +/* WIN0_BPP_LUT141 */ +#define VOP_WIN0_BPP_LUT141_OFFSET (0x434U) +/* WIN0_BPP_LUT142 */ +#define VOP_WIN0_BPP_LUT142_OFFSET (0x438U) +/* WIN0_BPP_LUT143 */ +#define VOP_WIN0_BPP_LUT143_OFFSET (0x43CU) +/* WIN0_BPP_LUT144 */ +#define VOP_WIN0_BPP_LUT144_OFFSET (0x440U) +/* WIN0_BPP_LUT145 */ +#define VOP_WIN0_BPP_LUT145_OFFSET (0x444U) +/* WIN0_BPP_LUT146 */ +#define VOP_WIN0_BPP_LUT146_OFFSET (0x448U) +/* WIN0_BPP_LUT147 */ +#define VOP_WIN0_BPP_LUT147_OFFSET (0x44CU) +/* WIN0_BPP_LUT148 */ +#define VOP_WIN0_BPP_LUT148_OFFSET (0x450U) +/* WIN0_BPP_LUT149 */ +#define VOP_WIN0_BPP_LUT149_OFFSET (0x454U) +/* WIN0_BPP_LUT150 */ +#define VOP_WIN0_BPP_LUT150_OFFSET (0x458U) +/* WIN0_BPP_LUT151 */ +#define VOP_WIN0_BPP_LUT151_OFFSET (0x45CU) +/* WIN0_BPP_LUT152 */ +#define VOP_WIN0_BPP_LUT152_OFFSET (0x460U) +/* WIN0_BPP_LUT153 */ +#define VOP_WIN0_BPP_LUT153_OFFSET (0x464U) +/* WIN0_BPP_LUT154 */ +#define VOP_WIN0_BPP_LUT154_OFFSET (0x468U) +/* WIN0_BPP_LUT155 */ +#define VOP_WIN0_BPP_LUT155_OFFSET (0x46CU) +/* WIN0_BPP_LUT156 */ +#define VOP_WIN0_BPP_LUT156_OFFSET (0x470U) +/* WIN0_BPP_LUT157 */ +#define VOP_WIN0_BPP_LUT157_OFFSET (0x474U) +/* WIN0_BPP_LUT158 */ +#define VOP_WIN0_BPP_LUT158_OFFSET (0x478U) +/* WIN0_BPP_LUT159 */ +#define VOP_WIN0_BPP_LUT159_OFFSET (0x47CU) +/* WIN0_BPP_LUT160 */ +#define VOP_WIN0_BPP_LUT160_OFFSET (0x480U) +/* WIN0_BPP_LUT161 */ +#define VOP_WIN0_BPP_LUT161_OFFSET (0x484U) +/* WIN0_BPP_LUT162 */ +#define VOP_WIN0_BPP_LUT162_OFFSET (0x488U) +/* WIN0_BPP_LUT163 */ +#define VOP_WIN0_BPP_LUT163_OFFSET (0x48CU) +/* WIN0_BPP_LUT164 */ +#define VOP_WIN0_BPP_LUT164_OFFSET (0x490U) +/* WIN0_BPP_LUT165 */ +#define VOP_WIN0_BPP_LUT165_OFFSET (0x494U) +/* WIN0_BPP_LUT166 */ +#define VOP_WIN0_BPP_LUT166_OFFSET (0x498U) +/* WIN0_BPP_LUT167 */ +#define VOP_WIN0_BPP_LUT167_OFFSET (0x49CU) +/* WIN0_BPP_LUT168 */ +#define VOP_WIN0_BPP_LUT168_OFFSET (0x4A0U) +/* WIN0_BPP_LUT169 */ +#define VOP_WIN0_BPP_LUT169_OFFSET (0x4A4U) +/* WIN0_BPP_LUT170 */ +#define VOP_WIN0_BPP_LUT170_OFFSET (0x4A8U) +/* WIN0_BPP_LUT171 */ +#define VOP_WIN0_BPP_LUT171_OFFSET (0x4ACU) +/* WIN0_BPP_LUT172 */ +#define VOP_WIN0_BPP_LUT172_OFFSET (0x4B0U) +/* WIN0_BPP_LUT173 */ +#define VOP_WIN0_BPP_LUT173_OFFSET (0x4B4U) +/* WIN0_BPP_LUT174 */ +#define VOP_WIN0_BPP_LUT174_OFFSET (0x4B8U) +/* WIN0_BPP_LUT175 */ +#define VOP_WIN0_BPP_LUT175_OFFSET (0x4BCU) +/* WIN0_BPP_LUT176 */ +#define VOP_WIN0_BPP_LUT176_OFFSET (0x4C0U) +/* WIN0_BPP_LUT177 */ +#define VOP_WIN0_BPP_LUT177_OFFSET (0x4C4U) +/* WIN0_BPP_LUT178 */ +#define VOP_WIN0_BPP_LUT178_OFFSET (0x4C8U) +/* WIN0_BPP_LUT179 */ +#define VOP_WIN0_BPP_LUT179_OFFSET (0x4CCU) +/* WIN0_BPP_LUT180 */ +#define VOP_WIN0_BPP_LUT180_OFFSET (0x4D0U) +/* WIN0_BPP_LUT181 */ +#define VOP_WIN0_BPP_LUT181_OFFSET (0x4D4U) +/* WIN0_BPP_LUT182 */ +#define VOP_WIN0_BPP_LUT182_OFFSET (0x4D8U) +/* WIN0_BPP_LUT183 */ +#define VOP_WIN0_BPP_LUT183_OFFSET (0x4DCU) +/* WIN0_BPP_LUT184 */ +#define VOP_WIN0_BPP_LUT184_OFFSET (0x4E0U) +/* WIN0_BPP_LUT185 */ +#define VOP_WIN0_BPP_LUT185_OFFSET (0x4E4U) +/* WIN0_BPP_LUT186 */ +#define VOP_WIN0_BPP_LUT186_OFFSET (0x4E8U) +/* WIN0_BPP_LUT187 */ +#define VOP_WIN0_BPP_LUT187_OFFSET (0x4ECU) +/* WIN0_BPP_LUT188 */ +#define VOP_WIN0_BPP_LUT188_OFFSET (0x4F0U) +/* WIN0_BPP_LUT189 */ +#define VOP_WIN0_BPP_LUT189_OFFSET (0x4F4U) +/* WIN0_BPP_LUT190 */ +#define VOP_WIN0_BPP_LUT190_OFFSET (0x4F8U) +/* WIN0_BPP_LUT191 */ +#define VOP_WIN0_BPP_LUT191_OFFSET (0x4FCU) +/* WIN0_BPP_LUT192 */ +#define VOP_WIN0_BPP_LUT192_OFFSET (0x500U) +/* WIN0_BPP_LUT193 */ +#define VOP_WIN0_BPP_LUT193_OFFSET (0x504U) +/* WIN0_BPP_LUT194 */ +#define VOP_WIN0_BPP_LUT194_OFFSET (0x508U) +/* WIN0_BPP_LUT195 */ +#define VOP_WIN0_BPP_LUT195_OFFSET (0x50CU) +/* WIN0_BPP_LUT196 */ +#define VOP_WIN0_BPP_LUT196_OFFSET (0x510U) +/* WIN0_BPP_LUT197 */ +#define VOP_WIN0_BPP_LUT197_OFFSET (0x514U) +/* WIN0_BPP_LUT198 */ +#define VOP_WIN0_BPP_LUT198_OFFSET (0x518U) +/* WIN0_BPP_LUT199 */ +#define VOP_WIN0_BPP_LUT199_OFFSET (0x51CU) +/* WIN0_BPP_LUT200 */ +#define VOP_WIN0_BPP_LUT200_OFFSET (0x520U) +/* WIN0_BPP_LUT201 */ +#define VOP_WIN0_BPP_LUT201_OFFSET (0x524U) +/* WIN0_BPP_LUT202 */ +#define VOP_WIN0_BPP_LUT202_OFFSET (0x528U) +/* WIN0_BPP_LUT203 */ +#define VOP_WIN0_BPP_LUT203_OFFSET (0x52CU) +/* WIN0_BPP_LUT204 */ +#define VOP_WIN0_BPP_LUT204_OFFSET (0x530U) +/* WIN0_BPP_LUT205 */ +#define VOP_WIN0_BPP_LUT205_OFFSET (0x534U) +/* WIN0_BPP_LUT206 */ +#define VOP_WIN0_BPP_LUT206_OFFSET (0x538U) +/* WIN0_BPP_LUT207 */ +#define VOP_WIN0_BPP_LUT207_OFFSET (0x53CU) +/* WIN0_BPP_LUT208 */ +#define VOP_WIN0_BPP_LUT208_OFFSET (0x540U) +/* WIN0_BPP_LUT209 */ +#define VOP_WIN0_BPP_LUT209_OFFSET (0x544U) +/* WIN0_BPP_LUT210 */ +#define VOP_WIN0_BPP_LUT210_OFFSET (0x548U) +/* WIN0_BPP_LUT211 */ +#define VOP_WIN0_BPP_LUT211_OFFSET (0x54CU) +/* WIN0_BPP_LUT212 */ +#define VOP_WIN0_BPP_LUT212_OFFSET (0x550U) +/* WIN0_BPP_LUT213 */ +#define VOP_WIN0_BPP_LUT213_OFFSET (0x554U) +/* WIN0_BPP_LUT214 */ +#define VOP_WIN0_BPP_LUT214_OFFSET (0x558U) +/* WIN0_BPP_LUT215 */ +#define VOP_WIN0_BPP_LUT215_OFFSET (0x55CU) +/* WIN0_BPP_LUT216 */ +#define VOP_WIN0_BPP_LUT216_OFFSET (0x560U) +/* WIN0_BPP_LUT217 */ +#define VOP_WIN0_BPP_LUT217_OFFSET (0x564U) +/* WIN0_BPP_LUT218 */ +#define VOP_WIN0_BPP_LUT218_OFFSET (0x568U) +/* WIN0_BPP_LUT219 */ +#define VOP_WIN0_BPP_LUT219_OFFSET (0x56CU) +/* WIN0_BPP_LUT220 */ +#define VOP_WIN0_BPP_LUT220_OFFSET (0x570U) +/* WIN0_BPP_LUT221 */ +#define VOP_WIN0_BPP_LUT221_OFFSET (0x574U) +/* WIN0_BPP_LUT222 */ +#define VOP_WIN0_BPP_LUT222_OFFSET (0x578U) +/* WIN0_BPP_LUT223 */ +#define VOP_WIN0_BPP_LUT223_OFFSET (0x57CU) +/* WIN0_BPP_LUT224 */ +#define VOP_WIN0_BPP_LUT224_OFFSET (0x580U) +/* WIN0_BPP_LUT225 */ +#define VOP_WIN0_BPP_LUT225_OFFSET (0x584U) +/* WIN0_BPP_LUT226 */ +#define VOP_WIN0_BPP_LUT226_OFFSET (0x588U) +/* WIN0_BPP_LUT227 */ +#define VOP_WIN0_BPP_LUT227_OFFSET (0x58CU) +/* WIN0_BPP_LUT228 */ +#define VOP_WIN0_BPP_LUT228_OFFSET (0x590U) +/* WIN0_BPP_LUT229 */ +#define VOP_WIN0_BPP_LUT229_OFFSET (0x594U) +/* WIN0_BPP_LUT230 */ +#define VOP_WIN0_BPP_LUT230_OFFSET (0x598U) +/* WIN0_BPP_LUT231 */ +#define VOP_WIN0_BPP_LUT231_OFFSET (0x59CU) +/* WIN0_BPP_LUT232 */ +#define VOP_WIN0_BPP_LUT232_OFFSET (0x5A0U) +/* WIN0_BPP_LUT233 */ +#define VOP_WIN0_BPP_LUT233_OFFSET (0x5A4U) +/* WIN0_BPP_LUT234 */ +#define VOP_WIN0_BPP_LUT234_OFFSET (0x5A8U) +/* WIN0_BPP_LUT235 */ +#define VOP_WIN0_BPP_LUT235_OFFSET (0x5ACU) +/* WIN0_BPP_LUT236 */ +#define VOP_WIN0_BPP_LUT236_OFFSET (0x5B0U) +/* WIN0_BPP_LUT237 */ +#define VOP_WIN0_BPP_LUT237_OFFSET (0x5B4U) +/* WIN0_BPP_LUT238 */ +#define VOP_WIN0_BPP_LUT238_OFFSET (0x5B8U) +/* WIN0_BPP_LUT239 */ +#define VOP_WIN0_BPP_LUT239_OFFSET (0x5BCU) +/* WIN0_BPP_LUT240 */ +#define VOP_WIN0_BPP_LUT240_OFFSET (0x5C0U) +/* WIN0_BPP_LUT241 */ +#define VOP_WIN0_BPP_LUT241_OFFSET (0x5C4U) +/* WIN0_BPP_LUT242 */ +#define VOP_WIN0_BPP_LUT242_OFFSET (0x5C8U) +/* WIN0_BPP_LUT243 */ +#define VOP_WIN0_BPP_LUT243_OFFSET (0x5CCU) +/* WIN0_BPP_LUT244 */ +#define VOP_WIN0_BPP_LUT244_OFFSET (0x5D0U) +/* WIN0_BPP_LUT245 */ +#define VOP_WIN0_BPP_LUT245_OFFSET (0x5D4U) +/* WIN0_BPP_LUT246 */ +#define VOP_WIN0_BPP_LUT246_OFFSET (0x5D8U) +/* WIN0_BPP_LUT247 */ +#define VOP_WIN0_BPP_LUT247_OFFSET (0x5DCU) +/* WIN0_BPP_LUT248 */ +#define VOP_WIN0_BPP_LUT248_OFFSET (0x5E0U) +/* WIN0_BPP_LUT249 */ +#define VOP_WIN0_BPP_LUT249_OFFSET (0x5E4U) +/* WIN0_BPP_LUT250 */ +#define VOP_WIN0_BPP_LUT250_OFFSET (0x5E8U) +/* WIN0_BPP_LUT251 */ +#define VOP_WIN0_BPP_LUT251_OFFSET (0x5ECU) +/* WIN0_BPP_LUT252 */ +#define VOP_WIN0_BPP_LUT252_OFFSET (0x5F0U) +/* WIN0_BPP_LUT253 */ +#define VOP_WIN0_BPP_LUT253_OFFSET (0x5F4U) +/* WIN0_BPP_LUT254 */ +#define VOP_WIN0_BPP_LUT254_OFFSET (0x5F8U) +/* WIN0_BPP_LUT255 */ +#define VOP_WIN0_BPP_LUT255_OFFSET (0x5FCU) +/* WIN1_BPP_LUT000 */ +#define VOP_WIN1_BPP_LUT000_OFFSET (0x600U) +/* WIN1_BPP_LUT001 */ +#define VOP_WIN1_BPP_LUT001_OFFSET (0x604U) +/* WIN1_BPP_LUT002 */ +#define VOP_WIN1_BPP_LUT002_OFFSET (0x608U) +/* WIN1_BPP_LUT003 */ +#define VOP_WIN1_BPP_LUT003_OFFSET (0x60CU) +/* WIN1_BPP_LUT004 */ +#define VOP_WIN1_BPP_LUT004_OFFSET (0x610U) +/* WIN1_BPP_LUT005 */ +#define VOP_WIN1_BPP_LUT005_OFFSET (0x614U) +/* WIN1_BPP_LUT006 */ +#define VOP_WIN1_BPP_LUT006_OFFSET (0x618U) +/* WIN1_BPP_LUT007 */ +#define VOP_WIN1_BPP_LUT007_OFFSET (0x61CU) +/* WIN1_BPP_LUT008 */ +#define VOP_WIN1_BPP_LUT008_OFFSET (0x620U) +/* WIN1_BPP_LUT009 */ +#define VOP_WIN1_BPP_LUT009_OFFSET (0x624U) +/* WIN1_BPP_LUT010 */ +#define VOP_WIN1_BPP_LUT010_OFFSET (0x628U) +/* WIN1_BPP_LUT011 */ +#define VOP_WIN1_BPP_LUT011_OFFSET (0x62CU) +/* WIN1_BPP_LUT012 */ +#define VOP_WIN1_BPP_LUT012_OFFSET (0x630U) +/* WIN1_BPP_LUT013 */ +#define VOP_WIN1_BPP_LUT013_OFFSET (0x634U) +/* WIN1_BPP_LUT014 */ +#define VOP_WIN1_BPP_LUT014_OFFSET (0x638U) +/* WIN1_BPP_LUT015 */ +#define VOP_WIN1_BPP_LUT015_OFFSET (0x63CU) +/* WIN1_BPP_LUT016 */ +#define VOP_WIN1_BPP_LUT016_OFFSET (0x640U) +/* WIN1_BPP_LUT017 */ +#define VOP_WIN1_BPP_LUT017_OFFSET (0x644U) +/* WIN1_BPP_LUT018 */ +#define VOP_WIN1_BPP_LUT018_OFFSET (0x648U) +/* WIN1_BPP_LUT019 */ +#define VOP_WIN1_BPP_LUT019_OFFSET (0x64CU) +/* WIN1_BPP_LUT020 */ +#define VOP_WIN1_BPP_LUT020_OFFSET (0x650U) +/* WIN1_BPP_LUT021 */ +#define VOP_WIN1_BPP_LUT021_OFFSET (0x654U) +/* WIN1_BPP_LUT022 */ +#define VOP_WIN1_BPP_LUT022_OFFSET (0x658U) +/* WIN1_BPP_LUT023 */ +#define VOP_WIN1_BPP_LUT023_OFFSET (0x65CU) +/* WIN1_BPP_LUT024 */ +#define VOP_WIN1_BPP_LUT024_OFFSET (0x660U) +/* WIN1_BPP_LUT025 */ +#define VOP_WIN1_BPP_LUT025_OFFSET (0x664U) +/* WIN1_BPP_LUT026 */ +#define VOP_WIN1_BPP_LUT026_OFFSET (0x668U) +/* WIN1_BPP_LUT027 */ +#define VOP_WIN1_BPP_LUT027_OFFSET (0x66CU) +/* WIN1_BPP_LUT028 */ +#define VOP_WIN1_BPP_LUT028_OFFSET (0x670U) +/* WIN1_BPP_LUT029 */ +#define VOP_WIN1_BPP_LUT029_OFFSET (0x674U) +/* WIN1_BPP_LUT030 */ +#define VOP_WIN1_BPP_LUT030_OFFSET (0x678U) +/* WIN1_BPP_LUT031 */ +#define VOP_WIN1_BPP_LUT031_OFFSET (0x67CU) +/* WIN1_BPP_LUT032 */ +#define VOP_WIN1_BPP_LUT032_OFFSET (0x680U) +/* WIN1_BPP_LUT033 */ +#define VOP_WIN1_BPP_LUT033_OFFSET (0x684U) +/* WIN1_BPP_LUT034 */ +#define VOP_WIN1_BPP_LUT034_OFFSET (0x688U) +/* WIN1_BPP_LUT035 */ +#define VOP_WIN1_BPP_LUT035_OFFSET (0x68CU) +/* WIN1_BPP_LUT036 */ +#define VOP_WIN1_BPP_LUT036_OFFSET (0x690U) +/* WIN1_BPP_LUT037 */ +#define VOP_WIN1_BPP_LUT037_OFFSET (0x694U) +/* WIN1_BPP_LUT038 */ +#define VOP_WIN1_BPP_LUT038_OFFSET (0x698U) +/* WIN1_BPP_LUT039 */ +#define VOP_WIN1_BPP_LUT039_OFFSET (0x69CU) +/* WIN1_BPP_LUT040 */ +#define VOP_WIN1_BPP_LUT040_OFFSET (0x6A0U) +/* WIN1_BPP_LUT041 */ +#define VOP_WIN1_BPP_LUT041_OFFSET (0x6A4U) +/* WIN1_BPP_LUT042 */ +#define VOP_WIN1_BPP_LUT042_OFFSET (0x6A8U) +/* WIN1_BPP_LUT043 */ +#define VOP_WIN1_BPP_LUT043_OFFSET (0x6ACU) +/* WIN1_BPP_LUT044 */ +#define VOP_WIN1_BPP_LUT044_OFFSET (0x6B0U) +/* WIN1_BPP_LUT045 */ +#define VOP_WIN1_BPP_LUT045_OFFSET (0x6B4U) +/* WIN1_BPP_LUT046 */ +#define VOP_WIN1_BPP_LUT046_OFFSET (0x6B8U) +/* WIN1_BPP_LUT047 */ +#define VOP_WIN1_BPP_LUT047_OFFSET (0x6BCU) +/* WIN1_BPP_LUT048 */ +#define VOP_WIN1_BPP_LUT048_OFFSET (0x6C0U) +/* WIN1_BPP_LUT049 */ +#define VOP_WIN1_BPP_LUT049_OFFSET (0x6C4U) +/* WIN1_BPP_LUT050 */ +#define VOP_WIN1_BPP_LUT050_OFFSET (0x6C8U) +/* WIN1_BPP_LUT051 */ +#define VOP_WIN1_BPP_LUT051_OFFSET (0x6CCU) +/* WIN1_BPP_LUT052 */ +#define VOP_WIN1_BPP_LUT052_OFFSET (0x6D0U) +/* WIN1_BPP_LUT053 */ +#define VOP_WIN1_BPP_LUT053_OFFSET (0x6D4U) +/* WIN1_BPP_LUT054 */ +#define VOP_WIN1_BPP_LUT054_OFFSET (0x6D8U) +/* WIN1_BPP_LUT055 */ +#define VOP_WIN1_BPP_LUT055_OFFSET (0x6DCU) +/* WIN1_BPP_LUT056 */ +#define VOP_WIN1_BPP_LUT056_OFFSET (0x6E0U) +/* WIN1_BPP_LUT057 */ +#define VOP_WIN1_BPP_LUT057_OFFSET (0x6E4U) +/* WIN1_BPP_LUT058 */ +#define VOP_WIN1_BPP_LUT058_OFFSET (0x6E8U) +/* WIN1_BPP_LUT059 */ +#define VOP_WIN1_BPP_LUT059_OFFSET (0x6ECU) +/* WIN1_BPP_LUT060 */ +#define VOP_WIN1_BPP_LUT060_OFFSET (0x6F0U) +/* WIN1_BPP_LUT061 */ +#define VOP_WIN1_BPP_LUT061_OFFSET (0x6F4U) +/* WIN1_BPP_LUT062 */ +#define VOP_WIN1_BPP_LUT062_OFFSET (0x6F8U) +/* WIN1_BPP_LUT063 */ +#define VOP_WIN1_BPP_LUT063_OFFSET (0x6FCU) +/* WIN1_BPP_LUT064 */ +#define VOP_WIN1_BPP_LUT064_OFFSET (0x700U) +/* WIN1_BPP_LUT065 */ +#define VOP_WIN1_BPP_LUT065_OFFSET (0x704U) +/* WIN1_BPP_LUT066 */ +#define VOP_WIN1_BPP_LUT066_OFFSET (0x708U) +/* WIN1_BPP_LUT067 */ +#define VOP_WIN1_BPP_LUT067_OFFSET (0x70CU) +/* WIN1_BPP_LUT068 */ +#define VOP_WIN1_BPP_LUT068_OFFSET (0x710U) +/* WIN1_BPP_LUT069 */ +#define VOP_WIN1_BPP_LUT069_OFFSET (0x714U) +/* WIN1_BPP_LUT070 */ +#define VOP_WIN1_BPP_LUT070_OFFSET (0x718U) +/* WIN1_BPP_LUT071 */ +#define VOP_WIN1_BPP_LUT071_OFFSET (0x71CU) +/* WIN1_BPP_LUT072 */ +#define VOP_WIN1_BPP_LUT072_OFFSET (0x720U) +/* WIN1_BPP_LUT073 */ +#define VOP_WIN1_BPP_LUT073_OFFSET (0x724U) +/* WIN1_BPP_LUT074 */ +#define VOP_WIN1_BPP_LUT074_OFFSET (0x728U) +/* WIN1_BPP_LUT075 */ +#define VOP_WIN1_BPP_LUT075_OFFSET (0x72CU) +/* WIN1_BPP_LUT076 */ +#define VOP_WIN1_BPP_LUT076_OFFSET (0x730U) +/* WIN1_BPP_LUT077 */ +#define VOP_WIN1_BPP_LUT077_OFFSET (0x734U) +/* WIN1_BPP_LUT078 */ +#define VOP_WIN1_BPP_LUT078_OFFSET (0x738U) +/* WIN1_BPP_LUT079 */ +#define VOP_WIN1_BPP_LUT079_OFFSET (0x73CU) +/* WIN1_BPP_LUT080 */ +#define VOP_WIN1_BPP_LUT080_OFFSET (0x740U) +/* WIN1_BPP_LUT081 */ +#define VOP_WIN1_BPP_LUT081_OFFSET (0x744U) +/* WIN1_BPP_LUT082 */ +#define VOP_WIN1_BPP_LUT082_OFFSET (0x748U) +/* WIN1_BPP_LUT083 */ +#define VOP_WIN1_BPP_LUT083_OFFSET (0x74CU) +/* WIN1_BPP_LUT084 */ +#define VOP_WIN1_BPP_LUT084_OFFSET (0x750U) +/* WIN1_BPP_LUT085 */ +#define VOP_WIN1_BPP_LUT085_OFFSET (0x754U) +/* WIN1_BPP_LUT086 */ +#define VOP_WIN1_BPP_LUT086_OFFSET (0x758U) +/* WIN1_BPP_LUT087 */ +#define VOP_WIN1_BPP_LUT087_OFFSET (0x75CU) +/* WIN1_BPP_LUT088 */ +#define VOP_WIN1_BPP_LUT088_OFFSET (0x760U) +/* WIN1_BPP_LUT089 */ +#define VOP_WIN1_BPP_LUT089_OFFSET (0x764U) +/* WIN1_BPP_LUT090 */ +#define VOP_WIN1_BPP_LUT090_OFFSET (0x768U) +/* WIN1_BPP_LUT091 */ +#define VOP_WIN1_BPP_LUT091_OFFSET (0x76CU) +/* WIN1_BPP_LUT092 */ +#define VOP_WIN1_BPP_LUT092_OFFSET (0x770U) +/* WIN1_BPP_LUT093 */ +#define VOP_WIN1_BPP_LUT093_OFFSET (0x774U) +/* WIN1_BPP_LUT094 */ +#define VOP_WIN1_BPP_LUT094_OFFSET (0x778U) +/* WIN1_BPP_LUT095 */ +#define VOP_WIN1_BPP_LUT095_OFFSET (0x77CU) +/* WIN1_BPP_LUT096 */ +#define VOP_WIN1_BPP_LUT096_OFFSET (0x780U) +/* WIN1_BPP_LUT097 */ +#define VOP_WIN1_BPP_LUT097_OFFSET (0x784U) +/* WIN1_BPP_LUT098 */ +#define VOP_WIN1_BPP_LUT098_OFFSET (0x788U) +/* WIN1_BPP_LUT099 */ +#define VOP_WIN1_BPP_LUT099_OFFSET (0x78CU) +/* WIN1_BPP_LUT100 */ +#define VOP_WIN1_BPP_LUT100_OFFSET (0x790U) +/* WIN1_BPP_LUT101 */ +#define VOP_WIN1_BPP_LUT101_OFFSET (0x794U) +/* WIN1_BPP_LUT102 */ +#define VOP_WIN1_BPP_LUT102_OFFSET (0x798U) +/* WIN1_BPP_LUT103 */ +#define VOP_WIN1_BPP_LUT103_OFFSET (0x79CU) +/* WIN1_BPP_LUT104 */ +#define VOP_WIN1_BPP_LUT104_OFFSET (0x7A0U) +/* WIN1_BPP_LUT105 */ +#define VOP_WIN1_BPP_LUT105_OFFSET (0x7A4U) +/* WIN1_BPP_LUT106 */ +#define VOP_WIN1_BPP_LUT106_OFFSET (0x7A8U) +/* WIN1_BPP_LUT107 */ +#define VOP_WIN1_BPP_LUT107_OFFSET (0x7ACU) +/* WIN1_BPP_LUT108 */ +#define VOP_WIN1_BPP_LUT108_OFFSET (0x7B0U) +/* WIN1_BPP_LUT109 */ +#define VOP_WIN1_BPP_LUT109_OFFSET (0x7B4U) +/* WIN1_BPP_LUT110 */ +#define VOP_WIN1_BPP_LUT110_OFFSET (0x7B8U) +/* WIN1_BPP_LUT111 */ +#define VOP_WIN1_BPP_LUT111_OFFSET (0x7BCU) +/* WIN1_BPP_LUT112 */ +#define VOP_WIN1_BPP_LUT112_OFFSET (0x7C0U) +/* WIN1_BPP_LUT113 */ +#define VOP_WIN1_BPP_LUT113_OFFSET (0x7C4U) +/* WIN1_BPP_LUT114 */ +#define VOP_WIN1_BPP_LUT114_OFFSET (0x7C8U) +/* WIN1_BPP_LUT115 */ +#define VOP_WIN1_BPP_LUT115_OFFSET (0x7CCU) +/* WIN1_BPP_LUT116 */ +#define VOP_WIN1_BPP_LUT116_OFFSET (0x7D0U) +/* WIN1_BPP_LUT117 */ +#define VOP_WIN1_BPP_LUT117_OFFSET (0x7D4U) +/* WIN1_BPP_LUT118 */ +#define VOP_WIN1_BPP_LUT118_OFFSET (0x7D8U) +/* WIN1_BPP_LUT119 */ +#define VOP_WIN1_BPP_LUT119_OFFSET (0x7DCU) +/* WIN1_BPP_LUT120 */ +#define VOP_WIN1_BPP_LUT120_OFFSET (0x7E0U) +/* WIN1_BPP_LUT121 */ +#define VOP_WIN1_BPP_LUT121_OFFSET (0x7E4U) +/* WIN1_BPP_LUT122 */ +#define VOP_WIN1_BPP_LUT122_OFFSET (0x7E8U) +/* WIN1_BPP_LUT123 */ +#define VOP_WIN1_BPP_LUT123_OFFSET (0x7ECU) +/* WIN1_BPP_LUT124 */ +#define VOP_WIN1_BPP_LUT124_OFFSET (0x7F0U) +/* WIN1_BPP_LUT125 */ +#define VOP_WIN1_BPP_LUT125_OFFSET (0x7F4U) +/* WIN1_BPP_LUT126 */ +#define VOP_WIN1_BPP_LUT126_OFFSET (0x7F8U) +/* WIN1_BPP_LUT127 */ +#define VOP_WIN1_BPP_LUT127_OFFSET (0x7FCU) +/* WIN1_BPP_LUT128 */ +#define VOP_WIN1_BPP_LUT128_OFFSET (0x800U) +/* WIN1_BPP_LUT129 */ +#define VOP_WIN1_BPP_LUT129_OFFSET (0x804U) +/* WIN1_BPP_LUT130 */ +#define VOP_WIN1_BPP_LUT130_OFFSET (0x808U) +/* WIN1_BPP_LUT131 */ +#define VOP_WIN1_BPP_LUT131_OFFSET (0x80CU) +/* WIN1_BPP_LUT132 */ +#define VOP_WIN1_BPP_LUT132_OFFSET (0x810U) +/* WIN1_BPP_LUT133 */ +#define VOP_WIN1_BPP_LUT133_OFFSET (0x814U) +/* WIN1_BPP_LUT134 */ +#define VOP_WIN1_BPP_LUT134_OFFSET (0x818U) +/* WIN1_BPP_LUT135 */ +#define VOP_WIN1_BPP_LUT135_OFFSET (0x81CU) +/* WIN1_BPP_LUT136 */ +#define VOP_WIN1_BPP_LUT136_OFFSET (0x820U) +/* WIN1_BPP_LUT137 */ +#define VOP_WIN1_BPP_LUT137_OFFSET (0x824U) +/* WIN1_BPP_LUT138 */ +#define VOP_WIN1_BPP_LUT138_OFFSET (0x828U) +/* WIN1_BPP_LUT139 */ +#define VOP_WIN1_BPP_LUT139_OFFSET (0x82CU) +/* WIN1_BPP_LUT140 */ +#define VOP_WIN1_BPP_LUT140_OFFSET (0x830U) +/* WIN1_BPP_LUT141 */ +#define VOP_WIN1_BPP_LUT141_OFFSET (0x834U) +/* WIN1_BPP_LUT142 */ +#define VOP_WIN1_BPP_LUT142_OFFSET (0x838U) +/* WIN1_BPP_LUT143 */ +#define VOP_WIN1_BPP_LUT143_OFFSET (0x83CU) +/* WIN1_BPP_LUT144 */ +#define VOP_WIN1_BPP_LUT144_OFFSET (0x840U) +/* WIN1_BPP_LUT145 */ +#define VOP_WIN1_BPP_LUT145_OFFSET (0x844U) +/* WIN1_BPP_LUT146 */ +#define VOP_WIN1_BPP_LUT146_OFFSET (0x848U) +/* WIN1_BPP_LUT147 */ +#define VOP_WIN1_BPP_LUT147_OFFSET (0x84CU) +/* WIN1_BPP_LUT148 */ +#define VOP_WIN1_BPP_LUT148_OFFSET (0x850U) +/* WIN1_BPP_LUT149 */ +#define VOP_WIN1_BPP_LUT149_OFFSET (0x854U) +/* WIN1_BPP_LUT150 */ +#define VOP_WIN1_BPP_LUT150_OFFSET (0x858U) +/* WIN1_BPP_LUT151 */ +#define VOP_WIN1_BPP_LUT151_OFFSET (0x85CU) +/* WIN1_BPP_LUT152 */ +#define VOP_WIN1_BPP_LUT152_OFFSET (0x860U) +/* WIN1_BPP_LUT153 */ +#define VOP_WIN1_BPP_LUT153_OFFSET (0x864U) +/* WIN1_BPP_LUT154 */ +#define VOP_WIN1_BPP_LUT154_OFFSET (0x868U) +/* WIN1_BPP_LUT155 */ +#define VOP_WIN1_BPP_LUT155_OFFSET (0x86CU) +/* WIN1_BPP_LUT156 */ +#define VOP_WIN1_BPP_LUT156_OFFSET (0x870U) +/* WIN1_BPP_LUT157 */ +#define VOP_WIN1_BPP_LUT157_OFFSET (0x874U) +/* WIN1_BPP_LUT158 */ +#define VOP_WIN1_BPP_LUT158_OFFSET (0x878U) +/* WIN1_BPP_LUT159 */ +#define VOP_WIN1_BPP_LUT159_OFFSET (0x87CU) +/* WIN1_BPP_LUT160 */ +#define VOP_WIN1_BPP_LUT160_OFFSET (0x880U) +/* WIN1_BPP_LUT161 */ +#define VOP_WIN1_BPP_LUT161_OFFSET (0x884U) +/* WIN1_BPP_LUT162 */ +#define VOP_WIN1_BPP_LUT162_OFFSET (0x888U) +/* WIN1_BPP_LUT163 */ +#define VOP_WIN1_BPP_LUT163_OFFSET (0x88CU) +/* WIN1_BPP_LUT164 */ +#define VOP_WIN1_BPP_LUT164_OFFSET (0x890U) +/* WIN1_BPP_LUT165 */ +#define VOP_WIN1_BPP_LUT165_OFFSET (0x894U) +/* WIN1_BPP_LUT166 */ +#define VOP_WIN1_BPP_LUT166_OFFSET (0x898U) +/* WIN1_BPP_LUT167 */ +#define VOP_WIN1_BPP_LUT167_OFFSET (0x89CU) +/* WIN1_BPP_LUT168 */ +#define VOP_WIN1_BPP_LUT168_OFFSET (0x8A0U) +/* WIN1_BPP_LUT169 */ +#define VOP_WIN1_BPP_LUT169_OFFSET (0x8A4U) +/* WIN1_BPP_LUT170 */ +#define VOP_WIN1_BPP_LUT170_OFFSET (0x8A8U) +/* WIN1_BPP_LUT171 */ +#define VOP_WIN1_BPP_LUT171_OFFSET (0x8ACU) +/* WIN1_BPP_LUT172 */ +#define VOP_WIN1_BPP_LUT172_OFFSET (0x8B0U) +/* WIN1_BPP_LUT173 */ +#define VOP_WIN1_BPP_LUT173_OFFSET (0x8B4U) +/* WIN1_BPP_LUT174 */ +#define VOP_WIN1_BPP_LUT174_OFFSET (0x8B8U) +/* WIN1_BPP_LUT175 */ +#define VOP_WIN1_BPP_LUT175_OFFSET (0x8BCU) +/* WIN1_BPP_LUT176 */ +#define VOP_WIN1_BPP_LUT176_OFFSET (0x8C0U) +/* WIN1_BPP_LUT177 */ +#define VOP_WIN1_BPP_LUT177_OFFSET (0x8C4U) +/* WIN1_BPP_LUT178 */ +#define VOP_WIN1_BPP_LUT178_OFFSET (0x8C8U) +/* WIN1_BPP_LUT179 */ +#define VOP_WIN1_BPP_LUT179_OFFSET (0x8CCU) +/* WIN1_BPP_LUT180 */ +#define VOP_WIN1_BPP_LUT180_OFFSET (0x8D0U) +/* WIN1_BPP_LUT181 */ +#define VOP_WIN1_BPP_LUT181_OFFSET (0x8D4U) +/* WIN1_BPP_LUT182 */ +#define VOP_WIN1_BPP_LUT182_OFFSET (0x8D8U) +/* WIN1_BPP_LUT183 */ +#define VOP_WIN1_BPP_LUT183_OFFSET (0x8DCU) +/* WIN1_BPP_LUT184 */ +#define VOP_WIN1_BPP_LUT184_OFFSET (0x8E0U) +/* WIN1_BPP_LUT185 */ +#define VOP_WIN1_BPP_LUT185_OFFSET (0x8E4U) +/* WIN1_BPP_LUT186 */ +#define VOP_WIN1_BPP_LUT186_OFFSET (0x8E8U) +/* WIN1_BPP_LUT187 */ +#define VOP_WIN1_BPP_LUT187_OFFSET (0x8ECU) +/* WIN1_BPP_LUT188 */ +#define VOP_WIN1_BPP_LUT188_OFFSET (0x8F0U) +/* WIN1_BPP_LUT189 */ +#define VOP_WIN1_BPP_LUT189_OFFSET (0x8F4U) +/* WIN1_BPP_LUT190 */ +#define VOP_WIN1_BPP_LUT190_OFFSET (0x8F8U) +/* WIN1_BPP_LUT191 */ +#define VOP_WIN1_BPP_LUT191_OFFSET (0x8FCU) +/* WIN1_BPP_LUT192 */ +#define VOP_WIN1_BPP_LUT192_OFFSET (0x900U) +/* WIN1_BPP_LUT193 */ +#define VOP_WIN1_BPP_LUT193_OFFSET (0x904U) +/* WIN1_BPP_LUT194 */ +#define VOP_WIN1_BPP_LUT194_OFFSET (0x908U) +/* WIN1_BPP_LUT195 */ +#define VOP_WIN1_BPP_LUT195_OFFSET (0x90CU) +/* WIN1_BPP_LUT196 */ +#define VOP_WIN1_BPP_LUT196_OFFSET (0x910U) +/* WIN1_BPP_LUT197 */ +#define VOP_WIN1_BPP_LUT197_OFFSET (0x914U) +/* WIN1_BPP_LUT198 */ +#define VOP_WIN1_BPP_LUT198_OFFSET (0x918U) +/* WIN1_BPP_LUT199 */ +#define VOP_WIN1_BPP_LUT199_OFFSET (0x91CU) +/* WIN1_BPP_LUT200 */ +#define VOP_WIN1_BPP_LUT200_OFFSET (0x920U) +/* WIN1_BPP_LUT201 */ +#define VOP_WIN1_BPP_LUT201_OFFSET (0x924U) +/* WIN1_BPP_LUT202 */ +#define VOP_WIN1_BPP_LUT202_OFFSET (0x928U) +/* WIN1_BPP_LUT203 */ +#define VOP_WIN1_BPP_LUT203_OFFSET (0x92CU) +/* WIN1_BPP_LUT204 */ +#define VOP_WIN1_BPP_LUT204_OFFSET (0x930U) +/* WIN1_BPP_LUT205 */ +#define VOP_WIN1_BPP_LUT205_OFFSET (0x934U) +/* WIN1_BPP_LUT206 */ +#define VOP_WIN1_BPP_LUT206_OFFSET (0x938U) +/* WIN1_BPP_LUT207 */ +#define VOP_WIN1_BPP_LUT207_OFFSET (0x93CU) +/* WIN1_BPP_LUT208 */ +#define VOP_WIN1_BPP_LUT208_OFFSET (0x940U) +/* WIN1_BPP_LUT209 */ +#define VOP_WIN1_BPP_LUT209_OFFSET (0x944U) +/* WIN1_BPP_LUT210 */ +#define VOP_WIN1_BPP_LUT210_OFFSET (0x948U) +/* WIN1_BPP_LUT211 */ +#define VOP_WIN1_BPP_LUT211_OFFSET (0x94CU) +/* WIN1_BPP_LUT212 */ +#define VOP_WIN1_BPP_LUT212_OFFSET (0x950U) +/* WIN1_BPP_LUT213 */ +#define VOP_WIN1_BPP_LUT213_OFFSET (0x954U) +/* WIN1_BPP_LUT214 */ +#define VOP_WIN1_BPP_LUT214_OFFSET (0x958U) +/* WIN1_BPP_LUT215 */ +#define VOP_WIN1_BPP_LUT215_OFFSET (0x95CU) +/* WIN1_BPP_LUT216 */ +#define VOP_WIN1_BPP_LUT216_OFFSET (0x960U) +/* WIN1_BPP_LUT217 */ +#define VOP_WIN1_BPP_LUT217_OFFSET (0x964U) +/* WIN1_BPP_LUT218 */ +#define VOP_WIN1_BPP_LUT218_OFFSET (0x968U) +/* WIN1_BPP_LUT219 */ +#define VOP_WIN1_BPP_LUT219_OFFSET (0x96CU) +/* WIN1_BPP_LUT220 */ +#define VOP_WIN1_BPP_LUT220_OFFSET (0x970U) +/* WIN1_BPP_LUT221 */ +#define VOP_WIN1_BPP_LUT221_OFFSET (0x974U) +/* WIN1_BPP_LUT222 */ +#define VOP_WIN1_BPP_LUT222_OFFSET (0x978U) +/* WIN1_BPP_LUT223 */ +#define VOP_WIN1_BPP_LUT223_OFFSET (0x97CU) +/* WIN1_BPP_LUT224 */ +#define VOP_WIN1_BPP_LUT224_OFFSET (0x980U) +/* WIN1_BPP_LUT225 */ +#define VOP_WIN1_BPP_LUT225_OFFSET (0x984U) +/* WIN1_BPP_LUT226 */ +#define VOP_WIN1_BPP_LUT226_OFFSET (0x988U) +/* WIN1_BPP_LUT227 */ +#define VOP_WIN1_BPP_LUT227_OFFSET (0x98CU) +/* WIN1_BPP_LUT228 */ +#define VOP_WIN1_BPP_LUT228_OFFSET (0x990U) +/* WIN1_BPP_LUT229 */ +#define VOP_WIN1_BPP_LUT229_OFFSET (0x994U) +/* WIN1_BPP_LUT230 */ +#define VOP_WIN1_BPP_LUT230_OFFSET (0x998U) +/* WIN1_BPP_LUT231 */ +#define VOP_WIN1_BPP_LUT231_OFFSET (0x99CU) +/* WIN1_BPP_LUT232 */ +#define VOP_WIN1_BPP_LUT232_OFFSET (0x9A0U) +/* WIN1_BPP_LUT233 */ +#define VOP_WIN1_BPP_LUT233_OFFSET (0x9A4U) +/* WIN1_BPP_LUT234 */ +#define VOP_WIN1_BPP_LUT234_OFFSET (0x9A8U) +/* WIN1_BPP_LUT235 */ +#define VOP_WIN1_BPP_LUT235_OFFSET (0x9ACU) +/* WIN1_BPP_LUT236 */ +#define VOP_WIN1_BPP_LUT236_OFFSET (0x9B0U) +/* WIN1_BPP_LUT237 */ +#define VOP_WIN1_BPP_LUT237_OFFSET (0x9B4U) +/* WIN1_BPP_LUT238 */ +#define VOP_WIN1_BPP_LUT238_OFFSET (0x9B8U) +/* WIN1_BPP_LUT239 */ +#define VOP_WIN1_BPP_LUT239_OFFSET (0x9BCU) +/* WIN1_BPP_LUT240 */ +#define VOP_WIN1_BPP_LUT240_OFFSET (0x9C0U) +/* WIN1_BPP_LUT241 */ +#define VOP_WIN1_BPP_LUT241_OFFSET (0x9C4U) +/* WIN1_BPP_LUT242 */ +#define VOP_WIN1_BPP_LUT242_OFFSET (0x9C8U) +/* WIN1_BPP_LUT243 */ +#define VOP_WIN1_BPP_LUT243_OFFSET (0x9CCU) +/* WIN1_BPP_LUT244 */ +#define VOP_WIN1_BPP_LUT244_OFFSET (0x9D0U) +/* WIN1_BPP_LUT245 */ +#define VOP_WIN1_BPP_LUT245_OFFSET (0x9D4U) +/* WIN1_BPP_LUT246 */ +#define VOP_WIN1_BPP_LUT246_OFFSET (0x9D8U) +/* WIN1_BPP_LUT247 */ +#define VOP_WIN1_BPP_LUT247_OFFSET (0x9DCU) +/* WIN1_BPP_LUT248 */ +#define VOP_WIN1_BPP_LUT248_OFFSET (0x9E0U) +/* WIN1_BPP_LUT249 */ +#define VOP_WIN1_BPP_LUT249_OFFSET (0x9E4U) +/* WIN1_BPP_LUT250 */ +#define VOP_WIN1_BPP_LUT250_OFFSET (0x9E8U) +/* WIN1_BPP_LUT251 */ +#define VOP_WIN1_BPP_LUT251_OFFSET (0x9ECU) +/* WIN1_BPP_LUT252 */ +#define VOP_WIN1_BPP_LUT252_OFFSET (0x9F0U) +/* WIN1_BPP_LUT253 */ +#define VOP_WIN1_BPP_LUT253_OFFSET (0x9F4U) +/* WIN1_BPP_LUT254 */ +#define VOP_WIN1_BPP_LUT254_OFFSET (0x9F8U) +/* WIN1_BPP_LUT255 */ +#define VOP_WIN1_BPP_LUT255_OFFSET (0x9FCU) +/* DSC_SYS_CTRL0_IMD */ +#define VOP_DSC_SYS_CTRL0_IMD_OFFSET (0xA00U) +#define VOP_DSC_SYS_CTRL0_IMD_DSC_CONFIG_EN_SHIFT (0U) +#define VOP_DSC_SYS_CTRL0_IMD_DSC_CONFIG_EN_MASK (0x1U << VOP_DSC_SYS_CTRL0_IMD_DSC_CONFIG_EN_SHIFT) /* 0x00000001 */ +#define VOP_DSC_SYS_CTRL0_IMD_DSC_IMD_CONFIG_EN_SHIFT (4U) +#define VOP_DSC_SYS_CTRL0_IMD_DSC_IMD_CONFIG_EN_MASK (0x1U << VOP_DSC_SYS_CTRL0_IMD_DSC_IMD_CONFIG_EN_SHIFT) /* 0x00000010 */ +#define VOP_DSC_SYS_CTRL0_IMD_DSC_MEM_GATING_EN_SHIFT (8U) +#define VOP_DSC_SYS_CTRL0_IMD_DSC_MEM_GATING_EN_MASK (0x1U << VOP_DSC_SYS_CTRL0_IMD_DSC_MEM_GATING_EN_SHIFT) /* 0x00000100 */ +#define VOP_DSC_SYS_CTRL0_IMD_DSC_SOFT_RST_SHIFT (12U) +#define VOP_DSC_SYS_CTRL0_IMD_DSC_SOFT_RST_MASK (0x1U << VOP_DSC_SYS_CTRL0_IMD_DSC_SOFT_RST_SHIFT) /* 0x00001000 */ +/* DSC_SYS_CTRL1 */ +#define VOP_DSC_SYS_CTRL1_OFFSET (0xA04U) +#define VOP_DSC_SYS_CTRL1_DSI_HALT_EN_SHIFT (0U) +#define VOP_DSC_SYS_CTRL1_DSI_HALT_EN_MASK (0x1U << VOP_DSC_SYS_CTRL1_DSI_HALT_EN_SHIFT) /* 0x00000001 */ +#define VOP_DSC_SYS_CTRL1_DSC_REQ_OUT_EN_SHIFT (1U) +#define VOP_DSC_SYS_CTRL1_DSC_REQ_OUT_EN_MASK (0x1U << VOP_DSC_SYS_CTRL1_DSC_REQ_OUT_EN_SHIFT) /* 0x00000002 */ +#define VOP_DSC_SYS_CTRL1_DSC_MUTIPLEX_EOC_EN_SHIFT (2U) +#define VOP_DSC_SYS_CTRL1_DSC_MUTIPLEX_EOC_EN_MASK (0x1U << VOP_DSC_SYS_CTRL1_DSC_MUTIPLEX_EOC_EN_SHIFT) /* 0x00000004 */ +#define VOP_DSC_SYS_CTRL1_DSC_VIDEO_MODE_SHIFT (3U) +#define VOP_DSC_SYS_CTRL1_DSC_VIDEO_MODE_MASK (0x1U << VOP_DSC_SYS_CTRL1_DSC_VIDEO_MODE_SHIFT) /* 0x00000008 */ +#define VOP_DSC_SYS_CTRL1_DSC_ICH_RST_MANUAL_VALUE_SHIFT (4U) +#define VOP_DSC_SYS_CTRL1_DSC_ICH_RST_MANUAL_VALUE_MASK (0x1U << VOP_DSC_SYS_CTRL1_DSC_ICH_RST_MANUAL_VALUE_SHIFT) /* 0x00000010 */ +#define VOP_DSC_SYS_CTRL1_DSC_ICH_RST_MANUAL_MODE_SHIFT (5U) +#define VOP_DSC_SYS_CTRL1_DSC_ICH_RST_MANUAL_MODE_MASK (0x1U << VOP_DSC_SYS_CTRL1_DSC_ICH_RST_MANUAL_MODE_SHIFT) /* 0x00000020 */ +#define VOP_DSC_SYS_CTRL1_DSC_ICH_DISABLE_SHIFT (6U) +#define VOP_DSC_SYS_CTRL1_DSC_ICH_DISABLE_MASK (0x1U << VOP_DSC_SYS_CTRL1_DSC_ICH_DISABLE_SHIFT) /* 0x00000040 */ +#define VOP_DSC_SYS_CTRL1_DSC_FULL_ICH_ERR_PRECISION_SHIFT (7U) +#define VOP_DSC_SYS_CTRL1_DSC_FULL_ICH_ERR_PRECISION_MASK (0x1U << VOP_DSC_SYS_CTRL1_DSC_FULL_ICH_ERR_PRECISION_SHIFT) /* 0x00000080 */ +#define VOP_DSC_SYS_CTRL1_DSC_INT_CLR_TRIG_SHIFT (8U) +#define VOP_DSC_SYS_CTRL1_DSC_INT_CLR_TRIG_MASK (0x1U << VOP_DSC_SYS_CTRL1_DSC_INT_CLR_TRIG_SHIFT) /* 0x00000100 */ +#define VOP_DSC_SYS_CTRL1_WORD_SWAP_SHIFT (12U) +#define VOP_DSC_SYS_CTRL1_WORD_SWAP_MASK (0x1U << VOP_DSC_SYS_CTRL1_WORD_SWAP_SHIFT) /* 0x00001000 */ +#define VOP_DSC_SYS_CTRL1_HI_LO_BYTE_SWAP_SHIFT (13U) +#define VOP_DSC_SYS_CTRL1_HI_LO_BYTE_SWAP_MASK (0x1U << VOP_DSC_SYS_CTRL1_HI_LO_BYTE_SWAP_SHIFT) /* 0x00002000 */ +#define VOP_DSC_SYS_CTRL1_DSC_OUTPUT_DELAY_PERI_SHIFT (16U) +#define VOP_DSC_SYS_CTRL1_DSC_OUTPUT_DELAY_PERI_MASK (0xFFFFU << VOP_DSC_SYS_CTRL1_DSC_OUTPUT_DELAY_PERI_SHIFT) /* 0xFFFF0000 */ +/* DSC_SYS_CTRL2 */ +#define VOP_DSC_SYS_CTRL2_OFFSET (0xA08U) +#define VOP_DSC_SYS_CTRL2_DSC_INITIAL_LINES_SHIFT (0U) +#define VOP_DSC_SYS_CTRL2_DSC_INITIAL_LINES_MASK (0xFFU << VOP_DSC_SYS_CTRL2_DSC_INITIAL_LINES_SHIFT) /* 0x000000FF */ +#define VOP_DSC_SYS_CTRL2_DSC_OUTPUT_DELAY_EN_SHIFT (8U) +#define VOP_DSC_SYS_CTRL2_DSC_OUTPUT_DELAY_EN_MASK (0x1U << VOP_DSC_SYS_CTRL2_DSC_OUTPUT_DELAY_EN_SHIFT) /* 0x00000100 */ +#define VOP_DSC_SYS_CTRL2_DSC_OUTPUT_DELAY_INIT_SHIFT (16U) +#define VOP_DSC_SYS_CTRL2_DSC_OUTPUT_DELAY_INIT_MASK (0xFFFFU << VOP_DSC_SYS_CTRL2_DSC_OUTPUT_DELAY_INIT_SHIFT) /* 0xFFFF0000 */ +/* DSC_SYS_CTRL3 */ +#define VOP_DSC_SYS_CTRL3_OFFSET (0xA0CU) +#define VOP_DSC_SYS_CTRL3_DSC_OB_MAX_ADDR_SHIFT (0U) +#define VOP_DSC_SYS_CTRL3_DSC_OB_MAX_ADDR_MASK (0x3FFFU << VOP_DSC_SYS_CTRL3_DSC_OB_MAX_ADDR_SHIFT) /* 0x00003FFF */ +/* DSC_CFG0 */ +#define VOP_DSC_CFG0_OFFSET (0xA10U) +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET0_SHIFT (0U) +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET0_MASK (0x3FU << VOP_DSC_CFG0_RANGE_BPG_OFFSET0_SHIFT) /* 0x0000003F */ +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET1_SHIFT (6U) +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET1_MASK (0x3FU << VOP_DSC_CFG0_RANGE_BPG_OFFSET1_SHIFT) /* 0x00000FC0 */ +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET2_SHIFT (12U) +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET2_MASK (0x3FU << VOP_DSC_CFG0_RANGE_BPG_OFFSET2_SHIFT) /* 0x0003F000 */ +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET3_SHIFT (18U) +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET3_MASK (0x3FU << VOP_DSC_CFG0_RANGE_BPG_OFFSET3_SHIFT) /* 0x00FC0000 */ +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET4_SHIFT (24U) +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET4_MASK (0x3FU << VOP_DSC_CFG0_RANGE_BPG_OFFSET4_SHIFT) /* 0x3F000000 */ +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET5_LO_SHIFT (30U) +#define VOP_DSC_CFG0_RANGE_BPG_OFFSET5_LO_MASK (0x3U << VOP_DSC_CFG0_RANGE_BPG_OFFSET5_LO_SHIFT) /* 0xC0000000 */ +/* DSC_CFG1 */ +#define VOP_DSC_CFG1_OFFSET (0xA14U) +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET5_HI_SHIFT (0U) +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET5_HI_MASK (0xFU << VOP_DSC_CFG1_RANGE_BPG_OFFSET5_HI_SHIFT) /* 0x0000000F */ +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET6_SHIFT (4U) +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET6_MASK (0x3FU << VOP_DSC_CFG1_RANGE_BPG_OFFSET6_SHIFT) /* 0x000003F0 */ +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET7_SHIFT (10U) +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET7_MASK (0x3FU << VOP_DSC_CFG1_RANGE_BPG_OFFSET7_SHIFT) /* 0x0000FC00 */ +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET8_SHIFT (16U) +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET8_MASK (0x3FU << VOP_DSC_CFG1_RANGE_BPG_OFFSET8_SHIFT) /* 0x003F0000 */ +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET9_SHIFT (22U) +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET9_MASK (0x3FU << VOP_DSC_CFG1_RANGE_BPG_OFFSET9_SHIFT) /* 0x0FC00000 */ +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET10_LO_SHIFT (28U) +#define VOP_DSC_CFG1_RANGE_BPG_OFFSET10_LO_MASK (0xFU << VOP_DSC_CFG1_RANGE_BPG_OFFSET10_LO_SHIFT) /* 0xF0000000 */ +/* DSC_CFG2 */ +#define VOP_DSC_CFG2_OFFSET (0xA18U) +#define VOP_DSC_CFG2_RANGE_BPG_OFFSET10_HI_SHIFT (0U) +#define VOP_DSC_CFG2_RANGE_BPG_OFFSET10_HI_MASK (0x3U << VOP_DSC_CFG2_RANGE_BPG_OFFSET10_HI_SHIFT) /* 0x00000003 */ +#define VOP_DSC_CFG2_RANGE_BPG_OFFSET11_SHIFT (2U) +#define VOP_DSC_CFG2_RANGE_BPG_OFFSET11_MASK (0x3FU << VOP_DSC_CFG2_RANGE_BPG_OFFSET11_SHIFT) /* 0x000000FC */ +#define VOP_DSC_CFG2_RANGE_BPG_OFFSET12_SHIFT (8U) +#define VOP_DSC_CFG2_RANGE_BPG_OFFSET12_MASK (0x3FU << VOP_DSC_CFG2_RANGE_BPG_OFFSET12_SHIFT) /* 0x00003F00 */ +#define VOP_DSC_CFG2_RANGE_BPG_OFFSET13_SHIFT (14U) +#define VOP_DSC_CFG2_RANGE_BPG_OFFSET13_MASK (0x3FU << VOP_DSC_CFG2_RANGE_BPG_OFFSET13_SHIFT) /* 0x000FC000 */ +#define VOP_DSC_CFG2_RANGE_BPG_OFFSET14_SHIFT (20U) +#define VOP_DSC_CFG2_RANGE_BPG_OFFSET14_MASK (0x3FU << VOP_DSC_CFG2_RANGE_BPG_OFFSET14_SHIFT) /* 0x03F00000 */ +#define VOP_DSC_CFG2_RANGE_MAX_QP0_SHIFT (26U) +#define VOP_DSC_CFG2_RANGE_MAX_QP0_MASK (0x1FU << VOP_DSC_CFG2_RANGE_MAX_QP0_SHIFT) /* 0x7C000000 */ +#define VOP_DSC_CFG2_RANGE_MAX_QP1_LO_SHIFT (31U) +#define VOP_DSC_CFG2_RANGE_MAX_QP1_LO_MASK (0x1U << VOP_DSC_CFG2_RANGE_MAX_QP1_LO_SHIFT) /* 0x80000000 */ +/* DSC_CFG3 */ +#define VOP_DSC_CFG3_OFFSET (0xA1CU) +#define VOP_DSC_CFG3_RANGE_MAX_QP1_HI_SHIFT (0U) +#define VOP_DSC_CFG3_RANGE_MAX_QP1_HI_MASK (0xFU << VOP_DSC_CFG3_RANGE_MAX_QP1_HI_SHIFT) /* 0x0000000F */ +#define VOP_DSC_CFG3_RANGE_MAX_QP2_SHIFT (4U) +#define VOP_DSC_CFG3_RANGE_MAX_QP2_MASK (0x1FU << VOP_DSC_CFG3_RANGE_MAX_QP2_SHIFT) /* 0x000001F0 */ +#define VOP_DSC_CFG3_RANGE_MAX_QP3_SHIFT (9U) +#define VOP_DSC_CFG3_RANGE_MAX_QP3_MASK (0x1FU << VOP_DSC_CFG3_RANGE_MAX_QP3_SHIFT) /* 0x00003E00 */ +#define VOP_DSC_CFG3_RANGE_MAX_QP4_SHIFT (14U) +#define VOP_DSC_CFG3_RANGE_MAX_QP4_MASK (0x1FU << VOP_DSC_CFG3_RANGE_MAX_QP4_SHIFT) /* 0x0007C000 */ +#define VOP_DSC_CFG3_RANGE_MAX_QP5_SHIFT (19U) +#define VOP_DSC_CFG3_RANGE_MAX_QP5_MASK (0x1FU << VOP_DSC_CFG3_RANGE_MAX_QP5_SHIFT) /* 0x00F80000 */ +#define VOP_DSC_CFG3_RANGE_MAX_QP6_SHIFT (24U) +#define VOP_DSC_CFG3_RANGE_MAX_QP6_MASK (0x1FU << VOP_DSC_CFG3_RANGE_MAX_QP6_SHIFT) /* 0x1F000000 */ +#define VOP_DSC_CFG3_RANGE_MAX_QP7_LO_SHIFT (29U) +#define VOP_DSC_CFG3_RANGE_MAX_QP7_LO_MASK (0x7U << VOP_DSC_CFG3_RANGE_MAX_QP7_LO_SHIFT) /* 0xE0000000 */ +/* DSC_CFG4 */ +#define VOP_DSC_CFG4_OFFSET (0xA20U) +#define VOP_DSC_CFG4_RANGE_MAX_QP7_HI_SHIFT (0U) +#define VOP_DSC_CFG4_RANGE_MAX_QP7_HI_MASK (0x3U << VOP_DSC_CFG4_RANGE_MAX_QP7_HI_SHIFT) /* 0x00000003 */ +#define VOP_DSC_CFG4_RANGE_MAX_QP8_SHIFT (2U) +#define VOP_DSC_CFG4_RANGE_MAX_QP8_MASK (0x1FU << VOP_DSC_CFG4_RANGE_MAX_QP8_SHIFT) /* 0x0000007C */ +#define VOP_DSC_CFG4_RANGE_MAX_QP9_SHIFT (7U) +#define VOP_DSC_CFG4_RANGE_MAX_QP9_MASK (0x1FU << VOP_DSC_CFG4_RANGE_MAX_QP9_SHIFT) /* 0x00000F80 */ +#define VOP_DSC_CFG4_RANGE_MAX_QP10_SHIFT (12U) +#define VOP_DSC_CFG4_RANGE_MAX_QP10_MASK (0x1FU << VOP_DSC_CFG4_RANGE_MAX_QP10_SHIFT) /* 0x0001F000 */ +#define VOP_DSC_CFG4_RANGE_MAX_QP11_SHIFT (17U) +#define VOP_DSC_CFG4_RANGE_MAX_QP11_MASK (0x1FU << VOP_DSC_CFG4_RANGE_MAX_QP11_SHIFT) /* 0x003E0000 */ +#define VOP_DSC_CFG4_RANGE_MAX_QP12_SHIFT (22U) +#define VOP_DSC_CFG4_RANGE_MAX_QP12_MASK (0x1FU << VOP_DSC_CFG4_RANGE_MAX_QP12_SHIFT) /* 0x07C00000 */ +#define VOP_DSC_CFG4_RANGE_MAX_QP13_SHIFT (27U) +#define VOP_DSC_CFG4_RANGE_MAX_QP13_MASK (0x1FU << VOP_DSC_CFG4_RANGE_MAX_QP13_SHIFT) /* 0xF8000000 */ +/* DSC_CFG5 */ +#define VOP_DSC_CFG5_OFFSET (0xA24U) +#define VOP_DSC_CFG5_RANGE_MAX_QP14_SHIFT (0U) +#define VOP_DSC_CFG5_RANGE_MAX_QP14_MASK (0x1FU << VOP_DSC_CFG5_RANGE_MAX_QP14_SHIFT) /* 0x0000001F */ +#define VOP_DSC_CFG5_RANGE_MIN_QP0_SHIFT (5U) +#define VOP_DSC_CFG5_RANGE_MIN_QP0_MASK (0x1FU << VOP_DSC_CFG5_RANGE_MIN_QP0_SHIFT) /* 0x000003E0 */ +#define VOP_DSC_CFG5_RANGE_MIN_QP1_SHIFT (10U) +#define VOP_DSC_CFG5_RANGE_MIN_QP1_MASK (0x1FU << VOP_DSC_CFG5_RANGE_MIN_QP1_SHIFT) /* 0x00007C00 */ +#define VOP_DSC_CFG5_RANGE_MIN_QP2_SHIFT (15U) +#define VOP_DSC_CFG5_RANGE_MIN_QP2_MASK (0x1FU << VOP_DSC_CFG5_RANGE_MIN_QP2_SHIFT) /* 0x000F8000 */ +#define VOP_DSC_CFG5_RANGE_MIN_QP3_SHIFT (20U) +#define VOP_DSC_CFG5_RANGE_MIN_QP3_MASK (0x1FU << VOP_DSC_CFG5_RANGE_MIN_QP3_SHIFT) /* 0x01F00000 */ +#define VOP_DSC_CFG5_RANGE_MIN_QP4_SHIFT (25U) +#define VOP_DSC_CFG5_RANGE_MIN_QP4_MASK (0x1FU << VOP_DSC_CFG5_RANGE_MIN_QP4_SHIFT) /* 0x3E000000 */ +#define VOP_DSC_CFG5_RANGE_MIN_QP5_LO_SHIFT (30U) +#define VOP_DSC_CFG5_RANGE_MIN_QP5_LO_MASK (0x3U << VOP_DSC_CFG5_RANGE_MIN_QP5_LO_SHIFT) /* 0xC0000000 */ +/* DSC_CFG6 */ +#define VOP_DSC_CFG6_OFFSET (0xA28U) +#define VOP_DSC_CFG6_RANGE_MIN_QP5_HI_SHIFT (0U) +#define VOP_DSC_CFG6_RANGE_MIN_QP5_HI_MASK (0x7U << VOP_DSC_CFG6_RANGE_MIN_QP5_HI_SHIFT) /* 0x00000007 */ +#define VOP_DSC_CFG6_RANGE_MIN_QP6_SHIFT (3U) +#define VOP_DSC_CFG6_RANGE_MIN_QP6_MASK (0x1FU << VOP_DSC_CFG6_RANGE_MIN_QP6_SHIFT) /* 0x000000F8 */ +#define VOP_DSC_CFG6_RANGE_MIN_QP7_SHIFT (8U) +#define VOP_DSC_CFG6_RANGE_MIN_QP7_MASK (0x1FU << VOP_DSC_CFG6_RANGE_MIN_QP7_SHIFT) /* 0x00001F00 */ +#define VOP_DSC_CFG6_RANGE_MIN_QP8_SHIFT (13U) +#define VOP_DSC_CFG6_RANGE_MIN_QP8_MASK (0x1FU << VOP_DSC_CFG6_RANGE_MIN_QP8_SHIFT) /* 0x0003E000 */ +#define VOP_DSC_CFG6_RANGE_MIN_QP9_SHIFT (18U) +#define VOP_DSC_CFG6_RANGE_MIN_QP9_MASK (0x1FU << VOP_DSC_CFG6_RANGE_MIN_QP9_SHIFT) /* 0x007C0000 */ +#define VOP_DSC_CFG6_RANGE_MIN_QP10_SHIFT (23U) +#define VOP_DSC_CFG6_RANGE_MIN_QP10_MASK (0x1FU << VOP_DSC_CFG6_RANGE_MIN_QP10_SHIFT) /* 0x0F800000 */ +#define VOP_DSC_CFG6_RANGE_MIN_QP11_LO_SHIFT (28U) +#define VOP_DSC_CFG6_RANGE_MIN_QP11_LO_MASK (0xFU << VOP_DSC_CFG6_RANGE_MIN_QP11_LO_SHIFT) /* 0xF0000000 */ +/* DSC_CFG7 */ +#define VOP_DSC_CFG7_OFFSET (0xA2CU) +#define VOP_DSC_CFG7_RANGE_MIN_QP11_HI_SHIFT (0U) +#define VOP_DSC_CFG7_RANGE_MIN_QP11_HI_MASK (0x1U << VOP_DSC_CFG7_RANGE_MIN_QP11_HI_SHIFT) /* 0x00000001 */ +#define VOP_DSC_CFG7_RANGE_MIN_QP12_SHIFT (1U) +#define VOP_DSC_CFG7_RANGE_MIN_QP12_MASK (0x1FU << VOP_DSC_CFG7_RANGE_MIN_QP12_SHIFT) /* 0x0000003E */ +#define VOP_DSC_CFG7_RANGE_MIN_QP13_SHIFT (6U) +#define VOP_DSC_CFG7_RANGE_MIN_QP13_MASK (0x1FU << VOP_DSC_CFG7_RANGE_MIN_QP13_SHIFT) /* 0x000007C0 */ +#define VOP_DSC_CFG7_RANGE_MIN_QP14_SHIFT (11U) +#define VOP_DSC_CFG7_RANGE_MIN_QP14_MASK (0x1FU << VOP_DSC_CFG7_RANGE_MIN_QP14_SHIFT) /* 0x0000F800 */ +#define VOP_DSC_CFG7_RC_BUF_THRESH0_SHIFT (16U) +#define VOP_DSC_CFG7_RC_BUF_THRESH0_MASK (0xFFU << VOP_DSC_CFG7_RC_BUF_THRESH0_SHIFT) /* 0x00FF0000 */ +#define VOP_DSC_CFG7_RC_BUF_THRESH1_SHIFT (24U) +#define VOP_DSC_CFG7_RC_BUF_THRESH1_MASK (0xFFU << VOP_DSC_CFG7_RC_BUF_THRESH1_SHIFT) /* 0xFF000000 */ +/* DSC_CFG8 */ +#define VOP_DSC_CFG8_OFFSET (0xA30U) +#define VOP_DSC_CFG8_RC_BUF_THRESH2_SHIFT (0U) +#define VOP_DSC_CFG8_RC_BUF_THRESH2_MASK (0xFFU << VOP_DSC_CFG8_RC_BUF_THRESH2_SHIFT) /* 0x000000FF */ +#define VOP_DSC_CFG8_RC_BUF_THRESH3_SHIFT (8U) +#define VOP_DSC_CFG8_RC_BUF_THRESH3_MASK (0xFFU << VOP_DSC_CFG8_RC_BUF_THRESH3_SHIFT) /* 0x0000FF00 */ +#define VOP_DSC_CFG8_RC_BUF_THRESH4_SHIFT (16U) +#define VOP_DSC_CFG8_RC_BUF_THRESH4_MASK (0xFFU << VOP_DSC_CFG8_RC_BUF_THRESH4_SHIFT) /* 0x00FF0000 */ +#define VOP_DSC_CFG8_RC_BUF_THRESH5_SHIFT (24U) +#define VOP_DSC_CFG8_RC_BUF_THRESH5_MASK (0xFFU << VOP_DSC_CFG8_RC_BUF_THRESH5_SHIFT) /* 0xFF000000 */ +/* DSC_CFG9 */ +#define VOP_DSC_CFG9_OFFSET (0xA34U) +#define VOP_DSC_CFG9_RC_BUF_THRESH6_SHIFT (0U) +#define VOP_DSC_CFG9_RC_BUF_THRESH6_MASK (0xFFU << VOP_DSC_CFG9_RC_BUF_THRESH6_SHIFT) /* 0x000000FF */ +#define VOP_DSC_CFG9_RC_BUF_THRESH7_SHIFT (8U) +#define VOP_DSC_CFG9_RC_BUF_THRESH7_MASK (0xFFU << VOP_DSC_CFG9_RC_BUF_THRESH7_SHIFT) /* 0x0000FF00 */ +#define VOP_DSC_CFG9_RC_BUF_THRESH8_SHIFT (16U) +#define VOP_DSC_CFG9_RC_BUF_THRESH8_MASK (0xFFU << VOP_DSC_CFG9_RC_BUF_THRESH8_SHIFT) /* 0x00FF0000 */ +#define VOP_DSC_CFG9_RC_BUF_THRESH9_SHIFT (24U) +#define VOP_DSC_CFG9_RC_BUF_THRESH9_MASK (0xFFU << VOP_DSC_CFG9_RC_BUF_THRESH9_SHIFT) /* 0xFF000000 */ +/* DSC_CFG10 */ +#define VOP_DSC_CFG10_OFFSET (0xA38U) +#define VOP_DSC_CFG10_RC_BUF_THRESH10_SHIFT (0U) +#define VOP_DSC_CFG10_RC_BUF_THRESH10_MASK (0xFFU << VOP_DSC_CFG10_RC_BUF_THRESH10_SHIFT) /* 0x000000FF */ +#define VOP_DSC_CFG10_RC_BUF_THRESH11_SHIFT (8U) +#define VOP_DSC_CFG10_RC_BUF_THRESH11_MASK (0xFFU << VOP_DSC_CFG10_RC_BUF_THRESH11_SHIFT) /* 0x0000FF00 */ +#define VOP_DSC_CFG10_RC_BUF_THRESH12_SHIFT (16U) +#define VOP_DSC_CFG10_RC_BUF_THRESH12_MASK (0xFFU << VOP_DSC_CFG10_RC_BUF_THRESH12_SHIFT) /* 0x00FF0000 */ +#define VOP_DSC_CFG10_RC_BUF_THRESH13_SHIFT (24U) +#define VOP_DSC_CFG10_RC_BUF_THRESH13_MASK (0xFFU << VOP_DSC_CFG10_RC_BUF_THRESH13_SHIFT) /* 0xFF000000 */ +/* DSC_CFG11 */ +#define VOP_DSC_CFG11_OFFSET (0xA3CU) +#define VOP_DSC_CFG11_RC_TGT_OFFSET_LO_SHIFT (0U) +#define VOP_DSC_CFG11_RC_TGT_OFFSET_LO_MASK (0xFU << VOP_DSC_CFG11_RC_TGT_OFFSET_LO_SHIFT) /* 0x0000000F */ +#define VOP_DSC_CFG11_RC_TGT_OFFSET_HI_SHIFT (4U) +#define VOP_DSC_CFG11_RC_TGT_OFFSET_HI_MASK (0xFU << VOP_DSC_CFG11_RC_TGT_OFFSET_HI_SHIFT) /* 0x000000F0 */ +#define VOP_DSC_CFG11_RC_QUANT_INCR_LIMIT1_SHIFT (8U) +#define VOP_DSC_CFG11_RC_QUANT_INCR_LIMIT1_MASK (0x1FU << VOP_DSC_CFG11_RC_QUANT_INCR_LIMIT1_SHIFT) /* 0x00001F00 */ +#define VOP_DSC_CFG11_RC_QUANT_INCR_LIMIT0_SHIFT (13U) +#define VOP_DSC_CFG11_RC_QUANT_INCR_LIMIT0_MASK (0x1FU << VOP_DSC_CFG11_RC_QUANT_INCR_LIMIT0_SHIFT) /* 0x0003E000 */ +#define VOP_DSC_CFG11_RC_EDGE_FACTOR_SHIFT (18U) +#define VOP_DSC_CFG11_RC_EDGE_FACTOR_MASK (0xFU << VOP_DSC_CFG11_RC_EDGE_FACTOR_SHIFT) /* 0x003C0000 */ +#define VOP_DSC_CFG11_RC_MODEL_SIZE_LO_SHIFT (22U) +#define VOP_DSC_CFG11_RC_MODEL_SIZE_LO_MASK (0x3FFU << VOP_DSC_CFG11_RC_MODEL_SIZE_LO_SHIFT) /* 0xFFC00000 */ +/* DSC_CFG12 */ +#define VOP_DSC_CFG12_OFFSET (0xA40U) +#define VOP_DSC_CFG12_RC_MODEL_SIZE_HI_SHIFT (0U) +#define VOP_DSC_CFG12_RC_MODEL_SIZE_HI_MASK (0x3FU << VOP_DSC_CFG12_RC_MODEL_SIZE_HI_SHIFT) /* 0x0000003F */ +#define VOP_DSC_CFG12_FLATNESS_DET_THRESH_SHIFT (6U) +#define VOP_DSC_CFG12_FLATNESS_DET_THRESH_MASK (0xFFU << VOP_DSC_CFG12_FLATNESS_DET_THRESH_SHIFT) /* 0x00003FC0 */ +#define VOP_DSC_CFG12_FLATNESS_MAX_QP_SHIFT (14U) +#define VOP_DSC_CFG12_FLATNESS_MAX_QP_MASK (0x1FU << VOP_DSC_CFG12_FLATNESS_MAX_QP_SHIFT) /* 0x0007C000 */ +#define VOP_DSC_CFG12_FLATNESS_MIN_QP_SHIFT (19U) +#define VOP_DSC_CFG12_FLATNESS_MIN_QP_MASK (0x1FU << VOP_DSC_CFG12_FLATNESS_MIN_QP_SHIFT) /* 0x00F80000 */ +#define VOP_DSC_CFG12_FINAL_OFFSET_LO_SHIFT (24U) +#define VOP_DSC_CFG12_FINAL_OFFSET_LO_MASK (0xFFU << VOP_DSC_CFG12_FINAL_OFFSET_LO_SHIFT) /* 0xFF000000 */ +/* DSC_CFG13 */ +#define VOP_DSC_CFG13_OFFSET (0xA44U) +#define VOP_DSC_CFG13_FINAL_OFFSET_HI_SHIFT (0U) +#define VOP_DSC_CFG13_FINAL_OFFSET_HI_MASK (0xFFU << VOP_DSC_CFG13_FINAL_OFFSET_HI_SHIFT) /* 0x000000FF */ +#define VOP_DSC_CFG13_INITIAL_OFFSET_SHIFT (8U) +#define VOP_DSC_CFG13_INITIAL_OFFSET_MASK (0xFFFFU << VOP_DSC_CFG13_INITIAL_OFFSET_SHIFT) /* 0x00FFFF00 */ +#define VOP_DSC_CFG13_SLICE_BPG_OFFSET_LO_SHIFT (24U) +#define VOP_DSC_CFG13_SLICE_BPG_OFFSET_LO_MASK (0xFFU << VOP_DSC_CFG13_SLICE_BPG_OFFSET_LO_SHIFT) /* 0xFF000000 */ +/* DSC_CFG14 */ +#define VOP_DSC_CFG14_OFFSET (0xA48U) +#define VOP_DSC_CFG14_SLICE_BPG_OFFSET_HI_SHIFT (0U) +#define VOP_DSC_CFG14_SLICE_BPG_OFFSET_HI_MASK (0xFFU << VOP_DSC_CFG14_SLICE_BPG_OFFSET_HI_SHIFT) /* 0x000000FF */ +#define VOP_DSC_CFG14_NFL_BPG_OFFSET_SHIFT (8U) +#define VOP_DSC_CFG14_NFL_BPG_OFFSET_MASK (0xFFFFU << VOP_DSC_CFG14_NFL_BPG_OFFSET_SHIFT) /* 0x00FFFF00 */ +#define VOP_DSC_CFG14_FIRST_LINE_BPG_OFFSET_SHIFT (24U) +#define VOP_DSC_CFG14_FIRST_LINE_BPG_OFFSET_MASK (0x1FU << VOP_DSC_CFG14_FIRST_LINE_BPG_OFFSET_SHIFT) /* 0x1F000000 */ +#define VOP_DSC_CFG14_SCALE_DECREMENT_INTERVAL_LO_SHIFT (29U) +#define VOP_DSC_CFG14_SCALE_DECREMENT_INTERVAL_LO_MASK (0x7U << VOP_DSC_CFG14_SCALE_DECREMENT_INTERVAL_LO_SHIFT) /* 0xE0000000 */ +/* DSC_CFG15 */ +#define VOP_DSC_CFG15_OFFSET (0xA4CU) +#define VOP_DSC_CFG15_SCALE_DECREMENT_INTERVAL_HI_SHIFT (0U) +#define VOP_DSC_CFG15_SCALE_DECREMENT_INTERVAL_HI_MASK (0x1FFU << VOP_DSC_CFG15_SCALE_DECREMENT_INTERVAL_HI_SHIFT) /* 0x000001FF */ +#define VOP_DSC_CFG15_SCALE_INCREMENT_INTERVAL_SHIFT (9U) +#define VOP_DSC_CFG15_SCALE_INCREMENT_INTERVAL_MASK (0xFFFFU << VOP_DSC_CFG15_SCALE_INCREMENT_INTERVAL_SHIFT) /* 0x01FFFE00 */ +#define VOP_DSC_CFG15_INITIAL_SCALE_VALUE_SHIFT (25U) +#define VOP_DSC_CFG15_INITIAL_SCALE_VALUE_MASK (0x3FU << VOP_DSC_CFG15_INITIAL_SCALE_VALUE_SHIFT) /* 0x7E000000 */ +#define VOP_DSC_CFG15_INITIAL_DEC_DELAY_LO_SHIFT (31U) +#define VOP_DSC_CFG15_INITIAL_DEC_DELAY_LO_MASK (0x1U << VOP_DSC_CFG15_INITIAL_DEC_DELAY_LO_SHIFT) /* 0x80000000 */ +/* DSC_CFG16 */ +#define VOP_DSC_CFG16_OFFSET (0xA50U) +#define VOP_DSC_CFG16_INITIAL_DEC_DELAY_HI_SHIFT (0U) +#define VOP_DSC_CFG16_INITIAL_DEC_DELAY_HI_MASK (0x7FFFU << VOP_DSC_CFG16_INITIAL_DEC_DELAY_HI_SHIFT) /* 0x00007FFF */ +#define VOP_DSC_CFG16_INITIAL_XMIT_DELAY_SHIFT (15U) +#define VOP_DSC_CFG16_INITIAL_XMIT_DELAY_MASK (0x3FFU << VOP_DSC_CFG16_INITIAL_XMIT_DELAY_SHIFT) /* 0x01FF8000 */ +#define VOP_DSC_CFG16_CHUNK_SIZE_LO_SHIFT (25U) +#define VOP_DSC_CFG16_CHUNK_SIZE_LO_MASK (0x7FU << VOP_DSC_CFG16_CHUNK_SIZE_LO_SHIFT) /* 0xFE000000 */ +/* DSC_CFG17 */ +#define VOP_DSC_CFG17_OFFSET (0xA54U) +#define VOP_DSC_CFG17_CHUNK_SIZE_HI_SHIFT (0U) +#define VOP_DSC_CFG17_CHUNK_SIZE_HI_MASK (0x1FFU << VOP_DSC_CFG17_CHUNK_SIZE_HI_SHIFT) /* 0x000001FF */ +#define VOP_DSC_CFG17_SLICE_HEIGHT_SHIFT (9U) +#define VOP_DSC_CFG17_SLICE_HEIGHT_MASK (0xFFFFU << VOP_DSC_CFG17_SLICE_HEIGHT_SHIFT) /* 0x01FFFE00 */ +#define VOP_DSC_CFG17_SLICE_WIDTH_LO_SHIFT (25U) +#define VOP_DSC_CFG17_SLICE_WIDTH_LO_MASK (0x7FU << VOP_DSC_CFG17_SLICE_WIDTH_LO_SHIFT) /* 0xFE000000 */ +/* DSC_CFG18 */ +#define VOP_DSC_CFG18_OFFSET (0xA58U) +#define VOP_DSC_CFG18_SLICE_WIDTH_HI_SHIFT (0U) +#define VOP_DSC_CFG18_SLICE_WIDTH_HI_MASK (0x1FFU << VOP_DSC_CFG18_SLICE_WIDTH_HI_SHIFT) /* 0x000001FF */ +#define VOP_DSC_CFG18_PICTURE_HEIGHT_SHIFT (9U) +#define VOP_DSC_CFG18_PICTURE_HEIGHT_MASK (0xFFFFU << VOP_DSC_CFG18_PICTURE_HEIGHT_SHIFT) /* 0x01FFFE00 */ +#define VOP_DSC_CFG18_PICTURE_WIDTH_LO_SHIFT (25U) +#define VOP_DSC_CFG18_PICTURE_WIDTH_LO_MASK (0x7FU << VOP_DSC_CFG18_PICTURE_WIDTH_LO_SHIFT) /* 0xFE000000 */ +/* DSC_CFG19 */ +#define VOP_DSC_CFG19_OFFSET (0xA5CU) +#define VOP_DSC_CFG19_PICTURE_WIDTH_HI_SHIFT (0U) +#define VOP_DSC_CFG19_PICTURE_WIDTH_HI_MASK (0x1FFU << VOP_DSC_CFG19_PICTURE_WIDTH_HI_SHIFT) /* 0x000001FF */ +#define VOP_DSC_CFG19_DSC_VERSION_MINOR_SHIFT (9U) +#define VOP_DSC_CFG19_DSC_VERSION_MINOR_MASK (0xFU << VOP_DSC_CFG19_DSC_VERSION_MINOR_SHIFT) /* 0x00001E00 */ +#define VOP_DSC_CFG19_BITS_PER_PIXEL_SHIFT (13U) +#define VOP_DSC_CFG19_BITS_PER_PIXEL_MASK (0x3FFU << VOP_DSC_CFG19_BITS_PER_PIXEL_SHIFT) /* 0x007FE000 */ +#define VOP_DSC_CFG19_BLOCK_PRED_ENABLE_SHIFT (23U) +#define VOP_DSC_CFG19_BLOCK_PRED_ENABLE_MASK (0x1U << VOP_DSC_CFG19_BLOCK_PRED_ENABLE_SHIFT) /* 0x00800000 */ +#define VOP_DSC_CFG19_LINEBUF_DEPTH_SHIFT (24U) +#define VOP_DSC_CFG19_LINEBUF_DEPTH_MASK (0xFU << VOP_DSC_CFG19_LINEBUF_DEPTH_SHIFT) /* 0x0F000000 */ +#define VOP_DSC_CFG19_ENABLE_422_SHIFT (28U) +#define VOP_DSC_CFG19_ENABLE_422_MASK (0x1U << VOP_DSC_CFG19_ENABLE_422_SHIFT) /* 0x10000000 */ +#define VOP_DSC_CFG19_CONVERT_RGB_SHIFT (29U) +#define VOP_DSC_CFG19_CONVERT_RGB_MASK (0x1U << VOP_DSC_CFG19_CONVERT_RGB_SHIFT) /* 0x20000000 */ +#define VOP_DSC_CFG19_BITS_PER_COMPONENT_LO_SHIFT (30U) +#define VOP_DSC_CFG19_BITS_PER_COMPONENT_LO_MASK (0x3U << VOP_DSC_CFG19_BITS_PER_COMPONENT_LO_SHIFT) /* 0xC0000000 */ +/* DSC_CFG20 */ +#define VOP_DSC_CFG20_OFFSET (0xA60U) +#define VOP_DSC_CFG20_BITS_PER_COMPONENT_HI_SHIFT (0U) +#define VOP_DSC_CFG20_BITS_PER_COMPONENT_HI_MASK (0x3U << VOP_DSC_CFG20_BITS_PER_COMPONENT_HI_SHIFT) /* 0x00000003 */ +/* DSC_INT_EN */ +#define VOP_DSC_INT_EN_OFFSET (0xA70U) +#define VOP_DSC_INT_EN_OUT_BUFF_FULL_CONTEXT_1_SHIFT (0U) +#define VOP_DSC_INT_EN_OUT_BUFF_FULL_CONTEXT_1_MASK (0x1U << VOP_DSC_INT_EN_OUT_BUFF_FULL_CONTEXT_1_SHIFT) /* 0x00000001 */ +#define VOP_DSC_INT_EN_OUT_BUFF_FULL_CONTEXT_0_SHIFT (1U) +#define VOP_DSC_INT_EN_OUT_BUFF_FULL_CONTEXT_0_MASK (0x1U << VOP_DSC_INT_EN_OUT_BUFF_FULL_CONTEXT_0_SHIFT) /* 0x00000002 */ +#define VOP_DSC_INT_EN_OUT_BUFF_EMPTY_CONTEXT_1_SHIFT (2U) +#define VOP_DSC_INT_EN_OUT_BUFF_EMPTY_CONTEXT_1_MASK (0x1U << VOP_DSC_INT_EN_OUT_BUFF_EMPTY_CONTEXT_1_SHIFT) /* 0x00000004 */ +#define VOP_DSC_INT_EN_OUT_BUFF_EMPTY_CONTEXT_0_SHIFT (3U) +#define VOP_DSC_INT_EN_OUT_BUFF_EMPTY_CONTEXT_0_MASK (0x1U << VOP_DSC_INT_EN_OUT_BUFF_EMPTY_CONTEXT_0_SHIFT) /* 0x00000008 */ +#define VOP_DSC_INT_EN_FRAME_DONE_SHIFT (4U) +#define VOP_DSC_INT_EN_FRAME_DONE_MASK (0x1U << VOP_DSC_INT_EN_FRAME_DONE_SHIFT) /* 0x00000010 */ +#define VOP_DSC_INT_EN_FRAME_STARTED_SHIFT (5U) +#define VOP_DSC_INT_EN_FRAME_STARTED_MASK (0x1U << VOP_DSC_INT_EN_FRAME_STARTED_SHIFT) /* 0x00000020 */ +#define VOP_DSC_INT_EN_CE_SHIFT (6U) +#define VOP_DSC_INT_EN_CE_MASK (0x1U << VOP_DSC_INT_EN_CE_SHIFT) /* 0x00000040 */ +#define VOP_DSC_INT_EN_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT (7U) +#define VOP_DSC_INT_EN_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK (0x1U << VOP_DSC_INT_EN_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT) /* 0x00000080 */ +#define VOP_DSC_INT_EN_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT (8U) +#define VOP_DSC_INT_EN_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK (0x1U << VOP_DSC_INT_EN_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT) /* 0x00000100 */ +#define VOP_DSC_INT_EN_DSC_UNDERFLOW_CONTEX_1_SHIFT (9U) +#define VOP_DSC_INT_EN_DSC_UNDERFLOW_CONTEX_1_MASK (0x1U << VOP_DSC_INT_EN_DSC_UNDERFLOW_CONTEX_1_SHIFT) /* 0x00000200 */ +#define VOP_DSC_INT_EN_DSC_UNDERFLOW_CONTEX_0_SHIFT (10U) +#define VOP_DSC_INT_EN_DSC_UNDERFLOW_CONTEX_0_MASK (0x1U << VOP_DSC_INT_EN_DSC_UNDERFLOW_CONTEX_0_SHIFT) /* 0x00000400 */ +/* DSC_INT_CLR */ +#define VOP_DSC_INT_CLR_OFFSET (0xA74U) +#define VOP_DSC_INT_CLR_OUT_BUFF_FULL_CONTEXT_1_SHIFT (0U) +#define VOP_DSC_INT_CLR_OUT_BUFF_FULL_CONTEXT_1_MASK (0x1U << VOP_DSC_INT_CLR_OUT_BUFF_FULL_CONTEXT_1_SHIFT) /* 0x00000001 */ +#define VOP_DSC_INT_CLR_OUT_BUFF_FULL_CONTEXT_0_SHIFT (1U) +#define VOP_DSC_INT_CLR_OUT_BUFF_FULL_CONTEXT_0_MASK (0x1U << VOP_DSC_INT_CLR_OUT_BUFF_FULL_CONTEXT_0_SHIFT) /* 0x00000002 */ +#define VOP_DSC_INT_CLR_OUT_BUFF_EMPTY_CONTEXT_1_SHIFT (2U) +#define VOP_DSC_INT_CLR_OUT_BUFF_EMPTY_CONTEXT_1_MASK (0x1U << VOP_DSC_INT_CLR_OUT_BUFF_EMPTY_CONTEXT_1_SHIFT) /* 0x00000004 */ +#define VOP_DSC_INT_CLR_OUT_BUFF_EMPTY_CONTEXT_0_SHIFT (3U) +#define VOP_DSC_INT_CLR_OUT_BUFF_EMPTY_CONTEXT_0_MASK (0x1U << VOP_DSC_INT_CLR_OUT_BUFF_EMPTY_CONTEXT_0_SHIFT) /* 0x00000008 */ +#define VOP_DSC_INT_CLR_FRAME_DONE_SHIFT (4U) +#define VOP_DSC_INT_CLR_FRAME_DONE_MASK (0x1U << VOP_DSC_INT_CLR_FRAME_DONE_SHIFT) /* 0x00000010 */ +#define VOP_DSC_INT_CLR_FRAME_STARTED_SHIFT (5U) +#define VOP_DSC_INT_CLR_FRAME_STARTED_MASK (0x1U << VOP_DSC_INT_CLR_FRAME_STARTED_SHIFT) /* 0x00000020 */ +#define VOP_DSC_INT_CLR_CE_SHIFT (6U) +#define VOP_DSC_INT_CLR_CE_MASK (0x1U << VOP_DSC_INT_CLR_CE_SHIFT) /* 0x00000040 */ +#define VOP_DSC_INT_CLR_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT (7U) +#define VOP_DSC_INT_CLR_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK (0x1U << VOP_DSC_INT_CLR_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT) /* 0x00000080 */ +#define VOP_DSC_INT_CLR_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT (8U) +#define VOP_DSC_INT_CLR_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK (0x1U << VOP_DSC_INT_CLR_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT) /* 0x00000100 */ +#define VOP_DSC_INT_CLR_DSC_UNDERFLOW_CONTEX_1_SHIFT (9U) +#define VOP_DSC_INT_CLR_DSC_UNDERFLOW_CONTEX_1_MASK (0x1U << VOP_DSC_INT_CLR_DSC_UNDERFLOW_CONTEX_1_SHIFT) /* 0x00000200 */ +#define VOP_DSC_INT_CLR_DSC_UNDERFLOW_CONTEX_0_SHIFT (10U) +#define VOP_DSC_INT_CLR_DSC_UNDERFLOW_CONTEX_0_MASK (0x1U << VOP_DSC_INT_CLR_DSC_UNDERFLOW_CONTEX_0_SHIFT) /* 0x00000400 */ +/* DSC_INT_STATUS */ +#define VOP_DSC_INT_STATUS_OFFSET (0xA78U) +#define VOP_DSC_INT_STATUS_OUT_BUFF_FULL_CONTEXT_1_SHIFT (0U) +#define VOP_DSC_INT_STATUS_OUT_BUFF_FULL_CONTEXT_1_MASK (0x1U << VOP_DSC_INT_STATUS_OUT_BUFF_FULL_CONTEXT_1_SHIFT) /* 0x00000001 */ +#define VOP_DSC_INT_STATUS_OUT_BUFF_FULL_CONTEXT_0_SHIFT (1U) +#define VOP_DSC_INT_STATUS_OUT_BUFF_FULL_CONTEXT_0_MASK (0x1U << VOP_DSC_INT_STATUS_OUT_BUFF_FULL_CONTEXT_0_SHIFT) /* 0x00000002 */ +#define VOP_DSC_INT_STATUS_OUT_BUFF_EMPTY_CONTEXT_1_SHIFT (2U) +#define VOP_DSC_INT_STATUS_OUT_BUFF_EMPTY_CONTEXT_1_MASK (0x1U << VOP_DSC_INT_STATUS_OUT_BUFF_EMPTY_CONTEXT_1_SHIFT) /* 0x00000004 */ +#define VOP_DSC_INT_STATUS_OUT_BUFF_EMPTY_CONTEXT_0_SHIFT (3U) +#define VOP_DSC_INT_STATUS_OUT_BUFF_EMPTY_CONTEXT_0_MASK (0x1U << VOP_DSC_INT_STATUS_OUT_BUFF_EMPTY_CONTEXT_0_SHIFT) /* 0x00000008 */ +#define VOP_DSC_INT_STATUS_FRAME_DONE_SHIFT (4U) +#define VOP_DSC_INT_STATUS_FRAME_DONE_MASK (0x1U << VOP_DSC_INT_STATUS_FRAME_DONE_SHIFT) /* 0x00000010 */ +#define VOP_DSC_INT_STATUS_FRAME_STARTED_SHIFT (5U) +#define VOP_DSC_INT_STATUS_FRAME_STARTED_MASK (0x1U << VOP_DSC_INT_STATUS_FRAME_STARTED_SHIFT) /* 0x00000020 */ +#define VOP_DSC_INT_STATUS_CE_SHIFT (6U) +#define VOP_DSC_INT_STATUS_CE_MASK (0x1U << VOP_DSC_INT_STATUS_CE_SHIFT) /* 0x00000040 */ +#define VOP_DSC_INT_STATUS_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT (7U) +#define VOP_DSC_INT_STATUS_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK (0x1U << VOP_DSC_INT_STATUS_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT) /* 0x00000080 */ +#define VOP_DSC_INT_STATUS_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT (8U) +#define VOP_DSC_INT_STATUS_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK (0x1U << VOP_DSC_INT_STATUS_RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT) /* 0x00000100 */ +#define VOP_DSC_INT_STATUS_DSC_UNDERFLOW_CONTEX_1_SHIFT (9U) +#define VOP_DSC_INT_STATUS_DSC_UNDERFLOW_CONTEX_1_MASK (0x1U << VOP_DSC_INT_STATUS_DSC_UNDERFLOW_CONTEX_1_SHIFT) /* 0x00000200 */ +#define VOP_DSC_INT_STATUS_DSC_UNDERFLOW_CONTEX_0_SHIFT (10U) +#define VOP_DSC_INT_STATUS_DSC_UNDERFLOW_CONTEX_0_MASK (0x1U << VOP_DSC_INT_STATUS_DSC_UNDERFLOW_CONTEX_0_SHIFT) /* 0x00000400 */ +/* DSC_DBG_STATUS0 */ +#define VOP_DSC_DBG_STATUS0_OFFSET (0xA80U) +#define VOP_DSC_DBG_STATUS0 (0x0U) +#define VOP_DSC_DBG_STATUS0_SLICE_COUNT_OUT_SHIFT (0U) +#define VOP_DSC_DBG_STATUS0_SLICE_COUNT_OUT_MASK (0xFFFFU << VOP_DSC_DBG_STATUS0_SLICE_COUNT_OUT_SHIFT) /* 0x0000FFFF */ +#define VOP_DSC_DBG_STATUS0_SLICE_LINE_COUNT_OUT_SHIFT (16U) +#define VOP_DSC_DBG_STATUS0_SLICE_LINE_COUNT_OUT_MASK (0xFFFFU << VOP_DSC_DBG_STATUS0_SLICE_LINE_COUNT_OUT_SHIFT) /* 0xFFFF0000 */ +/* DSC_DBG_STATUS1 */ +#define VOP_DSC_DBG_STATUS1_OFFSET (0xA84U) +#define VOP_DSC_DBG_STATUS1 (0x0U) +#define VOP_DSC_DBG_STATUS1_SLICE_COUNT_ENCODED_SHIFT (0U) +#define VOP_DSC_DBG_STATUS1_SLICE_COUNT_ENCODED_MASK (0xFFFFU << VOP_DSC_DBG_STATUS1_SLICE_COUNT_ENCODED_SHIFT) /* 0x0000FFFF */ +#define VOP_DSC_DBG_STATUS1_SLICE_LINE_COUNT_ENCODED_SHIFT (16U) +#define VOP_DSC_DBG_STATUS1_SLICE_LINE_COUNT_ENCODED_MASK (0xFFFFU << VOP_DSC_DBG_STATUS1_SLICE_LINE_COUNT_ENCODED_SHIFT) /* 0xFFFF0000 */ +/* DSC_DBG_STATUS2 */ +#define VOP_DSC_DBG_STATUS2_OFFSET (0xA88U) +#define VOP_DSC_DBG_STATUS2_OUT_BUFF_FULL_CONTEXT_1_SHIFT (0U) +#define VOP_DSC_DBG_STATUS2_OUT_BUFF_FULL_CONTEXT_1_MASK (0x1U << VOP_DSC_DBG_STATUS2_OUT_BUFF_FULL_CONTEXT_1_SHIFT) /* 0x00000001 */ +#define VOP_DSC_DBG_STATUS2_OUT_BUFF_FULL_CONTEXT_0_SHIFT (1U) +#define VOP_DSC_DBG_STATUS2_OUT_BUFF_FULL_CONTEXT_0_MASK (0x1U << VOP_DSC_DBG_STATUS2_OUT_BUFF_FULL_CONTEXT_0_SHIFT) /* 0x00000002 */ +#define VOP_DSC_DBG_STATUS2_OUT_BUFF_EMPTY_CONTEXT_1_SHIFT (2U) +#define VOP_DSC_DBG_STATUS2_OUT_BUFF_EMPTY_CONTEXT_1_MASK (0x1U << VOP_DSC_DBG_STATUS2_OUT_BUFF_EMPTY_CONTEXT_1_SHIFT) /* 0x00000004 */ +#define VOP_DSC_DBG_STATUS2_OUT_BUFF_EMPTY_CONTEXT_0_SHIFT (3U) +#define VOP_DSC_DBG_STATUS2_OUT_BUFF_EMPTY_CONTEXT_0_MASK (0x1U << VOP_DSC_DBG_STATUS2_OUT_BUFF_EMPTY_CONTEXT_0_SHIFT) /* 0x00000008 */ +#define VOP_DSC_DBG_STATUS2_FRAME_DONE_SHIFT (4U) +#define VOP_DSC_DBG_STATUS2_FRAME_DONE_MASK (0x1U << VOP_DSC_DBG_STATUS2_FRAME_DONE_SHIFT) /* 0x00000010 */ +#define VOP_DSC_DBG_STATUS2_FRAME_STARTED_SHIFT (5U) +#define VOP_DSC_DBG_STATUS2_FRAME_STARTED_MASK (0x1U << VOP_DSC_DBG_STATUS2_FRAME_STARTED_SHIFT) /* 0x00000020 */ +#define VOP_DSC_DBG_STATUS2_CE_SHIFT (6U) +#define VOP_DSC_DBG_STATUS2_CE_MASK (0x1U << VOP_DSC_DBG_STATUS2_CE_SHIFT) /* 0x00000040 */ +/******************************************DSI*******************************************/ +/* VERSION */ +#define DSI_VERSION_OFFSET (0x0U) +#define DSI_VERSION (0x3133302AU) +#define DSI_VERSION_VERSION_SHIFT (0U) +#define DSI_VERSION_VERSION_MASK (0xFFFFFFFFU << DSI_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */ +/* PWR_UP */ +#define DSI_PWR_UP_OFFSET (0x4U) +#define DSI_PWR_UP_SHUTDOWNZ_SHIFT (0U) +#define DSI_PWR_UP_SHUTDOWNZ_MASK (0x1U << DSI_PWR_UP_SHUTDOWNZ_SHIFT) /* 0x00000001 */ +/* CLKMGR_CFG */ +#define DSI_CLKMGR_CFG_OFFSET (0x8U) +#define DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT (0U) +#define DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK (0xFFU << DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) /* 0x000000FF */ +#define DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT (8U) +#define DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK (0xFFU << DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) /* 0x0000FF00 */ +/* DPI_VCID */ +#define DSI_DPI_VCID_OFFSET (0xCU) +#define DSI_DPI_VCID_DPI_VCID_SHIFT (0U) +#define DSI_DPI_VCID_DPI_VCID_MASK (0x3U << DSI_DPI_VCID_DPI_VCID_SHIFT) /* 0x00000003 */ +/* DPI_COLOR_CODING */ +#define DSI_DPI_COLOR_CODING_OFFSET (0x10U) +#define DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT (0U) +#define DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK (0xFU << DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) /* 0x0000000F */ +#define DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT (8U) +#define DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK (0x1U << DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) /* 0x00000100 */ +/* DPI_CFG_POL */ +#define DSI_DPI_CFG_POL_OFFSET (0x14U) +#define DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT (0U) +#define DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK (0x1U << DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) /* 0x00000001 */ +#define DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT (1U) +#define DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK (0x1U << DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) /* 0x00000002 */ +#define DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT (2U) +#define DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK (0x1U << DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) /* 0x00000004 */ +#define DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT (3U) +#define DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK (0x1U << DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) /* 0x00000008 */ +#define DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT (4U) +#define DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK (0x1U << DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) /* 0x00000010 */ +/* DPI_LP_CMD_TIM */ +#define DSI_DPI_LP_CMD_TIM_OFFSET (0x18U) +#define DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT (0U) +#define DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK (0xFFU << DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) /* 0x000000FF */ +#define DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT (16U) +#define DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK (0xFFU << DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) /* 0x00FF0000 */ +/* PCKHDL_CFG */ +#define DSI_PCKHDL_CFG_OFFSET (0x2CU) +#define DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT (0U) +#define DSI_PCKHDL_CFG_EOTP_TX_EN_MASK (0x1U << DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) /* 0x00000001 */ +#define DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT (1U) +#define DSI_PCKHDL_CFG_EOTP_RX_EN_MASK (0x1U << DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) /* 0x00000002 */ +#define DSI_PCKHDL_CFG_BTA_EN_SHIFT (2U) +#define DSI_PCKHDL_CFG_BTA_EN_MASK (0x1U << DSI_PCKHDL_CFG_BTA_EN_SHIFT) /* 0x00000004 */ +#define DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT (3U) +#define DSI_PCKHDL_CFG_ECC_RX_EN_MASK (0x1U << DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) /* 0x00000008 */ +#define DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT (4U) +#define DSI_PCKHDL_CFG_CRC_RX_EN_MASK (0x1U << DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) /* 0x00000010 */ +/* GEN_VCID */ +#define DSI_GEN_VCID_OFFSET (0x30U) +#define DSI_GEN_VCID_GEN_VCID_RX_SHIFT (0U) +#define DSI_GEN_VCID_GEN_VCID_RX_MASK (0x3U << DSI_GEN_VCID_GEN_VCID_RX_SHIFT) /* 0x00000003 */ +/* MODE_CFG */ +#define DSI_MODE_CFG_OFFSET (0x34U) +#define DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT (0U) +#define DSI_MODE_CFG_CMD_VIDEO_MODE_MASK (0x1U << DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) /* 0x00000001 */ +/* VID_MODE_CFG */ +#define DSI_VID_MODE_CFG_OFFSET (0x38U) +#define DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT (0U) +#define DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK (0x3U << DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) /* 0x00000003 */ +#define DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT (8U) +#define DSI_VID_MODE_CFG_LP_VSA_EN_MASK (0x1U << DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) /* 0x00000100 */ +#define DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT (9U) +#define DSI_VID_MODE_CFG_LP_VBP_EN_MASK (0x1U << DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) /* 0x00000200 */ +#define DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT (10U) +#define DSI_VID_MODE_CFG_LP_VFP_EN_MASK (0x1U << DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) /* 0x00000400 */ +#define DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT (11U) +#define DSI_VID_MODE_CFG_LP_VACT_EN_MASK (0x1U << DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) /* 0x00000800 */ +#define DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT (12U) +#define DSI_VID_MODE_CFG_LP_HBP_EN_MASK (0x1U << DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) /* 0x00001000 */ +#define DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT (13U) +#define DSI_VID_MODE_CFG_LP_HFP_EN_MASK (0x1U << DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) /* 0x00002000 */ +#define DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT (14U) +#define DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK (0x1U << DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) /* 0x00004000 */ +#define DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT (15U) +#define DSI_VID_MODE_CFG_LP_CMD_EN_MASK (0x1U << DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) /* 0x00008000 */ +#define DSI_VID_MODE_CFG_VGP_EN_SHIFT (16U) +#define DSI_VID_MODE_CFG_VGP_EN_MASK (0x1U << DSI_VID_MODE_CFG_VGP_EN_SHIFT) /* 0x00010000 */ +#define DSI_VID_MODE_CFG_VGP_MODE_SHIFT (20U) +#define DSI_VID_MODE_CFG_VGP_MODE_MASK (0x1U << DSI_VID_MODE_CFG_VGP_MODE_SHIFT) /* 0x00100000 */ +#define DSI_VID_MODE_CFG_VGP_ORIENTATION_SHIFT (24U) +#define DSI_VID_MODE_CFG_VGP_ORIENTATION_MASK (0x1U << DSI_VID_MODE_CFG_VGP_ORIENTATION_SHIFT) /* 0x01000000 */ +/* VID_PKT_SIZE */ +#define DSI_VID_PKT_SIZE_OFFSET (0x3CU) +#define DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT (0U) +#define DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK (0x3FFFU << DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) /* 0x00003FFF */ +/* VID_NUM_CHUNKS */ +#define DSI_VID_NUM_CHUNKS_OFFSET (0x40U) +#define DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT (0U) +#define DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK (0x1FFFU << DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) /* 0x00001FFF */ +/* VID_NULL_SIZE */ +#define DSI_VID_NULL_SIZE_OFFSET (0x44U) +#define DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT (0U) +#define DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK (0x1FFFU << DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) /* 0x00001FFF */ +/* VID_HSA_TIME */ +#define DSI_VID_HSA_TIME_OFFSET (0x48U) +#define DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT (0U) +#define DSI_VID_HSA_TIME_VID_HSA_TIME_MASK (0xFFFU << DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) /* 0x00000FFF */ +/* VID_HBP_TIME */ +#define DSI_VID_HBP_TIME_OFFSET (0x4CU) +#define DSI_VID_HBP_TIME_VID_HBP_TIME_SHIFT (0U) +#define DSI_VID_HBP_TIME_VID_HBP_TIME_MASK (0xFFFU << DSI_VID_HBP_TIME_VID_HBP_TIME_SHIFT) /* 0x00000FFF */ +/* VID_HLINE_TIME */ +#define DSI_VID_HLINE_TIME_OFFSET (0x50U) +#define DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT (0U) +#define DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK (0x7FFFU << DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) /* 0x00007FFF */ +/* VID_VSA_LINES */ +#define DSI_VID_VSA_LINES_OFFSET (0x54U) +#define DSI_VID_VSA_LINES_VSA_LINES_SHIFT (0U) +#define DSI_VID_VSA_LINES_VSA_LINES_MASK (0x3FFU << DSI_VID_VSA_LINES_VSA_LINES_SHIFT) /* 0x000003FF */ +/* VID_VBP_LINES */ +#define DSI_VID_VBP_LINES_OFFSET (0x58U) +#define DSI_VID_VBP_LINES_VBP_LINE_SHIFT (0U) +#define DSI_VID_VBP_LINES_VBP_LINE_MASK (0x3FFU << DSI_VID_VBP_LINES_VBP_LINE_SHIFT) /* 0x000003FF */ +/* VID_VFP_LINES */ +#define DSI_VID_VFP_LINES_OFFSET (0x5CU) +#define DSI_VID_VFP_LINES_VFP_LINES_SHIFT (0U) +#define DSI_VID_VFP_LINES_VFP_LINES_MASK (0x3FFU << DSI_VID_VFP_LINES_VFP_LINES_SHIFT) /* 0x000003FF */ +/* VID_VACTIVE_LINES */ +#define DSI_VID_VACTIVE_LINES_OFFSET (0x60U) +#define DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT (0U) +#define DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK (0x3FFFU << DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) /* 0x00003FFF */ +/* EDPI_CMD_SIZE */ +#define DSI_EDPI_CMD_SIZE_OFFSET (0x64U) +#define DSI_EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_SHIFT (0U) +#define DSI_EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_MASK (0xFFFFU << DSI_EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_SHIFT) /* 0x0000FFFF */ +/* CMD_MODE_CFG */ +#define DSI_CMD_MODE_CFG_OFFSET (0x68U) +#define DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT (0U) +#define DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK (0x1U << DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) /* 0x00000001 */ +#define DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT (1U) +#define DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK (0x1U << DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) /* 0x00000002 */ +#define DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT (8U) +#define DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK (0x1U << DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) /* 0x00000100 */ +#define DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT (9U) +#define DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK (0x1U << DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) /* 0x00000200 */ +#define DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT (10U) +#define DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK (0x1U << DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) /* 0x00000400 */ +#define DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT (11U) +#define DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK (0x1U << DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) /* 0x00000800 */ +#define DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT (12U) +#define DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK (0x1U << DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) /* 0x00001000 */ +#define DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT (13U) +#define DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK (0x1U << DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) /* 0x00002000 */ +#define DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT (14U) +#define DSI_CMD_MODE_CFG_GEN_LW_TX_MASK (0x1U << DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) /* 0x00004000 */ +#define DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT (16U) +#define DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK (0x1U << DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) /* 0x00010000 */ +#define DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT (17U) +#define DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK (0x1U << DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) /* 0x00020000 */ +#define DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT (18U) +#define DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK (0x1U << DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) /* 0x00040000 */ +#define DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT (19U) +#define DSI_CMD_MODE_CFG_DCS_LW_TX_MASK (0x1U << DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) /* 0x00080000 */ +#define DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT (24U) +#define DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK (0x1U << DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) /* 0x01000000 */ +/* GEN_HDR */ +#define DSI_GEN_HDR_OFFSET (0x6CU) +#define DSI_GEN_HDR_GEN_DT_SHIFT (0U) +#define DSI_GEN_HDR_GEN_DT_MASK (0x3FU << DSI_GEN_HDR_GEN_DT_SHIFT) /* 0x0000003F */ +#define DSI_GEN_HDR_GEN_VC_SHIFT (6U) +#define DSI_GEN_HDR_GEN_VC_MASK (0x3U << DSI_GEN_HDR_GEN_VC_SHIFT) /* 0x000000C0 */ +#define DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT (8U) +#define DSI_GEN_HDR_GEN_WC_LSBYTE_MASK (0xFFU << DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) /* 0x0000FF00 */ +#define DSI_GEN_HDR_GEM_WC_MSBYTE_SHIFT (16U) +#define DSI_GEN_HDR_GEM_WC_MSBYTE_MASK (0xFFU << DSI_GEN_HDR_GEM_WC_MSBYTE_SHIFT) /* 0x00FF0000 */ +/* GEN_PLD_DATA */ +#define DSI_GEN_PLD_DATA_OFFSET (0x70U) +#define DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT (0U) +#define DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK (0xFFU << DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) /* 0x000000FF */ +#define DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT (8U) +#define DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK (0xFFU << DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) /* 0x0000FF00 */ +#define DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT (16U) +#define DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK (0xFFU << DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) /* 0x00FF0000 */ +#define DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT (24U) +#define DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK (0xFFU << DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) /* 0xFF000000 */ +/* CMD_PKT_STATUS */ +#define DSI_CMD_PKT_STATUS_OFFSET (0x74U) +#define DSI_CMD_PKT_STATUS (0x1515U) +#define DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT (0U) +#define DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK (0x1U << DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT) /* 0x00000001 */ +#define DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT (1U) +#define DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK (0x1U << DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT) /* 0x00000002 */ +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT (2U) +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK (0x1U << DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT) /* 0x00000004 */ +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT (3U) +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK (0x1U << DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT) /* 0x00000008 */ +#define DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT (4U) +#define DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK (0x1U << DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT) /* 0x00000010 */ +#define DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT (5U) +#define DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK (0x1U << DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT) /* 0x00000020 */ +#define DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT (6U) +#define DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK (0x1U << DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT) /* 0x00000040 */ +#define DSI_CMD_PKT_STATUS_DBI_CMD_EMPTY_SHIFT (8U) +#define DSI_CMD_PKT_STATUS_DBI_CMD_EMPTY_MASK (0x1U << DSI_CMD_PKT_STATUS_DBI_CMD_EMPTY_SHIFT) /* 0x00000100 */ +#define DSI_CMD_PKT_STATUS_DBI_CMD_FULL_SHIFT (9U) +#define DSI_CMD_PKT_STATUS_DBI_CMD_FULL_MASK (0x1U << DSI_CMD_PKT_STATUS_DBI_CMD_FULL_SHIFT) /* 0x00000200 */ +#define DSI_CMD_PKT_STATUS_DBI_PLD_W_EMPTY_SHIFT (10U) +#define DSI_CMD_PKT_STATUS_DBI_PLD_W_EMPTY_MASK (0x1U << DSI_CMD_PKT_STATUS_DBI_PLD_W_EMPTY_SHIFT) /* 0x00000400 */ +#define DSI_CMD_PKT_STATUS_DBI_PLD_W_FULL_SHIFT (11U) +#define DSI_CMD_PKT_STATUS_DBI_PLD_W_FULL_MASK (0x1U << DSI_CMD_PKT_STATUS_DBI_PLD_W_FULL_SHIFT) /* 0x00000800 */ +#define DSI_CMD_PKT_STATUS_DBI_PLD_R_EMPTY_SHIFT (12U) +#define DSI_CMD_PKT_STATUS_DBI_PLD_R_EMPTY_MASK (0x1U << DSI_CMD_PKT_STATUS_DBI_PLD_R_EMPTY_SHIFT) /* 0x00001000 */ +#define DSI_CMD_PKT_STATUS_DBI_PLD_R_FULL_SHIFT (13U) +#define DSI_CMD_PKT_STATUS_DBI_PLD_R_FULL_MASK (0x1U << DSI_CMD_PKT_STATUS_DBI_PLD_R_FULL_SHIFT) /* 0x00002000 */ +#define DSI_CMD_PKT_STATUS_DBI_RD_CMD_BUSY_SHIFT (14U) +#define DSI_CMD_PKT_STATUS_DBI_RD_CMD_BUSY_MASK (0x1U << DSI_CMD_PKT_STATUS_DBI_RD_CMD_BUSY_SHIFT) /* 0x00004000 */ +/* TO_CNT_CFG */ +#define DSI_TO_CNT_CFG_OFFSET (0x78U) +#define DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT (0U) +#define DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK (0xFFFFU << DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) /* 0x0000FFFF */ +#define DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT (16U) +#define DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK (0xFFFFU << DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) /* 0xFFFF0000 */ +/* HS_RD_TO_CNT */ +#define DSI_HS_RD_TO_CNT_OFFSET (0x7CU) +#define DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT (0U) +#define DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK (0xFFFFU << DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) /* 0x0000FFFF */ +/* LP_RD_TO_CNT */ +#define DSI_LP_RD_TO_CNT_OFFSET (0x80U) +#define DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT (0U) +#define DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK (0xFFFFU << DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) /* 0x0000FFFF */ +/* HS_WR_TO_CNT */ +#define DSI_HS_WR_TO_CNT_OFFSET (0x84U) +#define DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT (0U) +#define DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK (0xFFFFU << DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) /* 0x0000FFFF */ +#define DSI_HS_WR_TO_CNT_PRESP_TO_MODE_SHIFT (24U) +#define DSI_HS_WR_TO_CNT_PRESP_TO_MODE_MASK (0x1U << DSI_HS_WR_TO_CNT_PRESP_TO_MODE_SHIFT) /* 0x01000000 */ +/* LP_WR_TO_CNT */ +#define DSI_LP_WR_TO_CNT_OFFSET (0x88U) +#define DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT (0U) +#define DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK (0xFFFFU << DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) /* 0x0000FFFF */ +/* BTA_TO_CNT */ +#define DSI_BTA_TO_CNT_OFFSET (0x8CU) +#define DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT (0U) +#define DSI_BTA_TO_CNT_BTA_TO_CNT_MASK (0xFFFFU << DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) /* 0x0000FFFF */ +/* SDF_3D */ +#define DSI_SDF_3D_OFFSET (0x90U) +#define DSI_SDF_3D_MODE_3D_SHIFT (0U) +#define DSI_SDF_3D_MODE_3D_MASK (0x3U << DSI_SDF_3D_MODE_3D_SHIFT) /* 0x00000003 */ +#define DSI_SDF_3D_FORMAT_3D_SHIFT (2U) +#define DSI_SDF_3D_FORMAT_3D_MASK (0x3U << DSI_SDF_3D_FORMAT_3D_SHIFT) /* 0x0000000C */ +#define DSI_SDF_3D_SECOND_VSYNC_SHIFT (4U) +#define DSI_SDF_3D_SECOND_VSYNC_MASK (0x1U << DSI_SDF_3D_SECOND_VSYNC_SHIFT) /* 0x00000010 */ +#define DSI_SDF_3D_RIGHT_FIRST_SHIFT (5U) +#define DSI_SDF_3D_RIGHT_FIRST_MASK (0x1U << DSI_SDF_3D_RIGHT_FIRST_SHIFT) /* 0x00000020 */ +#define DSI_SDF_3D_SEND_3D_CFG_SHIFT (16U) +#define DSI_SDF_3D_SEND_3D_CFG_MASK (0x1U << DSI_SDF_3D_SEND_3D_CFG_SHIFT) /* 0x00010000 */ +/* LPCLK_CTRL */ +#define DSI_LPCLK_CTRL_OFFSET (0x94U) +#define DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT (0U) +#define DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK (0x1U << DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) /* 0x00000001 */ +#define DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT (1U) +#define DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK (0x1U << DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) /* 0x00000002 */ +/* PHY_TMR_LPCLK_CFG */ +#define DSI_PHY_TMR_LPCLK_CFG_OFFSET (0x98U) +#define DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT (0U) +#define DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK (0x3FFU << DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) /* 0x000003FF */ +#define DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT (16U) +#define DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK (0x3FFU << DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) /* 0x03FF0000 */ +/* PHY_TMR_CFG */ +#define DSI_PHY_TMR_CFG_OFFSET (0x9CU) +#define DSI_PHY_TMR_CFG_MAX_RD_TIME_SHIFT (0U) +#define DSI_PHY_TMR_CFG_MAX_RD_TIME_MASK (0x7FFFU << DSI_PHY_TMR_CFG_MAX_RD_TIME_SHIFT) /* 0x00007FFF */ +#define DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT (16U) +#define DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK (0xFFU << DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) /* 0x00FF0000 */ +#define DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT (24U) +#define DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK (0xFFU << DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) /* 0xFF000000 */ +/* PHY_RSTZ */ +#define DSI_PHY_RSTZ_OFFSET (0xA0U) +#define DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT (0U) +#define DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK (0x1U << DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) /* 0x00000001 */ +#define DSI_PHY_RSTZ_PHY_RSTZ_SHIFT (1U) +#define DSI_PHY_RSTZ_PHY_RSTZ_MASK (0x1U << DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) /* 0x00000002 */ +#define DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT (2U) +#define DSI_PHY_RSTZ_PHY_ENABLECLK_MASK (0x1U << DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) /* 0x00000004 */ +#define DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT (3U) +#define DSI_PHY_RSTZ_PHY_FORCEPLL_MASK (0x1U << DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) /* 0x00000008 */ +/* PHY_IF_CFG */ +#define DSI_PHY_IF_CFG_OFFSET (0xA4U) +#define DSI_PHY_IF_CFG_N_LANES_SHIFT (0U) +#define DSI_PHY_IF_CFG_N_LANES_MASK (0x3U << DSI_PHY_IF_CFG_N_LANES_SHIFT) /* 0x00000003 */ +#define DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT (8U) +#define DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK (0xFFU << DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) /* 0x0000FF00 */ +/* PHY_STATUS */ +#define DSI_PHY_STATUS_OFFSET (0xB0U) +#define DSI_PHY_STATUS (0x1528U) +#define DSI_PHY_STATUS_PHY_LOCK_SHIFT (0U) +#define DSI_PHY_STATUS_PHY_LOCK_MASK (0x1U << DSI_PHY_STATUS_PHY_LOCK_SHIFT) /* 0x00000001 */ +#define DSI_PHY_STATUS_PHY_DIRECTION_SHIFT (1U) +#define DSI_PHY_STATUS_PHY_DIRECTION_MASK (0x1U << DSI_PHY_STATUS_PHY_DIRECTION_SHIFT) /* 0x00000002 */ +#define DSI_PHY_STATUS_HPY_STOPSTATECLKLANE_SHIFT (2U) +#define DSI_PHY_STATUS_HPY_STOPSTATECLKLANE_MASK (0x1U << DSI_PHY_STATUS_HPY_STOPSTATECLKLANE_SHIFT) /* 0x00000004 */ +#define DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT (3U) +#define DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK (0x1U << DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT) /* 0x00000008 */ +#define DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT (4U) +#define DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK (0x1U << DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT) /* 0x00000010 */ +#define DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT (5U) +#define DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK (0x1U << DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT) /* 0x00000020 */ +#define DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT (6U) +#define DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK (0x1U << DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT) /* 0x00000040 */ +#define DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT (7U) +#define DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK (0x1U << DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT) /* 0x00000080 */ +#define DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT (8U) +#define DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK (0x1U << DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT) /* 0x00000100 */ +#define DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT (9U) +#define DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK (0x1U << DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT) /* 0x00000200 */ +#define DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT (10U) +#define DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK (0x1U << DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT) /* 0x00000400 */ +#define DSI_PHY_STATUS_PHY_STOPSTATELANE_SHIFT (11U) +#define DSI_PHY_STATUS_PHY_STOPSTATELANE_MASK (0x1U << DSI_PHY_STATUS_PHY_STOPSTATELANE_SHIFT) /* 0x00000800 */ +#define DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT (12U) +#define DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK (0x1U << DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT) /* 0x00001000 */ +/* INT_ST0 */ +#define DSI_INT_ST0_OFFSET (0xBCU) +#define DSI_INT_ST0 (0x0U) +#define DSI_INT_ST0_ACK_WITH_ERR_0_SHIFT (0U) +#define DSI_INT_ST0_ACK_WITH_ERR_0_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_0_SHIFT) /* 0x00000001 */ +#define DSI_INT_ST0_ACK_WITH_ERR_1_SHIFT (1U) +#define DSI_INT_ST0_ACK_WITH_ERR_1_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_1_SHIFT) /* 0x00000002 */ +#define DSI_INT_ST0_ACK_WITH_ERR_2_SHIFT (2U) +#define DSI_INT_ST0_ACK_WITH_ERR_2_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_2_SHIFT) /* 0x00000004 */ +#define DSI_INT_ST0_ACK_WITH_ERR_3_SHIFT (3U) +#define DSI_INT_ST0_ACK_WITH_ERR_3_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_3_SHIFT) /* 0x00000008 */ +#define DSI_INT_ST0_ACK_WITH_ERR_4_SHIFT (4U) +#define DSI_INT_ST0_ACK_WITH_ERR_4_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_4_SHIFT) /* 0x00000010 */ +#define DSI_INT_ST0_ACK_WITH_ERR_5_SHIFT (5U) +#define DSI_INT_ST0_ACK_WITH_ERR_5_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_5_SHIFT) /* 0x00000020 */ +#define DSI_INT_ST0_ACK_WITH_ERR_6_SHIFT (6U) +#define DSI_INT_ST0_ACK_WITH_ERR_6_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_6_SHIFT) /* 0x00000040 */ +#define DSI_INT_ST0_ACK_WITH_ERR_7_SHIFT (7U) +#define DSI_INT_ST0_ACK_WITH_ERR_7_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_7_SHIFT) /* 0x00000080 */ +#define DSI_INT_ST0_ACK_WITH_ERR_8_SHIFT (8U) +#define DSI_INT_ST0_ACK_WITH_ERR_8_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_8_SHIFT) /* 0x00000100 */ +#define DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT (9U) +#define DSI_INT_ST0_ACK_WITH_ERR_9_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT) /* 0x00000200 */ +#define DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT (10U) +#define DSI_INT_ST0_ACK_WITH_ERR_10_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT) /* 0x00000400 */ +#define DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT (11U) +#define DSI_INT_ST0_ACK_WITH_ERR_11_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT) /* 0x00000800 */ +#define DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT (12U) +#define DSI_INT_ST0_ACK_WITH_ERR_12_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT) /* 0x00001000 */ +#define DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT (13U) +#define DSI_INT_ST0_ACK_WITH_ERR_13_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT) /* 0x00002000 */ +#define DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT (14U) +#define DSI_INT_ST0_ACK_WITH_ERR_14_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT) /* 0x00004000 */ +#define DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT (15U) +#define DSI_INT_ST0_ACK_WITH_ERR_15_MASK (0x1U << DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT) /* 0x00008000 */ +#define DSI_INT_ST0_DPHY_ERRORS_0_SHIFT (16U) +#define DSI_INT_ST0_DPHY_ERRORS_0_MASK (0x1U << DSI_INT_ST0_DPHY_ERRORS_0_SHIFT) /* 0x00010000 */ +#define DSI_INT_ST0_DPHY_ERRORS_1_SHIFT (17U) +#define DSI_INT_ST0_DPHY_ERRORS_1_MASK (0x1U << DSI_INT_ST0_DPHY_ERRORS_1_SHIFT) /* 0x00020000 */ +#define DSI_INT_ST0_DPHY_ERRORS_2_SHIFT (18U) +#define DSI_INT_ST0_DPHY_ERRORS_2_MASK (0x1U << DSI_INT_ST0_DPHY_ERRORS_2_SHIFT) /* 0x00040000 */ +#define DSI_INT_ST0_DPHY_ERRORS_3_SHIFT (19U) +#define DSI_INT_ST0_DPHY_ERRORS_3_MASK (0x1U << DSI_INT_ST0_DPHY_ERRORS_3_SHIFT) /* 0x00080000 */ +#define DSI_INT_ST0_DPHY_ERRORS_4_SHIFT (20U) +#define DSI_INT_ST0_DPHY_ERRORS_4_MASK (0x1U << DSI_INT_ST0_DPHY_ERRORS_4_SHIFT) /* 0x00100000 */ +/* INT_ST1 */ +#define DSI_INT_ST1_OFFSET (0xC0U) +#define DSI_INT_ST1 (0x0U) +#define DSI_INT_ST1_TO_HS_TX_SHIFT (0U) +#define DSI_INT_ST1_TO_HS_TX_MASK (0x1U << DSI_INT_ST1_TO_HS_TX_SHIFT) /* 0x00000001 */ +#define DSI_INT_ST1_TO_LP_RX_SHIFT (1U) +#define DSI_INT_ST1_TO_LP_RX_MASK (0x1U << DSI_INT_ST1_TO_LP_RX_SHIFT) /* 0x00000002 */ +#define DSI_INT_ST1_ECC_SINGLE_ERR_SHIFT (2U) +#define DSI_INT_ST1_ECC_SINGLE_ERR_MASK (0x1U << DSI_INT_ST1_ECC_SINGLE_ERR_SHIFT) /* 0x00000004 */ +#define DSI_INT_ST1_ECC_MULTI_ERR_SHIFT (3U) +#define DSI_INT_ST1_ECC_MULTI_ERR_MASK (0x1U << DSI_INT_ST1_ECC_MULTI_ERR_SHIFT) /* 0x00000008 */ +#define DSI_INT_ST1_CRC_ERR_SHIFT (4U) +#define DSI_INT_ST1_CRC_ERR_MASK (0x1U << DSI_INT_ST1_CRC_ERR_SHIFT) /* 0x00000010 */ +#define DSI_INT_ST1_PKT_SIZE_ERR_SHIFT (5U) +#define DSI_INT_ST1_PKT_SIZE_ERR_MASK (0x1U << DSI_INT_ST1_PKT_SIZE_ERR_SHIFT) /* 0x00000020 */ +#define DSI_INT_ST1_EOPT_ERR_SHIFT (6U) +#define DSI_INT_ST1_EOPT_ERR_MASK (0x1U << DSI_INT_ST1_EOPT_ERR_SHIFT) /* 0x00000040 */ +#define DSI_INT_ST1_DPI_PLD_WR_ERR_SHIFT (7U) +#define DSI_INT_ST1_DPI_PLD_WR_ERR_MASK (0x1U << DSI_INT_ST1_DPI_PLD_WR_ERR_SHIFT) /* 0x00000080 */ +#define DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT (8U) +#define DSI_INT_ST1_GEN_CMD_WR_ERR_MASK (0x1U << DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT) /* 0x00000100 */ +#define DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT (9U) +#define DSI_INT_ST1_GEN_PLD_WR_ERR_MASK (0x1U << DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT) /* 0x00000200 */ +#define DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT (10U) +#define DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK (0x1U << DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT) /* 0x00000400 */ +#define DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT (11U) +#define DSI_INT_ST1_GEN_PLD_RD_ERR_MASK (0x1U << DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT) /* 0x00000800 */ +#define DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT (12U) +#define DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK (0x1U << DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT) /* 0x00001000 */ +#define DSI_INT_ST1_DBI_CMD_WR_ERR_SHIFT (13U) +#define DSI_INT_ST1_DBI_CMD_WR_ERR_MASK (0x1U << DSI_INT_ST1_DBI_CMD_WR_ERR_SHIFT) /* 0x00002000 */ +#define DSI_INT_ST1_DBI_PLD_WR_ERR_SHIFT (14U) +#define DSI_INT_ST1_DBI_PLD_WR_ERR_MASK (0x1U << DSI_INT_ST1_DBI_PLD_WR_ERR_SHIFT) /* 0x00004000 */ +#define DSI_INT_ST1_DBI_PLD_RD_ERR_SHIFT (15U) +#define DSI_INT_ST1_DBI_PLD_RD_ERR_MASK (0x1U << DSI_INT_ST1_DBI_PLD_RD_ERR_SHIFT) /* 0x00008000 */ +#define DSI_INT_ST1_DBI_PLD_RECV_ERR_SHIFT (16U) +#define DSI_INT_ST1_DBI_PLD_RECV_ERR_MASK (0x1U << DSI_INT_ST1_DBI_PLD_RECV_ERR_SHIFT) /* 0x00010000 */ +#define DSI_INT_ST1_DBI_ILEGAL_COMM_ERR_SHIFT (17U) +#define DSI_INT_ST1_DBI_ILEGAL_COMM_ERR_MASK (0x1U << DSI_INT_ST1_DBI_ILEGAL_COMM_ERR_SHIFT) /* 0x00020000 */ +/* INT_MSK0 */ +#define DSI_INT_MSK0_OFFSET (0xC4U) +#define DSI_INT_MSK0_ACK_WITH_ERR_0_SHIFT (0U) +#define DSI_INT_MSK0_ACK_WITH_ERR_0_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_0_SHIFT) /* 0x00000001 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_1_SHIFT (1U) +#define DSI_INT_MSK0_ACK_WITH_ERR_1_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_1_SHIFT) /* 0x00000002 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_2_SHIFT (2U) +#define DSI_INT_MSK0_ACK_WITH_ERR_2_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_2_SHIFT) /* 0x00000004 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_3_SHIFT (3U) +#define DSI_INT_MSK0_ACK_WITH_ERR_3_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_3_SHIFT) /* 0x00000008 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_4_SHIFT (4U) +#define DSI_INT_MSK0_ACK_WITH_ERR_4_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_4_SHIFT) /* 0x00000010 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_5_SHIFT (5U) +#define DSI_INT_MSK0_ACK_WITH_ERR_5_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_5_SHIFT) /* 0x00000020 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_6_SHIFT (6U) +#define DSI_INT_MSK0_ACK_WITH_ERR_6_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_6_SHIFT) /* 0x00000040 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_7_SHIFT (7U) +#define DSI_INT_MSK0_ACK_WITH_ERR_7_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_7_SHIFT) /* 0x00000080 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_8_SHIFT (8U) +#define DSI_INT_MSK0_ACK_WITH_ERR_8_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_8_SHIFT) /* 0x00000100 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_9_SHIFT (9U) +#define DSI_INT_MSK0_ACK_WITH_ERR_9_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_9_SHIFT) /* 0x00000200 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_10_SHIFT (10U) +#define DSI_INT_MSK0_ACK_WITH_ERR_10_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_10_SHIFT) /* 0x00000400 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_11_SHIFT (11U) +#define DSI_INT_MSK0_ACK_WITH_ERR_11_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_11_SHIFT) /* 0x00000800 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_12_SHIFT (12U) +#define DSI_INT_MSK0_ACK_WITH_ERR_12_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_12_SHIFT) /* 0x00001000 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_13_SHIFT (13U) +#define DSI_INT_MSK0_ACK_WITH_ERR_13_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_13_SHIFT) /* 0x00002000 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_14_SHIFT (14U) +#define DSI_INT_MSK0_ACK_WITH_ERR_14_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_14_SHIFT) /* 0x00004000 */ +#define DSI_INT_MSK0_ACK_WITH_ERR_15_SHIFT (15U) +#define DSI_INT_MSK0_ACK_WITH_ERR_15_MASK (0x1U << DSI_INT_MSK0_ACK_WITH_ERR_15_SHIFT) /* 0x00008000 */ +#define DSI_INT_MSK0_DPHY_ERRORS_0_SHIFT (16U) +#define DSI_INT_MSK0_DPHY_ERRORS_0_MASK (0x1U << DSI_INT_MSK0_DPHY_ERRORS_0_SHIFT) /* 0x00010000 */ +#define DSI_INT_MSK0_DPHY_ERRORS_1_SHIFT (17U) +#define DSI_INT_MSK0_DPHY_ERRORS_1_MASK (0x1U << DSI_INT_MSK0_DPHY_ERRORS_1_SHIFT) /* 0x00020000 */ +#define DSI_INT_MSK0_DPHY_ERRORS_2_SHIFT (18U) +#define DSI_INT_MSK0_DPHY_ERRORS_2_MASK (0x1U << DSI_INT_MSK0_DPHY_ERRORS_2_SHIFT) /* 0x00040000 */ +#define DSI_INT_MSK0_DPHY_ERRORS_3_SHIFT (19U) +#define DSI_INT_MSK0_DPHY_ERRORS_3_MASK (0x1U << DSI_INT_MSK0_DPHY_ERRORS_3_SHIFT) /* 0x00080000 */ +#define DSI_INT_MSK0_DPHY_ERRORS_4_SHIFT (20U) +#define DSI_INT_MSK0_DPHY_ERRORS_4_MASK (0x1U << DSI_INT_MSK0_DPHY_ERRORS_4_SHIFT) /* 0x00100000 */ +/* INT_MSK1 */ +#define DSI_INT_MSK1_OFFSET (0xC8U) +#define DSI_INT_MSK1_TO_HS_TX_SHIFT (0U) +#define DSI_INT_MSK1_TO_HS_TX_MASK (0x1U << DSI_INT_MSK1_TO_HS_TX_SHIFT) /* 0x00000001 */ +#define DSI_INT_MSK1_TO_LP_RX_SHIFT (1U) +#define DSI_INT_MSK1_TO_LP_RX_MASK (0x1U << DSI_INT_MSK1_TO_LP_RX_SHIFT) /* 0x00000002 */ +#define DSI_INT_MSK1_ECC_SINGLE_ERR_SHIFT (2U) +#define DSI_INT_MSK1_ECC_SINGLE_ERR_MASK (0x1U << DSI_INT_MSK1_ECC_SINGLE_ERR_SHIFT) /* 0x00000004 */ +#define DSI_INT_MSK1_ECC_MILTI_ERR_SHIFT (3U) +#define DSI_INT_MSK1_ECC_MILTI_ERR_MASK (0x1U << DSI_INT_MSK1_ECC_MILTI_ERR_SHIFT) /* 0x00000008 */ +#define DSI_INT_MSK1_CRC_ERR_SHIFT (4U) +#define DSI_INT_MSK1_CRC_ERR_MASK (0x1U << DSI_INT_MSK1_CRC_ERR_SHIFT) /* 0x00000010 */ +#define DSI_INT_MSK1_PKT_SIZE_ERR_SHIFT (5U) +#define DSI_INT_MSK1_PKT_SIZE_ERR_MASK (0x1U << DSI_INT_MSK1_PKT_SIZE_ERR_SHIFT) /* 0x00000020 */ +#define DSI_INT_MSK1_EOPT_ERR_SHIFT (6U) +#define DSI_INT_MSK1_EOPT_ERR_MASK (0x1U << DSI_INT_MSK1_EOPT_ERR_SHIFT) /* 0x00000040 */ +#define DSI_INT_MSK1_DPI_PLD_WR_ERR_SHIFT (7U) +#define DSI_INT_MSK1_DPI_PLD_WR_ERR_MASK (0x1U << DSI_INT_MSK1_DPI_PLD_WR_ERR_SHIFT) /* 0x00000080 */ +#define DSI_INT_MSK1_GEN_CMD_WR_ERR_SHIFT (8U) +#define DSI_INT_MSK1_GEN_CMD_WR_ERR_MASK (0x1U << DSI_INT_MSK1_GEN_CMD_WR_ERR_SHIFT) /* 0x00000100 */ +#define DSI_INT_MSK1_GEN_PLD_WR_ERR_SHIFT (9U) +#define DSI_INT_MSK1_GEN_PLD_WR_ERR_MASK (0x1U << DSI_INT_MSK1_GEN_PLD_WR_ERR_SHIFT) /* 0x00000200 */ +#define DSI_INT_MSK1_GEN_PLD_SEND_ERR_SHIFT (10U) +#define DSI_INT_MSK1_GEN_PLD_SEND_ERR_MASK (0x1U << DSI_INT_MSK1_GEN_PLD_SEND_ERR_SHIFT) /* 0x00000400 */ +#define DSI_INT_MSK1_GEN_PLD_RD_ERR_SHIFT (11U) +#define DSI_INT_MSK1_GEN_PLD_RD_ERR_MASK (0x1U << DSI_INT_MSK1_GEN_PLD_RD_ERR_SHIFT) /* 0x00000800 */ +#define DSI_INT_MSK1_GEN_PLD_REVEV_ERR_SHIFT (12U) +#define DSI_INT_MSK1_GEN_PLD_REVEV_ERR_MASK (0x1U << DSI_INT_MSK1_GEN_PLD_REVEV_ERR_SHIFT) /* 0x00001000 */ +#define DSI_INT_MSK1_DBI_CMD_WR_ERR_SHIFT (13U) +#define DSI_INT_MSK1_DBI_CMD_WR_ERR_MASK (0x1U << DSI_INT_MSK1_DBI_CMD_WR_ERR_SHIFT) /* 0x00002000 */ +#define DSI_INT_MSK1_DBI_PLD_WR_ERR_SHIFT (14U) +#define DSI_INT_MSK1_DBI_PLD_WR_ERR_MASK (0x1U << DSI_INT_MSK1_DBI_PLD_WR_ERR_SHIFT) /* 0x00004000 */ +#define DSI_INT_MSK1_DBI_PLD_RD_ERR_SHIFT (15U) +#define DSI_INT_MSK1_DBI_PLD_RD_ERR_MASK (0x1U << DSI_INT_MSK1_DBI_PLD_RD_ERR_SHIFT) /* 0x00008000 */ +#define DSI_INT_MSK1_DBI_PLD_RECV_ERR_SHIFT (16U) +#define DSI_INT_MSK1_DBI_PLD_RECV_ERR_MASK (0x1U << DSI_INT_MSK1_DBI_PLD_RECV_ERR_SHIFT) /* 0x00010000 */ +#define DSI_INT_MSK1_DBI_ILEGAL_COMM_ERR_SHIFT (17U) +#define DSI_INT_MSK1_DBI_ILEGAL_COMM_ERR_MASK (0x1U << DSI_INT_MSK1_DBI_ILEGAL_COMM_ERR_SHIFT) /* 0x00020000 */ +/* INT_FORCE0 */ +#define DSI_INT_FORCE0_OFFSET (0xD8U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_0_SHIFT (0U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_0_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_0_SHIFT) /* 0x00000001 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_1_SHIFT (1U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_1_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_1_SHIFT) /* 0x00000002 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_2_SHIFT (2U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_2_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_2_SHIFT) /* 0x00000004 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_3_SHIFT (3U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_3_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_3_SHIFT) /* 0x00000008 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_4_SHIFT (4U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_4_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_4_SHIFT) /* 0x00000010 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_5_SHIFT (5U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_5_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_5_SHIFT) /* 0x00000020 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_6_SHIFT (6U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_6_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_6_SHIFT) /* 0x00000040 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_7_SHIFT (7U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_7_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_7_SHIFT) /* 0x00000080 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_8_SHIFT (8U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_8_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_8_SHIFT) /* 0x00000100 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_9_SHIFT (9U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_9_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_9_SHIFT) /* 0x00000200 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_10_SHIFT (10U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_10_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_10_SHIFT) /* 0x00000400 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_11_SHIFT (11U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_11_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_11_SHIFT) /* 0x00000800 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_12_SHIFT (12U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_12_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_12_SHIFT) /* 0x00001000 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_13_SHIFT (13U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_13_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_13_SHIFT) /* 0x00002000 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_14_SHIFT (14U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_14_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_14_SHIFT) /* 0x00004000 */ +#define DSI_INT_FORCE0_ACK_WITH_ERR_15_SHIFT (15U) +#define DSI_INT_FORCE0_ACK_WITH_ERR_15_MASK (0x1U << DSI_INT_FORCE0_ACK_WITH_ERR_15_SHIFT) /* 0x00008000 */ +#define DSI_INT_FORCE0_DPHY_ERRORS_0_SHIFT (16U) +#define DSI_INT_FORCE0_DPHY_ERRORS_0_MASK (0x1U << DSI_INT_FORCE0_DPHY_ERRORS_0_SHIFT) /* 0x00010000 */ +#define DSI_INT_FORCE0_DPHY_ERRORS_1_SHIFT (17U) +#define DSI_INT_FORCE0_DPHY_ERRORS_1_MASK (0x1U << DSI_INT_FORCE0_DPHY_ERRORS_1_SHIFT) /* 0x00020000 */ +#define DSI_INT_FORCE0_DPHY_ERRORS_2_SHIFT (18U) +#define DSI_INT_FORCE0_DPHY_ERRORS_2_MASK (0x1U << DSI_INT_FORCE0_DPHY_ERRORS_2_SHIFT) /* 0x00040000 */ +#define DSI_INT_FORCE0_DPHY_ERRORS_3_SHIFT (19U) +#define DSI_INT_FORCE0_DPHY_ERRORS_3_MASK (0x1U << DSI_INT_FORCE0_DPHY_ERRORS_3_SHIFT) /* 0x00080000 */ +#define DSI_INT_FORCE0_DPHY_ERRORS_4_SHIFT (20U) +#define DSI_INT_FORCE0_DPHY_ERRORS_4_MASK (0x1U << DSI_INT_FORCE0_DPHY_ERRORS_4_SHIFT) /* 0x00100000 */ +/* INT_FORCE1 */ +#define DSI_INT_FORCE1_OFFSET (0xDCU) +#define DSI_INT_FORCE1_TO_HS_TX_SHIFT (0U) +#define DSI_INT_FORCE1_TO_HS_TX_MASK (0x1U << DSI_INT_FORCE1_TO_HS_TX_SHIFT) /* 0x00000001 */ +#define DSI_INT_FORCE1_TO_LP_RX_SHIFT (1U) +#define DSI_INT_FORCE1_TO_LP_RX_MASK (0x1U << DSI_INT_FORCE1_TO_LP_RX_SHIFT) /* 0x00000002 */ +#define DSI_INT_FORCE1_ECC_SINGLE_ERR_SHIFT (2U) +#define DSI_INT_FORCE1_ECC_SINGLE_ERR_MASK (0x1U << DSI_INT_FORCE1_ECC_SINGLE_ERR_SHIFT) /* 0x00000004 */ +#define DSI_INT_FORCE1_ECC_MILTI_ERR_SHIFT (3U) +#define DSI_INT_FORCE1_ECC_MILTI_ERR_MASK (0x1U << DSI_INT_FORCE1_ECC_MILTI_ERR_SHIFT) /* 0x00000008 */ +#define DSI_INT_FORCE1_CRC_ERR_OR_RESERVED_SHIFT (4U) +#define DSI_INT_FORCE1_CRC_ERR_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_CRC_ERR_OR_RESERVED_SHIFT) /* 0x00000010 */ +#define DSI_INT_FORCE1_PKT_SIZE_ERR_SHIFT (5U) +#define DSI_INT_FORCE1_PKT_SIZE_ERR_MASK (0x1U << DSI_INT_FORCE1_PKT_SIZE_ERR_SHIFT) /* 0x00000020 */ +#define DSI_INT_FORCE1_EOPT_ERR_SHIFT (6U) +#define DSI_INT_FORCE1_EOPT_ERR_MASK (0x1U << DSI_INT_FORCE1_EOPT_ERR_SHIFT) /* 0x00000040 */ +#define DSI_INT_FORCE1_DPI_PLD_WR_ERR_OR_RESERVED_SHIFT (7U) +#define DSI_INT_FORCE1_DPI_PLD_WR_ERR_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_DPI_PLD_WR_ERR_OR_RESERVED_SHIFT) /* 0x00000080 */ +#define DSI_INT_FORCE1_GEN_CMD_WR_ERR_OR_RESERVED_SHIFT (8U) +#define DSI_INT_FORCE1_GEN_CMD_WR_ERR_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_GEN_CMD_WR_ERR_OR_RESERVED_SHIFT) /* 0x00000100 */ +#define DSI_INT_FORCE1_GEN_PLD_WR_EN_OR_RESERVED_SHIFT (9U) +#define DSI_INT_FORCE1_GEN_PLD_WR_EN_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_GEN_PLD_WR_EN_OR_RESERVED_SHIFT) /* 0x00000200 */ +#define DSI_INT_FORCE1_GEN_PLD_SEND_ERR_OR_RESERVE_SHIFT (10U) +#define DSI_INT_FORCE1_GEN_PLD_SEND_ERR_OR_RESERVE_MASK (0x1U << DSI_INT_FORCE1_GEN_PLD_SEND_ERR_OR_RESERVE_SHIFT) /* 0x00000400 */ +#define DSI_INT_FORCE1_GEN_PLD_RD_ERR_OR_RESERVED_SHIFT (11U) +#define DSI_INT_FORCE1_GEN_PLD_RD_ERR_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_GEN_PLD_RD_ERR_OR_RESERVED_SHIFT) /* 0x00000800 */ +#define DSI_INT_FORCE1_GEN_PLD_RECEV_ERR_OR_RESERVED_SHIFT (12U) +#define DSI_INT_FORCE1_GEN_PLD_RECEV_ERR_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_GEN_PLD_RECEV_ERR_OR_RESERVED_SHIFT) /* 0x00001000 */ +#define DSI_INT_FORCE1_DBI_CMD_WR_ERR_OR_RESERVED_SHIFT (13U) +#define DSI_INT_FORCE1_DBI_CMD_WR_ERR_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_DBI_CMD_WR_ERR_OR_RESERVED_SHIFT) /* 0x00002000 */ +#define DSI_INT_FORCE1_DBI_PLD_WR_ERR_OR_RESERVED_SHIFT (14U) +#define DSI_INT_FORCE1_DBI_PLD_WR_ERR_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_DBI_PLD_WR_ERR_OR_RESERVED_SHIFT) /* 0x00004000 */ +#define DSI_INT_FORCE1_DBI_PLD_RD_ERR_OR_RESERVED_SHIFT (15U) +#define DSI_INT_FORCE1_DBI_PLD_RD_ERR_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_DBI_PLD_RD_ERR_OR_RESERVED_SHIFT) /* 0x00008000 */ +#define DSI_INT_FORCE1_DBI_PLD_RECV_ERR_OR_RESERVED_SHIFT (16U) +#define DSI_INT_FORCE1_DBI_PLD_RECV_ERR_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_DBI_PLD_RECV_ERR_OR_RESERVED_SHIFT) /* 0x00010000 */ +#define DSI_INT_FORCE1_DBI_ILEGAL_COMM_ERR_OR_RESERVED_SHIFT (17U) +#define DSI_INT_FORCE1_DBI_ILEGAL_COMM_ERR_OR_RESERVED_MASK (0x1U << DSI_INT_FORCE1_DBI_ILEGAL_COMM_ERR_OR_RESERVED_SHIFT) /* 0x00020000 */ +/* VID_SHADOW_CTRL */ +#define DSI_VID_SHADOW_CTRL_OFFSET (0x100U) +#define DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT (0U) +#define DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK (0x1U << DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) /* 0x00000001 */ +#define DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT (8U) +#define DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK (0x1U << DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) /* 0x00000100 */ +#define DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT (16U) +#define DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK (0x1U << DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) /* 0x00010000 */ +/* DPI_VCID_ACT */ +#define DSI_DPI_VCID_ACT_OFFSET (0x10CU) +#define DSI_DPI_VCID_ACT (0x0U) +#define DSI_DPI_VCID_ACT_DPI_VCID_SHIFT (0U) +#define DSI_DPI_VCID_ACT_DPI_VCID_MASK (0x3U << DSI_DPI_VCID_ACT_DPI_VCID_SHIFT) /* 0x00000003 */ +/* DPI_COLOR_CODING_ACT */ +#define DSI_DPI_COLOR_CODING_ACT_OFFSET (0x110U) +#define DSI_DPI_COLOR_CODING_ACT (0x0U) +#define DSI_DPI_COLOR_CODING_ACT_DPI_COLOR_CODING_SHIFT (0U) +#define DSI_DPI_COLOR_CODING_ACT_DPI_COLOR_CODING_MASK (0xFU << DSI_DPI_COLOR_CODING_ACT_DPI_COLOR_CODING_SHIFT) /* 0x0000000F */ +#define DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT (8U) +#define DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK (0x1U << DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT) /* 0x00000100 */ +/* DPI_LP_CMD_TIM_ACT */ +#define DSI_DPI_LP_CMD_TIM_ACT_OFFSET (0x118U) +#define DSI_DPI_LP_CMD_TIM_ACT (0x0U) +#define DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT (0U) +#define DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK (0xFFU << DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT) /* 0x000000FF */ +#define DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT (16U) +#define DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK (0xFFU << DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT) /* 0x00FF0000 */ +/* VID_MODE_CFG_ACT */ +#define DSI_VID_MODE_CFG_ACT_OFFSET (0x138U) +#define DSI_VID_MODE_CFG_ACT (0x0U) +#define DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT (0U) +#define DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK (0x3U << DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT) /* 0x00000003 */ +#define DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT (8U) +#define DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK (0x1U << DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT) /* 0x00000100 */ +#define DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT (9U) +#define DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK (0x1U << DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT) /* 0x00000200 */ +#define DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT (10U) +#define DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK (0x1U << DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT) /* 0x00000400 */ +#define DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT (11U) +#define DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK (0x1U << DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT) /* 0x00000800 */ +#define DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT (12U) +#define DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK (0x1U << DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT) /* 0x00001000 */ +#define DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT (13U) +#define DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK (0x1U << DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT) /* 0x00002000 */ +#define DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT (14U) +#define DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK (0x1U << DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT) /* 0x00004000 */ +#define DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT (15U) +#define DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK (0x1U << DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT) /* 0x00008000 */ +/* VID_PKT_SIZE_ACT */ +#define DSI_VID_PKT_SIZE_ACT_OFFSET (0x13CU) +#define DSI_VID_PKT_SIZE_ACT (0x0U) +#define DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT (0U) +#define DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK (0x3FFFU << DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT) /* 0x00003FFF */ +/* VID_NUM_CHUNKS_ACT */ +#define DSI_VID_NUM_CHUNKS_ACT_OFFSET (0x140U) +#define DSI_VID_NUM_CHUNKS_ACT (0x0U) +#define DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT (0U) +#define DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK (0x1FFFU << DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT) /* 0x00001FFF */ +/* VID_NULL_SIZE_ACT */ +#define DSI_VID_NULL_SIZE_ACT_OFFSET (0x144U) +#define DSI_VID_NULL_SIZE_ACT (0x0U) +#define DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT (0U) +#define DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK (0x1FFFU << DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT) /* 0x00001FFF */ +/* VID_HSA_TIME_ACT */ +#define DSI_VID_HSA_TIME_ACT_OFFSET (0x148U) +#define DSI_VID_HSA_TIME_ACT (0x0U) +#define DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT (0U) +#define DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK (0xFFFU << DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT) /* 0x00000FFF */ +/* VID_HBP_TIME_ACT */ +#define DSI_VID_HBP_TIME_ACT_OFFSET (0x14CU) +#define DSI_VID_HBP_TIME_ACT (0x0U) +#define DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT (0U) +#define DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK (0xFFFU << DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT) /* 0x00000FFF */ +/* VID_HLINE_TIME_ACT */ +#define DSI_VID_HLINE_TIME_ACT_OFFSET (0x150U) +#define DSI_VID_HLINE_TIME_ACT (0x0U) +#define DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT (0U) +#define DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK (0x7FFFU << DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT) /* 0x00007FFF */ +/* VID_VSA_LINES_ACT */ +#define DSI_VID_VSA_LINES_ACT_OFFSET (0x154U) +#define DSI_VID_VSA_LINES_ACT (0x0U) +#define DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT (0U) +#define DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK (0x3FFU << DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT) /* 0x000003FF */ +/* VID_VBP_LINES_ACT */ +#define DSI_VID_VBP_LINES_ACT_OFFSET (0x158U) +#define DSI_VID_VBP_LINES_ACT (0x0U) +#define DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT (0U) +#define DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK (0x3FFU << DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT) /* 0x000003FF */ +/* VID_VFP_LINES_ACT */ +#define DSI_VID_VFP_LINES_ACT_OFFSET (0x15CU) +#define DSI_VID_VFP_LINES_ACT (0x0U) +#define DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT (0U) +#define DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK (0x3FFU << DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT) /* 0x000003FF */ +/* VID_VACTIVE_LINES_ACT */ +#define DSI_VID_VACTIVE_LINES_ACT_OFFSET (0x160U) +#define DSI_VID_VACTIVE_LINES_ACT (0x0U) +#define DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT (0U) +#define DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK (0x3FFFU << DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT) /* 0x00003FFF */ +/* SDF_3D_ACT */ +#define DSI_SDF_3D_ACT_OFFSET (0x190U) +#define DSI_SDF_3D_ACT_MODE_3D_SHIFT (0U) +#define DSI_SDF_3D_ACT_MODE_3D_MASK (0x3U << DSI_SDF_3D_ACT_MODE_3D_SHIFT) /* 0x00000003 */ +#define DSI_SDF_3D_ACT_FORMAT_3D_SHIFT (2U) +#define DSI_SDF_3D_ACT_FORMAT_3D_MASK (0x3U << DSI_SDF_3D_ACT_FORMAT_3D_SHIFT) /* 0x0000000C */ +#define DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT (4U) +#define DSI_SDF_3D_ACT_SECOND_VSYNC_MASK (0x1U << DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT) /* 0x00000010 */ +#define DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT (5U) +#define DSI_SDF_3D_ACT_RIGHT_FIRST_MASK (0x1U << DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT) /* 0x00000020 */ +#define DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT (16U) +#define DSI_SDF_3D_ACT_SEND_3D_CFG_MASK (0x1U << DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT) /* 0x00010000 */ +/*****************************************VICAP******************************************/ +/* DVP_CTRL */ +#define VICAP_DVP_CTRL_OFFSET (0x0U) +#define VICAP_DVP_CTRL_CAP_EN_SHIFT (0U) +#define VICAP_DVP_CTRL_CAP_EN_MASK (0x1U << VICAP_DVP_CTRL_CAP_EN_SHIFT) /* 0x00000001 */ +#define VICAP_DVP_CTRL_WORK_MODE_SHIFT (1U) +#define VICAP_DVP_CTRL_WORK_MODE_MASK (0x3U << VICAP_DVP_CTRL_WORK_MODE_SHIFT) /* 0x00000006 */ +#define VICAP_DVP_CTRL_AXI_BURST_TYPE_SHIFT (12U) +#define VICAP_DVP_CTRL_AXI_BURST_TYPE_MASK (0xFU << VICAP_DVP_CTRL_AXI_BURST_TYPE_SHIFT) /* 0x0000F000 */ +/* DVP_INTEN */ +#define VICAP_DVP_INTEN_OFFSET (0x4U) +#define VICAP_DVP_INTEN_DMA_FRAME_END_EN_SHIFT (0U) +#define VICAP_DVP_INTEN_DMA_FRAME_END_EN_MASK (0x1U << VICAP_DVP_INTEN_DMA_FRAME_END_EN_SHIFT) /* 0x00000001 */ +#define VICAP_DVP_INTEN_LINE_END_EN_SHIFT (1U) +#define VICAP_DVP_INTEN_LINE_END_EN_MASK (0x1U << VICAP_DVP_INTEN_LINE_END_EN_SHIFT) /* 0x00000002 */ +#define VICAP_DVP_INTEN_LINE_ERR_EN_SHIFT (2U) +#define VICAP_DVP_INTEN_LINE_ERR_EN_MASK (0x1U << VICAP_DVP_INTEN_LINE_ERR_EN_SHIFT) /* 0x00000004 */ +#define VICAP_DVP_INTEN_PIX_ERR_EN_SHIFT (3U) +#define VICAP_DVP_INTEN_PIX_ERR_EN_MASK (0x1U << VICAP_DVP_INTEN_PIX_ERR_EN_SHIFT) /* 0x00000008 */ +#define VICAP_DVP_INTEN_IFIFO_OF_EN_SHIFT (4U) +#define VICAP_DVP_INTEN_IFIFO_OF_EN_MASK (0x1U << VICAP_DVP_INTEN_IFIFO_OF_EN_SHIFT) /* 0x00000010 */ +#define VICAP_DVP_INTEN_DFIFO_OF_EN_SHIFT (5U) +#define VICAP_DVP_INTEN_DFIFO_OF_EN_MASK (0x1U << VICAP_DVP_INTEN_DFIFO_OF_EN_SHIFT) /* 0x00000020 */ +#define VICAP_DVP_INTEN_BUS_ERR_EN_SHIFT (6U) +#define VICAP_DVP_INTEN_BUS_ERR_EN_MASK (0x1U << VICAP_DVP_INTEN_BUS_ERR_EN_SHIFT) /* 0x00000040 */ +#define VICAP_DVP_INTEN_FRAME_START_EN_SHIFT (7U) +#define VICAP_DVP_INTEN_FRAME_START_EN_MASK (0x1U << VICAP_DVP_INTEN_FRAME_START_EN_SHIFT) /* 0x00000080 */ +#define VICAP_DVP_INTEN_PRE_INF_FRAME_END_EN_SHIFT (8U) +#define VICAP_DVP_INTEN_PRE_INF_FRAME_END_EN_MASK (0x1U << VICAP_DVP_INTEN_PRE_INF_FRAME_END_EN_SHIFT) /* 0x00000100 */ +#define VICAP_DVP_INTEN_PST_INF_FRAME_END_EN_SHIFT (9U) +#define VICAP_DVP_INTEN_PST_INF_FRAME_END_EN_MASK (0x1U << VICAP_DVP_INTEN_PST_INF_FRAME_END_EN_SHIFT) /* 0x00000200 */ +#define VICAP_DVP_INTEN_BLOCK0_END_EN_SHIFT (10U) +#define VICAP_DVP_INTEN_BLOCK0_END_EN_MASK (0x1U << VICAP_DVP_INTEN_BLOCK0_END_EN_SHIFT) /* 0x00000400 */ +#define VICAP_DVP_INTEN_BLOCK1_END_EN_SHIFT (11U) +#define VICAP_DVP_INTEN_BLOCK1_END_EN_MASK (0x1U << VICAP_DVP_INTEN_BLOCK1_END_EN_SHIFT) /* 0x00000800 */ +#define VICAP_DVP_INTEN_LINE0_END_EN_SHIFT (12U) +#define VICAP_DVP_INTEN_LINE0_END_EN_MASK (0x1U << VICAP_DVP_INTEN_LINE0_END_EN_SHIFT) /* 0x00001000 */ +#define VICAP_DVP_INTEN_LINE1_END_EN_SHIFT (13U) +#define VICAP_DVP_INTEN_LINE1_END_EN_MASK (0x1U << VICAP_DVP_INTEN_LINE1_END_EN_SHIFT) /* 0x00002000 */ +#define VICAP_DVP_INTEN_BLOCK_ERR_EN_SHIFT (14U) +#define VICAP_DVP_INTEN_BLOCK_ERR_EN_MASK (0x1U << VICAP_DVP_INTEN_BLOCK_ERR_EN_SHIFT) /* 0x00004000 */ +/* DVP_INTSTAT */ +#define VICAP_DVP_INTSTAT_OFFSET (0x8U) +#define VICAP_DVP_INTSTAT_DMA_FRAME_END_SHIFT (0U) +#define VICAP_DVP_INTSTAT_DMA_FRAME_END_MASK (0x1U << VICAP_DVP_INTSTAT_DMA_FRAME_END_SHIFT) /* 0x00000001 */ +#define VICAP_DVP_INTSTAT_LINE_END_SHIFT (1U) +#define VICAP_DVP_INTSTAT_LINE_END_MASK (0x1U << VICAP_DVP_INTSTAT_LINE_END_SHIFT) /* 0x00000002 */ +#define VICAP_DVP_INTSTAT_LINE_ERR_SHIFT (2U) +#define VICAP_DVP_INTSTAT_LINE_ERR_MASK (0x1U << VICAP_DVP_INTSTAT_LINE_ERR_SHIFT) /* 0x00000004 */ +#define VICAP_DVP_INTSTAT_PIX_ERR_SHIFT (3U) +#define VICAP_DVP_INTSTAT_PIX_ERR_MASK (0x1U << VICAP_DVP_INTSTAT_PIX_ERR_SHIFT) /* 0x00000008 */ +#define VICAP_DVP_INTSTAT_IFIFO_OF_SHIFT (4U) +#define VICAP_DVP_INTSTAT_IFIFO_OF_MASK (0x1U << VICAP_DVP_INTSTAT_IFIFO_OF_SHIFT) /* 0x00000010 */ +#define VICAP_DVP_INTSTAT_DFIFO_OF_SHIFT (5U) +#define VICAP_DVP_INTSTAT_DFIFO_OF_MASK (0x1U << VICAP_DVP_INTSTAT_DFIFO_OF_SHIFT) /* 0x00000020 */ +#define VICAP_DVP_INTSTAT_BUS_ERR_SHIFT (6U) +#define VICAP_DVP_INTSTAT_BUS_ERR_MASK (0x1U << VICAP_DVP_INTSTAT_BUS_ERR_SHIFT) /* 0x00000040 */ +#define VICAP_DVP_INTSTAT_FRAME_START_SHIFT (7U) +#define VICAP_DVP_INTSTAT_FRAME_START_MASK (0x1U << VICAP_DVP_INTSTAT_FRAME_START_SHIFT) /* 0x00000080 */ +#define VICAP_DVP_INTSTAT_PRE_INF_FRAME_END_SHIFT (8U) +#define VICAP_DVP_INTSTAT_PRE_INF_FRAME_END_MASK (0x1U << VICAP_DVP_INTSTAT_PRE_INF_FRAME_END_SHIFT) /* 0x00000100 */ +#define VICAP_DVP_INTSTAT_PST_INF_FRAME_END_SHIFT (9U) +#define VICAP_DVP_INTSTAT_PST_INF_FRAME_END_MASK (0x1U << VICAP_DVP_INTSTAT_PST_INF_FRAME_END_SHIFT) /* 0x00000200 */ +#define VICAP_DVP_INTSTAT_BLOCK0_END_SHIFT (10U) +#define VICAP_DVP_INTSTAT_BLOCK0_END_MASK (0x1U << VICAP_DVP_INTSTAT_BLOCK0_END_SHIFT) /* 0x00000400 */ +#define VICAP_DVP_INTSTAT_BLOCK1_END_SHIFT (11U) +#define VICAP_DVP_INTSTAT_BLOCK1_END_MASK (0x1U << VICAP_DVP_INTSTAT_BLOCK1_END_SHIFT) /* 0x00000800 */ +#define VICAP_DVP_INTSTAT_LINE0_END_SHIFT (12U) +#define VICAP_DVP_INTSTAT_LINE0_END_MASK (0x1U << VICAP_DVP_INTSTAT_LINE0_END_SHIFT) /* 0x00001000 */ +#define VICAP_DVP_INTSTAT_LINE1_END_SHIFT (13U) +#define VICAP_DVP_INTSTAT_LINE1_END_MASK (0x1U << VICAP_DVP_INTSTAT_LINE1_END_SHIFT) /* 0x00002000 */ +#define VICAP_DVP_INTSTAT_BLOCK_ERR_SHIFT (14U) +#define VICAP_DVP_INTSTAT_BLOCK_ERR_MASK (0x1U << VICAP_DVP_INTSTAT_BLOCK_ERR_SHIFT) /* 0x00004000 */ +/* DVP_FOR */ +#define VICAP_DVP_FOR_OFFSET (0xCU) +#define VICAP_DVP_FOR_VSYNC_POL_SHIFT (0U) +#define VICAP_DVP_FOR_VSYNC_POL_MASK (0x1U << VICAP_DVP_FOR_VSYNC_POL_SHIFT) /* 0x00000001 */ +#define VICAP_DVP_FOR_HREF_POL_SHIFT (1U) +#define VICAP_DVP_FOR_HREF_POL_MASK (0x1U << VICAP_DVP_FOR_HREF_POL_SHIFT) /* 0x00000002 */ +#define VICAP_DVP_FOR_INPUT_MODE_SHIFT (2U) +#define VICAP_DVP_FOR_INPUT_MODE_MASK (0x7U << VICAP_DVP_FOR_INPUT_MODE_SHIFT) /* 0x0000001C */ +#define VICAP_DVP_FOR_YUV_IN_ORDER_SHIFT (5U) +#define VICAP_DVP_FOR_YUV_IN_ORDER_MASK (0x3U << VICAP_DVP_FOR_YUV_IN_ORDER_SHIFT) /* 0x00000060 */ +#define VICAP_DVP_FOR_FIELD_ORDER_SHIFT (9U) +#define VICAP_DVP_FOR_FIELD_ORDER_MASK (0x1U << VICAP_DVP_FOR_FIELD_ORDER_SHIFT) /* 0x00000200 */ +#define VICAP_DVP_FOR_JPEG_MODE_SHIFT (10U) +#define VICAP_DVP_FOR_JPEG_MODE_MASK (0x1U << VICAP_DVP_FOR_JPEG_MODE_SHIFT) /* 0x00000400 */ +#define VICAP_DVP_FOR_RAW_WIDTH_SHIFT (11U) +#define VICAP_DVP_FOR_RAW_WIDTH_MASK (0x3U << VICAP_DVP_FOR_RAW_WIDTH_SHIFT) /* 0x00001800 */ +#define VICAP_DVP_FOR_ONLY_Y_MODE_SHIFT (15U) +#define VICAP_DVP_FOR_ONLY_Y_MODE_MASK (0x1U << VICAP_DVP_FOR_ONLY_Y_MODE_SHIFT) /* 0x00008000 */ +#define VICAP_DVP_FOR_OUTPUT_420_SHIFT (16U) +#define VICAP_DVP_FOR_OUTPUT_420_MASK (0x1U << VICAP_DVP_FOR_OUTPUT_420_SHIFT) /* 0x00010000 */ +#define VICAP_DVP_FOR_OUT_420_ORDER_SHIFT (17U) +#define VICAP_DVP_FOR_OUT_420_ORDER_MASK (0x1U << VICAP_DVP_FOR_OUT_420_ORDER_SHIFT) /* 0x00020000 */ +#define VICAP_DVP_FOR_RAW_END_SHIFT (18U) +#define VICAP_DVP_FOR_RAW_END_MASK (0x1U << VICAP_DVP_FOR_RAW_END_SHIFT) /* 0x00040000 */ +#define VICAP_DVP_FOR_UV_STORE_ORDER_SHIFT (19U) +#define VICAP_DVP_FOR_UV_STORE_ORDER_MASK (0x1U << VICAP_DVP_FOR_UV_STORE_ORDER_SHIFT) /* 0x00080000 */ +#define VICAP_DVP_FOR_HSYNC_MODE_SHIFT (20U) +#define VICAP_DVP_FOR_HSYNC_MODE_MASK (0x1U << VICAP_DVP_FOR_HSYNC_MODE_SHIFT) /* 0x00100000 */ +/* DVP_DMA_IDLE_REQ */ +#define VICAP_DVP_DMA_IDLE_REQ_OFFSET (0x10U) +#define VICAP_DVP_DMA_IDLE_REQ_DMA_IDLE_REQ_SHIFT (0U) +#define VICAP_DVP_DMA_IDLE_REQ_DMA_IDLE_REQ_MASK (0x1U << VICAP_DVP_DMA_IDLE_REQ_DMA_IDLE_REQ_SHIFT) /* 0x00000001 */ +/* DVP_FRM0_ADDR_Y */ +#define VICAP_DVP_FRM0_ADDR_Y_OFFSET (0x14U) +#define VICAP_DVP_FRM0_ADDR_Y_FRM0_ADDR_Y_SHIFT (0U) +#define VICAP_DVP_FRM0_ADDR_Y_FRM0_ADDR_Y_MASK (0xFFFFFFFFU << VICAP_DVP_FRM0_ADDR_Y_FRM0_ADDR_Y_SHIFT) /* 0xFFFFFFFF */ +/* DVP_FRM0_ADDR_UV */ +#define VICAP_DVP_FRM0_ADDR_UV_OFFSET (0x18U) +#define VICAP_DVP_FRM0_ADDR_UV_FRM0_ADDR_UV_SHIFT (0U) +#define VICAP_DVP_FRM0_ADDR_UV_FRM0_ADDR_UV_MASK (0xFFFFFFFFU << VICAP_DVP_FRM0_ADDR_UV_FRM0_ADDR_UV_SHIFT) /* 0xFFFFFFFF */ +/* DVP_FRM1_ADDR_Y */ +#define VICAP_DVP_FRM1_ADDR_Y_OFFSET (0x1CU) +#define VICAP_DVP_FRM1_ADDR_Y_FRM1_ADDR_Y_SHIFT (0U) +#define VICAP_DVP_FRM1_ADDR_Y_FRM1_ADDR_Y_MASK (0xFFFFFFFFU << VICAP_DVP_FRM1_ADDR_Y_FRM1_ADDR_Y_SHIFT) /* 0xFFFFFFFF */ +/* DVP_FRM1_ADDR_UV */ +#define VICAP_DVP_FRM1_ADDR_UV_OFFSET (0x20U) +#define VICAP_DVP_FRM1_ADDR_UV_FRM1_ADDR_UV_SHIFT (0U) +#define VICAP_DVP_FRM1_ADDR_UV_FRM1_ADDR_UV_MASK (0xFFFFFFFFU << VICAP_DVP_FRM1_ADDR_UV_FRM1_ADDR_UV_SHIFT) /* 0xFFFFFFFF */ +/* DVP_VIR_LINE_WIDTH */ +#define VICAP_DVP_VIR_LINE_WIDTH_OFFSET (0x24U) +#define VICAP_DVP_VIR_LINE_WIDTH_VIR_LINE_WIDTH_SHIFT (0U) +#define VICAP_DVP_VIR_LINE_WIDTH_VIR_LINE_WIDTH_MASK (0x7FFFU << VICAP_DVP_VIR_LINE_WIDTH_VIR_LINE_WIDTH_SHIFT) /* 0x00007FFF */ +/* DVP_SET_SIZE */ +#define VICAP_DVP_SET_SIZE_OFFSET (0x28U) +#define VICAP_DVP_SET_SIZE_SET_WIDTH_SHIFT (0U) +#define VICAP_DVP_SET_SIZE_SET_WIDTH_MASK (0x1FFFU << VICAP_DVP_SET_SIZE_SET_WIDTH_SHIFT) /* 0x00001FFF */ +#define VICAP_DVP_SET_SIZE_SET_HEIGHT_SHIFT (16U) +#define VICAP_DVP_SET_SIZE_SET_HEIGHT_MASK (0x1FFFU << VICAP_DVP_SET_SIZE_SET_HEIGHT_SHIFT) /* 0x1FFF0000 */ +/* DVP_BLOCK_LINE_NUM */ +#define VICAP_DVP_BLOCK_LINE_NUM_OFFSET (0x2CU) +#define VICAP_DVP_BLOCK_LINE_NUM_BLOCK_LINE_NUM_SHIFT (0U) +#define VICAP_DVP_BLOCK_LINE_NUM_BLOCK_LINE_NUM_MASK (0x1FFFU << VICAP_DVP_BLOCK_LINE_NUM_BLOCK_LINE_NUM_SHIFT) /* 0x00001FFF */ +/* DVP_BLOCK0_ADDR_Y */ +#define VICAP_DVP_BLOCK0_ADDR_Y_OFFSET (0x30U) +#define VICAP_DVP_BLOCK0_ADDR_Y_BLOCK0_ADDR_Y_SHIFT (0U) +#define VICAP_DVP_BLOCK0_ADDR_Y_BLOCK0_ADDR_Y_MASK (0xFFFFFFFFU << VICAP_DVP_BLOCK0_ADDR_Y_BLOCK0_ADDR_Y_SHIFT) /* 0xFFFFFFFF */ +/* DVP_BLOCK0_ADDR_UV */ +#define VICAP_DVP_BLOCK0_ADDR_UV_OFFSET (0x34U) +#define VICAP_DVP_BLOCK0_ADDR_UV_BLOCK0_ADDR_UV_SHIFT (0U) +#define VICAP_DVP_BLOCK0_ADDR_UV_BLOCK0_ADDR_UV_MASK (0xFFFFFFFFU << VICAP_DVP_BLOCK0_ADDR_UV_BLOCK0_ADDR_UV_SHIFT) /* 0xFFFFFFFF */ +/* DVP_BLOCK1_ADDR_Y */ +#define VICAP_DVP_BLOCK1_ADDR_Y_OFFSET (0x38U) +#define VICAP_DVP_BLOCK1_ADDR_Y_BLOCK1_ADDR_Y_SHIFT (0U) +#define VICAP_DVP_BLOCK1_ADDR_Y_BLOCK1_ADDR_Y_MASK (0xFFFFFFFFU << VICAP_DVP_BLOCK1_ADDR_Y_BLOCK1_ADDR_Y_SHIFT) /* 0xFFFFFFFF */ +/* DVP_BLOCK1_ADDR_UV */ +#define VICAP_DVP_BLOCK1_ADDR_UV_OFFSET (0x3CU) +#define VICAP_DVP_BLOCK1_ADDR_UV_BLOCK1_ADDR_UV_SHIFT (0U) +#define VICAP_DVP_BLOCK1_ADDR_UV_BLOCK1_ADDR_UV_MASK (0xFFFFFFFFU << VICAP_DVP_BLOCK1_ADDR_UV_BLOCK1_ADDR_UV_SHIFT) /* 0xFFFFFFFF */ +/* DVP_BLOCK_STATUS */ +#define VICAP_DVP_BLOCK_STATUS_OFFSET (0x40U) +#define VICAP_DVP_BLOCK_STATUS_BLK0_STATUS_SHIFT (0U) +#define VICAP_DVP_BLOCK_STATUS_BLK0_STATUS_MASK (0x1U << VICAP_DVP_BLOCK_STATUS_BLK0_STATUS_SHIFT) /* 0x00000001 */ +#define VICAP_DVP_BLOCK_STATUS_BLK1_STATUS_SHIFT (1U) +#define VICAP_DVP_BLOCK_STATUS_BLK1_STATUS_MASK (0x1U << VICAP_DVP_BLOCK_STATUS_BLK1_STATUS_SHIFT) /* 0x00000002 */ +#define VICAP_DVP_BLOCK_STATUS_BLK_ID_SHIFT (16U) +#define VICAP_DVP_BLOCK_STATUS_BLK_ID_MASK (0xFFU << VICAP_DVP_BLOCK_STATUS_BLK_ID_SHIFT) /* 0x00FF0000 */ +/* DVP_CROP */ +#define VICAP_DVP_CROP_OFFSET (0x44U) +#define VICAP_DVP_CROP_START_X_SHIFT (0U) +#define VICAP_DVP_CROP_START_X_MASK (0x1FFFU << VICAP_DVP_CROP_START_X_SHIFT) /* 0x00001FFF */ +#define VICAP_DVP_CROP_START_Y_SHIFT (16U) +#define VICAP_DVP_CROP_START_Y_MASK (0x1FFFU << VICAP_DVP_CROP_START_Y_SHIFT) /* 0x1FFF0000 */ +/* DVP_PATH_SEL */ +#define VICAP_DVP_PATH_SEL_OFFSET (0x48U) +#define VICAP_DVP_PATH_SEL_YUV_SEL_SHIFT (4U) +#define VICAP_DVP_PATH_SEL_YUV_SEL_MASK (0x1U << VICAP_DVP_PATH_SEL_YUV_SEL_SHIFT) /* 0x00000010 */ +#define VICAP_DVP_PATH_SEL_RAW_SEL_SHIFT (5U) +#define VICAP_DVP_PATH_SEL_RAW_SEL_MASK (0x1U << VICAP_DVP_PATH_SEL_RAW_SEL_SHIFT) /* 0x00000020 */ +/* DVP_LINE_INT_NUM */ +#define VICAP_DVP_LINE_INT_NUM_OFFSET (0x4CU) +#define VICAP_DVP_LINE_INT_NUM_LINE0_INT_NUM_SHIFT (0U) +#define VICAP_DVP_LINE_INT_NUM_LINE0_INT_NUM_MASK (0x1FFFU << VICAP_DVP_LINE_INT_NUM_LINE0_INT_NUM_SHIFT) /* 0x00001FFF */ +#define VICAP_DVP_LINE_INT_NUM_LINE1_INT_NUM_SHIFT (16U) +#define VICAP_DVP_LINE_INT_NUM_LINE1_INT_NUM_MASK (0x1FFFU << VICAP_DVP_LINE_INT_NUM_LINE1_INT_NUM_SHIFT) /* 0x1FFF0000 */ +/* DVP_WATER_LINE */ +#define VICAP_DVP_WATER_LINE_OFFSET (0x50U) +#define VICAP_DVP_WATER_LINE_HURRY_EN_SHIFT (0U) +#define VICAP_DVP_WATER_LINE_HURRY_EN_MASK (0x1U << VICAP_DVP_WATER_LINE_HURRY_EN_SHIFT) /* 0x00000001 */ +#define VICAP_DVP_WATER_LINE_HURRY_VALUE_SHIFT (4U) +#define VICAP_DVP_WATER_LINE_HURRY_VALUE_MASK (0x3U << VICAP_DVP_WATER_LINE_HURRY_VALUE_SHIFT) /* 0x00000030 */ +#define VICAP_DVP_WATER_LINE_WATER_LINE_SHIFT (8U) +#define VICAP_DVP_WATER_LINE_WATER_LINE_MASK (0x3U << VICAP_DVP_WATER_LINE_WATER_LINE_SHIFT) /* 0x00000300 */ +/* DVP_FIFO_ENTRY */ +#define VICAP_DVP_FIFO_ENTRY_OFFSET (0x54U) +#define VICAP_DVP_FIFO_ENTRY_Y_FIFO_ENTRY_SHIFT (0U) +#define VICAP_DVP_FIFO_ENTRY_Y_FIFO_ENTRY_MASK (0x1FFU << VICAP_DVP_FIFO_ENTRY_Y_FIFO_ENTRY_SHIFT) /* 0x000001FF */ +#define VICAP_DVP_FIFO_ENTRY_UV_FIFO_ENTRY_SHIFT (9U) +#define VICAP_DVP_FIFO_ENTRY_UV_FIFO_ENTRY_MASK (0x1FFU << VICAP_DVP_FIFO_ENTRY_UV_FIFO_ENTRY_SHIFT) /* 0x0003FE00 */ +/* DVP_FRAME_STATUS */ +#define VICAP_DVP_FRAME_STATUS_OFFSET (0x60U) +#define VICAP_DVP_FRAME_STATUS (0x0U) +#define VICAP_DVP_FRAME_STATUS_F0_STS_SHIFT (0U) +#define VICAP_DVP_FRAME_STATUS_F0_STS_MASK (0x1U << VICAP_DVP_FRAME_STATUS_F0_STS_SHIFT) /* 0x00000001 */ +#define VICAP_DVP_FRAME_STATUS_F1_STS_SHIFT (1U) +#define VICAP_DVP_FRAME_STATUS_F1_STS_MASK (0x1U << VICAP_DVP_FRAME_STATUS_F1_STS_SHIFT) /* 0x00000002 */ +#define VICAP_DVP_FRAME_STATUS_IDLE_SHIFT (2U) +#define VICAP_DVP_FRAME_STATUS_IDLE_MASK (0x1U << VICAP_DVP_FRAME_STATUS_IDLE_SHIFT) /* 0x00000004 */ +#define VICAP_DVP_FRAME_STATUS_FRAME_NUM_SHIFT (16U) +#define VICAP_DVP_FRAME_STATUS_FRAME_NUM_MASK (0xFFFFU << VICAP_DVP_FRAME_STATUS_FRAME_NUM_SHIFT) /* 0xFFFF0000 */ +/* DVP_CUR_DST */ +#define VICAP_DVP_CUR_DST_OFFSET (0x64U) +#define VICAP_DVP_CUR_DST (0x0U) +#define VICAP_DVP_CUR_DST_CUR_DST_SHIFT (0U) +#define VICAP_DVP_CUR_DST_CUR_DST_MASK (0xFFFFFFFFU << VICAP_DVP_CUR_DST_CUR_DST_SHIFT) /* 0xFFFFFFFF */ +/* DVP_LAST_LINE */ +#define VICAP_DVP_LAST_LINE_OFFSET (0x68U) +#define VICAP_DVP_LAST_LINE_LAST_Y_NUM_SHIFT (0U) +#define VICAP_DVP_LAST_LINE_LAST_Y_NUM_MASK (0x1FFFU << VICAP_DVP_LAST_LINE_LAST_Y_NUM_SHIFT) /* 0x00001FFF */ +#define VICAP_DVP_LAST_LINE_LAST_UV_NUM_SHIFT (16U) +#define VICAP_DVP_LAST_LINE_LAST_UV_NUM_MASK (0x1FFFU << VICAP_DVP_LAST_LINE_LAST_UV_NUM_SHIFT) /* 0x1FFF0000 */ +/* DVP_LAST_PIX */ +#define VICAP_DVP_LAST_PIX_OFFSET (0x6CU) +#define VICAP_DVP_LAST_PIX_LAST_Y_NUM_SHIFT (0U) +#define VICAP_DVP_LAST_PIX_LAST_Y_NUM_MASK (0x1FFFU << VICAP_DVP_LAST_PIX_LAST_Y_NUM_SHIFT) /* 0x00001FFF */ +#define VICAP_DVP_LAST_PIX_LAST_UV_NUM_SHIFT (16U) +#define VICAP_DVP_LAST_PIX_LAST_UV_NUM_MASK (0x1FFFU << VICAP_DVP_LAST_PIX_LAST_UV_NUM_SHIFT) /* 0x1FFF0000 */ +/****************************************AUDIOPWM****************************************/ +/* VERSION */ +#define AUDIOPWM_VERSION_OFFSET (0x0U) +#define AUDIOPWM_VERSION (0x1000000U) +#define AUDIOPWM_VERSION_VERSION_SHIFT (0U) +#define AUDIOPWM_VERSION_VERSION_MASK (0xFFFFFFFFU << AUDIOPWM_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */ +/* XFER */ +#define AUDIOPWM_XFER_OFFSET (0x4U) +#define AUDIOPWM_XFER_START_SHIFT (0U) +#define AUDIOPWM_XFER_START_MASK (0x1U << AUDIOPWM_XFER_START_SHIFT) /* 0x00000001 */ +#define AUDIOPWM_XFER_LSTOP_SHIFT (1U) +#define AUDIOPWM_XFER_LSTOP_MASK (0x1U << AUDIOPWM_XFER_LSTOP_SHIFT) /* 0x00000002 */ +/* SRC_CFG */ +#define AUDIOPWM_SRC_CFG_OFFSET (0x8U) +#define AUDIOPWM_SRC_CFG_WIDTH_SHIFT (0U) +#define AUDIOPWM_SRC_CFG_WIDTH_MASK (0x1FU << AUDIOPWM_SRC_CFG_WIDTH_SHIFT) /* 0x0000001F */ +#define AUDIOPWM_SRC_CFG_ALIGN_SHIFT (5U) +#define AUDIOPWM_SRC_CFG_ALIGN_MASK (0x1U << AUDIOPWM_SRC_CFG_ALIGN_SHIFT) /* 0x00000020 */ +#define AUDIOPWM_SRC_CFG_HALF_EN_SHIFT (6U) +#define AUDIOPWM_SRC_CFG_HALF_EN_MASK (0x1U << AUDIOPWM_SRC_CFG_HALF_EN_SHIFT) /* 0x00000040 */ +/* PWM_CFG */ +#define AUDIOPWM_PWM_CFG_OFFSET (0x10U) +#define AUDIOPWM_PWM_CFG_INTERP_RATE_SHIFT (0U) +#define AUDIOPWM_PWM_CFG_INTERP_RATE_MASK (0xFU << AUDIOPWM_PWM_CFG_INTERP_RATE_SHIFT) /* 0x0000000F */ +#define AUDIOPWM_PWM_CFG_LINEAR_INTERP_EN_SHIFT (4U) +#define AUDIOPWM_PWM_CFG_LINEAR_INTERP_EN_MASK (0x1U << AUDIOPWM_PWM_CFG_LINEAR_INTERP_EN_SHIFT) /* 0x00000010 */ +#define AUDIOPWM_PWM_CFG_OUT_SWAP_SHIFT (5U) +#define AUDIOPWM_PWM_CFG_OUT_SWAP_MASK (0x1U << AUDIOPWM_PWM_CFG_OUT_SWAP_SHIFT) /* 0x00000020 */ +#define AUDIOPWM_PWM_CFG_LEFT_DIS_SHIFT (6U) +#define AUDIOPWM_PWM_CFG_LEFT_DIS_MASK (0x1U << AUDIOPWM_PWM_CFG_LEFT_DIS_SHIFT) /* 0x00000040 */ +#define AUDIOPWM_PWM_CFG_RIGHT_DIS_SHIFT (7U) +#define AUDIOPWM_PWM_CFG_RIGHT_DIS_MASK (0x1U << AUDIOPWM_PWM_CFG_RIGHT_DIS_SHIFT) /* 0x00000080 */ +#define AUDIOPWM_PWM_CFG_SAMPLE_WIDTH_SHIFT (8U) +#define AUDIOPWM_PWM_CFG_SAMPLE_WIDTH_MASK (0x3U << AUDIOPWM_PWM_CFG_SAMPLE_WIDTH_SHIFT) /* 0x00000300 */ +/* PWM_ST */ +#define AUDIOPWM_PWM_ST_OFFSET (0x14U) +#define AUDIOPWM_PWM_ST (0x0U) +#define AUDIOPWM_PWM_ST_FIFO_BUSY_SHIFT (0U) +#define AUDIOPWM_PWM_ST_FIFO_BUSY_MASK (0x1U << AUDIOPWM_PWM_ST_FIFO_BUSY_SHIFT) /* 0x00000001 */ +#define AUDIOPWM_PWM_ST_PWM_BUSY_SHIFT (1U) +#define AUDIOPWM_PWM_ST_PWM_BUSY_MASK (0x1U << AUDIOPWM_PWM_ST_PWM_BUSY_SHIFT) /* 0x00000002 */ +/* PWM_BUF_01 */ +#define AUDIOPWM_PWM_BUF_01_OFFSET (0x18U) +#define AUDIOPWM_PWM_BUF_01 (0x0U) +#define AUDIOPWM_PWM_BUF_01_PWM_BUF_0_SHIFT (0U) +#define AUDIOPWM_PWM_BUF_01_PWM_BUF_0_MASK (0x7FFU << AUDIOPWM_PWM_BUF_01_PWM_BUF_0_SHIFT) /* 0x000007FF */ +#define AUDIOPWM_PWM_BUF_01_PWM_BUF_1_SHIFT (16U) +#define AUDIOPWM_PWM_BUF_01_PWM_BUF_1_MASK (0x7FFU << AUDIOPWM_PWM_BUF_01_PWM_BUF_1_SHIFT) /* 0x07FF0000 */ +/* PWM_BUF_23 */ +#define AUDIOPWM_PWM_BUF_23_OFFSET (0x1CU) +#define AUDIOPWM_PWM_BUF_23 (0x0U) +#define AUDIOPWM_PWM_BUF_23_PWM_BUF_2_SHIFT (0U) +#define AUDIOPWM_PWM_BUF_23_PWM_BUF_2_MASK (0x7FFU << AUDIOPWM_PWM_BUF_23_PWM_BUF_2_SHIFT) /* 0x000007FF */ +#define AUDIOPWM_PWM_BUF_23_PWM_BUF_3_SHIFT (16U) +#define AUDIOPWM_PWM_BUF_23_PWM_BUF_3_MASK (0x7FFU << AUDIOPWM_PWM_BUF_23_PWM_BUF_3_SHIFT) /* 0x07FF0000 */ +/* FIFO_CFG */ +#define AUDIOPWM_FIFO_CFG_OFFSET (0x20U) +#define AUDIOPWM_FIFO_CFG_DMA_WATERMARK_SHIFT (0U) +#define AUDIOPWM_FIFO_CFG_DMA_WATERMARK_MASK (0x1FU << AUDIOPWM_FIFO_CFG_DMA_WATERMARK_SHIFT) /* 0x0000001F */ +#define AUDIOPWM_FIFO_CFG_DMA_EN_SHIFT (7U) +#define AUDIOPWM_FIFO_CFG_DMA_EN_MASK (0x1U << AUDIOPWM_FIFO_CFG_DMA_EN_SHIFT) /* 0x00000080 */ +#define AUDIOPWM_FIFO_CFG_ALMOST_FULL_WATERMARK_SHIFT (8U) +#define AUDIOPWM_FIFO_CFG_ALMOST_FULL_WATERMARK_MASK (0x1FU << AUDIOPWM_FIFO_CFG_ALMOST_FULL_WATERMARK_SHIFT) /* 0x00001F00 */ +/* FIFO_LVL */ +#define AUDIOPWM_FIFO_LVL_OFFSET (0x24U) +#define AUDIOPWM_FIFO_LVL (0x0U) +#define AUDIOPWM_FIFO_LVL_FIFO_SPACE2FULL_SHIFT (0U) +#define AUDIOPWM_FIFO_LVL_FIFO_SPACE2FULL_MASK (0x3FU << AUDIOPWM_FIFO_LVL_FIFO_SPACE2FULL_SHIFT) /* 0x0000003F */ +/* FIFO_INT_EN */ +#define AUDIOPWM_FIFO_INT_EN_OFFSET (0x28U) +#define AUDIOPWM_FIFO_INT_EN_FULL_INT_EN_SHIFT (0U) +#define AUDIOPWM_FIFO_INT_EN_FULL_INT_EN_MASK (0x1U << AUDIOPWM_FIFO_INT_EN_FULL_INT_EN_SHIFT) /* 0x00000001 */ +#define AUDIOPWM_FIFO_INT_EN_OVERRUN_INT_EN_SHIFT (1U) +#define AUDIOPWM_FIFO_INT_EN_OVERRUN_INT_EN_MASK (0x1U << AUDIOPWM_FIFO_INT_EN_OVERRUN_INT_EN_SHIFT) /* 0x00000002 */ +#define AUDIOPWM_FIFO_INT_EN_EMPTY_INT_EN_SHIFT (2U) +#define AUDIOPWM_FIFO_INT_EN_EMPTY_INT_EN_MASK (0x1U << AUDIOPWM_FIFO_INT_EN_EMPTY_INT_EN_SHIFT) /* 0x00000004 */ +/* FIFO_INT_ST */ +#define AUDIOPWM_FIFO_INT_ST_OFFSET (0x2CU) +#define AUDIOPWM_FIFO_INT_ST_FULL_INT_ST_SHIFT (0U) +#define AUDIOPWM_FIFO_INT_ST_FULL_INT_ST_MASK (0x1U << AUDIOPWM_FIFO_INT_ST_FULL_INT_ST_SHIFT) /* 0x00000001 */ +#define AUDIOPWM_FIFO_INT_ST_OVERRUN_INT_ST_SHIFT (1U) +#define AUDIOPWM_FIFO_INT_ST_OVERRUN_INT_ST_MASK (0x1U << AUDIOPWM_FIFO_INT_ST_OVERRUN_INT_ST_SHIFT) /* 0x00000002 */ +#define AUDIOPWM_FIFO_INT_ST_EMPTY_INT_ST_SHIFT (2U) +#define AUDIOPWM_FIFO_INT_ST_EMPTY_INT_ST_MASK (0x1U << AUDIOPWM_FIFO_INT_ST_EMPTY_INT_ST_SHIFT) /* 0x00000004 */ +/* FIFO_ENTRY */ +#define AUDIOPWM_FIFO_ENTRY_OFFSET (0x80U) +#define AUDIOPWM_FIFO_ENTRY_FIFO_DATA_ENTRY_SHIFT (0U) +#define AUDIOPWM_FIFO_ENTRY_FIFO_DATA_ENTRY_MASK (0xFFFFFFFFU << AUDIOPWM_FIFO_ENTRY_FIFO_DATA_ENTRY_SHIFT) /* 0xFFFFFFFF */ + +/****************************************************************************************/ +/* */ +/* Clock Description Section */ +/* */ +/****************************************************************************************/ +/********Name=SOFTRST_CON00,Offset=0x200********/ +#define SRST_D_DSP 0U +#define SRST_B_DSP 1U +#define SRST_A_DSP_NIU 2U +#define SRST_P_DSP_NIU 4U +#define SRST_P_DSP_GRF 5U +#define SRST_P_WDT1 6U +/********Name=SOFTRST_CON01,Offset=0x204********/ +#define SRST_S_SHRM 16U +#define SRST_A_SHRM_NIU 17U +#define SRST_P_SHRM 18U +#define SRST_P_SHRM_NIU 19U +/********Name=SOFTRST_CON02,Offset=0x208********/ +#define SRST_P_UART0 32U +#define SRST_P_UART1 33U +#define SRST_P_UART2 35U +#define SRST_S_UART0 38U +#define SRST_S_UART1 41U +#define SRST_S_UART2 46U +/********Name=SOFTRST_CON04,Offset=0x210********/ +#define SRST_P_TIMER 64U +#define SRST_TIMER0 65U +#define SRST_TIMER1 66U +#define SRST_TIMER2 67U +#define SRST_TIMER3 68U +#define SRST_TIMER4 69U +#define SRST_TIMER5 70U +/********Name=SOFTRST_CON05,Offset=0x214********/ +#define SRST_P_I2C2APB_NIU 80U +#define SRST_P_I2C0 81U +#define SRST_P_I2C1 82U +#define SRST_P_I2C2 83U +#define SRST_P_I2C2APB 84U +#define SRST_I2C0 85U +#define SRST_I2C1 86U +#define SRST_I2C2 87U +#define SRST_CODEC_I2S_OUT 92U +#define SRST_P_ACDC_DIG 94U +#define SRST_A_DMAC_CORE 95U +/********Name=SOFTRST_CON06,Offset=0x218********/ +#define SRST_H_PDM0 96U +#define SRST_H_I2S_8CH 98U +#define SRST_H_VAD 99U +#define SRST_H_AUDIO_NIU 100U +#define SRST_H_AUDIO_AHB_ARB 101U +#define SRST_P_AUDIO_NIU 102U +#define SRST_M_PDM0 103U +#define SRST_M_I2S8CH 108U +#define SRST_A_DMAC_NIU 111U +/********Name=SOFTRST_CON07,Offset=0x21C********/ +#define SRST_A_VOP 112U +#define SRST_D_VOP_S 114U +#define SRST_A_VOP_NIU 115U +/********Name=SOFTRST_CON08,Offset=0x220********/ +#define SRST_P_GPIO0 128U +#define SRST_P_GPIO1 129U +#define SRST_GPIO_DB0 131U +#define SRST_GPIO_DB1 132U +/********Name=SOFTRST_CON09,Offset=0x224********/ +#define SRST_H_ALIVE_NIU 146U +#define SRST_H_ALIVEAHB_ARB 147U +#define SRST_H_INTC0 148U +#define SRST_H_INTC1 149U +#define SRST_P_CRU 152U +#define SRST_P_ALIVE_NIU 153U +#define SRST_P_PMU 154U +#define SRST_P_GRF 155U +#define SRST_PMU 156U +#define SRST_PVTM 158U +#define SRST_PDM_SAMP 159U +/********Name=SOFTRST_CON11,Offset=0x22C********/ +#define SRST_A_LOGIC_NIU 177U +#define SRST_P_SPI2APB_NIU 180U +#define SRST_P_PWM 181U +#define SRST_P_SPI1 182U +#define SRST_P_SPI2 183U +#define SRST_P_SPI2APB 184U +#define SRST_P_MAILBOX0 185U +#define SRST_P_MAILBOX1 186U +#define SRST_P_MAILBOX2 187U +#define SRST_P_WDT0 188U +#define SRST_P_MIPIDSI_HOST 189U +#define SRST_P_CIF 190U +#define SRST_P_LOGIC_NIU 191U +/********Name=SOFTRST_CON12,Offset=0x230********/ +#define SRST_H_USB2CTRL 193U +#define SRST_H_USB2_NIU 194U +#define SRST_H_BOOTROM 195U +#define SRST_H_VOP 196U +#define SRST_H_AUDPWM 197U +#define SRST_H_CIF 198U +#define SRST_H_LOGIC_NIU 199U +#define SRST_H_SFC 200U +#define SRST_H_XIP_SFC 201U +#define SRST_H_SDIO 202U +#define SRST_H_LOGIC_AHB_ARB 203U +#define SRST_H_I2S1_8CH 204U +#define SRST_H_CM4_NIU 205U +#define SRST_H_CM4_CORE 206U +/********Name=SOFTRST_CON13,Offset=0x234********/ +#define SRST_SPI1 208U +#define SRST_SPI2 209U +#define SRST_S_SFC 212U +#define SRST_H_SFC1 213U +#define SRST_H_XIP_SFC1 214U +#define SRST_SDIO 216U +#define SRST_M_I2S1_8CH 219U +#define SRST_PWM 221U +#define SRST_AUDPWM 222U +#define SRST_A_CIF 223U +/********Name=SOFTRST_CON14,Offset=0x238********/ +#define SRST_A_CIF_NIU 225U +#define SRST_S_SFC1 228U +#define SRST_USB2_ADP 229U +#define SRST_KEY 233U +#define SRST_P_KEY 234U +#define SRST_USB2PHYUTMI 236U +#define SRST_USB2CTRL 237U +#define SRST_USB2PHYPO 238U +/********Name=SOFTRST_CON15,Offset=0x23C********/ +#define SRST_H_AC_CM4_CORE 240U +#define SRST_WRITE_ENABLE 256U + +/********Name=CLKGATE_CON00,Offset=0x180********/ +#define ACLK_DSP_GATE 0U +#define ACLK_DSP_NIU_GATE 2U +#define PCLK_DSP_GATE 3U +#define PCLK_DSP_NIU_GATE 4U +#define PCLK_DSP_GRF_GATE 5U +#define PCLK_WDT1_GATE 6U +#define ACLK_DSP_S_GATE 7U +/********Name=CLKGATE_CON01,Offset=0x184********/ +#define SCLK_SHRM_GATE 16U +#define ACLK_SHRM_NIU_GATE 17U +#define PCLK_SHRM_GATE 18U +#define PCLK_SHRM_NIU_GATE 19U +/********Name=CLKGATE_CON02,Offset=0x188********/ +#define PCLK_UART0_GATE 32U +#define PCLK_UART1_GATE 33U +#define PCLK_UART2_GATE 34U +#define CLK_UART0_GATE 35U +#define CLK_UART0_FRAC_GATE 36U +#define CLK_UART0_NP5_GATE 37U +#define SCLK_UART0_GATE 38U +#define CLK_UART1_GATE 39U +#define CLK_UART1_FRAC_GATE 40U +#define CLK_UART1_NP5_GATE 41U +#define SCLK_UART1_GATE 42U +#define CLK_UART2_GATE 43U +#define CLK_UART2_FRAC_GATE 44U +#define CLK_UART2_NP5_GATE 45U +#define SCLK_UART2_GATE 46U +/********Name=CLKGATE_CON04,Offset=0x190********/ +#define PCLK_TIMER_GATE 64U +#define CLK_TIMER0_GATE 65U +#define CLK_TIMER1_GATE 66U +#define CLK_TIMER2_GATE 67U +#define CLK_TIMER3_GATE 68U +#define CLK_TIMER4_GATE 69U +#define CLK_TIMER5_GATE 70U +/********Name=CLKGATE_CON05,Offset=0x194********/ +#define PCLK_I2C2APB_NIU_GATE 80U +#define PCLK_I2C0_GATE 81U +#define PCLK_I2C1_GATE 82U +#define PCLK_I2C2_GATE 83U +#define PCLK_I2C2APB_GATE 84U +#define CLK_I2C0_GATE 85U +#define CLK_I2C1_GATE 86U +#define CLK_I2C2_GATE 87U +#define PCLK_ACDC_DIG_GATE 94U +#define ACLK_DMAC_CORE_GATE 95U +/********Name=CLKGATE_CON06,Offset=0x198********/ +#define HCLK_PDM0_GATE 96U +#define HCLK_AUDIO_GATE 97U +#define HCLK_I2S_8CH_GATE 98U +#define HCLK_VAD_GATE 99U +#define HCLK_AUDIO_NIU_GATE 100U +#define HCLK_AUDIO_AHB_ARB_GATE 101U +#define PCLK_AUDIO_NIU_GATE 102U +#define MCLK_PDM0_GATE 103U +#define MCLK_PDM0_OUT_GATE 104U +#define PCLK_AUDIO_GATE 105U +#define CLK_I2S8CH_GATE 106U +#define CLK_I2S8CH_FRAC_GATE 107U +#define MCLK_I2S8CH_GATE 108U +#define I2S_MCLKOUT_GATE 109U +#define ACLK_DMAC_GATE 110U +#define ACLK_DMAC_NIU_GATE 111U +/********Name=CLKGATE_CON07,Offset=0x19C********/ +#define ACLK_VOP_GATE 112U +#define DCLK_VOP_S_GATE 114U +#define ACLK_VOP_NIU_GATE 115U +#define DCLK_VOP_GATE 116U +#define DCLK_MIPIDSI_HOST_GATE 117U +#define OCC_SCAN_CLK_DPHYLANBYTE_GATE 120U +/********Name=CLKGATE_CON08,Offset=0x1A0********/ +#define PCLK_GPIO0_GATE 128U +#define PCLK_GPIO1_GATE 129U +#define CLK_GPIO_DB0_GATE 131U +#define CLK_GPIO_DB1_GATE 132U +/********Name=CLKGATE_CON09,Offset=0x1A4********/ +#define PCLK_ALIVE_GATE 144U +#define HCLK_ALIVE_GATE 145U +#define HCLK_ALIVE_NIU_GATE 146U +#define HCLK_ALIVEAHB_ARB_GATE 147U +#define HCLK_INTC0_GATE 148U +#define HCLK_INTC1_GATE 149U +#define PCLK_CRU_GATE 152U +#define PCLK_ALIVE_NIU_GATE 153U +#define PCLK_PMU_GATE 154U +#define PCLK_GRF_GATE 155U +#define CLK_PMU_GATE 156U +#define CLK_TESTOUT_GATE 157U +#define CLK_PVTM_GATE 158U +#define CLK_PDM_SAMP_GATE 159U +/********Name=CLKGATE_CON10,Offset=0x1A8********/ +#define CLK_MEMSUBSYS0_GATE 160U +#define CLK_MEMSUBSYS1_GATE 161U +#define CLK_MEMSUBSYS2_GATE 162U +#define CLK_MEMSUBSYS3_GATE 163U +#define ACLK_MEMSUBSYS_GATE 164U +/********Name=CLKGATE_CON11,Offset=0x1AC********/ +#define ACLK_LOGIC_GATE 176U +#define ACLK_LOGIC_NIU_GATE 177U +#define HCLK_LOGIC_GATE 178U +#define PCLK_LOGIC_GATE 179U +#define PCLK_SPI2APB_NIU_GATE 180U +#define PCLK_PWM_GATE 181U +#define PCLK_SPI1_GATE 182U +#define PCLK_SPI2_GATE 183U +#define PCLK_SPI2APB_GATE 184U +#define PCLK_MAILBOX0_GATE 185U +#define PCLK_MAILBOX1_GATE 186U +#define PCLK_MAILBOX2_GATE 187U +#define PCLK_WDT0_GATE 188U +#define PCLK_MIPIDSI_HOST_GATE 189U +#define PCLK_CIF_GATE 190U +#define PCLK_LOGIC_NIU_GATE 191U +/********Name=CLKGATE_CON12,Offset=0x1B0********/ +#define HCLK_M4_GATE 192U +#define HCLK_USB2CTRL_GATE 193U +#define HCLK_USB2_NIU_GATE 194U +#define HCLK_BOOTROM_GATE 195U +#define HCLK_VOP_GATE 196U +#define HCLK_AUDPWM_GATE 197U +#define HCLK_CIF_GATE 198U +#define HCLK_LOGIC_NIU_GATE 199U +#define HCLK_SFC_GATE 200U +#define HCLK_XIP_SFC_GATE 201U +#define HCLK_SDIO_GATE 202U +#define HCLK_LOGIC_AHB_ARB_GATE 203U +#define HCLK_I2S1_8CH_GATE 204U +#define HCLK_CM4_NIU_GATE 205U +#define HCLK_CM4_CORE_GATE 206U +#define CLK_CIFOUT_GATE 207U +/********Name=CLKGATE_CON13,Offset=0x1B4********/ +#define CLK_SPI1_GATE 208U +#define CLK_SPI2_GATE 209U +#define SCLK_SFC_GATE 212U +#define HCLK_SFC1_GATE 213U +#define HCLK_XIP_SFC1_GATE 214U +#define CLK_SDIO_GATE 216U +#define CLK_I2S1_8CH_GATE 217U +#define CLK_I2S1_8CH_FRAC_GATE 218U +#define MCLK_I2S1_8CH_GATE 219U +#define I2S1_MCLKOUT_GATE 220U +#define CLK_PWM_GATE 221U +#define CLK_AUDPWM_DF_GATE 222U +#define ACLK_CIF_GATE 223U +/********Name=CLKGATE_CON14,Offset=0x1B8********/ +#define CLK_AUDPWM_FRAC_GATE 224U +#define ACLK_CIF_NIU_GATE 225U +#define SCLK_SFC1_GATE 228U +#define CLK_USB2_ADP_GATE 229U +#define CLK_USB2PHY_REF_FRAC_GATE 230U +#define CLK_DPHY_REF_FRAC_GATE 231U +#define STCLK_M4_GATE 232U +#define CLK_KEY_GATE 233U +#define PCLK_KEY_GATE 234U +#define CLK_USB2CTRL_GATE 237U +#define CLK_BT32K_GATE 239U + +/********Name=CLKSEL_CON00,Offset=0x80********/ +#define ACLK_DSP_S_DIV 0x06000000U +#define PCLK_DSP_DIV 0x06080000U +/********Name=CLKSEL_CON02,Offset=0x88********/ +#define SCLK_SHRM_DIV 0x04000002U +#define PCLK_SHRM_DIV 0x05080002U +/********Name=CLKSEL_CON03,Offset=0x8C********/ +#define CLK_UART0_SRC_DIV 0x05000003U +/********Name=CLKSEL_CON04,Offset=0x90********/ +#define CLK_UART0_FRAC_DIV 0x20000004U +/********Name=CLKSEL_CON05,Offset=0x94********/ +#define CLK_UART1_SRC_DIV 0x05000005U +/********Name=CLKSEL_CON06,Offset=0x98********/ +#define CLK_UART1_FRAC_DIV 0x20000006U +/********Name=CLKSEL_CON07,Offset=0x9C********/ +#define CLK_UART2_SRC_DIV 0x05000007U +/********Name=CLKSEL_CON08,Offset=0xA0********/ +#define CLK_UART2_FRAC_DIV 0x20000008U +/********Name=CLKSEL_CON13,Offset=0xB4********/ +#define CLK_I2C0_DIV 0x0400000DU +#define CLK_I2C1_DIV 0x0404000DU +#define CLK_I2C2_DIV 0x0408000DU +/********Name=CLKSEL_CON14,Offset=0xB8********/ +#define MCLK_PDM0_DIV 0x0500000EU +#define HCLK_AUDIO_DIV 0x0508000EU +/********Name=CLKSEL_CON15,Offset=0xBC********/ +#define MCLK_PDM0_OUT_DIV 0x2000000FU +/********Name=CLKSEL_CON16,Offset=0xC0********/ +#define CLK_I2S8CH_SRC_DIV 0x05000010U +#define PCLK_AUDIO_DIV 0x05080010U +/********Name=CLKSEL_CON17,Offset=0xC4********/ +#define CLK_I2S8CH_FRAC_DIV 0x20000011U +/********Name=CLKSEL_CON18,Offset=0xC8********/ +#define ACLK_DMAC_DIV 0x05000012U +/********Name=CLKSEL_CON19,Offset=0xCC********/ +#define ACLK_VOP_DIV 0x05000013U +/********Name=CLKSEL_CON20,Offset=0xD0********/ +#define DCLK_VOP_S_DIV 0x05000014U +/********Name=CLKSEL_CON22,Offset=0xD8********/ +/********Name=CLKSEL_CON23,Offset=0xDC********/ +#define OCC_SCAN_CLK_DPHYLANBYTE_DIV 0x08000017U +/********Name=CLKSEL_CON24,Offset=0xE0********/ +#define CLK_GPIO_DB0_DIV 0x0A000018U +/********Name=CLKSEL_CON25,Offset=0xE4********/ +#define CLK_GPIO_DB1_DIV 0x0A000019U +/********Name=CLKSEL_CON27,Offset=0xEC********/ +#define PCLK_ALIVE_DIV 0x0500001BU +/********Name=CLKSEL_CON28,Offset=0xF0********/ +#define HCLK_ALIVE_DIV 0x0500001CU +/********Name=CLKSEL_CON30,Offset=0xF8********/ +#define CLK_TESTOUT_DIV 0x0800001EU +/********Name=CLKSEL_CON31,Offset=0xFC********/ +#define CLK_PDM_SAMP_DIV 0x0500001FU +/********Name=CLKSEL_CON33,Offset=0x104********/ +#define HCLK_M4_DIV 0x05000021U +#define CLK_SPI1_DIV 0x05080021U +/********Name=CLKSEL_CON34,Offset=0x108********/ +#define CLK_SPI2_DIV 0x05080022U +/********Name=CLKSEL_CON35,Offset=0x10C********/ +#define SCLK_SFC_DIV 0x08000023U +#define CLK_SDIO_DIV 0x08080023U +/********Name=CLKSEL_CON36,Offset=0x110********/ +/********Name=CLKSEL_CON37,Offset=0x114********/ +#define CLK_AUDPWM_DF_DIV 0x05000025U +#define CLK_I2S1_8CH_SRC_DIV 0x05080025U +/********Name=CLKSEL_CON38,Offset=0x118********/ +#define CLK_I2S1_8CH_FRAC_DIV 0x20000026U +/********Name=CLKSEL_CON39,Offset=0x11C********/ +#define CLK_PWM_DIV 0x05000027U +#define HCLK_LOGIC_DIV 0x05080027U +/********Name=CLKSEL_CON40,Offset=0x120********/ +#define PCLK_LOGIC_DIV 0x05000028U +#define ACLK_LOGIC_DIV 0x05080028U +/********Name=CLKSEL_CON41,Offset=0x124********/ +#define CLK_CIFOUT_DIV 0x05000029U +/********Name=CLKSEL_CON42,Offset=0x128********/ +#define CLK_AUDPWM_FRAC_DIV 0x2000002AU +/********Name=CLKSEL_CON43,Offset=0x12C********/ +#define CLK_USB2PHY_REF_FRAC_DIV 0x2000002BU +/********Name=CLKSEL_CON44,Offset=0x130********/ +#define CLK_DPHY_REF_FRAC_DIV 0x2000002CU +/********Name=CLKSEL_CON46,Offset=0x138********/ +/********Name=CLKSEL_CON47,Offset=0x13C********/ +#define SCLK_SFC1_DIV 0x0800002FU +/********Name=CLKSEL_CON49,Offset=0x144********/ +#define XIN_OSC0_DIV 0x20000031U + +/********Name=CLKSEL_CON00,Offset=0x80********/ +#define ACLK_DSP_S_SEL 0x02060000U +#define ACLK_DSP_S_SEL_CLK_GPLL_MUX 0U +#define ACLK_DSP_S_SEL_CLK_CPLL_MUX 1U +#define ACLK_DSP_S_SEL_XIN_OSC0_FUNC 2U +/********Name=CLKSEL_CON02,Offset=0x88********/ +#define SCLK_SHRM_SEL 0x01040002U +#define SCLK_SHRM_SEL_CLK_GPLL_MUX 0U +#define SCLK_SHRM_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON03,Offset=0x8C********/ +#define CLK_UART0_SRC_SEL 0x01050003U +#define CLK_UART0_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART0_SRC_SEL_CLK_CPLL_MUX 1U +#define SCLK_UART0_SEL 0x02060003U +#define SCLK_UART0_SEL_CLK_UART0_SRC 0U +#define SCLK_UART0_SEL_CLK_UART0_FRAC 1U +#define SCLK_UART0_SEL_XIN_OSC0_FUNC 2U +/********Name=CLKSEL_CON04,Offset=0x90********/ +/********Name=CLKSEL_CON05,Offset=0x94********/ +#define CLK_UART1_SRC_SEL 0x01050005U +#define CLK_UART1_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART1_SRC_SEL_CLK_CPLL_MUX 1U +#define SCLK_UART1_SEL 0x02060005U +#define SCLK_UART1_SEL_CLK_UART1_SRC 0U +#define SCLK_UART1_SEL_CLK_UART1_FRAC 1U +#define SCLK_UART1_SEL_XIN_OSC0_FUNC 2U +/********Name=CLKSEL_CON06,Offset=0x98********/ +/********Name=CLKSEL_CON07,Offset=0x9C********/ +#define CLK_UART2_SRC_SEL 0x01050007U +#define CLK_UART2_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART2_SRC_SEL_CLK_CPLL_MUX 1U +#define SCLK_UART2_SEL 0x02060007U +#define SCLK_UART2_SEL_CLK_UART2_SRC 0U +#define SCLK_UART2_SEL_CLK_UART2_FRAC 1U +#define SCLK_UART2_SEL_XIN_OSC0_FUNC 2U +/********Name=CLKSEL_CON08,Offset=0xA0********/ +/********Name=CLKSEL_CON13,Offset=0xB4********/ +/********Name=CLKSEL_CON14,Offset=0xB8********/ +#define MCLK_PDM0_SEL 0x0107000EU +#define MCLK_PDM0_SEL_CLK_GPLL_MUX 0U +#define MCLK_PDM0_SEL_CLK_CPLL_MUX 1U +#define HCLK_AUDIO_SEL 0x010F000EU +#define HCLK_AUDIO_SEL_CLK_GPLL_MUX 0U +#define HCLK_AUDIO_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON15,Offset=0xBC********/ +/********Name=CLKSEL_CON16,Offset=0xC0********/ +#define CLK_I2S8CH_SRC_SEL 0x01050010U +#define CLK_I2S8CH_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S8CH_SRC_SEL_CLK_CPLL_MUX 1U +#define MCLK_I2S8CH_SEL 0x02060010U +#define MCLK_I2S8CH_SEL_CLK_I2S8CH_SRC 0U +#define MCLK_I2S8CH_SEL_CLK_I2S8CH_FRAC 1U +#define MCLK_I2S8CH_SEL_I2S_MCLKIN 2U +#define MCLK_I2S8CH_SEL_XIN_OSC0_HALF 3U +#define PCLK_AUDIO_SEL 0x010E0010U +#define PCLK_AUDIO_SEL_CLK_GPLL_MUX 0U +#define PCLK_AUDIO_SEL_CLK_CPLL_MUX 1U +#define I2S_MCLKOUT_SEL 0x010F0010U +#define I2S_MCLKOUT_SEL_MCLK_I2S8CH_NDFT 0U +#define I2S_MCLKOUT_SEL_XIN_OSC0_HALF 1U +/********Name=CLKSEL_CON17,Offset=0xC4********/ +/********Name=CLKSEL_CON18,Offset=0xC8********/ +#define ACLK_DMAC_SEL 0x01070012U +#define ACLK_DMAC_SEL_CLK_GPLL_MUX 0U +#define ACLK_DMAC_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON19,Offset=0xCC********/ +#define ACLK_VOP_SEL 0x01070013U +#define ACLK_VOP_SEL_CLK_GPLL_MUX 0U +#define ACLK_VOP_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON20,Offset=0xD0********/ +#define DCLK_VOP_S_SEL 0x01070014U +#define DCLK_VOP_S_SEL_CLK_GPLL_MUX 0U +#define DCLK_VOP_S_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON22,Offset=0xD8********/ +#define OCC_SCAN_CLK_DPHYLANBYTE_SEL 0x02060016U +#define OCC_SCAN_CLK_DPHYLANBYTE_SEL_CLK_GPLL_MUX 0U +#define OCC_SCAN_CLK_DPHYLANBYTE_SEL_CLK_CPLL_MUX 1U +#define OCC_SCAN_CLK_DPHYLANBYTE_SEL_XIN_OSC0_FUNC 2U +/********Name=CLKSEL_CON23,Offset=0xDC********/ +/********Name=CLKSEL_CON24,Offset=0xE0********/ +/********Name=CLKSEL_CON25,Offset=0xE4********/ +/********Name=CLKSEL_CON27,Offset=0xEC********/ +/********Name=CLKSEL_CON28,Offset=0xF0********/ +/********Name=CLKSEL_CON30,Offset=0xF8********/ +#define CLK_TESTOUT_SEL 0x0408001EU +#define CLK_TESTOUT_SEL_ACLK_DSP 0U +#define CLK_TESTOUT_SEL_HCLK_M4 1U +#define CLK_TESTOUT_SEL_XIN_OSC0_FUNC 2U +#define CLK_TESTOUT_SEL_CLK_DEEPSLOW 3U +#define CLK_TESTOUT_SEL_PCLK_CIF 4U +#define CLK_TESTOUT_SEL_CLK_USB2PHY_REF 5U +#define CLK_TESTOUT_SEL_CLK_DPHY_REF 6U +#define CLK_TESTOUT_SEL_CLK_MIPIPHY_LANBYTE 7U +#define CLK_TESTOUT_SEL_CLK_USBPHY48M 8U +#define CLK_TESTOUT_SEL_CLK_USBPHY480M 9U +#define CLK_TESTOUT_SEL_ACLK_LOGIC 10U +#define CLK_TESTOUT_SEL_CLK_AUDPWM 11U +#define CLK_TESTOUT_SEL_CLK_SDIO 12U +#define CLK_TESTOUT_SEL_MCLK_I2S8CH 13U +#define CLK_TESTOUT_SEL_DCLK_VOP 14U +#define CLK_TESTOUT_SEL_HCLK_AUDIO 15U +/********Name=CLKSEL_CON31,Offset=0xFC********/ +#define CLK_PDM_SAMP_SEL 0x0105001FU +#define CLK_PDM_SAMP_SEL_CLK_GPLL_MUX 0U +#define CLK_PDM_SAMP_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON33,Offset=0x104********/ +#define HCLK_M4_SEL 0x01070021U +#define HCLK_M4_SEL_CLK_GPLL_MUX 0U +#define HCLK_M4_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON34,Offset=0x108********/ +#define SCLK_SFC_SEL 0x010E0022U +#define SCLK_SFC_SEL_CLK_GPLL_MUX 0U +#define SCLK_SFC_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON35,Offset=0x10C********/ +/********Name=CLKSEL_CON36,Offset=0x110********/ +#define CLK_SDIO_SEL 0x02080024U +#define CLK_SDIO_SEL_CLK_GPLL_MUX 0U +#define CLK_SDIO_SEL_CLK_CPLL_MUX 1U +#define CLK_SDIO_SEL_XIN_OSC0_FUNC 2U +#define PCLK_CIF_SRC_SEL 0x010C0024U +#define PCLK_CIF_SRC_SEL_PCLK_CIF 0U +#define PCLK_CIF_SRC_SEL_PCLK_CIF_INVERT 1U +/********Name=CLKSEL_CON37,Offset=0x114********/ +#define CLK_AUDPWM_SEL 0x01050025U +#define CLK_AUDPWM_SEL_CLK_AUDPWM_DF 0U +#define CLK_AUDPWM_SEL_CLK_AUDPWM_FRAC 1U +#define CLK_AUDPWM_SRC_SEL 0x01060025U +#define CLK_AUDPWM_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_AUDPWM_SRC_SEL_CLK_CPLL_MUX 1U +#define I2S1_MCLKOUT_SEL 0x01070025U +#define I2S1_MCLKOUT_SEL_MCLK_I2S1_8CH_NDFT 0U +#define I2S1_MCLKOUT_SEL_XIN_OSC0_HALF 1U +#define CLK_I2S1_8CH_SRC_SEL 0x010D0025U +#define CLK_I2S1_8CH_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S1_8CH_SRC_SEL_CLK_CPLL_MUX 1U +#define MCLK_I2S1_8CH_SEL 0x020E0025U +#define MCLK_I2S1_8CH_SEL_CLK_I2S1_8CH_SRC 0U +#define MCLK_I2S1_8CH_SEL_CLK_I2S1_8CH_FRAC 1U +#define MCLK_I2S1_8CH_SEL_I2S1_MCLKIN 2U +#define MCLK_I2S1_8CH_SEL_XIN_OSC0_HALF 3U +/********Name=CLKSEL_CON38,Offset=0x118********/ +/********Name=CLKSEL_CON39,Offset=0x11C********/ +#define CLK_PWM_SEL 0x01050027U +#define CLK_PWM_SEL_CLK_GPLL_MUX 0U +#define CLK_PWM_SEL_XIN_OSC0_FUNC 1U +#define HCLK_LOGIC_SEL 0x010F0027U +#define HCLK_LOGIC_SEL_CLK_GPLL_MUX 0U +#define HCLK_LOGIC_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON40,Offset=0x120********/ +#define PCLK_LOGIC_SEL 0x01070028U +#define PCLK_LOGIC_SEL_CLK_GPLL_MUX 0U +#define PCLK_LOGIC_SEL_CLK_CPLL_MUX 1U +#define ACLK_LOGIC_SEL 0x010F0028U +#define ACLK_LOGIC_SEL_CLK_GPLL_MUX 0U +#define ACLK_LOGIC_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON41,Offset=0x124********/ +#define CLK_CIFOUT_SEL 0x02060029U +#define CLK_CIFOUT_SEL_CLK_GPLL_MUX 0U +#define CLK_CIFOUT_SEL_CLK_CPLL_MUX 1U +#define CLK_CIFOUT_SEL_XIN_OSC0_FUNC 2U +#define CLK_USB2PHY_REF_FRAC_SEL 0x01080029U +#define CLK_USB2PHY_REF_FRAC_SEL_CLK_GPLL_MUX 0U +#define CLK_USB2PHY_REF_FRAC_SEL_CLK_CPLL_MUX 1U +#define CLK_USB2PHY_REF_SEL 0x01090029U +#define CLK_USB2PHY_REF_SEL_XIN_OSC0_HALF 0U +#define CLK_USB2PHY_REF_SEL_CLK_USB2PHY_REF_FRAC 1U +#define CLK_DPHY_REF_FRAC_SEL 0x010A0029U +#define CLK_DPHY_REF_FRAC_SEL_CLK_GPLL_MUX 0U +#define CLK_DPHY_REF_FRAC_SEL_CLK_CPLL_MUX 1U +#define CLK_DPHY_REF_SEL 0x010B0029U +#define CLK_DPHY_REF_SEL_XIN_OSC0_FUNC 0U +#define CLK_DPHY_REF_SEL_CLK_DPHY_REF_FRAC 1U +/********Name=CLKSEL_CON42,Offset=0x128********/ +/********Name=CLKSEL_CON43,Offset=0x12C********/ +/********Name=CLKSEL_CON44,Offset=0x130********/ +/********Name=CLKSEL_CON46,Offset=0x138********/ +#define SCLK_SFC1_SEL 0x010E002EU +#define SCLK_SFC1_SEL_CLK_GPLL_MUX 0U +#define SCLK_SFC1_SEL_CLK_CPLL_MUX 1U +/********Name=CLKSEL_CON47,Offset=0x13C********/ +/********Name=CLKSEL_CON49,Offset=0x144********/ + +#define CLK(mux, div) \ + (((mux) & 0x0F0F00FFU) | (((div) & 0xFFU) << 8) | (((div) & 0x0F0F0000U) << 4)) + +#ifndef __ASSEMBLY__ +typedef enum CLOCK_Name { + CLK_INVALID = 0U, + PLL_GPLL, + PLL_CPLL, + ACLK_DSP = CLK(ACLK_DSP_S_SEL, ACLK_DSP_S_DIV), + PCLK_DSP = CLK(0U, PCLK_DSP_DIV), + SCLK_SHRM = CLK(SCLK_SHRM_SEL, SCLK_SHRM_DIV), + PCLK_SHRM = CLK(0U, PCLK_SHRM_DIV), + CLK_UART0_SRC = CLK(CLK_UART0_SRC_SEL, CLK_UART0_SRC_DIV), + CLK_UART0_FRAC = CLK(0U, CLK_UART0_FRAC_DIV), + CLK_UART0 = CLK(SCLK_UART0_SEL, 0U), + CLK_UART1_SRC = CLK(CLK_UART1_SRC_SEL, CLK_UART1_SRC_DIV), + CLK_UART1_FRAC = CLK(0U, CLK_UART1_FRAC_DIV), + CLK_UART1 = CLK(SCLK_UART1_SEL, 0U), + CLK_UART2_SRC = CLK(CLK_UART2_SRC_SEL, CLK_UART2_SRC_DIV), + CLK_UART2_FRAC = CLK(0U, CLK_UART2_FRAC_DIV), + CLK_UART2 = CLK(SCLK_UART2_SEL, 0U), + CLK_I2C0 = CLK(0U, CLK_I2C0_DIV), + CLK_I2C1 = CLK(0U, CLK_I2C1_DIV), + CLK_I2C2 = CLK(0U, CLK_I2C2_DIV), + MCLK_PDM0 = CLK(MCLK_PDM0_SEL, MCLK_PDM0_DIV), + HCLK_AUDIO = CLK(HCLK_AUDIO_SEL, HCLK_AUDIO_DIV), + CLK_I2S8CH_SRC = CLK(CLK_I2S8CH_SRC_SEL, CLK_I2S8CH_SRC_DIV), + CLK_I2S8CH_FRAC = CLK(0U, CLK_I2S8CH_FRAC_DIV), + MCLK_I2S8CH = CLK(MCLK_I2S8CH_SEL, 0U), + I2S_MCLKOUT = CLK(I2S_MCLKOUT_SEL, 0U), + ACLK_DMAC = CLK(ACLK_DMAC_SEL, ACLK_DMAC_DIV), + PCLK_AUDIO = CLK(PCLK_AUDIO_SEL, PCLK_AUDIO_DIV), + ACLK_VOP = CLK(ACLK_VOP_SEL, ACLK_VOP_DIV), + DCLK_VOP_S = CLK(DCLK_VOP_S_SEL, DCLK_VOP_S_DIV), + OCC_SCAN_CLK_DPHYLANBYTE = CLK(OCC_SCAN_CLK_DPHYLANBYTE_SEL, OCC_SCAN_CLK_DPHYLANBYTE_DIV), + CLK_GPIO_DBG0 = CLK(0U, CLK_GPIO_DB0_DIV), + CLK_GPIO_DBG1 = CLK(0U, CLK_GPIO_DB1_DIV), + PCLK_ALIVE = CLK(0U, PCLK_ALIVE_DIV), + HCLK_ALIVE = CLK(0U, HCLK_ALIVE_DIV), + CLK_TESTOUT = CLK(CLK_TESTOUT_SEL, CLK_TESTOUT_DIV), + CLK_PDM_SAMP = CLK(CLK_PDM_SAMP_SEL, CLK_PDM_SAMP_DIV), + HCLK_M4 = CLK(HCLK_M4_SEL, HCLK_M4_DIV), + CLK_SPI1 = CLK(0U, CLK_SPI1_DIV), + SCLK_SFC_SRC = CLK(SCLK_SFC_SEL, SCLK_SFC_DIV), + CLK_SPI2 = CLK(0U, CLK_SPI2_DIV), + CLK_SDIO_SRC = CLK(CLK_SDIO_SEL, CLK_SDIO_DIV), + CLK_AUDPWM_SRC = CLK(CLK_AUDPWM_SRC_SEL, CLK_AUDPWM_DF_DIV), + CLK_AUDPWM_FRAC = CLK(0U, CLK_AUDPWM_FRAC_DIV), + CLK_AUDPWM = CLK(CLK_AUDPWM_SEL, 0U), + CLK_I2S1_8CH_SRC = CLK(CLK_I2S1_8CH_SRC_SEL, CLK_I2S1_8CH_SRC_DIV), + CLK_I2S1_8CH_FRAC = CLK(0U, CLK_I2S1_8CH_FRAC_DIV), + MCLK_I2S1_8CH = CLK(MCLK_I2S1_8CH_SEL, 0U), + I2S1_MCLKOUT = CLK(I2S1_MCLKOUT_SEL, 0U), + CLK_PWM = CLK(CLK_PWM_SEL, CLK_PWM_DIV), + HCLK_LOGIC = CLK(HCLK_LOGIC_SEL, HCLK_LOGIC_DIV), + PCLK_LOGIC = CLK(PCLK_LOGIC_SEL, PCLK_LOGIC_DIV), + ACLK_LOGIC = CLK(ACLK_LOGIC_SEL, ACLK_LOGIC_DIV), + CLK_CIFOUT = CLK(CLK_CIFOUT_SEL, CLK_CIFOUT_DIV), + CLK_USB2PHY_REF_FRAC = CLK(CLK_USB2PHY_REF_FRAC_SEL, CLK_USB2PHY_REF_FRAC_DIV), + CLK_USB2PHY_REF = CLK(CLK_USB2PHY_REF_SEL, 0U), + CLK_DPHY_REF_FRAC = CLK(CLK_DPHY_REF_FRAC_SEL, CLK_DPHY_REF_FRAC_DIV), + CLK_DPHY_REF = CLK(CLK_DPHY_REF_SEL, 0U), + SCLK_SFC1_SRC = CLK(SCLK_SFC1_SEL, SCLK_SFC1_DIV), + CLK_32K = CLK(0U, XIN_OSC0_DIV), +} eCLOCK_Name; +#endif /* __ASSEMBLY__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __RK2108_H */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/rk2108_usb.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/rk2108_usb.h new file mode 100644 index 00000000000..7e213335c6d --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/rk2108_usb.h @@ -0,0 +1,1332 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __RK2108_USB_H +#define __RK2108_USB_H +#ifdef __cplusplus + extern "C" { +#endif +/****************************************************************************************/ +/* */ +/* Module Structure Section */ +/* */ +/****************************************************************************************/ +#ifndef __ASSEMBLY__ +/* USB_OTG_CORE Register Structure Define */ +struct USB_GLOBAL_REG { + __IO uint32_t GOTGCTL; /* Address Offset: 0x0000 */ + __IO uint32_t GOTGINT; /* Address Offset: 0x0004 */ + __IO uint32_t GAHBCFG; /* Address Offset: 0x0008 */ + __IO uint32_t GUSBCFG; /* Address Offset: 0x000C */ + __IO uint32_t GRSTCTL; /* Address Offset: 0x0010 */ + __IO uint32_t GINTSTS; /* Address Offset: 0x0014 */ + __IO uint32_t GINTMSK; /* Address Offset: 0x0018 */ + __IO uint32_t GRXSTSR; /* Address Offset: 0x001C */ + __IO uint32_t GRXSTSP; /* Address Offset: 0x0020 */ + __IO uint32_t GRXFSIZ; /* Address Offset: 0x0024 */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* Address Offset: 0x0028 */ + __IO uint32_t HNPTXSTS; /* Address Offset: 0x002C */ + uint32_t RESERVED0[2]; /* Address Offset: 0x0030 */ + __IO uint32_t GGPIO; /* Address Offset: 0x0038 */ + __IO uint32_t GUID; /* Address Offset: 0x003C */ + __O uint32_t GSNPSID; /* Address Offset: 0x0040 */ + __O uint32_t GHWCFG1; /* Address Offset: 0x0044 */ + __O uint32_t GHWCFG2; /* Address Offset: 0x0048 */ + __O uint32_t GHWCFG3; /* Address Offset: 0x004C */ + __O uint32_t GHWCFG4; /* Address Offset: 0x0050 */ + __IO uint32_t GLPMCFG; /* Address Offset: 0x0054 */ + __IO uint32_t GPWRDN; /* Address Offset: 0x0058 */ + __IO uint32_t GDFIFOCFG; /* Address Offset: 0x005C */ + __IO uint32_t GADPCTL; /* Address Offset: 0x0060 */ + uint32_t RESERVED1[39]; /* Address Offset: 0x0064 */ + __IO uint32_t HPTXFSIZ; /* Address Offset: 0x0100 */ + __IO uint32_t DIEPTXF[0x0F]; /* Address Offset: 0x0104 */ +}; +/* USB_OTG_DEV Register Structure Define */ +struct USB_DEVICE_REG { + __IO uint32_t DCFG; /* Address Offset: 0x0800 */ + __IO uint32_t DCTL; /* Address Offset: 0x0804 */ + __IO uint32_t DSTS; /* Address Offset: 0x0808 */ + uint32_t RESERVED0; /* Address Offset: 0x080C */ + __IO uint32_t DIEPMSK; /* Address Offset: 0x0810 */ + __IO uint32_t DOEPMSK; /* Address Offset: 0x0814 */ + __IO uint32_t DAINT; /* Address Offset: 0x0818 */ + __IO uint32_t DAINTMSK; /* Address Offset: 0x081C */ + uint32_t RESERVED1[2]; /* Address Offset: 0x0820 */ + __IO uint32_t DVBUSDIS; /* Address Offset: 0x0828 */ + __IO uint32_t DVBUSPULSE; /* Address Offset: 0x082C */ + __IO uint32_t DTHRCTL; /* Address Offset: 0x0830 */ + __IO uint32_t DIEPEMPMSK; /* Address Offset: 0x0834 */ + __IO uint32_t DEACHINT; /* Address Offset: 0x0838 */ + __IO uint32_t DEACHMSK; /* Address Offset: 0x083C */ + uint32_t RESERVED2; /* Address Offset: 0x0840 */ + __IO uint32_t DINEP1MSK; /* Address Offset: 0x0844 */ + uint32_t RESERVED3[15]; /* Address Offset: 0x0848 */ + __IO uint32_t DOUTEP1MSK; /* Address Offset: 0x0884 */ +}; +/* USB_OTG_DEV_IN_ENDPOINT Register Structure Define */ +struct USB_IN_EP_REG { + __IO uint32_t DIEPCTL; /* Address Offset: 900h + (ep_num * 20h) + 00h */ + uint32_t RESERVED0; /* Address Offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /* Address Offset: 900h + (ep_num * 20h) + 08h */ + uint32_t RESERVED1; /* Address Offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /* Address Offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /* Address Offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /* Address Offset: 900h + (ep_num * 20h) + 18h */ + uint32_t RESERVED2; /* Address Offset: 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +}; +/* USB_OTG_DEV_OUT_ENDPOINT Register Structure Define */ +struct USB_OUT_EP_REG { + __IO uint32_t DOEPCTL; /* Address Offset: B00h + (ep_num * 20h) + 00h */ + uint32_t RESERVED0; /* Address Offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /* Address Offset: B00h + (ep_num * 20h) + 08h */ + uint32_t RESERVED1; /* Address Offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /* Address Offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /* Address Offset: B00h + (ep_num * 20h) + 14h */ + uint32_t RESERVED2[2]; /* Address Offset: B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +}; +/* USB_OTG_HOST Register Structure Define */ +struct USB_HOST_REG { + __IO uint32_t HCFG; /* Address Offset: 0x0400 */ + __IO uint32_t HFIR; /* Address Offset: 0x0404 */ + __IO uint32_t HFNUM; /* Address Offset: 0x0408 */ + uint32_t RESERVED0; /* Address Offset: 0x040C */ + __IO uint32_t HPTXSTS; /* Address Offset: 0x0410 */ + __IO uint32_t HAINT; /* Address Offset: 0x0414 */ + __IO uint32_t HAINTMSK; /* Address Offset: 0x0418 */ +}; +/* USB_OTG_HOST_CHANNEL Register Structure Define */ +struct USB_HOST_CH_REG { + __IO uint32_t HCCHAR; /* Address Offset: 0x0500 */ + __IO uint32_t HCSPLT; /* Address Offset: 0x0504 */ + __IO uint32_t HCINT; /* Address Offset: 0x0508 */ + __IO uint32_t HCINTMSK; /* Address Offset: 0x050C */ + __IO uint32_t HCTSIZ; /* Address Offset: 0x0510 */ + __IO uint32_t HCDMA; /* Address Offset: 0x0514 */ + uint32_t RESERVED0[2]; /* Address Offset: 0x0518 */ +}; +#endif /* __ASSEMBLY__ */ +/****************************************************************************************/ +/* */ +/* Module Variable Section */ +/* */ +/****************************************************************************************/ +/* Module Variable Define */ +#define USB ((struct USB_GLOBAL_REG *) USB_BASE) + +#define IS_PCD_INSTANCE(instance) ((instance) == USB) +#define IS_HCD_INSTANCE(instance) ((instance) == USB) +/****************************************************************************************/ +/* */ +/* Register Bitmap Section */ +/* */ +/****************************************************************************************/ +/***************************************USB_OTG_GOTGCTL*********************************/ +#define USB_OTG_GOTGCTL_SRQSCS_SHIFT (0U) +#define USB_OTG_GOTGCTL_SRQSCS_MASK (0x1U << USB_OTG_GOTGCTL_SRQSCS_SHIFT) /* 0x00000001 */ +#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_MASK /* Session request success */ +#define USB_OTG_GOTGCTL_SRQ_SHIFT (1U) +#define USB_OTG_GOTGCTL_SRQ_MASK (0x1U << USB_OTG_GOTGCTL_SRQ_SHIFT) /* 0x00000002 */ +#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_MASK /* Session request */ +#define USB_OTG_GOTGCTL_VBVALOEN_SHIFT (2U) +#define USB_OTG_GOTGCTL_VBVALOEN_MASK (0x1U << USB_OTG_GOTGCTL_VBVALOEN_SHIFT) /* 0x00000004 */ +#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_MASK /* VBUS valid override enable */ +#define USB_OTG_GOTGCTL_VBVALOVAL_SHIFT (3U) +#define USB_OTG_GOTGCTL_VBVALOVAL_MASK (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_SHIFT) /* 0x00000008 */ +#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_MASK /* VBUS valid override value */ +#define USB_OTG_GOTGCTL_AVALOEN_SHIFT (4U) +#define USB_OTG_GOTGCTL_AVALOEN_MASK (0x1U << USB_OTG_GOTGCTL_AVALOEN_SHIFT) /* 0x00000010 */ +#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_MASK /* A-peripheral session valid override enable */ +#define USB_OTG_GOTGCTL_AVALOVAL_SHIFT (5U) +#define USB_OTG_GOTGCTL_AVALOVAL_MASK (0x1U << USB_OTG_GOTGCTL_AVALOVAL_SHIFT) /* 0x00000020 */ +#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_MASK /* A-peripheral session valid override value */ +#define USB_OTG_GOTGCTL_BVALOEN_SHIFT (6U) +#define USB_OTG_GOTGCTL_BVALOEN_MASK (0x1U << USB_OTG_GOTGCTL_BVALOEN_SHIFT) /* 0x00000040 */ +#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_MASK /* B-peripheral session valid override enable */ +#define USB_OTG_GOTGCTL_BVALOVAL_SHIFT (7U) +#define USB_OTG_GOTGCTL_BVALOVAL_MASK (0x1U << USB_OTG_GOTGCTL_BVALOVAL_SHIFT) /* 0x00000080 */ +#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_MASK /* B-peripheral session valid override value */ +#define USB_OTG_GOTGCTL_HNGSCS_SHIFT (8U) +#define USB_OTG_GOTGCTL_HNGSCS_MASK (0x1U << USB_OTG_GOTGCTL_HNGSCS_SHIFT) /* 0x00000100 */ +#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_MASK /* Host set HNP enable */ +#define USB_OTG_GOTGCTL_HNPRQ_SHIFT (9U) +#define USB_OTG_GOTGCTL_HNPRQ_MASK (0x1U << USB_OTG_GOTGCTL_HNPRQ_SHIFT) /* 0x00000200 */ +#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_MASK /* HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN_SHIFT (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_MASK (0x1U << USB_OTG_GOTGCTL_HSHNPEN_SHIFT) /* 0x00000400 */ +#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_MASK /* Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN_SHIFT (11U) +#define USB_OTG_GOTGCTL_DHNPEN_MASK (0x1U << USB_OTG_GOTGCTL_DHNPEN_SHIFT) /* 0x00000800 */ +#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_MASK /* Device HNP enabled */ +#define USB_OTG_GOTGCTL_EHEN_SHIFT (12U) +#define USB_OTG_GOTGCTL_EHEN_MASK (0x1U << USB_OTG_GOTGCTL_EHEN_SHIFT) /* 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_MASK /* Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_SHIFT (16) +#define USB_OTG_GOTGCTL_CIDSTS_MASK (0x1U << USB_OTG_GOTGCTL_CIDSTS_SHIFT) /* 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_MASK /* Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_SHIFT (17U) +#define USB_OTG_GOTGCTL_DBCT_MASK (0x1U << USB_OTG_GOTGCTL_DBCT_SHIFT) /* 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_MASK /* Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_SHIFT (18U) +#define USB_OTG_GOTGCTL_ASVLD_MASK (0x1U << USB_OTG_GOTGCTL_ASVLD_SHIFT) /* 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_MASK /* A-session valid */ +#define USB_OTG_GOTGCTL_BSESVLD_SHIFT (19U) +#define USB_OTG_GOTGCTL_BSESVLD_MASK (0x1U << USB_OTG_GOTGCTL_BSESVLD_SHIFT) /* 0x00080000 */ +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_MASK /* B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_SHIFT (20U) +#define USB_OTG_GOTGCTL_OTGVER_MASK (0x1U << USB_OTG_GOTGCTL_OTGVER_SHIFT) /* 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_MASK /* OTG version */ +/******************** Bit definition for USB_OTG_GOTGINT register ********************/ +#define USB_OTG_GOTGINT_SEDET_SHIFT (2U) +#define USB_OTG_GOTGINT_SEDET_MASK (0x1U << USB_OTG_GOTGINT_SEDET_SHIFT) /* 0x00000004 */ +#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_MASK /* Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG_SHIFT (8U) +#define USB_OTG_GOTGINT_SRSSCHG_MASK (0x1U << USB_OTG_GOTGINT_SRSSCHG_SHIFT) /* 0x00000100 */ +#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_MASK /* Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG_SHIFT (9U) +#define USB_OTG_GOTGINT_HNSSCHG_MASK (0x1U << USB_OTG_GOTGINT_HNSSCHG_SHIFT) /* 0x00000200 */ +#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_MASK /* Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET_SHIFT (17U) +#define USB_OTG_GOTGINT_HNGDET_MASK (0x1U << USB_OTG_GOTGINT_HNGDET_SHIFT) /* 0x00020000 */ +#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_MASK /* Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG_SHIFT (18U) +#define USB_OTG_GOTGINT_ADTOCHG_MASK (0x1U << USB_OTG_GOTGINT_ADTOCHG_SHIFT) /* 0x00040000 */ +#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_MASK /* A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE_SHIFT (19U) +#define USB_OTG_GOTGINT_DBCDNE_MASK (0x1U << USB_OTG_GOTGINT_DBCDNE_SHIFT) /* 0x00080000 */ +#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_MASK /* Debounce done */ +#define USB_OTG_GOTGINT_IDCHNG_SHIFT (20U) +#define USB_OTG_GOTGINT_IDCHNG_MASK (0x1U << USB_OTG_GOTGINT_IDCHNG_SHIFT) /* 0x00100000 */ +#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_MASK /* Change in ID pin input value */ +/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ +#define USB_OTG_GAHBCFG_GINT_SHIFT (0U) +#define USB_OTG_GAHBCFG_GINT_MASK (0x1U << USB_OTG_GAHBCFG_GINT_SHIFT) /* 0x00000001 */ +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_MASK /* Global interrupt mask */ +#define USB_OTG_GAHBCFG_HBSTLEN_SHIFT (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_MASK (0xFU << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* 0x0000001E */ +#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_MASK /* Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* Single */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* INCR */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* INCR4 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* INCR8 */ +#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* INCR16 */ +#define USB_OTG_GAHBCFG_DMAEN_SHIFT (5U) +#define USB_OTG_GAHBCFG_DMAEN_MASK (0x1U << USB_OTG_GAHBCFG_DMAEN_SHIFT) /* 0x00000020 */ +#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_MASK /* DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL_SHIFT (7U) +#define USB_OTG_GAHBCFG_TXFELVL_MASK (0x1U << USB_OTG_GAHBCFG_TXFELVL_SHIFT) /* 0x00000080 */ +#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_MASK /* TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL_SHIFT (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_MASK (0x1U << USB_OTG_GAHBCFG_PTXFELVL_SHIFT) /* 0x00000100 */ +#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_MASK /* Periodic TxFIFO empty level */ +/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ +#define USB_OTG_GUSBCFG_TOCAL_SHIFT (0U) +#define USB_OTG_GUSBCFG_TOCAL_MASK (0x7U << USB_OTG_GUSBCFG_TOCAL_SHIFT) /* 0x00000007 */ +#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_MASK /* FS timeout calibration */ +#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_SHIFT) /* 0x00000001 */ +#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_SHIFT) /* 0x00000002 */ +#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_SHIFT) /* 0x00000004 */ +#define USB_OTG_GUSBCFG_PHYIF_SHIFT (3U) +#define USB_OTG_GUSBCFG_PHYIF_MASK (0x1U << USB_OTG_GUSBCFG_PHYIF_SHIFT) /* 0x00000008 */ +#define USB_OTG_GUSBCFG_PHYIF USB_OTG_GUSBCFG_PHYIF_MASK /* PHY Interface (PHYIf) */ +#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_SHIFT (4U) +#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_MASK (0x1U << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_SHIFT) /* 0x00000010 */ +#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL USB_OTG_GUSBCFG_ULPI_UTMI_SEL_MASK /* ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ +#define USB_OTG_GUSBCFG_PHYSEL_SHIFT (6U) +#define USB_OTG_GUSBCFG_PHYSEL_MASK (0x1U << USB_OTG_GUSBCFG_PHYSEL_SHIFT) /* 0x00000040 */ +#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_MASK /* USB 2.0 high-speed PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_SRPCAP_SHIFT (8U) +#define USB_OTG_GUSBCFG_SRPCAP_MASK (0x1U << USB_OTG_GUSBCFG_SRPCAP_SHIFT) /* 0x00000100 */ +#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_MASK /* SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP_SHIFT (9U) +#define USB_OTG_GUSBCFG_HNPCAP_MASK (0x1U << USB_OTG_GUSBCFG_HNPCAP_SHIFT) /* 0x00000200 */ +#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_MASK /* HNP-capable */ +#define USB_OTG_GUSBCFG_TRDT_SHIFT (10U) +#define USB_OTG_GUSBCFG_TRDT_MASK (0xFU << USB_OTG_GUSBCFG_TRDT_SHIFT) /* 0x00003C00 */ +#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_MASK /* USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_SHIFT) /* 0x00000400 */ +#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_SHIFT) /* 0x00000800 */ +#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_SHIFT) /* 0x00001000 */ +#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_SHIFT) /* 0x00002000 */ +#define USB_OTG_GUSBCFG_PHYLPCS_SHIFT (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_MASK (0x1U << USB_OTG_GUSBCFG_PHYLPCS_SHIFT) /* 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_MASK /* PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS_SHIFT (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_MASK (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_SHIFT) /* 0x00020000 */ +#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_MASK /* ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR_SHIFT (18U) +#define USB_OTG_GUSBCFG_ULPIAR_MASK (0x1U << USB_OTG_GUSBCFG_ULPIAR_SHIFT) /* 0x00040000 */ +#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_MASK /* ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM_SHIFT (19U) +#define USB_OTG_GUSBCFG_ULPICSM_MASK (0x1U << USB_OTG_GUSBCFG_ULPICSM_SHIFT) /* 0x00080000 */ +#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_MASK /* ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD_SHIFT (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_MASK (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_SHIFT) /* 0x00100000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_MASK /* ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI_SHIFT (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_MASK (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_SHIFT) /* 0x00200000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_MASK /* ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS_SHIFT (22U) +#define USB_OTG_GUSBCFG_TSDPS_MASK (0x1U << USB_OTG_GUSBCFG_TSDPS_SHIFT) /* 0x00400000 */ +#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_MASK /* TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI_SHIFT (23U) +#define USB_OTG_GUSBCFG_PCCI_MASK (0x1U << USB_OTG_GUSBCFG_PCCI_SHIFT) /* 0x00800000 */ +#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_MASK /* Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI_SHIFT (24U) +#define USB_OTG_GUSBCFG_PTCI_MASK (0x1U << USB_OTG_GUSBCFG_PTCI_SHIFT) /* 0x01000000 */ +#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_MASK /* Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD_SHIFT (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_MASK (0x1U << USB_OTG_GUSBCFG_ULPIIPD_SHIFT) /* 0x02000000 */ +#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_MASK /* ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD_SHIFT (29U) +#define USB_OTG_GUSBCFG_FHMOD_MASK (0x1U << USB_OTG_GUSBCFG_FHMOD_SHIFT) /* 0x20000000 */ +#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_MASK /* Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD_SHIFT (30U) +#define USB_OTG_GUSBCFG_FDMOD_MASK (0x1U << USB_OTG_GUSBCFG_FDMOD_SHIFT) /* 0x40000000 */ +#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_MASK /* Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT_SHIFT (31U) +#define USB_OTG_GUSBCFG_CTXPKT_MASK (0x1U << USB_OTG_GUSBCFG_CTXPKT_SHIFT) /* 0x80000000 */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_MASK /* Corrupt Tx packet */ +/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ +#define USB_OTG_GRSTCTL_CSRST_SHIFT (0U) +#define USB_OTG_GRSTCTL_CSRST_MASK (0x1U << USB_OTG_GRSTCTL_CSRST_SHIFT) /* 0x00000001 */ +#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_MASK /* Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST_SHIFT (1U) +#define USB_OTG_GRSTCTL_HSRST_MASK (0x1U << USB_OTG_GRSTCTL_HSRST_SHIFT) /* 0x00000002 */ +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_MASK /* HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST_SHIFT (2U) +#define USB_OTG_GRSTCTL_FCRST_MASK (0x1U << USB_OTG_GRSTCTL_FCRST_SHIFT) /* 0x00000004 */ +#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_MASK /* Host frame counter reset */ +#define USB_OTG_GRSTCTL_INTKNQFLSH_SHIFT (3U) +#define USB_OTG_GRSTCTL_INTKNQFLSH_MASK (0x1U << USB_OTG_GRSTCTL_INTKNQFLSH_SHIFT) /* 0x00000080 */ +#define USB_OTG_GRSTCTL_INTKNQFLSH USB_OTG_GRSTCTL_INTKNQFLSH_MASK /* INTknQ flush */ +#define USB_OTG_GRSTCTL_RXFFLSH_SHIFT (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_MASK (0x1U << USB_OTG_GRSTCTL_RXFFLSH_SHIFT) /* 0x00000010 */ +#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_MASK /* RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH_SHIFT (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_MASK (0x1U << USB_OTG_GRSTCTL_TXFFLSH_SHIFT) /* 0x00000020 */ +#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_MASK /* TxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFNUM_SHIFT (6U) +#define USB_OTG_GRSTCTL_TXFNUM_MASK (0x1FU << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x000007C0 */ +#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_MASK /* TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x00000040 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x00000080 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x00000100 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x00000200 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x00000400 */ +#define USB_OTG_GRSTCTL_DMAREQ_SHIFT (30U) +#define USB_OTG_GRSTCTL_DMAREQ_MASK (0x1U << USB_OTG_GRSTCTL_DMAREQ_SHIFT) /* 0x40000000 */ +#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_MASK /* DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL_SHIFT (31U) +#define USB_OTG_GRSTCTL_AHBIDL_MASK (0x1U << USB_OTG_GRSTCTL_AHBIDL_SHIFT) /* 0x80000000 */ +#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_MASK /* AHB master idle */ +/******************** Bit definition for USB_OTG_GINTSTS register ********************/ +#define USB_OTG_GINTSTS_CMOD_SHIFT (0U) +#define USB_OTG_GINTSTS_CMOD_MASK (0x1U << USB_OTG_GINTSTS_CMOD_SHIFT) /* 0x00000001 */ +#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_MASK /* Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS_SHIFT (1U) +#define USB_OTG_GINTSTS_MMIS_MASK (0x1U << USB_OTG_GINTSTS_MMIS_SHIFT) /* 0x00000002 */ +#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_MASK /* Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT_SHIFT (2U) +#define USB_OTG_GINTSTS_OTGINT_MASK (0x1U << USB_OTG_GINTSTS_OTGINT_SHIFT) /* 0x00000004 */ +#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_MASK /* OTG interrupt */ +#define USB_OTG_GINTSTS_SOF_SHIFT (3U) +#define USB_OTG_GINTSTS_SOF_MASK (0x1U << USB_OTG_GINTSTS_SOF_SHIFT) /* 0x00000008 */ +#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_MASK /* Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL_SHIFT (4U) +#define USB_OTG_GINTSTS_RXFLVL_MASK (0x1U << USB_OTG_GINTSTS_RXFLVL_SHIFT) /* 0x00000010 */ +#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_MASK /* RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE_SHIFT (5U) +#define USB_OTG_GINTSTS_NPTXFE_MASK (0x1U << USB_OTG_GINTSTS_NPTXFE_SHIFT) /* 0x00000020 */ +#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_MASK /* Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF_SHIFT (6U) +#define USB_OTG_GINTSTS_GINAKEFF_MASK (0x1U << USB_OTG_GINTSTS_GINAKEFF_SHIFT) /* 0x00000040 */ +#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_MASK /* Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF_SHIFT (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_MASK (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_SHIFT) /* 0x00000080 */ +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_MASK /* Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP_SHIFT (10U) +#define USB_OTG_GINTSTS_ESUSP_MASK (0x1U << USB_OTG_GINTSTS_ESUSP_SHIFT) /* 0x00000400 */ +#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_MASK /* Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP_SHIFT (11U) +#define USB_OTG_GINTSTS_USBSUSP_MASK (0x1U << USB_OTG_GINTSTS_USBSUSP_SHIFT) /* 0x00000800 */ +#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_MASK /* USB suspend */ +#define USB_OTG_GINTSTS_USBRST_SHIFT (12U) +#define USB_OTG_GINTSTS_USBRST_MASK (0x1U << USB_OTG_GINTSTS_USBRST_SHIFT) /* 0x00001000 */ +#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_MASK /* USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE_SHIFT (13U) +#define USB_OTG_GINTSTS_ENUMDNE_MASK (0x1U << USB_OTG_GINTSTS_ENUMDNE_SHIFT) /* 0x00002000 */ +#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_MASK /* Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP_SHIFT (14U) +#define USB_OTG_GINTSTS_ISOODRP_MASK (0x1U << USB_OTG_GINTSTS_ISOODRP_SHIFT) /* 0x00004000 */ +#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_MASK /* Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF_SHIFT (15U) +#define USB_OTG_GINTSTS_EOPF_MASK (0x1U << USB_OTG_GINTSTS_EOPF_SHIFT) /* 0x00008000 */ +#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_MASK /* End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT_SHIFT (18U) +#define USB_OTG_GINTSTS_IEPINT_MASK (0x1U << USB_OTG_GINTSTS_IEPINT_SHIFT) /* 0x00040000 */ +#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_MASK /* IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT_SHIFT (19U) +#define USB_OTG_GINTSTS_OEPINT_MASK (0x1U << USB_OTG_GINTSTS_OEPINT_SHIFT) /* 0x00080000 */ +#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_MASK /* OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR_SHIFT (20U) +#define USB_OTG_GINTSTS_IISOIXFR_MASK (0x1U << USB_OTG_GINTSTS_IISOIXFR_SHIFT) /* 0x00100000 */ +#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_MASK /* Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_SHIFT (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_MASK (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_SHIFT) /* 0x00200000 */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_MASK /* Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP_SHIFT (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_MASK (0x1U << USB_OTG_GINTSTS_DATAFSUSP_SHIFT) /* 0x00400000 */ +#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_MASK /* Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_SHIFT (23U) +#define USB_OTG_GINTSTS_RSTDET_MASK (0x1U << USB_OTG_GINTSTS_RSTDET_SHIFT) /* 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_MASK /* Reset detected interrupt */ +#define USB_OTG_GINTSTS_HPRTINT_SHIFT (24U) +#define USB_OTG_GINTSTS_HPRTINT_MASK (0x1U << USB_OTG_GINTSTS_HPRTINT_SHIFT) /* 0x01000000 */ +#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_MASK /* Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT_SHIFT (25U) +#define USB_OTG_GINTSTS_HCINT_MASK (0x1U << USB_OTG_GINTSTS_HCINT_SHIFT) /* 0x02000000 */ +#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_MASK /* Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE_SHIFT (26U) +#define USB_OTG_GINTSTS_PTXFE_MASK (0x1U << USB_OTG_GINTSTS_PTXFE_SHIFT) /* 0x04000000 */ +#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_MASK /* Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_LPMINT_SHIFT (27U) +#define USB_OTG_GINTSTS_LPMINT_MASK (0x1U << USB_OTG_GINTSTS_LPMINT_SHIFT) /* 0x08000000 */ +#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_MASK /* LPM interrupt */ +#define USB_OTG_GINTSTS_CIDSCHG_SHIFT (28U) +#define USB_OTG_GINTSTS_CIDSCHG_MASK (0x1U << USB_OTG_GINTSTS_CIDSCHG_SHIFT) /* 0x10000000 */ +#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_MASK /* Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT_SHIFT (29U) +#define USB_OTG_GINTSTS_DISCINT_MASK (0x1U << USB_OTG_GINTSTS_DISCINT_SHIFT) /* 0x20000000 */ +#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_MASK /* Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT_SHIFT (30U) +#define USB_OTG_GINTSTS_SRQINT_MASK (0x1U << USB_OTG_GINTSTS_SRQINT_SHIFT) /* 0x40000000 */ +#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_MASK /* Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT_SHIFT (31U) +#define USB_OTG_GINTSTS_WKUINT_MASK (0x1U << USB_OTG_GINTSTS_WKUINT_SHIFT) /* 0x80000000 */ +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_MASK /* Resume/remote wakeup detected interrupt */ +/******************** Bit definition for USB_OTG_GINTMSK register ********************/ +#define USB_OTG_GINTMSK_MMISM_SHIFT (1U) +#define USB_OTG_GINTMSK_MMISM_MASK (0x1U << USB_OTG_GINTMSK_MMISM_SHIFT) /* 0x00000002 */ +#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_MASK /* Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT_SHIFT (2U) +#define USB_OTG_GINTMSK_OTGINT_MASK (0x1U << USB_OTG_GINTMSK_OTGINT_SHIFT) /* 0x00000004 */ +#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_MASK /* OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM_SHIFT (3U) +#define USB_OTG_GINTMSK_SOFM_MASK (0x1U << USB_OTG_GINTMSK_SOFM_SHIFT) /* 0x00000008 */ +#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_MASK /* Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM_SHIFT (4U) +#define USB_OTG_GINTMSK_RXFLVLM_MASK (0x1U << USB_OTG_GINTMSK_RXFLVLM_SHIFT) /* 0x00000010 */ +#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_MASK /* Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM_SHIFT (5U) +#define USB_OTG_GINTMSK_NPTXFEM_MASK (0x1U << USB_OTG_GINTMSK_NPTXFEM_SHIFT) /* 0x00000020 */ +#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_MASK /* Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM_SHIFT (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_MASK (0x1U << USB_OTG_GINTMSK_GINAKEFFM_SHIFT) /* 0x00000040 */ +#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_MASK /* Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM_SHIFT (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_MASK (0x1U << USB_OTG_GINTMSK_GONAKEFFM_SHIFT) /* 0x00000080 */ +#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_MASK /* Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM_SHIFT (10U) +#define USB_OTG_GINTMSK_ESUSPM_MASK (0x1U << USB_OTG_GINTMSK_ESUSPM_SHIFT) /* 0x00000400 */ +#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_MASK /* Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM_SHIFT (11U) +#define USB_OTG_GINTMSK_USBSUSPM_MASK (0x1U << USB_OTG_GINTMSK_USBSUSPM_SHIFT) /* 0x00000800 */ +#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_MASK /* USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST_SHIFT (12U) +#define USB_OTG_GINTMSK_USBRST_MASK (0x1U << USB_OTG_GINTMSK_USBRST_SHIFT) /* 0x00001000 */ +#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_MASK /* USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM_SHIFT (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_MASK (0x1U << USB_OTG_GINTMSK_ENUMDNEM_SHIFT) /* 0x00002000 */ +#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_MASK /* Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM_SHIFT (14U) +#define USB_OTG_GINTMSK_ISOODRPM_MASK (0x1U << USB_OTG_GINTMSK_ISOODRPM_SHIFT) /* 0x00004000 */ +#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_MASK /* Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM_SHIFT (15U) +#define USB_OTG_GINTMSK_EOPFM_MASK (0x1U << USB_OTG_GINTMSK_EOPFM_SHIFT) /* 0x00008000 */ +#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_MASK /* End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM_SHIFT (17U) +#define USB_OTG_GINTMSK_EPMISM_MASK (0x1U << USB_OTG_GINTMSK_EPMISM_SHIFT) /* 0x00020000 */ +#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_MASK /* Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT_SHIFT (18U) +#define USB_OTG_GINTMSK_IEPINT_MASK (0x1U << USB_OTG_GINTMSK_IEPINT_SHIFT) /* 0x00040000 */ +#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_MASK /* IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT_SHIFT (19U) +#define USB_OTG_GINTMSK_OEPINT_MASK (0x1U << USB_OTG_GINTMSK_OEPINT_SHIFT) /* 0x00080000 */ +#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_MASK /* OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM_SHIFT (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_MASK (0x1U << USB_OTG_GINTMSK_IISOIXFRM_SHIFT) /* 0x00100000 */ +#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_MASK /* Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_SHIFT (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_MASK (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_SHIFT) /* 0x00200000 */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_MASK /* Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM_SHIFT (22U) +#define USB_OTG_GINTMSK_FSUSPM_MASK (0x1U << USB_OTG_GINTMSK_FSUSPM_SHIFT) /* 0x00400000 */ +#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_MASK /* Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDEM_SHIFT (23U) +#define USB_OTG_GINTMSK_RSTDEM_MASK (0x1U << USB_OTG_GINTMSK_RSTDEM_SHIFT) /* 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_MASK /* Reset detected interrupt mask */ +#define USB_OTG_GINTMSK_PRTIM_SHIFT (24U) +#define USB_OTG_GINTMSK_PRTIM_MASK (0x1U << USB_OTG_GINTMSK_PRTIM_SHIFT) /* 0x01000000 */ +#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_MASK /* Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM_SHIFT (25U) +#define USB_OTG_GINTMSK_HCIM_MASK (0x1U << USB_OTG_GINTMSK_HCIM_SHIFT) /* 0x02000000 */ +#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_MASK /* Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM_SHIFT (26U) +#define USB_OTG_GINTMSK_PTXFEM_MASK (0x1U << USB_OTG_GINTMSK_PTXFEM_SHIFT) /* 0x04000000 */ +#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_MASK /* Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_LPMINTM_SHIFT (27U) +#define USB_OTG_GINTMSK_LPMINTM_MASK (0x1U << USB_OTG_GINTMSK_LPMINTM_SHIFT) /* 0x08000000 */ +#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_MASK /* LPM interrupt Mask */ +#define USB_OTG_GINTMSK_CIDSCHGM_SHIFT (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_MASK (0x1U << USB_OTG_GINTMSK_CIDSCHGM_SHIFT) /* 0x10000000 */ +#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_MASK /* Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT_SHIFT (29U) +#define USB_OTG_GINTMSK_DISCINT_MASK (0x1U << USB_OTG_GINTMSK_DISCINT_SHIFT) /* 0x20000000 */ +#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_MASK /* Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM_SHIFT (30U) +#define USB_OTG_GINTMSK_SRQIM_MASK (0x1U << USB_OTG_GINTMSK_SRQIM_SHIFT) /* 0x40000000 */ +#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_MASK /* Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM_SHIFT (31U) +#define USB_OTG_GINTMSK_WUIM_MASK (0x1U << USB_OTG_GINTMSK_WUIM_SHIFT) /* 0x80000000 */ +#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_MASK /* Resume/remote wakeup detected interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ +#define USB_OTG_GRXSTSP_EPNUM_SHIFT (0U) +#define USB_OTG_GRXSTSP_EPNUM_MASK (0xFU << USB_OTG_GRXSTSP_EPNUM_SHIFT) /* 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_MASK /* IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT_SHIFT (4U) +#define USB_OTG_GRXSTSP_BCNT_MASK (0x7FFU << USB_OTG_GRXSTSP_BCNT_SHIFT) /* 0x00007FF0 */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_MASK /* OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID_SHIFT (15U) +#define USB_OTG_GRXSTSP_DPID_MASK (0x3U << USB_OTG_GRXSTSP_DPID_SHIFT) /* 0x00018000 */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_MASK /* OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS_SHIFT (17U) +#define USB_OTG_GRXSTSP_PKTSTS_MASK (0xFU << USB_OTG_GRXSTSP_PKTSTS_SHIFT) /* 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_MASK /* OUT EP interrupt mask bits */ +/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ +#define USB_OTG_GRXFSIZ_RXFD_SHIFT (0U) +#define USB_OTG_GRXFSIZ_RXFD_MASK (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_MASK /* RxFIFO depth */ +/******************** Bit definition for USB_OTG_GNPTXFSIZ register *******************/ +#define USB_OTG_GNPTXFSIZ_NPTXFSA_SHIFT (0U) +#define USB_OTG_GNPTXFSIZ_NPTXFSA_MASK (0xFFFFU << USB_OTG_GNPTXFSIZ_NPTXFSA_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_GNPTXFSIZ_NPTXFSA USB_OTG_GNPTXFSIZ_NPTXFSA_MASK /* Nonperiodic transmit RAM start address */ +#define USB_OTG_GNPTXFSIZ_NPTXFD_SHIFT (16U) +#define USB_OTG_GNPTXFSIZ_NPTXFD_MASK (0xFFFFU << USB_OTG_GNPTXFSIZ_NPTXFD_SHIFT) /* 0xFFFF0000 */ +#define USB_OTG_GNPTXFSIZ_NPTXFD USB_OTG_GNPTXFSIZ_NPTXFD_MASK /* Nonperiodic TxFIFO depth */ +#define USB_OTG_GNPTXFSIZ_TXF0SA_SHIFT (0U) +#define USB_OTG_GNPTXFSIZ_TXF0SA_MASK (0xFFFFU << USB_OTG_GNPTXFSIZ_TXF0SA_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_GNPTXFSIZ_TXF0SA USB_OTG_GNPTXFSIZ_TXF0SA_MASK /* Endpoint 0 transmit RAM start address */ +#define USB_OTG_GNPTXFSIZ_TXF0D_SHIFT (16U) +#define USB_OTG_GNPTXFSIZ_TXF0D_MASK (0xFFFFU << USB_OTG_GNPTXFSIZ_TXF0D_SHIFT) /* 0xFFFF0000 */ +#define USB_OTG_GNPTXFSIZ_TXF0D USB_OTG_GNPTXFSIZ_TXF0D_MASK /* Endpoint 0 TxFIFO depth */ +/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ +#define USB_OTG_GNPTXSTS_NPTXFSAV_SHIFT (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_MASK (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_MASK /* Nonperiodic TxFIFO space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_MASK (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00FF0000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_MASK /* Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00010000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00020000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00040000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00080000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00100000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00200000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00400000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00800000 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_MASK (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x7F000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_MASK /* Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x01000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x02000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x04000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x08000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x10000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x20000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x40000000 */ +/******************** Bit definition for USB_OTG_GHWCFG2 register ********************/ +#define USB_OTG_GHWCFG2_DYNFIFOSIZING_SHIFT (19U) +#define USB_OTG_GHWCFG2_DYNFIFOSIZING_MASK (0x1U << USB_OTG_GHWCFG2_DYNFIFOSIZING_SHIFT) /* 0x00080000 */ +#define USB_OTG_GHWCFG2_DYNFIFOSIZING USB_OTG_GHWCFG2_DYNFIFOSIZING_MASK /* Dynamic FIFO Sizing enabled */ +/******************** Bit definition for USB_OTG_GHWCFG4 register ********************/ +#define USB_OTG_GHWCFG4_DEDFIFOMODE_SHIFT (25U) +#define USB_OTG_GHWCFG4_DEDFIFOMODE_MASK (0x1U << USB_OTG_GHWCFG4_DEDFIFOMODE_SHIFT) /* 0x00080000 */ +#define USB_OTG_GHWCFG4_DEDFIFOMODE USB_OTG_GHWCFG4_DEDFIFOMODE_MASK /* Dedicated FIFO enabled */ +/******************** Bit definition for USB_OTG_GLPMCFG register ********************/ +#define USB_OTG_GLPMCFG_LPMEN_SHIFT (0U) +#define USB_OTG_GLPMCFG_LPMEN_MASK (0x1U << USB_OTG_GLPMCFG_LPMEN_SHIFT) /* 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_MASK /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_SHIFT (1U) +#define USB_OTG_GLPMCFG_LPMACK_MASK (0x1U << USB_OTG_GLPMCFG_LPMACK_SHIFT) /* 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_MASK /* LPM Token acknowledge enable */ +#define USB_OTG_GLPMCFG_BESL_SHIFT (2U) +#define USB_OTG_GLPMCFG_BESL_MASK (0xFU << USB_OTG_GLPMCFG_BESL_SHIFT) /* 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_MASK /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_SHIFT (6U) +#define USB_OTG_GLPMCFG_REMWAKE_MASK (0x1U << USB_OTG_GLPMCFG_REMWAKE_SHIFT) /* 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_MASK /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_SHIFT (7U) +#define USB_OTG_GLPMCFG_L1SSEN_MASK (0x1U << USB_OTG_GLPMCFG_L1SSEN_SHIFT) /* 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_MASK /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_SHIFT (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_MASK (0xFU << USB_OTG_GLPMCFG_BESLTHRS_SHIFT) /* 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_MASK /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_SHIFT (12U) +#define USB_OTG_GLPMCFG_L1DSEN_MASK (0x1U << USB_OTG_GLPMCFG_L1DSEN_SHIFT) /* 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_MASK /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_SHIFT (13U) +#define USB_OTG_GLPMCFG_LPMRSP_MASK (0x3U << USB_OTG_GLPMCFG_LPMRSP_SHIFT) /* 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_MASK /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_SHIFT (15U) +#define USB_OTG_GLPMCFG_SLPSTS_MASK (0x1U << USB_OTG_GLPMCFG_SLPSTS_SHIFT) /* 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_MASK /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_SHIFT (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_MASK (0x1U << USB_OTG_GLPMCFG_L1RSMOK_SHIFT) /* 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_MASK /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_SHIFT (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_MASK (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_SHIFT) /* 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_MASK /* LPM Channel Index */ +#define USB_OTG_GLPMCFG_LPMRCNT_SHIFT (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_MASK (0x7U << USB_OTG_GLPMCFG_LPMRCNT_SHIFT) /* 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_MASK /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_SHIFT (24U) +#define USB_OTG_GLPMCFG_SNDLPM_MASK (0x1U << USB_OTG_GLPMCFG_SNDLPM_SHIFT) /* 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_MASK /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_SHIFT (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_MASK (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_SHIFT) /* 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_MASK /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_SHIFT (28U) +#define USB_OTG_GLPMCFG_ENBESL_MASK (0x1U << USB_OTG_GLPMCFG_ENBESL_SHIFT) /* 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_MASK /* Enable best effort service latency */ +/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ +#define USB_OTG_HPTXFSIZ_PTXSA_SHIFT (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_MASK (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_MASK /* Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD_SHIFT (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_MASK (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_SHIFT) /* 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_MASK /* Host periodic TxFIFO depth */ +/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ +#define USB_OTG_DIEPTXF_INEPTXSA_SHIFT (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_MASK (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_MASK /* IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD_SHIFT (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_MASK (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_SHIFT) /* 0xFFFF0000 */ +#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_MASK /* IN endpoint TxFIFO depth */ +/******************** Bit definition for USB_OTG_HCFG register ********************/ +#define USB_OTG_HCFG_FSLSPCS_SHIFT (0U) +#define USB_OTG_HCFG_FSLSPCS_MASK (0x3U << USB_OTG_HCFG_FSLSPCS_SHIFT) /* 0x00000003 */ +#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_MASK /* FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_SHIFT) /* 0x00000001 */ +#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_SHIFT) /* 0x00000002 */ +#define USB_OTG_HCFG_FSLSS_SHIFT (2U) +#define USB_OTG_HCFG_FSLSS_MASK (0x1U << USB_OTG_HCFG_FSLSS_SHIFT) /* 0x00000004 */ +#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_MASK /* FS- and LS-only support */ +/******************** Bit definition for USB_OTG_HFIR register ********************/ +#define USB_OTG_HFIR_FRIVL_SHIFT (0U) +#define USB_OTG_HFIR_FRIVL_MASK (0xFFFFU << USB_OTG_HFIR_FRIVL_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_MASK /* Frame interval */ +/******************** Bit definition for USB_OTG_HFNUM register ********************/ +#define USB_OTG_HFNUM_FRNUM_SHIFT (0U) +#define USB_OTG_HFNUM_FRNUM_MASK (0xFFFFU << USB_OTG_HFNUM_FRNUM_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_MASK /* Frame number */ +#define USB_OTG_HFNUM_FTREM_SHIFT (16U) +#define USB_OTG_HFNUM_FTREM_MASK (0xFFFFU << USB_OTG_HFNUM_FTREM_SHIFT) /* 0xFFFF0000 */ +#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_MASK /* Frame time remaining */ +/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ +#define USB_OTG_HPTXSTS_PTXFSAVL_SHIFT (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_MASK (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_MASK /* Periodic transmit data FIFO space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_SHIFT (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_MASK (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00FF0000 */ +#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_MASK /* Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00010000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00020000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00040000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00080000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00100000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00200000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00400000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00800000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_SHIFT (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_MASK (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0xFF000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_MASK /* Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x01000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x02000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x04000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x08000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x10000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x20000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x40000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x80000000 */ +/******************** Bit definition for USB_OTG_HAINT register ********************/ +#define USB_OTG_HAINT_HAINT_SHIFT (0U) +#define USB_OTG_HAINT_HAINT_MASK (0xFFFFU << USB_OTG_HAINT_HAINT_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_MASK /* Channel interrupts */ +/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ +#define USB_OTG_HAINTMSK_HAINTM_SHIFT (0U) +#define USB_OTG_HAINTMSK_HAINTM_MASK (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_MASK /* Channel interrupt mask */ +/******************** Bit definition for USB_OTG_HPRT register ********************/ +#define USB_OTG_HPRT_PCSTS_SHIFT (0U) +#define USB_OTG_HPRT_PCSTS_MASK (0x1U << USB_OTG_HPRT_PCSTS_SHIFT) /* 0x00000001 */ +#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_MASK /* Port connect status */ +#define USB_OTG_HPRT_PCDET_SHIFT (1U) +#define USB_OTG_HPRT_PCDET_MASK (0x1U << USB_OTG_HPRT_PCDET_SHIFT) /* 0x00000002 */ +#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_MASK /* Port connect detected */ +#define USB_OTG_HPRT_PENA_SHIFT (2U) +#define USB_OTG_HPRT_PENA_MASK (0x1U << USB_OTG_HPRT_PENA_SHIFT) /* 0x00000004 */ +#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_MASK /* Port enable */ +#define USB_OTG_HPRT_PENCHNG_SHIFT (3U) +#define USB_OTG_HPRT_PENCHNG_MASK (0x1U << USB_OTG_HPRT_PENCHNG_SHIFT) /* 0x00000008 */ +#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_MASK /* Port enable/disable change */ +#define USB_OTG_HPRT_POCA_SHIFT (4U) +#define USB_OTG_HPRT_POCA_MASK (0x1U << USB_OTG_HPRT_POCA_SHIFT) /* 0x00000010 */ +#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_MASK /* Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG_SHIFT (5U) +#define USB_OTG_HPRT_POCCHNG_MASK (0x1U << USB_OTG_HPRT_POCCHNG_SHIFT) /* 0x00000020 */ +#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_MASK /* Port overcurrent change */ +#define USB_OTG_HPRT_PRES_SHIFT (6U) +#define USB_OTG_HPRT_PRES_MASK (0x1U << USB_OTG_HPRT_PRES_SHIFT) /* 0x00000040 */ +#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_MASK /* Port resume */ +#define USB_OTG_HPRT_PSUSP_SHIFT (7U) +#define USB_OTG_HPRT_PSUSP_MASK (0x1U << USB_OTG_HPRT_PSUSP_SHIFT) /* 0x00000080 */ +#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_MASK /* Port suspend */ +#define USB_OTG_HPRT_PRST_SHIFT (8U) +#define USB_OTG_HPRT_PRST_MASK (0x1U << USB_OTG_HPRT_PRST_SHIFT) /* 0x00000100 */ +#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_MASK /* Port reset */ +#define USB_OTG_HPRT_PLSTS_SHIFT (10U) +#define USB_OTG_HPRT_PLSTS_MASK (0x3U << USB_OTG_HPRT_PLSTS_SHIFT) /* 0x00000C00 */ +#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_MASK /* Port line status */ +#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_SHIFT) /* 0x00000400 */ +#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_SHIFT) /* 0x00000800 */ +#define USB_OTG_HPRT_PPWR_SHIFT (12U) +#define USB_OTG_HPRT_PPWR_MASK (0x1U << USB_OTG_HPRT_PPWR_SHIFT) /* 0x00001000 */ +#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_MASK /* Port power */ +#define USB_OTG_HPRT_PTCTL_SHIFT (13U) +#define USB_OTG_HPRT_PTCTL_MASK (0xFU << USB_OTG_HPRT_PTCTL_SHIFT) /* 0x0001E000 */ +#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_MASK /* Port test control */ +#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_SHIFT) /* 0x00002000 */ +#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_SHIFT) /* 0x00004000 */ +#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_SHIFT) /* 0x00008000 */ +#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_SHIFT) /* 0x00010000 */ +#define USB_OTG_HPRT_PSPD_SHIFT (17U) +#define USB_OTG_HPRT_PSPD_MASK (0x3U << USB_OTG_HPRT_PSPD_SHIFT) /* 0x00060000 */ +#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_MASK /* Port speed */ +#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_SHIFT) /* 0x00020000 */ +#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_SHIFT) /* 0x00040000 */ +/******************** Bit definition for USB_OTG_HCCHAR register ********************/ +#define USB_OTG_HCCHAR_MPSIZ_SHIFT (0U) +#define USB_OTG_HCCHAR_MPSIZ_MASK (0x7FFU << USB_OTG_HCCHAR_MPSIZ_SHIFT) /* 0x000007FF */ +#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_MASK /* Maximum packet size */ +#define USB_OTG_HCCHAR_EPNUM_SHIFT (11U) +#define USB_OTG_HCCHAR_EPNUM_MASK (0xFU << USB_OTG_HCCHAR_EPNUM_SHIFT) /* 0x00007800 */ +#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_MASK /* Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_SHIFT) /* 0x00000800 */ +#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_SHIFT) /* 0x00001000 */ +#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_SHIFT) /* 0x00002000 */ +#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_SHIFT) /* 0x00004000 */ +#define USB_OTG_HCCHAR_EPDIR_SHIFT (15U) +#define USB_OTG_HCCHAR_EPDIR_MASK (0x1U << USB_OTG_HCCHAR_EPDIR_SHIFT) /* 0x00008000 */ +#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_MASK /* Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV_SHIFT (17U) +#define USB_OTG_HCCHAR_LSDEV_MASK (0x1U << USB_OTG_HCCHAR_LSDEV_SHIFT) /* 0x00020000 */ +#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_MASK /* Low-speed device */ +#define USB_OTG_HCCHAR_EPTYP_SHIFT (18U) +#define USB_OTG_HCCHAR_EPTYP_MASK (0x3U << USB_OTG_HCCHAR_EPTYP_SHIFT) /* 0x000C0000 */ +#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_MASK /* Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_SHIFT) /* 0x00040000 */ +#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_SHIFT) /* 0x00080000 */ +#define USB_OTG_HCCHAR_MC_SHIFT (20U) +#define USB_OTG_HCCHAR_MC_MASK (0x3U << USB_OTG_HCCHAR_MC_SHIFT) /* 0x00300000 */ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_MASK /* Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_SHIFT) /* 0x00100000 */ +#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_SHIFT) /* 0x00200000 */ +#define USB_OTG_HCCHAR_DAD_SHIFT (22U) +#define USB_OTG_HCCHAR_DAD_MASK (0x7FU << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x1FC00000 */ +#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_MASK /* Device address */ +#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x00400000 */ +#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x00800000 */ +#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x01000000 */ +#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x02000000 */ +#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x04000000 */ +#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x08000000 */ +#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x10000000 */ +#define USB_OTG_HCCHAR_ODDFRM_SHIFT (29U) +#define USB_OTG_HCCHAR_ODDFRM_MASK (0x1U << USB_OTG_HCCHAR_ODDFRM_SHIFT) /* 0x20000000 */ +#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_MASK /* Odd frame */ +#define USB_OTG_HCCHAR_CHDIS_SHIFT (30U) +#define USB_OTG_HCCHAR_CHDIS_MASK (0x1U << USB_OTG_HCCHAR_CHDIS_SHIFT) /* 0x40000000 */ +#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_MASK /* Channel disable */ +#define USB_OTG_HCCHAR_CHENA_SHIFT (31U) +#define USB_OTG_HCCHAR_CHENA_MASK (0x1U << USB_OTG_HCCHAR_CHENA_SHIFT) /* 0x80000000 */ +#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_MASK /* Channel enable */ +/******************** Bit definition for USB_OTG_HCSPLT register ********************/ +#define USB_OTG_HCSPLT_PRTADDR_SHIFT (0U) +#define USB_OTG_HCSPLT_PRTADDR_MASK (0x7FU << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x0000007F */ +#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_MASK /* Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000001 */ +#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000002 */ +#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000004 */ +#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000008 */ +#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000010 */ +#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000020 */ +#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000040 */ +#define USB_OTG_HCSPLT_HUBADDR_SHIFT (7U) +#define USB_OTG_HCSPLT_HUBADDR_MASK (0x7FU << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00003F80 */ +#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_MASK /* Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00000080 */ +#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00000100 */ +#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00000200 */ +#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00000400 */ +#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00000800 */ +#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00001000 */ +#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00002000 */ +#define USB_OTG_HCSPLT_XACTPOS_SHIFT (14U) +#define USB_OTG_HCSPLT_XACTPOS_MASK (0x3U << USB_OTG_HCSPLT_XACTPOS_SHIFT) /* 0x0000C000 */ +#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_MASK /* XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_SHIFT) /* 0x00004000 */ +#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_SHIFT) /* 0x00008000 */ +#define USB_OTG_HCSPLT_COMPLSPLT_SHIFT (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_MASK (0x1U << USB_OTG_HCSPLT_COMPLSPLT_SHIFT) /* 0x00010000 */ +#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_MASK /* Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN_SHIFT (31U) +#define USB_OTG_HCSPLT_SPLITEN_MASK (0x1U << USB_OTG_HCSPLT_SPLITEN_SHIFT) /* 0x80000000 */ +#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_MASK /* Split enable */ +/******************** Bit definition for USB_OTG_HCINT register ********************/ +#define USB_OTG_HCINT_XFRC_SHIFT (0U) +#define USB_OTG_HCINT_XFRC_MASK (0x1U << USB_OTG_HCINT_XFRC_SHIFT) /* 0x00000001 */ +#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_MASK /* Transfer completed */ +#define USB_OTG_HCINT_CHH_SHIFT (1U) +#define USB_OTG_HCINT_CHH_MASK (0x1U << USB_OTG_HCINT_CHH_SHIFT) /* 0x00000002 */ +#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_MASK /* Channel halted */ +#define USB_OTG_HCINT_AHBERR_SHIFT (2U) +#define USB_OTG_HCINT_AHBERR_MASK (0x1U << USB_OTG_HCINT_AHBERR_SHIFT) /* 0x00000004 */ +#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_MASK /* AHB error */ +#define USB_OTG_HCINT_STALL_SHIFT (3U) +#define USB_OTG_HCINT_STALL_MASK (0x1U << USB_OTG_HCINT_STALL_SHIFT) /* 0x00000008 */ +#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_MASK /* STALL response received interrupt */ +#define USB_OTG_HCINT_NAK_SHIFT (4U) +#define USB_OTG_HCINT_NAK_MASK (0x1U << USB_OTG_HCINT_NAK_SHIFT) /* 0x00000010 */ +#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_MASK /* NAK response received interrupt */ +#define USB_OTG_HCINT_ACK_SHIFT (5U) +#define USB_OTG_HCINT_ACK_MASK (0x1U << USB_OTG_HCINT_ACK_SHIFT) /* 0x00000020 */ +#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_MASK /* ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET_SHIFT (6U) +#define USB_OTG_HCINT_NYET_MASK (0x1U << USB_OTG_HCINT_NYET_SHIFT) /* 0x00000040 */ +#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_MASK /* Response received interrupt */ +#define USB_OTG_HCINT_TXERR_SHIFT (7U) +#define USB_OTG_HCINT_TXERR_MASK (0x1U << USB_OTG_HCINT_TXERR_SHIFT) /* 0x00000080 */ +#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_MASK /* Transaction error */ +#define USB_OTG_HCINT_BBERR_SHIFT (8U) +#define USB_OTG_HCINT_BBERR_MASK (0x1U << USB_OTG_HCINT_BBERR_SHIFT) /* 0x00000100 */ +#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_MASK /* Babble error */ +#define USB_OTG_HCINT_FRMOR_SHIFT (9U) +#define USB_OTG_HCINT_FRMOR_MASK (0x1U << USB_OTG_HCINT_FRMOR_SHIFT) /* 0x00000200 */ +#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_MASK /* Frame overrun */ +#define USB_OTG_HCINT_DTERR_SHIFT (10U) +#define USB_OTG_HCINT_DTERR_MASK (0x1U << USB_OTG_HCINT_DTERR_SHIFT) /* 0x00000400 */ +#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_MASK /* Data toggle error */ +/******************** Bit definition for USB_OTG_HCINTMSK register ********************/ +#define USB_OTG_HCINTMSK_XFRCM_SHIFT (0U) +#define USB_OTG_HCINTMSK_XFRCM_MASK (0x1U << USB_OTG_HCINTMSK_XFRCM_SHIFT) /* 0x00000001 */ +#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_MASK /* Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM_SHIFT (1U) +#define USB_OTG_HCINTMSK_CHHM_MASK (0x1U << USB_OTG_HCINTMSK_CHHM_SHIFT) /* 0x00000002 */ +#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_MASK /* Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR_SHIFT (2U) +#define USB_OTG_HCINTMSK_AHBERR_MASK (0x1U << USB_OTG_HCINTMSK_AHBERR_SHIFT) /* 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_MASK /* AHB error */ +#define USB_OTG_HCINTMSK_STALLM_SHIFT (3U) +#define USB_OTG_HCINTMSK_STALLM_MASK (0x1U << USB_OTG_HCINTMSK_STALLM_SHIFT) /* 0x00000008 */ +#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_MASK /* STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM_SHIFT (4U) +#define USB_OTG_HCINTMSK_NAKM_MASK (0x1U << USB_OTG_HCINTMSK_NAKM_SHIFT) /* 0x00000010 */ +#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_MASK /* NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM_SHIFT (5U) +#define USB_OTG_HCINTMSK_ACKM_MASK (0x1U << USB_OTG_HCINTMSK_ACKM_SHIFT) /* 0x00000020 */ +#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_MASK /* ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET_SHIFT (6U) +#define USB_OTG_HCINTMSK_NYET_MASK (0x1U << USB_OTG_HCINTMSK_NYET_SHIFT) /* 0x00000040 */ +#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_MASK /* response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM_SHIFT (7U) +#define USB_OTG_HCINTMSK_TXERRM_MASK (0x1U << USB_OTG_HCINTMSK_TXERRM_SHIFT) /* 0x00000080 */ +#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_MASK /* Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM_SHIFT (8U) +#define USB_OTG_HCINTMSK_BBERRM_MASK (0x1U << USB_OTG_HCINTMSK_BBERRM_SHIFT) /* 0x00000100 */ +#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_MASK /* Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM_SHIFT (9U) +#define USB_OTG_HCINTMSK_FRMORM_MASK (0x1U << USB_OTG_HCINTMSK_FRMORM_SHIFT) /* 0x00000200 */ +#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_MASK /* Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM_SHIFT (10U) +#define USB_OTG_HCINTMSK_DTERRM_MASK (0x1U << USB_OTG_HCINTMSK_DTERRM_SHIFT) /* 0x00000400 */ +#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_MASK /* Data toggle error mask */ +/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ +#define USB_OTG_HCTSIZ_XFRSIZ_SHIFT (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_MASK (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_SHIFT) /* 0x0007FFFF */ +#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_MASK /* Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT_SHIFT (19U) +#define USB_OTG_HCTSIZ_PKTCNT_MASK (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_SHIFT) /* 0x1FF80000 */ +#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_MASK /* Packet count */ +#define USB_OTG_HCTSIZ_DOPING_SHIFT (31U) +#define USB_OTG_HCTSIZ_DOPING_MASK (0x1U << USB_OTG_HCTSIZ_DOPING_SHIFT) /* 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_MASK /* Do PING */ +#define USB_OTG_HCTSIZ_DPID_SHIFT (29U) +#define USB_OTG_HCTSIZ_DPID_MASK (0x3U << USB_OTG_HCTSIZ_DPID_SHIFT) /* 0x60000000 */ +#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_MASK /* Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_SHIFT) /* 0x20000000 */ +#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_SHIFT) /* 0x40000000 */ +/******************** Bit definition for USB_OTG_HCDMA register ********************/ +#define USB_OTG_HCDMA_DMAADDR_SHIFT (0U) +#define USB_OTG_HCDMA_DMAADDR_MASK (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_SHIFT) /* 0xFFFFFFFF */ +#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_MASK /* DMA address */ +/******************** Bit definition for USB_OTG_DCFG register ********************/ +#define USB_OTG_DCFG_DSPD_SHIFT (0U) +#define USB_OTG_DCFG_DSPD_MASK (0x3U << USB_OTG_DCFG_DSPD_SHIFT) /* 0x00000003 */ +#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_MASK /* Device speed */ +#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_SHIFT) /* 0x00000001 */ +#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_SHIFT) /* 0x00000002 */ +#define USB_OTG_DCFG_NZLSOHSK_SHIFT (2U) +#define USB_OTG_DCFG_NZLSOHSK_MASK (0x1U << USB_OTG_DCFG_NZLSOHSK_SHIFT) /* 0x00000004 */ +#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_MASK /* Nonzero-length status OUT handshake */ +#define USB_OTG_DCFG_DAD_SHIFT (4U) +#define USB_OTG_DCFG_DAD_MASK (0x7FU << USB_OTG_DCFG_DAD_SHIFT) /* 0x000007F0 */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_MASK /* Device address */ +#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000010 */ +#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000020 */ +#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000040 */ +#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000080 */ +#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000100 */ +#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000200 */ +#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000400 */ +#define USB_OTG_DCFG_PFIVL_SHIFT (11U) +#define USB_OTG_DCFG_PFIVL_MASK (0x3U << USB_OTG_DCFG_PFIVL_SHIFT) /* 0x00001800 */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_MASK /* Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_SHIFT) /* 0x00000800 */ +#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_SHIFT) /* 0x00001000 */ +#define USB_OTG_DCFG_PERSCHIVL_SHIFT (24U) +#define USB_OTG_DCFG_PERSCHIVL_MASK (0x3U << USB_OTG_DCFG_PERSCHIVL_SHIFT) /* 0x03000000 */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_MASK /* Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_SHIFT) /* 0x01000000 */ +#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_SHIFT) /* 0x02000000 */ +/******************** Bit definition for USB_OTG_DCTL register ********************/ +#define USB_OTG_DCTL_RWUSIG_SHIFT (0U) +#define USB_OTG_DCTL_RWUSIG_MASK (0x1U << USB_OTG_DCTL_RWUSIG_SHIFT) /* 0x00000001 */ +#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_MASK /* Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS_SHIFT (1U) +#define USB_OTG_DCTL_SDIS_MASK (0x1U << USB_OTG_DCTL_SDIS_SHIFT) /* 0x00000002 */ +#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_MASK /* Soft disconnect */ +#define USB_OTG_DCTL_GINSTS_SHIFT (2U) +#define USB_OTG_DCTL_GINSTS_MASK (0x1U << USB_OTG_DCTL_GINSTS_SHIFT) /* 0x00000004 */ +#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_MASK /* Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS_SHIFT (3U) +#define USB_OTG_DCTL_GONSTS_MASK (0x1U << USB_OTG_DCTL_GONSTS_SHIFT) /* 0x00000008 */ +#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_MASK /* Global OUT NAK status */ +#define USB_OTG_DCTL_TCTL_SHIFT (4U) +#define USB_OTG_DCTL_TCTL_MASK (0x7U << USB_OTG_DCTL_TCTL_SHIFT) /* 0x00000070 */ +#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_MASK /* Test control */ +#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_SHIFT) /* 0x00000010 */ +#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_SHIFT) /* 0x00000020 */ +#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_SHIFT) /* 0x00000040 */ +#define USB_OTG_DCTL_SGINAK_SHIFT (7U) +#define USB_OTG_DCTL_SGINAK_MASK (0x1U << USB_OTG_DCTL_SGINAK_SHIFT) /* 0x00000080 */ +#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_MASK /* Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK_SHIFT (8U) +#define USB_OTG_DCTL_CGINAK_MASK (0x1U << USB_OTG_DCTL_CGINAK_SHIFT) /* 0x00000100 */ +#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_MASK /* Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK_SHIFT (9U) +#define USB_OTG_DCTL_SGONAK_MASK (0x1U << USB_OTG_DCTL_SGONAK_SHIFT) /* 0x00000200 */ +#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_MASK /* Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK_SHIFT (10U) +#define USB_OTG_DCTL_CGONAK_MASK (0x1U << USB_OTG_DCTL_CGONAK_SHIFT) /* 0x00000400 */ +#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_MASK /* Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE_SHIFT (11U) +#define USB_OTG_DCTL_POPRGDNE_MASK (0x1U << USB_OTG_DCTL_POPRGDNE_SHIFT) /* 0x00000800 */ +#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_MASK /* Power-on programming done */ +/******************** Bit definition for USB_OTG_DSTS register ********************/ +#define USB_OTG_DSTS_SUSPSTS_SHIFT (0U) +#define USB_OTG_DSTS_SUSPSTS_MASK (0x1U << USB_OTG_DSTS_SUSPSTS_SHIFT) /* 0x00000001 */ +#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_MASK /* Suspend status */ +#define USB_OTG_DSTS_ENUMSPD_SHIFT (1U) +#define USB_OTG_DSTS_ENUMSPD_MASK (0x3U << USB_OTG_DSTS_ENUMSPD_SHIFT) /* 0x00000006 */ +#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_MASK /* Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_SHIFT) /* 0x00000002 */ +#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_SHIFT) /* 0x00000004 */ +#define USB_OTG_DSTS_EERR_SHIFT (3U) +#define USB_OTG_DSTS_EERR_MASK (0x1U << USB_OTG_DSTS_EERR_SHIFT) /* 0x00000008 */ +#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_MASK /* Erratic error */ +#define USB_OTG_DSTS_FNSOF_SHIFT (8U) +#define USB_OTG_DSTS_FNSOF_MASK (0x3FFFU << USB_OTG_DSTS_FNSOF_SHIFT) /* 0x003FFF00 */ +#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_MASK /* Frame number of the received SOF */ +/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ +#define USB_OTG_DIEPMSK_XFRCM_SHIFT (0U) +#define USB_OTG_DIEPMSK_XFRCM_MASK (0x1U << USB_OTG_DIEPMSK_XFRCM_SHIFT) /* 0x00000001 */ +#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_MASK /* Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM_SHIFT (1U) +#define USB_OTG_DIEPMSK_EPDM_MASK (0x1U << USB_OTG_DIEPMSK_EPDM_SHIFT) /* 0x00000002 */ +#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_MASK /* Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM_SHIFT (3U) +#define USB_OTG_DIEPMSK_TOM_MASK (0x1U << USB_OTG_DIEPMSK_TOM_SHIFT) /* 0x00000008 */ +#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_MASK /* Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK_SHIFT (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_MASK (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_SHIFT) /* 0x00000010 */ +#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_MASK /* IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM_SHIFT (5U) +#define USB_OTG_DIEPMSK_INEPNMM_MASK (0x1U << USB_OTG_DIEPMSK_INEPNMM_SHIFT) /* 0x00000020 */ +#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_MASK /* IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM_SHIFT (6U) +#define USB_OTG_DIEPMSK_INEPNEM_MASK (0x1U << USB_OTG_DIEPMSK_INEPNEM_SHIFT) /* 0x00000040 */ +#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_MASK /* IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM_SHIFT (8U) +#define USB_OTG_DIEPMSK_TXFURM_MASK (0x1U << USB_OTG_DIEPMSK_TXFURM_SHIFT) /* 0x00000100 */ +#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_MASK /* FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM_SHIFT (9U) +#define USB_OTG_DIEPMSK_BIM_MASK (0x1U << USB_OTG_DIEPMSK_BIM_SHIFT) /* 0x00000200 */ +#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_MASK /* BNA interrupt mask */ +/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ +#define USB_OTG_DOEPMSK_XFRCM_SHIFT (0U) +#define USB_OTG_DOEPMSK_XFRCM_MASK (0x1U << USB_OTG_DOEPMSK_XFRCM_SHIFT) /* 0x00000001 */ +#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_MASK /* Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM_SHIFT (1U) +#define USB_OTG_DOEPMSK_EPDM_MASK (0x1U << USB_OTG_DOEPMSK_EPDM_SHIFT) /* 0x00000002 */ +#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_MASK /* Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM_SHIFT (3U) +#define USB_OTG_DOEPMSK_STUPM_MASK (0x1U << USB_OTG_DOEPMSK_STUPM_SHIFT) /* 0x00000008 */ +#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_MASK /* SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM_SHIFT (4U) +#define USB_OTG_DOEPMSK_OTEPDM_MASK (0x1U << USB_OTG_DOEPMSK_OTEPDM_SHIFT) /* 0x00000010 */ +#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_MASK /* OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_OTEPSPRM_SHIFT (5U) +#define USB_OTG_DOEPMSK_OTEPSPRM_MASK (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_SHIFT) /* 0x00000020 */ +#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_MASK /* Status Phase Received mask */ +#define USB_OTG_DOEPMSK_B2BSTUP_SHIFT (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_MASK (0x1U << USB_OTG_DOEPMSK_B2BSTUP_SHIFT) /* 0x00000040 */ +#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_MASK /* Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM_SHIFT (8U) +#define USB_OTG_DOEPMSK_OPEM_MASK (0x1U << USB_OTG_DOEPMSK_OPEM_SHIFT) /* 0x00000100 */ +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_MASK /* OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM_SHIFT (9U) +#define USB_OTG_DOEPMSK_BOIM_MASK (0x1U << USB_OTG_DOEPMSK_BOIM_SHIFT) /* 0x00000200 */ +#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_MASK /* BNA interrupt mask */ +/******************** Bit definition for USB_OTG_DAINT register ********************/ +#define USB_OTG_DAINT_IEPINT_SHIFT (0U) +#define USB_OTG_DAINT_IEPINT_MASK (0xFFFFU << USB_OTG_DAINT_IEPINT_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_MASK /* IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT_SHIFT (16U) +#define USB_OTG_DAINT_OEPINT_MASK (0xFFFFU << USB_OTG_DAINT_OEPINT_SHIFT) /* 0xFFFF0000 */ +#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_MASK /* OUT endpoint interrupt bits */ +/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ +#define USB_OTG_DAINTMSK_IEPM_SHIFT (0U) +#define USB_OTG_DAINTMSK_IEPM_MASK (0xFFFFU << USB_OTG_DAINTMSK_IEPM_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_MASK /* IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM_SHIFT (16U) +#define USB_OTG_DAINTMSK_OEPM_MASK (0xFFFFU << USB_OTG_DAINTMSK_OEPM_SHIFT) /* 0xFFFF0000 */ +#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_MASK /* OUT EP interrupt mask bits */ +/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ +#define USB_OTG_DTHRCTL_NONISOTHREN_SHIFT (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_MASK (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_SHIFT) /* 0x00000001 */ +#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_MASK /* Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN_SHIFT (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_MASK (0x1U << USB_OTG_DTHRCTL_ISOTHREN_SHIFT) /* 0x00000002 */ +#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_MASK /* ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN_SHIFT (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_MASK (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x000007FC */ +#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_MASK /* Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000004 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000008 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000010 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000020 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000040 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000080 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000100 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000200 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000400 */ +#define USB_OTG_DTHRCTL_RXTHREN_SHIFT (16U) +#define USB_OTG_DTHRCTL_RXTHREN_MASK (0x1U << USB_OTG_DTHRCTL_RXTHREN_SHIFT) /* 0x00010000 */ +#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_MASK /* Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN_SHIFT (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_MASK (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x03FE0000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_MASK /* Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00020000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00040000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00080000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00100000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00200000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00400000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00800000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x01000000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x02000000 */ +#define USB_OTG_DTHRCTL_ARPEN_SHIFT (27U) +#define USB_OTG_DTHRCTL_ARPEN_MASK (0x1U << USB_OTG_DTHRCTL_ARPEN_SHIFT) /* 0x08000000 */ +#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_MASK /* Arbiter parking enable */ +/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_SHIFT (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_MASK (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_MASK /* IN EP Tx FIFO empty interrupt mask bits */ +/******************** Bit definition for USB_OTG_DEACHINT register ********************/ +#define USB_OTG_DEACHINT_IEP1INT_SHIFT (1U) +#define USB_OTG_DEACHINT_IEP1INT_MASK (0x1U << USB_OTG_DEACHINT_IEP1INT_SHIFT) /* 0x00000002 */ +#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_MASK /* IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT_SHIFT (17U) +#define USB_OTG_DEACHINT_OEP1INT_MASK (0x1U << USB_OTG_DEACHINT_OEP1INT_SHIFT) /* 0x00020000 */ +#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_MASK /* OUT endpoint 1 interrupt bit */ +/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ +#define USB_OTG_DEACHINTMSK_IEP1INTM_SHIFT (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_MASK (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_SHIFT) /* 0x00000002 */ +#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_MASK /* IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM_SHIFT (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_MASK (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_SHIFT) /* 0x00020000 */ +#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_MASK /* OUT Endpoint 1 interrupt mask bit */ +/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ +#define USB_OTG_DIEPEACHMSK1_XFRCM_SHIFT (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_SHIFT) /* 0x00000001 */ +#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_MASK /* Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM_SHIFT (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_SHIFT) /* 0x00000002 */ +#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_MASK /* Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM_SHIFT (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_TOM_SHIFT) /* 0x00000008 */ +#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_MASK /* Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_SHIFT (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_MASK (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_SHIFT) /* 0x00000010 */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_MASK /* IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM_SHIFT (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_SHIFT) /* 0x00000020 */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_MASK /* IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM_SHIFT (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_SHIFT) /* 0x00000040 */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_MASK /* IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM_SHIFT (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_SHIFT) /* 0x00000100 */ +#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_MASK /* FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM_SHIFT (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_BIM_SHIFT) /* 0x00000200 */ +#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_MASK /* BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM_SHIFT (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_SHIFT) /* 0x00002000 */ +#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_MASK /* NAK interrupt mask */ +/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ +#define USB_OTG_DOEPEACHMSK1_XFRCM_SHIFT (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_SHIFT) /* 0x00000001 */ +#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_MASK /* Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM_SHIFT (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_SHIFT) /* 0x00000002 */ +#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_MASK /* Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM_SHIFT (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_TOM_SHIFT) /* 0x00000008 */ +#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_MASK /* Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_SHIFT (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_MASK (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_SHIFT) /* 0x00000010 */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_MASK /* IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM_SHIFT (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_SHIFT) /* 0x00000020 */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_MASK /* IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM_SHIFT (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_SHIFT) /* 0x00000040 */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_MASK /* IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM_SHIFT (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_SHIFT) /* 0x00000100 */ +#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_MASK /* OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM_SHIFT (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_BIM_SHIFT) /* 0x00000200 */ +#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_MASK /* BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM_SHIFT (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_SHIFT) /* 0x00001000 */ +#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_MASK /* Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM_SHIFT (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_SHIFT) /* 0x00002000 */ +#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_MASK /* NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM_SHIFT (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_SHIFT) /* 0x00004000 */ +#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_MASK /* NYET interrupt mask */ +/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ +#define USB_OTG_DIEPCTL_MPSIZ_SHIFT (0U) +#define USB_OTG_DIEPCTL_MPSIZ_MASK (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_SHIFT) /* 0x000007FF */ +#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_MASK /* Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP_SHIFT (15U) +#define USB_OTG_DIEPCTL_USBAEP_MASK (0x1U << USB_OTG_DIEPCTL_USBAEP_SHIFT) /* 0x00008000 */ +#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_MASK /* USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID_SHIFT (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_MASK (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_SHIFT) /* 0x00010000 */ +#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_MASK /* Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS_SHIFT (17U) +#define USB_OTG_DIEPCTL_NAKSTS_MASK (0x1U << USB_OTG_DIEPCTL_NAKSTS_SHIFT) /* 0x00020000 */ +#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_MASK /* NAK status */ +#define USB_OTG_DIEPCTL_EPTYP_SHIFT (18U) +#define USB_OTG_DIEPCTL_EPTYP_MASK (0x3U << USB_OTG_DIEPCTL_EPTYP_SHIFT) /* 0x000C0000 */ +#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_MASK /* Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_SHIFT) /* 0x00040000 */ +#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_SHIFT) /* 0x00080000 */ +#define USB_OTG_DIEPCTL_STALL_SHIFT (21U) +#define USB_OTG_DIEPCTL_STALL_MASK (0x1U << USB_OTG_DIEPCTL_STALL_SHIFT) /* 0x00200000 */ +#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_MASK /* STALL handshake */ +#define USB_OTG_DIEPCTL_TXFNUM_SHIFT (22U) +#define USB_OTG_DIEPCTL_TXFNUM_MASK (0xFU << USB_OTG_DIEPCTL_TXFNUM_SHIFT) /* 0x03C00000 */ +#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_MASK /* TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_SHIFT) /* 0x00400000 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_SHIFT) /* 0x00800000 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_SHIFT) /* 0x01000000 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_SHIFT) /* 0x02000000 */ +#define USB_OTG_DIEPCTL_CNAK_SHIFT (26U) +#define USB_OTG_DIEPCTL_CNAK_MASK (0x1U << USB_OTG_DIEPCTL_CNAK_SHIFT) /* 0x04000000 */ +#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_MASK /* Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK_SHIFT (27U) +#define USB_OTG_DIEPCTL_SNAK_MASK (0x1U << USB_OTG_DIEPCTL_SNAK_SHIFT) /* 0x08000000 */ +#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_MASK /* Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_SHIFT (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_MASK (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_SHIFT) /* 0x10000000 */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_MASK /* Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM_SHIFT (29U) +#define USB_OTG_DIEPCTL_SODDFRM_MASK (0x1U << USB_OTG_DIEPCTL_SODDFRM_SHIFT) /* 0x20000000 */ +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_MASK /* Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS_SHIFT (30U) +#define USB_OTG_DIEPCTL_EPDIS_MASK (0x1U << USB_OTG_DIEPCTL_EPDIS_SHIFT) /* 0x40000000 */ +#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_MASK /* Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA_SHIFT (31U) +#define USB_OTG_DIEPCTL_EPENA_MASK (0x1U << USB_OTG_DIEPCTL_EPENA_SHIFT) /* 0x80000000 */ +#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_MASK /* Endpoint enable */ +/******************** Bit definition for USB_OTG_DIEPINT register ********************/ +#define USB_OTG_DIEPINT_XFRC_SHIFT (0U) +#define USB_OTG_DIEPINT_XFRC_MASK (0x1U << USB_OTG_DIEPINT_XFRC_SHIFT) /* 0x00000001 */ +#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_MASK /* Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD_SHIFT (1U) +#define USB_OTG_DIEPINT_EPDISD_MASK (0x1U << USB_OTG_DIEPINT_EPDISD_SHIFT) /* 0x00000002 */ +#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_MASK /* Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_TOC_SHIFT (3U) +#define USB_OTG_DIEPINT_TOC_MASK (0x1U << USB_OTG_DIEPINT_TOC_SHIFT) /* 0x00000008 */ +#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_MASK /* Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE_SHIFT (4U) +#define USB_OTG_DIEPINT_ITTXFE_MASK (0x1U << USB_OTG_DIEPINT_ITTXFE_SHIFT) /* 0x00000010 */ +#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_MASK /* IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNE_SHIFT (6U) +#define USB_OTG_DIEPINT_INEPNE_MASK (0x1U << USB_OTG_DIEPINT_INEPNE_SHIFT) /* 0x00000040 */ +#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_MASK /* IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE_SHIFT (7U) +#define USB_OTG_DIEPINT_TXFE_MASK (0x1U << USB_OTG_DIEPINT_TXFE_SHIFT) /* 0x00000080 */ +#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_MASK /* Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN_SHIFT (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_MASK (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_SHIFT) /* 0x00000100 */ +#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_MASK /* Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA_SHIFT (9U) +#define USB_OTG_DIEPINT_BNA_MASK (0x1U << USB_OTG_DIEPINT_BNA_SHIFT) /* 0x00000200 */ +#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_MASK /* Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS_SHIFT (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_MASK (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_SHIFT) /* 0x00000800 */ +#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_MASK /* Packet dropped status */ +#define USB_OTG_DIEPINT_BERR_SHIFT (12U) +#define USB_OTG_DIEPINT_BERR_MASK (0x1U << USB_OTG_DIEPINT_BERR_SHIFT) /* 0x00001000 */ +#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_MASK /* Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK_SHIFT (13U) +#define USB_OTG_DIEPINT_NAK_MASK (0x1U << USB_OTG_DIEPINT_NAK_SHIFT) /* 0x00002000 */ +#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_MASK /* NAK interrupt */ +/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ +#define USB_OTG_DIEPTSIZ_XFRSIZ_SHIFT (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_SHIFT) /* 0x0007FFFF */ +#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_MASK /* Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT_SHIFT (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_MASK (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_SHIFT) /* 0x1FF80000 */ +#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_MASK /* Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT_SHIFT (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_MASK (0x3U << USB_OTG_DIEPTSIZ_MULCNT_SHIFT) /* 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_MASK /* Packet count */ +/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ +#define USB_OTG_DIEPDMA_DMAADDR_SHIFT (0U) +#define USB_OTG_DIEPDMA_DMAADDR_MASK (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_SHIFT) /* 0xFFFFFFFF */ +#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_MASK /* DMA address */ +/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ +#define USB_OTG_DTXFSTS_INEPTFSAV_SHIFT (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_MASK (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_SHIFT) /* 0x0000FFFF */ +#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_MASK /* IN endpoint TxFIFO space available */ +/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ +#define USB_OTG_DOEPCTL_MPSIZ_SHIFT (0U) +#define USB_OTG_DOEPCTL_MPSIZ_MASK (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_SHIFT) /* 0x000007FF */ +#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_MASK /* Maximum packet size */ +#define USB_OTG_DOEPCTL_USBAEP_SHIFT (15U) +#define USB_OTG_DOEPCTL_USBAEP_MASK (0x1U << USB_OTG_DOEPCTL_USBAEP_SHIFT) /* 0x00008000 */ +#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_MASK /* USB active endpoint */ +#define USB_OTG_DOEPCTL_NAKSTS_SHIFT (17U) +#define USB_OTG_DOEPCTL_NAKSTS_MASK (0x1U << USB_OTG_DOEPCTL_NAKSTS_SHIFT) /* 0x00020000 */ +#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_MASK /* NAK status */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_SHIFT (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_MASK (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_SHIFT) /* 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_MASK /* Set DATA0 PID */ +#define USB_OTG_DOEPCTL_SODDFRM_SHIFT (29U) +#define USB_OTG_DOEPCTL_SODDFRM_MASK (0x1U << USB_OTG_DOEPCTL_SODDFRM_SHIFT) /* 0x20000000 */ +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_MASK /* Set odd frame */ +#define USB_OTG_DOEPCTL_EPTYP_SHIFT (18U) +#define USB_OTG_DOEPCTL_EPTYP_MASK (0x3U << USB_OTG_DOEPCTL_EPTYP_SHIFT) /* 0x000C0000 */ +#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_MASK /* Endpoint type */ +#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_SHIFT) /* 0x00040000 */ +#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_SHIFT) /* 0x00080000 */ +#define USB_OTG_DOEPCTL_SNPM_SHIFT (20U) +#define USB_OTG_DOEPCTL_SNPM_MASK (0x1U << USB_OTG_DOEPCTL_SNPM_SHIFT) /* 0x00100000 */ +#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_MASK /* Snoop mode */ +#define USB_OTG_DOEPCTL_STALL_SHIFT (21U) +#define USB_OTG_DOEPCTL_STALL_MASK (0x1U << USB_OTG_DOEPCTL_STALL_SHIFT) /* 0x00200000 */ +#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_MASK /* STALL handshake */ +#define USB_OTG_DOEPCTL_CNAK_SHIFT (26U) +#define USB_OTG_DOEPCTL_CNAK_MASK (0x1U << USB_OTG_DOEPCTL_CNAK_SHIFT) /* 0x04000000 */ +#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_MASK /* Clear NAK */ +#define USB_OTG_DOEPCTL_SNAK_SHIFT (27U) +#define USB_OTG_DOEPCTL_SNAK_MASK (0x1U << USB_OTG_DOEPCTL_SNAK_SHIFT) /* 0x08000000 */ +#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_MASK /* Set NAK */ +#define USB_OTG_DOEPCTL_EPDIS_SHIFT (30U) +#define USB_OTG_DOEPCTL_EPDIS_MASK (0x1U << USB_OTG_DOEPCTL_EPDIS_SHIFT) /* 0x40000000 */ +#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_MASK /* Endpoint disable */ +#define USB_OTG_DOEPCTL_EPENA_SHIFT (31U) +#define USB_OTG_DOEPCTL_EPENA_MASK (0x1U << USB_OTG_DOEPCTL_EPENA_SHIFT) /* 0x80000000 */ +#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_MASK /* Endpoint enable */ +/******************** Bit definition for USB_OTG_DOEPINT register ********************/ +#define USB_OTG_DOEPINT_XFRC_SHIFT (0U) +#define USB_OTG_DOEPINT_XFRC_MASK (0x1U << USB_OTG_DOEPINT_XFRC_SHIFT) /* 0x00000001 */ +#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_MASK /* Transfer completed interrupt */ +#define USB_OTG_DOEPINT_EPDISD_SHIFT (1U) +#define USB_OTG_DOEPINT_EPDISD_MASK (0x1U << USB_OTG_DOEPINT_EPDISD_SHIFT) /* 0x00000002 */ +#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_MASK /* Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_STUP_SHIFT (3U) +#define USB_OTG_DOEPINT_STUP_MASK (0x1U << USB_OTG_DOEPINT_STUP_SHIFT) /* 0x00000008 */ +#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_MASK /* SETUP phase done */ +#define USB_OTG_DOEPINT_OTEPDIS_SHIFT (4U) +#define USB_OTG_DOEPINT_OTEPDIS_MASK (0x1U << USB_OTG_DOEPINT_OTEPDIS_SHIFT) /* 0x00000010 */ +#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_MASK /* OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_OTEPSPR_SHIFT (5U) +#define USB_OTG_DOEPINT_OTEPSPR_MASK (0x1U << USB_OTG_DOEPINT_OTEPSPR_SHIFT) /* 0x00000020 */ +#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_MASK /* Status Phase Received For Control Write */ +#define USB_OTG_DOEPINT_B2BSTUP_SHIFT (6U) +#define USB_OTG_DOEPINT_B2BSTUP_MASK (0x1U << USB_OTG_DOEPINT_B2BSTUP_SHIFT) /* 0x00000040 */ +#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_MASK /* Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_NYET_SHIFT (14U) +#define USB_OTG_DOEPINT_NYET_MASK (0x1U << USB_OTG_DOEPINT_NYET_SHIFT) /* 0x00004000 */ +#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_MASK /* NYET interrupt */ +#define USB_OTG_DOEPINT_STUPPKTRCVD_SHIFT (15U) +#define USB_OTG_DOEPINT_STUPPKTRCVD_MASK (0x1U << USB_OTG_DOEPINT_STUPPKTRCVD_SHIFT) /* 0x00008000 */ +#define USB_OTG_DOEPINT_STUPPKTRCVD USB_OTG_DOEPINT_STUPPKTRCVD_MASK /* STUPPKTRCVD interrupt */ +/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ +#define USB_OTG_DOEPTSIZ_XFRSIZ_SHIFT (0U) +#define USB_OTG_DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_SHIFT) /* 0x0007FFFF */ +#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_MASK /* Transfer size */ +#define USB_OTG_DOEPTSIZ_PKTCNT_SHIFT (19U) +#define USB_OTG_DOEPTSIZ_PKTCNT_MASK (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_SHIFT) /* 0x1FF80000 */ +#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_MASK /* Packet count */ +#define USB_OTG_DOEPTSIZ_STUPCNT_SHIFT (29U) +#define USB_OTG_DOEPTSIZ_STUPCNT_MASK (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_SHIFT) /* 0x60000000 */ +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_MASK /* SETUP packet count */ +#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_SHIFT) /* 0x20000000 */ +#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_SHIFT) /* 0x40000000 */ +/******************** Bit definition for PCGCCTL register ********************/ +#define USB_OTG_PCGCCTL_STOPCLK_SHIFT (0U) +#define USB_OTG_PCGCCTL_STOPCLK_MASK (0x1U << USB_OTG_PCGCCTL_STOPCLK_SHIFT) /* 0x00000001 */ +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_MASK /* SETUP packet count */ +#define USB_OTG_PCGCCTL_GATECLK_SHIFT (1U) +#define USB_OTG_PCGCCTL_GATECLK_MASK (0x1U << USB_OTG_PCGCCTL_GATECLK_SHIFT) /* 0x00000002 */ +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_MASK /* Gate Hclk */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __RK2108_USB_H */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/soc.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/soc.h new file mode 100644 index 00000000000..ac1e622695f --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/soc.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __SOC_H +#define __SOC_H +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __ASSEMBLY__ +/* ================================================================================ */ +/* ================ DMA REQ =============== */ +/* ================================================================================ */ +typedef enum { + DMA_REQ_UART0_TX = 0, + DMA_REQ_UART0_RX = 1, + DMA_REQ_UART1_TX = 2, + DMA_REQ_UART1_RX = 3, + DMA_REQ_UART2_TX = 4, + DMA_REQ_UART2_RX = 5, + DMA_REQ_I2S0_TX = 6, + DMA_REQ_I2S0_RX = 7, + DMA_REQ_I2S1_TX = 8, + DMA_REQ_I2S1_RX = 9, + DMA_REQ_PDM0 = 10, + DMA_REQ_SPI1_TX = 11, + DMA_REQ_SPI1_RX = 12, + DMA_REQ_SPI2_TX = 13, + DMA_REQ_SPI2_RX = 14, + DMA_REQ_PWM = 15, + DMA_REQ_AUDIOPWM = 16, +} DMA_REQ_Type; + +/* ================================================================================ */ +/* ================ IRQ ================ */ +/* ================================================================================ */ +typedef enum +{ + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + /****** RK2108 specific Interrupt Numbers **********************************************************************/ + CACHE_IRQn = 0, /* cortex m4 cache */ + MAILBOX0_AP_IRQn = 2, /* Mailbox0 ap */ + MAILBOX0_BB_IRQn = 3, /* Mailbox0 bb */ + MAILBOX1_AP_IRQn = 4, /* Mailbox1 ap */ + MAILBOX1_BB_IRQn = 5, /* Mailbox1 bb */ + MAILBOX2_AP_IRQn = 6, /* Mailbox2 ap */ + MAILBOX2_BB_IRQn = 7, /* Mailbox2 bb */ + PMU_IRQn = 8, /* PMU */ + DMAC_IRQn = 9, /* DMAC */ + DMAC_ABORT_IRQn = 10, /* DMA Abort */ + UART0_IRQn = 11, /* UART 0 */ + UART1_IRQn = 12, /* UART 1 */ + UART2_IRQn = 13, /* UART 2 */ + TIMER0_IRQn = 14, /* Timer 0 */ + TIMER1_IRQn = 15, /* Timer 1 */ + TIMER2_IRQn = 16, /* Timer 2 */ + TIMER3_IRQn = 17, /* Timer 3 */ + TIMER4_IRQn = 18, /* Timer 4 */ + TIMER5_IRQn = 19, /* Timer 5 */ + WDT0_IRQn = 20, /* Watch dog 0 */ + WDT1_IRQn = 21, /* Watch dog 1 */ + I2CMST0_IRQn = 22, /* I2C Master 0 */ + I2CMST1_IRQn = 23, /* I2C Master 1 */ + I2CMST2_IRQn = 24, /* I2C Master 2 */ + SPISLV0_IRQn = 25, /* SPI Slave 0 */ + SPIMST1_IRQn = 26, /* SPI Master 1 */ + FSPI0_IRQn = 27, /* FSPI0 */ + SDIO_IRQn = 28, /* SDIO */ + GPIO0_IRQn = 29, /* GPIO 0 */ + GPIO1_IRQn = 30, /* GPIO 1 */ + USB_IRQn = 31, /* USB */ + I2S0_IRQn = 32, /* I2S 0 */ + PDM0_IRQn = 33, /* PDM 0 */ + I2S1_IRQn = 34, /* I2S 1 */ + VAD_IRQn = 35, /* VAD */ + VOP_IRQn = 36, /* VOP */ + VOP_POST_LB_IRQn = 37, /* VOP post lb */ + MIPI_DSI_HOST_IRQn = 38, /* MIPI dsi host */ + TP_IRQn = 39, /* TP */ + DSP_PFATAL_ERROR_IRQn = 40, /* DSP pfatal error */ + PWM_IRQn = 41, /* PWM */ + PWM_PWR_IRQn = 42, /* PWM PWR */ + AUDIOPWM_IRQn = 43, /* AUDIOPWM */ + VICAP_IRQn = 44, /* VICAP */ + SPIMST2_IRQn = 45, /* SPI Master 2 */ + KEY_CTRL_IRQn = 46, /* KEY Control */ + FSPI1_IRQn = 47, /* FSPI1 */ + NUM_INTERRUPTS +} IRQn_Type; +#endif /* __ASSEMBLY__ */ + +#define NVIC_PERIPH_IRQ_NUM MAX_IRQn +#define NVIC_PERIPH_IRQ_OFFSET 16 + +#define MAILBOX0_AP_IRQ0 MAILBOX0_AP_IRQn +#define MAILBOX0_AP_IRQ1 MAILBOX0_AP_IRQn +#define MAILBOX0_AP_IRQ2 MAILBOX0_AP_IRQn +#define MAILBOX0_AP_IRQ3 MAILBOX0_AP_IRQn + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +#define __CM4_REV 0x0001U /* Core revision r0p1 */ +#define __MPU_PRESENT 1U /* RK2108 provides an MPU */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 3U /* RK2108 uses 3 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ + +#ifndef __ASSEMBLY__ +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_rk2108.h" +#endif /* __ASSEMBLY__ */ +#include "rk2108.h" +#include "rk2108_usb.h" + +/****************************************************************************************/ +/* */ +/* Module Structure Section */ +/* */ +/****************************************************************************************/ + +/****************************************************************************************/ +/* */ +/* Module Address Section */ +/* */ +/****************************************************************************************/ +/* Memory Base */ +#define XIP_MAP0_BASE0 0x18000000U /* FSPI0 map address0 */ +#define XIP_MAP1_BASE0 0x1C000000U /* FSPI1 map address0 */ +#define DSP_ITCM_BASE 0x30000000U /* DSP itcm base address */ +#define DSP_ITCM_END 0x3000ffffU /* DSP itcm end address */ +#define DSP_DTCM_BASE 0x30200000U /* DSP dtcm base address */ +#define DSP_DTCM_END 0x3027ffffU /* DSP dtcm end address */ +#define USB_M31PHY_BASE 0x400B0340U /* USB M31 PHY base address */ +#define SDIO_BASE MMC_BASE /* 0x40C90000U MMC base address */ +#define USB_BASE 0x41300000U /* USB base address */ +#define XIP_MAP0_BASE1 0x60000000U /* FSPI0 map address1 */ +#define XIP_MAP1_BASE1 0x64000000U /* FSPI1 map address1 */ +#define USB_PHY_CON_BASE (GRF->USBPHY_CON0) /* USB PHY control base address */ +#define USB_PHY_STATUS_BASE (GRF->USBPHY_STATUS0) /* USB PHY status base address */ +/****************************************************************************************/ +/* */ +/* Module Variable Section */ +/* */ +/****************************************************************************************/ +/* Module Variable Define */ +#define USB ((struct USB_GLOBAL_REG *) USB_BASE) + +#define IS_PCD_INSTANCE(instance) ((instance) == USB) +#define IS_HCD_INSTANCE(instance) ((instance) == USB) +/****************************************************************************************/ +/* */ +/* Register Bitmap Section */ +/* */ +/****************************************************************************************/ +/*****************************************ICACHE*****************************************/ +/* CACHE LINE SIZE */ +#define CACHE_LINE_SHIFT (5U) +#define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT) +#define CACHE_LINE_ADDR_MASK (0xFFFFFFFFU << CACHE_LINE_SHIFT) +#define CACHE_M_CLEAN 0x0U +#define CACHE_M_INVALID 0x2U +#define CACHE_M_CLEAN_INVALID 0x4U +#define CACHE_M_INVALID_ALL 0x6U + +/* ICACHE ADDR TO DCACHE ADDR */ +#define SRAM_IADDR_START (0x04000000U) +#define SRAM_SIZE (0x00100000U) +#define SRAM_IADDR_TO_DADDR_OFFSET (0x1c000000U) +#define XIP_NOR_IADDR_START (0x18000000U) +#define XIP_NOR_SIZE (0x04000000U) +#define XIP_NOR_IADDR_TO_DADDR_OFFSET (0x48000000U) +#define XIP_PSRAM_IADDR_START (0x1C000000U) +#define XIP_PSRAM_SIZE (0x04000000U) +#define XIP_PSRAM_IADDR_TO_DADDR_OFFSET (0x48000000U) + +#define CACHE_REVISION (0x00000100U) +/*****************************************PMU*****************************************/ +#ifndef __ASSEMBLY__ +typedef enum PD_Id { + PD_DSP = 0x80000000U, + PD_LOGIC = 0x80011111U, + PD_SHRM = 0x80022222U, + PD_AUDIO = 0x80033333U, +} ePD_Id; +#endif +/****************************************FSPI********************************************/ +#define FSPI_CHIP_CNT (2) +/****************************************MMC*********************************************/ +#define CLK_SDIO_PLL CLK_SDIO_SRC +/****************************************WDT*********************************************/ +#define PCLK_WDT PCLK_LOGIC +/****************************************CRU*********************************************/ +#define CPU_CLK_ID HCLK_M4 +#define MEM_CLK_ID SCLK_SHRM +#define DSP_CLK_ID ACLK_DSP +/****************************************MBOX********************************************/ +#define MBOX_CNT 2 +#define MBOX_CHAN_CNT 4 +/****************************************USB********************************************/ +#define USB_PHY_SUSPEND_MASK \ + (GRF_USBPHY_CON0_UTMI_SEL_MASK | GRF_USBPHY_CON0_UTMI_SUSPEND_N_MASK | \ + GRF_USBPHY_CON0_UTMI_OPMODE_MASK | GRF_USBPHY_CON0_UTMI_XCVRSELECT_MASK | \ + GRF_USBPHY_CON0_UTMI_TERMSELECT_MASK | GRF_USBPHY_CON0_UTMI_DPPULLDOWN_MASK |\ + GRF_USBPHY_CON0_UTMI_DMPULLDOWN_MASK) +#define USB_PHY_RESUME_MASK GRF_USBPHY_CON0_UTMI_SEL_MASK +#define USB_PHY_CON_SHIFT GRF_USBPHY_CON0_UTMI_SEL_SHIFT +#define USB_PHY_LINESTATE_MASK GRF_USBPHY_STATUS0_UTMI_LINESTATE_MASK +#define USB_PHY_LINESTATE_SHIFT GRF_USBPHY_STATUS0_UTMI_LINESTATE_SHIFT +#define USB_PHY_SUSPEND_VAL 0x1d1U +#define USB_PHY_RESUME_VAL 0 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __SOC_H */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/system_rk2108.h b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/system_rk2108.h new file mode 100644 index 00000000000..458957bd501 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/system_rk2108.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __SYSTEM_RK2108_H_ +#define __SYSTEM_RK2108_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; + +/** + \brief Setup the Cache. + + Initialize the Cache in the CPU. + */ +extern void CacheInit(void); + +/** + \brief Setup the system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + \brief Update SystemCoreClock variable. + + Updates the System Clock Frequency (Core Clock). + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_RK2108_H */ diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Source/GCC/gcc_arm.ld b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Source/GCC/gcc_arm.ld new file mode 100644 index 00000000000..2945015cc57 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Source/GCC/gcc_arm.ld @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2019-2021 Rockchip Electronics Co., Ltd. + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x18000000, LENGTH = 16M /* Nor Flash */ + SRAM_I (rx) : ORIGIN = 0x04000000, LENGTH = 1M /* SRAM */ + SRAM_D (rxw) : ORIGIN = 0x20000000, LENGTH = 1M /* SRAM */ +} + +MAIN_STACK_SIZE = 0x400; + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + . = ALIGN(32); + KEEP(*(.vectors)) + . = ALIGN(32); + + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > SRAM_I + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > SRAM_I + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > SRAM_I + + .ctors : + { + . = ALIGN(32); + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + . = ALIGN(32); + PROVIDE(__ctors_end__ = .); + } > SRAM_I + + .dtors : + { + . = ALIGN(32); + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(32); + PROVIDE(__dtors_end__ = .); + } > SRAM_I + + .copy.table : + { + . = ALIGN(32); + PROVIDE(__copy_table_start__ = .); + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + PROVIDE(__copy_table_end__ = .); + } > SRAM_I + + .zero.table : + { + . = ALIGN(32); + PROVIDE(__zero_table_start__ = .); + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__) / 4) + PROVIDE(__zero_table_end__ = .); + } > SRAM_I + +/** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned. In addition, 32byte cacheline alignment + * is required here, because of RK2108 with cache. + */ + __etext = ALIGN (32); + + SRAM_DATA_DEST = ORIGIN(SRAM_D) + __etext - ORIGIN(SRAM_I); + + .data SRAM_DATA_DEST : AT (__etext) + { + __data_start__ = ALIGN (32); + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + _gp = ABSOLUTE(.); /* Base of small data */ + + . = ALIGN(32); + /* All data end */ + __data_end__ = .; + } > SRAM_D + + .bss : + { + . = ALIGN(32); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + . = ALIGN(32); + __bss_end__ = .; + } > SRAM_D + + .stack : + { + . = ALIGN(32); + __StackLimit = .; + . = . + MAIN_STACK_SIZE; + . = ALIGN(32); + __StackTop = .; + __stack = __StackTop; + } > SRAM_D + + .heap : + { + . = ALIGN(32); + __end__ = .; + PROVIDE(end = .); + . = ORIGIN(SRAM_D) + LENGTH(SRAM_D); + __HeapLimit = .; + } > SRAM_D +} diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Source/startup_rk2108.c b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Source/startup_rk2108.c new file mode 100644 index 00000000000..e18603f534c --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Source/startup_rk2108.c @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2019-2021 Rockchip Electronics Co., Ltd. + */ +#include "soc.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector Table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[80]; + const VECTOR_TABLE_Type __VECTOR_TABLE[80] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Source/system_rk2108.c b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Source/system_rk2108.c new file mode 100644 index 00000000000..f1b2f560046 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Source/system_rk2108.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2019-2021 Rockchip Electronics Co., Ltd. + */ + +#include "soc.h" +#include "hal_base.h" +#include "hal_def.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define SYSTEM_CLOCK (24000000U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[80]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +void CacheInit(void) +{ +#if defined(HAL_ICACHE_MODULE_ENABLED) || defined(HAL_DCACHE_MODULE_ENABLED) + uint32_t status; +#endif + +#if defined(HAL_ICACHE_MODULE_ENABLED) + /* config icache: mpu disable, stb disable, write through, hot buffer enable */ + ICACHE->CACHE_CTRL |= (ICACHE_CACHE_CTRL_CACHE_EN_MASK | ICACHE_CACHE_CTRL_CACHE_WT_EN_MASK | + ICACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK); + ICACHE->CACHE_CTRL &= (~ICACHE_CACHE_CTRL_CACHE_STB_EN_MASK); + + do { + status = + ICACHE->CACHE_STATUS & ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK; + } while (status == 0); + + ICACHE->CACHE_CTRL &= ~ICACHE_CACHE_CTRL_CACHE_BYPASS_MASK; +#endif + +#if defined(HAL_DCACHE_MODULE_ENABLED) + /* stb enable, stb_entry=7, stb_timeout enable, write back */ + DCACHE->CACHE_CTRL |= DCACHE_CACHE_CTRL_CACHE_EN_MASK | + (7U << DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT) | + DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_MASK | + DCACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK; + DCACHE->STB_TIMEOUT_CTRL = 1; + + do { + status = + DCACHE->CACHE_STATUS & DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK; + } while (status == 0); + + DCACHE->CACHE_CTRL &= ~DCACHE_CACHE_CTRL_CACHE_BYPASS_MASK; + + /* enable dap cache access for jtag protocol. don't modify the uncache data + * by jtag, the data will be inconsistent. */ + GRF->MCU_CON0 |= GRF_MCU_CON0_M4_DAP_DCACHE_MASK; +#endif +} + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit(void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} + diff --git a/bsp/rockchip/common/rk_hal/lib/CMSIS/LICENSE.txt b/bsp/rockchip/common/rk_hal/lib/CMSIS/LICENSE.txt new file mode 100644 index 00000000000..8dada3edaf5 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/bsp/rockchip/common/rk_hal/lib/bsp/RK2108/hal_bsp.c b/bsp/rockchip/common/rk_hal/lib/bsp/RK2108/hal_bsp.c new file mode 100644 index 00000000000..bf79d3b375b --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/bsp/RK2108/hal_bsp.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_bsp.h" + +#ifdef HAL_UART_MODULE_ENABLED +const struct HAL_UART_DEV g_uart2Dev = +{ + .pReg = UART2, + .sclkID = CLK_UART2, + .sclkGateID = CLK_UART2_GATE, + .pclkGateID = PCLK_UART2_GATE, + .irqNum = UART2_IRQn, + .isAutoFlow = false, +}; +#endif + +__WEAK void BSP_MPU_Init(void) +{ +} + +void BSP_Init(void) +{ + BSP_MPU_Init(); +} + +void BSP_DeInit(void) +{ +} + diff --git a/bsp/rockchip/common/rk_hal/lib/bsp/RK2108/hal_bsp.h b/bsp/rockchip/common/rk_hal/lib/bsp/RK2108/hal_bsp.h new file mode 100644 index 00000000000..22a9831c0da --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/bsp/RK2108/hal_bsp.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __BSP_H__ +#define __BSP_H__ + +#include "hal_base.h" + +/***************************** MACRO Definition ******************************/ + +/***************************** Structure Definition **************************/ +#ifdef HAL_UART_MODULE_ENABLED +extern const struct HAL_UART_DEV g_uart2Dev; +#endif + +/***************************** Function Declare ******************************/ + +void BSP_MPU_Init(void); +void BSP_Init(void); +void BSP_DeInit(void); + +#endif diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_base.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_base.h new file mode 100644 index 00000000000..a8991cef165 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_base.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_BASE + * @{ + */ + +#ifndef _HAL_BASE_H_ +#define _HAL_BASE_H_ + +#include "hal_conf.h" +#include "hal_driver.h" +#include "hal_debug.h" + +/***************************** MACRO Definition ******************************/ + +/** @defgroup HAL_BASE_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/** enter markrom usb upgrade */ +#define SYS_UPGRADE_FLAG (0xEF08A53C) + +#define IS_TICKFREQ(f) (((f) == HAL_TICK_FREQ_1KHZ) || ((f) == HAL_TICK_FREQ_100HZ) || ((f) == HAL_TICK_FREQ_10HZ)) + +/***************************** Structure Definition **************************/ +typedef enum { + HAL_TICK_FREQ_10HZ = 100U, /**< 10 ticks per second, so it's 100ms/tick */ + HAL_TICK_FREQ_100HZ = 10U, /**< 100 ticks per second, so it's 10ms/tick */ + HAL_TICK_FREQ_1KHZ = 1U, /**< 1000 ticks per second, so it's 1ms/tick */ + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} eHAL_tickFreq; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup HAL_BASE_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_Init(void); +HAL_Status HAL_DeInit(void); +HAL_Status HAL_InitTick(uint32_t tickPriority); +HAL_Status HAL_IncTick(void); +uint32_t HAL_GetTick(void); +HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq); +eHAL_tickFreq HAL_GetTickFreq(void); + +HAL_Status HAL_DelayUs(uint32_t us); +HAL_Status HAL_DelayMs(uint32_t ms); +HAL_Status HAL_CPUDelayUs(uint32_t us); +HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSource); + +uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder); +uint64_t HAL_GetSysTimerCount(void); + +/** @} */ + +/********************* Public Function Definition ***************************/ +/** @defgroup HAL_BASE_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief uint64_t numerator / uint32_t denominator + * @param numerator + * @param denominator + * @return uint64_t result + */ +__STATIC_INLINE uint64_t HAL_DivU64(uint64_t numerator, uint32_t denominator) +{ + return HAL_DivU64Rem(numerator, denominator, NULL); +} + +/** + * @brief uint32_t numerator / uint32_t denominator rounded to nearest integer + * @param numerator + * @param denominator + * @return uint32_t result rounded to nearest integer + */ +__STATIC_INLINE uint32_t HAL_DivRoundClosest(uint32_t numerator, uint32_t denominator) +{ + return (numerator + (denominator / 2)) / denominator; +} + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_cache.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_cache.h new file mode 100644 index 00000000000..14e8eb9149f --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_cache.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CACHE + * @{ + */ + +#ifndef _HAL_CACHE_H_ +#define _HAL_CACHE_H_ + +#include "hal_def.h" +#include "hal_debug.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup CACHE_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/***************************** Structure Definition **************************/ + +/** + * performance measurement count for icache & dcache + * + */ +struct CACHE_PMU_CNT { + uint32_t rdNum; /**< PMU read number counter */ + uint32_t wrNum; /**< PMU write number counter */ + uint32_t sramRdHit; /**< PMU SRAM hit counter */ + uint32_t hbRdHit; /**< PMU hot buffer hit */ + uint32_t stbRdHit; /**< PMU store buffer hit */ + uint32_t rdHit; /**< PMU read hit counter */ + uint32_t wrHit; /**< PMU write hit counter */ + uint32_t rdMissPenalty; /**< PMU read miss penalty counter */ + uint32_t wrMissPenalty; /**< PMU write miss penalty counter */ + uint32_t rdLat; /**< PMU read latency */ + uint32_t wrLat; /**< PMU write latency */ +}; + +/** @} */ +/********************* Public Function Definition ****************************/ +/** @defgroup CACHE_Exported_Functions_Group5 Other Functions + * @attention these APIs allow direct use in the HAL layer + * @{ + */ + +uint32_t HAL_CpuAddrToDmaAddr(uint32_t cpuAddr); +HAL_Status HAL_ICACHE_Enable(void); +HAL_Status HAL_ICACHE_Disable(void); +HAL_Status HAL_ICACHE_Invalidate(void); +HAL_Status HAL_ICACHE_InvalidateByRange(uint32_t address, uint32_t sizeByte); +HAL_Status HAL_ICACHE_EnablePMU(void); +HAL_Status HAL_ICACHE_DisablePMU(void); +HAL_Status HAL_ICACHE_GetPMU(struct CACHE_PMU_CNT *stat); +HAL_Status HAL_ICACHE_EnableInt(void); +HAL_Status HAL_ICACHE_DisableInt(void); +HAL_Check HAL_ICACHE_GetInt(void); +uint32_t HAL_ICACHE_GetErrAddr(void); +HAL_Status HAL_ICACHE_ClearInt(void); +HAL_Status HAL_DCACHE_Enable(void); +HAL_Status HAL_DCACHE_Disable(void); +HAL_Status HAL_DCACHE_Invalidate(void); +HAL_Status HAL_DCACHE_InvalidateByRange(uint32_t address, uint32_t sizeByte); +HAL_Status HAL_DCACHE_CleanByRange(uint32_t address, uint32_t sizeByte); +HAL_Status HAL_DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t sizeByte); +HAL_Status HAL_DCACHE_CleanInvalidate(void); +HAL_Status HAL_DCACHE_EnablePMU(void); +HAL_Status HAL_DCACHE_DisablePMU(void); +HAL_Status HAL_DCACHE_GetPMU(struct CACHE_PMU_CNT *stat); +HAL_Status HAL_DCACHE_EnableInt(void); +HAL_Status HAL_DCACHE_DisableInt(void); +HAL_Check HAL_DCACHE_GetInt(void); +HAL_Status HAL_DCACHE_ClearInt(void); +uint32_t HAL_DCACHE_GetErrAddr(void); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_cru.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_cru.h new file mode 100644 index 00000000000..d7ca750316f --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_cru.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_CRU_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +#ifndef _HAL_CRU_H_ +#define _HAL_CRU_H_ + +#include "hal_def.h" + +/*************************** MACRO Definition ****************************/ +/** @defgroup CRU_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define MHZ 1000000 +#define KHZ 1000 + +#ifndef PLL_INPUT_OSC_RATE +#define PLL_INPUT_OSC_RATE (24 * MHZ) +#endif + +#define CLK_RESET_GET_REG_OFFSET(x) ((uint32_t)((x) / 16)) +#define CLK_RESET_GET_BITS_SHIFT(x) ((uint32_t)((x) % 16)) + +#define CLK_GATE_GET_REG_OFFSET(x) ((uint32_t)((x) / 16)) +#define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)((x) % 16)) + +#define CLK_GET_MUX(x) ((x) & 0x0F0F00FFU) +#define CLK_GET_DIV(x) ((((x) & 0xFF00U) >> 8) | (((x) & 0xF0F00000U) >> 4)) + +#define WIDTH_TO_MASK(width) ((1 << (width)) - 1) + +#define CLK_MUX_REG_OFFSET_SHIFT 0U +#define CLK_MUX_REG_OFFSET_MASK 0x0000FFFFU +#define CLK_MUX_SHIFT_SHIFT 16U +#define CLK_MUX_SHIFT_MASK 0x00FF0000U +#define CLK_MUX_WIDTH_SHIFT 24U +#define CLK_MUX_WIDTH_MASK 0xFF000000U + +#define CLK_MUX_GET_REG_OFFSET(x) \ + (((uint32_t)(x) & CLK_MUX_REG_OFFSET_MASK) >> CLK_MUX_REG_OFFSET_SHIFT) +#define CLK_MUX_GET_BITS_SHIFT(x) \ + (((uint32_t)(x) & CLK_MUX_SHIFT_MASK) >> CLK_MUX_SHIFT_SHIFT) +#define CLK_MUX_GET_MASK(x) \ + WIDTH_TO_MASK((((uint32_t)(x) & CLK_MUX_WIDTH_MASK) >> CLK_MUX_WIDTH_SHIFT)) \ + << CLK_MUX_GET_BITS_SHIFT(x) + +#define CLK_DIV_REG_OFFSET_SHIFT 0U +#define CLK_DIV_REG_OFFSET_MASK 0x0000FFFFU +#define CLK_DIV_SHIFT_SHIFT 16U +#define CLK_DIV_SHIFT_MASK 0x00FF0000U +#define CLK_DIV_WIDTH_SHIFT 24U +#define CLK_DIV_WIDTH_MASK 0xFF000000U + +#define CLK_DIV_GET_REG_OFFSET(x) \ + (((uint32_t)(x) & CLK_DIV_REG_OFFSET_MASK) >> CLK_DIV_REG_OFFSET_SHIFT) +#define CLK_DIV_GET_BITS_SHIFT(x) \ + (((uint32_t)(x) & CLK_DIV_SHIFT_MASK) >> CLK_DIV_SHIFT_SHIFT) +#define CLK_DIV_GET_MASK(x) \ + WIDTH_TO_MASK((((uint32_t)(x) & CLK_DIV_WIDTH_MASK) >> CLK_DIV_WIDTH_SHIFT)) \ + << CLK_DIV_GET_BITS_SHIFT(x) + +#define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, \ + _frac) \ + { \ + .rate = _rate##U, .fbDiv = _fbdiv, .postDiv1 = _postdiv1, \ + .refDiv = _refdiv, .postDiv2 = _postdiv2, .dsmpd = _dsmpd, \ + .frac = _frac, \ + } + +struct PLL_CONFIG { + uint32_t rate; + uint32_t fbDiv; + uint32_t postDiv1; + uint32_t refDiv; + uint32_t postDiv2; + uint32_t dsmpd; + uint32_t frac; +}; + +struct PLL_SETUP { + __IO uint32_t *conOffset0; + __IO uint32_t *conOffset1; + __IO uint32_t *conOffset2; + __IO uint32_t *conOffset3; + __IO uint32_t *modeOffset; + __I uint32_t *stat0; + uint32_t modeShift; + uint32_t lockShift; + uint32_t modeMask; + const struct PLL_CONFIG *rateTable; +}; + +typedef enum { + GLB_SRST_FST = 0xfdb9, + GLB_SRST_SND = 0xeca8, +} eCRU_GlbSrstType; + +typedef enum { + GLB_RST_FST_WDT0 = 0U, + GLB_RST_SND_WDT0, + GLB_RST_FST_WDT1, + GLB_RST_SND_WDT1, + GLB_RST_FST_WDT2, + GLB_RST_SND_WDT2, +} eCRU_WdtRstType; + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup CRU_Public_Function_Declare Public Function Declare + * @{ + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup); +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate); +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup); +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup); + +HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk); +HAL_Status HAL_CRU_ClkEnable(uint32_t clk); +HAL_Status HAL_CRU_ClkDisable(uint32_t clk); + +HAL_Check HAL_CRU_ClkIsReset(uint32_t clk); +HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk); +HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk); + +HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue); +uint32_t HAL_CRU_ClkGetDiv(uint32_t divName); + +HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue); +uint32_t HAL_CRU_ClkGetMux(uint32_t muxName); + +HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, + uint32_t *numerator, + uint32_t *denominator); + +uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName); +HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate); + +HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId); +HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId); + +HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv); + +HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type); + +HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType); + +HAL_Status HAL_CRU_PllCompensation(eCLOCK_Name clockName, int ppm); + +#ifdef HAL_CRU_AS_FEATURE_ENABLED +/** + * @brief it is for AS init. + */ +void HAL_CRU_AsInit(void); + +/** + * @brief it is for AS enable. + * @param ch: channel + * @param en: 1 is enable, 0 is disable. + */ +void HAL_CRU_AsEnable(uint8_t ch, uint8_t en); +#endif + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_CRU_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_debug.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_debug.h new file mode 100644 index 00000000000..90002166e9c --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_debug.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2018-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_DEBUG_H_ +#define _HAL_DEBUG_H_ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup DEBUG + * @{ + */ + +/***************************** MACRO Definition ******************************/ + +/* Run only for debugging, please refer to how-to-use for the definition of the specification. */ +//#define HAL_DBG_USING_RTT_SERIAL +//#define HAL_DBG_USING_LIBC_PRINTF +#ifdef HAL_DBG_USING_RTT_SERIAL +#include +#include + +#define HAL_SYSLOG rt_kprintf +#elif defined(HAL_DBG_USING_LIBC_PRINTF) +#define HAL_SYSLOG printf +#endif + +/** @defgroup DEBUG_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#ifndef HAL_SYSLOG +#define HAL_SYSLOG HAL_DBG_Printf +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_DBG_INFO_ON) +#define HAL_DBG(fmt, arg...) HAL_SYSLOG("[HAL INFO] " fmt, ##arg) +#else +#define HAL_DBG(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL INFO] " fmt, ##arg); } while (0) +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_DBG_WRN_ON) +#define HAL_DBG_WRN(fmt, arg...) HAL_SYSLOG("[HAL WARNING] " fmt, ##arg) +#else +#define HAL_DBG_WRN(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL WARNING] " fmt, ##arg); } while (0) +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_DBG_ERR_ON) +#define HAL_DBG_ERR(fmt, arg...) HAL_SYSLOG("[HAL ERROR] " fmt, ##arg) +#else +#define HAL_DBG_ERR(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL ERROR] " fmt, ##arg); } while (0) +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_ASSERT_ON) +#define HAL_ASSERT(expr) \ + do { \ + if (!(expr)) \ + HAL_AssertFailed((const char *)__FILE__, __LINE__); \ + } while (0) +#else +#define HAL_ASSERT(expr) +#endif + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup DEBUG_Public_Function_Declare Public Function Declare + * @{ + */ + +void HAL_AssertFailed(const char *file, uint32_t line); +HAL_Status HAL_DBG_HEX(char *s, void *buf, uint32_t width, uint32_t len); +#ifdef __GNUC__ +__attribute__((__format__(printf, 1, 2))) +#endif +int32_t HAL_DBG_Printf(const char *format, ...); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_def.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_def.h new file mode 100644 index 00000000000..268cd99f5a8 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_def.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_DEF + * @{ + */ + +#ifndef _HAL_DEF_H_ +#define _HAL_DEF_H_ + +#include +#include +#include +#include +#include +#include + +#include "cmsis_compiler.h" +#include "soc.h" +#include "hal_list.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup HAL_DEF_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define SET_BIT(REG, BIT) ((*(volatile uint32_t *)&(REG)) |= (BIT)) /**< Set 1 to the register specific bit field */ +#define CLEAR_BIT(REG, MASK) ((*(volatile uint32_t *)&(REG)) &= ~(MASK)) /**< Clear the specific bits filed from the register */ +#define READ_BIT(REG, MASK) ((*(volatile const uint32_t *)&(REG)) & (MASK)) /**< Read the value of a specific bits field from the register */ +#define CLEAR_REG(REG) ((*(volatile uint32_t *)&(REG)) = (0x0)) /**< Write 0 to the register */ +#define WRITE_REG(REG, VAL) ((*(volatile uint32_t *)&(REG)) = (VAL)) /**< Write the register */ +#define READ_REG(REG) ((*(volatile const uint32_t *)&(REG))) /**< Read the register */ +#define MODIFY_REG(REG, CLEARMASK, SETMASK) \ + WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) /**< Clear and set the value of a specific bits field from the register */ +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +#if defined(__GNUC__) || defined(__CC_ARM) +#define MASK_TO_WE(msk) (__builtin_constant_p(msk) ? ((msk) > 0xFFFFU ? 0 : ((msk) << 16)) : ((msk) << 16)) +#else +#define MASK_TO_WE(msk) ((msk) << 16) +#endif +#define VAL_MASK_WE(msk, val) ((MASK_TO_WE(msk)) | (val)) +#define WRITE_REG_MASK_WE(reg, msk, val) WRITE_REG(reg, (VAL_MASK_WE(msk, val))) + +/* Misc OPS Marco */ +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define RESET 0 +#define HAL_IS_BIT_SET(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) != RESET) /**< Check if the the specific bits filed from the register is valid */ +#define HAL_IS_BIT_CLR(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) == RESET) /**< Check if the the specific bits filed from the register is isvalid */ + +#define HAL_BIT(nr) (1UL << (nr)) +#define HAL_ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0])) +#define HAL_MAX(x, y) ((x) > (y) ? (x) : (y)) +#define HAL_MIN(x, y) ((x) < (y) ? (x) : (y)) + +#define HAL_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) + +#define HAL_IS_ALIGNED(x, a) (((x) & (a - 1)) == 0) +#ifdef CACHE_LINE_SIZE +#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), CACHE_LINE_SIZE) +#else +#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), 4) +#endif + +/* Compiller Macro */ +#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) || defined(__ICCARM__) +#define HAL_UNUSED __attribute__((__unused__)) +#else +#define HAL_UNUSED +#endif + +#ifdef CACHE_LINE_SIZE +#define HAL_CACHELINE_ALIGNED __ALIGNED(CACHE_LINE_SIZE) +#else +#define HAL_CACHELINE_ALIGNED +#endif + +#ifdef HAL_SRAM_SECTION_ENABLED +#define HAL_SECTION_SRAM_CODE __attribute__((section(".sram_code"))) +#define HAL_SECTION_SRAM_RODATA __attribute__((section(".sram_rodata"))) +#define HAL_SECTION_SRAM_DATA __attribute__((section(".sram_data"))) +#define HAL_SECTION_SRAM_BSS __attribute__((section(".sram_bss"))) +#else +#define HAL_SECTION_SRAM_CODE +#define HAL_SECTION_SRAM_RODATA +#define HAL_SECTION_SRAM_DATA +#define HAL_SECTION_SRAM_BSS +#endif + +#ifdef HAL_PSRAM_SECTION_ENABLED +#define HAL_SECTION_PSRAM_CODE __attribute__((section(".psram_code"))) +#define HAL_SECTION_PSRAM_RODATA __attribute__((section(".psram_rodata"))) +#define HAL_SECTION_PSRAM_DATA __attribute__((section(".psram_data"))) +#define HAL_SECTION_PSRAM_BSS __attribute__((section(".psram_bss"))) +#else +#define HAL_SECTION_PSRAM_CODE +#define HAL_SECTION_PSRAM_RODATA +#define HAL_SECTION_PSRAM_DATA +#define HAL_SECTION_PSRAM_BSS +#endif + +#ifdef HAL_XIP_SECTION_ENABLED +#define HAL_SECTION_XIP_CODE __attribute__((section(".xip_code"))) +#define HAL_SECTION_XIP_RODATA __attribute__((section(".xip_rodata"))) +#else +#define HAL_SECTION_XIP_CODE +#define HAL_SECTION_XIP_RODATA +#endif + +/** MCU systick clock source */ +typedef enum { + HAL_SYSTICK_CLKSRC_CORE, + HAL_SYSTICK_CLKSRC_EXT +} eHAL_systickClkSource; + +/** Check if is MCU systick clock source */ +#define IS_SYSTICK_SOURCE(s) (((s) == HAL_SYSTICK_CLKSRC_CORE) || ((s) == HAL_SYSTICK_CLKSRC_EXT)) + +/***************************** Structure Definition **************************/ +/** HAL boolean type definition */ +typedef enum { + HAL_FALSE = 0x00U, + HAL_TRUE = 0x01U +} HAL_Check; + +/** HAL error code definition */ +typedef enum { + HAL_OK = 0x00U, + HAL_ERROR = (-1), + HAL_BUSY = (-16), + HAL_NODEV = (-19), + HAL_INVAL = (-22), + HAL_NOSYS = (-38), + HAL_TIMEOUT = (-110) +} HAL_Status; + +/** HAL functional status definition */ +typedef enum { + HAL_DISABLE = 0x00U, + HAL_ENABLE = 0x01U +} HAL_FuncStatus; + +/** HAL lock structures definition */ +typedef enum { + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockStatus; + +/** RK GPIO bank definition */ +typedef enum { +#ifdef GPIO0 + GPIO_BANK0 = 0, +#endif +#ifdef GPIO1 + GPIO_BANK1 = 1, +#endif +#ifdef GPIO2 + GPIO_BANK2 = 2, +#endif +#ifdef GPIO3 + GPIO_BANK3 = 3, +#endif +#ifdef GPIO4 + GPIO_BANK4 = 4, +#endif + GPIO_BANK_NUM +} eGPIO_bankId; + +/** HAL function type definition */ +typedef void (*pFunc)(void); + +/** @} */ +/***************************** Function Declare ******************************/ + +#endif + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_dma.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_dma.h new file mode 100644 index 00000000000..5b4b5720840 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_dma.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +#ifndef _HAL_DMA_H +#define _HAL_DMA_H + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup DMA_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/***************************** Structure Definition **************************/ +/** + * enum DMA_TRANSFER_DIRECTION - dma transfer mode and direction indicator + */ +typedef enum { + DMA_MEM_TO_MEM, /**< Async/Memcpy mode */ + DMA_MEM_TO_DEV, /**< Slave mode & From Memory to Device */ + DMA_DEV_TO_MEM, /**< Slave mode & From Device to Memory */ + DMA_DEV_TO_DEV, /**< Slave mode & From Device to Device */ + DMA_TRANS_NONE, +} eDMA_TRANSFER_DIRECTION; + +/** + * enum DMA_SLAVE_BUSWIDTH - defines bus width of the DMA slave + * device, source or target buses + */ +typedef enum { + DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, + DMA_SLAVE_BUSWIDTH_1_BYTE = 1, + DMA_SLAVE_BUSWIDTH_2_BYTES = 2, + DMA_SLAVE_BUSWIDTH_3_BYTES = 3, + DMA_SLAVE_BUSWIDTH_4_BYTES = 4, + DMA_SLAVE_BUSWIDTH_8_BYTES = 8, + DMA_SLAVE_BUSWIDTH_16_BYTES = 16, + DMA_SLAVE_BUSWIDTH_32_BYTES = 32, + DMA_SLAVE_BUSWIDTH_64_BYTES = 64, +} eDMA_SLAVE_BUSWIDTH; + +/** + * struct DMA_SLAVE_CONFIG - dma slave channel runtime config + */ +struct DMA_SLAVE_CONFIG { + eDMA_TRANSFER_DIRECTION direction; /**< Transfer direction. */ + eDMA_SLAVE_BUSWIDTH srcAddrWidth; /**< The width in bytes of the source, + * Legal values: 1, 2, 4, 8. + */ + eDMA_SLAVE_BUSWIDTH dstAddrWidth; /**< The same as srcAddrWidth. */ + uint32_t srcAddr; /**< The source physical address. */ + uint32_t dstAddr; /**< The destination physical address. */ + uint16_t srcMaxBurst; /**< The maximum number of words (note: words, as in + * units of the srcAddrWidth member, not bytes) that + * can be sent in one burst to the device, Typically + * something like half the FIFO depth on I/O peri so + * you don't overflow it. + */ + uint16_t dstMaxBurst; /**< The same as srcMaxBurst for destination. */ + uint16_t srcInterlaceSize; /**< The interlace size for src mem increase */ + uint16_t dstInterlaceSize; /**< The interlace size for dst mem increase */ +}; + +/** + * dma complete callback. + */ +typedef void (*DMA_Callback)(void *cparam); + +/** @} */ + +/********************* Public Function Definition ****************************/ +/** @defgroup DMA_Exported_Functions_Group5 Other Functions + * @{ +*/ + +__STATIC_INLINE bool HAL_DMA_IsSlaveDirection(eDMA_TRANSFER_DIRECTION direction) +{ + return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); +} + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_driver.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_driver.h new file mode 100644 index 00000000000..f31092152e3 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_driver.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2018-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_DRIVER_H_ +#define _HAL_DRIVER_H_ + +#include "hal_pm.h" + +#ifdef HAL_ACDCDIG_MODULE_ENABLED +#include "hal_acdcdig.h" +#endif + +#ifdef HAL_ACODEC_MODULE_ENABLED +#include "hal_acodec.h" +#endif + +#ifdef HAL_AUDIOPWM_MODULE_ENABLED +#include "hal_audiopwm.h" +#endif + +#include "hal_cache.h" + +#ifdef HAL_BUFMGR_MODULE_ENABLED +#include "hal_bufmgr.h" +#endif + +#ifdef HAL_CANFD_MODULE_ENABLED +#include "hal_canfd.h" +#endif + +#ifdef HAL_CKCAL_MODULE_ENABLED +#include "hal_ckcal.h" +#endif + +#ifdef HAL_CACHE_ECC_MODULE_ENABLED +#include "hal_cache_ecc.h" +#endif + +#ifdef HAL_CPU_TOPOLOGY_MODULE_ENABLED +#include "hal_cpu_topology.h" +#endif + +#ifdef HAL_CRU_MODULE_ENABLED +#include "hal_cru.h" +#endif + +#ifdef HAL_CRYPTO_MODULE_ENABLED +#include "hal_crypto.h" +#endif + +#ifdef HAL_DSI_MODULE_ENABLED +#include "hal_display.h" +#include "hal_dsi.h" +#endif + +#ifdef HAL_DEMO_MODULE_ENABLED +#include "hal_demo.h" +#endif + +#ifdef HAL_DDR_ECC_MODULE_ENABLED +#include "hal_ddr_ecc.h" +#endif + +#ifdef HAL_DSP_MODULE_ENABLED +#include "hal_dsp.h" +#endif + +#include "hal_dma.h" + +#ifdef HAL_DWDMA_MODULE_ENABLED +#include "hal_dwdma.h" +#endif + +#ifdef HAL_EFUSE_MODULE_ENABLED +#include "hal_efuse.h" +#endif + +#ifdef HAL_GMAC_MODULE_ENABLED +#include "hal_gmac.h" +#endif + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "hal_gpio.h" +#endif + +#ifdef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED +#include "hal_gpio_irq_group.h" +#endif + +#ifdef HAL_PINCTRL_MODULE_ENABLED +#include "hal_pinctrl.h" +#endif + +#if defined(HAL_HCD_MODULE_ENABLED) || defined(HAL_PCD_MODULE_ENABLED) +#include "hal_usb_core.h" +#include "hal_usb_phy.h" +#endif + +#if defined(HAL_EHCI_MODULE_ENABLED) || defined(HAL_OHCI_MODULE_ENABLED) +#include "hal_usbh.h" +#endif + +#ifdef HAL_HCD_MODULE_ENABLED +#include "hal_hcd.h" +#endif + +#ifdef HAL_HWSPINLOCK_MODULE_ENABLED +#include "hal_hwspinlock.h" +#endif + +#ifdef HAL_HYPERPSRAM_MODULE_ENABLED +#include "hal_hyperpsram.h" +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +#include "hal_i2c.h" +#endif + +#ifdef HAL_I2S_MODULE_ENABLED +#include "hal_i2s.h" +#endif + +#ifdef HAL_I2STDM_MODULE_ENABLED +#include "hal_i2stdm.h" +#endif + +#ifdef HAL_INTC_MODULE_ENABLED +#include "hal_intc.h" +#endif + +#ifdef HAL_IRQ_HANDLER_MODULE_ENABLED +#include "hal_irq_handler.h" +#endif + +#ifdef HAL_GIC_MODULE_ENABLED +#include "hal_gic.h" +#endif + +#ifdef HAL_MBOX_MODULE_ENABLED +#include "hal_mbox.h" +#endif + +#ifdef HAL_NVIC_MODULE_ENABLED +#include "hal_nvic.h" +#endif + +#ifdef HAL_PCD_MODULE_ENABLED +#include "hal_pcd.h" +#endif + +#ifdef HAL_PDM_MODULE_ENABLED +#include "hal_pdm.h" +#endif + +#ifdef HAL_PL330_MODULE_ENABLED +#include "hal_pl330.h" +#endif + +#ifdef HAL_PMU_MODULE_ENABLED +#include "hal_pd.h" +#endif + +#ifdef HAL_PVTM_MODULE_ENABLED +#include "hal_pvtm.h" +#endif + +#ifdef HAL_PWM_MODULE_ENABLED +#include "hal_pwm.h" +#endif + +#include "hal_pwr.h" + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "hal_sdio.h" +#endif + +#ifdef HAL_SNOR_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_snor.h" +#endif + +#ifdef HAL_SFC_MODULE_ENABLED +#include "hal_sfc.h" +#endif + +#ifdef HAL_SPINAND_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_spinand.h" +#endif + +#ifdef HAL_SYSTICK_MODULE_ENABLED +#include "hal_systick.h" +#endif + +#ifdef HAL_FSPI_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_fspi.h" +#endif + +#ifdef HAL_QPIPSRAM_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_qpipsram.h" +#endif + +#ifdef HAL_TOUCHKEY_MODULE_ENABLED +#include "hal_touchkey.h" +#endif + +#ifdef HAL_TSADC_MODULE_ENABLED +#include "hal_tsadc.h" +#endif + +#ifdef HAL_SARADC_MODULE_ENABLED +#include "hal_saradc.h" +#endif + +#ifdef HAL_SMCCC_MODULE_ENABLED +#include "hal_smccc.h" +#endif + +#ifdef HAL_KEYCTRL_MODULE_ENABLED +#include "hal_keyctrl.h" +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +#include "hal_spi.h" +#endif + +#ifdef HAL_SPI2APB_MODULE_ENABLED +#include "hal_spi2apb.h" +#endif + +#ifdef HAL_TIMER_MODULE_ENABLED +#include "hal_timer.h" +#endif + +#ifdef HAL_UART_MODULE_ENABLED +#include "hal_uart.h" +#endif + +#ifdef HAL_VAD_MODULE_ENABLED +#include "hal_vad.h" +#endif + +#ifdef HAL_VICAP_MODULE_ENABLED +#include "hal_vicap.h" +#endif + +#ifdef HAL_VOP_MODULE_ENABLED +#include "hal_display.h" +#include "hal_vop.h" +#endif + +#ifdef HAL_WDT_MODULE_ENABLED +#include "hal_wdt.h" +#endif + +#endif diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_dwdma.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_dwdma.h new file mode 100644 index 00000000000..63615b6b7f9 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_dwdma.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2019-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_DWDMA_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup DWDMA + * @{ + */ + +#ifndef _HAL_DWDMA_H +#define _HAL_DWDMA_H + +#include "hal_def.h" + +/** @defgroup DWDMA_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/***************************** MACRO Definition ******************************/ + +#define NR_DESCS_PER_CHANNEL 8 +#define DMA_MAX_CHANNELS 8 + +/* Bitfields in CTL_LO */ +#define DWC_CTLL_INT_EN (1 << 0) /**< irqs enabled? */ +#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /**< bytes per element */ +#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4) +#define DWC_CTLL_DST_INC (0<<7) /**< DAR update/not */ +#define DWC_CTLL_DST_DEC (1<<7) +#define DWC_CTLL_DST_FIX (2<<7) +#define DWC_CTLL_SRC_INC (0<<7) /**< SAR update/not */ +#define DWC_CTLL_SRC_DEC (1<<9) +#define DWC_CTLL_SRC_FIX (2<<9) +#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /**< burst, \#elements */ +#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) +#define DWC_CTLL_S_GATH_EN (1 << 17) /**< src gather, !FIX */ +#define DWC_CTLL_D_SCAT_EN (1 << 18) /**< dst scatter, !FIX */ +#define DWC_CTLL_FC(n) ((n) << 20) +#define DWC_CTLL_FC_M2M (0 << 20) /**< mem-to-mem */ +#define DWC_CTLL_FC_M2P (1 << 20) /**< mem-to-periph */ +#define DWC_CTLL_FC_P2M (2 << 20) /**< periph-to-mem */ +#define DWC_CTLL_FC_P2P (3 << 20) /**< periph-to-periph */ +/* plus 4 transfer types for peripheral-as-flow-controller */ +#define DWC_CTLL_DMS(n) ((n)<<23) /**< dst master select */ +#define DWC_CTLL_SMS(n) ((n)<<25) /**< src master select */ +#define DWC_CTLL_LLP_D_EN (1 << 27) /**< dest block chain */ +#define DWC_CTLL_LLP_S_EN (1 << 28) /**< src block chain */ + +/* Bitfields in CTL_HI */ +#define DWC_CTLH_DONE 0x00001000 +#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff + +/* Bitfields in CFG_LO */ +#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /**< priority mask */ +#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /**< priority */ +#define DWC_CFGL_CH_SUSP (1 << 8) /**< pause xfer */ +#define DWC_CFGL_FIFO_EMPTY (1 << 9) /**< pause xfer */ +#define DWC_CFGL_HS_DST (1 << 10) /**< handshake w/dst */ +#define DWC_CFGL_HS_SRC (1 << 11) /**< handshake w/src */ +#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /**< scope of LOCK_CH */ +#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) +#define DWC_CFGL_LOCK_CH_XACT (2 << 12) +#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /**< scope of LOCK_BUS */ +#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) +#define DWC_CFGL_LOCK_BUS_XACT (2 << 14) +#define DWC_CFGL_LOCK_CH (1 << 15) /**< channel lockout */ +#define DWC_CFGL_LOCK_BUS (1 << 16) /**< busmaster lockout */ +#define DWC_CFGL_HS_DST_POL (1 << 18) /**< dst handshake active low */ +#define DWC_CFGL_HS_SRC_POL (1 << 19) /**< src handshake active low */ +#define DWC_CFGL_MAX_BURST(x) ((x) << 20) +#define DWC_CFGL_RELOAD_SAR (1 << 30) +#define DWC_CFGL_RELOAD_DAR (1 << 31) + +/* Bitfields in CFG_HI */ +#define DWC_CFGH_FCMODE (1 << 0) +#define DWC_CFGH_FIFO_MODE (1 << 1) +#define DWC_CFGH_PROTCTL(x) ((x) << 2) +#define DWC_CFGH_DS_UPD_EN (1 << 5) +#define DWC_CFGH_SS_UPD_EN (1 << 6) +#define DWC_CFGH_SRC_PER(x) ((x) << 7) +#define DWC_CFGH_DST_PER(x) ((x) << 11) + +/* Bitfields in SGR */ +#define DWC_SGR_SGI(x) ((x) << 0) +#define DWC_SGR_SGC(x) ((x) << 20) + +/* Bitfields in DSR */ +#define DWC_DSR_DSI(x) ((x) << 0) +#define DWC_DSR_DSC(x) ((x) << 20) + +/* Bitfields in CFG */ +#define DW_CFG_DMA_EN (1 << 0) + +/* bursts size */ +typedef enum { + DWDMA_MSIZE_1, + DWDMA_MSIZE_4, + DWDMA_MSIZE_8, + DWDMA_MSIZE_16, + DWDMA_MSIZE_32, + DWDMA_MSIZE_64, + DWDMA_MSIZE_128, + DWDMA_MSIZE_256, +} eDWDMA_MSIZE; + +/***************************** Structure Definition **************************/ + +/** + * LLI == Linked List Item; a.k.a. DMA block descriptor + */ +struct DW_LLI { + uint32_t sar; /**< values that are not changed by hardware */ + uint32_t dar; /**< values that are not changed by hardware */ + uint32_t llp; /**< chain to next lli */ + uint32_t ctllo; + uint32_t ctlhi; + + uint32_t sstat; /**< values that may get written back. */ + uint32_t dstat; /**< values that may get written back. */ +}; + +/** + * struct DW_DESC - dma transfer desc + */ +struct DW_DESC { + struct DW_LLI lli; /**< FIRST values the hardware uses, must be in the first place. */ + + uint32_t len; +}; + +/** + * struct DWDMA_CHAN - dw dma channel. + */ +struct DWDMA_CHAN { + struct HAL_DWDMA_DEV *dw; + struct DMA_CHAN_REGS *creg; + struct DMA_SLAVE_CONFIG config; + struct DW_DESC *desc; + eDMA_TRANSFER_DIRECTION direction; + + uint8_t mask; + uint8_t srcMaster; + uint8_t dstMaster; + uint8_t periId; + uint8_t chanId; + + bool cyclic; + bool paused; + + DMA_Callback callback; + void *cparam; +}; + +/** + * struct HAL_DWDMA_DEV - dw dma hal dev. + */ +struct HAL_DWDMA_DEV { + struct DMA_REG *pReg; + struct DWDMA_CHAN chan[DMA_MAX_CHANNELS]; + uint8_t irq[DMA_MAX_CHANNELS]; + uint8_t allChanMask; + uint8_t used; + uint8_t maxChans; + /* hardware configuration */ + uint8_t dataWidth; + uint32_t blockSize; + + void *priv; +}; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup DWDMA_Public_Function_Declare Public Function Declare + * @{ + */ + +uint32_t HAL_DWDMA_GetRawBlockStatus(struct HAL_DWDMA_DEV *dw); +uint32_t HAL_DWDMA_GetRawErrStatus(struct HAL_DWDMA_DEV *dw); +uint32_t HAL_DWDMA_GetRawXferStatus(struct HAL_DWDMA_DEV *dw); + +HAL_Status HAL_DWDMA_Init(struct HAL_DWDMA_DEV *dw); +HAL_Status HAL_DWDMA_DeInit(struct HAL_DWDMA_DEV *dw); + +HAL_Status HAL_DWDMA_Start(struct DWDMA_CHAN *dwc); +HAL_Status HAL_DWDMA_Stop(struct DWDMA_CHAN *dwc); +HAL_Status HAL_DWDMA_Pause(struct DWDMA_CHAN *dwc); +HAL_Status HAL_DWDMA_Resume(struct DWDMA_CHAN *dwc); + +struct DWDMA_CHAN *HAL_DWDMA_RequestChannel(struct HAL_DWDMA_DEV *dma, DMA_REQ_Type id); +HAL_Status HAL_DWDMA_ReleaseChannel(struct DWDMA_CHAN *dwc); + +HAL_Status HAL_DWDMA_Config(struct DWDMA_CHAN *dwc, struct DMA_SLAVE_CONFIG *config); +HAL_Status HAL_DWDMA_PrepDmaMemcpy(struct DWDMA_CHAN *dwc, uint32_t dst, + uint32_t src, uint32_t len, + DMA_Callback callback, void *cparam); +HAL_Status HAL_DWDMA_PrepDmaCyclic(struct DWDMA_CHAN *dwc, uint32_t dmaAddr, + uint32_t len, uint32_t periodLen, + eDMA_TRANSFER_DIRECTION direction, + DMA_Callback callback, void *cparam); +HAL_Status HAL_DWDMA_PrepDmaSingle(struct DWDMA_CHAN *dwc, uint32_t dmaAddr, + uint32_t len, + eDMA_TRANSFER_DIRECTION direction, + DMA_Callback callback, void *cparam); + +uint32_t HAL_DWDMA_IrqHandler(struct HAL_DWDMA_DEV *dw, uint32_t chanId); +uint32_t HAL_DWDMA_HandleChan(struct HAL_DWDMA_DEV *dw, uint32_t chanId); +struct DWDMA_CHAN *HAL_DWDMA_GetChannel(struct HAL_DWDMA_DEV *dw, uint32_t chanId); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_DWDMA_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_gpio.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_gpio.h new file mode 100644 index 00000000000..93a51d35273 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_gpio.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +#ifndef __HAL_GPIO_H +#define __HAL_GPIO_H + +#include "hal_def.h" +#include "hal_pinctrl.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup GPIO_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#ifndef GPIO_VER_ID +#define GPIO_VER_ID (0U) +#endif + +#define PIN_NUMBER_PER_BANK (32) + +#define GPIO_PIN_SHIFT (0) /**< Bits 0-4: GPIO Pin number: 0 - 31 */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +#define GPIO_BANK_SHIFT (5) /**< Bits 5-7: GPIO Port number: 0 - 7 */ +#define GPIO_BANK_MASK (0x7 << GPIO_BANK_SHIFT) + +#define BANK_PIN(BANK, PIN) ((((BANK) << GPIO_BANK_SHIFT) & GPIO_BANK_MASK) + (((PIN) << GPIO_PIN_SHIFT) & GPIO_PIN_MASK)) + +/***************************** Structure Definition **************************/ +/** GPIO pin level definition */ +typedef enum { + GPIO_LOW, + GPIO_HIGH +} eGPIO_pinLevel; + +/** GPIO pin direction definition */ +typedef enum { + GPIO_IN, + GPIO_OUT +} eGPIO_pinDirection; + +/** GPIO pin debounce definition */ +typedef enum { + GPIO_DEBOUNCE_DIS, + GPIO_DEBOUNCE_EN +} eGPIO_pinDebounce; + +/** GPIO pin interrupt enable definition */ +typedef enum { + GPIO_INT_ENABLE, + GPIO_INT_DISABLE +} eGPIO_intEnable; + +/** GPIO pin interrupt type definition */ +typedef enum { + GPIO_INT_TYPE_NONE = 0x00000000, + GPIO_INT_TYPE_EDGE_RISING = 0x00000001, + GPIO_INT_TYPE_EDGE_FALLING = 0x00000002, + GPIO_INT_TYPE_EDGE_BOTH = (GPIO_INT_TYPE_EDGE_FALLING | GPIO_INT_TYPE_EDGE_RISING), + GPIO_INT_TYPE_LEVEL_HIGH = 0x00000004, + GPIO_INT_TYPE_LEVEL_LOW = 0x00000008, + GPIO_INT_TYPE_LEVEL_MASK = (GPIO_INT_TYPE_LEVEL_LOW | GPIO_INT_TYPE_LEVEL_HIGH), + GPIO_INT_TYPE_SENSE_MASK = 0x0000000f, + GPIO_INT_TYPE_DEFAULT = GPIO_INT_TYPE_SENSE_MASK, +} eGPIO_intType; + +/** GPIO pin interrupt mode definition */ +typedef enum { + GPIO_INT_MODE_EDGE_RISING, + GPIO_INT_MODE_EDGE_FALLING, + GPIO_INT_MODE_EDGE_RISING_FALLING, + GPIO_INT_MODE_LEVEL_HIGH, + GPIO_INT_MODE_LEVEL_LOW, + GPIO_INT_MODE_INVALID +} eGPIO_intMode; + +#define IS_GPIO_PIN_DIR(ACTION) (((ACTION) == GPIO_IN) || ((ACTION) == GPIO_OUT)) +#define IS_GPIO_PIN_LEVEL(ACTION) (((ACTION) == GPIO_LOW) || ((ACTION) == GPIO_HIGH)) + +#define IS_GPIO_PIN(PIN) ((PIN) != 0x00000000U) +#define IS_GPIO_HIGH_PIN(PIN) IS_GPIO_PIN(((PIN) & 0xFFFF0000U)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_PIN_A0) || \ + ((PIN) == GPIO_PIN_A1) || \ + ((PIN) == GPIO_PIN_A2) || \ + ((PIN) == GPIO_PIN_A3) || \ + ((PIN) == GPIO_PIN_A4) || \ + ((PIN) == GPIO_PIN_A5) || \ + ((PIN) == GPIO_PIN_A6) || \ + ((PIN) == GPIO_PIN_A7) || \ + ((PIN) == GPIO_PIN_B0) || \ + ((PIN) == GPIO_PIN_B1) || \ + ((PIN) == GPIO_PIN_B2) || \ + ((PIN) == GPIO_PIN_B3) || \ + ((PIN) == GPIO_PIN_B4) || \ + ((PIN) == GPIO_PIN_B5) || \ + ((PIN) == GPIO_PIN_B6) || \ + ((PIN) == GPIO_PIN_B7) || \ + ((PIN) == GPIO_PIN_C0) || \ + ((PIN) == GPIO_PIN_C1) || \ + ((PIN) == GPIO_PIN_C2) || \ + ((PIN) == GPIO_PIN_C3) || \ + ((PIN) == GPIO_PIN_C4) || \ + ((PIN) == GPIO_PIN_C5) || \ + ((PIN) == GPIO_PIN_C6) || \ + ((PIN) == GPIO_PIN_C7) || \ + ((PIN) == GPIO_PIN_D0) || \ + ((PIN) == GPIO_PIN_D1) || \ + ((PIN) == GPIO_PIN_D2) || \ + ((PIN) == GPIO_PIN_D3) || \ + ((PIN) == GPIO_PIN_D4) || \ + ((PIN) == GPIO_PIN_D5) || \ + ((PIN) == GPIO_PIN_D6) || \ + ((PIN) == GPIO_PIN_D7)) + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup GPIO_Exported_Definition_Group2 Public Functions Declare. + * @{ + */ +eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO); + +HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level); +HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction); +HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode); + +HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level); +HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction); + +void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank); + +/* The parameter pin for this function is special, it's 0~31. */ +void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin); + +/** @} */ + +#endif +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_list.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_list.h new file mode 100644 index 00000000000..4e3678ef0fb --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_list.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_LIST_H_ +#define _HAL_LIST_H_ + +/***************************** Structure Definition **************************/ + +/** double list struct */ +struct HAL_LIST_NODE { + struct HAL_LIST_NODE *next; + struct HAL_LIST_NODE *prev; +}; + +typedef struct HAL_LIST_NODE HAL_LIST; + +/***************************** Function Declare ******************************/ +/** + * @brief cast a member of a structure out to the containing structure + * @param ptr: the pointer to the member. + * @param type: the type of the container struct this is embedded in. + * @param member: the name of the member within the struct. + */ +#define HAL_CONTAINER_OF(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * @brief initialize a list object + * @param object: object itself. + */ +#define HAL_LIST_OBJECT_INIT(object) { &(object), &(object) } + +#define HAL_LIST_HEAD_INIT(name) { &(name), &(name) } + +/** + * @brief initialize a list head + * @param name: list name.. + */ +#define HAL_LIST_HEAD(name) \ + struct HAL_LIST_NODE name = HAL_LIST_HEAD_INIT(name) + +/** + * @brief initialize a list + * @param l: list to be initialized + */ +__STATIC_INLINE void HAL_LIST_Init(HAL_LIST *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * @param l: list to insert it + * @param n: new node to be inserted + */ +__STATIC_INLINE void HAL_LIST_InsertAfter(HAL_LIST *l, HAL_LIST *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * @param n: new node to be inserted + * @param l: list to insert it + */ +__STATIC_INLINE void HAL_LIST_InsertBefore(HAL_LIST *l, HAL_LIST *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n: the node to remove from the list. + */ +__STATIC_INLINE void HAL_LIST_Remove(HAL_LIST *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief tests whether a list is empty + * @param l: the list to test. + */ +__STATIC_INLINE int HAL_LIST_IsEmpty(const HAL_LIST *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l: the list to get. + */ +__STATIC_INLINE uint32_t HAL_LIST_Len(const HAL_LIST *l) +{ + uint32_t len = 0; + const HAL_LIST *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief get the struct for this entry + * @param node: the entry point + * @param type: the type of structure + * @param member: the name of list in structure + */ +#define HAL_LIST_ENTRY(node, type, member) \ + HAL_CONTAINER_OF(node, type, member) + +/** + * @brief iterate over a list + * @param pos: the rt_list_t * to use as a loop cursor. + * @param head: the head for your list. + */ +#define HAL_LIST_FOR_EACH(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * @brief iterate over a list safe against removal of list entry + * @param pos: the rt_list_t * to use as a loop cursor. + * @param n: another rt_list_t * to use as temporary storage + * @param head: the head for your list. + */ +#define HAL_LIST_FOR_EACH_SAFE(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * @brief iterate over list of given type + * @param pos: the type * to use as a loop cursor. + * @param head: the head for your list. + * @param member: the name of the list_struct within the struct. + */ +#define HAL_LIST_FOR_EACH_ENTRY(pos, head, member) \ + for (pos = HAL_LIST_ENTRY((head)->next, __typeof__(*pos), member); \ + &pos->member != (head); \ + pos = HAL_LIST_ENTRY(pos->member.next, __typeof__(*pos), member)) + +/** + * @brief iterate over list of given type safe against removal of list entry + * @param pos: the type * to use as a loop cursor. + * @param n: another type * to use as temporary storage + * @param head: the head for your list. + * @param member: the name of the list_struct within the struct. + */ +#define HAL_LIST_FOR_EACH_ENTRY_SAFE(pos, n, head, member) \ + for (pos = HAL_LIST_ENTRY((head)->next, __typeof__(*pos), member), \ + n = HAL_LIST_ENTRY(pos->member.next, __typeof__(*pos), member); \ + &pos->member != (head); \ + pos = n, n = HAL_LIST_ENTRY(n->member.next, __typeof__(*n), member)) + +/** + * @brief get the first element from a list + * @param ptr: the list head to take the element from. + * @param type: the type of the struct this is embedded in. + * @param member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define HAL_LIST_FIRST_ENTRY(ptr, type, member) \ + HAL_LIST_ENTRY((ptr)->next, type, member) + +#endif diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_nvic.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_nvic.h new file mode 100644 index 00000000000..d897c8fcfc0 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_nvic.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_NVIC_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup NVIC + * @{ + */ + +#ifndef _HAL_NVIC_H_ +#define _HAL_NVIC_H_ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup NVIC_Exported_Definition_Group1 Basic Definition + * @{ + */ + +typedef enum { + NVIC_PRIORITYGROUP_0 = (0x7U), /*!< 0 bits pre-emption, 8 bits subpriority*/ + NVIC_PRIORITYGROUP_1 = (0x6U), /*!< 1 bits pre-emption, 7 bits subpriority*/ + NVIC_PRIORITYGROUP_2 = (0x5U), /*!< 2 bits pre-emption, 6 bits subpriority*/ + NVIC_PRIORITYGROUP_3 = (0x4U), /*!< 3 bits pre-emption, 5 bits subpriority*/ + NVIC_PRIORITYGROUP_4 = (0x3U), /*!< 4 bits pre-emption, 4 bits subpriority*/ + NVIC_PRIORITYGROUP_5 = (0x2U), /*!< 5 bits pre-emption, 3 bits subpriority*/ +} eNVIC_PriorityGroup; + +#ifndef NVIC_PRIORITYGROUP_DEFAULT +#define NVIC_PRIORITYGROUP_DEFAULT NVIC_PRIORITYGROUP_5 /**< Can be redefined in soc.h */ +#endif + +/* preempt priority */ +#define NVIC_PERIPH_PRIO_LOWEST (0xFFU) +#ifndef NVIC_PERIPH_PRIO_DEFAULT +#if (__NVIC_PRIO_BITS == 2U) +#define NVIC_PERIPH_PRIO_DEFAULT (0x2U) /**< Can be redefined in soc.h */ +#elif (__NVIC_PRIO_BITS == 3U) +#define NVIC_PERIPH_PRIO_DEFAULT (0x4U) /**< Can be redefined in soc.h */ +#else +#define NVIC_PERIPH_PRIO_DEFAULT (0xFFU) /**< Can be redefined in soc.h */ +#endif +#endif +#define NVIC_PERIPH_PRIO_HIGHEST (0x0U) + +/* sub priority */ +#define NVIC_PERIPH_SUB_PRIO_LOWEST (0xFFU) +#define NVIC_PERIPH_SUB_PRIO_DEFAULT (0xFFU) +#define NVIC_PERIPH_SUB_PRIO_HIGHEST (0x0U) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x100U) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x100U) + +/** @brief Type define of NVIC interrupt handler */ +typedef void (*NVIC_IRQHandler)(void); + +/***************************** Structure Definition **************************/ + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup NVIC_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_NVIC_SetIRQHandler(IRQn_Type IRQn, NVIC_IRQHandler handler); +NVIC_IRQHandler HAL_NVIC_GetIRQHandler(IRQn_Type IRQn); +HAL_Status HAL_NVIC_SetPriorityGrouping(eNVIC_PriorityGroup priorityGroup); +uint32_t HAL_NVIC_GetPriorityGrouping(void); +HAL_Status HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t preemptPriority, uint32_t subPriority); +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); +HAL_Status HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +HAL_Status HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +HAL_Status HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +HAL_Check HAL_NVIC_IsPendingIRQ(IRQn_Type IRQn); +HAL_Status HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +HAL_Status HAL_NVIC_ConfigExtIRQ(IRQn_Type IRQn, NVIC_IRQHandler handler, + uint32_t preemptPriority, uint32_t subPriority); +HAL_Status HAL_NVIC_Init(void); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_NVIC_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pd.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pd.h new file mode 100644 index 00000000000..44f0ba2a2f2 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pd.h @@ -0,0 +1,44 @@ + +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_PMU_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PD + * @{ + */ + +#ifndef _HAL_PD_H_ +#define _HAL_PD_H_ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ + +/***************************** Structure Definition **************************/ + +/***************************** Function Declare ******************************/ +/** @defgroup PD_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_PD_On(ePD_Id pd); +HAL_Status HAL_PD_Off(ePD_Id pd); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_PMU_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pinctrl.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pinctrl.h new file mode 100644 index 00000000000..3cd72230423 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pinctrl.h @@ -0,0 +1,537 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PINCTRL + * @{ + */ + +#ifndef __HAL_PINCTRL_H__ +#define __HAL_PINCTRL_H__ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup PINCTRL_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/** PINCTRL IOFUNC Select definition */ +typedef enum { + IOFUNC_SEL_M0, + IOFUNC_SEL_M1, + IOFUNC_SEL_M2, +} eIOFUNC_SEL; + +typedef enum { +#if defined(GPIO0) + GPIO0_A0 = 0, + GPIO0_A1, + GPIO0_A2, + GPIO0_A3, + GPIO0_A4, + GPIO0_A5, + GPIO0_A6, + GPIO0_A7, + GPIO0_B0 = 8, + GPIO0_B1, + GPIO0_B2, + GPIO0_B3, + GPIO0_B4, + GPIO0_B5, + GPIO0_B6, + GPIO0_B7, + GPIO0_C0 = 16, + GPIO0_C1, + GPIO0_C2, + GPIO0_C3, + GPIO0_C4, + GPIO0_C5, + GPIO0_C6, + GPIO0_C7, + GPIO0_D0 = 24, + GPIO0_D1, + GPIO0_D2, + GPIO0_D3, + GPIO0_D4, + GPIO0_D5, + GPIO0_D6, + GPIO0_D7, +#endif +#if defined(GPIO1) + GPIO1_A0 = 32, + GPIO1_A1, + GPIO1_A2, + GPIO1_A3, + GPIO1_A4, + GPIO1_A5, + GPIO1_A6, + GPIO1_A7, + GPIO1_B0 = 40, + GPIO1_B1, + GPIO1_B2, + GPIO1_B3, + GPIO1_B4, + GPIO1_B5, + GPIO1_B6, + GPIO1_B7, + GPIO1_C0 = 48, + GPIO1_C1, + GPIO1_C2, + GPIO1_C3, + GPIO1_C4, + GPIO1_C5, + GPIO1_C6, + GPIO1_C7, + GPIO1_D0 = 56, + GPIO1_D1, + GPIO1_D2, + GPIO1_D3, + GPIO1_D4, + GPIO1_D5, + GPIO1_D6, + GPIO1_D7, +#endif +#if defined(GPIO2) + GPIO2_A0 = 64, + GPIO2_A1, + GPIO2_A2, + GPIO2_A3, + GPIO2_A4, + GPIO2_A5, + GPIO2_A6, + GPIO2_A7, + GPIO2_B0 = 72, + GPIO2_B1, + GPIO2_B2, + GPIO2_B3, + GPIO2_B4, + GPIO2_B5, + GPIO2_B6, + GPIO2_B7, + GPIO2_C0 = 80, + GPIO2_C1, + GPIO2_C2, + GPIO2_C3, + GPIO2_C4, + GPIO2_C5, + GPIO2_C6, + GPIO2_C7, + GPIO2_D0 = 88, + GPIO2_D1, + GPIO2_D2, + GPIO2_D3, + GPIO2_D4, + GPIO2_D5, + GPIO2_D6, + GPIO2_D7, +#endif +#if defined(GPIO3) + GPIO3_A0 = 96, + GPIO3_A1, + GPIO3_A2, + GPIO3_A3, + GPIO3_A4, + GPIO3_A5, + GPIO3_A6, + GPIO3_A7, + GPIO3_B0 = 104, + GPIO3_B1, + GPIO3_B2, + GPIO3_B3, + GPIO3_B4, + GPIO3_B5, + GPIO3_B6, + GPIO3_B7, + GPIO3_C0 = 112, + GPIO3_C1, + GPIO3_C2, + GPIO3_C3, + GPIO3_C4, + GPIO3_C5, + GPIO3_C6, + GPIO3_C7, + GPIO3_D0 = 120, + GPIO3_D1, + GPIO3_D2, + GPIO3_D3, + GPIO3_D4, + GPIO3_D5, + GPIO3_D6, + GPIO3_D7, +#endif +#if defined(GPIO4) + GPIO4_A0 = 128, + GPIO4_A1, + GPIO4_A2, + GPIO4_A3, + GPIO4_A4, + GPIO4_A5, + GPIO4_A6, + GPIO4_A7, + GPIO4_B0 = 136, + GPIO4_B1, + GPIO4_B2, + GPIO4_B3, + GPIO4_B4, + GPIO4_B5, + GPIO4_B6, + GPIO4_B7, + GPIO4_C0 = 144, + GPIO4_C1, + GPIO4_C2, + GPIO4_C3, + GPIO4_C4, + GPIO4_C5, + GPIO4_C6, + GPIO4_C7, + GPIO4_D0 = 152, + GPIO4_D1, + GPIO4_D2, + GPIO4_D3, + GPIO4_D4, + GPIO4_D5, + GPIO4_D6, + GPIO4_D7, +#endif + GPIO_NUM_MAX +} ePINCTRL_PIN; + +/** PINCTRL IOMUX definition */ +typedef enum { + PINCTRL_IOMUX_FUNC0, + PINCTRL_IOMUX_FUNC1, + PINCTRL_IOMUX_FUNC2, + PINCTRL_IOMUX_FUNC3, + PINCTRL_IOMUX_FUNC4, + PINCTRL_IOMUX_FUNC5, + PINCTRL_IOMUX_FUNC6, + PINCTRL_IOMUX_FUNC7 +} ePINCTRL_iomuxFunc; + +/** PINCTRL PULL definition */ +typedef enum { + PINCTRL_PULL_OD, + PINCTRL_PULL_UP, + PINCTRL_PULL_DOWN, + PINCTRL_PULL_KEEP +} ePINCTRL_pullMode; + +/** PINCTRL Drive Strength definition */ +typedef enum { + PINCTRL_DRIVE_LEVEL0, + PINCTRL_DRIVE_LEVEL1, + PINCTRL_DRIVE_LEVEL2, + PINCTRL_DRIVE_LEVEL3, + PINCTRL_DRIVE_LEVEL4, + PINCTRL_DRIVE_LEVEL5, + PINCTRL_DRIVE_LEVEL6, + PINCTRL_DRIVE_LEVEL7 +} ePINCTRL_driveLevel; + +/** PINCTRL Slew Rate definition */ +typedef enum { + PINCTRL_SLEWRATE_SLOW, + PINCTRL_SLEWRATE_FAST +} ePINCTRL_slewRate; + +/** PINCTRL Schmitt enable definition */ +typedef enum { + PINCTRL_SCHMITT_DIS, + PINCTRL_SCHMITT_EN +} ePINCTRL_schmitt; + +#define FLAG_MUX HAL_BIT(31) +#define FLAG_PUL HAL_BIT(30) +#define FLAG_DRV HAL_BIT(29) +#define FLAG_SRT HAL_BIT(28) +#define FLAG_SMT HAL_BIT(27) +#define SHIFT_MUX (0) +#define SHIFT_PUL (4) +#define SHIFT_DRV (8) +#define SHIFT_SRT (16) +#define SHIFT_SMT (18) +#define MASK_MUX (0xFU << SHIFT_MUX) +#define MASK_PUL (0xFU << SHIFT_PUL) +#define MASK_DRV (0xFFU << SHIFT_DRV) +#define MASK_SRT (0x3U << SHIFT_SRT) +#define MASK_SMT (0x3U << SHIFT_SMT) + +/** @brief PIN Configuration Mode + * Elements values convention: gggg g000 0000 ttrr dddd dddd pppp xxxx + * - ggggg : Flag to set Mux/Pull/Drive/Slewrate/Schmitt + * - tt : Schmitt value + * - rr : Slewrate value + * - dddddddd : Drive value + * - pppp : Pull value + * - xxxx : Mux mode value + */ +typedef enum { + PIN_CONFIG_MUX_FUNC0 = (0x0 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC1 = (0x1 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC2 = (0x2 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC3 = (0x3 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC4 = (0x4 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC5 = (0x5 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC6 = (0x6 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC7 = (0x7 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC8 = (0x8 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC9 = (0x9 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC10 = (0xa << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC11 = (0xb << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC12 = (0xc << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC13 = (0xd << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC14 = (0xe << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC15 = (0xf << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_DEFAULT = PIN_CONFIG_MUX_FUNC0, + +#if defined(SOC_SWALLOW) + PIN_CONFIG_PUL_NORMAL = (0x1 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DEFAULT = (0x0 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_UP = PIN_CONFIG_PUL_DEFAULT, + PIN_CONFIG_PUL_DOWN = PIN_CONFIG_PUL_DEFAULT, + PIN_CONFIG_PUL_KEEP = PIN_CONFIG_PUL_DEFAULT, +#else + PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_UP = (0x1 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DOWN = (0x2 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_KEEP = (0x3 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL, +#endif + +#if defined(SOC_RK3568) + PIN_CONFIG_DRV_LEVEL0 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x3 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x7 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0xf << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL4 = (0x1f << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL5 = (0x3f << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#else + PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x2 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL4 = (0x4 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL5 = (0x5 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL6 = (0x6 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL7 = (0x7 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#endif + + PIN_CONFIG_SRT_SLOW = (0x0 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_FAST = (0x1 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_SLOW, + + PIN_CONFIG_SMT_DISABLE = (0x0 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_ENABLE = (0x1 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_DEFAULT = PIN_CONFIG_SMT_DISABLE, + + PIN_CONFIG_MAX = 0xFFFFFFFFU, +} ePINCTRL_configParam; + +typedef enum { + GRF_MUX_INFO = 0, + GRF_PUL_INFO, + GRF_DRV_INFO, + GRF_SRT_INFO, + GRF_SMT_INFO, + GRF_INFO_NUM +} ePIN_GRF_INFO_ID; + +#define PIN_BANK_CFG_FLAGS(chn, cnt, reg, \ + offset0, bpp0, ppr0, \ + offset1, bpp1, ppr1, \ + offset2, bpp2, ppr2, \ + offset3, bpp3, ppr3, \ + offset4, bpp4, ppr4) \ + { \ + .channel = chn, \ + .pinCount = cnt, \ + .grfBase = reg, \ + .GRFInfo[GRF_MUX_INFO] = { .offset = offset0, .bitsPerPin = bpp0, .pinsPerReg = ppr0 }, \ + .GRFInfo[GRF_PUL_INFO] = { .offset = offset1, .bitsPerPin = bpp1, .pinsPerReg = ppr1 }, \ + .GRFInfo[GRF_DRV_INFO] = { .offset = offset2, .bitsPerPin = bpp2, .pinsPerReg = ppr2 }, \ + .GRFInfo[GRF_SRT_INFO] = { .offset = offset3, .bitsPerPin = bpp3, .pinsPerReg = ppr3 }, \ + .GRFInfo[GRF_SMT_INFO] = { .offset = offset4, .bitsPerPin = bpp4, .pinsPerReg = ppr4 }, \ + } + +/** @defgroup ePINCTRL_GPIO_PINS Pins Definition + * @{ + */ +typedef enum { + GPIO_PIN_A0 = 0x00000001U, /*!< Pin 0 selected */ + GPIO_PIN_A1 = 0x00000002U, /*!< Pin 1 selected */ + GPIO_PIN_A2 = 0x00000004U, /*!< Pin 2 selected */ + GPIO_PIN_A3 = 0x00000008U, /*!< Pin 3 selected */ + GPIO_PIN_A4 = 0x00000010U, /*!< Pin 4 selected */ + GPIO_PIN_A5 = 0x00000020U, /*!< Pin 5 selected */ + GPIO_PIN_A6 = 0x00000040U, /*!< Pin 6 selected */ + GPIO_PIN_A7 = 0x00000080U, /*!< Pin 7 selected */ + GPIO_PIN_B0 = 0x00000100U, /*!< Pin 8 selected */ + GPIO_PIN_B1 = 0x00000200U, /*!< Pin 9 selected */ + GPIO_PIN_B2 = 0x00000400U, /*!< Pin 10 selected */ + GPIO_PIN_B3 = 0x00000800U, /*!< Pin 11 selected */ + GPIO_PIN_B4 = 0x00001000U, /*!< Pin 12 selected */ + GPIO_PIN_B5 = 0x00002000U, /*!< Pin 13 selected */ + GPIO_PIN_B6 = 0x00004000U, /*!< Pin 14 selected */ + GPIO_PIN_B7 = 0x00008000U, /*!< Pin 15 selected */ + GPIO_PIN_C0 = 0x00010000U, /*!< Pin 16 selected */ + GPIO_PIN_C1 = 0x00020000U, /*!< Pin 17 selected */ + GPIO_PIN_C2 = 0x00040000U, /*!< Pin 18 selected */ + GPIO_PIN_C3 = 0x00080000U, /*!< Pin 19 selected */ + GPIO_PIN_C4 = 0x00100000U, /*!< Pin 20 selected */ + GPIO_PIN_C5 = 0x00200000U, /*!< Pin 21 selected */ + GPIO_PIN_C6 = 0x00400000U, /*!< Pin 22 selected */ + GPIO_PIN_C7 = 0x00800000U, /*!< Pin 23 selected */ + GPIO_PIN_D0 = 0x01000000U, /*!< Pin 24 selected */ + GPIO_PIN_D1 = 0x02000000U, /*!< Pin 25 selected */ + GPIO_PIN_D2 = 0x04000000U, /*!< Pin 26 selected */ + GPIO_PIN_D3 = 0x08000000U, /*!< Pin 27 selected */ + GPIO_PIN_D4 = 0x10000000U, /*!< Pin 28 selected */ + GPIO_PIN_D5 = 0x20000000U, /*!< Pin 29 selected */ + GPIO_PIN_D6 = 0x40000000U, /*!< Pin 30 selected */ + GPIO_PIN_D7 = 0x80000000U, /*!< Pin 31 selected */ +} ePINCTRL_GPIO_PINS; + +#define GPIO_PIN_ALL (0xFFFFFFFFU) /*!< All pins selected */ + +/** @} */ + +#define ROUTE_VAL(v, s, m) (((v) << (s)) | (m) << ((s) + 16)) + +/***************************** Structure Definition **************************/ + +struct PINCTRL_GRF_INFO { + uint16_t offset; + uint8_t bitsPerPin; + uint8_t pinsPerReg; +}; + +struct PINCTRL_MUX_RECAL_DATA { + uint32_t reg; + uint8_t bank; + uint8_t pin; + uint8_t bit; + uint8_t mask; +}; + +struct PINCTRL_MUX_ROUTE_DATA { + uint32_t routeReg; + uint32_t routeVal; + uint32_t pin; + uint8_t bank; + uint8_t func; +}; + +struct PINCTRL_BANK_INFO { + struct PINCTRL_GRF_INFO GRFInfo[GRF_INFO_NUM]; + uint32_t grfBase; + uint8_t pinCount; + uint8_t channel; +}; + +struct HAL_PINCTRL_DEV { + const struct PINCTRL_BANK_INFO *banks; + const struct PINCTRL_MUX_RECAL_DATA *muxRecalData; + const struct PINCTRL_MUX_ROUTE_DATA *muxRouteData; + uint8_t banksNum; + uint8_t muxRecalDataNum; + uint8_t muxRouteDataNum; +}; + +/** @brief Rockchip pinctrl device struct define + * Define a struct for pinctrl, including banks info, bank number, + * and grf info about iomux offset, iomux bit info, drive/pull/ + * slewrate/schmitt offset and bit info. + */ +extern const struct HAL_PINCTRL_DEV g_pinDev; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup PINCTRL_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_PINCTRL_Suspend(void); +HAL_Status HAL_PINCTRL_Resume(void); + +HAL_Status HAL_PINCTRL_Init(void); +HAL_Status HAL_PINCTRL_DeInit(void); + +HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param); +HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param); + +HAL_Status HAL_PINCTRL_IOFuncSelForCIF(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForEMMC(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForFLASH(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForFSPI(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForLCDC(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForMIPICSI(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForRGMII(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForGMAC0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForGMAC1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSDIO(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSDMMC0(eIOFUNC_SEL mode); + +HAL_Status HAL_PINCTRL_IOFuncSelForCAN0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2S0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2S1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2S2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM6(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM7(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM8(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM9(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM10(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM11(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART6(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART7(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART8(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART9(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART10(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART11(eIOFUNC_SEL mode); + +/** @} */ + +#endif /* __HAL_PINCTRL_H__ */ + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pl330.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pl330.h new file mode 100644 index 00000000000..91077d07a74 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pl330.h @@ -0,0 +1,249 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_PL330_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PL330 + * @{ + */ + +#ifndef _HAL_PL330_H +#define _HAL_PL330_H + +#include "hal_def.h" + +/** @defgroup PL330_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/***************************** MACRO Definition ******************************/ + +/** PL330 status */ +#define PL330_STATE_STOPPED HAL_BIT(0) +#define PL330_STATE_EXECUTING HAL_BIT(1) +#define PL330_STATE_WFE HAL_BIT(2) +#define PL330_STATE_FAULTING HAL_BIT(3) +#define PL330_STATE_COMPLETING HAL_BIT(4) +#define PL330_STATE_WFP HAL_BIT(5) +#define PL330_STATE_KILLING HAL_BIT(6) +#define PL330_STATE_FAULT_COMPLETE HAL_BIT(7) +#define PL330_STATE_CACHEMISS HAL_BIT(8) +#define PL330_STATE_UPDTPC HAL_BIT(9) +#define PL330_STATE_ATBARRIER HAL_BIT(10) +#define PL330_STATE_QUEUEBUSY HAL_BIT(11) +#define PL330_STATE_INVALID HAL_BIT(15) + +#define PL330_STABLE_STATES \ + (PL330_STATE_STOPPED | PL330_STATE_EXECUTING | PL330_STATE_WFE | \ + PL330_STATE_FAULTING) + +#define PL330_MAX_CHAN 8 +#define PL330_MAX_IRQS 32 +#define PL330_MAX_PERI 32 +#define PL330_MAX_BURST 16 + +/* + * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req + * at 1byte/burst for P<->M and M<->M respectively. + * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req + * should be enough for P<->M and M<->M respectively. + */ +#define MCODE_BUFF_PER_REQ 256 +#define PL330_MAX_CHAN_BUFS 2 +#define PL330_CHAN_BUF_LEN 128 +#define PL330_CHANNELS_PER_DEV 8 +#define PL330_NR_IRQS 2 + +/***************************** Structure Definition **************************/ + +/** enum PL330_CACHECTRL - pl330 cache control */ +typedef enum { + CCTRL0, /**< Noncacheable and nonbufferable */ + CCTRL1, /**< Bufferable only */ + CCTRL2, /**< Cacheable, but do not allocate */ + CCTRL3, /**< Cacheable and bufferable, but do not allocate */ + INVALID1, /**< AWCACHE = 0x1000 */ + INVALID2, + CCTRL6, /**< Cacheable write-through, allocate on writes only */ + CCTRL7, /**< Cacheable write-back, allocate on writes only */ +} ePL330_CACHECTRL; + +/** enum PL330_BYTESWAP - pl330 byte swap control */ +typedef enum { + SWAP_NO, + SWAP_2, + SWAP_4, + SWAP_8, + SWAP_16, +} ePL330_BYTESWAP; + +/** + * enum PL330_COND - dma transfer mode + */ +typedef enum { + SINGLE, + BURST, + ALWAYS, +} ePL330_COND; + +/** PL330 soc configuration */ +struct PL330_CONFIG { + uint32_t periphId; + uint32_t mode; + uint32_t dataBusWidth; /**< In number of bits */ + uint32_t dataBufDep; + uint32_t numChan; + uint32_t numPeri; + uint32_t periNs; + uint32_t numEvents; + uint32_t irqNs; +}; + +/** PL330 request config */ +struct PL330_REQCFG { + /* Address Incrementing */ + uint32_t dstInc; + uint32_t srcInc; + + /* + * For now, the SRC & DST protection levels + * and burst size/length are assumed same. + */ + bool nonsecure; + bool privileged; + bool insnaccess; + uint32_t brstLen; + uint32_t brstSize; /**< bytes */ + + ePL330_CACHECTRL dcctl; + ePL330_CACHECTRL scctl; + ePL330_BYTESWAP swap; +}; + +/** DMA block descriptor struct. */ +struct PL330_XFER { + uint32_t srcAddr; /**< Source starting address */ + uint32_t dstAddr; /**< Destination starting address */ + uint32_t length; /**< Number of bytes for the xfer */ +}; + +/** + * It's the done callback a user can set for a desc + */ +typedef void (*PL330_Callback)(void *cparam); + +/** + * A DMA Desc consisits of a request config struct, a xfer descriptor, + * a pointer pointing to generated DMA program, and execution result. + */ +struct PL330_DESC { + struct PL330_REQCFG rqcfg; + struct PL330_XFER px; + uint8_t peri; + eDMA_TRANSFER_DIRECTION dir; + bool cyclic; + uint32_t numPeriods; + uint32_t bytesReq; + uint16_t srcInterlaceSize; + uint16_t dstInterlaceSize; + void *mcBuf; + PL330_Callback callback; + void *cparam; +}; + +struct PL330_XFER_SPEC { + uint32_t ccr; + struct PL330_DESC *desc; +}; + +struct HAL_PL330_DEV; +/** + * The PL330_CHAN Data is a struct to book keep individual channel of + * the DMAC. + */ +struct PL330_CHAN { + uint16_t periId; + uint16_t chanId; + uint32_t fifoAddr; + uint32_t brstSz; + uint32_t brstLen; + uint16_t srcInterlaceSize; + uint16_t dstInterlaceSize; + struct PL330_DESC desc; + struct HAL_PL330_DEV *pl330; + void *mcBuf; + bool used; +}; + +/** + * The PL330 driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +struct HAL_PL330_DEV { + struct DMA_REG *pReg; + struct PL330_CHAN chans[PL330_CHANNELS_PER_DEV]; + struct PL330_CONFIG pcfg; + ePL330_COND peripReqType; + IRQn_Type irq[PL330_NR_IRQS]; + ePD_Id pd; + + void *priv; +}; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup PL330_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_PL330_Init(struct HAL_PL330_DEV *pl330); +HAL_Status HAL_PL330_DeInit(struct HAL_PL330_DEV *pl330); + +HAL_Status HAL_PL330_Start(struct PL330_CHAN *pchan); +HAL_Status HAL_PL330_Stop(struct PL330_CHAN *pchan); + +struct PL330_CHAN *HAL_PL330_RequestChannel(struct HAL_PL330_DEV *pl330, DMA_REQ_Type id); +HAL_Status HAL_PL330_ReleaseChannel(struct PL330_CHAN *pchan); + +HAL_Status HAL_PL330_Config(struct PL330_CHAN *pchan, struct DMA_SLAVE_CONFIG *config); +HAL_Status HAL_PL330_PrepDmaMemcpy(struct PL330_CHAN *pchan, uint32_t dst, + uint32_t src, uint32_t len, + PL330_Callback callback, void *cparam); +HAL_Status HAL_PL330_PrepDmaCyclic(struct PL330_CHAN *pchan, uint32_t dmaAddr, + uint32_t len, uint32_t periodLen, + eDMA_TRANSFER_DIRECTION direction, + PL330_Callback callback, void *cparam); +HAL_Status HAL_PL330_PrepDmaSingle(struct PL330_CHAN *pchan, uint32_t dmaAddr, + uint32_t len, + eDMA_TRANSFER_DIRECTION direction, + PL330_Callback callback, void *cparam); +int HAL_PL330_GetPosition(struct PL330_CHAN *pchan); + +uint32_t HAL_PL330_IrqHandler(struct HAL_PL330_DEV *pl330); +uint32_t HAL_PL330_GetRawIrqStatus(struct HAL_PL330_DEV *pl330); +HAL_Status HAL_PL330_ClearIrq(struct HAL_PL330_DEV *pl330, uint32_t irq); + +HAL_Status HAL_PL330_SetMcBuf(struct PL330_CHAN *pchan, void *buf); +void *HAL_PL330_GetMcBuf(struct PL330_CHAN *pchan); +const struct PL330_DESC *HAL_PL330_GetDesc(struct PL330_CHAN *pchan); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif +/* HAL_PL330_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pm.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pm.h new file mode 100644 index 00000000000..1bb6f4251fa --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pm.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PM + * @{ + */ + +#ifndef _HAL_PM_H_ +#define _HAL_PM_H_ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup DEMO_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define PM_RUNTIME_TYPE_MUTI_SFT (3) +#define PM_RUNTIME_PER_TYPE_NUM (8) + +#define PM_RUNTIME_TYPE_TO_FIRST_ID(type) ((type) << PM_RUNTIME_TYPE_MUTI_SFT) +#define PM_RUNTIME_ID_TO_TYPE(id) ((id) >> PM_RUNTIME_TYPE_MUTI_SFT) +#define PM_RUNTIME_ID_TO_TYPE_OFFSET(id) ((id) % PM_RUNTIME_PER_TYPE_NUM) +#define PM_RUNTIME_ID_TYPE_BIT_MSK(id) HAL_BIT(((id) % PM_RUNTIME_PER_TYPE_NUM)) + +#define PM_DISPLAY_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_DISPLAY]) +#define PM_UART_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_UART]) +#define PM_I2C_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_I2C]) +#define PM_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_INTF]) +#define PM_HS_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_HS_INTF]) +#define PM_SPI_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_SPI]) + +/* suspend config id */ +#define PM_SLEEP_MODE_CONFIG 0x01 +#define PM_SLEEP_WAKEUP_SOURCE 0x02 + +enum { + PM_RUNTIME_TYPE_INTF = 0, /**< normal interface */ + PM_RUNTIME_TYPE_DISPLAY, + PM_RUNTIME_TYPE_AUDIO, + PM_RUNTIME_TYPE_HS_INTF, /**< high speed interface */ + PM_RUNTIME_TYPE_STORAGE, + PM_RUNTIME_TYPE_UART, + PM_RUNTIME_TYPE_I2C, + PM_RUNTIME_TYPE_SPI, + PM_RUNTIME_TYPE_DEVICE, + PM_RUNTIME_TYPE_END, +}; + +typedef enum { + PM_RUNTIME_IDLE_ONLY = 0, + PM_RUNTIME_IDLE_NORMAL, + PM_RUNTIME_IDLE_DEEP, + PM_RUNTIME_IDLE_DEEP1, + PM_RUNTIME_IDLE_DEEP2, +} ePM_RUNTIME_idleMode; + +typedef enum { + PM_RUNTIME_ID_INTF_INVLD = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_INTF), /**< the id = 0, is means invalid */ + PM_RUNTIME_ID_SPI_APB, + PM_RUNTIME_ID_VOP = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_DISPLAY), + PM_RUNTIME_ID_MIPI, + + PM_RUNTIME_ID_I2S = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_AUDIO), + PM_RUNTIME_ID_I2S1, + PM_RUNTIME_ID_I2S2, + PM_RUNTIME_ID_ADC, + PM_RUNTIME_ID_DMA, + + PM_RUNTIME_ID_USB = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_HS_INTF), + PM_RUNTIME_ID_SDIO, + + PM_RUNTIME_ID_UART0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_UART), + PM_RUNTIME_ID_UART1, + PM_RUNTIME_ID_UART2, + + PM_RUNTIME_ID_I2C0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_I2C), + PM_RUNTIME_ID_I2C1, + PM_RUNTIME_ID_I2C2, + PM_RUNTIME_ID_I2C3, + PM_RUNTIME_ID_I2C4, + PM_RUNTIME_ID_I2C5, + + PM_RUNTIME_ID_SPI = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_SPI), + PM_RUNTIME_ID_END, +} ePM_RUNTIME_ID; + +/***************************** Structure Definition **************************/ +struct PM_RUNTIME_INFO { + uint8_t bits[PM_RUNTIME_TYPE_END]; +}; + +#ifdef HAL_PM_SLEEP_MODULE_ENABLED +struct PM_SUSPEND_INFO { + union { + struct { + uint32_t uartChannel : 4; /*!< bit: 0.. 3 uart debug channel num */ + uint32_t uartValid : 1; /*!< bit: 4 uart channel valid flag */ + uint32_t _reserved : 27; /*!< bit: 5..31 Reserved */ + } flag; + uint32_t suspendFlag; + }; +}; + +struct SLEEP_CONFIG_DATA { + uint32_t suspendMode; + uint32_t suspendWkupSrc; +}; +#endif + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup PM_Public_Function_Declare Public Function Declare + * @{ + */ +#ifdef HAL_PM_SLEEP_MODULE_ENABLED +/** + * @brief it is the enterpoint for suspend invoked by a os's powermanager implement. + * @param suspendInfo: suspend information for controlling + * @return HAL_Status + */ +int HAL_SYS_Suspend(struct PM_SUSPEND_INFO *suspendInfo); +struct SLEEP_CONFIG_DATA *HAL_SYS_GetSuspendConfig(void); +HAL_Status HAL_SYS_SuspendConfig(uint32_t id, uint32_t data); +#endif + +#ifdef HAL_PM_CPU_SLEEP_MODULE_ENABLED +void HAL_CPU_ArchSuspend(uint32_t *ptr); +void HAL_CPU_ArchResume(void); +void HAL_CPU_DoResume(void); + +void HAL_NVIC_SuspendSave(void); +void HAL_NVIC_ResumeRestore(void); + +void HAL_SCB_SuspendSave(void); +void HAL_SCB_ResumeRestore(void); + +int HAL_CPU_SuspendEnter(uint32_t flag, int (*suspend)(uint32_t)); +void HAL_CPU_SuspendSave(uint32_t *ptr, uint32_t ptrsz, uint32_t sp, uint32_t *ptrSave); +#endif + +#ifdef HAL_PM_RUNTIME_MODULE_ENABLED +HAL_Status HAL_PM_RuntimeRequest(ePM_RUNTIME_ID runtimeId); +HAL_Status HAL_PM_RuntimeRelease(ePM_RUNTIME_ID runtimeId); +const struct PM_RUNTIME_INFO *HAL_PM_RuntimeGetData(void); + +/** + * @brief it is for runtime power manager. + * @param idleMode: the soc pm mode will be config + * @return the mask bits indicate request source. + */ +uint32_t HAL_PM_RuntimeEnter(ePM_RUNTIME_idleMode idleMode); +#endif + +/** + * @brief it is for statting a pm timer . + * @param timeoutCount: the next timeout count + * @param needTimeout: if ture, need to start a timer. + * @return HAL_Status. + */ +HAL_Status HAL_PM_TimerStart(uint64_t timeoutCount, bool needTimeout); + +/** + * @brief it is for stopping a pm timer . + * @return HAL_Status. + */ +HAL_Status HAL_PM_TimerStop(void); + +/** + * @brief it is for getting the sleep time. + * @return the sleep time. + */ +uint64_t HAL_PM_GetTimerCount(void); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pwm.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pwm.h new file mode 100644 index 00000000000..d2cc75d8b9c --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pwm.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_PWM_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PWM + * @{ + */ + +#ifndef __HAL_PWM_H +#define __HAL_PWM_H + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup PWM_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define HAL_PWM_NUM_CHANNELS (HAL_ARRAY_SIZE(((struct PWM_REG *)0)->CHANNELS)) +#define PWM_PWRMATCH_MAX_COUNT (10) + +/***************************** Structure Definition **************************/ + +typedef enum { + HAL_PWM_ONE_SHOT = 0, + HAL_PWM_CONTINUOUS, + HAL_PWM_CAPTURE, +} ePWM_Mode; + +/** + * @brief PWM HW information definition + */ +struct HAL_PWM_DEV { + struct PWM_REG *pReg; + uint32_t clkID; + uint32_t clkGateID; + uint32_t pclkGateID; + IRQn_Type irqNum; +}; + +/** + * @brief PWM handle Structure definition + */ +struct HAL_PWM_CONFIG { + uint8_t channel; + uint32_t periodNS; + uint32_t dutyNS; + bool polarity; +}; + +/** + * @brief PWM capture data + */ +struct PWM_CAPTURE { + uint32_t period; + bool pol; + bool active; +}; + +/** + * @brief PWM match data + */ +struct PWM_MATCH { + uint32_t match[PWM_PWRMATCH_MAX_COUNT]; + uint8_t matchCount; + uint16_t lpreMin; + uint16_t lpreMax; + uint16_t hpreMin; + uint16_t hpreMax; + uint16_t ldMin; + uint16_t ldMax; + uint16_t hdZeroMin; + uint16_t hdZeroMax; + uint16_t hdOneMin; + uint16_t hdOneMax; +}; + +/** + * @brief PWM Handle Structure definition + */ + +struct PWM_HANDLE { + struct PWM_REG *pReg; + uint32_t freq; + ePWM_Mode mode[HAL_PWM_NUM_CHANNELS]; + struct PWM_CAPTURE result[HAL_PWM_NUM_CHANNELS]; +}; + +/** + * @} + */ + +/***************************** Function Declare ******************************/ +/** @defgroup PWM_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_PWM_IRQHandler(struct PWM_HANDLE *pPWM); +HAL_Status HAL_PWM_SetConfig(struct PWM_HANDLE *pPWM, uint8_t channel, + const struct HAL_PWM_CONFIG *config); +HAL_Status HAL_PWM_SetOneshot(struct PWM_HANDLE *pPWM, uint8_t channel, uint32_t count); +HAL_Status HAL_PWM_SetCapturedFreq(struct PWM_HANDLE *pPWM, uint8_t channel, uint32_t freq); +HAL_Status HAL_PWM_SetMatch(struct PWM_HANDLE *pPWM, uint8_t channel, const struct PWM_MATCH *data); +ePWM_Mode HAL_PWM_GetMode(struct PWM_HANDLE *pPWM, uint8_t channel); +HAL_Status HAL_PWM_Enable(struct PWM_HANDLE *pPWM, uint8_t channel, ePWM_Mode mode); +HAL_Status HAL_PWM_Disable(struct PWM_HANDLE *pPWM, uint8_t channel); +HAL_Status HAL_PWM_Init(struct PWM_HANDLE *pPWM, struct PWM_REG *pReg, uint32_t freq); +HAL_Status HAL_PWM_DeInit(struct PWM_HANDLE *pPWM); + +/** @} */ + +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWM_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pwr.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pwr.h new file mode 100644 index 00000000000..5c8ff522b70 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_pwr.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +#ifndef _HAL_PWR_H_ +#define _HAL_PWR_H_ + +#include "hal_def.h" + +/** @defgroup PWR_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/***************************** MACRO Definition ******************************/ + +typedef enum { + PWR_ID_NULL = 0, + PWR_ID_CORE, + PWR_ID_LOG, + PWR_ID_DSP_CORE, + PWR_ID_VCC_MIPI, + PWR_ID_VCC_AUDIO, + PWR_ID_DSP_VCC_MIPI, + PWR_ID_MEMORY, /**< for share memory and sram */ + PWR_ID_TOP, + PWR_ID_BUCK_1V8, /**< Usually as a transition between high and low voltage */ + PWR_ID_VCCIO_3V3, + PWR_ID_VDD_1V1, + PWR_ID_VCCIO_1V8, + PWR_ID_VCCIO_1V8_PMU, + PWR_ID_VCC_3V0_BL, + PWR_ID_VCC_1V8_BUCK, + PWR_ID_VCC_1V8_LDO, + PWR_ID_VCC33_CODEC, + PWR_ID_VCC33_AUDIO, + PWR_ID_VCC1, + PWR_ID_VLDO3, + PWR_ID_VLDO6, + PWR_ID_MAX, +} ePWR_ID; + +typedef enum { + PWR_CTRL_VOLT_RUN = 0, /**< run mode voltage */ + PWR_CTRL_VOLT_SSPD, /**< suspend mode voltage */ + PWR_CTRL_PWR_EN, /**< enable a regulator */ + PWR_CTRL_PWR_SSPD, /**< suspend mode enable a regulator */ + PWR_CTRL_VOLT_ST, /**< get a regulator state */ + PWR_CTRL_MAX +} ePWR_CtrlType; + +#define PWR_FLG_VOLT_RUN HAL_BIT(PWR_CTRL_VOLT_RUN) +#define PWR_FLG_VOLT_SSPD HAL_BIT(PWR_CTRL_VOLT_SSPD) +#define PWR_FLG_PWR_EN HAL_BIT(PWR_CTRL_PWR_EN) +#define PWR_FLG_PWR_SSPD HAL_BIT(PWR_CTRL_PWR_SSPD) +#define PWR_FLG_VOLT_ST HAL_BIT(PWR_CTRL_VOLT_ST) +#define PWR_FLG_LINEAR HAL_BIT(PWR_CTRL_MAX) +#define PWR_FLG_FIXED (PWR_FLG_LINEAR << 1) +#define PWR_FLG_ALWAYSON (PWR_FLG_FIXED << 1) +#define PWR_FLG_ENMASK (PWR_FLG_ALWAYSON << 1) + +#define DESC_FLAG_LINEAR(flag) (PWR_FLG_LINEAR | PWR_FLG_VOLT_RUN | (flag)) +#define DESC_FLAG_N_LINEAR(flag) (PWR_FLG_VOLT_RUN | (flag)) + +#define PWR_INTREG_SHIFT_RUN(reg, sft) \ + .preg[PWR_CTRL_VOLT_RUN] = (uint32_t *)(reg), \ + .shift[PWR_CTRL_VOLT_RUN] = (sft) + +#define PWR_INTREG_SHIFT_SSPD(reg, sft) \ + .preg[PWR_CTRL_VOLT_SSPD] = (uint32_t *)(reg), \ + .shift[PWR_CTRL_VOLT_SSPD] = (sft) + +#define PWR_INTREG_SHIFT_EN(reg, sft) \ + .preg[PWR_CTRL_PWR_EN] = (uint32_t *)(reg), \ + .shift[PWR_CTRL_PWR_EN] = (sft) + +#define PWR_INTREG_SHIFT_ST(reg, sft) \ + .preg[PWR_CTRL_VOLT_ST] = (uint32_t *)(reg), \ + .shift[PWR_CTRL_VOLT_ST] = (sft) + +#define PWR_DESC_LINEAR_VOLT(min, max, step) \ + .voltCnt = (((max)-(min))/(step)) + 1, \ + .minVolt = (min), \ + .volt_list = { \ + .stepVolt = (step) \ + } + +#define POWER_LINEAR_RANGE(_minUV, _minSel, _maxSel, _stepUV) \ +{ \ + .minUV = _minUV, \ + .minSel = _minSel, \ + .maxSel = _maxSel, \ + .uVStep = _stepUV, \ +} + +/***************************** Structure Definition **************************/ +struct PWR_LINEAR_RANGE { + unsigned int minUV; + unsigned int minSel; + unsigned int maxSel; + unsigned int uVStep; +}; + +struct PWR_LINEAR_RANGE_TABLE { + int nEntry; + struct PWR_LINEAR_RANGE *entry; +}; + +union U_PWR_VOLT_LIST { + int stepVolt; + const uint32_t *voltTable; + struct PWR_LINEAR_RANGE_TABLE linearTables; +}; + +struct PWR_CTRL_INFO { + uint16_t pwrId : 8; + uint16_t enCnt : 4; +}; + +struct PWR_INTREG_DESC { + struct PWR_CTRL_INFO info; + uint16_t flag; + uint8_t voltMask; + uint8_t voltCnt; + __IO uint32_t *preg[PWR_CTRL_MAX]; + uint8_t shift[PWR_CTRL_MAX]; + uint32_t minVolt; + union U_PWR_VOLT_LIST volt_list; +}; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup PWR_Public_Function_Declare Public Function Declare + * @{ + */ +#ifdef HAL_PWR_INTBUS_MODULE_ENABLED +int HAL_PWR_GetEnableState(struct PWR_INTREG_DESC *desc); +uint32_t HAL_PWR_GetVoltage(struct PWR_INTREG_DESC *desc); +uint32_t HAL_PWR_GetVoltageSuspend(struct PWR_INTREG_DESC *desc); +uint32_t HAL_PWR_GetVoltageReal(struct PWR_INTREG_DESC *desc); +HAL_Status HAL_PWR_SetVoltage(struct PWR_INTREG_DESC *desc, uint32_t volt); +HAL_Status HAL_PWR_SetVoltageSuspend(struct PWR_INTREG_DESC *desc, uint32_t volt); +HAL_Status HAL_PWR_Enable(struct PWR_INTREG_DESC *desc); +HAL_Status HAL_PWR_Disable(struct PWR_INTREG_DESC *desc); +HAL_Check HAL_PWR_CheckDescByPwrId(struct PWR_INTREG_DESC *pdesc, + ePWR_ID pwrId); +uint32_t HAL_PWR_RoundVoltage(struct PWR_INTREG_DESC *desc, uint32_t volt); +#endif + +int HAL_PWR_LinearRangeSelToVolt(const struct PWR_LINEAR_RANGE_TABLE *linearTables, uint32_t sel); +int HAL_PWR_LinearRangeVoltToSel(const struct PWR_LINEAR_RANGE_TABLE *linearTables, uint32_t volt); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_systick.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_systick.h new file mode 100644 index 00000000000..b89d97eb023 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_systick.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_SYSTICK_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup SYSTICK + * @{ + */ + +#ifndef _HAL_SYSTICK_H_ +#define _HAL_SYSTICK_H_ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup SYSTICK_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup SYSTICK_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_SYSTICK_Init(void); +HAL_Status HAL_SYSTICK_Config(uint32_t ticksNumb); +HAL_Status HAL_SYSTICK_CLKSourceConfig(eHAL_systickClkSource clkSource); +HAL_Check HAL_SYSTICK_IsExtRefClockEnabled(void); +void HAL_SYSTICK_IRQHandler(void); +HAL_Status HAL_SYSTICK_Enable(void); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_SYSTICK_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_timer.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_timer.h new file mode 100644 index 00000000000..0f815b9412a --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_timer.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_TIMER_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +#ifndef _HAL_TIMER_H_ +#define _HAL_TIMER_H_ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ + +/** @defgroup TIMER_Exported_Definition_Group1 Basic Definition + * @{ + */ + +typedef enum { + TIMER_FREE_RUNNING = 0, + TIMER_USER_DEFINED, + TIMER_MODE_MAX +} eTIMER_MODE; + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup TIMER_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t usTick); +uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER0_Handler(void); +HAL_Status HAL_TIMER1_Handler(void); +HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode); +HAL_Status HAL_TIMER_SysTimerInit(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_TIMER_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_uart.h b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_uart.h new file mode 100644 index 00000000000..bcfdc660a9e --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/inc/hal_uart.h @@ -0,0 +1,276 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_UART_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +#ifndef _HAL_UART_H_ +#define _HAL_UART_H_ + +#include "hal_def.h" +#include "hal_base.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup UART_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/* Out: Interrupt Enable Register */ +#define UART_IER_PTIME 0x80 /**< Enable Programmable THRE Interrupt Mode */ +#define UART_IER_MSI 0x08 /**< Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /**< Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /**< Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /**< Enable receiver data interrupt */ + +/* In: Interrupt ID Register */ +#define UART_IIR_MASK 0x0f /**< Interrupt ID Mask */ +#define UART_IIR_NO_INT 0x01 /**< No interrupts pending */ +#define UART_IIR_ID 0x0e /**< Mask for the interrupt ID */ +#define UART_IIR_MSI 0x00 /**< Modem status interrupt */ +#define UART_IIR_THRI 0x02 /**< Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /**< Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /**< Receiver line status interrupt */ +#define UART_IIR_BUSY 0x07 /**< DesignWare APB Busy Detect */ +#define UART_IIR_RX_TIMEOUT 0x0c /**< RX Timeout interrupt */ + +/* Out: FIFO Control Register */ +#define UART_FCR_ENABLE_FIFO 0x01 /**< Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /**< Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /**< Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /**< For DMA applications */ + +#define UART_FCR_R_TRIG_00 0x00 +#define UART_FCR_R_TRIG_01 0x40 +#define UART_FCR_R_TRIG_10 0x80 +#define UART_FCR_R_TRIG_11 0xc0 +#define UART_FCR_T_TRIG_00 0x00 +#define UART_FCR_T_TRIG_01 0x10 +#define UART_FCR_T_TRIG_10 0x20 +#define UART_FCR_T_TRIG_11 0x30 + +#define UART_FCR_TRIGGER_MASK 0xC0 /**< Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /**< Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /**< Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /**< Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /**< Mask for trigger set at 14 */ +/* 16650 definitions */ +#define UART_FCR6_R_TRIGGER_8 0x00 /**< Mask for receive trigger set at 1 */ +#define UART_FCR6_R_TRIGGER_16 0x40 /**< Mask for receive trigger set at 4 */ +#define UART_FCR6_R_TRIGGER_24 0x80 /**< Mask for receive trigger set at 8 */ +#define UART_FCR6_R_TRIGGER_28 0xC0 /**< Mask for receive trigger set at 14 */ +#define UART_FCR6_T_TRIGGER_16 0x00 /**< Mask for transmit trigger set at 16 */ +#define UART_FCR6_T_TRIGGER_8 0x10 /**< Mask for transmit trigger set at 8 */ +#define UART_FCR6_T_TRIGGER_24 0x20 /**< Mask for transmit trigger set at 24 */ +#define UART_FCR6_T_TRIGGER_30 0x30 /**< Mask for transmit trigger set at 30 */ +#define UART_FCR7_64BYTE 0x20 +/* Go into 64 byte mode (TI16C750 and some Freescale UARTs) */ + +#define UART_FCR_R_TRIG_SHIFT 6 +#define UART_FCR_R_TRIG_BITS(x) (((x)&UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT) +#define UART_FCR_R_TRIG_MAX_STATE 4 + +/* Out: Line Control Register */ +/* + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /**< Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /**< Set break control */ +#define UART_LCR_SPAR 0x20 /**< Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /**< Even parity select */ +#define UART_LCR_PARITY 0x08 /**< Parity Enable */ +#define UART_LCR_STOP 0x04 /**< Stop bits: 0=1 bit, 1=2 bits */ +#define UART_LCR_WLEN5 0x00 /**< Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /**< Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /**< Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /**< Wordlength: 8 bits */ + +/* Out: Modem Control Register */ +#define UART_MCR_CLKSEL 0x80 /**< Divide clock by 4 (TI16C752, EFR[4]=1) */ +#define UART_MCR_TCRTLR 0x40 /**< Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_XONANY 0x20 /**< Enable Xon Any (TI16C752, EFR[4]=1) */ +#define UART_MCR_AFE 0x20 /**< Enable auto-RTS/CTS (TI16C550C/TI16C750) */ +#define UART_MCR_LOOP 0x10 /**< Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /**< Out2 complement */ +#define UART_MCR_OUT1 0x04 /**< Out1 complement */ +#define UART_MCR_RTS 0x02 /**< RTS complement */ +#define UART_MCR_DTR 0x01 /**< DTR complement */ + +/* In: Line Status Register */ +#define UART_LSR_FIFOE 0x80 /**< Fifo error */ +#define UART_LSR_TEMT 0x40 /**< Transmitter empty */ +#define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /**< Break interrupt indicator */ +#define UART_LSR_FE 0x08 /**< Frame error indicator */ +#define UART_LSR_PE 0x04 /**< Parity error indicator */ +#define UART_LSR_OE 0x02 /**< Overrun error indicator */ +#define UART_LSR_DR 0x01 /**< Receiver data ready */ +#define UART_LSR_BRK_ERROR_BITS 0x1E /**< BI, FE, PE, OE bits */ + +/* In: Modem Status Register */ +#define UART_MSR_DCD 0x80 /**< Data Carrier Detect */ +#define UART_MSR_RI 0x40 /**< Ring Indicator */ +#define UART_MSR_DSR 0x20 /**< Data Set Ready */ +#define UART_MSR_CTS 0x10 /**< Clear to Send */ +#define UART_MSR_DDCD 0x08 /**< Delta DCD */ +#define UART_MSR_TERI 0x04 /**< Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /**< Delta DSR */ +#define UART_MSR_DCTS 0x01 /**< Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /**< Any of the delta bits! */ + +#define UART_USR_RX_FIFO_FULL 0x10 /**< Receive FIFO full */ +#define UART_USR_RX_FIFO_NOT_EMPTY 0x08 /**< Receive FIFO not empty */ +#define UART_USR_TX_FIFO_EMPTY 0x04 /**< Transmit FIFO empty */ +#define UART_USR_TX_FIFO_NOT_FULL 0x02 /**< Transmit FIFO not full */ +#define UART_USR_BUSY 0x01 /**< UART busy indicator */ + +#define UART_SRR_UR 0x1 /**< UART Reset */ +#define UART_SRR_RFR 0X2 /**< RCVR FIFO Reset */ +#define UART_SRR_XFR 0x4 /**< XMIT FIFO Reset */ + +#define MODE_X_DIV 16 /**< baud = f / 16 / div */ + +/***************************** Structure Definition **************************/ + +/** + * @brief UART baud rate definition + */ +typedef enum { + UART_BR_110 = 110, + UART_BR_300 = 300, + UART_BR_600 = 600, + UART_BR_1200 = 1200, + UART_BR_2400 = 2400, + UART_BR_4800 = 4800, + UART_BR_9600 = 9600, + UART_BR_14400 = 14400, + UART_BR_19200 = 19200, + UART_BR_38400 = 38400, + UART_BR_57600 = 57600, + UART_BR_115200 = 115200, + UART_BR_230400 = 230400, + UART_BR_380400 = 380400, + UART_BR_460800 = 460800, + UART_BR_921600 = 921600, + UART_BR_1000000 = 1000000, + UART_BR_1500000 = 1500000, + UART_BR_2000000 = 2000000, + UART_BR_3000000 = 3000000, + UART_BR_4000000 = 4000000, +} eUART_baudRate; + +/** + * @brief UART data bit definition + */ +typedef enum { + UART_DATA_5B = 5, + UART_DATA_6B, + UART_DATA_7B, + UART_DATA_8B +} eUART_dataLen; + +/** + * @brief UART stop bit definition + */ +typedef enum { + UART_ONE_STOPBIT, + UART_ONE_AND_HALF_OR_TWO_STOPBIT +} eUART_stopBit; + +/** + * @brief UART parity definition + */ +typedef enum { + UART_ODD_PARITY, + UART_EVEN_PARITY, + UART_PARITY_DISABLE +} eUART_parityEn; + +/** + * @brief UART config definition + */ +struct HAL_UART_CONFIG { + eUART_baudRate baudRate; + eUART_dataLen dataBit; + eUART_stopBit stopBit; + eUART_parityEn parity; +}; + +/** + * @brief UART HW information definition on a soc + */ +struct HAL_UART_DEV { + struct UART_REG *pReg; /**< registers base address */ + + /* sclk is for uart logic, pclk is for register access */ + eCLOCK_Name sclkID; + uint32_t sclkGateID; + uint32_t pclkGateID; + + IRQn_Type irqNum; + bool isAutoFlow; + ePM_RUNTIME_ID runtimeID; + DMA_REQ_Type dmaTxReqNum; /**< peri dma tx request num */ + DMA_REQ_Type dmaRxReqNum; /**< peri dma rx request num */ + struct DMA_REG *dmac; /**< dmac reg base ptr */ +}; + +/** + * @brief Save UART regist + */ +struct UART_SAVE_CONFIG { + uint32_t DLL; + uint32_t DLH; + uint32_t IER; + uint32_t LCR; + uint32_t MCR; + uint32_t SRT; + uint32_t STET; +}; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup UART_Public_Function_Declare Public Function Declare + * @{ + */ +void HAL_UART_EnableIrq(struct UART_REG *pReg, uint32_t uartIntNumb); +void HAL_UART_DisableIrq(struct UART_REG *pReg, uint32_t uartIntNumb); +void HAL_UART_EnableLoopback(struct UART_REG *pReg); +void HAL_UART_DisableLoopback(struct UART_REG *pReg); +void HAL_UART_EnableAutoFlowControl(struct UART_REG *pReg); +void HAL_UART_DisableAutoFlowControl(struct UART_REG *pReg); +uint32_t HAL_UART_GetIrqID(struct UART_REG *pReg); +uint32_t HAL_UART_GetLsr(struct UART_REG *pReg); +uint32_t HAL_UART_GetUsr(struct UART_REG *pReg); +uint32_t HAL_UART_GetMsr(struct UART_REG *pReg); +void HAL_UART_SerialOutChar(struct UART_REG *pReg, char c); +int HAL_UART_SerialOut(struct UART_REG *pReg, const uint8_t *pdata, uint32_t cnt); +int HAL_UART_SerialIn(struct UART_REG *pReg, uint8_t *pdata, uint32_t cnt); +HAL_Status HAL_UART_HandleIrq(struct UART_REG *pReg); +void HAL_UART_Reset(struct UART_REG *pReg); +HAL_Status HAL_UART_Init(const struct HAL_UART_DEV *dev, const struct HAL_UART_CONFIG *config); +HAL_Status HAL_UART_DeInit(struct UART_REG *pReg); +HAL_Status HAL_UART_Suspend(struct UART_REG *pReg, struct UART_SAVE_CONFIG *pUartSave); +HAL_Status HAL_UART_Resume(struct UART_REG *pReg, struct UART_SAVE_CONFIG *pUartSave); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_UART_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/cru/hal_cru.c b/bsp/rockchip/common/rk_hal/lib/hal/src/cru/hal_cru.c new file mode 100644 index 00000000000..5cb6a39d76f --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/cru/hal_cru.c @@ -0,0 +1,1022 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_CRU_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +/** @defgroup CRU_How_To_Use How To Use + * @{ + + The CRU driver can be used as follows: + + - Invoke cru functions to set clk rate, enable or disable clk, reset clk in each device. + - The gate and soft reset id is include register offset and shift information: + + con_offset: id /16 + shift: id %16 + + - The mux and div id is include register offset, shift, mask information: + + [15:0]: con + [23:16]: shift + [31:24]: width + + - CRU driver is just responsible for passing simple command data, And + the usecount is the user's responsibility. Protection the usecount at the driver layer. + - More details refer to APIs' descriptions as below. + + @} */ + +/** @defgroup CRU_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#if defined(SOC_RV1108) +#define PWRDOWN_SHIT 0 +#define PWRDOWN_MASK 1 << PWRDOWN_SHIT +#define PLL_POSTDIV1_SHIFT 8 +#define PLL_POSTDIV1_MASK 0x7 << PLL_POSTDIV1_SHIFT +#define PLL_FBDIV_SHIFT 0 +#define PLL_FBDIV_MASK 0xfff << PLL_FBDIV_SHIFT +#define PLL_POSTDIV2_SHIFT 12 +#define PLL_POSTDIV2_MASK 0x7 << PLL_POSTDIV2_SHIFT +#define PLL_REFDIV_SHIFT 0 +#define PLL_REFDIV_MASK 0x3f << PLL_REFDIV_SHIFT +#define PLL_DSMPD_SHIFT 3 +#define PLL_DSMPD_MASK 1 << PLL_DSMPD_SHIFT +#define PLL_FRAC_SHIFT 0 +#define PLL_FRAC_MASK 0xffffff << PLL_FRAC_SHIFT +#else +#define PWRDOWN_SHIT 13 +#define PWRDOWN_MASK 1 << PWRDOWN_SHIT +#define PLL_POSTDIV1_SHIFT 12 +#define PLL_POSTDIV1_MASK 0x7 << PLL_POSTDIV1_SHIFT +#define PLL_FBDIV_SHIFT 0 +#define PLL_FBDIV_MASK 0xfff << PLL_FBDIV_SHIFT +#define PLL_POSTDIV2_SHIFT 6 +#define PLL_POSTDIV2_MASK 0x7 << PLL_POSTDIV2_SHIFT +#define PLL_REFDIV_SHIFT 0 +#define PLL_REFDIV_MASK 0x3f << PLL_REFDIV_SHIFT +#define PLL_DSMPD_SHIFT 12 +#define PLL_DSMPD_MASK 1 << PLL_DSMPD_SHIFT +#define PLL_FRAC_SHIFT 0 +#define PLL_FRAC_MASK 0xffffff << PLL_FRAC_SHIFT +#endif + +#define MIN_FOUTVCO_FREQ (800 * MHZ) +#define MAX_FOUTVCO_FREQ (2000 * MHZ) +#define MIN_FOUT_FREQ (24 * MHZ) +#define MAX_FOUT_FREQ (1400 * MHZ) + +#define EXPONENT_OF_FRAC_PLL 24 +#define RK_PLL_MODE_SLOW 0 +#define RK_PLL_MODE_NORMAL 1 +#define RK_PLL_MODE_DEEP 2 +#define PLL_GET_PLLMODE(val, shift, mask) (((uint32_t)(val) & mask) >> shift) + +#define PLL_GET_FBDIV(x) (((uint32_t)(x) & (PLL_FBDIV_MASK)) >> PLL_FBDIV_SHIFT) +#define PLL_GET_REFDIV(x) \ + (((uint32_t)(x) & (PLL_REFDIV_MASK)) >> PLL_REFDIV_SHIFT) +#define PLL_GET_POSTDIV1(x) \ + (((uint32_t)(x) & (PLL_POSTDIV1_MASK)) >> PLL_POSTDIV1_SHIFT) +#define PLL_GET_POSTDIV2(x) \ + (((uint32_t)(x) & (PLL_POSTDIV2_MASK)) >> PLL_POSTDIV2_SHIFT) +#define PLL_GET_DSMPD(x) (((uint32_t)(x) & (PLL_DSMPD_MASK)) >> PLL_DSMPD_SHIFT) +#define PLL_GET_FRAC(x) (((uint32_t)(x) & (PLL_FRAC_MASK)) >> PLL_FRAC_SHIFT) + +#define CRU_PLL_ROUND_UP_TO_KHZ(x) (HAL_DIV_ROUND_UP((x), KHZ) * KHZ) + +/********************* Private Structure Definition **************************/ +static struct PLL_CONFIG g_rockchipAutoTable; + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** Calculate the greatest common divisor */ +static uint32_t CRU_Gcd(uint32_t m, uint32_t n) +{ + int t; + + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } + m -= n; + } + + return n; +} + +/** + * @brief Rockchip pll clk set postdiv. + * @param foutHz: output freq + * @param *postDiv1: pll postDiv1 + * @param *postDiv2: pll postDiv2 + * @param *foutVco: pll vco + * @return HAL_Status. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = fractional PLL non-divided output frequency + * FOUTPOSTDIV = fractional PLL divided output frequency + * (output of second post divider) + */ +static HAL_Status CRU_PllSetPostDiv(uint32_t foutHz, uint32_t *postDiv1, + uint32_t *postDiv2, uint32_t *foutVco) +{ + uint32_t freq; + + if (foutHz < MIN_FOUTVCO_FREQ) { + for (*postDiv1 = 1; *postDiv1 <= 7; (*postDiv1)++) { + for (*postDiv2 = 1; *postDiv2 <= 7; (*postDiv2)++) { + freq = foutHz * (*postDiv1) * (*postDiv2); + if (freq >= MIN_FOUTVCO_FREQ && freq <= MAX_FOUTVCO_FREQ) { + *foutVco = freq; + + return HAL_OK; + } + } + } + + return HAL_ERROR; + } else { + *postDiv1 = 1; + *postDiv2 = 1; + + return HAL_OK; + } +} + +/** + * @brief Get pll parameter by auto. + * @param finHz: pll intput freq + * @param foutHz: pll output freq + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = fractional PLL non-divided output frequency + * FOUTPOSTDIV = fractional PLL divided output frequency + * (output of second post divider) + * FREF = fractional PLL input reference frequency, (the OSC_HZ 24MHz input) + * REFDIV = fractional PLL input reference clock divider + * FBDIV = Integer value programmed into feedback divide + */ +static const struct PLL_CONFIG *CRU_PllSetByAuto(uint32_t finHz, + uint32_t foutHz) +{ + struct PLL_CONFIG *rateTable = &g_rockchipAutoTable; + uint32_t foutVco = foutHz; + uint64_t fin64, frac64; + uint32_t postDiv1, postDiv2; + uint32_t clkGcd = 0; + HAL_Status error; + + if (finHz == 0 || foutHz == 0 || foutHz == finHz) { + return NULL; + } + + error = CRU_PllSetPostDiv(foutHz, &postDiv1, &postDiv2, &foutVco); + if (error) { + return NULL; + } + rateTable->postDiv1 = postDiv1; + rateTable->postDiv2 = postDiv2; + rateTable->dsmpd = 1; + + if (finHz / MHZ * MHZ == finHz && foutHz / MHZ * MHZ == foutHz) { + finHz /= MHZ; + foutVco /= MHZ; + clkGcd = CRU_Gcd(finHz, foutVco); + rateTable->refDiv = finHz / clkGcd; + rateTable->fbDiv = foutVco / clkGcd; + + rateTable->frac = 0; + } else if (finHz / MHZ * MHZ != finHz) { + clkGcd = foutHz / finHz; + rateTable->fbDiv = clkGcd; + rateTable->refDiv = 1; + rateTable->postDiv1 = 1; + rateTable->postDiv2 = 1; + + fin64 = foutHz * rateTable->refDiv; + fin64 = HAL_DivU64(fin64 << EXPONENT_OF_FRAC_PLL, finHz); + frac64 = rateTable->fbDiv; + frac64 = rateTable->fbDiv << EXPONENT_OF_FRAC_PLL; + frac64 = fin64 - frac64; + rateTable->frac = frac64; + if (rateTable->frac > 0) { + rateTable->dsmpd = 0; + } + } else { + clkGcd = CRU_Gcd(finHz / MHZ, foutVco / MHZ); + rateTable->refDiv = finHz / MHZ / clkGcd; + rateTable->fbDiv = foutVco / MHZ / clkGcd; + rateTable->frac = 0; + + frac64 = (foutVco % MHZ); + fin64 = finHz; + frac64 = frac64 * rateTable->refDiv; + frac64 = HAL_DivU64(frac64 << EXPONENT_OF_FRAC_PLL, fin64); + rateTable->frac = frac64; + if (rateTable->frac > 0) { + rateTable->dsmpd = 0; + } + } + + return rateTable; +} + +/** + * @brief Get pll parameter by rateTable. + * @param *pSetup: struct PLL_SETUP struct, Contains PLL register parameters + * @param rate: pll target rate. + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * Look up the rateTable to get the PLL config parameter + */ +static const struct PLL_CONFIG *CRU_PllGetSettings(struct PLL_SETUP *pSetup, + uint32_t rate) +{ + const struct PLL_CONFIG *rateTable = pSetup->rateTable; + + if (rateTable == NULL) { + return CRU_PllSetByAuto(PLL_INPUT_OSC_RATE, rate); + } + + while (rateTable->rate) { + if (rateTable->rate == rate) { + break; + } + rateTable++; + } + if (rateTable->rate != rate) { + return CRU_PllSetByAuto(PLL_INPUT_OSC_RATE, rate); + } else { + return rateTable; + } +} +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup CRU_Exported_Functions_Group5 Other Functions + * @attention these APIs allow direct use in the HAL layer. + * @{ + */ + +#if defined(SOC_RV1108) +/** + * @brief Get pll freq. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @return pll rate. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + * If DSMPD = 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / REFDIV) * (FBDIV + FRAC / (2^24)) + * FOUTPOSTDIV = FOUTVCO / (POSTDIV1*POSTDIV2) + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd; + uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE; + + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + case RK_PLL_MODE_NORMAL: + fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0))); + postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset1))); + postDiv2 = PLL_GET_POSTDIV2(READ_REG(*(pSetup->conOffset1))); + refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1))); + dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset3))); + frac = PLL_GET_FRAC(READ_REG(*(pSetup->conOffset2))); + rate = (rate / refDiv) * fbDiv; + if (dsmpd == 0) { + uint64_t fracRate = PLL_INPUT_OSC_RATE; + + fracRate *= frac; + fracRate = fracRate >> EXPONENT_OF_FRAC_PLL; + fracRate = fracRate / refDiv; + rate += fracRate; + } + rate = rate / (postdDv1 * postDiv2); + rate = CRU_PLL_ROUND_UP_TO_KHZ(rate); + break; + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/** + * @brief Set pll freq. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @param rate: pll set rate + * @return HAL_Status. + * How to calculate the PLL: + * Force PLL into slow mode + * Pll Power down + * Pll Config fbDiv, refDiv, postdDv1, postDiv2, dsmpd, frac + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 2400; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 1 << PWRDOWN_SHIT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV2_MASK, pConfig->postDiv2 << PLL_POSTDIV2_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_REFDIV_MASK, pConfig->refDiv << PLL_REFDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV1_MASK, pConfig->postDiv1 << PLL_POSTDIV1_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PLL_DSMPD_MASK, pConfig->dsmpd << PLL_DSMPD_SHIFT); + + if (pConfig->frac) { + WRITE_REG(*(pSetup->conOffset2), (READ_REG(*(pSetup->conOffset2)) & 0xff000000) | pConfig->frac); + } + + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset2)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + + return HAL_OK; +} + +/** + * @brief Set pll power up. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset2)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Set pll power down. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 1 << PWRDOWN_SHIT); + + return HAL_OK; +} +#else +/** + * @brief Get pll freq. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @return pll rate. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + * If DSMPD = 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / REFDIV) * (FBDIV + FRAC / (2^24)) + * FOUTPOSTDIV = FOUTVCO / (POSTDIV1*POSTDIV2) + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd; + uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE; + + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + case RK_PLL_MODE_NORMAL: + postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset0))); + fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0))); + postDiv2 = PLL_GET_POSTDIV2(READ_REG(*(pSetup->conOffset1))); + refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1))); + dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset1))); + frac = PLL_GET_FRAC(READ_REG(*(pSetup->conOffset2))); + rate = (rate / refDiv) * fbDiv; + if (dsmpd == 0) { + uint64_t fracRate = PLL_INPUT_OSC_RATE; + + fracRate *= frac; + fracRate = fracRate >> EXPONENT_OF_FRAC_PLL; + fracRate = fracRate / refDiv; + rate += fracRate; + } + rate = rate / (postdDv1 * postDiv2); + rate = CRU_PLL_ROUND_UP_TO_KHZ(rate); + break; + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/** + * @brief Set pll freq. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @param rate: pll set rate + * @return HAL_Status. + * How to calculate the PLL: + * Force PLL into slow mode + * Pll Power down + * Pll Config fbDiv, refDiv, postdDv1, postDiv2, dsmpd, frac + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 2400; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV2_MASK, pConfig->postDiv2 << PLL_POSTDIV2_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_REFDIV_MASK, pConfig->refDiv << PLL_REFDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_POSTDIV1_MASK, pConfig->postDiv1 << PLL_POSTDIV1_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_DSMPD_MASK, pConfig->dsmpd << PLL_DSMPD_SHIFT); + + if (pConfig->frac) { + WRITE_REG(*(pSetup->conOffset2), (READ_REG(*(pSetup->conOffset2)) & 0xff000000) | pConfig->frac); + } + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (pSetup->stat0) { + if (READ_REG(*(pSetup->stat0)) & (1 << pSetup->lockShift)) { + break; + } + } else { + if (READ_REG(*(pSetup->conOffset1)) & (1 << pSetup->lockShift)) { + break; + } + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + + return HAL_OK; +} + +/** + * @brief Set pll power up. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (pSetup->stat0) { + if (READ_REG(*(pSetup->stat0)) & (1 << pSetup->lockShift)) { + break; + } + } else { + if (READ_REG(*(pSetup->conOffset1)) & (1 << pSetup->lockShift)) { + break; + } + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Set pll power down. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIT); + + return HAL_OK; +} +#endif + +/** + * @brief IP Clock is Enabled API + * @param clk: clk gate id + * @return HAL_Check + */ +HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + HAL_Check ret; + +#ifdef CRU_GATE_CON_CNT + if (index < CRU_GATE_CON_CNT) { + ret = (HAL_Check)(!((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift)); + } else { +#ifdef PMUCRU_BASE + ret = (HAL_Check)(!((PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] & (1 << shift)) >> shift)); +#else + ret = (HAL_Check)(!((CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] & (1 << shift)) >> shift)); +#endif + } +#else + ret = (HAL_Check)(!((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift)); +#endif + + return ret; +} + +/** + * @brief IP Clock Enable API + * @param clk: clk gate id + * @return NONE + */ +HAL_Status HAL_CRU_ClkEnable(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + +#ifdef CRU_GATE_CON_CNT + if (index < CRU_GATE_CON_CNT) { + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift); +#else + CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift); +#endif + } +#else + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); +#endif + + return HAL_OK; +} + +/** + * @brief IP Clock Disabled API + * @param clk: clk gate id + * @return NONE + */ +HAL_Status HAL_CRU_ClkDisable(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + +#ifdef CRU_GATE_CON_CNT + if (index < CRU_GATE_CON_CNT) { + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift); +#else + CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift); +#endif + } +#else + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); +#endif + + return HAL_OK; +} + +/** + * @brief IP Clock is reset API + * @param clk: clk reset id + * @return HAL_Check + */ +HAL_Check HAL_CRU_ClkIsReset(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + HAL_Check ret; + +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + ret = (HAL_Check)((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift); + } else { + ret = (HAL_Check)((PMUCRU->CRU_CLKGATE_CON[index - CRU_SRST_CON_CNT] & (1 << shift)) >> shift); + } +#else + ret = (HAL_Check)((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift); +#endif + + return ret; +} + +/** + * @brief IP Clock Reset Assert API + * @param clk: clk reset id + * @return NONE + */ +HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk) +{ + uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); + uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); + + HAL_ASSERT(shift < 16); +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); + } else { + PMUCRU->CRU_SOFTRST_CON[index - CRU_SRST_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift); + } +#else + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); +#endif + + return HAL_OK; +} + +/** + * @brief IP Clock Reset Deassert API + * @param clk: clk reset id + * @return NONE + */ +HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk) +{ + uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); + uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); + + HAL_ASSERT(shift < 16); +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); + } else { + PMUCRU->CRU_SOFTRST_CON[index - CRU_SRST_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift); + } +#else + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); +#endif + + return HAL_OK; +} + +/** + * @brief IP Clock set div API + * @param divName: div id(Contains div offset, shift, mask information) + * @param divValue: div value + * @return NONE + */ +HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue) +{ + uint32_t shift, mask, index; + + index = CLK_DIV_GET_REG_OFFSET(divName); + shift = CLK_DIV_GET_BITS_SHIFT(divName); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(divName); + if (divValue > mask) { + divValue = mask; + } + +#ifdef CRU_CLK_DIV_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, (divValue - 1U) << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = VAL_MASK_WE(mask, (divValue - 1U) << shift); +#else + CRU->PMU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = VAL_MASK_WE(mask, (divValue - 1U) << shift); +#endif + } +#else + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, (divValue - 1U) << shift); +#endif + + return HAL_OK; +} + +/** + * @brief IP Clock get div API + * @param divName: div id(Contains div offset, shift, mask information) + * @return div value + */ +uint32_t HAL_CRU_ClkGetDiv(uint32_t divName) +{ + uint32_t shift, mask, index, divValue; + + index = CLK_DIV_GET_REG_OFFSET(divName); + shift = CLK_DIV_GET_BITS_SHIFT(divName); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(divName); + +#ifdef CRU_CLK_DIV_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + divValue = ((((CRU->CRU_CLKSEL_CON[index]) & mask) >> shift) + 1); + } else { +#ifdef PMUCRU_BASE + divValue = ((((PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]) & mask) >> shift) + 1); +#else + divValue = ((((CRU->PMU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]) & mask) >> shift) + 1); +#endif + } +#else + divValue = ((((CRU->CRU_CLKSEL_CON[index]) & mask) >> shift) + 1); +#endif + + return divValue; +} + +/** + * @brief IP Clock set mux API + * @param muxName: mux id(Contains mux offset, shift, mask information) + * @param muxValue: mux value + * @return NONE + */ +HAL_SECTION_SRAM_CODE +HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue) +{ + uint32_t shift, mask, index; + + index = CLK_MUX_GET_REG_OFFSET(muxName); + shift = CLK_MUX_GET_BITS_SHIFT(muxName); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(muxName); + +#ifdef CRU_CLK_SEL_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, muxValue << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] = VAL_MASK_WE(mask, muxValue << shift); +#else + CRU->PMU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] = VAL_MASK_WE(mask, muxValue << shift); +#endif + } +#else + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, muxValue << shift); +#endif + + return HAL_OK; +} + +/** + * @brief IP Clock get mux API + * @param muxName: mux id(Contains mux offset, shift, mask information) + * @return mux value + */ +HAL_SECTION_SRAM_CODE +uint32_t HAL_CRU_ClkGetMux(uint32_t muxName) +{ + uint32_t shift, mask, index, muxValue; + + index = CLK_MUX_GET_REG_OFFSET(muxName); + shift = CLK_MUX_GET_BITS_SHIFT(muxName); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(muxName); + +#ifdef CRU_CLK_SEL_CON_CNT + if (index < CRU_CLK_SEL_CON_CNT) { + muxValue = ((CRU->CRU_CLKSEL_CON[index] & mask) >> shift); + } else { +#ifdef PMUCRU_BASE + muxValue = ((PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] & mask) >> shift); +#else + muxValue = ((CRU->PMU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] & mask) >> shift); +#endif + } +#else + muxValue = ((CRU->CRU_CLKSEL_CON[index] & mask) >> shift); +#endif + + return muxValue; +} + +/** + * @brief Get frac div config. + * @param rateOut: clk out rate. + * @param rate: clk src rate. + * @param numerator: the returned numerator. + * @param denominator: the returned denominator. + * @return HAL_Status. + */ +HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, + uint32_t *numerator, + uint32_t *denominator) +{ + uint32_t gcdVal; + + gcdVal = CRU_Gcd(rate, rateOut); + if (!gcdVal) { + return HAL_ERROR; + } + + *numerator = rateOut / gcdVal; + *denominator = rate / gcdVal; + + if (*numerator < 4) { + *numerator *= 4; + *denominator *= 4; + } + if (*numerator > 0xffff || *denominator > 0xffff) { + return HAL_INVAL; + } + + return HAL_OK; +} + +/** + * @brief Get Np5 best div. + * @param clockName: clk id. + * @param rate: clk rate. + * @param pRate: clk parent rate + * @param bestdiv: the returned bestdiv. + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv) +{ + uint32_t div = CLK_GET_DIV(clockName); + uint32_t maxDiv = CLK_DIV_GET_MASK(div); + uint32_t i; + + for (i = 0; i < maxDiv; i++) { + if (((pRate * 2) == (rate * (i * 2 + 3)))) { + *bestdiv = i; + + return HAL_OK; + } + } + + return HAL_ERROR; +} + +/** + * @brief vop dclk enable. + * @param gateId: gate id + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +__WEAK HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId) +{ + HAL_CRU_ClkEnable(gateId); + + return HAL_OK; +} + +/** + * @brief vop dclk disable. + * @param gateId: gate id + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +__WEAK HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId) +{ + HAL_CRU_ClkDisable(gateId); + + return HAL_OK; +} + +/** + * @brief assert CRU global software reset. + * @param type: global software reset type. + * @return HAL_INVAL if the SoC does not support. + */ +HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type) +{ +#ifdef CRU_GLB_SRST_FST_VALUE_OFFSET + if (type == GLB_SRST_FST) { + CRU->GLB_SRST_FST_VALUE = GLB_SRST_FST; + } +#endif +#ifdef CRU_GLB_SRST_SND_VALUE_OFFSET + if (type == GLB_SRST_SND) { + CRU->GLB_SRST_SND_VALUE = GLB_SRST_SND; + } +#endif + + return HAL_INVAL; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_CRU_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/cru/hal_cru_rk2108.c b/bsp/rockchip/common/rk_hal/lib/hal/src/cru/hal_cru_rk2108.c new file mode 100644 index 00000000000..40f7be00eac --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/cru/hal_cru_rk2108.c @@ -0,0 +1,825 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#if defined(RKMCU_RK2108) && defined(HAL_CRU_MODULE_ENABLED) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +/** @defgroup CRU_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define DCLK_LCDC_PLL_LIMIT_FREQ 800 * 1000000 +#define CRU_AS_CFG_VAL2 0x1 +#define CRU_AS_CNT_MSK 0xFFFF + +/********************* Private Structure Definition **************************/ + +static struct PLL_CONFIG PLL_TABLE[] = { + /* _mhz, _refDiv, _fbDiv, _postdDv1, _postDiv2, _dsmpd, _frac */ + RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), + RK_PLL_RATE(600000000, 3, 75, 1, 1, 1, 0), + RK_PLL_RATE(282240000, 1, 35, 3, 1, 0, 4697620), + RK_PLL_RATE(245760000, 1, 40, 4, 1, 0, 16106127), + { 0 /* sentinel */ }, +}; + +static uint32_t s_gpllFreq; +static uint32_t s_cpllFreq; + +static struct PLL_SETUP GPLL = { + .conOffset0 = &(CRU->GPLL_CON[0]), + .conOffset1 = &(CRU->GPLL_CON[1]), + .conOffset2 = &(CRU->GPLL_CON[2]), + .modeOffset = &(CRU->CRU_MODE_CON00), + .modeShift = 0, + .lockShift = 10, + .modeMask = 0x3 << 0, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP CPLL = { + .conOffset0 = &(CRU->CPLL_CON[0]), + .conOffset1 = &(CRU->CPLL_CON[1]), + .conOffset2 = &(CRU->CPLL_CON[2]), + .modeOffset = &(CRU->CRU_MODE_CON00), + .modeShift = 2, + .lockShift = 10, + .modeMask = 0x3 << 2, + .rateTable = PLL_TABLE, +}; +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ +#ifdef HAL_CRU_DCG_FEATURE_ENABLED +static void CRU_DcgConfig(uint8_t ch, uint8_t func, uint32_t val1, uint32_t val2) +{ + HAL_ASSERT(ch < 2); + + switch (func) { + case 1: /* cfg en */ + CRU->DCG_CON[ch][4] = VAL_MASK_WE(CRU_DCG0_CON4_CFG_EN_MASK, + val1 << CRU_DCG0_CON4_CFG_EN_SHIFT); + break; + case 2: /* period cnt */ + CRU->DCG_CON[ch][0] = val1; + CRU->DCG_CON[ch][1] = val2; + break; + case 3: /* period cnt */ + CRU->DCG_CON[ch][2] = val1; + CRU->DCG_CON[ch][3] = val2; + break; + case 4: /* step */ + CRU->DCG_CON[ch][4] = VAL_MASK_WE(CRU_DCG0_CON4_CFG_STEP1_MASK, + val1 << CRU_DCG0_CON4_CFG_STEP1_SHIFT); + CRU->DCG_CON[ch][4] = VAL_MASK_WE(CRU_DCG0_CON4_CFG_STEP2_MASK, + val2 << CRU_DCG0_CON4_CFG_STEP2_SHIFT); + break; + case 5: /* limit */ + CRU->DCG_CON[ch][5] = VAL_MASK_WE(CRU_DCG0_CON5_CFG_LMT_MASK, + val1 << CRU_DCG0_CON5_CFG_LMT_SHIFT); + break; + default: + break; + } +} +#endif + +#ifdef HAL_CRU_AS_FEATURE_ENABLED +static void CRU_AsConfig(uint8_t ch, uint32_t val1, uint32_t val2) +{ + HAL_ASSERT(ch < 5); + CRU->AS_CON[ch][1] = VAL_MASK_WE(CRU_AS0_CON1_AS_CTRL_MASK | + CRU_AS0_CON1_AS_CFG_MASK | + CRU_AS0_CON1_ASS_EN_MASK | + CRU_AS0_CON1_AS_EN_MASK, + val1 << CRU_AS0_CON1_AS_CTRL_SHIFT | + val2 << CRU_AS0_CON1_AS_CFG_SHIFT); +} + +static void CRU_AsCntConfig(uint8_t ch, uint32_t val1, uint32_t val2) +{ + HAL_ASSERT(ch < 5); + + if (val1 >= CRU_AS_CNT_MSK) { + val1 = CRU->AS_CON[ch][0] & CRU_AS_CNT_MSK; + } + + if (val2 >= CRU_AS_CNT_MSK) { + val2 = (CRU->AS_CON[ch][0] >> 16) & CRU_AS_CNT_MSK; + } + + CRU->AS_CON[ch][0] = val1 | (val2 << 16); +} +#endif +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup CRU_Exported_Functions_Group5 Other Functions + * @{ + */ + +#ifdef HAL_CRU_AS_FEATURE_ENABLED +void HAL_CRU_AsEnable(uint8_t ch, uint8_t en) +{ + HAL_ASSERT(ch < 5); + + if (en) { + CRU->AS_CON[ch][1] = VAL_MASK_WE(CRU_AS0_CON1_AS_EN_MASK | + CRU_AS0_CON1_ASS_EN_MASK, + CRU_AS0_CON1_AS_EN_MASK | + CRU_AS0_CON1_ASS_EN_MASK); + } else { + CRU->AS_CON[ch][1] = VAL_MASK_WE(CRU_AS0_CON1_AS_EN_MASK | + CRU_AS0_CON1_ASS_EN_MASK, 0); + } +} + +void HAL_CRU_AsInit(void) +{ + CRU_AsConfig(0, 0x77, CRU_AS_CFG_VAL2); + CRU_AsCntConfig(0, 0x20, 0x18); + + CRU_AsConfig(1, 0x99, CRU_AS_CFG_VAL2); + CRU_AsCntConfig(1, 0x20, 0x18); + + CRU_AsConfig(2, 0x1, CRU_AS_CFG_VAL2); + CRU_AsCntConfig(2, 0x20, 0x18); + + CRU_AsConfig(3, 0x99, CRU_AS_CFG_VAL2); + CRU_AsCntConfig(3, 0x20, 0x18); + + CRU_AsConfig(4, 0x99, CRU_AS_CFG_VAL2); + CRU_AsCntConfig(4, 0x20, 0x18); + + HAL_CRU_AsEnable(1, 1); + HAL_CRU_AsEnable(2, 1); + HAL_CRU_AsEnable(3, 1); + HAL_CRU_AsEnable(4, 1); +} +#endif + +/** + * @brief vop dclk enable. + * @param gateId: gate id + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId) +{ + HAL_Status ret = HAL_OK; + + HAL_CRU_ClkEnable(gateId); + + return ret; +} + +/** + * @brief vop dclk disable. + * @param gateId: gate id + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId) +{ + HAL_Status ret = HAL_OK; + + HAL_CRU_ClkDisable(gateId); + + return ret; +} + +/** + * @brief Get frac clk freq. + * @param clockName: CLOCK_Name id + * @return clk rate. + * How to calculate the Frac clk divider: + * numerator is frac register[31:16] + * denominator is frac register[15:0] + * clk rate = pRate * numerator / denominator + * for a better jitter, pRate > 20 * rate + */ +static uint32_t HAL_CRU_ClkFracGetFreq(eCLOCK_Name clockName) +{ + uint32_t freq = 0; + uint32_t muxSrc = 0, mux = CLK_GET_MUX(clockName); + uint32_t divSrc = 0, divFrac = 0; + uint32_t n, m, pRate; + + switch (clockName) { + case CLK_UART0: + muxSrc = CLK_GET_MUX(CLK_UART0_SRC); + divSrc = CLK_GET_DIV(CLK_UART0_SRC); + divFrac = CLK_GET_DIV(CLK_UART0_FRAC); + break; + case CLK_UART1: + muxSrc = CLK_GET_MUX(CLK_UART1_SRC); + divSrc = CLK_GET_DIV(CLK_UART1_SRC); + divFrac = CLK_GET_DIV(CLK_UART1_FRAC); + break; + case CLK_UART2: + muxSrc = CLK_GET_MUX(CLK_UART2_SRC); + divSrc = CLK_GET_DIV(CLK_UART2_SRC); + divFrac = CLK_GET_DIV(CLK_UART2_FRAC); + break; + case I2S_MCLKOUT: + muxSrc = CLK_GET_MUX(CLK_I2S8CH_SRC); + divSrc = CLK_GET_DIV(CLK_I2S8CH_SRC); + divFrac = CLK_GET_DIV(CLK_I2S8CH_FRAC); + mux = CLK_GET_MUX(MCLK_I2S8CH); + break; + case I2S1_MCLKOUT: + muxSrc = CLK_GET_MUX(CLK_I2S1_8CH_SRC); + divSrc = CLK_GET_DIV(CLK_I2S1_8CH_SRC); + divFrac = CLK_GET_DIV(CLK_I2S1_8CH_FRAC); + mux = CLK_GET_MUX(MCLK_I2S1_8CH); + break; + case CLK_AUDPWM: + muxSrc = CLK_GET_MUX(CLK_AUDPWM_SRC); + divSrc = CLK_GET_DIV(CLK_AUDPWM_SRC); + divFrac = CLK_GET_DIV(CLK_AUDPWM_FRAC); + break; + case CLK_32K: + divFrac = CLK_GET_DIV(CLK_32K); + break; + default: + + return 0; + } + + n = (CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] & 0xffff0000) >> 16; + m = CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] & 0x0000ffff; + + switch (clockName) { + case CLK_32K: + pRate = PLL_INPUT_OSC_RATE; + freq = (pRate / m) * n; + break; + case CLK_AUDPWM: + if (HAL_CRU_ClkGetMux(mux) == 0) { + freq = s_gpllFreq / HAL_CRU_ClkGetDiv(divSrc); + } else if (HAL_CRU_ClkGetMux(mux) == 1) { + freq = (s_gpllFreq / m) * n; + } + break; + default: + if (HAL_CRU_ClkGetMux(muxSrc)) { + pRate = s_cpllFreq / HAL_CRU_ClkGetDiv(divSrc); + } else { + pRate = s_gpllFreq / HAL_CRU_ClkGetDiv(divSrc); + } + + if (HAL_CRU_ClkGetMux(mux) == 0) { + freq = pRate; + } else if (HAL_CRU_ClkGetMux(mux) == 1) { + freq = (pRate / m) * n; + } else if (HAL_CRU_ClkGetMux(mux) == 2) { + freq = PLL_INPUT_OSC_RATE; + } + break; + } + + return freq; +} + +/** + * @brief Set frac clk freq. + * @param clockName: CLOCK_Name id. + * @param rate: clk set rate + * @return HAL_Status. + * How to calculate the Frac clk divider: + * if pRate > 20 * rate, select frac divider + * else select normal divider, but the clk rate may be not accurate + */ +static HAL_Status HAL_CRU_ClkFracSetFreq(eCLOCK_Name clockName, uint32_t rate) +{ + uint32_t muxSrc, mux = CLK_GET_MUX(clockName), muxOut = 0; + uint32_t divSrc, divFrac; + uint32_t n = 0, m = 0, pRate = s_gpllFreq; + uint32_t gateId, fracGateId; + + switch (clockName) { + case CLK_UART0: + muxSrc = CLK_GET_MUX(CLK_UART0_SRC); + divSrc = CLK_GET_DIV(CLK_UART0_SRC); + divFrac = CLK_GET_DIV(CLK_UART0_FRAC); + gateId = CLK_UART0_GATE; + fracGateId = CLK_UART0_FRAC_GATE; + break; + case CLK_UART1: + muxSrc = CLK_GET_MUX(CLK_UART1_SRC); + divSrc = CLK_GET_DIV(CLK_UART1_SRC); + divFrac = CLK_GET_DIV(CLK_UART1_FRAC); + gateId = CLK_UART1_GATE; + fracGateId = CLK_UART1_FRAC_GATE; + break; + case CLK_UART2: + muxSrc = CLK_GET_MUX(CLK_UART2_SRC); + divSrc = CLK_GET_DIV(CLK_UART2_SRC); + divFrac = CLK_GET_DIV(CLK_UART2_FRAC); + gateId = CLK_UART2_GATE; + fracGateId = CLK_UART2_FRAC_GATE; + break; + case I2S_MCLKOUT: + muxSrc = CLK_GET_MUX(CLK_I2S8CH_SRC); + divSrc = CLK_GET_DIV(CLK_I2S8CH_SRC); + divFrac = CLK_GET_DIV(CLK_I2S8CH_FRAC); + mux = CLK_GET_MUX(MCLK_I2S8CH); + muxOut = CLK_GET_MUX(I2S_MCLKOUT); + gateId = CLK_I2S8CH_GATE; + fracGateId = CLK_I2S8CH_FRAC_GATE; + break; + case I2S1_MCLKOUT: + muxSrc = CLK_GET_MUX(CLK_I2S1_8CH_SRC); + divSrc = CLK_GET_DIV(CLK_I2S1_8CH_SRC); + divFrac = CLK_GET_DIV(CLK_I2S1_8CH_FRAC); + mux = CLK_GET_MUX(MCLK_I2S1_8CH); + muxOut = CLK_GET_MUX(I2S1_MCLKOUT); + gateId = CLK_I2S1_8CH_GATE; + fracGateId = CLK_I2S1_8CH_FRAC_GATE; + break; + case CLK_AUDPWM: + muxSrc = CLK_GET_MUX(CLK_AUDPWM_SRC); + divSrc = CLK_GET_DIV(CLK_AUDPWM_SRC); + divFrac = CLK_GET_DIV(CLK_AUDPWM_FRAC); + pRate = s_gpllFreq; + gateId = CLK_AUDPWM_DF_GATE; + fracGateId = CLK_AUDPWM_FRAC_GATE; + break; + case CLK_32K: + divFrac = CLK_GET_DIV(CLK_32K); + pRate = PLL_INPUT_OSC_RATE; + break; + default: + + return HAL_INVAL; + } + + switch (clockName) { + case CLK_UART0: + case CLK_UART1: + case CLK_UART2: + HAL_CRU_ClkEnable(gateId); + HAL_CRU_ClkEnable(fracGateId); + if (PLL_INPUT_OSC_RATE == rate) { + HAL_CRU_ClkSetMux(mux, 2); + HAL_CRU_ClkDisable(gateId); + } else if ((!(s_gpllFreq % rate)) && ((s_gpllFreq / rate) < 31)) { + HAL_CRU_ClkSetDiv(divSrc, s_gpllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 0); + HAL_CRU_ClkSetMux(mux, 0); + HAL_CRU_ClkDisable(fracGateId); + } else if ((!(s_cpllFreq % rate)) && ((s_cpllFreq / rate) < 31)) { + HAL_CRU_ClkSetDiv(divSrc, s_cpllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 1); + HAL_CRU_ClkSetMux(mux, 0); + HAL_CRU_ClkDisable(fracGateId); + } else { + HAL_CRU_FracdivGetConfig(rate, pRate, &n, &m); + HAL_CRU_ClkSetDiv(divSrc, 1); + HAL_CRU_ClkSetMux(muxSrc, 0); + CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] = (n << 16) | m; + HAL_CRU_ClkSetMux(mux, 1); + } + + return HAL_OK; + case I2S_MCLKOUT: + case I2S1_MCLKOUT: + case CLK_AUDPWM: + HAL_CRU_ClkEnable(gateId); + HAL_CRU_ClkEnable(fracGateId); + if (PLL_INPUT_OSC_RATE == rate) { + HAL_CRU_ClkSetMux(mux, 2); + HAL_CRU_ClkDisable(gateId); + } else if ((!(s_cpllFreq % rate)) && ((s_cpllFreq / rate) < 31)) { + HAL_CRU_ClkSetDiv(divSrc, s_cpllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 1); + HAL_CRU_ClkSetMux(mux, 0); + HAL_CRU_ClkDisable(fracGateId); + } else { + HAL_CRU_FracdivGetConfig(rate, s_cpllFreq, &n, &m); + HAL_CRU_ClkSetDiv(divSrc, 1); + HAL_CRU_ClkSetMux(muxSrc, 1); + CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] = (n << 16) | m; + HAL_CRU_ClkSetMux(mux, 1); + } + if (muxOut) { + HAL_CRU_ClkSetMux(muxOut, 0); + } + + return HAL_OK; + case CLK_32K: + HAL_CRU_FracdivGetConfig(rate, PLL_INPUT_OSC_RATE, &n, &m); + CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] = (n << 16) | m; + + return HAL_OK; + default: + + return HAL_INVAL; + } +} + +/** + * @brief Get Usb clk freq. + * @param clockName: CLOCK_Name id + * @return clk rate. + * How to calculate the Frac clk divider: + * numerator is frac register[31:16] + * denominator is frac register[15:0] + * clk rate = pRate * numerator / denominator + */ +static uint32_t HAL_CRU_ClkUsbGetFreq(eCLOCK_Name clockName) +{ + uint32_t freq = 0; + uint32_t muxSrc, mux = CLK_GET_MUX(clockName); + uint32_t divFrac; + uint32_t n, m, pRate; + + switch (clockName) { + case CLK_USB2PHY_REF: + muxSrc = CLK_GET_MUX(CLK_USB2PHY_REF_FRAC); + divFrac = CLK_GET_DIV(CLK_USB2PHY_REF_FRAC); + break; + case CLK_DPHY_REF: + muxSrc = CLK_GET_MUX(CLK_DPHY_REF_FRAC); + divFrac = CLK_GET_DIV(CLK_DPHY_REF_FRAC); + break; + default: + + return 0; + } + n = (CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] & 0xffff0000) >> 16; + m = CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] & 0x0000ffff; + + if (HAL_CRU_ClkGetMux(muxSrc)) { + pRate = s_cpllFreq; + } else { + pRate = s_gpllFreq; + } + + if (HAL_CRU_ClkGetMux(mux) == 0) { + freq = PLL_INPUT_OSC_RATE; + } else if (HAL_CRU_ClkGetMux(mux) == 1) { + freq = (pRate / m) * n; + } + + return freq; +} + +/** + * @brief Set usb clk freq. + * @param clockName: CLOCK_Name id. + * @param rate: clk set rate + * @return HAL_Status. + * How to calculate the Frac clk divider: + * if rate is inpust osc rate, select input osc + * else select ifrac divider + */ +static HAL_Status HAL_CRU_ClkUsbSetFreq(eCLOCK_Name clockName, uint32_t rate) +{ + uint32_t muxSrc, mux = CLK_GET_MUX(clockName); + uint32_t divFrac; + uint32_t n = 0, m = 0, pRate = s_gpllFreq; + + switch (clockName) { + case CLK_USB2PHY_REF: + muxSrc = CLK_GET_MUX(CLK_USB2PHY_REF_FRAC); + divFrac = CLK_GET_DIV(CLK_USB2PHY_REF_FRAC); + break; + case CLK_DPHY_REF: + muxSrc = CLK_GET_MUX(CLK_DPHY_REF_FRAC); + divFrac = CLK_GET_DIV(CLK_DPHY_REF_FRAC); + break; + default: + + return HAL_INVAL; + } + + if (rate == PLL_INPUT_OSC_RATE) { + HAL_CRU_ClkSetMux(mux, 0); + } else { + HAL_CRU_FracdivGetConfig(rate, pRate, &n, &m); + HAL_CRU_ClkSetMux(muxSrc, 0); + CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] = (n << 16) | m; + HAL_CRU_ClkSetMux(mux, 1); + } + + return HAL_OK; +} + +/** + * @brief Get clk freq. + * @param clockName: CLOCK_Name id. + * @return rate. + * @attention these APIs allow direct use in the HAL layer. + */ +uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName) +{ + uint32_t freq; + uint32_t clkMux = CLK_GET_MUX(clockName), mux = 0; + uint32_t clkDiv = CLK_GET_DIV(clockName); + uint32_t pRate = s_gpllFreq; + + if (!s_gpllFreq) { + s_gpllFreq = HAL_CRU_GetPllFreq(&GPLL); + } + if (!s_cpllFreq) { + s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); + } + + switch (clockName) { + case PLL_GPLL: + freq = HAL_CRU_GetPllFreq(&GPLL); + s_gpllFreq = freq; + + return freq; + case PLL_CPLL: + freq = HAL_CRU_GetPllFreq(&CPLL); + s_cpllFreq = freq; + + return freq; + case DCLK_VOP_S: + if (HAL_CRU_ClkGetMux(clkMux)) { + pRate = s_cpllFreq; + } + + freq = pRate / HAL_CRU_ClkGetDiv(clkDiv); + + return freq; + case CLK_UART0: + case CLK_UART1: + case CLK_UART2: + case I2S_MCLKOUT: + case I2S1_MCLKOUT: + case CLK_AUDPWM: + case CLK_32K: + freq = HAL_CRU_ClkFracGetFreq(clockName); + + return freq; + case ACLK_DSP: + case HCLK_AUDIO: + case MCLK_PDM0: + case SCLK_SFC_SRC: + case SCLK_SFC1_SRC: + if (HAL_CRU_ClkGetMux(clkMux)) { + pRate = s_cpllFreq; + } else { + pRate = s_gpllFreq; + } + break; + case CLK_PWM: + mux = HAL_CRU_ClkGetMux(clkMux); + if (mux) { + pRate = PLL_INPUT_OSC_RATE; + } + break; + case CLK_GPIO_DBG0: + case CLK_GPIO_DBG1: + pRate = PLL_INPUT_OSC_RATE; + break; + case CLK_USB2PHY_REF: + case CLK_DPHY_REF: + freq = HAL_CRU_ClkUsbGetFreq(clockName); + + return freq; + case CLK_CIFOUT: + mux = HAL_CRU_ClkGetMux(clkMux); + if (mux == 2) { + pRate = PLL_INPUT_OSC_RATE; + } + break; + default: + break; + } + + if ((clkMux == 0) && (clkDiv == 0)) { + return 0; + } + + if (clkDiv) { + freq = pRate / (HAL_CRU_ClkGetDiv(clkDiv)); + } else { + freq = pRate; + } + + return freq; +} + +/** + * @brief Set clk freq. + * @param clockName: CLOCK_Name id. + * @param rate: clk rate. + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate) +{ + HAL_Status error = HAL_OK; + uint32_t clkMux = CLK_GET_MUX(clockName), mux = 0; + uint32_t clkDiv = CLK_GET_DIV(clockName), div = 0; + uint32_t pRate = s_gpllFreq; + + if (!s_gpllFreq) { + s_gpllFreq = HAL_CRU_GetPllFreq(&GPLL); + } + if (!s_cpllFreq) { + s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); + } + + switch (clockName) { + case PLL_GPLL: + error = HAL_CRU_SetPllFreq(&GPLL, rate); + s_gpllFreq = HAL_CRU_GetPllFreq(&GPLL); + + return error; + case PLL_CPLL: + error = HAL_CRU_SetPllFreq(&CPLL, rate); + s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); + + return error; + case DCLK_VOP_S: + if (!(s_gpllFreq % rate)) { + pRate = s_gpllFreq; + mux = 0; + } else { + pRate = s_cpllFreq; + mux = 1; + } + div = HAL_DIV_ROUND_UP(pRate, rate); + HAL_CRU_ClkSetMux(clkMux, mux); + HAL_CRU_ClkSetDiv(clkDiv, div); + + return error; + case CLK_UART0: + case CLK_UART1: + case CLK_UART2: + case I2S_MCLKOUT: + case I2S1_MCLKOUT: + case CLK_AUDPWM: + case CLK_32K: + error = HAL_CRU_ClkFracSetFreq(clockName, rate); + + return error; + case ACLK_DSP: + case HCLK_AUDIO: + case MCLK_PDM0: + error = HAL_CRU_ClkFracSetFreq(clockName, rate); + pRate = s_cpllFreq; + mux = 1; + break; + case SCLK_SFC_SRC: + case SCLK_SFC1_SRC: + if (s_cpllFreq == PLL_INPUT_OSC_RATE) { + pRate = s_gpllFreq; + mux = 0; + } else { + pRate = s_cpllFreq; + mux = 1; + } + break; + case CLK_PWM: + if (rate <= PLL_INPUT_OSC_RATE) { + mux = 1; + pRate = PLL_INPUT_OSC_RATE; + } + break; + case CLK_GPIO_DBG0: + case CLK_GPIO_DBG1: + pRate = PLL_INPUT_OSC_RATE; + break; + case CLK_USB2PHY_REF: + case CLK_DPHY_REF: + error = HAL_CRU_ClkUsbSetFreq(clockName, rate); + + return error; + case CLK_CIFOUT: + if (rate == PLL_INPUT_OSC_RATE) { + mux = 2; + pRate = PLL_INPUT_OSC_RATE; + } + break; + default: + break; + } + + if ((clkMux == 0) && (clkDiv == 0)) { + return HAL_INVAL; + } + + div = HAL_DIV_ROUND_UP(pRate, rate); + if (clkMux) { + HAL_CRU_ClkSetMux(clkMux, mux); + } + if (clkDiv) { + HAL_CRU_ClkSetDiv(clkDiv, div); + } + + if (clockName == HCLK_M4) { + HAL_SystemCoreClockUpdate(rate, HAL_SYSTICK_CLKSRC_EXT); + } + + return HAL_OK; +} + +/** + * @brief pll output freq Compensation. + * @param clockName: CLOCK_Name id. + * @param ppm: Efforts to compensate. + * @return HAL_OK. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_PllCompensation(eCLOCK_Name clockName, int ppm) +{ + __IO uint32_t *conOffset0, *conOffset2; + uint32_t frac, fbdiv; + uint64_t fracdiv; + long int m, n; + + if ((ppm > 100) || (ppm < -100)) { + return HAL_INVAL; + } + + switch (clockName) { + case PLL_GPLL: + conOffset0 = &(CRU->GPLL_CON[0]); + conOffset2 = &(CRU->GPLL_CON[2]); + break; + case PLL_CPLL: + conOffset0 = &(CRU->CPLL_CON[0]); + conOffset2 = &(CRU->CPLL_CON[2]); + break; + default: + + return HAL_INVAL; + } + + frac = READ_REG(*conOffset2) & 0xffffff; + fbdiv = READ_REG(*conOffset0) & 0xfff; + m = frac * ppm; + n = ppm << 24; + + fracdiv = (m / MHZ) + ((n / MHZ) * fbdiv) + frac; + + if (fracdiv > 0xffffff) { + return HAL_INVAL; + } + + WRITE_REG(*conOffset2, (READ_REG(*conOffset2) & 0xff000000) | fracdiv); + + return HAL_OK; +} + +/** + * @brief wdt glbrst enable. + * @param wdtType: wdt reset type. + * @return HAL_OK. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType) +{ + uint32_t mask = 0, val = 0; + + switch (wdtType) { + case GLB_RST_FST_WDT0: + mask = CRU_GLB_RST_CON_WDT0_GLBRST_EN_MASK | CRU_GLB_RST_CON_WDT0_FST_GLBRST_EN_MASK; + val = (1 << CRU_GLB_RST_CON_WDT0_GLBRST_EN_SHIFT) | (1 << CRU_GLB_RST_CON_WDT0_FST_GLBRST_EN_SHIFT); + break; + case GLB_RST_FST_WDT1: + mask = CRU_GLB_RST_CON_WDT1_GLBRST_EN_MASK | CRU_GLB_RST_CON_WDT1_FST_GLBRST_EN_MASK; + val = (1 << CRU_GLB_RST_CON_WDT1_GLBRST_EN_SHIFT) | (1 << CRU_GLB_RST_CON_WDT1_FST_GLBRST_EN_SHIFT); + break; + case GLB_RST_SND_WDT0: + mask = CRU_GLB_RST_CON_WDT0_GLBRST_EN_MASK | CRU_GLB_RST_CON_WDT0_FST_GLBRST_EN_MASK; + val = (1 << CRU_GLB_RST_CON_WDT0_GLBRST_EN_SHIFT); + break; + case GLB_RST_SND_WDT1: + mask = CRU_GLB_RST_CON_WDT1_GLBRST_EN_MASK | CRU_GLB_RST_CON_WDT1_FST_GLBRST_EN_MASK; + val = (1 << CRU_GLB_RST_CON_WDT1_GLBRST_EN_SHIFT); + break; + default: + + return HAL_INVAL; + } + + CRU->GLB_RST_CON = VAL_MASK_WE(mask, val); + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* RKMCU_RK2108 && HAL_CRU_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_base.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_base.c new file mode 100644 index 00000000000..cd68f1d2cfa --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_base.c @@ -0,0 +1,357 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_BASE + * @{ + */ + +/** @defgroup HAL_BASE_How_To_Use How To Use + * @{ + + HAL system support is including delay system, HAL tick system and global system clock, + + HAL system tick setting: + + - Attach HAL_IncTick() to system tick interrupt handler; + - Notify the HAL system the system's tick frequency by calling HAL_SetTickFreq() unless + it is the same as default value HAL_TICK_FREQ_1KHZ; + - If you need a more accurate delay system, specify SYS_TIMER in hal_conf.h. + + Init HAL system: + + - Initialize the HAL system by calling HAL_Init(): + + Reset when SOC system is changed: + + - Update system with new core clock and new SysTick clock source by calling HAL_SystemCoreClockUpdate(); + + APIs: + + - Get system time by calling HAL_GetTick(); + - Delay for a certain length of time, HAL_DelayMs(), HAL_DelayUs(), and HAL_CPUDelayUs(). + - Blocking for a certain period of time to continuously query HW status, use HAL_GetTick() + to do timeout, this will be more accurate. + + @} */ + +/** @defgroup HAL_BASE_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +static __IO uint32_t uwTick; +static eHAL_tickFreq uwTickFreq = HAL_TICK_FREQ_DEFAULT; + +/********************* Private Function Definition ***************************/ +#if defined(__CORTEX_A) || defined(__CORTEX_M) +#if __CORTEX_M == 0U || !defined(__GNUC__) +static void CPUCycleLoop(uint32_t cycles) +{ + uint32_t count; + + if (cycles < 100U) { + return; + } + + count = cycles / 3; + while (count-- > 0) { + __asm volatile ("nop"); + } +} +#else +static void CPUCycleLoop(uint32_t cycles) +{ + __ASM volatile ( + "mov r0, %0\n\t" + "adds r0, r0, #2\n\t" // 1 2 Round to the nearest multiple of 4. + "lsrs r0, r0, #2\n\t" // 1 2 Divide by 4 and set flags. + "beq 2f\n\t" // 2 2 Skip if 0. + ".align 4\n\t" + "1:\n\t" + "adds r0, r0, #1\n\t" // 1 2 Increment the counter. + "subs r0, r0, #2\n\t" // 1 2 Decrement the counter by 2. + "bne 1b\n\t" // (1)2 2 2 CPU cycles (if branch is taken). + "nop\n\t" // 1 2 Loop alignment padding. + "2:" + : : "r" (cycles) + ); +} +#endif +#elif defined(__RISC_V) +static void CPUCycleLoop(uint32_t cycles) +{ + asm volatile ( + "mv a0, %0\n\t" + "addi a0, a0, 2\n\t" // 1 2 Round to the nearest multiple of 4. + "li a1, 4\n\t" + "div a0, a0, a1\n\t" // 1 2 Divide by 4 and set flags. + "li a1, 2\n\t" + "bnez a0, 1f\n\t" // 2 2 Skip if 0. + "j 2f\n\t" + ".align 6\n\t" + "1:\n\t" + "addi a0, a0, 1\n\t" // 1 2 Increment the counter. + "sub a0, a0, a1\n\t" // 1 2 Decrement the counter by 2. + "bnez a0, 1b\n\t" // (1)2 2 2 CPU cycles (if branch is taken). + "nop\n\t" // 1 2 Loop alignment padding. + "2:" + : : "r" (cycles) + ); +} +#endif + +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) +__STATIC_FORCEINLINE HAL_Status TimerDelayUs(uint32_t us) +{ + uint64_t count, from, now, pass; + + from = HAL_TIMER_GetCount(SYS_TIMER); + count = PLL_INPUT_OSC_RATE / 1000000 * us; + + do { + now = HAL_TIMER_GetCount(SYS_TIMER); + pass = now > from ? now - from : from - now; + } while (pass < count); + + return HAL_OK; +} +#endif + +/** @} */ +/********************* Public Function Definition ***************************/ +/** @defgroup HAL_BASE_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +/** + * @brief Init HAL driver basic code. + * @return HAL_OK. + */ +HAL_Status HAL_Init(void) +{ +#ifdef __CORTEX_M +#ifdef HAL_NVIC_MODULE_ENABLED + /* Set Interrupt Group Priority */ + HAL_NVIC_Init(); + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_DEFAULT); +#endif +#endif + +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) + HAL_TIMER_SysTimerInit(SYS_TIMER); +#endif + +#ifdef RK_BSP_TEMP +#ifdef HAL_PINCTRL_MODULE_ENABLED + HAL_PINCTRL_Init(); +#endif +#endif + + return HAL_OK; +} + +/** + * @brief HAL system update with new core clock and systick clock source. + * @param hz: new core clock. + * @param clkSource: new systick clock source. + * @return HAL_OK. + */ +HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSource) +{ + uint32_t rate = hz; + HAL_Status ret = HAL_OK; + +#if defined(__CORTEX_M) && defined(HAL_SYSTICK_MODULE_ENABLED) + ret = HAL_SYSTICK_CLKSourceConfig(clkSource); + if (ret == HAL_OK && clkSource == HAL_SYSTICK_CLKSRC_EXT) { + rate = PLL_INPUT_OSC_RATE; + } + HAL_SYSTICK_Config(rate / (1000 / HAL_GetTickFreq())); + ret = HAL_OK; +#endif + + if (ret == HAL_OK) { + SystemCoreClock = rate; /* Update global SystemCoreClock */ + } + + return ret; +} + +/** + * @brief HAL deinit. + * @return HAL_Status: HAL_OK. + */ +HAL_Status HAL_DeInit(void) +{ + /* TO-DO */ + + return HAL_OK; +} + +/** @} */ + +/** @defgroup HAL_BASE_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief Count plus tickFreq when interrupt occurs. + * @return HAL_Status: HAL_OK. + */ +HAL_Status HAL_IncTick(void) +{ + uwTick += uwTickFreq; + + return HAL_OK; +} + +/** + * @brief Provides tick value in millisecond. + * @return uint32_t: tick value in millisecond. + * @attention this API allow direct use in the HAL layer. + */ +uint32_t HAL_GetTick(void) +{ +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) + uint64_t tick = HAL_TIMER_GetCount(SYS_TIMER); + uint32_t base = PLL_INPUT_OSC_RATE / 1000; + + if (tick >> 62) { + tick = ~tick; + } + + return (uint32_t)HAL_DivU64(tick, base); +#else + + return uwTick; +#endif +} + +/** + * @brief Provides system timer count. + * @return uint64_t: timer count. + * @attention this API allow direct use in the HAL layer. + */ +uint64_t HAL_GetSysTimerCount(void) +{ +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) + uint64_t count = HAL_TIMER_GetCount(SYS_TIMER); + if (count >> 62) { + count = ~count; + } + + return count; +#else + + return 0LLU; +#endif +} + +/** + * @brief Set new tick frequency. + * @return HAL_Status. + */ +HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq) +{ + HAL_ASSERT(IS_TICKFREQ(freq)); + + uwTickFreq = freq; + + return HAL_OK; +} + +/** + * @brief Return tick frequency. + * @return uint32_t: tick period in Hz. + * @attention this API allow direct use in the HAL layer. + */ +eHAL_tickFreq HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief SysTick mdelay. + * @param ms: mdelay count. + * @return HAL_Status: HAL_OK. + * @attention this API allow direct use in the HAL layer. Blocking for a + * certain period of time to continuously query HW status, use HAL_GetTick + * to do timeout, that will be more accurate. + */ +__WEAK HAL_Status HAL_DelayMs(uint32_t ms) +{ + for (uint32_t i = 0; i < ms; i++) { + HAL_DelayUs(1000); + } + + return HAL_OK; +} + +/** + * @brief SysTick udelay. + * @param us: udelay count. + * @return HAL_Status: HAL_OK. + * @attention this API allow direct use in the HAL layer. The longer the delay, + * the more accurate. Actual delay is greater than the parameter. + */ +HAL_Status HAL_DelayUs(uint32_t us) +{ +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) + + return TimerDelayUs(us); +#else + + return HAL_CPUDelayUs(us); +#endif +} + +/** + * @brief CPU loop udelay. + * @param us: udelay count. + * @return HAL_Status: HAL_OK. + * @attention this API allow direct use in the HAL layer. The longer the delay, + * the more accurate. Actual delay is greater than the parameter. + * During delay, CPU rate change result in delay imprecise, so call it in + * following case: + * 1.IRQ disable + * 2.CRU code + */ +HAL_Status HAL_CPUDelayUs(uint32_t us) +{ + volatile uint32_t cycles; + +#if (__CORTEX_M == 0) + cycles = (uint32_t)HAL_DivU64((uint64_t)SystemCoreClock, 1000000) * us; /* Add few cycles penalty */ +#else + cycles = SystemCoreClock / 1000000 * us; /* Add few cycles penalty */ +#endif + + CPUCycleLoop(cycles); + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_base_ex.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_base_ex.c new file mode 100644 index 00000000000..de5c79a3d5f --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_base_ex.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_BASE_EX + * @{ + */ + +/** @addtogroup HAL_BASE_EX_How_To_Use How To Use + * @{ + + The HAL_BASE_EX driver can be used as follows: + + @} */ + +/** @defgroup HAL_BASE_EX_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ***************************/ +/** @defgroup HAL_BASE_EX_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief uint64_t numerator / uint32_t denominator with remainder + * @param numerator + * @param denominator + * @param pRemainder [out] pointer to unsigned 32bit remainder + * @return uint64_t result. sets *pRemainder if pRemainder is not null + */ +uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder) +{ + uint64_t remainder = numerator; + uint64_t b = denominator; + uint64_t result; + uint64_t d = 1; + uint32_t high = numerator >> 32; + + result = 0; + if (high >= denominator) { + high /= denominator; + result = (uint64_t)high << 32; + remainder -= (uint64_t)(high * denominator) << 32; + } + + while ((int64_t)b > 0 && b < remainder) { + b = b + b; + d = d + d; + } + + do { + if (remainder >= b) { + remainder -= b; + result += d; + } + b >>= 1; + d >>= 1; + } while (d); + + if (pRemainder) { + *pRemainder = remainder; + } + + return result; +} + +/** @} */ + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_cache.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_cache.c new file mode 100644 index 00000000000..3a799221494 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_cache.c @@ -0,0 +1,925 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CACHE + * @{ + */ +#include "hal_base.h" +#include "hal_cache.h" + +/** @defgroup CACHE_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/***************************** MACRO Definition ******************************/ + +/***************************** Structure Definition **************************/ + +/********************* Private Function Definition ***************************/ + +#if defined(__CORTEX_M) +__STATIC_INLINE unsigned long HAL_SYS_EnterCriticalSection(void) +{ + unsigned long flags; + + flags = __get_PRIMASK(); + __disable_irq(); + + return flags; +} + +__STATIC_INLINE void HAL_SYS_ExitCriticalSection(unsigned long flags) +{ + __set_PRIMASK(flags); +} +#else +__STATIC_INLINE unsigned long HAL_SYS_EnterCriticalSection(void) +{ + return 0; +} + +__STATIC_INLINE void HAL_SYS_ExitCriticalSection(unsigned long flags) +{ +} +#endif + +/** @} */ +/********************* Public Function Definition ****************************/ +/** @defgroup CACHE_Exported_Functions_Group5 Other Functions + * @attention these APIs allow direct use in the HAL layer + * @{ + */ + +/** + * @brief translate the cpuAddr to sramAddr + * @param cpuAddr: the address mapping to sram, only can be accessed by cpu + * @return sramAddr: the real address of sram, it can be accessed by cpu & device + */ +uint32_t HAL_CpuAddrToDmaAddr(uint32_t cpuAddr) +{ + uint32_t sramAddr = cpuAddr; + +#ifdef SRAM_IADDR_TO_DADDR_OFFSET + + if (cpuAddr >= SRAM_IADDR_START + && cpuAddr < (SRAM_IADDR_START + SRAM_SIZE)) { + sramAddr = cpuAddr + SRAM_IADDR_TO_DADDR_OFFSET; + } + +#endif + +#ifdef XIP_NOR_IADDR_TO_DADDR_OFFSET + + if (cpuAddr >= XIP_NOR_IADDR_START + && cpuAddr < (XIP_NOR_IADDR_START + XIP_NOR_SIZE)) { + sramAddr = cpuAddr + XIP_NOR_IADDR_TO_DADDR_OFFSET; + } + +#endif + +#ifdef XIP_PSRAM_IADDR_TO_DADDR_OFFSET + + if (cpuAddr >= XIP_PSRAM_IADDR_START + && cpuAddr < (XIP_PSRAM_IADDR_START + XIP_PSRAM_SIZE)) { + sramAddr = cpuAddr + XIP_PSRAM_IADDR_TO_DADDR_OFFSET; + } + +#endif + + return sramAddr; +} + +#ifdef MPU +/** + * @brief check mpu is enable. + * @return HAL_ENABLE if mpu enable. + */ +__STATIC_INLINE HAL_FuncStatus HAL_MPU_IsEnable(void) +{ + HAL_FuncStatus ret = HAL_DISABLE; + + if (MPU->CTRL & MPU_CTRL_ENABLE_Msk) { + ret = HAL_ENABLE; + } + + return ret; +} +#endif + +/** + * @brief enable icache. + * @return HAL_OK if success. + * @attention The MPU must be configured before cache if you need the function. + */ +HAL_Status HAL_ICACHE_Enable(void) +{ +#if defined(HAL_ICACHE_MODULE_ENABLED) && defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + uint32_t status; + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + /* config icache: mpu disable, stb disable, write through, hot buffer enable, + prefetch enable */ + ICACHE->CACHE_CTRL |= + (ICACHE_CACHE_CTRL_CACHE_EN_MASK | ICACHE_CACHE_CTRL_CACHE_WT_EN_MASK); + ICACHE->CACHE_CTRL &= (~ICACHE_CACHE_CTRL_CACHE_STB_EN_MASK); + + /* if mpu has been enable, we will enable cache mpu function */ +#ifdef MPU + if (HAL_MPU_IsEnable()) { + ICACHE->CACHE_CTRL |= ICACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK; + } +#endif + + do { + status = + ICACHE->CACHE_STATUS & ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK; + } while (status == 0); + + ICACHE->CACHE_CTRL &= ~ICACHE_CACHE_CTRL_CACHE_BYPASS_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief disable icache. + * @return HAL_OK if success. + */ +HAL_Status HAL_ICACHE_Disable(void) +{ +#if defined(HAL_ICACHE_MODULE_ENABLED) && defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + ICACHE->CACHE_CTRL |= ICACHE_CACHE_CTRL_CACHE_BYPASS_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief invalidate all of the icache. + * @return HAL_OK if success. + */ +HAL_Status HAL_ICACHE_Invalidate(void) +{ +#if defined(HAL_ICACHE_MODULE_ENABLED) && defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + uint32_t status = 0; + unsigned long flags; + + if ((uint32_t)DCACHE == (uint32_t)ICACHE) { + if (DCACHE->CACHE_CTRL & DCACHE_CACHE_CTRL_CACHE_WT_EN_MASK) { + return HAL_OK; + } else { + return HAL_INVAL; + } + } + + flags = HAL_SYS_EnterCriticalSection(); + + ICACHE->CACHE_MAINTAIN[0] = + CACHE_M_INVALID_ALL | ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + + do { + status = ICACHE->CACHE_MAINTAIN[0] & + ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + } while (status); + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief invalidate the specified region of the icache. + * @param address: the start address of specified region which you want invalidate. + * @param sizeByte: the length in bytes of invalidate range. + * @return HAL_OK if success. + */ +HAL_Status HAL_ICACHE_InvalidateByRange(uint32_t address, + uint32_t sizeByte) +{ +#if defined(HAL_ICACHE_MODULE_ENABLED) && defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + uint32_t value = 0; + uint32_t offset = 0; + uint32_t status = 0; + unsigned long flags; + + if (sizeByte == 0) { + return HAL_OK; + } + + address = HAL_CpuAddrToDmaAddr(address); + + offset = ((address & (CACHE_LINE_SIZE - 1)) + sizeByte - 1) >> CACHE_LINE_SHIFT; + value = (address & ICACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_MASK) | + CACHE_M_INVALID | ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + + flags = HAL_SYS_EnterCriticalSection(); + + ICACHE->CACHE_MAINTAIN[1] = offset; + ICACHE->CACHE_MAINTAIN[0] = value; + + do { + status = ICACHE->CACHE_MAINTAIN[0] & + ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + } while (status); + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief enable performance measurement unit of icache. + * @return HAL_OK if success. + */ +HAL_Status HAL_ICACHE_EnablePMU(void) +{ +#if defined(HAL_ICACHE_MODULE_ENABLED) && defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + ICACHE->CACHE_CTRL |= ICACHE_CACHE_CTRL_CACHE_PMU_EN_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief disable performance measurement unit of icache. + * @return HAL_OK if success. + */ +HAL_Status HAL_ICACHE_DisablePMU(void) +{ +#if defined(HAL_ICACHE_MODULE_ENABLED) && defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + ICACHE->CACHE_CTRL &= (~ICACHE_CACHE_CTRL_CACHE_PMU_EN_MASK); + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief get current state of performance measurement unit in icache. + * @param stat: return the current state if success. + * @return HAL_OK if success. + */ +HAL_Status HAL_ICACHE_GetPMU(struct CACHE_PMU_CNT *stat) +{ +#if defined(HAL_ICACHE_MODULE_ENABLED) && defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + HAL_ASSERT(stat != NULL); + + flags = HAL_SYS_EnterCriticalSection(); + + stat->rdNum = ICACHE->PMU_RD_NUM_CNT; + stat->wrNum = ICACHE->PMU_WR_NUM_CNT; + stat->sramRdHit = ICACHE->PMU_SRAM_RD_HIT_CNT; + stat->hbRdHit = ICACHE->PMU_HB_RD_HIT_CNT; + stat->stbRdHit = ICACHE->PMU_STB_RD_HIT_CNT; + stat->rdHit = ICACHE->PMU_RD_HIT_CNT; + stat->wrHit = ICACHE->PMU_WR_HIT_CNT; + stat->rdMissPenalty = ICACHE->PMU_RD_MISS_PENALTY_CNT; + stat->wrMissPenalty = ICACHE->PMU_WR_MISS_PENALTY_CNT; + stat->rdLat = ICACHE->PMU_RD_LAT_CNT; + stat->wrLat = ICACHE->PMU_WR_LAT_CNT; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief Enable the interrupt of icache. + * @return HAL_OK if success. + */ +HAL_Status HAL_ICACHE_EnableInt(void) +{ +#if defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + ICACHE->CACHE_INT_EN |= ICACHE_CACHE_INT_EN_ERR_RECORD_EN_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief Disable the interrupt of icache. + * @return HAL_OK if success. + */ +HAL_Status HAL_ICACHE_DisableInt(void) +{ +#if defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + ICACHE->CACHE_INT_EN &= ~ICACHE_CACHE_INT_EN_ERR_RECORD_EN_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief Get the interrupt status of icache. + * @return HAL_TRUE if ahb error occur. + */ +HAL_Check HAL_ICACHE_GetInt(void) +{ + uint32_t status = 0; + +#if defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + + status = ICACHE->CACHE_INT_ST & ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_MASK; + +#endif + +#endif + + return status ? HAL_TRUE : HAL_FALSE; +} + +/** + * @brief Get the ahb bus error address of icache. + * @return ahb buss error address if success. + * @attention The return value is only valid if you get a ahb error from CACHE_INT_ST + */ +uint32_t HAL_ICACHE_GetErrAddr(void) +{ + uint32_t address = -1; + +#if defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + + address = ICACHE->CACHE_ERR_HADDR; + +#endif + +#endif + + return address; +} + +/** + * @brief Clear the interrupt status of icache. + * @return HAL_OK if success. + */ +HAL_Status HAL_ICACHE_ClearInt(void) +{ +#if defined(ICACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + ICACHE->CACHE_INT_ST |= ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief enable dcache. + * @return HAL_OK if success. + * @attention The MPU must be configured before cache if you need the feature. + * @attention Dynamically disable and enable dcache is not allowed. + */ +HAL_Status HAL_DCACHE_Enable(void) +{ +#if defined(HAL_DCACHE_MODULE_ENABLED) && defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + uint32_t status; + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + /* stb enable, stb_entry=7, stb_timeout enable, write back, prefetch enable */ + DCACHE->CACHE_CTRL |= + DCACHE_CACHE_CTRL_CACHE_EN_MASK + | (7U << DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT) + | DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_MASK; + DCACHE->STB_TIMEOUT_CTRL = 1; + + /* if mpu has been enable, we will enable cache mpu function */ +#ifdef MPU + if (HAL_MPU_IsEnable()) { + DCACHE->CACHE_CTRL |= DCACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK; + } +#endif + + do { + status = + DCACHE->CACHE_STATUS & DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK; + } while (status == 0); + + DCACHE->CACHE_CTRL &= ~DCACHE_CACHE_CTRL_CACHE_BYPASS_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief disable dcache. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_Disable(void) +{ +#if defined(HAL_DCACHE_MODULE_ENABLED) && defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_CTRL |= DCACHE_CACHE_CTRL_CACHE_BYPASS_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief invalidate all of the dcache. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_Invalidate(void) +{ +#if defined(HAL_DCACHE_MODULE_ENABLED) && defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + uint32_t status = 0; + unsigned long flags; + + if ((uint32_t)DCACHE == (uint32_t)ICACHE) { + if (DCACHE->CACHE_CTRL & DCACHE_CACHE_CTRL_CACHE_WT_EN_MASK) { + return HAL_OK; + } else { + return HAL_INVAL; + } + } + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_MAINTAIN[0] = + CACHE_M_INVALID_ALL | DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + + do { + status = DCACHE->CACHE_MAINTAIN[0] & + DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + } while (status); + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief invalidate the specified region of the dcache. + * @param address: the start address of specified region which you want invalidate. + * @param sizeByte: the length in bytes of invalidate range. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_InvalidateByRange(uint32_t address, + uint32_t sizeByte) +{ +#if defined(HAL_DCACHE_MODULE_ENABLED) && defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + uint32_t value = 0; + uint32_t offset = 0; + uint32_t status = 0; + unsigned long flags; + + if (sizeByte == 0) { + return HAL_OK; + } + + offset = ((address & (CACHE_LINE_SIZE - 1)) + sizeByte - 1) >> CACHE_LINE_SHIFT; + value = (address & DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_MASK) | + CACHE_M_INVALID | DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_MAINTAIN[1] = offset; + DCACHE->CACHE_MAINTAIN[0] = value; + + do { + status = DCACHE->CACHE_MAINTAIN[0] & + DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + } while (status); + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief clean the specified region of the dcache, it will flush the dirty cache in + * the specified region. + * @param address: the start address of specified region which you want invalidate. + * @param sizeByte: the length in bytes of invalidate range. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_CleanByRange(uint32_t address, + uint32_t sizeByte) +{ +#if defined(HAL_DCACHE_MODULE_ENABLED) && defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + uint32_t value = 0; + uint32_t offset = 0; + uint32_t status = 0; + unsigned long flags; + + if (sizeByte == 0) { + return HAL_OK; + } + + offset = ((address & (CACHE_LINE_SIZE - 1)) + sizeByte - 1) >> CACHE_LINE_SHIFT; + value = (address & DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_MASK) | + CACHE_M_CLEAN | DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_MAINTAIN[1] = offset; + DCACHE->CACHE_MAINTAIN[0] = value; + + do { + status = DCACHE->CACHE_MAINTAIN[0] & + DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + } while (status); + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief clean and invalidate the specified region of the dcache, it will flush the dirty + * cache in the specified region, and set the cache line to invalid state. + * @param address: the start address of specified region which you want invalidate. + * @param sizeByte: the length in bytes of invalidate range. + * @return HAL_OK if success. + */ +HAL_Status +HAL_DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t sizeByte) +{ +#if defined(HAL_DCACHE_MODULE_ENABLED) && defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + uint32_t value = 0; + uint32_t offset = 0; + uint32_t status = 0; + unsigned long flags; + + if (sizeByte == 0) { + return HAL_OK; + } + + offset = ((address & (CACHE_LINE_SIZE - 1)) + sizeByte - 1) >> CACHE_LINE_SHIFT; + value = (address & DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_MASK) | + CACHE_M_CLEAN_INVALID | DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_MAINTAIN[1] = offset; + DCACHE->CACHE_MAINTAIN[0] = value; + + do { + status = DCACHE->CACHE_MAINTAIN[0] & + DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK; + } while (status); + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief clean and invalidate all of the dcache, the dirty cache line will be flush + * to external memory, and all of the cache line will be set invalid. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_CleanInvalidate(void) +{ +#if defined(HAL_DCACHE_MODULE_ENABLED) && defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + uint32_t status = 0; + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_CTRL |= DCACHE_CACHE_CTRL_CACHE_FLUSH_MASK; + + do { + status = + DCACHE->CACHE_STATUS & DCACHE_CACHE_STATUS_CACHE_FLUSH_DONE_MASK; + } while (!status); + + DCACHE->CACHE_CTRL &= ~DCACHE_CACHE_CTRL_CACHE_FLUSH_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief enable performance measurement unit of dcache. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_EnablePMU(void) +{ +#if defined(HAL_DCACHE_MODULE_ENABLED) && defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_CTRL |= DCACHE_CACHE_CTRL_CACHE_PMU_EN_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief disable performance measurement unit of dcache. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_DisablePMU(void) +{ +#if defined(HAL_DCACHE_MODULE_ENABLED) && defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_CTRL &= (~DCACHE_CACHE_CTRL_CACHE_PMU_EN_MASK); + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief get current state of performance measurement unit in icache. + * @param stat: return the current state if success. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_GetPMU(struct CACHE_PMU_CNT *stat) +{ +#if defined(HAL_DCACHE_MODULE_ENABLED) && defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + HAL_ASSERT(stat != NULL); + + flags = HAL_SYS_EnterCriticalSection(); + + stat->rdNum = DCACHE->PMU_RD_NUM_CNT; + stat->wrNum = DCACHE->PMU_WR_NUM_CNT; + stat->sramRdHit = DCACHE->PMU_SRAM_RD_HIT_CNT; + stat->hbRdHit = DCACHE->PMU_HB_RD_HIT_CNT; + stat->stbRdHit = DCACHE->PMU_STB_RD_HIT_CNT; + stat->rdHit = DCACHE->PMU_RD_HIT_CNT; + stat->wrHit = DCACHE->PMU_WR_HIT_CNT; + stat->rdMissPenalty = DCACHE->PMU_RD_MISS_PENALTY_CNT; + stat->wrMissPenalty = DCACHE->PMU_WR_MISS_PENALTY_CNT; + stat->rdLat = DCACHE->PMU_RD_LAT_CNT; + stat->wrLat = DCACHE->PMU_WR_LAT_CNT; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief Enable the interrupt of dcache. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_EnableInt(void) +{ +#if defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_INT_EN |= DCACHE_CACHE_INT_EN_ERR_RECORD_EN_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief Disable the interrupt of dcache. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_DisableInt(void) +{ +#if defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_INT_EN &= ~DCACHE_CACHE_INT_EN_ERR_RECORD_EN_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief Get the interrupt status of dcache. + * @return HAL_TRUE if ahb error occur. + */ +HAL_Check HAL_DCACHE_GetInt(void) +{ + uint32_t status = 0; + +#if defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + + status = DCACHE->CACHE_INT_ST & DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_MASK; + +#endif + +#endif + + return status ? HAL_TRUE : HAL_FALSE; +} + +/** + * @brief Clear the interrupt status of dcache. + * @return HAL_OK if success. + */ +HAL_Status HAL_DCACHE_ClearInt(void) +{ +#if defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + unsigned long flags; + + flags = HAL_SYS_EnterCriticalSection(); + + DCACHE->CACHE_INT_ST |= DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_MASK; + + HAL_SYS_ExitCriticalSection(flags); +#endif + +#endif + + return HAL_OK; +} + +/** + * @brief Get the ahb bus error address of dcache. + * @return ahb buss error address if success. + * @attention The return value is only valid if you get a ahb error from CACHE_INT_ST + */ +uint32_t HAL_DCACHE_GetErrAddr(void) +{ + uint32_t address = -1; + +#if defined(DCACHE) + +#if defined(CACHE_REVISION) && (CACHE_REVISION == 0x00000100U) + + address = DCACHE->CACHE_ERR_HADDR; + +#endif + +#endif + + return address; +} + +/** @} */ + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_debug.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_debug.c new file mode 100644 index 00000000000..ad690b3fdca --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_debug.c @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup DEBUG + * @{ + */ + +/** @defgroup DEBUG_How_To_Use How To Use + * @{ + + The DEBUG driver can be used as follows: + + Implement DBG hook: + + - printf func: define new HAL_SYSLOG in hal_conf.h or use HAL_DBG_Printf() in default; + - assert func: redefine AssertFailed(). + + Define debug level in hal_conf.h: + + - HAL_DBG_ON: print master switch; + - HAL_DBG_INFO_ON: information printing switch; + - HAL_DBG_WRN_ON: information printing switch; + - HAL_DBG_ERR_ON: information printing switch; + - HAL_ASSERT_ON: Support assert. + + APIS: + + - printf information by calling HAL_DBG(); + - printf warning by calling HAL_DBG_WRN(); + - printf error by calling HAL_DBG_ERR(); + - do assert by calling HAL_ASSERT(). + + @} */ + +#include "hal_base.h" + +/** @defgroup DEBUG_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup DEBUG_Exported_Functions_Group5 Other Functions + + This section provides functions allowing to init and deinit module as follows: + + * @{ + */ + +/** + * @brief Reports the name of the source file and the source line number + * where the HAL_ASSERT error has occurred. + * @param file: pointer to the source file name + * @param line: HAL_ASSERT error line source number + */ +__WEAK void HAL_AssertFailed(const char *file, uint32_t line) +{ + HAL_DBG_ERR("assert failed at %s %lu\n", file, line); + while (1) { + ; + } +} + +/** + * @brief format hex print. + * @param s: head tag for every new line. + * @param buf: buffer for printing. + * @param width: every single printed object width. + * @param len: the number of printed objects. + * @return HAL_Status: HAL_OK. + * sum = width * len (BYTE). + */ +HAL_Status HAL_DBG_HEX(char *s, void *buf, uint32_t width, uint32_t len) +{ +#ifdef HAL_DBG_ON + uint32_t i, j; + unsigned char *p8 = (unsigned char *)buf; + unsigned short *p16 = (unsigned short *)buf; + uint32_t *p32 = (uint32_t *)buf; + + j = 0; + for (i = 0; i < len; i++) { + if (j == 0) { + HAL_SYSLOG("[HAL_DBG_HEX] %s %p + 0x%lx:", s, buf, i * width); + } + + if (width == 4) { + HAL_SYSLOG("0x%08lx,", p32[i]); + } else if (width == 2) { + HAL_SYSLOG("0x%04x,", p16[i]); + } else { + HAL_SYSLOG("0x%02x,", p8[i]); + } + + if (++j >= 16) { + j = 0; + HAL_SYSLOG("\n"); + } + } + HAL_SYSLOG("\n"); +#endif + + return HAL_OK; +} + +/** + * @brief format and print data + * @param format: format printf param. + * @return int32_t. + */ +__WEAK int32_t HAL_DBG_Printf(const char *format, ...) +{ + return 0; +} + +/** @} */ + +/** @} */ + +/** @} */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_dwdma.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_dwdma.c new file mode 100644 index 00000000000..3946a47c4b5 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_dwdma.c @@ -0,0 +1,990 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_DWDMA_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup DWDMA + * @{ + */ + +/** @defgroup DWDMA_How_To_Use How To Use + * @{ + + The DWDMA driver can be used as follows: + + - Invoke HAL_DWDMA_Init() to initialize dma. + - Invoke HAL_DWDMA_RequestChannel() to request a available dma channel. + - Invoke HAL_DWDMA_Config() to config dma transfer config. + - Invoke HAL_DWDMA_PrepDmaSingle()/HAL_DWDMA_PrepDmaCyclic() for single/cyclic transfer. + - Invoke HAL_DWDMA_Start() to start a ready dma transfer. + - Invoke HAL_DWDMA_Stop() to stop the dma channel. + - Invoke HAL_DWDMA_ReleaseChannel() to release the dma channel. + - Invoke HAL_DWDMA_DeInit() to deinitialize dma. + - More details refer to APIs' descriptions as below. + + @} */ + +/** @defgroup DWDMA_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define DW_CHAN_SET_BIT(reg, mask) \ + WRITE_REG(reg, ((mask) << 8) | (mask)) +#define DW_CHAN_CLEAR_BIT(reg, mask) \ + WRITE_REG(reg, ((mask) << 8) | 0) + +#define DWC_DEFAULT_CTLLO(_dwc) ({ \ + struct DMA_SLAVE_CONFIG *_config = &(_dwc)->config; \ + bool _islave = HAL_DMA_IsSlaveDirection((_dwc)->direction); \ + uint8_t _smSize = _islave ? _config->srcMaxBurst : \ + DWDMA_MSIZE_256; \ + uint8_t _dmSize = _islave ? _config->dstMaxBurst : \ + DWDMA_MSIZE_256; \ + \ + (DWC_CTLL_DST_MSIZE(_dmSize) \ + | DWC_CTLL_SRC_MSIZE(_smSize) \ + | DWC_CTLL_LLP_D_EN \ + | DWC_CTLL_LLP_S_EN \ + | DWC_CTLL_DMS((_dwc)->dstMaster) \ + | DWC_CTLL_SMS((_dwc)->srcMaster)); \ + }) + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +__STATIC_INLINE void DWC_DumpRegs(struct DWDMA_CHAN *dwc) +{ + HAL_DBG("SAR: 0x%08lx DAR: 0x%08lx LLP: 0x%08lx CTL: 0x%08lx:%08lx\n", + READ_REG(dwc->creg->SAR), READ_REG(dwc->creg->DAR), + READ_REG(dwc->creg->LLP), READ_REG(dwc->creg->CTL_HI), + READ_REG(dwc->creg->CTL_LO)); +} + +/** + * Fix config's burst len to bit. + */ +__STATIC_INLINE void DW_ConvertBurst(uint16_t *maxburst) +{ + uint32_t val; + + switch (*maxburst) { + case 1: + val = 0; + break; + case 4: + val = 1; + break; + case 8: + val = 2; + break; + case 16: + val = 3; + break; + case 32: + val = 4; + break; + case 64: + val = 5; + break; + case 128: + val = 6; + break; + case 256: + val = 7; + break; + default: + val = 0; + break; + } + + *maxburst = val; +} + +/** + * Get burst len from bit. + * refer to MSIZE of register CTLx[13:11]. + */ +__STATIC_INLINE uint32_t DW_GetBurstLength(uint32_t val) +{ + uint32_t len = 1; + + if (val >= 1 && val <= 7) { + len = 1 << (val + 1); + } + + return len; +} + +__STATIC_INLINE uint32_t DW_FFS(uint32_t word) +{ +#ifdef __GNUC__ + HAL_ASSERT(word); + + return (__builtin_ffs(word) - 1); +#else + int num = 0; + + HAL_ASSERT(word); + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) { + num += 1; + } + + return num; +#endif +} + +static void DWDMA_off(struct HAL_DWDMA_DEV *dw) +{ + struct DMA_REG *reg = dw->pReg; + + WRITE_REG(reg->DMACFGREG, 0); + + DW_CHAN_CLEAR_BIT(reg->MASK.TFR, dw->allChanMask); + DW_CHAN_CLEAR_BIT(reg->MASK.BLOCK, dw->allChanMask); + DW_CHAN_CLEAR_BIT(reg->MASK.SRCTRAN, dw->allChanMask); + DW_CHAN_CLEAR_BIT(reg->MASK.DSTTRAN, dw->allChanMask); + DW_CHAN_CLEAR_BIT(reg->MASK.ERR, dw->allChanMask); + + while (READ_REG(reg->DMACFGREG) & DW_CFG_DMA_EN) { + ; + } +} + +static void DWDMA_on(struct HAL_DWDMA_DEV *dw) +{ + struct DMA_REG *reg = dw->pReg; + + WRITE_REG(reg->DMACFGREG, DW_CFG_DMA_EN); +} + +static void DWC_initialize(struct DWDMA_CHAN *dwc) +{ + struct HAL_DWDMA_DEV *dw = dwc->dw; + uint32_t cfghi = DWC_CFGH_FIFO_MODE; + uint32_t cfglo = 0; + + switch (dwc->direction) { + case DMA_MEM_TO_DEV: + cfglo |= dwc->cyclic ? DWC_CFGL_RELOAD_DAR : 0; + cfghi |= DWC_CFGH_DST_PER(dwc->periId); + break; + case DMA_DEV_TO_MEM: + cfglo |= dwc->cyclic ? DWC_CFGL_RELOAD_SAR : 0; + cfghi |= DWC_CFGH_SRC_PER(dwc->periId); + break; + default: + break; + } + + WRITE_REG(dwc->creg->CFG_LO, cfglo); + WRITE_REG(dwc->creg->CFG_HI, cfghi); + + /* Enable interrupts */ + DW_CHAN_SET_BIT(dw->pReg->MASK.TFR, dwc->mask); + DW_CHAN_SET_BIT(dw->pReg->MASK.ERR, dwc->mask); + if (dwc->cyclic) { + DW_CHAN_SET_BIT(dw->pReg->MASK.BLOCK, dwc->mask); + } +} + +static void DWC_deinitialize(struct DWDMA_CHAN *dwc) +{ + struct HAL_DWDMA_DEV *dw = dwc->dw; + + /* Disable interrupts */ + DW_CHAN_CLEAR_BIT(dw->pReg->MASK.TFR, dwc->mask); + DW_CHAN_CLEAR_BIT(dw->pReg->MASK.ERR, dwc->mask); + DW_CHAN_CLEAR_BIT(dw->pReg->MASK.BLOCK, dwc->mask); + + /* Clear interrupts. */ + WRITE_REG(dw->pReg->CLEAR.TFR, dwc->mask); + WRITE_REG(dw->pReg->CLEAR.SRCTRAN, dwc->mask); + WRITE_REG(dw->pReg->CLEAR.DSTTRAN, dwc->mask); + WRITE_REG(dw->pReg->CLEAR.ERR, dwc->mask); + WRITE_REG(dw->pReg->CLEAR.BLOCK, dwc->mask); +} + +static void DWC_HandleCyclic(struct HAL_DWDMA_DEV *dw, struct DWDMA_CHAN *dwc, + uint32_t statusBlock, uint32_t statusErr, uint32_t statusXfer) +{ + if (statusBlock & dwc->mask) { + if (!dwc->paused) { + WRITE_REG(dw->pReg->CLEAR.BLOCK, dwc->mask); + } + } + + /* TODO: execption handler */ + HAL_ASSERT(!statusErr && !statusXfer); + + if (!dwc->paused) { + DW_CHAN_SET_BIT(dw->pReg->MASK.BLOCK, dwc->mask); + } +} + +static void DWC_HandleError(struct HAL_DWDMA_DEV *dw, struct DWDMA_CHAN *dwc) +{ + HAL_DBG("%s: %d\n", __func__, __LINE__); + + /* TODO: error handler */ + DWC_DumpRegs(dwc); + WRITE_REG(dw->pReg->CLEAR.ERR, dwc->mask); +} + +static void DWC_HandleXfer(struct HAL_DWDMA_DEV *dw, struct DWDMA_CHAN *dwc) +{ + HAL_DBG("%s: %d\n", __func__, __LINE__); + + WRITE_REG(dw->pReg->CLEAR.TFR, dwc->mask); +} + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup DWDMA_Exported_Functions_Group2 State and Errors Functions + + This section provides functions allowing to get the status of the module: + + * @{ + */ + +/** @} */ + +/** @defgroup DWDMA_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +/** + * @brief DW DMA Get Raw Block Status + * + * @param dw: the handle of dw dma. + * + * @return raw block status + */ +uint32_t HAL_DWDMA_GetRawBlockStatus(struct HAL_DWDMA_DEV *dw) +{ + return READ_REG(dw->pReg->RAW.BLOCK); +} + +/** + * @brief DW DMA Get Raw Err Status + * + * @param dw: the handle of dw dma. + * + * @return raw err status + */ +uint32_t HAL_DWDMA_GetRawErrStatus(struct HAL_DWDMA_DEV *dw) +{ + return READ_REG(dw->pReg->RAW.ERR); +} + +/** + * @brief DW DMA Get Raw Xfer Status + * + * @param dw: the handle of dw dma. + * + * @return raw xfer status + */ +uint32_t HAL_DWDMA_GetRawXferStatus(struct HAL_DWDMA_DEV *dw) +{ + return READ_REG(dw->pReg->RAW.TFR); +} + +/** + * @brief Initializes a specific dw dma. + * + * @param dw: the handle of dw dma. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_DWDMA_Init(struct HAL_DWDMA_DEV *dw) +{ + int i; + struct DMA_REG *reg = dw->pReg; + struct DWDMA_CHAN *dwc; + + HAL_ASSERT(dw); + +#ifdef HAL_DWDMA_BLOCK_ALIGN_SZ + HAL_ASSERT(HAL_DWDMA_BLOCK_ALIGN_SZ); + dw->blockSize &= ~(HAL_DWDMA_BLOCK_ALIGN_SZ - 1); +#endif + /* Calculate all channel mask before DMA setup */ + dw->allChanMask = (1 << dw->maxChans) - 1; + /* Force dma off, just in case */ + DWDMA_off(dw); + + for (i = 0; i < dw->maxChans; i++) { + dwc = &dw->chan[i]; + + dwc->dw = dw; + dwc->creg = &(dw->pReg->CHAN[i]); + dwc->mask = 1 << i; + /* clear bit */ + DW_CHAN_CLEAR_BIT(reg->CHENREG, dwc->mask); + + dwc->direction = DMA_TRANS_NONE; + } + + /* Clear all interrupts on all channels. */ + WRITE_REG(reg->CLEAR.TFR, dw->allChanMask); + WRITE_REG(reg->CLEAR.BLOCK, dw->allChanMask); + WRITE_REG(reg->CLEAR.SRCTRAN, dw->allChanMask); + WRITE_REG(reg->CLEAR.DSTTRAN, dw->allChanMask); + WRITE_REG(reg->CLEAR.ERR, dw->allChanMask); + + return HAL_OK; +} + +/** + * @brief DeInitializes a specific dw dma. + * + * @param dw: the handle of dw dma. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_DWDMA_DeInit(struct HAL_DWDMA_DEV *dw) +{ + HAL_ASSERT(dw); + + DWDMA_off(dw); + + DW_CHAN_CLEAR_BIT(dw->pReg->CHENREG, dw->allChanMask); + + return HAL_OK; +} + +/** @} */ + +/** @defgroup DWDMA_Exported_Functions_Group3 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ + +/** + * @brief Pause the dma chan. + * + * @param dwc: the handle of dma chan. + * + * @return + * - HAL_OK on success + * - HAL_ERROR on other failures + */ +HAL_Status HAL_DWDMA_Pause(struct DWDMA_CHAN *dwc) +{ + dwc->paused = true; + + return HAL_OK; +} + +/** + * @brief Resume the dma chan. + * + * @param dwc: the handle of dma chan. + * + * @return + * - HAL_OK on success + * - HAL_ERROR on other failures + */ +HAL_Status HAL_DWDMA_Resume(struct DWDMA_CHAN *dwc) +{ + if (!dwc->paused) { + return HAL_OK; + } + + dwc->paused = false; + + WRITE_REG(dwc->dw->pReg->CLEAR.BLOCK, dwc->mask); + DW_CHAN_SET_BIT(dwc->dw->pReg->MASK.BLOCK, dwc->mask); + + return HAL_OK; +} + +/** + * @brief Start to run the dma chan. + * + * @param dwc: the handle of dma chan. + * + * @return + * - HAL_OK on success + * - HAL_BUSY if chan is busy + * - HAL_ERROR on other failures + */ +HAL_Status HAL_DWDMA_Start(struct DWDMA_CHAN *dwc) +{ + struct HAL_DWDMA_DEV *dw; + struct DMA_REG *reg; + struct DW_DESC *desc = &dwc->desc[0]; + uint32_t ctllo = desc->lli.ctllo; + + HAL_ASSERT(dwc); + + dw = dwc->dw; + reg = dw->pReg; + + if (READ_REG(reg->CHENREG) & dwc->mask) { + HAL_DBG("%s: chan is not idle\n", __func__); + DWC_DumpRegs(dwc); + + return HAL_ERROR; + } + + DWC_initialize(dwc); + + desc = &dwc->desc[0]; + WRITE_REG(dwc->creg->LLP, (uint32_t)desc); + + ctllo = desc->lli.ctllo; + switch (dwc->direction) { + case DMA_MEM_TO_DEV: + ctllo |= DWC_CTLL_LLP_S_EN; + break; + case DMA_DEV_TO_MEM: + ctllo |= DWC_CTLL_LLP_D_EN; + break; + case DMA_MEM_TO_MEM: + ctllo |= DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN; + break; + default: + break; + } + + WRITE_REG(dwc->creg->CTL_LO, ctllo); + WRITE_REG(dwc->creg->CTL_HI, 0); + + DW_CHAN_SET_BIT(dw->pReg->CHENREG, dwc->mask); + + return HAL_OK; +} + +/** + * @brief Stop the dma chan. + * + * @param dwc: the handle of dma chan. + * + * @return + * - HAL_OK on success + * - HAL_BUSY if dma is busy + * - HAL_ERROR on other failures + */ +HAL_Status HAL_DWDMA_Stop(struct DWDMA_CHAN *dwc) +{ + struct HAL_DWDMA_DEV *dw; + + HAL_ASSERT(dwc); + + dw = dwc->dw; + + DW_CHAN_CLEAR_BIT(dw->pReg->CHENREG, dwc->mask); + while (READ_REG(dw->pReg->CHENREG) & dwc->mask) { + ; + } + + DWC_deinitialize(dwc); + + return HAL_OK; +} + +/** + * @brief Handle dma chan + * + * @param dw: the handle of dw dma. + * @param chanId: the chan num. + * + * @return raw irq status + */ +uint32_t HAL_DWDMA_HandleChan(struct HAL_DWDMA_DEV *dw, uint32_t chanId) +{ + struct DWDMA_CHAN *dwc = &dw->chan[chanId]; + uint32_t statusBlock; + uint32_t statusXfer; + uint32_t statusErr; + + statusBlock = READ_REG(dw->pReg->RAW.BLOCK); + statusXfer = READ_REG(dw->pReg->RAW.TFR); + statusErr = READ_REG(dw->pReg->RAW.ERR); + + if (dwc->cyclic) { + DWC_HandleCyclic(dw, dwc, statusBlock, statusXfer, statusXfer); + } else if (statusErr & dwc->mask) { + DWC_HandleError(dw, dwc); + } else if (statusXfer & dwc->mask) { + DWC_HandleXfer(dw, dwc); + } + + return (statusBlock & dwc->mask) | (statusXfer & dwc->mask); +} + +/** + * @brief dw dma IrqHandler + * + * @param dw: the handle of dw dma. + * @param chanId: the chan num. + * + * @return raw irq status + */ +uint32_t HAL_DWDMA_IrqHandler(struct HAL_DWDMA_DEV *dw, uint32_t chanId) +{ + struct DWDMA_CHAN *dwc = &dw->chan[chanId]; + uint32_t status = 0; + + DW_CHAN_CLEAR_BIT(dw->pReg->MASK.TFR, dwc->mask); + DW_CHAN_CLEAR_BIT(dw->pReg->MASK.BLOCK, dwc->mask); + DW_CHAN_CLEAR_BIT(dw->pReg->MASK.ERR, dwc->mask); + + status = HAL_DWDMA_HandleChan(dw, chanId); + + /* Re-enable interrupts */ + DW_CHAN_SET_BIT(dw->pReg->MASK.TFR, dwc->mask); + DW_CHAN_SET_BIT(dw->pReg->MASK.ERR, dwc->mask); + + return status; +} + +/** + * @brief Get the dma channel + * + * @param dw: the handle of dw dma. + * @param chanId: the chan id. + * + * @return the dma channel by chan id or NULL on error. + */ +struct DWDMA_CHAN *HAL_DWDMA_GetChannel(struct HAL_DWDMA_DEV *dw, uint32_t chanId) +{ + HAL_ASSERT(dw); + + if (chanId > dw->maxChans) { + return NULL; + } + + return &dw->chan[chanId]; +} + +/** + * @brief Request a dma channel + * + * @param dw: the handle of dw dma. + * @param id: the peri id. + * + * @return a idle dma channel. + * @note must hold lock. + */ +struct DWDMA_CHAN *HAL_DWDMA_RequestChannel(struct HAL_DWDMA_DEV *dw, DMA_REQ_Type id) +{ + struct DWDMA_CHAN *dwc = NULL; + int i; + + HAL_ASSERT(dw); + + if (!dw->used) { + DWDMA_on(dw); + } + + for (i = 0; i < dw->maxChans; i++) { + dwc = &dw->chan[i]; + + if (dw->used & dwc->mask) { + continue; + } + + dwc->periId = id; + dwc->chanId = i; + dw->used |= dwc->mask; + break; + } + + if (i >= dw->maxChans || !dwc) { + return NULL; + } + + return dwc; +} + +/** + * @brief Release a dma channel + * + * @param dwc: the handle of dma chan. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + * @note must hold lock. + */ +HAL_Status HAL_DWDMA_ReleaseChannel(struct DWDMA_CHAN *dwc) +{ + struct HAL_DWDMA_DEV *dw; + + HAL_ASSERT(dwc); + + dw = dwc->dw; + + dwc->periId = 0xff; + + dwc->srcMaster = 0; + dwc->dstMaster = 0; + + dwc->cyclic = false; + + /* Disable interrupts */ + DW_CHAN_CLEAR_BIT(dw->pReg->MASK.TFR, dwc->mask); + DW_CHAN_CLEAR_BIT(dw->pReg->MASK.BLOCK, dwc->mask); + DW_CHAN_CLEAR_BIT(dw->pReg->MASK.ERR, dwc->mask); + + dw->used &= ~dwc->mask; + if (!dw->used) { + DWDMA_off(dw); + } + + return HAL_OK; +} + +/** + * @brief Config a dma channel + * + * @param dwc: the handle of dma chan. + * @param config: the peri req config. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_DWDMA_Config(struct DWDMA_CHAN *dwc, struct DMA_SLAVE_CONFIG *config) +{ + memcpy(&dwc->config, config, sizeof(*config)); + dwc->direction = config->direction; + + DW_ConvertBurst(&dwc->config.srcMaxBurst); + DW_ConvertBurst(&dwc->config.dstMaxBurst); + + return HAL_OK; +} + +/** + * @brief Prepare a cyclic dma transfer for the channel + * + * @param dwc: the handle of dma chan. + * @param dmaAddr: the memory addr. + * @param len: data len. + * @param periodLen: periodic len. + * @param direction: transfer direction. + * @param callback: callback function. + * @param cparam: callback param. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_DWDMA_PrepDmaCyclic(struct DWDMA_CHAN *dwc, uint32_t dmaAddr, + uint32_t len, uint32_t periodLen, + eDMA_TRANSFER_DIRECTION direction, + DMA_Callback callback, void *cparam) +{ + HAL_UNUSED struct HAL_DWDMA_DEV *dw; + struct DMA_SLAVE_CONFIG *config; + struct DW_DESC *desc, *last = NULL; + uint32_t regWidth; + uint32_t periods; + uint32_t i; + + HAL_ASSERT(dwc); + + dw = dwc->dw; + config = &dwc->config; + + HAL_ASSERT(HAL_DMA_IsSlaveDirection(direction)); + + dwc->direction = direction; + + if (direction == DMA_MEM_TO_DEV) { + regWidth = DW_FFS(config->dstAddrWidth); + WRITE_REG(dwc->creg->DAR, config->dstAddr); + } else { + regWidth = DW_FFS(config->srcAddrWidth); + WRITE_REG(dwc->creg->SAR, config->srcAddr); + } + + periods = len / periodLen; + + /* Check for too big/unaligned periods and unaligned DMA buffer. */ +#ifdef HAL_DWDMA_BLOCK_ALIGN_SZ + HAL_ASSERT(HAL_IS_ALIGNED(periodLen, HAL_DWDMA_BLOCK_ALIGN_SZ)); +#endif + HAL_ASSERT(periodLen <= (dw->blockSize << regWidth)); + HAL_ASSERT(!(periodLen & ((1 << regWidth) - 1))); + HAL_ASSERT(!(dmaAddr & ((1 << regWidth) - 1))); + + for (i = 0; i < periods; i++) { + desc = &dwc->desc[i]; + + HAL_ASSERT(desc); + + switch (direction) { + case DMA_MEM_TO_DEV: + desc->lli.dar = config->dstAddr; + desc->lli.sar = dmaAddr + (periodLen * i); + desc->lli.ctllo = (DWC_DEFAULT_CTLLO(dwc) + | DWC_CTLL_DST_WIDTH(regWidth) + | DWC_CTLL_SRC_WIDTH(regWidth) + | DWC_CTLL_DST_FIX + | DWC_CTLL_SRC_INC + | DWC_CTLL_INT_EN + | DWC_CTLL_FC_M2P); + + desc->lli.ctllo &= ~DWC_CTLL_LLP_D_EN; + + break; + case DMA_DEV_TO_MEM: + desc->lli.dar = dmaAddr + (periodLen * i); + desc->lli.sar = config->srcAddr; + desc->lli.ctllo = (DWC_DEFAULT_CTLLO(dwc) + | DWC_CTLL_SRC_WIDTH(regWidth) + | DWC_CTLL_DST_WIDTH(regWidth) + | DWC_CTLL_DST_INC + | DWC_CTLL_SRC_FIX + | DWC_CTLL_INT_EN + | DWC_CTLL_FC_P2M); + + desc->lli.ctllo &= ~DWC_CTLL_LLP_S_EN; + + break; + default: + break; + } + + desc->lli.ctlhi = (periodLen >> regWidth); + if (last) { + last->lli.llp = (uint32_t)desc; + } + + last = desc; + } + + /* cyclic */ + last->lli.llp = (uint32_t)&dwc->desc[0]; + dwc->cyclic = true; + dwc->callback = callback; + dwc->cparam = cparam; + + HAL_DCACHE_CleanByRange((uint32_t)dwc->desc, + NR_DESCS_PER_CHANNEL * sizeof(*(dwc->desc))); + + return HAL_OK; +} + +/** + * @brief Prepare a single dma transfer for the channel + * + * @param dwc: the handle of dma chan. + * @param dmaAddr: the memory addr. + * @param len: data len. + * @param direction: transfer direction. + * @param callback: callback function. + * @param cparam: callback param. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_DWDMA_PrepDmaSingle(struct DWDMA_CHAN *dwc, uint32_t dmaAddr, + uint32_t len, + eDMA_TRANSFER_DIRECTION direction, + DMA_Callback callback, void *cparam) +{ + struct HAL_DWDMA_DEV *dw; + struct DMA_SLAVE_CONFIG *config; + struct DW_DESC *desc, *last = NULL; + uint32_t regWidth; + uint32_t xferCount; + uint32_t offset; + uint32_t src, dst; + uint32_t ctllo; + uint32_t burstLen; + uint32_t i = 0; + + HAL_ASSERT(dwc); + + dw = dwc->dw; + config = &dwc->config; + + HAL_ASSERT(HAL_DMA_IsSlaveDirection(direction)); + + dwc->direction = direction; + + if (direction == DMA_MEM_TO_DEV) { + burstLen = config->dstMaxBurst; + regWidth = DW_FFS(config->dstAddrWidth); + src = dmaAddr; + dst = config->dstAddr; + ctllo = (DWC_DEFAULT_CTLLO(dwc) + | DWC_CTLL_SRC_WIDTH(regWidth) + | DWC_CTLL_DST_WIDTH(regWidth) + | DWC_CTLL_DST_FIX + | DWC_CTLL_SRC_INC + | DWC_CTLL_FC_M2P); + } else { + burstLen = config->srcMaxBurst; + regWidth = DW_FFS(config->srcAddrWidth); + src = config->srcAddr; + dst = dmaAddr; + ctllo = (DWC_DEFAULT_CTLLO(dwc) + | DWC_CTLL_SRC_WIDTH(regWidth) + | DWC_CTLL_DST_WIDTH(regWidth) + | DWC_CTLL_DST_INC + | DWC_CTLL_SRC_FIX + | DWC_CTLL_FC_P2M); + } + + burstLen = DW_GetBurstLength(burstLen); + + for (offset = 0; offset < len; offset += xferCount << regWidth) { + xferCount = HAL_MIN((len - offset) >> regWidth, dw->blockSize); + xferCount &= ~(burstLen - 1); + desc = &dwc->desc[i]; + desc->lli.sar = (ctllo & DWC_CTLL_SRC_FIX) ? src : src + offset; + desc->lli.dar = (ctllo & DWC_CTLL_DST_FIX) ? dst : dst + offset; + desc->lli.ctllo = ctllo; + desc->lli.ctlhi = xferCount; + desc->len = xferCount << regWidth; + + if (last) { + last->lli.llp = (uint32_t)desc; + } + + last = desc; + + i++; + } + + last->lli.ctllo |= DWC_CTLL_INT_EN; + last->lli.llp = 0; + + dwc->callback = callback; + dwc->cparam = cparam; + + HAL_DCACHE_CleanByRange((uint32_t)dwc->desc, + NR_DESCS_PER_CHANNEL * sizeof(*(dwc->desc))); + + return HAL_OK; +} + +/** + * @brief Prepare a dma memcpy + * + * @param dwc: the handle of dma chan. + * @param dst: the memory dst addr. + * @param src: the memory src addr. + * @param len: data len. + * @param callback: callback function. + * @param cparam: callback param. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_DWDMA_PrepDmaMemcpy(struct DWDMA_CHAN *dwc, uint32_t dst, + uint32_t src, uint32_t len, + DMA_Callback callback, void *cparam) +{ + struct HAL_DWDMA_DEV *dw; + struct DW_DESC *desc, *last = NULL; + uint32_t xferCount; + uint32_t offset; + uint32_t srcWidth; + uint32_t dstWidth; + uint32_t dataWidth; + uint32_t ctllo; + int i = 0; + + HAL_ASSERT(dwc); + HAL_ASSERT(len); + + dw = dwc->dw; + + dwc->direction = DMA_MEM_TO_MEM; + + dataWidth = dw->dataWidth; + + srcWidth = dstWidth = DW_FFS(dataWidth | src | dst | len); + + ctllo = DWC_DEFAULT_CTLLO(dwc) + | DWC_CTLL_DST_WIDTH(dstWidth) + | DWC_CTLL_SRC_WIDTH(srcWidth) + | DWC_CTLL_DST_INC + | DWC_CTLL_SRC_INC + | DWC_CTLL_FC_M2M; + + for (offset = 0; offset < len; offset += xferCount << srcWidth) { + xferCount = HAL_MIN((len - offset) >> srcWidth, dw->blockSize); + + desc = &dwc->desc[i]; + + desc->lli.sar = src + offset; + desc->lli.dar = dst + offset; + desc->lli.ctllo = ctllo; + desc->lli.ctlhi = xferCount; + desc->len = xferCount << srcWidth; + + if (last) { + last->lli.llp = (uint32_t)desc; + } + + last = desc; + + i++; + } + + last->lli.ctllo |= DWC_CTLL_INT_EN; + last->lli.llp = 0; + + dwc->callback = callback; + dwc->cparam = cparam; + + HAL_DCACHE_CleanByRange((uint32_t)dwc->desc, + NR_DESCS_PER_CHANNEL * sizeof(*(dwc->desc))); + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_DWDMA_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_gpio.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_gpio.c new file mode 100644 index 00000000000..da2e5006261 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_gpio.c @@ -0,0 +1,495 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_GPIO_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_How_To_Use How To Use + * @{ + + The GPIO driver can be used as follows: + APIs for GPIO io read write: + 1) HAL_GPIO_GetPinLevel to get EXT port level. + 2) HAL_GPIO_SetPinLevel to set io level. + 3) HAL_GPIO_SetPinDirection to set io direction. + + APIs for GPIO IRQ: + 1) HAL_GPIO_EnableIRQ to enable a GPIO IRQ. + 2) HAL_GPIO_DisableIRQ to disable a GPIO IRQ. + 3) HAL_GPIO_IRQHandler to handle GPIO IRQ isr. + 4) HAL_GPIO_IRQDispatch to dispatch GPIO IRQ, should be implemented by User. + + @} */ + +/** @defgroup GPIO_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define UNUSED(X) (void)(X) /* To avoid gcc/g++ warnings */ + +/********************* Private Function Definition ***************************/ + +/** + * @brief Set the GPIO IRQ end of interrupt(EOI). + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + */ +static void GPIO_SetEOI(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->PORT_EOI_H = pin | (pin >> 16); + } else { + pin &= 0x0000FFFF; + pGPIO->PORT_EOI_L = pin | (pin << 16); + } +#else + { + pGPIO->PORTA_EOI = pin; + } +#endif +} + +/** + * @brief Get GPIO all pins irq type. + * @param pGPIO: the GPIO struct. + * @return uint32_t: type value. + */ +static uint32_t GPIO_GetIntType(struct GPIO_REG *pGPIO) +{ + uint32_t type; + +#if (GPIO_VER_ID == 0x01000C2BU) + type = (pGPIO->INT_TYPE_L & 0xffff); + type |= ((pGPIO->INT_TYPE_H & 0xffff) << 16); + type |= (pGPIO->INT_BOTHEDGE_L & 0xffff); + type |= ((pGPIO->INT_BOTHEDGE_H & 0xffff) << 16); +#else + type = pGPIO->INTTYPE_LEVEL; + #ifdef SOC_RK1808 + type |= pGPIO->INT_BOTHEDGE; + #endif +#endif + + return type; +} + +/** + * @brief Get GPIO all pins irq status. + * @param pGPIO: the GPIO struct. + * @return uint32_t: status value. + */ +static uint32_t GPIO_GetIntStatus(struct GPIO_REG *pGPIO) +{ + return pGPIO->INT_STATUS; +} + +/** @} */ +/********************* Public Function Definition ***************************/ + +/** @defgroup GPIO_Exported_Functions_Group1 State and Errors Functions + + This section provides functions allowing to get the status of the module: + + * @{ + */ + +/** + * @brief GPIO Configure IRQ trigger type. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param mode: The value defined in @ref eGPIO_intType. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode) +{ + uint32_t both = 0, type = 0, plar = 0; + + UNUSED(both); + + switch (mode) { + case GPIO_INT_TYPE_EDGE_RISING: + type = 1; + plar = 1; + both = 0; + break; + case GPIO_INT_TYPE_EDGE_FALLING: + type = 1; + plar = 0; + both = 0; + break; + case GPIO_INT_TYPE_LEVEL_HIGH: + type = 0; + plar = 1; + both = 0; + break; + case GPIO_INT_TYPE_LEVEL_LOW: + type = 0; + plar = 0; + both = 0; + break; + case GPIO_INT_TYPE_EDGE_BOTH: + type = 0; + plar = 0; + both = 1; + break; + default: + + return HAL_INVAL; + } + +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->INT_TYPE_H = (type) ? (pin | (pin >> 16)) : (pin); + pGPIO->INT_POLARITY_H = (plar) ? (pin | (pin >> 16)) : (pin); + pGPIO->INT_BOTHEDGE_H = (both) ? (pin | (pin >> 16)) : (pin); + } else { + pin &= 0x0000FFFF; + pGPIO->INT_TYPE_L = (type) ? (pin | (pin << 16)) : (pin << 16); + pGPIO->INT_POLARITY_L = (plar) ? (pin | (pin << 16)) : (pin << 16); + pGPIO->INT_BOTHEDGE_L = (both) ? (pin | (pin << 16)) : (pin << 16); + } +#else + { + pGPIO->INTTYPE_LEVEL = (type) ? (pin) : (pGPIO->INTTYPE_LEVEL & ~(pin)); + pGPIO->INT_POLARITY = (plar) ? (pin) : (pGPIO->INT_POLARITY & ~(pin)); + #ifdef SOC_RK1808 + pGPIO->INT_BOTHEDGE = (both) ? (pin) : (pGPIO->INT_BOTHEDGE & ~(pin)); + #endif + } +#endif + + return HAL_OK; +} + +/** + * @brief Set GPIO direction. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param direction: direction value defined in @ref eGPIO_pinDirection. + * @return HAL_Status: HAL_OK if success. + */ +HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->SWPORT_DDR_H = (direction == GPIO_OUT) ? (pin | (pin >> 16)) : (pin); + } else { + pin &= 0x0000FFFF; + pGPIO->SWPORT_DDR_L = (direction == GPIO_OUT) ? (pin | (pin << 16)) : (pin << 16); + } +#else + { + pGPIO->SWPORTA_DDR = (direction == GPIO_OUT) ? (pin) : (pGPIO->SWPORTA_DDR & ~(pin)); + } +#endif + + return HAL_OK; +} + +/** + * @brief Set GPIO direction. + * @param pGPIO: the GPIO struct. + * @param mPins: The pins defined in @ref ePINCTRL_GPIO_PINS. + * @param direction: value defined in @ref eGPIO_pinDirection. + * @return HAL_Status: HAL_OK if success. + */ +HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction) +{ + uint8_t pin; + HAL_Status rc; + + HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO)); + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = HAL_GPIO_SetPinDirection(pGPIO, (1 << pin), direction); + if (rc) { + return rc; + } + } + } + + return HAL_OK; +} + +/** + * @brief Get GPIO Pin data direction value. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @retval eGPIO_pinDirection: data direction value. + */ +eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ + eGPIO_pinDirection direction; + uint32_t value; + +#if (GPIO_VER_ID == 0x01000C2BU) + value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DDR_H & (pin >> 16)) : (pGPIO->SWPORT_DDR_L & pin); +#else + value = pGPIO->SWPORTA_DDR & pin; +#endif + + if (value != (uint32_t)GPIO_IN) { + direction = GPIO_OUT; + } else { + direction = GPIO_IN; + } + + return direction; +} + +/** + * @brief Set GPIO pin level. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param level: The level defined in @ref eGPIO_pinLevel. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->SWPORT_DR_H = (level == GPIO_HIGH) ? (pin | (pin >> 16)) : (pin); + } else { + pin &= 0x0000FFFF; + pGPIO->SWPORT_DR_L = (level == GPIO_HIGH) ? (pin | (pin << 16)) : (pin << 16); + } +#else + { + pGPIO->SWPORTA_DR = (level == GPIO_HIGH) ? (pin) : (pGPIO->SWPORTA_DR & ~(pin)); + } +#endif + + return HAL_OK; +} + +/** + * @brief Set GPIO pin level. + * @param pGPIO: The pointer of GPIO struct. + * @param mPins: The pins defined in @ref ePINCTRL_GPIO_PINS. + * @param level: The level defined in @ref eGPIO_pinLevel. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level) +{ + uint8_t pin; + HAL_Status rc; + + HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO)); + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = HAL_GPIO_SetPinLevel(pGPIO, (1 << pin), level); + if (rc) { + return rc; + } + } + } + + return HAL_OK; +} + +/** @} */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ + +/** + * @brief Get GPIO Pin data value. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @retval eGPIO_pinLevel: data value. + */ +eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ + eGPIO_pinLevel level; + uint32_t value; + +#if (GPIO_VER_ID == 0x01000C2BU) + value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DR_H & (pin >> 16)) : (pGPIO->SWPORT_DR_L & pin); +#else + value = pGPIO->SWPORTA_DR & pin; +#endif + + if (value != (uint32_t)GPIO_LOW) { + level = GPIO_HIGH; + } else { + level = GPIO_LOW; + } + + return level; +} + +/** + * @brief Get GPIO Pin ext bank level. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @retval GPIO_PinState: ext bank value. + */ +eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ + uint32_t value; + +#if (GPIO_VER_ID == 0x01000C2BU) + value = (pGPIO->EXT_PORT & pin); +#else + value = (pGPIO->EXT_PORTA & pin); +#endif + + return (value == (uint32_t)GPIO_LOW) ? GPIO_LOW : GPIO_HIGH; +} + +/** + * @brief Get GPIO Pin ext bank level. + * @param pGPIO: the GPIO struct. + * @retval uint32_t: ext bank value. + */ +uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO) +{ + uint32_t value; + +#if (GPIO_VER_ID == 0x01000C2BU) + value = (pGPIO->EXT_PORT); +#else + value = (pGPIO->EXT_PORTA); +#endif + + return value; +} +/** @} */ + +/** @defgroup GPIO_Exported_Functions_Group3 Other Functions + * @{ + */ + +/** + * @brief Set GPIO irq enable. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + */ +void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_H = pin; +#endif + pGPIO->INT_EN_H = pin | (pin >> 16); + } else { + pin &= 0x0000FFFF; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_L = pin << 16; +#endif + pGPIO->INT_EN_L = pin | (pin << 16); + } +#else + { + pGPIO->INTEN |= pin; + pGPIO->INTMASK &= ~pin; + } +#endif +} + +/** + * @brief Set GPIO irq disable. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + */ +void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->INT_EN_H = pin; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_H = pin | (pin >> 16); +#endif + } else { + pin &= 0x0000FFFF; + pGPIO->INT_EN_L = pin << 16; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_L = pin | (pin << 16); +#endif + } +#else + { + pGPIO->INTEN &= ~pin; + pGPIO->INTMASK |= pin; + } +#endif +} + +/** + * @brief GPIO IRQ callbacks. + * @param bank: The bank id. + * @param pin: The true pin index, 0~31. + * NOTE: This function Should not be modified, when the callback is needed, + * the HAL_GPIO_IRQDispatch could be implemented in the user file. + */ +__WEAK void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin) +{ + UNUSED(bank); + UNUSED(pin); +} + +/** + * @brief GPIO IRQ hanlder. + * @param pGPIO: The pointer of GPIO struct. + * @param bank: The bank id. + */ +void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank) +{ + uint32_t stat, type, clear; + uint32_t i; + uint32_t pin; + + stat = GPIO_GetIntStatus(pGPIO); + type = GPIO_GetIntType(pGPIO); + + /* Then process each pending GPIO interrupt */ + for (i = 0x0U; i < PIN_NUMBER_PER_BANK && stat != 0; i++) { + clear = 0x1U << i; + pin = HAL_BIT(i); + + if ((stat & clear) != 0x0U) { + /* If gpio is Edge-sensitive triggered, clear eoi */ + if (type & clear) { + GPIO_SetEOI(pGPIO, pin); + } + + /* Remove the pending interrupt bit from the clear */ + stat &= ~clear; + + /* And disptach the GPIO interrupt to the handler */ + HAL_GPIO_IRQDispatch(bank, i); + } + } +} +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_nvic.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_nvic.c new file mode 100644 index 00000000000..b2263f9a1db --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_nvic.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_NVIC_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup NVIC + * @{ + */ + +/** @defgroup NVIC_How_To_Use How To Use + * @{ + + The NVIC driver can be used as follows: + + @} */ + +/** @defgroup NVIC_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup NVIC_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief Set interrupt handler. + * @param IRQn: interrupt number. + * @param handler: NVIC_IRQHandler. + * @return HAL_OK. + */ +HAL_Status HAL_NVIC_SetIRQHandler(IRQn_Type IRQn, NVIC_IRQHandler handler) +{ +#if __VTOR_PRESENT + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + /* cortex m0 has no vtor, the vector table alway based 0x0*/ + uint32_t *vectors = (uint32_t *)0x0U; +#endif + + vectors[IRQn + NVIC_PERIPH_IRQ_OFFSET] = (uint32_t)handler; + + return HAL_OK; +} + +/** + * @brief Get interrupt handler. + * @param IRQn: interrupt number + * @return NVIC_IRQHandler. + */ +NVIC_IRQHandler HAL_NVIC_GetIRQHandler(IRQn_Type IRQn) +{ +#if __VTOR_PRESENT + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + /* cortex m0 has no vtor, the vector table alway based 0x0*/ + uint32_t *vectors = (uint32_t *)0x0U; +#endif + + return (NVIC_IRQHandler)(vectors[IRQn + NVIC_PERIPH_IRQ_OFFSET]); +} + +/** + * @brief Set interrupt priority group. + * @return priorityGroup: priority group. + * @return HAL_OK. + */ +HAL_Status HAL_NVIC_SetPriorityGrouping(eNVIC_PriorityGroup priorityGroup) +{ + NVIC_SetPriorityGrouping(priorityGroup); + + return HAL_OK; +} + +/** + * @brief Get interrupt priority group. + * @return uint32_t: priority group. + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Set interrupt priority. + * @param IRQn: interrupt number. + * @param preemptPriority: preemt priority. + * @param subPriority: sub priority. + * @return HAL_OK. + */ +HAL_Status HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t preemptPriority, uint32_t subPriority) +{ + uint32_t prioritygroup = 0x00U; + + /* Check the parameters */ + HAL_ASSERT(IS_NVIC_SUB_PRIORITY(subPriority)); + HAL_ASSERT(IS_NVIC_PREEMPTION_PRIORITY(preemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, preemptPriority, subPriority)); + + return HAL_OK; +} + +/** + * @brief Get interrupt priority. + * @param IRQn: interrupt number + * @return HAL_OK. + */ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) +{ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Enabled interrupt. + * @param IRQn: interrupt number + * @return HAL_OK. + */ +HAL_Status HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC_EnableIRQ(IRQn); + + return HAL_OK; +} + +/** + * @brief Disable interrupt. + * @param IRQn: interrupt number + * @return HAL_OK. + */ +HAL_Status HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC_DisableIRQ(IRQn); + + return HAL_OK; +} + +/** + * @brief Pending interrupt. + * @param IRQn: interrupt number + * @return HAL_OK. + */ +HAL_Status HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC_SetPendingIRQ(IRQn); + + return HAL_OK; +} + +/** + * @brief Check whether the interrupt is suspended. + * @param IRQn: interrupt number + * @return int: if is pending return 1, or 0. + */ +HAL_Check HAL_NVIC_IsPendingIRQ(IRQn_Type IRQn) +{ + return (HAL_Check)(NVIC_GetPendingIRQ(IRQn)); +} + +/** + * @brief Clear pending interrupt. + * @param IRQn: interrupt number + * @return None. + */ +HAL_Status HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC_ClearPendingIRQ(IRQn); + + return HAL_OK; +} + +/** + * @brief Register peripheral interrupt handle and priority. + * @param IRQn: interrupt number. + * @param handler: interrupt handle. + * @param preemptPriority: preemt priority. + * @param subPriority: sub priority. + * @return None. + */ +HAL_Status HAL_NVIC_ConfigExtIRQ(IRQn_Type IRQn, NVIC_IRQHandler handler, + uint32_t preemptPriority, uint32_t subPriority) +{ + HAL_NVIC_SetIRQHandler(IRQn, handler); + HAL_NVIC_SetPriority(IRQn, preemptPriority, subPriority); + HAL_NVIC_EnableIRQ(IRQn); + + return HAL_OK; +} + +/** + * @brief Init NVIC Interrupt Controller. + * @return None. + */ +HAL_Status HAL_NVIC_Init(void) +{ + /* Use HardFault */ + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_NVIC_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pd.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pd.c new file mode 100644 index 00000000000..167b2c4a445 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pd.c @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_PMU_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PD + * @{ + */ + +/** @defgroup PD_How_To_Use How To Use + * @{ + + The PD driver can be used as follows: + + - Invoke HAL_PD_Setting in each device power on/off its own Pd. + - The order of setting power domain. + + power on: + set power domain on + leave idle + power off: + request ilde + set power domain off + + - The PD ID is include shift information: + + [3:0]: power on shift + [7:4]: power on status shift + [11:8]: idle request shift + [15:12]: idle status shift + [19:16]: ack status shift + + - PD driver is just responsible for passing simple command data, And + the usecount is the user's responsibility. Protection the usecount at the driver layer. + - More details refer to APIs' descriptions as below. + + @} */ + +/** @defgroup PD_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define PD_PWR_SHIFT 0U +#define PD_PWR_MASK 0x0000000FU +#define PD_ST_SHIFT 4U +#define PD_ST_MASK 0x000000F0U +#define PD_REQ_SHIFT 8U +#define PD_REQ_MASK 0x00000F00U +#define PD_IDLE_SHIFT 12U +#define PD_IDLE_MASK 0x0000F000U +#define PD_ACK_SHIFT 16U +#define PD_ACK_MASK 0x000F0000U +#define PD_VALID_SHIFT 31U +#define PD_VALID_MASK 0x80000000U + +#define PD_GET_PWR_SHIFT(x) (((uint32_t)(x)&PD_PWR_MASK) >> PD_PWR_SHIFT) +#define PD_GET_ST_SHIFT(x) (((uint32_t)(x)&PD_ST_MASK) >> PD_ST_SHIFT) +#define PD_GET_REQ_SHIFT(x) (((uint32_t)(x)&PD_REQ_MASK) >> PD_REQ_SHIFT) +#if defined(SOC_RK1808) +#define PD_GET_IDLE_SHIFT(x) ((((uint32_t)(x)&PD_IDLE_MASK) >> PD_IDLE_SHIFT) + 16) +#else +#define PD_GET_IDLE_SHIFT(x) (((uint32_t)(x)&PD_IDLE_MASK) >> PD_IDLE_SHIFT) +#endif +#define PD_GET_ACK_SHIFT(x) (((uint32_t)(x)&PD_ACK_MASK) >> PD_ACK_SHIFT) + +#define PD_IS_INVALID(x) (!(((uint32_t)(x)&PD_VALID_MASK) >> PD_VALID_SHIFT)) + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +static HAL_Check PD_IsIdle(ePD_Id pd) +{ + uint32_t idleShift = PD_GET_IDLE_SHIFT(pd); + + return (HAL_Check)((PMU->BUS_IDLE_ST & (1 << idleShift)) >> idleShift); +} + +#if defined(SOC_RK1808) +static HAL_Check PD_ReadAck(ePD_Id pd) +{ + uint32_t ackShift = PD_GET_ACK_SHIFT(pd); + + return (HAL_Check)((PMU->BUS_IDLE_ST & (1 << ackShift)) >> ackShift); +} +#else +static HAL_Check PD_ReadAck(ePD_Id pd) +{ + uint32_t ackShift = PD_GET_ACK_SHIFT(pd); + + return (HAL_Check)((PMU->BUS_IDLE_ACK & (1 << ackShift)) >> ackShift); +} +#endif + +static HAL_Check PD_IsOn(ePD_Id pd) +{ + uint32_t stShift = PD_GET_ST_SHIFT(pd); + + /* check idle status for idle-only domains */ + + if (stShift > 16) { + return PD_IsIdle(pd) ? HAL_FALSE : HAL_TRUE; + } + + return (HAL_Check)(!((PMU->PWRDN_ST & (1 << stShift)) >> stShift)); +} + +static HAL_Status PD_IdleRequest(ePD_Id pd, HAL_Check idle) +{ + uint32_t reqShift = PD_GET_REQ_SHIFT(pd); + uint32_t start, timeoutMs = 1000; + + if (reqShift > 16) { + return HAL_INVAL; + } + + PMU->BUS_IDLE_REQ = VAL_MASK_WE(1U << reqShift, (idle ? 1U : 0U) << reqShift); + + /* Wait util idle_ack = 1 */ + start = HAL_GetTick(); + + while (PD_ReadAck(pd) != idle) { + if ((HAL_GetTick() - start) > timeoutMs) { + return HAL_TIMEOUT; + } + } + + start = HAL_GetTick(); + while (PD_IsIdle(pd) != idle) { + if ((HAL_GetTick() - start) > timeoutMs) { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +static HAL_Status PD_PowerOn(ePD_Id pd, HAL_Check on) +{ + uint32_t pwrShift = PD_GET_PWR_SHIFT(pd); + uint32_t start, timeoutMs = 1000; + + if (pwrShift > 16) { + return HAL_INVAL; + } + + PMU->PWRDN_CON = VAL_MASK_WE(1U << pwrShift, (on ? 0U : 1U) << pwrShift); + + start = HAL_GetTick(); + + while (PD_IsOn(pd) != on) { + if ((HAL_GetTick() - start) > timeoutMs) { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup PD_Exported_Functions_Group5 Other Functions + * @attention these APIs allow direct use in the HAL layer. + * @{ + */ + +/** + * @brief Pd setting on + * @param pd: pd id + * @return HAL_Status + */ +HAL_Status HAL_PD_On(ePD_Id pd) +{ + HAL_Status error; + + if (PD_IS_INVALID(pd)) { + return HAL_INVAL; + } + + if (PD_IsOn(pd)) { + return HAL_OK; + } + + error = PD_PowerOn(pd, HAL_TRUE); + if (error) { + return error; + } + + /* if powering up, leave idle mode */ + error = PD_IdleRequest(pd, HAL_FALSE); + + return error; +} + +/** + * @brief Pd setting off + * @param pd: pd id + * @return HAL_Status + */ +HAL_Status HAL_PD_Off(ePD_Id pd) +{ + HAL_Status error; + + if (PD_IS_INVALID(pd)) { + return HAL_INVAL; + } + + if (!PD_IsOn(pd)) { + return HAL_OK; + } + + /* if powering down, idle request to NIU first */ + error = PD_IdleRequest(pd, HAL_TRUE); + if (error) { + return error; + } + + error = PD_PowerOn(pd, HAL_FALSE); + + return error; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_PMU_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pl330.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pl330.c new file mode 100644 index 00000000000..c01849ddd58 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pl330.c @@ -0,0 +1,2012 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_PL330_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PL330 + * @{ + */ + +/** @defgroup PL330_How_To_Use How To Use + * @{ + + The PL330 driver can be used as follows: + + - Invoke HAL_PL330_Init to initialize pl330. + - Invoke HAL_PL330_RequestChannel to request a available dma channel. + - Invoke HAL_PL330_Config to config dma transfer config. + - Invoke HAL_PL330_PrepDmaSingle/Cyclic for single/cyclic transfer. + - Invoke HAL_PL330_Start to start a ready dma transfer. + - Invoke HAL_PL330_Stop to stop the dma channel. + - Invoke HAL_PL330_ReleaseChannel to release the dma channel. + - Invoke HAL_PL330_DeInit to deinitialize pl330. + - More details refer to APIs' descriptions as below. + + @} */ + +/** @defgroup PL330_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#ifdef PL330_DEBUG_MCGEN +static uint32_t s_cmdLine; +#define PL330_DBGCMD_DUMP(off, x...) \ + do { \ + HAL_DBG("%lx:", s_cmdLine); \ + HAL_DBG(x); \ + s_cmdLine += off; \ + } while (0) +#define PL330_DBGMC_START(addr) (s_cmdLine = addr) +#else +#define PL330_DBGCMD_DUMP(off, x...) \ + do { \ + } while (0) +#define PL330_DBGMC_START(addr) \ + do { \ + } while (0) +#endif + +#ifndef PL330_MAX_WAIT +#define PL330_MAX_WAIT 4000 +#endif + +#define DMAC_MODE_NS HAL_BIT(0) + +#define DS_ST_STOP 0x0 +#define DS_ST_EXEC 0x1 +#define DS_ST_CMISS 0x2 +#define DS_ST_UPDTPC 0x3 +#define DS_ST_WFE 0x4 +#define DS_ST_ATBRR 0x5 +#define DS_ST_QBUSY 0x6 +#define DS_ST_WFP 0x7 +#define DS_ST_KILL 0x8 +#define DS_ST_CMPLT 0x9 +#define DS_ST_FLTCMP 0xe +#define DS_ST_FAULT 0xf + +#define CC_SRCINC HAL_BIT(0) +#define CC_DSTINC HAL_BIT(14) +#define CC_SRCPRI HAL_BIT(8) +#define CC_DSTPRI HAL_BIT(22) +#define CC_SRCNS HAL_BIT(9) +#define CC_DSTNS HAL_BIT(23) +#define CC_SRCIA HAL_BIT(10) +#define CC_DSTIA HAL_BIT(24) +#define CC_SRCBRSTLEN_SHFT 4 +#define CC_DSTBRSTLEN_SHFT 18 +#define CC_SRCBRSTSIZE_SHFT 1 +#define CC_DSTBRSTSIZE_SHFT 15 +#define CC_SRCCCTRL_SHFT 11 +#define CC_SRCCCTRL_MASK 0x7 +#define CC_DSTCCTRL_SHFT 25 +#define CC_DRCCCTRL_MASK 0x7 +#define CC_SWAP_SHFT 28 + +#define CR0_PERIPH_REQ_SET HAL_BIT(0) +#define CR0_BOOT_EN_SET HAL_BIT(1) +#define CR0_BOOT_MAN_NS HAL_BIT(2) +#define CR0_NUM_CHANS_SHIFT 4 +#define CR0_NUM_CHANS_MASK 0x7 +#define CR0_NUM_PERIPH_SHIFT 12 +#define CR0_NUM_PERIPH_MASK 0x1f +#define CR0_NUM_EVENTS_SHIFT 17 +#define CR0_NUM_EVENTS_MASK 0x1f + +#define CR1_ICACHE_LEN_SHIFT 0 +#define CR1_ICACHE_LEN_MASK 0x7 +#define CR1_NUM_ICACHELINES_SHIFT 4 +#define CR1_NUM_ICACHELINES_MASK 0xf + +#define CRD_DATA_WIDTH_SHIFT 0 +#define CRD_DATA_WIDTH_MASK 0x7 +#define CRD_WR_CAP_SHIFT 4 +#define CRD_WR_CAP_MASK 0x7 +#define CRD_WR_Q_DEP_SHIFT 8 +#define CRD_WR_Q_DEP_MASK 0xf +#define CRD_RD_CAP_SHIFT 12 +#define CRD_RD_CAP_MASK 0x7 +#define CRD_RD_Q_DEP_SHIFT 16 +#define CRD_RD_Q_DEP_MASK 0xf +#define CRD_DATA_BUFF_SHIFT 20 +#define CRD_DATA_BUFF_MASK 0x3ff + +#define PART 0x330 +#define DESIGNER 0x41 +#define REVISION 0x0 +#define INTEG_CFG 0x0 +#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) + +#define PL330_DS_DMA_STATUS 0x0f +#define PL330_DS_DMA_STATUS_STOPPED 0x00 +#define PL330_DBGSTATUS_BUSY 0x01 +#define PL330_CS_ACTIVE_MASK 0x07 +#define PL330_CR1_I_CACHE_LEN_MASK 0x07 +#define PL330_INTCLR_ALL_MASK 0xff + +#define CMD_DMAADDH 0x54 +#define CMD_DMAEND 0x00 +#define CMD_DMAFLUSHP 0x35 +#define CMD_DMAGO 0xa0 +#define CMD_DMALD 0x04 +#define CMD_DMALDP 0x25 +#define CMD_DMALP 0x20 +#define CMD_DMALPEND 0x28 +#define CMD_DMAKILL 0x01 +#define CMD_DMAMOV 0xbc +#define CMD_DMANOP 0x18 +#define CMD_DMARMB 0x12 +#define CMD_DMASEV 0x34 +#define CMD_DMAST 0x08 +#define CMD_DMASTP 0x29 +#define CMD_DMASTZ 0x0c +#define CMD_DMAWFE 0x36 +#define CMD_DMAWFP 0x30 +#define CMD_DMAWMB 0x13 + +#define SZ_DMAADDH 3 +#define SZ_DMAEND 1 +#define SZ_DMAFLUSHP 2 +#define SZ_DMALD 1 +#define SZ_DMALDP 2 +#define SZ_DMALP 2 +#define SZ_DMALPEND 2 +#define SZ_DMAKILL 1 +#define SZ_DMAMOV 6 +#define SZ_DMANOP 1 +#define SZ_DMARMB 1 +#define SZ_DMASEV 2 +#define SZ_DMAST 1 +#define SZ_DMASTP 2 +#define SZ_DMASTZ 1 +#define SZ_DMAWFE 2 +#define SZ_DMAWFP 2 +#define SZ_DMAWMB 1 +#define SZ_DMAGO 6 + +#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) +#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) + +#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) +#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) +#define BYTE_MOD_BURST_LEN(b, ccr) (((b) / BRST_SIZE(ccr)) % BRST_LEN(ccr)) + +/* + * PL330_DBGINST0 - constructs the word for the Debug Instruction-0 Register. + * @b1: Instruction byte 1 + * @b0: Instruction byte 0 + * @ch: channel number + * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel + */ +#define PL330_DBGINST0(b1, b0, ch, dbg_th) \ + (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1))) + +/********************* Private Structure Definition **************************/ + +typedef enum { + SAR = 0, + CCR, + DAR, +} eDMAMOV_DST; + +typedef enum { + SRC = 0, + DST, +} ePL330_DST; + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +__STATIC_INLINE int PL330_Instr_DMAADDH(uint8_t dryRun, char *buf, + ePL330_DST da, uint16_t val) +{ + if (dryRun) { + return SZ_DMAADDH; + } + + *buf = CMD_DMAADDH; + *buf |= (da << 1); + *((uint16_t *)(buf + 1)) = val; + + PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", + da == DST ? "DA" : "SA", val); + + return SZ_DMAADDH; +} + +__STATIC_INLINE int PL330_Instr_DMAEND(uint8_t dryRun, char *buf) +{ + if (dryRun) { + return SZ_DMAEND; + } + /* + * DMAEND encoding: + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 0 0 0 + */ + *buf = CMD_DMAEND; + + PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); + + return SZ_DMAEND; +} + +__STATIC_INLINE void PL330_Memcpy4(char *dst, char *src) +{ + *dst = *src; + *(dst + 1) = *(src + 1); + *(dst + 2) = *(src + 2); + *(dst + 3) = *(src + 3); +} + +__STATIC_INLINE int PL330_Instr_DMAGO(uint8_t dryRun, char *buf, uint8_t cn, + uint32_t imm, uint8_t ns) +{ + if (dryRun) { + return SZ_DMAGO; + } + /* + * DMAGO encoding: + * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 + * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0 + * + * 47 ... 16 + * imm[32:0] + */ + *buf = CMD_DMAGO | ((ns << 1) & 0x02); + + *(buf + 1) = (uint8_t)(cn & 0x07); + + PL330_Memcpy4(buf + 2, (char *)&imm); + + return SZ_DMAGO; +} + +__STATIC_INLINE int PL330_Instr_DMALP(uint8_t dryRun, char *buf, uint8_t lc, + uint16_t loops) +{ + if (dryRun) { + return SZ_DMALP; + } + /* + * DMALP encoding + * 15 ... 8 7 6 5 4 3 2 1 0 + * | iter[7:0] |0 0 1 0 0 0 lc 0 + */ + *buf = (uint8_t)(CMD_DMALP | ((lc & 1) << 1)); + *(buf + 1) = (uint8_t)(loops - 1); + + PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", lc ? '1' : '0', loops - 1); + + return SZ_DMALP; +} + +__STATIC_INLINE int PL330_Instr_DMAMOV(uint8_t dryRun, char *buf, uint8_t rd, + uint32_t imm) +{ + if (dryRun) { + return SZ_DMAMOV; + } + /* + * DMAMOV encoding + * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0 + * + * 47 ... 16 + * imm[32:0] + * + * rd: b000 for SAR, b001 CCR, b010 DAR + */ + *buf = CMD_DMAMOV; + *(buf + 1) = rd & 0x7; + PL330_Memcpy4(buf + 2, (char *)&imm); + + PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%lx\n", + rd == SAR ? "SAR" : (rd == DAR ? "DAR" : "CCR"), imm); + + return SZ_DMAMOV; +} + +HAL_UNUSED __STATIC_INLINE int PL330_Instr_DMANOP(uint8_t dryRun, char *buf) +{ + if (dryRun) { + return SZ_DMANOP; + } + /* + * DMANOP encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 1 0 0 0 + */ + *buf = CMD_DMANOP; + + PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); + + return SZ_DMANOP; +} + +HAL_UNUSED __STATIC_INLINE int PL330_Instr_DMARMB(uint8_t dryRun, char *buf) +{ + if (dryRun) { + return SZ_DMARMB; + } + /* + * DMARMB encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 0 0 1 0 + */ + *buf = CMD_DMARMB; + + PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); + + return SZ_DMARMB; +} + +__STATIC_INLINE int PL330_Instr_DMASEV(uint8_t dryRun, char *buf, uint8_t event) +{ + if (dryRun) { + return SZ_DMASEV; + } + /* + * DMASEV encoding + * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0 + * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0 + */ + *buf = CMD_DMASEV; + *(buf + 1) = (uint8_t)(event << 3); + + PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", event); + + return SZ_DMASEV; +} + +HAL_UNUSED __STATIC_INLINE int PL330_Instr_DMAWMB(uint8_t dryRun, char *buf) +{ + if (dryRun) { + return SZ_DMAWMB; + } + /* + * DMAWMB encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 0 0 1 0 + */ + *buf = CMD_DMAWMB; + + PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); + + return SZ_DMAWMB; +} + +__STATIC_INLINE int PL330_Instr_DMAFLUSHP(uint8_t dryRun, char *buf, + uint8_t peri) +{ + if (dryRun) { + return SZ_DMAFLUSHP; + } + /* + * DMAFLUSHP encoding + * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0 + * |perip[4:0]| 0 0 0 0 0 1 1 0 1 0 1 + */ + *buf = CMD_DMAFLUSHP; + + peri &= 0x1f; + peri <<= 3; + *(buf + 1) = peri; + + PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); + + return SZ_DMAFLUSHP; +} + +__STATIC_INLINE int PL330_Instr_DMALD(uint8_t dryRun, char *buf, + ePL330_COND cond) +{ + if (dryRun) { + return SZ_DMALD; + } + /* + * DMALD encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 1 bs x + */ + *buf = CMD_DMALD; + + if (cond == SINGLE) { + *buf |= (0 << 1) | (1 << 0); + } else if (cond == BURST) { + *buf |= (1 << 1) | (1 << 0); + } + + PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", + cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); + + return SZ_DMALD; +} + +__STATIC_INLINE int PL330_Instr_DMALDP(uint8_t dryRun, char *buf, + ePL330_COND cond, uint8_t peri) +{ + if (dryRun) { + return SZ_DMALDP; + } + /* + * DMALDP encoding + * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0 + * |perip[4:0]| 0 0 0 0 0 1 0 0 1 bs 1 + */ + *buf = CMD_DMALDP; + + if (cond == BURST) { + *buf |= (1 << 1); + } + + peri &= 0x1f; + peri <<= 3; + *(buf + 1) = peri; + + PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", cond == SINGLE ? 'S' : 'B', + peri >> 3); + + return SZ_DMALDP; +} + +__STATIC_INLINE int PL330_Instr_DMALPEND(uint8_t dryRun, char *buf, + ePL330_COND cond, bool forever, + uint32_t loop, uint8_t bjump) +{ + if (dryRun) { + return SZ_DMALPEND; + } + /* + * DMALPEND encoding + * 15 ... 8 7 6 5 4 3 2 1 0 + * | backward_jump[7:0] |0 0 1 nf 1 lc bs x + */ + *buf = CMD_DMALPEND; + + if (loop) { + *buf |= (1 << 2); + } + + if (!forever) { + *buf |= (1 << 4); + } + + if (cond == SINGLE) { + *buf |= (0 << 1) | (1 << 0); + } else if (cond == BURST) { + *buf |= (1 << 1) | (1 << 0); + } + + *(buf + 1) = bjump; + + PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", + forever ? "FE" : "END", + cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), + loop ? '1' : '0', bjump); + + return SZ_DMALPEND; +} + +HAL_UNUSED __STATIC_INLINE int PL330_Instr_DMAKILL(uint8_t dryRun, char *buf) +{ + if (dryRun) { + return SZ_DMAKILL; + } + /* + * DMAKILL encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 0 0 1 + */ + *buf = CMD_DMAKILL; + + return SZ_DMAKILL; +} + +__STATIC_INLINE int PL330_Instr_DMAST(uint8_t dryRun, char *buf, + ePL330_COND cond) +{ + if (dryRun) { + return SZ_DMAST; + } + /* + * DMAST encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 1 0 bs x + */ + *buf = CMD_DMAST; + + if (cond == SINGLE) { + *buf |= (0 << 1) | (1 << 0); + } else if (cond == BURST) { + *buf |= (1 << 1) | (1 << 0); + } + + PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", + cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); + + return SZ_DMAST; +} + +__STATIC_INLINE int PL330_Instr_DMASTP(uint8_t dryRun, char *buf, + ePL330_COND cond, uint8_t peri) +{ + if (dryRun) { + return SZ_DMASTP; + } + /* + * DMASTP encoding + * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0 + * |perip[4:0]| 0 0 0 0 0 1 0 1 0 bs 1 + */ + *buf = CMD_DMASTP; + + if (cond == BURST) { + *buf |= (1 << 1); + } + + peri &= 0x1f; + peri <<= 3; + *(buf + 1) = peri; + + PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", cond == SINGLE ? 'S' : 'B', + peri >> 3); + + return SZ_DMASTP; +} + +HAL_UNUSED __STATIC_INLINE int PL330_Instr_DMASTZ(uint8_t dryRun, char *buf) +{ + if (dryRun) { + return SZ_DMASTZ; + } + /* + * DMASTZ encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 1 1 0 0 + */ + *buf = CMD_DMASTZ; + + PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); + + return SZ_DMASTZ; +} + +HAL_UNUSED __STATIC_INLINE int PL330_Instr_DMAWFE(uint8_t dryRun, char *buf, uint8_t ev, + uint32_t invalidate) +{ + if (dryRun) { + return SZ_DMAWFE; + } + /* + * DMAWFE encoding + * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0 + * |event[4:0]| 0 i 0 0 0 1 1 0 1 1 0 + */ + *buf = CMD_DMAWFE; + + ev &= 0x1f; + ev <<= 3; + *(buf + 1) = ev; + + if (invalidate) { + *(buf + 1) |= (1 << 1); + } + + PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", ev >> 3, + invalidate ? ", I" : ""); + + return SZ_DMAWFE; +} + +__STATIC_INLINE int PL330_Instr_DMAWFP(uint8_t dryRun, char *buf, + ePL330_COND cond, uint8_t peri) +{ + if (dryRun) { + return SZ_DMAWFP; + } + /* + * DMAWFP encoding + * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0 + * |perip[4:0]| 0 0 0 0 0 1 1 0 0 bs p + */ + *buf = CMD_DMAWFP; + + if (cond == SINGLE) { + *buf |= (0 << 1) | (0 << 0); + } else if (cond == BURST) { + *buf |= (1 << 1) | (0 << 0); + } else { + *buf |= (0 << 1) | (1 << 0); + } + + peri &= 0x1f; + peri <<= 3; + *(buf + 1) = peri; + + PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", + cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), + peri >> 3); + + return SZ_DMAWFP; +} + +static int _LDST_MemToMem(uint8_t dryRun, char *buf, int cyc) +{ + int off = 0; + + while (cyc--) { + off += PL330_Instr_DMALD(dryRun, &buf[off], ALWAYS); + off += PL330_Instr_DMAST(dryRun, &buf[off], ALWAYS); + } + + return off; +} + +static int _LDST_DevToMem(uint8_t dryRun, struct HAL_PL330_DEV *pl330, + char *buf, struct PL330_XFER_SPEC *pxs, int cyc) +{ + int off = 0; + ePL330_COND cond = pl330->peripReqType; + + while (cyc--) { + off += PL330_Instr_DMAWFP(dryRun, &buf[off], cond, pxs->desc->peri); + off += PL330_Instr_DMALDP(dryRun, &buf[off], cond, pxs->desc->peri); + off += PL330_Instr_DMAST(dryRun, &buf[off], ALWAYS); + off += PL330_Instr_DMAFLUSHP(dryRun, &buf[off], pxs->desc->peri); + if (pxs->desc->dstInterlaceSize) { + off += PL330_Instr_DMAADDH(dryRun, &buf[off], DST, + pxs->desc->dstInterlaceSize); + } + } + + return off; +} + +static int _LDST_MemToDev(uint8_t dryRun, struct HAL_PL330_DEV *pl330, + char *buf, struct PL330_XFER_SPEC *pxs, int cyc) +{ + int off = 0; + ePL330_COND cond = pl330->peripReqType; + + while (cyc--) { + off += PL330_Instr_DMAWFP(dryRun, &buf[off], cond, pxs->desc->peri); + off += PL330_Instr_DMALD(dryRun, &buf[off], ALWAYS); + off += PL330_Instr_DMASTP(dryRun, &buf[off], cond, pxs->desc->peri); + off += PL330_Instr_DMAFLUSHP(dryRun, &buf[off], pxs->desc->peri); + if (pxs->desc->srcInterlaceSize) { + off += PL330_Instr_DMAADDH(dryRun, &buf[off], SRC, + pxs->desc->srcInterlaceSize); + } + } + + return off; +} + +static int _Bursts(uint8_t dryRun, struct HAL_PL330_DEV *pl330, + char *buf, struct PL330_XFER_SPEC *pxs, int cyc) +{ + int off = 0; + + switch (pxs->desc->dir) { + case DMA_MEM_TO_DEV: + off += _LDST_MemToDev(dryRun, pl330, &buf[off], pxs, cyc); + break; + case DMA_DEV_TO_MEM: + off += _LDST_DevToMem(dryRun, pl330, &buf[off], pxs, cyc); + break; + case DMA_MEM_TO_MEM: + off += _LDST_MemToMem(dryRun, &buf[off], cyc); + break; + default: + off += 0x40000000; /* Scare off the Client */ + break; + } + + return off; +} + +/* Returns bytes consumed and updates bursts */ +static int _Loop(uint8_t dryRun, struct HAL_PL330_DEV *pl330, + char *buf, unsigned long *bursts, + struct PL330_XFER_SPEC *pxs) +{ + int cyc, cycmax, szlp, szlpend, szbrst, off; + uint32_t lcnt0, lcnt1, ljmp0, ljmp1; + + if (*bursts == 1) { + return _Bursts(dryRun, pl330, buf, pxs, 1); + } + + /* Max iterations possible in DMALP is 256 */ + if (*bursts >= 256 * 256) { + lcnt1 = 256; + lcnt0 = 256; + cyc = *bursts / lcnt1 / lcnt0; + } else if (*bursts > 256) { + lcnt1 = 256; + lcnt0 = *bursts / lcnt1; + cyc = 1; + } else { + lcnt1 = *bursts; + lcnt0 = 0; + cyc = 1; + } + + szlp = PL330_Instr_DMALP(1, buf, 0, 0); + szbrst = _Bursts(1, pl330, buf, pxs, 1); + szlpend = PL330_Instr_DMALPEND(1, buf, ALWAYS, false, 0, 0); + + if (lcnt0) { + szlp *= 2; + szlpend *= 2; + } + + /* + * Max bursts that we can unroll due to limit on the + * size of backward jump that can be encoded in DMALPEND + * which is 8-bits and hence 255 + */ + cycmax = (255 - (szlp + szlpend)) / szbrst; + cyc = (cycmax < cyc) ? cycmax : cyc; + off = 0; + + if (lcnt0) { + off += PL330_Instr_DMALP(dryRun, &buf[off], 0, lcnt0); + ljmp0 = off; + } + + off += PL330_Instr_DMALP(dryRun, &buf[off], 1, lcnt1); + ljmp1 = off; + + off += _Bursts(dryRun, pl330, &buf[off], pxs, cyc); + + off += + PL330_Instr_DMALPEND(dryRun, &buf[off], ALWAYS, false, 1, off - ljmp1); + + if (lcnt0) { + off += PL330_Instr_DMALPEND(dryRun, &buf[off], ALWAYS, false, 0, + off - ljmp0); + } + *bursts = lcnt1 * cyc; + if (lcnt0) { + *bursts *= lcnt0; + } + + return off; +} + +static int _Period(uint8_t dryRun, struct HAL_PL330_DEV *pl330, char *buf, + unsigned long bursts, struct PL330_XFER_SPEC *pxs, int ev) +{ + unsigned int lcnt1, ljmp1; + int cyc, off = 0; + struct PL330_XFER *x = &pxs->desc->px; + + if (bursts > 256) { + lcnt1 = 256; + cyc = bursts / 256; + } else { + lcnt1 = bursts; + cyc = 1; + } + + /* loop1 */ + off += PL330_Instr_DMALP(dryRun, &buf[off], 1, lcnt1); + ljmp1 = off; + off += _Bursts(dryRun, pl330, &buf[off], pxs, cyc); + off += + PL330_Instr_DMALPEND(dryRun, &buf[off], ALWAYS, false, 1, off - ljmp1); + + /* remainder */ + lcnt1 = bursts - (lcnt1 * cyc); + + if (lcnt1) { + off += PL330_Instr_DMALP(dryRun, &buf[off], 1, lcnt1); + ljmp1 = off; + off += _Bursts(dryRun, pl330, &buf[off], pxs, 1); + off += PL330_Instr_DMALPEND(dryRun, &buf[off], ALWAYS, false, 1, + off - ljmp1); + } + + if (!pxs->desc->srcInterlaceSize && + !pxs->desc->dstInterlaceSize && + pl330->peripReqType == BURST) { + unsigned int ccr = pxs->ccr; + unsigned long c = 0; + + c = BYTE_MOD_BURST_LEN(x->length, pxs->ccr); + + if (c) { + ccr &= ~(0xf << CC_SRCBRSTLEN_SHFT); + ccr &= ~(0xf << CC_DSTBRSTLEN_SHFT); + off += PL330_Instr_DMAMOV(dryRun, &buf[off], CCR, ccr); + off += PL330_Instr_DMALP(dryRun, &buf[off], 1, c); + ljmp1 = off; + off += _Bursts(dryRun, pl330, &buf[off], pxs, 1); + off += PL330_Instr_DMALPEND(dryRun, &buf[off], ALWAYS, false, 1, + off - ljmp1); + off += PL330_Instr_DMAMOV(dryRun, &buf[off], CCR, pxs->ccr); + } + } + + off += PL330_Instr_DMASEV(dryRun, &buf[off], ev); + + return off; +} + +static int _Loop_Cyclic(uint8_t dryRun, struct HAL_PL330_DEV *pl330, + char *buf, unsigned long bursts, + struct PL330_XFER_SPEC *pxs, int ev) +{ + int off, periods, residue, i; + unsigned int lcnt0, ljmp0, ljmpfe; + struct PL330_XFER *x = &pxs->desc->px; + + off = 0; + ljmpfe = off; + lcnt0 = pxs->desc->numPeriods; + periods = 1; + + while (lcnt0 > 256) { + periods++; + lcnt0 = pxs->desc->numPeriods / periods; + } + + residue = pxs->desc->numPeriods % periods; + + /* forever loop */ + off += PL330_Instr_DMAMOV(dryRun, &buf[off], SAR, x->srcAddr); + off += PL330_Instr_DMAMOV(dryRun, &buf[off], DAR, x->dstAddr); + off += PL330_Instr_DMAFLUSHP(dryRun, &buf[off], pxs->desc->peri); + /* loop0 */ + off += PL330_Instr_DMALP(dryRun, &buf[off], 0, lcnt0); + ljmp0 = off; + + for (i = 0; i < periods; i++) { + off += _Period(dryRun, pl330, &buf[off], bursts, pxs, ev); + } + + off += + PL330_Instr_DMALPEND(dryRun, &buf[off], ALWAYS, false, 0, off - ljmp0); + + for (i = 0; i < residue; i++) { + off += _Period(dryRun, pl330, &buf[off], bursts, pxs, ev); + } + + off += + PL330_Instr_DMALPEND(dryRun, &buf[off], ALWAYS, true, 1, off - ljmpfe); + + return off; +} + +static int _Setup_Loops(uint8_t dryRun, struct HAL_PL330_DEV *pl330, + char *buf, struct PL330_XFER_SPEC *pxs) +{ + struct PL330_XFER *x = &pxs->desc->px; + uint32_t ccr = pxs->ccr; + unsigned long c, bursts = BYTE_TO_BURST(x->length, ccr); + int off = 0; + + if (HAL_DMA_IsSlaveDirection(pxs->desc->dir)) { + off += PL330_Instr_DMAFLUSHP(dryRun, &buf[off], pxs->desc->peri); + } + + if (pxs->desc->dir == DMA_DEV_TO_MEM) { + bursts = x->length / (BRST_SIZE(ccr) * BRST_LEN(ccr) + + pxs->desc->dstInterlaceSize); + } else if (pxs->desc->dir == DMA_MEM_TO_DEV) { + bursts = x->length / (BRST_SIZE(ccr) * BRST_LEN(ccr) + + pxs->desc->srcInterlaceSize); + } + + while (bursts) { + c = bursts; + off += _Loop(dryRun, pl330, &buf[off], &c, pxs); + bursts -= c; + } + + return off; +} + +static int _Setup_Xfer(uint8_t dryRun, struct HAL_PL330_DEV *pl330, + char *buf, struct PL330_XFER_SPEC *pxs) +{ + struct PL330_XFER *x = &pxs->desc->px; + int off = 0; + + /* DMAMOV SAR, x->src_addr */ + off += PL330_Instr_DMAMOV(dryRun, &buf[off], SAR, x->srcAddr); + /* DMAMOV DAR, x->dst_addr */ + off += PL330_Instr_DMAMOV(dryRun, &buf[off], DAR, x->dstAddr); + + /* Setup Loop(s) */ + off += _Setup_Loops(dryRun, pl330, &buf[off], pxs); + + if (!pxs->desc->srcInterlaceSize && + !pxs->desc->dstInterlaceSize && + pl330->peripReqType == BURST) { + unsigned int ccr = pxs->ccr; + unsigned long c = 0; + + c = BYTE_MOD_BURST_LEN(x->length, pxs->ccr); + + if (c) { + ccr &= ~(0xf << CC_SRCBRSTLEN_SHFT); + ccr &= ~(0xf << CC_DSTBRSTLEN_SHFT); + off += PL330_Instr_DMAMOV(dryRun, &buf[off], CCR, ccr); + off += _Loop(dryRun, pl330, &buf[off], &c, pxs); + } + } + + return off; +} + +static int _Setup_Xfer_Cyclic(uint8_t dryRun, struct HAL_PL330_DEV *pl330, + char *buf, struct PL330_XFER_SPEC *pxs, int ev) +{ + struct PL330_XFER *x = &pxs->desc->px; + uint32_t ccr = pxs->ccr; + unsigned long bursts = BYTE_TO_BURST(x->length, ccr); + int off = 0; + + if (pxs->desc->dir == DMA_DEV_TO_MEM) { + bursts = x->length / (BRST_SIZE(ccr) * BRST_LEN(ccr) + + pxs->desc->dstInterlaceSize); + } else if (pxs->desc->dir == DMA_MEM_TO_DEV) { + bursts = x->length / (BRST_SIZE(ccr) * BRST_LEN(ccr) + + pxs->desc->srcInterlaceSize); + } + + /* Setup Loop(s) */ + off += _Loop_Cyclic(dryRun, pl330, &buf[off], bursts, pxs, ev); + + return off; +} + +/** + * @brief Conversion from the endian swap size to the bit encoding of the CCR + * + * @param endianSwapSize: the endian swap size, in terms of bits, it + * could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax) + * + * @return The endian swap size bit encoding for the CCR. + */ +HAL_UNUSED __STATIC_INLINE uint32_t PL330_ToendianSwapSizeBits(uint32_t endianSwapSize) +{ + switch (endianSwapSize) { + case 0: + case 8: + + return 0; + case 16: + + return 1; + case 32: + + return 2; + case 64: + + return 3; + case 128: + + return 4; + default: + + return 0; + } +} + +/** + * @brief Conversion from the burst size to the bit encoding of the CCR + * + * @param burstSize: is the burst size. It's the data width. + * In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128. + * It must be no larger than the bus width. + * + * @return The burstSize bit encoding for the CCR. + */ +static uint32_t PL330_ToBurstSizeBits(uint32_t burstSize) +{ + switch (burstSize) { + case 1: + + return 0; + case 2: + + return 1; + case 4: + + return 2; + case 8: + + return 3; + case 16: + + return 4; + case 32: + + return 5; + case 64: + + return 6; + case 128: + + return 7; + default: + + return 0; + } +} + +/** + * @brief Conversion from PL330 bus transfer descriptors to CCR value. + * + * @param rqc: request config. + * + * @return The 32-bit CCR value. + */ +static uint32_t _Prepare_CCR(struct PL330_REQCFG *rqc) +{ + uint32_t ccr = 0; + + if (rqc->srcInc) { + ccr |= CC_SRCINC; + } + + if (rqc->dstInc) { + ccr |= CC_DSTINC; + } + + /* We set same protection levels for Src and DST for now */ + if (rqc->privileged) { + ccr |= CC_SRCPRI | CC_DSTPRI; + } + if (rqc->nonsecure) { + ccr |= CC_SRCNS | CC_DSTNS; + } + if (rqc->insnaccess) { + ccr |= CC_SRCIA | CC_DSTIA; + } + + ccr |= (((rqc->brstLen - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); + ccr |= (((rqc->brstLen - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); + + ccr |= (rqc->brstSize << CC_SRCBRSTSIZE_SHFT); + ccr |= (rqc->brstSize << CC_DSTBRSTSIZE_SHFT); + + ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); + ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); + + ccr |= (rqc->swap << CC_SWAP_SHFT); + + return ccr; +} + +/* Call after fixing burst size */ +static int getBurstLen(struct PL330_DESC *desc, struct HAL_PL330_DEV *pl330, + uint32_t len) +{ + int burstLen; + + burstLen = pl330->pcfg.dataBusWidth / 8; + burstLen *= pl330->pcfg.dataBufDep / pl330->pcfg.numChan; + burstLen >>= desc->rqcfg.brstSize; + + /* src/dst_burst_len can't be more than 16 */ + if (burstLen > 16) { + burstLen = 16; + } + + while (burstLen > 1) { + if (!(len % (burstLen << desc->rqcfg.brstSize))) { + break; + } + burstLen--; + } + + return burstLen; +} + +/** + * @brief Use the debug registers to kill the DMA thread. + * + * @param reg: the DMA_REG info. + * @param channel: the DMA channel number. + * @param thread: the Debug thread encoding. + * 0: DMA manager thread, 1: DMA channel. + * + * @return 0 on success, -1 on time out + */ +static int PL330_Exec_DMAKILL(struct DMA_REG *reg, uint32_t channel, uint32_t thread) +{ + uint32_t dbgInst0; + int waitCount; + + dbgInst0 = PL330_DBGINST0(0, 0x01, channel, thread); + + /* wait while debug status is busy */ + waitCount = 0; + while ((READ_REG(reg->DBGSTATUS) & PL330_DBGSTATUS_BUSY) && + (waitCount < PL330_MAX_WAIT)) { + waitCount++; + } + + if (waitCount >= PL330_MAX_WAIT) { + /* wait time out */ + HAL_DBG("PL330 device at %p debug status busy time out\n", reg); + + return -1; + } + + /* write debug instruction 0 */ + WRITE_REG(reg->DBGINST[0], dbgInst0); + WRITE_REG(reg->DBGINST[1], 0); + + /* run the command in DbgInst0 and DbgInst1 */ + WRITE_REG(reg->DBGCMD, 0); + + return 0; +} + +/** + * @brief Read soc pl330 config. + * + * @param pl330: the handle of PL330. + * + * return None + */ +static void PL330_Read_Config(struct HAL_PL330_DEV *pl330) +{ + uint32_t val, crdn, cr; + struct PL330_CONFIG *pcfg = &pl330->pcfg; + struct DMA_REG *reg = pl330->pReg; + + crdn = READ_REG(reg->CRDN); + cr = READ_REG(reg->CR[0]); + + val = (crdn >> CRD_DATA_WIDTH_SHIFT) & CRD_DATA_WIDTH_MASK; + pcfg->dataBusWidth = 8 * (1 << val); + + pcfg->dataBufDep = ((crdn >> CRD_DATA_BUFF_SHIFT) & CRD_DATA_BUFF_MASK) + 1; + pcfg->numChan = ((cr >> CR0_NUM_CHANS_SHIFT) & CR0_NUM_CHANS_MASK) + 1; + + if (cr & CR0_PERIPH_REQ_SET) { + pcfg->numPeri = ((cr >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK) + 1; + pcfg->periNs = READ_REG(reg->CR[4]); + } else { + pcfg->numPeri = 0; + } + + if (cr & CR0_BOOT_MAN_NS) { + pcfg->mode |= DMAC_MODE_NS; + } else { + pcfg->mode &= ~DMAC_MODE_NS; + } + + pcfg->numEvents = ((cr >> CR0_NUM_EVENTS_SHIFT) & CR0_NUM_EVENTS_MASK) + 1; + pcfg->irqNs = READ_REG(reg->CR[3]); +} + +/** + * @brief Construct the DMA program based on the DMA transfer. + * + * @param pl330: the handle of PL330. + * @param pxs: pl330 xfer spec. + * @param channel: the DMA channel number + * + * @return The number of bytes for the program. + */ +static int PL330_BuildDmaProg(uint8_t dryRun, struct HAL_PL330_DEV *pl330, + struct PL330_XFER_SPEC *pxs, uint32_t channel) +{ + char *buf = (char *)pxs->desc->mcBuf; + struct PL330_XFER *x; + int off = 0; + + PL330_DBGMC_START((uint32_t)buf); + + /* DMAMOV CCR, ccr */ + off += PL330_Instr_DMAMOV(dryRun, &buf[off], CCR, pxs->ccr); + + x = &pxs->desc->px; + + if (pl330->peripReqType != BURST) { + /* Error if xfer length is not aligned at burst size */ + if (x->length % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) { + return HAL_ERROR; + } + } + + if (!pxs->desc->cyclic) { + off += _Setup_Xfer(dryRun, pl330, &buf[off], pxs); + /* DMASEV peripheral/event */ + off += PL330_Instr_DMASEV(dryRun, &buf[off], channel); + /* DMAEND */ + off += PL330_Instr_DMAEND(dryRun, &buf[off]); + } else { + off += _Setup_Xfer_Cyclic(dryRun, pl330, &buf[off], pxs, channel); + } + + /* make sure the buf and bufsize is cache line aligned. */ + if (!dryRun) { + HAL_ASSERT(HAL_IS_CACHELINE_ALIGNED((uint32_t)buf)); + HAL_DCACHE_CleanByRange((uint32_t)buf, PL330_CHAN_BUF_LEN); + } + + return off; +} + +/** + * @brief Generate a DMA program for the DMA command. + * + * @param pl330: the handle of PL330. + * @param pxs: pl330 xfer spec. + * @param channel: the DMA channel number + * + * @return - HAL_OK on success. + * - HAL_ERROR on fail. + */ +static HAL_Status PL330_GenDmaProg(struct HAL_PL330_DEV *pl330, struct PL330_XFER_SPEC *pxs, + uint32_t channel) +{ + HAL_UNUSED struct PL330_DESC *desc = pxs->desc; + int len; + + HAL_ASSERT(pl330 != NULL); + HAL_ASSERT(pxs != NULL); + HAL_ASSERT(desc != NULL); + HAL_ASSERT(desc->mcBuf != NULL); + + len = PL330_BuildDmaProg(1, pl330, pxs, channel); + if (len < 0 || len > PL330_CHAN_BUF_LEN) { + HAL_DBG_ERR("xfer size is too large, try to increase mc size\n"); + + return HAL_ERROR; + } + + PL330_BuildDmaProg(0, pl330, pxs, channel); + + return HAL_OK; +} + +/** + * @brief Execute the DMAGO to start a channel. + * + * @param reg: the DMA_REG info. + * @param channel: the DMA channel number. + * @param addr: DMA program starting address, this should be DMA address + * + * @return HAL_OK on success, HAL_TIMEOUT on time out + */ +static HAL_Status PL330_Exec_DMAGO(struct DMA_REG *reg, uint32_t channel, uint32_t addr) +{ + char buf[8]; + uint32_t dbgInst0; + uint32_t dbgInst1; + int waitCount; + + PL330_Instr_DMAGO(0, buf, channel, addr, 1); + + dbgInst0 = PL330_DBGINST0(buf[1], buf[0], 0, 0); + dbgInst1 = (uint32_t)addr; + + /* wait while debug status is busy */ + waitCount = 0; + while ((READ_REG(reg->DBGSTATUS) & PL330_DBGSTATUS_BUSY) && + (waitCount < PL330_MAX_WAIT)) { + waitCount++; + } + + if (waitCount >= PL330_MAX_WAIT) { + HAL_DBG("PL330 device at %p debug status busy time out\r\n", reg); + + return HAL_TIMEOUT; + } + + /* write debug instruction 0 */ + WRITE_REG(reg->DBGINST[0], dbgInst0); + /* write debug instruction 1 */ + WRITE_REG(reg->DBGINST[1], dbgInst1); + + /* wait while the DMA Manager is busy */ + waitCount = 0; + while ((READ_REG(reg->DSR) & PL330_DS_DMA_STATUS) != + PL330_DS_DMA_STATUS_STOPPED && + waitCount <= PL330_MAX_WAIT) { + waitCount++; + } + + if (waitCount >= PL330_MAX_WAIT) { + HAL_DBG("PL330 device at %p debug status busy time out\r\n", reg); + + return HAL_TIMEOUT; + } + + /* run the command in DbgInst0 and DbgInst1 */ + WRITE_REG(reg->DBGCMD, 0); + + return HAL_OK; +} + +static void PL330_CleanInvalidateDataBuf(struct PL330_DESC *desc) +{ + /* make sure the buf and bufsize cache line aligned. */ + if (desc->rqcfg.srcInc) { + HAL_ASSERT(HAL_IS_CACHELINE_ALIGNED(desc->px.srcAddr)); + HAL_ASSERT(HAL_IS_CACHELINE_ALIGNED(desc->px.length)); + HAL_DCACHE_CleanByRange(desc->px.srcAddr, desc->px.length); + } + + if (desc->rqcfg.dstInc) { + HAL_ASSERT(HAL_IS_CACHELINE_ALIGNED(desc->px.dstAddr)); + HAL_ASSERT(HAL_IS_CACHELINE_ALIGNED(desc->px.length)); + HAL_DCACHE_InvalidateByRange(desc->px.dstAddr, desc->px.length); + } +} + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup PL330_Exported_Functions_Group2 State and Errors Functions + + This section provides functions allowing to get the status of the module: + + * @{ + */ + +/** + * @brief PL330 Get Raw IrqStatus + * + * @param pl330: the handle of pl330. + * + * @return raw irq status + */ +uint32_t HAL_PL330_GetRawIrqStatus(struct HAL_PL330_DEV *pl330) +{ + struct DMA_REG *reg = pl330->pReg; + + return READ_REG(reg->EVENT_RIS); +} + +/** + * @brief PL330 Clear Irq + * + * @param pl330: the handle of pl330. + * @param irq: the channel irq. + * + * @return HAL_Status + */ +HAL_Status HAL_PL330_ClearIrq(struct HAL_PL330_DEV *pl330, uint32_t irq) +{ + struct DMA_REG *reg = pl330->pReg; + + WRITE_REG(reg->INTCLR, 1 << irq); + + return HAL_OK; +} + +/** + * @brief get the position + * + * @param pchan: the handle of struct PL330_CHAN. + * + * @return the size dma transferred. + */ +int HAL_PL330_GetPosition(struct PL330_CHAN *pchan) +{ + uint32_t val = 0, addr = 0; + struct HAL_PL330_DEV *pl330 = pchan->pl330; + struct PL330_DESC *desc = &pchan->desc; + struct DMA_REG *reg = pl330->pReg; + int transferred; + + if (desc->rqcfg.srcInc) { + val = READ_REG(reg->CHAN_CFG[pchan->chanId].SAR); + addr = desc->px.srcAddr; + } else { + val = READ_REG(reg->CHAN_CFG[pchan->chanId].DAR); + addr = desc->px.dstAddr; + } + + transferred = val - addr; + + return transferred; +} + +/** @} */ + +/** @defgroup PL330_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +/** + * @brief Initializes a specific PL330 dmac. + * + * @param pl330: the handle of PL330. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_PL330_Init(struct HAL_PL330_DEV *pl330) +{ + struct PL330_CHAN *pchan; + uint8_t channel; + + HAL_ASSERT(pl330 != NULL); + + memset(pl330->chans, 0, sizeof(*pchan) * PL330_CHANNELS_PER_DEV); + + for (channel = 0; channel < PL330_CHANNELS_PER_DEV; channel++) { + pchan = pl330->chans + channel; + pchan->chanId = channel; + } + + PL330_Read_Config(pl330); + + return HAL_OK; +} + +/** + * @brief DeInitializes a specific PL330 dmac. + * + * @param pl330: the handle of pl330. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_PL330_DeInit(struct HAL_PL330_DEV *pl330) +{ + uint32_t dbgInst; + uint32_t waitCount = 0; + uint32_t i; + struct DMA_REG *reg = pl330->pReg; + + /* Disable all the interrupts */ + WRITE_REG(reg->INTEN, 0x00); + /* Clear the interrupts */ + WRITE_REG(reg->INTCLR, PL330_INTCLR_ALL_MASK); + /* Kill the dma channel threads */ + for (i = 0; i < PL330_CHANNELS_PER_DEV; i++) { + while ((READ_REG(reg->DBGSTATUS) & PL330_DBGSTATUS_BUSY) && + (waitCount < PL330_MAX_WAIT)) { + waitCount++; + } + + dbgInst = PL330_DBGINST0(0, 0x01, i, 1); + WRITE_REG(reg->DBGINST[0], dbgInst); + WRITE_REG(reg->DBGINST[1], 0x0); + WRITE_REG(reg->DBGCMD, 0x0); + } + /* Kill the manager thread */ + dbgInst = PL330_DBGINST0(0, 0x01, 0, 0); + WRITE_REG(reg->DBGINST[0], dbgInst); + WRITE_REG(reg->DBGINST[1], 0x0); + WRITE_REG(reg->DBGCMD, 0x0); + + return HAL_OK; +} + +/** @} */ + +/** @defgroup PL330_Exported_Functions_Group3 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ + +/** + * @brief Start a DMA channel with the desc request. + * + * @param pchan: the hanlde of struct PL330_CHAN. + * + * @return + * - HAL_OK on success + * - HAL_BUSY if DMA is busy + * - HAL_ERROR on other failures + */ +HAL_Status HAL_PL330_Start(struct PL330_CHAN *pchan) +{ + HAL_Status ret = HAL_OK; + uint32_t ccr; + struct PL330_XFER_SPEC xs; + uint32_t channel = pchan->chanId; + struct HAL_PL330_DEV *pl330 = pchan->pl330; + struct PL330_DESC *desc = &pchan->desc; + struct DMA_REG *reg = pl330->pReg; + + HAL_ASSERT(pl330 != NULL); + HAL_ASSERT(pchan->mcBuf); + + if (pl330->pcfg.mode & DMAC_MODE_NS) { + desc->rqcfg.nonsecure = 1; + } else { + desc->rqcfg.nonsecure = 0; + } + + ccr = _Prepare_CCR(&desc->rqcfg); + + xs.ccr = ccr; + xs.desc = desc; + desc->mcBuf = pchan->mcBuf; + + ret = PL330_GenDmaProg(pl330, &xs, channel); + if (ret) { + return HAL_ERROR; + } + + /* enable the interrupt */ + SET_BIT(reg->INTEN, 0x01 << channel); + + return PL330_Exec_DMAGO(pl330->pReg, channel, (uint32_t)desc->mcBuf); +} + +/** + * @brief Stop a DMA channel. + * + * @param pchan: the hanlde of struct PL330_CHAN. + * + * @return + * - HAL_OK on success + * - HAL_BUSY if DMA is busy + * - HAL_ERROR on other failures + */ +HAL_Status HAL_PL330_Stop(struct PL330_CHAN *pchan) +{ + uint32_t intEn = READ_REG(pchan->pl330->pReg->INTEN); + + HAL_ASSERT(pchan != NULL); + + PL330_Exec_DMAKILL(pchan->pl330->pReg, pchan->chanId, 1); + + if (intEn & (1 << pchan->chanId)) { + WRITE_REG(pchan->pl330->pReg->INTCLR, 1 << pchan->chanId); + } + + WRITE_REG(pchan->pl330->pReg->INTEN, intEn & ~(1 << pchan->chanId)); + + return HAL_OK; +} + +/** + * @brief PL330 IrqHandler + * + * @param pl330: the handle of pl330. + * + * @return: raw irq status + */ +uint32_t HAL_PL330_IrqHandler(struct HAL_PL330_DEV *pl330) +{ + struct DMA_REG *reg = pl330->pReg; + uint32_t val, inten; + unsigned int ev, i = 0; + + val = READ_REG(reg->FSRD) & 0x1; + if (val) { + /* + * if DMA manager is fault + */ + HAL_DBG("Fault Type: 0x%lx\n", READ_REG(reg->FTRD)); + HAL_DBG("Fault PC 0x%lx\n", READ_REG(reg->DPC)); + /* kill the DMA manager thread */ + /* Should we disable interrupt?*/ + PL330_Exec_DMAKILL(pl330->pReg, 0, 0); + } + + val = READ_REG(reg->FSRC) & ((1 << pl330->pcfg.numChan) - 1); + if (val) { + while (i < pl330->pcfg.numChan) { + if (val & (1 << i)) { + HAL_DBG("Reset Channel-%d\t CS-%lx\n", + i, READ_REG(reg->CHAN_STS[i].CSR)); + HAL_DBG("Reset Channel-%d\t FTC-%lx\n", + i, READ_REG(reg->FTR[i])); + /* kill the channel thread */ + /* Should we disable interrupt? */ + PL330_Exec_DMAKILL(pl330->pReg, i, 1); + } + i++; + } + } + + /* Check which event happened i.e, thread notified */ + val = READ_REG(reg->EVENT_RIS); + inten = READ_REG(reg->INTEN); + + for (ev = 0; ev < PL330_CHANNELS_PER_DEV; ev++) { + if (val & (1 << ev)) { /* Event occurred */ + /* Clear the event */ + if (inten & (1 << ev)) { + WRITE_REG(reg->INTCLR, 1 << ev); + } + } + } + + /* return raw irq status */ + return val; +} + +/** + * @brief Set mc buf resource for chan + * + * @param pchan: the handle of struct PL330_CHAN. + * @param buf: mc buf addr. + * + * @return HAL_Status. + * + * @note must be invoked before function HAL_PL330_PrepDmaXXX. + */ +HAL_Status HAL_PL330_SetMcBuf(struct PL330_CHAN *pchan, void *buf) +{ + HAL_ASSERT(pchan); + HAL_ASSERT(buf); + + pchan->mcBuf = buf; + + return HAL_OK; +} + +/** + * @brief Get mc buf resource of chan + * + * @param pchan: the handle of struct PL330_CHAN. + * + * @return mc buf addr. + */ +void *HAL_PL330_GetMcBuf(struct PL330_CHAN *pchan) +{ + HAL_ASSERT(pchan); + + return pchan->mcBuf; +} + +/** + * @brief Get desc resource of chan + * + * @param pchan: the handle of struct PL330_CHAN. + * + * @return desc ptr. + */ +const struct PL330_DESC *HAL_PL330_GetDesc(struct PL330_CHAN *pchan) +{ + HAL_ASSERT(pchan); + + return &pchan->desc; +} + +/** + * @brief Request a dma channel + * + * @param pl330: the handle of struct HAL_PL330_DEV. + * @param id: the peri id. + * + * @return a idle dma channel. + */ +struct PL330_CHAN *HAL_PL330_RequestChannel(struct HAL_PL330_DEV *pl330, DMA_REQ_Type id) +{ + int i = 0; + struct PL330_CHAN *pchan = NULL; + + for (i = 0; i < PL330_CHANNELS_PER_DEV; i++) { + if (pl330->chans[i].used) { + continue; + } + pchan = &pl330->chans[i]; + pchan->used = true; + pchan->periId = id; + pchan->pl330 = pl330; + break; + } + + return pchan; +} + +/** + * @brief Release a dma channel + * + * @param pchan: the handle of struct PL330_CHAN. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_PL330_ReleaseChannel(struct PL330_CHAN *pchan) +{ + HAL_ASSERT(pchan); + + pchan->periId = 0; + pchan->used = false; + + return HAL_OK; +} + +/** + * @brief Config a pl330 dma channel + * + * @param pchan: the handle of struct PL330_CHAN. + * @param config: the peri req config. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_PL330_Config(struct PL330_CHAN *pchan, struct DMA_SLAVE_CONFIG *config) +{ + HAL_ASSERT(pchan); + + if (config->direction == DMA_MEM_TO_DEV) { + if (config->dstAddr) { + pchan->fifoAddr = config->dstAddr; + } + if (config->dstAddrWidth) { + pchan->brstSz = PL330_ToBurstSizeBits(config->dstAddrWidth); + } + if (config->dstMaxBurst) { + pchan->brstLen = config->dstMaxBurst; + } + if (config->srcInterlaceSize) { + pchan->srcInterlaceSize = config->srcInterlaceSize; + } + } else if (config->direction == DMA_DEV_TO_MEM) { + if (config->srcAddr) { + pchan->fifoAddr = config->srcAddr; + } + if (config->srcAddrWidth) { + pchan->brstSz = PL330_ToBurstSizeBits(config->srcAddrWidth); + } + if (config->srcMaxBurst) { + pchan->brstLen = config->srcMaxBurst; + } + if (config->dstInterlaceSize) { + pchan->dstInterlaceSize = config->dstInterlaceSize; + } + } + + return HAL_OK; +} + +/** + * @brief Prepare a cyclic dma transfer for the channel + * + * @param pchan: tthe handle of struct PL330_CHAN. + * @param dmaAddr: the memory addr. + * @param len: data len. + * @param periodLen: periodic len. + * @param direction: transfer direction. + * @param callback: callback function. + * @param cparam: callback param. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_PL330_PrepDmaCyclic(struct PL330_CHAN *pchan, uint32_t dmaAddr, + uint32_t len, uint32_t periodLen, + eDMA_TRANSFER_DIRECTION direction, + PL330_Callback callback, void *cparam) +{ + struct HAL_PL330_DEV *pl330 = pchan->pl330; + struct PL330_DESC *desc = &pchan->desc; + uint32_t dst; + uint32_t src; + + HAL_ASSERT(pl330 != NULL); + HAL_ASSERT(len % periodLen == 0); + HAL_ASSERT(direction == DMA_MEM_TO_DEV || direction == DMA_DEV_TO_MEM); + + memset(desc, 0x0, sizeof(*desc)); + + switch (direction) { + case DMA_MEM_TO_DEV: + desc->rqcfg.srcInc = 1; + desc->rqcfg.dstInc = 0; + src = dmaAddr; + dst = pchan->fifoAddr; + break; + case DMA_DEV_TO_MEM: + desc->rqcfg.srcInc = 0; + desc->rqcfg.dstInc = 1; + src = pchan->fifoAddr; + dst = dmaAddr; + break; + default: + + return HAL_ERROR; + } + + desc->peri = pchan->periId; + desc->dir = direction; + desc->rqcfg.brstSize = pchan->brstSz; + + if (pl330->peripReqType == BURST) { + desc->rqcfg.brstLen = pchan->brstLen; + } else { + desc->rqcfg.brstLen = 1; + } + + desc->bytesReq = len; + desc->px.srcAddr = src; + desc->px.dstAddr = dst; + desc->px.length = periodLen; + + desc->cyclic = true; + desc->numPeriods = len / periodLen; + + desc->callback = callback; + desc->cparam = cparam; + + desc->srcInterlaceSize = pchan->srcInterlaceSize; + desc->dstInterlaceSize = pchan->dstInterlaceSize; + + HAL_DBG("%s: srcInterlaceSize: %d, dstInterlaceSize: %d\n", __func__, + desc->srcInterlaceSize, desc->dstInterlaceSize); + + return HAL_OK; +} + +/** + * @brief Prepare a single dma transfer for the channel + * + * @param pchan: the handle of struct PL330_CHAN. + * @param dmaAddr: the memory addr. + * @param len: data len. + * @param direction: transfer direction. + * @param callback: callback function. + * @param cparam: callback param. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_PL330_PrepDmaSingle(struct PL330_CHAN *pchan, uint32_t dmaAddr, + uint32_t len, + eDMA_TRANSFER_DIRECTION direction, + PL330_Callback callback, void *cparam) +{ + struct HAL_PL330_DEV *pl330 = pchan->pl330; + struct PL330_DESC *desc = &pchan->desc; + uint32_t dst; + uint32_t src; + + HAL_ASSERT(pl330 != NULL); + HAL_ASSERT(direction == DMA_MEM_TO_DEV || direction == DMA_DEV_TO_MEM); + + memset(desc, 0x0, sizeof(*desc)); + + switch (direction) { + case DMA_MEM_TO_DEV: + desc->rqcfg.srcInc = 1; + desc->rqcfg.dstInc = 0; + src = dmaAddr; + dst = pchan->fifoAddr; + break; + case DMA_DEV_TO_MEM: + desc->rqcfg.srcInc = 0; + desc->rqcfg.dstInc = 1; + src = pchan->fifoAddr; + dst = dmaAddr; + break; + default: + + return HAL_ERROR; + } + + desc->peri = pchan->periId; + desc->dir = direction; + desc->rqcfg.brstSize = pchan->brstSz; + + if (pl330->peripReqType == BURST) { + desc->rqcfg.brstLen = pchan->brstLen; + } else { + desc->rqcfg.brstLen = 1; + } + + desc->bytesReq = len; + desc->px.srcAddr = src; + desc->px.dstAddr = dst; + desc->px.length = len; + + desc->cyclic = false; + desc->numPeriods = 0; + + desc->callback = callback; + desc->cparam = cparam; + + PL330_CleanInvalidateDataBuf(desc); + + return HAL_OK; +} + +/** + * @brief Prepare a dma memcpy + * + * @param pchan: the handle of struct PL330_CHAN. + * @param dst: the memory dst addr. + * @param src: the memory src addr. + * @param len: data len. + * @param callback: callback function. + * @param cparam: callback param. + * + * @return + * - HAL_OK on success. + * - HAL_ERROR on fail. + */ +HAL_Status HAL_PL330_PrepDmaMemcpy(struct PL330_CHAN *pchan, uint32_t dst, + uint32_t src, uint32_t len, + PL330_Callback callback, void *cparam) +{ + struct HAL_PL330_DEV *pl330 = pchan->pl330; + struct PL330_DESC *desc = &pchan->desc; + int burst; + + HAL_ASSERT(pl330 != NULL); + HAL_ASSERT(len > 0); + + memset(desc, 0x0, sizeof(*desc)); + + desc->px.srcAddr = src; + desc->px.dstAddr = dst; + desc->px.length = len; + desc->rqcfg.srcInc = 1; + desc->rqcfg.dstInc = 1; + desc->dir = DMA_MEM_TO_MEM; + + /* Select max possible burst size */ + burst = pl330->pcfg.dataBusWidth / 8; + + /* + * Make sure we use a burst size that aligns with all the memcpy + * parameters because our DMA programming algorithm doesn't cope with + * transfers which straddle an entry in the DMA device's MFIFO. + */ + while ((src | dst | len) & (burst - 1)) { + burst /= 2; + } + + desc->rqcfg.brstSize = 0; + while (burst != (1 << desc->rqcfg.brstSize)) { + desc->rqcfg.brstSize++; + } + + /* + * If burst size is smaller than bus width then make sure we only + * transfer one at a time to avoid a burst stradling an MFIFO entry. + */ + if (desc->rqcfg.brstSize * 8 < pl330->pcfg.dataBusWidth) { + desc->rqcfg.brstLen = 1; + } + + desc->rqcfg.brstLen = getBurstLen(desc, pl330, len); + desc->bytesReq = len; + + desc->callback = callback; + desc->cparam = cparam; + + PL330_CleanInvalidateDataBuf(desc); + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_PL330_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pwm.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pwm.c new file mode 100644 index 00000000000..fcd449b016e --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pwm.c @@ -0,0 +1,396 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_PWM_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PWM + * @{ + */ + +/** @defgroup PWM_How_To_Use How To Use + * @{ + + The PWM HAL driver can be used as follows: + + - Declare a PWM_Handle handle structure, for example: + ``` + PWM_Handle instance; + ``` + - Invoke HAL_PWM_Init() API to initialize base address and clock frequency: + - Base register address; + - Input clock frequency. + + - Invoke HAL_PWM_SetConfig() API and HAL_PWM_SetEnable() to start/stop: + - Use HAL_PWM_SetConfig() to configurate the request mode; + - Use HAL_PWM_Enable() to start PWM; + - Use HAL_PWM_Disable() to stop PWM. + + - Invoke HAL_PWM_DeInit() if necessary. + + @} */ + +/** @defgroup PWM_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define PWM_CNT_REG(pPWM, ch) (pPWM->pReg->CHANNELS[ch].CNT) +#define PWM_PERIOD_REG(pPWM, ch) (pPWM->pReg->CHANNELS[ch].PERIOD_HPR) +#define PWM_DUTY_REG(pPWM, ch) (pPWM->pReg->CHANNELS[ch].DUTY_LPR) +#define PWM_CTRL_REG(pPWM, ch) (pPWM->pReg->CHANNELS[ch].CTRL) + +#define PWM_INT_EN(ch) (1 << (ch)) +#define PWM_PWR_INT_EN(ch) (1 << ((ch) + 4 )) + +#define PWM_DISABLE (0 << PWM_PWM0_CTRL_PWM_EN_SHIFT) +#define PWM_ENABLE (1 << PWM_PWM0_CTRL_PWM_EN_SHIFT) + +#define PWM_MODE_SHIFT (1) +#define PWM_MODE_MASK (0x3U << PWM_MODE_SHIFT) + +#define PWM_DUTY_POSTIVE (1 << PWM_PWM0_CTRL_DUTY_POL_SHIFT) +#define PWM_DUTY_NEGATIVE (0 << PWM_PWM0_CTRL_DUTY_POL_SHIFT) +#define PWM_DUTY_MASK (1 << 3) + +#define PWM_INACTIVE_POSTIVE (1 << PWM_PWM0_CTRL_INACTIVE_POL_SHIFT) +#define PWM_INACTIVE_NEGATIVE (0 << PWM_PWM0_CTRL_INACTIVE_POL_SHIFT) +#define PWM_INACTIVE_MASK (1 << 4) + +#define PWM_OUTPUT_LEFT (0 << PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT) +#define PWM_OUTPUT_CENTER (1 << PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT) + +#define PWM_UNLOCK (0 << PWM_PWM0_CTRL_CONLOCK_SHIFT) +#define PWM_LOCK (1 << PWM_PWM0_CTRL_CONLOCK_SHIFT) + +#define PWM_LP_DISABLE (0 << PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT) +#define PWM_LP_ENABLE (1 << PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT) + +#define PWM_SEL_SRC_CLK (0 << PWM_PWM0_CTRL_CLK_SEL_SHIFT) +#define PWM_SEL_SCALE_CLK (1 << PWM_PWM0_CTRL_CLK_SEL_SHIFT) + +#define PWM_CTRL_SCALE_SHIFT (PWM_PWM0_CTRL_SCALE_SHIFT) +#define PWM_CTRL_SCALE_MASK (PWM_PWM0_CTRL_SCALE_MASK) + +#define PWM_PWRMATCH_MAX_SHIFT (PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT) + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup PWM_Exported_Functions_Group3 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ + +/** + * @brief Handle PWM interrupt for capture/oneshot mode. + * @param pPWM: pointer to a PWM_HANDLE structure that contains + * the information for PWM module. + * @retval HAL status + */ +HAL_Status HAL_PWM_IRQHandler(struct PWM_HANDLE *pPWM) +{ + uint32_t status = READ_REG(pPWM->pReg->INTSTS); + uint32_t i; + + /* clean ipd */ + WRITE_REG(pPWM->pReg->INTSTS, status & 0xf); + + if (status & 0xf) { + for (i = 0; i < HAL_PWM_NUM_CHANNELS; i++) { + if ((status & (1 << i)) && + (pPWM->mode[i] == HAL_PWM_CAPTURE)) { + pPWM->result[i].active = true; + pPWM->result[i].pol = status & (1 << (i + 8)); + if (pPWM->result[i].pol) { + pPWM->result[i].period = READ_REG(PWM_PERIOD_REG(pPWM, i)); + } else { + pPWM->result[i].period = READ_REG(PWM_DUTY_REG(pPWM, i)); + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Configurate PWM mode. + * @param pPWM: pointer to a PWM_HANDLE structure that contains + * the information for PWM module. + * @param channel: PWM channle(0~3). + * @param config: Configuration for PWM. + * @retval HAL status + */ +HAL_Status HAL_PWM_SetConfig(struct PWM_HANDLE *pPWM, uint8_t channel, + const struct HAL_PWM_CONFIG *config) +{ + unsigned long period, duty; + uint32_t ctrl; + + HAL_ASSERT(pPWM != NULL); + HAL_ASSERT(channel < HAL_PWM_NUM_CHANNELS); + HAL_ASSERT(config != NULL); + HAL_DBG("channel=%d, period_ns=%ld, duty_ns=%ld\n", + channel, config->periodNS, config->dutyNS); + + period = HAL_DivU64((uint64_t)pPWM->freq * config->periodNS, 1000000000); + duty = HAL_DivU64((uint64_t)pPWM->freq * config->dutyNS, 1000000000); + + ctrl = READ_REG(PWM_CTRL_REG(pPWM, channel)); + ctrl |= PWM_LOCK; + WRITE_REG(PWM_CTRL_REG(pPWM, channel), ctrl); + + WRITE_REG(PWM_PERIOD_REG(pPWM, channel), period); + WRITE_REG(PWM_DUTY_REG(pPWM, channel), duty); + + ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK); + if (config->polarity) { + ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE; + } else { + ctrl |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE; + } + + ctrl &= ~PWM_LOCK; + WRITE_REG(PWM_CTRL_REG(pPWM, channel), ctrl); + + HAL_DBG("channel=%d, period=%lu, duty=%lu, polarity=%d\n", + channel, period, duty, config->polarity); + + return HAL_OK; +} + +/** + * @brief Configurate PWM oneshot count. + * @param pPWM: pointer to a PWM_HANDLE structure that contains + * the information for PWM module. + * @param channel: PWM channle(0~3). + * @param count: (count + 1)repeated effective periods of output waveform + * @retval HAL status + */ +HAL_Status HAL_PWM_SetOneshot(struct PWM_HANDLE *pPWM, uint8_t channel, uint32_t count) +{ + uint32_t ctrl; + + HAL_ASSERT(pPWM != NULL); + HAL_ASSERT(channel < HAL_PWM_NUM_CHANNELS); + HAL_DBG("Oneshot count=%ld\n", count); + + ctrl = READ_REG(PWM_CTRL_REG(pPWM, channel)); + ctrl |= (count << PWM_PWM0_CTRL_RPT_SHIFT) & PWM_PWM0_CTRL_RPT_MASK; + WRITE_REG(PWM_CTRL_REG(pPWM, channel), ctrl); + + return HAL_OK; +} + +/** + * @brief Configurate PWM captured frequency. + * @param pPWM: pointer to a PWM_HANDLE structure that contains + * the information for PWM module. + * @param channel: PWM channle(0~3). + * @param freq: PWM use the frequency to capture data + * @retval HAL status + */ +HAL_Status HAL_PWM_SetCapturedFreq(struct PWM_HANDLE *pPWM, uint8_t channel, uint32_t freq) +{ + uint32_t ctrl; + + HAL_ASSERT(pPWM != NULL); + HAL_ASSERT(channel < HAL_PWM_NUM_CHANNELS); + HAL_ASSERT(freq != 0); + HAL_DBG("Captured freq=%ld\n", freq); + + ctrl = READ_REG(PWM_CTRL_REG(pPWM, channel)); + ctrl &= ~PWM_CTRL_SCALE_MASK; + ctrl |= PWM_LP_ENABLE | PWM_SEL_SCALE_CLK; + ctrl |= ((pPWM->freq / (2 * freq)) << PWM_CTRL_SCALE_SHIFT) & PWM_CTRL_SCALE_MASK; + WRITE_REG(PWM_CTRL_REG(pPWM, channel), ctrl); + + return HAL_OK; +} + +/** + * @brief Configurate PWM matched setting. + * @param pPWM: pointer to a PWM_HANDLE structure that contains + * the information for PWM module. + * @param channel: PWM channle(0~3). + * @param data: matching configuration. + * @retval HAL status + */ +HAL_Status HAL_PWM_SetMatch(struct PWM_HANDLE *pPWM, uint8_t channel, const struct PWM_MATCH *data) +{ + uint8_t i; + + HAL_ASSERT(pPWM != NULL); + HAL_ASSERT(channel < HAL_PWM_NUM_CHANNELS); + HAL_ASSERT(data != NULL); + HAL_ASSERT(data->matchCount <= PWM_PWRMATCH_MAX_COUNT); + + /* preloader low */ + WRITE_REG(pPWM->pReg->PWRMATCH_LPRE, data->lpreMin | (data->lpreMax << PWM_PWRMATCH_MAX_SHIFT)); + /* preloader high */ + WRITE_REG(pPWM->pReg->PWRMATCH_HPRE, data->hpreMin | (data->hpreMax << PWM_PWRMATCH_MAX_SHIFT)); + /* logic 0/1 low */ + WRITE_REG(pPWM->pReg->PWRMATCH_LD, data->ldMin | (data->ldMax << PWM_PWRMATCH_MAX_SHIFT)); + /* logic 0 high */ + WRITE_REG(pPWM->pReg->PWRMATCH_HD_ZERO, data->hdZeroMin | (data->hdZeroMax << PWM_PWRMATCH_MAX_SHIFT)); + /* logic 1 high */ + WRITE_REG(pPWM->pReg->PWRMATCH_HD_ONE, data->hdOneMin | (data->hdOneMax << PWM_PWRMATCH_MAX_SHIFT)); + + for (i = 0; i < data->matchCount; i++) { + WRITE_REG(pPWM->pReg->PWRMATCH_VALUE[i], data->match[i]); + } + + /* Enable pwr irq */ + SET_BIT(pPWM->pReg->INT_EN, PWM_PWR_INT_EN(channel)); + /* Enable pwr */ + SET_BIT(pPWM->pReg->PWRMATCH_CTRL, channel); + + return HAL_OK; +} + +/** + * @brief Get PWM mode. + * @param pPWM: pointer to a PWM_HANDLE structure that contains + * the information for PWM module. + * @param channel: PWM channle(0~3). + * @retval ePWM_Mode + */ +ePWM_Mode HAL_PWM_GetMode(struct PWM_HANDLE *pPWM, uint8_t channel) +{ + uint32_t ctrl; + + HAL_ASSERT(pPWM != NULL); + HAL_ASSERT(channel < HAL_PWM_NUM_CHANNELS); + HAL_DBG("channel=%d\n", channel); + + ctrl = READ_REG(PWM_CTRL_REG(pPWM, channel)); + + return (ePWM_Mode)((ctrl >> PWM_MODE_SHIFT) & PWM_MODE_MASK); +} + +/** + * @brief Enable PWM. + * @param pPWM: pointer to a PWM_HANDLE structure that contains + * the information for PWM module. + * @param channel: PWM channle(0~3). + * @param mode: Current mode on for PWM. + * @retval HAL status + */ +HAL_Status HAL_PWM_Enable(struct PWM_HANDLE *pPWM, uint8_t channel, ePWM_Mode mode) +{ + uint32_t enableConf, intEnable; + + HAL_ASSERT(pPWM != NULL); + HAL_ASSERT(channel < HAL_PWM_NUM_CHANNELS); + HAL_DBG("Enable channel=%d\n", channel); + + pPWM->mode[channel] = mode; + if (pPWM->mode[channel] != HAL_PWM_CONTINUOUS) { + intEnable = READ_REG(pPWM->pReg->INT_EN); + /* Enable irq */ + intEnable |= PWM_INT_EN(channel); + WRITE_REG(pPWM->pReg->INT_EN, intEnable); + } + + enableConf = READ_REG(PWM_CTRL_REG(pPWM, channel)); + /* clean mode */ + enableConf &= ~PWM_MODE_MASK; + enableConf |= (mode << PWM_MODE_SHIFT) | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE; + WRITE_REG(PWM_CTRL_REG(pPWM, channel), enableConf); + + return HAL_OK; +} + +/** + * @brief Disable PWM. + * @param pPWM: pointer to a PWM_HANDLE structure that contains + * the information for PWM module. + * @param channel: PWM channle(0~3). + * @retval HAL status + */ +HAL_Status HAL_PWM_Disable(struct PWM_HANDLE *pPWM, uint8_t channel) +{ + uint32_t ctrl, intEnable; + + HAL_ASSERT(pPWM != NULL); + HAL_ASSERT(channel < HAL_PWM_NUM_CHANNELS); + HAL_DBG("Disable channel=%d\n", channel); + + if (pPWM->mode[channel] != HAL_PWM_CONTINUOUS) { + intEnable = READ_REG(pPWM->pReg->INT_EN); + /* Disable irq */ + intEnable &= ~PWM_INT_EN(channel); + WRITE_REG(pPWM->pReg->INT_EN, intEnable); + } + + ctrl = READ_REG(PWM_CTRL_REG(pPWM, channel)); + ctrl &= ~PWM_ENABLE; + WRITE_REG(PWM_CTRL_REG(pPWM, channel), ctrl); + + return HAL_OK; +} + +/** @} */ + +/** @defgroup PWM_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +/** + * @brief Initialize the PWM according to the specified parameters. + * @param pPWM: pointer to a PWM_HANDLE structure that contains + * the information for PWM module. + * @param pReg: PWM controller register base address. + * @param freq: PWM bus input clock frequency. + * @return HAL_Status + */ +HAL_Status HAL_PWM_Init(struct PWM_HANDLE *pPWM, struct PWM_REG *pReg, uint32_t freq) +{ + HAL_ASSERT(pPWM != NULL); + + pPWM->pReg = pReg; + HAL_ASSERT(IS_PWM_INSTANCE(pPWM->pReg)); + + pPWM->freq = freq; + + return HAL_OK; +} + +/** + * @brief De Initialize the PWM peripheral. + * @param pPWM: pointer to a PWM_HANDLE structure that contains + * the information for PWM module. + * @return HAL status + */ +HAL_Status HAL_PWM_DeInit(struct PWM_HANDLE *pPWM) +{ + /* ...to do */ + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_PWM_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pwr.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pwr.c new file mode 100644 index 00000000000..62cbf665c06 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_pwr.c @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_PWR_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @defgroup PWR_How_To_Use How To Use + * @{ + + The PWR driver can be used as follows: + + - Invoke HAL_PWR_SetVoltage to set voltage value. + - Invoke HAL_PWR_GetVoltage to Get voltage value. + - Invoke HAL_PWR_SetVoltageSuspend to set voltage value for suspend mode. + - Invoke HAL_PWR_GetVoltageSuspend to get voltage value for suspend mode. + - Invoke HAL_PWR_GetVoltageReal to get voltage value while is in effect. + - Invoke HAL_PWR_Enable to enable a regulator. + - Invoke HAL_PWR_Disable to disable a regulator. + - Invoke HAL_PWR_GetEnableState to get the enable state. + - Invoke HAL_PWR_RoundVoltage to check the volt is valid or not. + + @} */ + +#ifdef HAL_PWR_INTBUS_MODULE_ENABLED + +/** @defgroup PWR_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define WM_SET_BITS(msk, shift, bits) ((msk <<(shift + 16)) | (bits << shift)) +#define WM_SET_BIT(shift) ((1 << (16 + shift) ) | (1 << shift)) +#define WM_CLR_BIT(shift) (1 << (16 + shift) ) + +/********************* Private Structure Definition **************************/ +/********************* Private Variable Definition ***************************/ +/********************* Private Function Definition ***************************/ +static HAL_Status PWR_SetVoltage_Linear(struct PWR_INTREG_DESC *desc, uint32_t volt, + ePWR_CtrlType ctrlType) +{ + uint32_t val, delta, mod; + __IO uint32_t *preg; + + HAL_ASSERT(desc->flag & HAL_BIT(ctrlType)); + + HAL_ASSERT(volt >= desc->minVolt); + + HAL_ASSERT(ctrlType <= PWR_CTRL_VOLT_SSPD); + + delta = volt - desc->minVolt; + mod = delta % desc->volt_list.stepVolt; + if (mod) { + return HAL_INVAL; + } + + val = delta / desc->volt_list.stepVolt; + + HAL_ASSERT(val < desc->voltCnt); + + preg = desc->preg[ctrlType]; + + val = WM_SET_BITS(desc->voltMask, desc->shift[ctrlType], val); + WRITE_REG(*preg, val); + + return HAL_OK; +} + +static uint32_t PWR_RoundVoltage_Linear(struct PWR_INTREG_DESC *desc, uint32_t volt) +{ + uint32_t val, delta, mod; + + HAL_ASSERT(volt >= desc->minVolt); + + delta = volt - desc->minVolt; + val = delta / desc->volt_list.stepVolt; + + mod = delta % desc->volt_list.stepVolt; + + if (mod) { + val += 1; + } + + return (desc->minVolt + desc->volt_list.stepVolt * val); +} + +static uint32_t PWR_GetVoltageLinear(struct PWR_INTREG_DESC *desc, + ePWR_CtrlType ctrlType) +{ + uint32_t val; + __IO uint32_t *preg; + + HAL_ASSERT(desc->flag & HAL_BIT(ctrlType)); + HAL_ASSERT(ctrlType <= PWR_CTRL_VOLT_ST); + + preg = desc->preg[ctrlType]; + + val = (READ_REG(*preg) >> desc->shift[ctrlType]) & desc->voltMask; + + HAL_ASSERT(val < desc->voltCnt); + + return (desc->minVolt + desc->volt_list.stepVolt * val); +} + +static HAL_Status PWR_EnableDisable(struct PWR_INTREG_DESC *desc, uint32_t enable) +{ + uint32_t val; + __IO uint32_t *preg; + + HAL_ASSERT(desc->flag & HAL_BIT(PWR_CTRL_PWR_EN)); + + preg = desc->preg[PWR_CTRL_PWR_EN]; + + if (enable) { + val = WM_SET_BIT(desc->shift[PWR_CTRL_PWR_EN]); + } else { + val = WM_CLR_BIT(desc->shift[PWR_CTRL_PWR_EN]); + } + + WRITE_REG(*preg, val); + + return HAL_OK; +} + +/** @} */ +/********************* Public Function Definition ****************************/ +/** @defgroup PWR_Exported_Functions_Group2 State and Errors Functions + + This section provides functions allowing to get the status of the module: + + * @{ + */ + +/** + * @brief get enable state for the power regulator. + * @param desc: the power regulator description pointer. + * @return 1 is enable, 0 is disable. + */ +int HAL_PWR_GetEnableState(struct PWR_INTREG_DESC *desc) +{ + __IO uint32_t *preg; + + HAL_ASSERT(desc->flag & HAL_BIT(PWR_CTRL_PWR_EN)); + + preg = desc->preg[PWR_CTRL_PWR_EN]; + + return (READ_REG(*preg) >> desc->shift[PWR_CTRL_PWR_EN]) & 0x1; +} + +/** + * @brief get voltage value. + * @param desc: the power regulator description pointer. + * @return the voltage value if support, otherwise return 0. + */ +uint32_t HAL_PWR_GetVoltage(struct PWR_INTREG_DESC *desc) +{ + HAL_ASSERT(desc); + if (desc->flag & PWR_FLG_LINEAR) { + return PWR_GetVoltageLinear(desc, PWR_CTRL_VOLT_RUN); + } else { + return 0; + } +} + +/** + * @brief round voltage value. + * @param desc: the power regulator description pointer. + * @param volt: the volt value to be check + * @return the voltage value if support, otherwise return 0. + */ +uint32_t HAL_PWR_RoundVoltage(struct PWR_INTREG_DESC *desc, uint32_t volt) +{ + HAL_ASSERT(desc); + if (desc->flag & PWR_FLG_LINEAR) { + return PWR_RoundVoltage_Linear(desc, volt); + } else { + return 0; + } +} + +/** + * @brief get voltage value for suspend mode. + * @param desc: the power regulator description pointer. + * @return the voltage value if support, otherwise return 0. + */ +uint32_t HAL_PWR_GetVoltageSuspend(struct PWR_INTREG_DESC *desc) +{ + HAL_ASSERT(desc); + if (desc->flag & PWR_FLG_LINEAR) { + return PWR_GetVoltageLinear(desc, PWR_CTRL_VOLT_SSPD); + } else { + return 0; + } +} + +/** + * @brief get real voltage value. + * @param desc: the power regulator description pointer. + * @return the voltage value if support, otherwise return 0. + */ +uint32_t HAL_PWR_GetVoltageReal(struct PWR_INTREG_DESC *desc) +{ + HAL_ASSERT(desc); + if ((desc->flag & (PWR_FLG_LINEAR | PWR_FLG_VOLT_ST)) == + (PWR_FLG_LINEAR | PWR_FLG_VOLT_ST)) { + return PWR_GetVoltageLinear(desc, PWR_CTRL_VOLT_ST); + } else { + return 0; + } +} + +/** @} */ + +/** @defgroup PWR_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief set voltage value. + * @param desc: the power regulator description pointer. + * @param volt: the volt value to be config + * @return HAL_Status. + */ +HAL_Status HAL_PWR_SetVoltage(struct PWR_INTREG_DESC *desc, uint32_t volt) +{ + HAL_ASSERT(desc); + + if (desc->flag & PWR_FLG_LINEAR) { + return PWR_SetVoltage_Linear(desc, volt, PWR_CTRL_VOLT_RUN); + } else { + return HAL_NODEV; + } +} + +/** + * @brief set voltage value for suspend mode. + * @param desc: the power regulator description pointer. + * @param volt: the volt value to be config + * @return HAL_Status. + */ +HAL_Status HAL_PWR_SetVoltageSuspend(struct PWR_INTREG_DESC *desc, + uint32_t volt) +{ + HAL_ASSERT(desc); + if (desc->flag & PWR_FLG_LINEAR) { + return PWR_SetVoltage_Linear(desc, volt, PWR_CTRL_VOLT_SSPD); + } else { + return HAL_NODEV; + } +} + +/** + * @brief enable a power regulator. + * @param desc: the power regulator description pointer. + * @return HAL_Status. + */ +HAL_Status HAL_PWR_Enable(struct PWR_INTREG_DESC *desc) +{ + HAL_ASSERT(desc); + + return PWR_EnableDisable(desc, 1); +} + +/** + * @brief disable a power regulator. + * @param desc: the power regulator description pointer. + * @return HAL_Status. + */ +HAL_Status HAL_PWR_Disable(struct PWR_INTREG_DESC *desc) +{ + HAL_ASSERT(desc); + + return PWR_EnableDisable(desc, 0); +} + +/** + * @brief match a power regulator description by pwr id. + * @param desc: a power regulator description. + * @param pwrId: a regulator channel id. + * @return if match return HAL_TRUE. + */ +HAL_Check HAL_PWR_CheckDescByPwrId(struct PWR_INTREG_DESC *desc, + ePWR_ID pwrId) +{ + if (desc->info.pwrId == pwrId) { + return HAL_TRUE; + } else { + return HAL_FALSE; + } +} + +/** @} */ + +#endif + +/** @defgroup PWR_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief use linear ranges to convert seletor to voltage. + * @param linearTables: the power linear range table pointer. + * @param sel: the selector value to be converted + * @return seletor value. + */ +int HAL_PWR_LinearRangeSelToVolt(const struct PWR_LINEAR_RANGE_TABLE *linearTables, uint32_t sel) +{ + const struct PWR_LINEAR_RANGE *range; + int i; + + HAL_ASSERT(linearTables); + HAL_ASSERT(linearTables->entry); + + for (i = 0; i < linearTables->nEntry; i++) { + range = &linearTables->entry[i]; + if (sel < range->minSel || sel > range->maxSel) { + continue; + } + + sel -= range->minSel; + + return range->minUV + (range->uVStep * sel); + } + + return HAL_INVAL; +} +/** + * @brief use linear ranges to convert voltage to seletor. + * @param linearTables: the power linear range table pointer. + * @param volt: the volt value to be converted + * @return voltage value. + */ +int HAL_PWR_LinearRangeVoltToSel(const struct PWR_LINEAR_RANGE_TABLE *linearTables, uint32_t volt) +{ + const struct PWR_LINEAR_RANGE *range; + int ret = HAL_INVAL; + int i; + + HAL_ASSERT(linearTables); + HAL_ASSERT(linearTables->entry); + + for (i = 0; i < linearTables->nEntry; i++) { + unsigned int linear_max_uV; + + range = &linearTables->entry[i]; + HAL_ASSERT(range->maxSel >= range->minSel); + linear_max_uV = range->minUV + + (range->maxSel - range->minSel) * range->uVStep; + + if (volt > linear_max_uV || volt < range->minUV) { + continue; + } + + /* range->uV_step == 0 means fixed voltage range */ + if (range->uVStep == 0) { + ret = 0; + } else { + ret = HAL_DIV_ROUND_UP(volt - range->minUV, + range->uVStep); + if (ret < 0) { + return ret; + } + } + + ret += range->minSel; + + break; + } + + return ret; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_PWR_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_systick.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_systick.c new file mode 100644 index 00000000000..0e37fbc87d5 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_systick.c @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_SYSTICK_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup SYSTICK + * @{ + */ + +/** @defgroup SYSTICK_How_To_Use How To Use + * @{ + + The SYSTICK driver can be used as follows: + + Reset SysTick in default setting: + + - Resgister HAL_SYSTICK_IRQHandler(); + - Reset HAL_BASE tick frequency value by calling HAL_SetTickFreq() if needed; + - Reset SysTick by calling HAL_SYSTICK_Init(). + + Reset SysTick by user: + + - Resgister HAL_SYSTICK_IRQHandler(); + - Choose SysTick clock source by calling HAL_SYSTICK_CLKSourceConfig(); + - Config SysTick reload value by calling HAL_SYSTICK_Config(); + - Configure the SysTick frequency by calling by calling HAL_SetTickFreq(). + + Reinit SysTick when system core clock and clock source is changed; + + - Reset core rate by calling CRU module interface; + - Update HAL global variable systemCoreClock by calling HAL_UpdateWithNewCoreRate(); + - Change SysTick clock source by calling HAL_SYSTICK_CLKSourceConfig(); + - Update SysTick reloader num in default frequency by calling + HAL_SYSTICK_Config(rate / (1000 / HAL_GetTickFreq())). + + @} */ + +/** @defgroup SYSTICK_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define SYSTICK_INT_PRIORITY 0x0FU + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup SYSTICK_Exported_Functions_Group4 Init and DeInit Functions + * @{ + */ + +/** + * @brief Init SysTick and enable SysTick. + * @return HAL_Status: HAL_OK. + * Reset SysTick to default setting. + */ +HAL_Status HAL_SYSTICK_Init(void) +{ + uint32_t ret, rate = SystemCoreClock; + + ret = HAL_SYSTICK_CLKSourceConfig(HAL_SYSTICK_CLKSRC_EXT); /* Choose external clock source */ + if (ret == HAL_OK) { + rate = PLL_INPUT_OSC_RATE; + } + + HAL_SYSTICK_Config(rate / (1000 / HAL_GetTickFreq())); /* Configure the SysTick to have interrupt in TickFreq time basis */ + + /*Configure the SysTick IRQ priority */ +#ifdef HAL_NVIC_MODULE_ENABLED + HAL_NVIC_SetPriority(SysTick_IRQn, SYSTICK_INT_PRIORITY, 0); +#endif + HAL_SYSTICK_Enable(); + + return HAL_OK; +} + +/** @} */ + +/** @defgroup SYSTICK_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief Config SysTick reload value. + * @param ticksNumb: SysTick reload value. + * @return HAL_Status. + */ +HAL_Status HAL_SYSTICK_Config(uint32_t ticksNumb) +{ + if ((ticksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return HAL_INVAL; /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticksNumb - 1UL); /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for SysTick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + + return HAL_OK; +} + +/** + * @brief Config clock source type for SysTick. + * @param clkSource: HAL_SYSTICK_CLKSRC_CORE clock source is from core clk, + * HAL_SYSTICK_CLKSRC_EXT clock source is from external reference + * @return HAL_OK if successful, HAL_INVAL if soc not support. + */ +HAL_Status HAL_SYSTICK_CLKSourceConfig(eHAL_systickClkSource clkSource) +{ + if (clkSource == HAL_SYSTICK_CLKSRC_CORE) { + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + } else { + if (SysTick->CALIB & SysTick_CALIB_NOREF_Msk) { + return HAL_INVAL; + } else { + SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk; + } + } + + return HAL_OK; +} + +/** + * @brief System Tick, Is the externalreferance clock enabled as a source clock. + * @return HAL_TRUE if external referance clock is enabled + */ +HAL_Check HAL_SYSTICK_IsExtRefClockEnabled(void) +{ + if (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) { + return HAL_FALSE; + } else { + HAL_ASSERT(!(SysTick->CALIB & SysTick_CALIB_NOREF_Msk)); + + return HAL_TRUE; + } +} + +/** + * @brief Core internal SysTick IRQ handler + * Count plus 1. + */ +__WEAK void HAL_SYSTICK_IRQHandler(void) +{ + HAL_IncTick(); +} + +/** + * @brief Enable SysTick. + * @return HAL_Status. + */ +HAL_Status HAL_SYSTICK_Enable(void) +{ + SysTick->CTRL |= (SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk); /* Enable SysTick IRQ and SysTick Timer */ + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_SYSTICK_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_timer.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_timer.c new file mode 100644 index 00000000000..f5e1f05e48f --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_timer.c @@ -0,0 +1,307 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_TIMER_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_How_To_Use How To Use + * @{ + + The TIMER driver can be used as follows: + + - IT mode: Resgister TIMER handler. + - Initialize the TIMER by calling HAL_TIMER_Init(): + - Set TIMER count by calling HAL_TIMER_SetCount(). + - Start the TIMER by calling HAL_TIMER_Start() or HAL_TIMER_Start_IT(). + - Stop the TIMER by calling HAL_TIMER_Stop() or HAL_TIMER_Stop_IT(). + + SYS_TIMER + + - SYS_TIMER is a rk timer fixed to serve the delay system. Invoke HAL_TIMER_SysTimerInit() to init. + + @} */ + +/** @defgroup TIMER_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define TIMER_CONTROLREG_TIMER_MODE_FREE_RUNNING (0x0U << TIMER_CONTROLREG_TIMER_MODE_SHIFT) + +#define TIMER_CONTROLREG_TIMER_ENABLE_ENABLED (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) +#define TIMER_CONTROLREG_TIMER_ENABLE_DISABLED (0x0U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) + +#define TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT) + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup TIMER_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit module as follows: + + * @{ + */ + +/** + * @brief Timer init. + * @param pReg: Choose TIMER. + * @param mode: Choose TIMER mode. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + WRITE_REG(pReg->CONTROLREG, mode << TIMER_CONTROLREG_TIMER_MODE_SHIFT); + + return HAL_OK; +} + +/** + * @brief System Timer init. + * @return HAL_Status. + * @attention this API allow direct use in the HAL layer. SYS_TTIMER is used for delay system. + */ +HAL_Status HAL_TIMER_SysTimerInit(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); + + if (READ_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK)) { + return HAL_OK; + } + + WRITE_REG(pReg->CONTROLREG, TIMER_FREE_RUNNING); + pReg->LOAD_COUNT[0] = 0xFFFFFFFFU; + pReg->LOAD_COUNT[1] = 0xFFFFFFFFU; + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK); + SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Timer deinit. + * @param pReg: Choose TIMER. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + WRITE_REG(pReg->CONTROLREG, 0); + + return HAL_OK; +} + +/** @} */ + +/** @defgroup TIMER_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief Start TIMER counter. + * @param pReg: Choose TIMER. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK); + SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Stop TIMER counter. + * @param pReg: Choose TIMER. + * @return HAL_Status. + * Just disable TIMER, and keep TIMER configuration. + */ +HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Start TIMER counter in interrupt mode. + * @param pReg: Choose TIMER. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_ENABLED | TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK); + + return HAL_OK; +} + +/** + * @brief Stop TIMER counter in interrupt mode. + * @param pReg: Choose TIMER. + * @return HAL_Status. + * Just disable TIMER, and keep TIMER configuration. + */ +HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Set TIMER count number. + * @param pReg: Choose TIMER. + * @param timerCount: TIMER counter loading number. + * @return HAL_Status. + * Set timer count number. + */ +HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t timerCount) +{ + uint64_t loadCount = 0; + + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + loadCount = timerCount; + pReg->LOAD_COUNT[0] = (loadCount & 0xffffffff); + pReg->LOAD_COUNT[1] = ((loadCount >> 32) & 0xffffffff); + + return HAL_OK; +} + +/** + * @brief Get TIMER count number. + * @param pReg: Choose TIMER. + * @return uint64_t: Current conut number. + */ +HAL_SECTION_SRAM_CODE +uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg) +{ + uint32_t high, low, temp; + + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); + + do { + high = pReg->CURRENT_VALUE[1]; + low = pReg->CURRENT_VALUE[0]; + temp = pReg->CURRENT_VALUE[1]; + } while (high != temp); + + return ((uint64_t)high << 32) | low; +} + +/** + * @brief Clear TIMER interrupt status. + * @param pReg: Choose TIMER. + * @return HAL_Status: HAL_OK. + */ +HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg) +{ + uint32_t timeOut = 1000; + + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); + + pReg->INTSTATUS = 0x1; + while (pReg->INTSTATUS && timeOut) { + timeOut--; + } + + if (timeOut == 0) { + return HAL_TIMEOUT; + } else { + return HAL_OK; + } +} + +/** + * @brief TIMER0 interrupt handler. + * @return HAL_Status: HAL_OK. + * Clear interrupt status. + */ +__WEAK HAL_Status HAL_TIMER0_Handler(void) +{ + HAL_TIMER_ClrInt(TIMER0); + + return HAL_OK; +} + +/** + * @brief TIMER1 interrupt handler. + * @return HAL_Status: HAL_OK. + * Clear interrupt status. + */ +__WEAK HAL_Status HAL_TIMER1_Handler(void) +{ + HAL_TIMER_ClrInt(TIMER1); + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_TIMER_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/hal_uart.c b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_uart.c new file mode 100644 index 00000000000..19a87901e9c --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/hal_uart.c @@ -0,0 +1,493 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_UART_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** @defgroup UART_How_To_Use How To Use + * @{ + + The UART driver can be used as follows: + + @} */ + +/** @defgroup UART_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +/********************* Private Structure Definition **************************/ +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ +static void UART_EnableDLAB(struct UART_REG *pReg) +{ + pReg->LCR |= UART_LCR_DLAB; +} + +static void UART_DisableDLAB(struct UART_REG *pReg) +{ + pReg->LCR &= ~(UART_LCR_DLAB); +} + +static int32_t UART_SetBaudRate(struct UART_REG *pReg, uint32_t clkRate, + uint32_t baudRate) +{ + uint32_t DivLatch; + + DivLatch = clkRate / MODE_X_DIV / baudRate; + + pReg->MCR |= UART_MCR_LOOP; + UART_EnableDLAB(pReg); + + pReg->DLL = DivLatch & 0xff; + pReg->DLH = (DivLatch >> 8) & 0xff; + + UART_DisableDLAB(pReg); + pReg->MCR &= ~(UART_MCR_LOOP); + + return (0); +} + +static int32_t UART_SetLcrReg(struct UART_REG *pReg, uint8_t byteSize, + uint8_t parity, uint8_t stopBits) +{ + uint32_t lcr = 0; + int32_t bRet = 0; + + switch (byteSize) { + case UART_DATA_5B: + lcr |= UART_LCR_WLEN5; + break; + case UART_DATA_6B: + lcr |= UART_LCR_WLEN6; + break; + case UART_DATA_7B: + lcr |= UART_LCR_WLEN7; + break; + case UART_DATA_8B: + lcr |= UART_LCR_WLEN8; + break; + default: + bRet = -1; + break; + } + + switch (parity) { + case UART_ODD_PARITY: + case UART_EVEN_PARITY: + lcr |= UART_LCR_PARITY; + lcr |= ((parity) << 4); + break; + case UART_PARITY_DISABLE: + lcr &= ~UART_LCR_PARITY; + break; + default: + bRet = -1; + break; + } + + if (stopBits == UART_ONE_AND_HALF_OR_TWO_STOPBIT) { + lcr |= UART_LCR_STOP; + } + + pReg->LCR = lcr; + + return (bRet); +} + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup UART_Exported_Functions_Group1 Suspend and Resume Functions + + This section provides functions allowing to suspend and resume the module: + + * @{ + */ +/** + * @brief suspend uart + * @param pReg: uart reg base + * @param pUartSave: save uart reg + * @return HAL_OK + */ +HAL_Status HAL_UART_Suspend(struct UART_REG *pReg, struct UART_SAVE_CONFIG *pUartSave) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + if (pUartSave && pReg) { + while (!(pReg->USR & UART_USR_TX_FIFO_EMPTY)) { + ; + } + pUartSave->LCR = pReg->LCR; + pUartSave->IER = pReg->IER; + pUartSave->MCR = pReg->MCR; + if (pReg->USR & UART_USR_BUSY) { + HAL_DelayMs(10); + } + if (pReg->USR & UART_USR_BUSY) { + pReg->SRR = UART_SRR_XFR | UART_SRR_RFR; + } + pReg->LCR = UART_LCR_DLAB; + pUartSave->DLL = pReg->DLL; + pUartSave->DLH = pReg->DLH; + pUartSave->SRT = pReg->SRT; + pUartSave->STET = pReg->STET; + pReg->LCR = pUartSave->LCR; + } + + return HAL_OK; +} + +/** + * @brief resume uart + * @param pReg: uart reg base + * @param pUartSave: save uart reg + * @return HAL_OK + */ +HAL_Status HAL_UART_Resume(struct UART_REG *pReg, struct UART_SAVE_CONFIG *pUartSave) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + if (pUartSave && pReg) { + pReg->SRR = UART_SRR_XFR | UART_SRR_RFR | UART_SRR_UR; + pReg->MCR = UART_MCR_LOOP; + pReg->LCR = UART_LCR_DLAB; + pReg->DLL = pUartSave->DLL; + pReg->DLH = pUartSave->DLH; + pReg->LCR = pUartSave->LCR; + pReg->IER = pUartSave->IER; + pReg->FCR = UART_FCR_ENABLE_FIFO; + pReg->MCR = pUartSave->MCR; + pReg->SRT = pUartSave->SRT; + pReg->STET = pUartSave->STET; + } + + return HAL_OK; +} +/** @} */ + +/** @defgroup UART_Exported_Functions_Group2 State and Errors Functions + + This section provides functions allowing to get uart status: + + * @{ + */ + +/** + * @brief get uart sub interrupt number + * @param pReg: uart reg base + * @return irq number like UART_IIR_RDI + */ +uint32_t HAL_UART_GetIrqID(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + return (pReg->IIR & UART_IIR_MASK); +} + +/** + * @brief get uart sub interrupt number + * @param pReg: uart reg base + * @return line status + */ +uint32_t HAL_UART_GetLsr(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + return pReg->LSR; +} + +/** + * @brief get uart status + * @param pReg: uart reg base + * @return uart status + */ +uint32_t HAL_UART_GetUsr(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + return pReg->USR; +} + +/** + * @brief get uart modem status + * @param pReg: uart reg base + * @return uart modem status + */ +uint32_t HAL_UART_GetMsr(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + return pReg->MSR; +} + +/** @} */ + +/** @defgroup UART_Exported_Functions_Group3 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ +/** + * @brief send one character + * @param pReg: uart reg base + * @param c: the character to be sent + */ +void HAL_UART_SerialOutChar(struct UART_REG *pReg, char c) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + while (!(pReg->USR & UART_USR_TX_FIFO_NOT_FULL)) { + ; + } + pReg->THR = (uint32_t)c; +} + +/** + * @brief send many characters + * @param pReg: uart reg base + * @param pdata: characters buffer + * @param cnt: the number of characters + * @return dwRealSize the number has been sent + */ +int HAL_UART_SerialOut(struct UART_REG *pReg, const uint8_t *pdata, uint32_t cnt) +{ + int dwRealSize = 0; + + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + while (cnt--) { + while (!(pReg->USR & UART_USR_TX_FIFO_NOT_FULL)) { + ; + } + pReg->THR = *pdata++; + dwRealSize++; + } + + return dwRealSize; +} + +/** + * @brief receive many characters + * @param pReg: uart reg base + * @param pdata: characters buffer + * @param cnt: the number of characters + * @return dwRealSize the number has been received + */ +int HAL_UART_SerialIn(struct UART_REG *pReg, uint8_t *pdata, uint32_t cnt) +{ + int dwRealSize = 0; + + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + while (cnt--) { + if (!(pReg->USR & UART_USR_RX_FIFO_NOT_EMPTY)) { + break; + } + + *pdata++ = (uint8_t)pReg->RBR; + dwRealSize++; + } + + return dwRealSize; +} + +/** @} */ + +/** @defgroup UART_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +/** + * @brief reset uart + * @param pReg: uart reg base + */ +void HAL_UART_Reset(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->SRR = UART_SRR_UR | UART_SRR_RFR | UART_SRR_XFR; + pReg->IER = 0; + pReg->DMASA = 1; +} + +/** + * @brief configure uart baudrate,data bit,stop bit and so on + * @param dev: uart hal information + * @param config: uart baud rate,data bit + * @return HAL_OK for reserve + */ +HAL_Status HAL_UART_Init(const struct HAL_UART_DEV *dev, const struct HAL_UART_CONFIG *config) +{ + uint32_t newRate; + struct UART_REG *pReg; + + HAL_ASSERT(dev != NULL); + + pReg = dev->pReg; + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + +#ifdef RK_BSP_TEMP +#if defined(HAL_CRU_MODULE_ENABLED) && !defined(IS_FPGA) + { + uint32_t rate; + + /* set sclk according to uart baud rate */ + if (config->baudRate <= 115200) { + rate = PLL_INPUT_OSC_RATE; + } else { + rate = config->baudRate * 16; + } + HAL_CRU_ClkSetFreq(dev->sclkID, rate); + newRate = HAL_CRU_ClkGetFreq(dev->sclkID); + HAL_ASSERT(rate == newRate); + } +#elif defined(PLL_INPUT_OSC_RATE) && !defined(IS_FPGA) + newRate = PLL_INPUT_OSC_RATE; +#else + newRate = 24000000; +#endif +#endif + newRate = 24000000; + + pReg->FCR = + UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | UART_FCR_T_TRIG_10; + UART_SetLcrReg(pReg, config->dataBit, config->parity, config->stopBit); + UART_SetBaudRate(pReg, newRate, config->baudRate); + + return HAL_OK; +} + +/** + * @brief disable uart by resetting it + * @param pReg: uart reg base + * @return HAL_OK for reserve + */ +HAL_Status HAL_UART_DeInit(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + HAL_UART_Reset(pReg); + + return HAL_OK; +} + +/** @} */ + +/** @defgroup UART_Exported_Functions_Group5 Other Functions + + This section provides functions allowing to control uart: + + * @{ + */ +/** + * @brief enable uart sub interrupt + * @param pReg: uart reg base + * @param uartIntNumb: uart irq num, such as UART_IER_RDI + */ +void HAL_UART_EnableIrq(struct UART_REG *pReg, uint32_t uartIntNumb) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->IER |= uartIntNumb; +} + +/** + * @brief disable uart sub interrupt + * @param pReg: uart reg base + * @param uartIntNumb: uart irq num, such as UART_IER_RDI + */ +void HAL_UART_DisableIrq(struct UART_REG *pReg, uint32_t uartIntNumb) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->IER &= ~uartIntNumb; +} + +/** + * @brief enable uart loop back mode + * @param pReg: uart reg base + */ +void HAL_UART_EnableLoopback(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->MCR |= UART_MCR_LOOP; +} + +/** + * @brief disable uart loop back mode + * @param pReg: uart reg base + */ +void HAL_UART_DisableLoopback(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->MCR &= ~(UART_MCR_LOOP); +} + +/** + * @brief enable uart hardware auto flow control + * @param pReg: uart reg base + */ +void HAL_UART_EnableAutoFlowControl(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->MCR = UART_MCR_AFE | 0X02; +} + +/** + * @brief disable uart hardware auto flow control + * @param pReg: uart reg base + */ +void HAL_UART_DisableAutoFlowControl(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->MCR &= ~UART_MCR_AFE; +} + +/** + * @brief low level irq handler, for msi, busy, rlsi + * @param pReg: uart reg base + * @return HAL_OK for reserve + */ +HAL_Status HAL_UART_HandleIrq(struct UART_REG *pReg) +{ + int iir = 0; + + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + iir = HAL_UART_GetIrqID(pReg); + + /* Handle the three sub interrupts, so the upper irq handler needn't handle those */ + switch (iir) { + case UART_IIR_MSI: + HAL_UART_GetMsr(pReg); /* clear MSI only */ + break; + case UART_IIR_BUSY: + HAL_UART_GetUsr(pReg); /* clear BUSY interrupt only */ + break; + case UART_IIR_RLSI: + HAL_UART_GetMsr(pReg); /* clear RLSI interrupt only */ + break; + case UART_IIR_NO_INT: + break; + } + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_UART_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/hal_pinctrl.c b/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/hal_pinctrl.c new file mode 100644 index 00000000000..6dcf9e25459 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/hal_pinctrl.c @@ -0,0 +1,568 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#if defined(HAL_PINCTRL_MODULE_ENABLED) && (defined(RKMCU_PISCES) || defined(RKMCU_KOALA) || defined(SOC_RK1808) || defined(RKMCU_RK2108) || defined(RKMCU_RK2206)) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PINCTRL + * @{ + */ + +/** @defgroup PINCTRL_How_To_Use How To Use + * @{ + + The pinctrl setting registers actually is bus grf registers, which include + iomux, drive strength, pull mode, slew rate and schmitt trigger. + + The pinctrl driver provides APIs: + - HAL_PINCTRL_SetPinIOMUX to set pin iomux + - HAL_PINCTRL_SetPinParam to set pin drive/pull/slewrate/schmitt + + Example: + + HAL_PINCTRL_SetIOMUX(GPIO_BANK0, + GPIO_PIN_A0 | // I2S_IN_SCLK + GPIO_PIN_A1 | // I2S_IN_LRCK + GPIO_PIN_A2 | // I2S_IN_SDI0 + GPIO_PIN_A3, // I2S_IN_SDI1 + PIN_CONFIG_MUX_FUNC2); + + HAL_PINCTRL_SetParam(GPIO_BANK0, + GPIO_PIN_A0 | // I2S_IN_SCLK + GPIO_PIN_A1 | // I2S_IN_LRCK + GPIO_PIN_A2 | // I2S_IN_SDI0 + GPIO_PIN_A3, // I2S_IN_SDI1 + PIN_CONFIG_PUL_DOWN | + PIN_CONFIG_DRV_LEVEL2 | + PIN_CONFIG_SRT_FAST | + PIN_CONFIG_SMT_ENABLE); + @} */ + +/** @defgroup PINCTRL_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define PIN_READ(r) (*(volatile uint32_t *)(r)) +#define PIN_WRITE(r, b, w, v) (*(volatile uint32_t *)(r) = (((w) << (16) | (v)) << (b))) + +/********************* Private Variable Definition ***************************/ +__WEAK const struct HAL_PINCTRL_DEV g_pinDev; + +/********************* Private Function Definition ***************************/ + +static const struct HAL_PINCTRL_DEV *PINCTRL_GetInfo(void) +{ + return &g_pinDev; +} + +/** + * @brief Acquire params for iomux setting. + * @param pBank: point to pin bank info. + * @param pin: pin index, 0~31. + * @param mux: func data. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_AcquireMuxRoute(const struct PINCTRL_BANK_INFO *pBank, uint8_t pin, uint32_t mux) +{ + const struct HAL_PINCTRL_DEV *ctrl = PINCTRL_GetInfo(); + const struct PINCTRL_MUX_ROUTE_DATA *data; + uint32_t i, reg = 0; + HAL_Status rc = HAL_OK; + + if (ctrl->muxRouteDataNum == 0) { + rc = HAL_ERROR; + goto exit; + } + + for (i = 0; i < ctrl->muxRouteDataNum; i++) { + data = &ctrl->muxRouteData[i]; + if (data->bank == pBank->channel && + data->pin & (1 << pin) && data->func == mux) { + break; + } + } + + if (i >= ctrl->muxRouteDataNum) { + rc = HAL_ERROR; + goto exit; + } + + reg = pBank->grfBase + data->routeReg; + *(volatile uint32_t *)(reg) = data->routeVal; + + HAL_DBG("setting route %08lx = %08lx, %08lx\n", reg, data->routeVal, *(volatile uint32_t *)(reg)); +exit: + + return rc; +} + +/** + * @brief Rectify params for iomux setting. + * @param pBank: point to pin bank info. + * @param pin: pin index, 0~31. + * @param reg: to get reg offset of the pin. + * @param bit: to get bit offset of the pin. + * @param mask: to get mask bits of the pin. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_RectifyMuxParams(const struct PINCTRL_BANK_INFO *pBank, uint8_t pin, + uint32_t *reg, uint8_t *bit, uint32_t *mask) +{ + const struct HAL_PINCTRL_DEV *ctrl = PINCTRL_GetInfo(); + const struct PINCTRL_MUX_RECAL_DATA *data; + uint32_t i; + HAL_Status rc = HAL_OK; + + if (ctrl->muxRecalDataNum == 0) { + rc = HAL_ERROR; + goto exit; + } + + for (i = 0; i < ctrl->muxRecalDataNum; i++) { + data = &ctrl->muxRecalData[i]; + if (data->bank == pBank->channel && + data->pin == pin) { + break; + } + } + + if (i >= ctrl->muxRecalDataNum) { + rc = HAL_ERROR; + goto exit; + } + + *reg = data->reg; + *mask = data->mask; + *bit = data->bit; +exit: + + return rc; +} + +/** + * @brief Core function to get params. + * @param pBank: point to pin bank info. + * @param pin: pin index, 0~31. + * @param id: get params for @ref ePIN_GRF_INFO_ID. + * @param reg: to get reg offset of the pin. + * @param bit: to get bit offset of the pin. + * @param mask: to get mask bits of the pin. + * @return HAL_Status: HAL_OK for success to get param. + */ +static HAL_Status PINCTRL_AcquireParam(const struct PINCTRL_BANK_INFO *pBank, uint8_t pin, + ePIN_GRF_INFO_ID id, + uint32_t *reg, uint8_t *bit, uint32_t *mask) +{ + uint8_t paramBit = pBank->GRFInfo[id].bitsPerPin; + uint8_t paramPin = pBank->GRFInfo[id].pinsPerReg; + uint32_t regVal, mskVal; + uint8_t bitVal; + + /* The '0' value means nothing to set */ + if (paramBit <= 0) { + return HAL_ERROR; + } + + /* GRF(PMUGRF) address + mux offset + pin offset */ + regVal = pBank->grfBase; + regVal += pBank->GRFInfo[id].offset; + regVal += (pin / paramPin) * 4; + + bitVal = (pin % paramPin) * paramBit; + mskVal = (0x1U << paramBit) - 0x1U; + + *reg = regVal; + *bit = bitVal; + *mask = mskVal; + + return HAL_OK; +} + +#if defined(RKMCU_RK2206) +#define GRF_SARADC_IEN_EN(x) ((0x0U << GRF_SOC_CON15_GRF_SARADC_IEN_SHIFT) << (x)) +#define GRF_SARADC_IEN_DIS(x) ((0x1U << GRF_SOC_CON15_GRF_SARADC_IEN_SHIFT) << (x)) +#define GRF_SARADC_IEN_MASK(x) ((0x1U << GRF_SOC_CON15_GRF_SARADC_IEN_SHIFT) << (x)) +#define IS_MUX_SARADC(m) ((m) == PIN_CONFIG_MUX_FUNC1) + +/** + * @brief Extra iomux for GPIO0_C0-GPIO0_C7 on rk2206 SoCs. + * @param pBank: point to pin bank info. + * @param pin: pin index, 0~31. + * @param arg: multi params defined in @ref ePINCTRL_configParam, + */ +static void PINCTRL_ExtraSet(const struct PINCTRL_BANK_INFO *pBank, uint8_t pin, uint32_t arg) +{ + if (pin < 16 || pin > 23 || (pBank->channel != GPIO_BANK0)) { + return; + } + + if (IS_MUX_SARADC(arg)) { + WRITE_REG_MASK_WE(GRF->SOC_CON15, + GRF_SARADC_IEN_MASK(pin - 16), + GRF_SARADC_IEN_DIS(pin - 16)); + } else { + WRITE_REG_MASK_WE(GRF->SOC_CON15, + GRF_SARADC_IEN_MASK(pin - 16), + GRF_SARADC_IEN_EN(pin - 16)); + } +} +#else +static inline void PINCTRL_ExtraSet(const struct PINCTRL_BANK_INFO *pBank, uint8_t pin, uint32_t arg) +{ +} +#endif + +/** + * @brief Private function to set iomux for one pin. + * @param pBank: point to pin bank info. + * @param pin: pin index, 0~31. + * @param param: mux value to set. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetMux(const struct PINCTRL_BANK_INFO *pBank, + uint8_t pin, uint8_t param) +{ + uint32_t reg = 0, mask = 0; + uint8_t bit = 0; + HAL_Status rc = HAL_OK; + + HAL_DBG("setting GPIO%d-%d to %d\n", pBank->channel, pin, param); + + rc = PINCTRL_AcquireParam(pBank, pin, GRF_MUX_INFO, ®, &bit, &mask); + if (rc) { + HAL_DBG("Warning: Acquire Mux Param failed\n"); + } + + rc = PINCTRL_RectifyMuxParams(pBank, pin, ®, &bit, &mask); + if (rc == HAL_OK) { + HAL_DBG("Warning: Param is rectified\n"); + } + + PIN_WRITE(reg, bit, mask, param); + + rc = PINCTRL_AcquireMuxRoute(pBank, pin, param); + if (rc == HAL_OK) { + HAL_DBG("setting route for GPIO%d-%d\n", pBank->channel, pin); + } + + return HAL_OK; +} + +/** + * @brief Set a new drive strength for a pin. + * @param pBank: point to pin bank info. + * @param pin: pin index, 0~31. + * @param param: drive strength to set. + * @return HAL_Status. + */ +static uint32_t PINCTRL_SetDrive(const struct PINCTRL_BANK_INFO *pBank, + uint8_t pin, uint8_t param) +{ + uint32_t reg = 0, mask = 0; + uint8_t bit = 0; + HAL_Status rc = HAL_OK; + + HAL_DBG("setting GPIO%d-%d drive to %d\n", pBank->channel, pin, param); + + rc = PINCTRL_AcquireParam(pBank, pin, GRF_DRV_INFO, ®, &bit, &mask); + if (rc) { + goto exit; + } + + PIN_WRITE(reg, bit, mask, param); +exit: + + return rc; +} + +/** + * @brief Set a new pull mode for a pin. + * @param pBank: point to pin bank info. + * @param pin: pin index, 0~31. + * @param param: pull mode to set. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetPull(const struct PINCTRL_BANK_INFO *pBank, + uint8_t pin, uint8_t param) +{ + uint32_t reg = 0, mask = 0; + uint8_t bit = 0; + HAL_Status rc = HAL_OK; + + HAL_DBG("setting GPIO%d-%d pull to %d\n", pBank->channel, pin, param); + + rc = PINCTRL_AcquireParam(pBank, pin, GRF_PUL_INFO, ®, &bit, &mask); + if (rc) { + goto exit; + } + + PIN_WRITE(reg, bit, mask, param); +exit: + + return rc; +} + +/** + * @brief Enable schmitt trigger for a pin. + * @param pBank: point to pin bank info. + * @param pin: pin index, 0~31. + * @param param: schmitt trigger enable or not. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetSchmitt(const struct PINCTRL_BANK_INFO *pBank, + uint8_t pin, uint8_t param) +{ + uint32_t reg = 0, mask = 0; + uint8_t bit = 0; + HAL_Status rc = HAL_OK; + + HAL_DBG("setting GPIO%d-%d schmitt to %d\n", pBank->channel, pin, param); + + rc = PINCTRL_AcquireParam(pBank, pin, GRF_SMT_INFO, ®, &bit, &mask); + if (rc) { + goto exit; + } + + PIN_WRITE(reg, bit, mask, param); +exit: + + return rc; +} + +/** + * @brief Change slew rate for a pin. + * @param pBank: point to pin bank info. + * @param pin: pin index, 0~31. + * @param param: slew rate fast or slow + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetSlewRate(const struct PINCTRL_BANK_INFO *pBank, + uint8_t pin, uint8_t param) +{ + uint32_t reg = 0, mask = 0; + uint8_t bit = 0; + HAL_Status rc = HAL_OK; + + HAL_DBG("setting GPIO%d-%d slewrate to %d\n", pBank->channel, pin, param); + + rc = PINCTRL_AcquireParam(pBank, pin, GRF_SRT_INFO, ®, &bit, &mask); + if (rc) { + goto exit; + } + + PIN_WRITE(reg, bit, mask, param); +exit: + + return rc; +} + +/** + * @brief Private function to configure one pin. + * @param bank: pin bank channel defined in @ref eGPIO_bankId. + * @param pin: pin index, 0~31. + * @param param: multi params defined in @ref ePINCTRL_configParam, + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetParam(const struct PINCTRL_BANK_INFO *pBank, + uint8_t pin, uint32_t param) +{ + HAL_Status rc = HAL_OK; + + if (param & FLAG_PUL) { + rc |= PINCTRL_SetPull(pBank, pin, (uint8_t)((param & MASK_PUL) >> SHIFT_PUL)); + } + + if (param & FLAG_DRV) { + rc |= PINCTRL_SetDrive(pBank, pin, (uint8_t)((param & MASK_DRV) >> SHIFT_DRV)); + } + + if (param & FLAG_SMT) { + rc |= PINCTRL_SetSchmitt(pBank, pin, (uint8_t)((param & MASK_SMT) >> SHIFT_SMT)); + } + + if (param & FLAG_SRT) { + rc |= PINCTRL_SetSlewRate(pBank, pin, (uint8_t)((param & MASK_SRT) >> SHIFT_SRT)); + } + + return rc; +} + +/** + * @brief Private function to configure one pin. + * @param bank: pin bank channel defined in @ref eGPIO_bankId. + * @param pin: pin index, 0~31. + * @param param: multi params defined in @ref ePINCTRL_configParam, + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetPinParam(eGPIO_bankId bank, uint8_t pin, uint32_t param) +{ + const struct HAL_PINCTRL_DEV *ctrl = PINCTRL_GetInfo(); + + return PINCTRL_SetParam(&ctrl->banks[bank], pin, param); +} + +/** + * @brief Private function to set iomux for one pin. + * @param bank: pin bank channel defined in @ref eGPIO_bankId. + * @param pin: pin index, 0~31. + * @param param: PIN_CONFIG_MUX_* defined in @ref ePINCTRL_configParam. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetPinIOMUX(eGPIO_bankId bank, uint8_t pin, uint32_t param) +{ + const struct HAL_PINCTRL_DEV *ctrl = PINCTRL_GetInfo(); + + PINCTRL_ExtraSet(&ctrl->banks[bank], pin, param); + + return PINCTRL_SetMux(&ctrl->banks[bank], pin, (uint8_t)((param & MASK_MUX) >> SHIFT_MUX)); +} + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup PINCTRL_Exported_Functions_Group1 Suspend and Resume Functions + + This section provides functions allowing to suspend and resume the module: + + * @{ + */ + +HAL_Status HAL_PINCTRL_Suspend(void) +{ + return HAL_OK; +} + +HAL_Status HAL_PINCTRL_Resume(void) +{ + return HAL_OK; +} +/** @} */ + +/** @defgroup PINCTRL_Exported_Functions_Group2 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +HAL_Status HAL_PINCTRL_Init(void) +{ +#ifdef RKMCU_PISCES + HAL_PINCTRL_SetIOMUX(GPIO_BANK0, GPIO_PIN_ALL & ~( + GPIO_PIN_C7 | // UART0_RX + GPIO_PIN_D0 | // UART0_TX + GPIO_PIN_D5 | // MIPI_SWITCH_CTRL + GPIO_PIN_D6), // AUD_BY_CTRL + PIN_CONFIG_MUX_FUNC0); + HAL_PINCTRL_SetIOMUX(GPIO_BANK1, GPIO_PIN_ALL & ~( + GPIO_PIN_A0 | // LCD_IN_RESET_N + GPIO_PIN_A1 | // LCD_IN_TE + GPIO_PIN_A2 | // LCD_OUT_RESETN + GPIO_PIN_A3 | // LCD_OUT_TE + GPIO_PIN_A5 | // BOOT_DEV_SEL + GPIO_PIN_A6 | // M4_DSP_JTAG_SEL + GPIO_PIN_B2), // CLK_IN_SEL + PIN_CONFIG_MUX_FUNC0); + + HAL_PINCTRL_SetParam(GPIO_BANK0, GPIO_PIN_ALL & ~( + GPIO_PIN_D5 | // MIPI_SWITCH_CTRL + GPIO_PIN_D6), // AUD_BY_CTRL + PIN_CONFIG_PUL_NORMAL); + HAL_PINCTRL_SetParam(GPIO_BANK1, GPIO_PIN_ALL & ~( + GPIO_PIN_A5 | // BOOT_DEV_SEL + GPIO_PIN_A6 | // M4_DSP_JTAG_SEL + GPIO_PIN_B2), // CLK_IN_SEL + PIN_CONFIG_PUL_NORMAL); +#endif + + return HAL_OK; +} + +HAL_Status HAL_PINCTRL_DeInit(void) +{ + return HAL_OK; +} +/** @} */ + +/** @defgroup PINCTRL_Exported_Functions_Group3 State and Errors Functions + + This section provides functions allowing to get the status of the module: + + * @{ + */ + +/** + * @brief Public function to configure for multi pins. + * @param bank: pin bank channel defined in ref eGPIO_bankId. + * @param mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS. + * @param param: multi params defined in @ref ePINCTRL_configParam, + * @return HAL_Status. + */ +HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param) +{ + uint8_t pin; + HAL_Status rc = HAL_OK; + + HAL_ASSERT(bank < GPIO_BANK_NUM); + HAL_ASSERT(IS_GPIO_PIN(mPins)); + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = PINCTRL_SetPinParam(bank, pin, param); + if (rc) { + return rc; + } + } + } + + return rc; +} + +/** + * @brief Public function to set iomux for multi pins. + * @param bank: pin bank channel defined in ref eGPIO_bankId. + * @param mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS. + * @param param: param PIN_CONFIG_MUX_* defined in @ref ePINCTRL_configParam. + * @return HAL_Status. + */ +HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param) +{ + uint8_t pin; + HAL_Status rc; + + HAL_ASSERT(bank < GPIO_BANK_NUM); + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = PINCTRL_SetPinIOMUX(bank, pin, param); + if (rc) { + return rc; + } + } + } + + return HAL_OK; +} +/** @} */ + +/** @defgroup PINCTRL_Exported_Functions_Group4 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_PINCTRL_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/hal_pinctrl_iofunc.c b/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/hal_pinctrl_iofunc.c new file mode 100644 index 00000000000..4f1a62c7c40 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/hal_pinctrl_iofunc.c @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#if defined(HAL_PINCTRL_MODULE_ENABLED) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PINCTRL + * @{ + */ + +/** @defgroup PINCTRL_How_To_Sel_IO_Func How To Select IO Function + * @{ + +APIs support to set iomux route mode to m0,m1,... + +HAL_PINCTRL_IOFuncSelFor(mode) + +MODULE support list: + + CIF EMMC FLASH FSPI LCDC MIPICSI RGMII SDIO SDMMC0 + CAN0 CAN1 CAN2 CAN3 CAN4 CAN5 + I2C0 I2C1 I2C2 I2C3 I2C4 I2C5 + I2S0 I2S1 I2S2 + SPI0 SPI1 SPI2 SPI3 SPI4 SPI5 + PWM0 PWM1 ... PWM11 + UART0 UART1 ... UART11 + +examples: + + HAL_PINCTRL_IOFuncSelForCAN0(IOFUNC_SEL_M0) + HAL_PINCTRL_IOFuncSelForCIF(IOFUNC_SEL_M0) + HAL_PINCTRL_IOFuncSelForMIPICSI(IOFUNC_SEL_M1) + HAL_PINCTRL_IOFuncSelForI2C0(IOFUNC_SEL_M2) + @} */ + +/** @defgroup PINCTRL_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +/* Basic Definitions */ +#define _CHECK(...) _CHECK_(__VA_ARGS__) +#define _CHECK_(a, b, ...) b +#define _IS_PAREN(x) _CHECK(_IS_PAREN_ x, 0) +#define _IS_PAREN_(...) 1, 1 +#define _CONCAT(a, b) _CONCAT_(a, b) +#define _CONCAT_(a, b) a ## b +#define _DEF(x) _IS_PAREN(x) + +/* IOFUNC Select Setting Definitions */ +#define _IOMUX_WRITE(REG, DATA, SHIFT, MASK) \ +{ \ + HAL_ASSERT((uint32_t)((DATA) << (SHIFT)) <= (uint32_t)(MASK)); \ + HAL_DBG("PINCTRL Write before set reg val=0x%lx\n", REG); \ + REG = ((DATA) << (SHIFT)) | ((MASK) << 16); \ + HAL_DBG("PINCTRL Write after set reg val=0x%lx\n", REG); \ + ret = HAL_OK; \ +} + +/* IOFUNC Select Basic Definition */ +#define S_DEF_IF_0(x, y, z) +#define S_DEF_IF_1(x, y, z) _IOMUX_WRITE(GRF->IOFUNC_SEL##x, z, GRF_IOFUNC_SEL##x##y##_IOMUX_SEL_SHIFT, GRF_IOFUNC_SEL##x##y##_IOMUX_SEL_MASK) +#define S_COND_DEF(x, y, z) _CONCAT(S_DEF_IF_, _DEF(GRF_IOFUNC_SEL##x##y##_IOMUX_SEL_MASK))(x, y, z) +#define C_DEF_IF_0(x, y, z) +#define C_DEF_IF_1(x, y, z) _IOMUX_WRITE(GRF->IOFUNC_CON##x, z, GRF_IOFUNC_CON##x##y##_IOMUX_SEL_SHIFT, GRF_IOFUNC_CON##x##y##_IOMUX_SEL_MASK) +#define C_COND_DEF(x, y, z) _CONCAT(C_DEF_IF_, _DEF(GRF_IOFUNC_CON##x##y##_IOMUX_SEL_MASK))(x, y, z) + +/** + * @brief HAL IOMUX Select API Basic Definition + * + * IOMUX SEL should be defined by members of GRF structure + * IOFUNC_CON0 + * IOFUNC_CON1 + * IOFUNC_CON2 + * IOFUNC_CON3 + * IOFUNC_CON4 + * IOFUNC_CON5 + * IOFUNC_SEL0 + * IOFUNC_SEL1 + * IOFUNC_SEL2 + * IOFUNC_SEL3 + * IOFUNC_SEL4 + * IOFUNC_SEL5 + * + * The HAL_PINCTRL_IOFuncSelFor will try to find valid SHIFT and MASK definition in + * IOFUNC_CONx or IOFUNC_SELx + * + * SHIFT and MASK bits are defined in soc head file. +*/ +#define DEFINE_IOMUX_FUNC(name) \ +HAL_Status HAL_PINCTRL_IOFuncSelFor##name(eIOFUNC_SEL m) \ +{ \ + HAL_Status ret = HAL_ERROR; \ + S_COND_DEF(0, _##name, m) \ + S_COND_DEF(1, _##name, m) \ + S_COND_DEF(2, _##name, m) \ + S_COND_DEF(3, _##name, m) \ + S_COND_DEF(4, _##name, m) \ + S_COND_DEF(5, _##name, m) \ + C_COND_DEF(0, _##name, m) \ + C_COND_DEF(1, _##name, m) \ + C_COND_DEF(2, _##name, m) \ + C_COND_DEF(3, _##name, m) \ + C_COND_DEF(4, _##name, m) \ + C_COND_DEF(5, _##name, m) \ + HAL_ASSERT(ret != HAL_ERROR); \ + return ret; \ +} + +DEFINE_IOMUX_FUNC(CIF) +DEFINE_IOMUX_FUNC(EMMC) +DEFINE_IOMUX_FUNC(FLASH) +DEFINE_IOMUX_FUNC(FSPI) +DEFINE_IOMUX_FUNC(LCDC) +DEFINE_IOMUX_FUNC(MIPICSI) +DEFINE_IOMUX_FUNC(RGMII) +DEFINE_IOMUX_FUNC(GMAC0) +DEFINE_IOMUX_FUNC(GMAC1) +DEFINE_IOMUX_FUNC(SDIO) +DEFINE_IOMUX_FUNC(SDMMC0) + +DEFINE_IOMUX_FUNC(CAN0) +DEFINE_IOMUX_FUNC(CAN1) +DEFINE_IOMUX_FUNC(CAN2) +DEFINE_IOMUX_FUNC(CAN3) +DEFINE_IOMUX_FUNC(CAN4) +DEFINE_IOMUX_FUNC(CAN5) +DEFINE_IOMUX_FUNC(I2C0) +DEFINE_IOMUX_FUNC(I2C1) +DEFINE_IOMUX_FUNC(I2C2) +DEFINE_IOMUX_FUNC(I2C3) +DEFINE_IOMUX_FUNC(I2C4) +DEFINE_IOMUX_FUNC(I2C5) +DEFINE_IOMUX_FUNC(I2S0) +DEFINE_IOMUX_FUNC(I2S1) +DEFINE_IOMUX_FUNC(I2S2) +DEFINE_IOMUX_FUNC(PWM0) +DEFINE_IOMUX_FUNC(PWM1) +DEFINE_IOMUX_FUNC(PWM2) +DEFINE_IOMUX_FUNC(PWM3) +DEFINE_IOMUX_FUNC(PWM4) +DEFINE_IOMUX_FUNC(PWM5) +DEFINE_IOMUX_FUNC(PWM6) +DEFINE_IOMUX_FUNC(PWM7) +DEFINE_IOMUX_FUNC(PWM8) +DEFINE_IOMUX_FUNC(PWM9) +DEFINE_IOMUX_FUNC(PWM10) +DEFINE_IOMUX_FUNC(PWM11) +DEFINE_IOMUX_FUNC(SPI0) +DEFINE_IOMUX_FUNC(SPI1) +DEFINE_IOMUX_FUNC(SPI2) +DEFINE_IOMUX_FUNC(SPI3) +DEFINE_IOMUX_FUNC(SPI4) +DEFINE_IOMUX_FUNC(SPI5) +DEFINE_IOMUX_FUNC(UART0) +DEFINE_IOMUX_FUNC(UART1) +DEFINE_IOMUX_FUNC(UART2) +DEFINE_IOMUX_FUNC(UART3) +DEFINE_IOMUX_FUNC(UART4) +DEFINE_IOMUX_FUNC(UART5) +DEFINE_IOMUX_FUNC(UART6) +DEFINE_IOMUX_FUNC(UART7) +DEFINE_IOMUX_FUNC(UART8) +DEFINE_IOMUX_FUNC(UART9) +DEFINE_IOMUX_FUNC(UART10) +DEFINE_IOMUX_FUNC(UART11) + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_PINCTRL_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/hal_pinctrl_v2.c b/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/hal_pinctrl_v2.c new file mode 100644 index 00000000000..1d7139454e2 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/hal_pinctrl_v2.c @@ -0,0 +1,562 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#if defined(HAL_PINCTRL_MODULE_ENABLED) && (defined(SOC_RV1126) || defined(SOC_SWALLOW) || defined(SOC_RK3568) || defined(RKMCU_RK2106)) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PINCTRL + * @{ + */ + +/** @defgroup PINCTRL_How_To_Use How To Use + * @{ + + The pinctrl setting registers actually is bus grf registers, which include + iomux, drive strength, pull mode, slew rate and schmitt trigger. + + The pinctrl driver provides APIs: + - HAL_PINCTRL_SetPinIOMUX to set pin iomux + - HAL_PINCTRL_SetPinParam to set pin iomux/drive/pull/slewrate/schmitt/ie + + Example: + + HAL_PINCTRL_SetIOMUX(GPIO_BANK0, + GPIO_PIN_A0 | // I2S_IN_SCLK + GPIO_PIN_A1 | // I2S_IN_LRCK + GPIO_PIN_A2 | // I2S_IN_SDI0 + GPIO_PIN_A3, // I2S_IN_SDI1 + PIN_CONFIG_MUX_FUNC2); + + HAL_PINCTRL_SetParam(GPIO_BANK0, + GPIO_PIN_A0 | // I2S_IN_SCLK + GPIO_PIN_A1 | // I2S_IN_LRCK + GPIO_PIN_A2 | // I2S_IN_SDI0 + GPIO_PIN_A3, // I2S_IN_SDI1 + PIN_CONFIG_MUX_FUNC2 | + PIN_CONFIG_PUL_DOWN | + PIN_CONFIG_DRV_LEVEL2 | + PIN_CONFIG_SRT_FAST | + PIN_CONFIG_SMT_ENABLE); + @} */ + +/** @defgroup PINCTRL_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define _TO_MASK(w) ((1U << (w)) - 1U) +#define _TO_OFFSET(p, w) ((p) * (w)) +#define RK_GEN_VAL(p, v, w) ((_TO_MASK(w) << (_TO_OFFSET(p, w) + 16)) | (((v) & _TO_MASK(w)) << _TO_OFFSET(p, w))) + +#define _PINCTRL_WRITE(REG, DATA) \ +{ \ + HAL_DBG("Write Data: 0x%lx to Reg: 0x%lx\n", REG, DATA); \ + REG = DATA; \ + HAL_DBG("Readback : 0x%lx\n", REG); \ +} + +#if defined(GRF_GPIO0A_IOMUX_OFFSET) +#define IOMUX_BIT_PER_PIN (2) +#define IOMUX_PIN_PER_REG (16 / IOMUX_BIT_PER_PIN) +#define IOMUX_0(__B, __P) (GRF->GPIO##__B##__P##_IOMUX) +#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_IOMUX_0(B, P, p, v) SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define SET_IOMUX(_GPIO, _PORT, pin, val) RK_SET_IOMUX_0(_GPIO, _PORT, pin, val) + +#elif defined(GRF_GPIO0A_IOMUX_H_OFFSET) +#define IOMUX_BIT_PER_PIN (4) +#define IOMUX_PIN_PER_REG (16 / IOMUX_BIT_PER_PIN) +#define IOMUX_0(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_L) +#define IOMUX_1(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_H) +#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_IOMUX_1(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_IOMUX_0(B, P, p, v) SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define RK_SET_IOMUX_1(B, P, p, v) SET_IOMUX_1(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define SET_IOMUX(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 4) { \ + RK_SET_IOMUX_0(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_IOMUX_1(_GPIO, _PORT, pin, val); \ + } \ +} + +#elif defined(GRF_GPIO0A_IOMUX_0_OFFSET) +#define IOMUX_BIT_PER_PIN (8) +#define IOMUX_PIN_PER_REG (16 / IOMUX_BIT_PER_PIN) +#define IOMUX_0(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_0) +#define IOMUX_1(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_1) +#define IOMUX_2(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_2) +#define IOMUX_3(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_3) +#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_IOMUX_1(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_IOMUX_2(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_2(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_IOMUX_3(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_3(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_IOMUX_0(B, P, p, v) SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define RK_SET_IOMUX_1(B, P, p, v) SET_IOMUX_1(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define RK_SET_IOMUX_2(B, P, p, v) SET_IOMUX_2(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define RK_SET_IOMUX_3(B, P, p, v) SET_IOMUX_3(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define SET_IOMUX(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 2) { \ + RK_SET_IOMUX_0(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 4) { \ + RK_SET_IOMUX_1(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 6) { \ + RK_SET_IOMUX_2(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_IOMUX_3(_GPIO, _PORT, pin, val); \ + } \ +} +#endif + +#if defined(GRF_GPIO0A_DS_OFFSET) +#define DS_BIT_PER_PIN (2) +#define DS_PIN_PER_REG (16 / DS_BIT_PER_PIN) +#define DS_0(__B, __P) (GRF->GPIO##__B##__P##_DS) +#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define SET_DS(_GPIO, _PORT, pin, val) RK_SET_DS_0(_GPIO, _PORT, pin, val) + +#elif defined(GRF_GPIO0A_DS_H_OFFSET) +#define DS_BIT_PER_PIN (4) +#define DS_PIN_PER_REG (16 / DS_BIT_PER_PIN) +#define DS_0(__B, __P) (GRF->GPIO##__B##__P##_DS_L) +#define DS_1(__B, __P) (GRF->GPIO##__B##__P##_DS_L) +#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_DS_1(_B, _P, p, v, w) _PINCTRL_WRITE(DS_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define RK_SET_DS_1(B, P, p, v) SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define SET_DS(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 4) { \ + RK_SET_DS_0(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_DS_1(_GPIO, _PORT, pin, val); \ + } \ +} + +#elif defined(GRF_GPIO0A_DS_0_OFFSET) +#define DS_BIT_PER_PIN (8) +#define DS_PIN_PER_REG (16 / DS_BIT_PER_PIN) +#define DS_0(__B, __P) (GRF->GPIO##__B##__P##_DS_0) +#define DS_1(__B, __P) (GRF->GPIO##__B##__P##_DS_1) +#define DS_2(__B, __P) (GRF->GPIO##__B##__P##_DS_2) +#define DS_3(__B, __P) (GRF->GPIO##__B##__P##_DS_3) +#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_DS_1(_B, _P, p, v, w) _PINCTRL_WRITE(DS_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_DS_2(_B, _P, p, v, w) _PINCTRL_WRITE(DS_2(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_DS_3(_B, _P, p, v, w) _PINCTRL_WRITE(DS_3(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define RK_SET_DS_1(B, P, p, v) SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define RK_SET_DS_2(B, P, p, v) SET_DS_2(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define RK_SET_DS_3(B, P, p, v) SET_DS_3(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define SET_DS(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 2) { \ + RK_SET_DS_0(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 4) { \ + RK_SET_DS_1(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 6) { \ + RK_SET_DS_2(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_DS_3(_GPIO, _PORT, pin, val); \ + } \ +} +#endif + +#if defined(GRF_GPIO0A_P_OFFSET) +#define P_BIT_PER_PIN (2) +#define P_PIN_PER_REG (16 / P_BIT_PER_PIN) +#define P_0(__B, __P) (GRF->GPIO##__B##__P##_P) +#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define SET_P(_GPIO, _PORT, pin, val) RK_SET_P_0(_GPIO, _PORT, pin, val) + +#elif defined(GRF_GPIO0A_P_H_OFFSET) +#define P_BIT_PER_PIN (4) +#define P_PIN_PER_REG (16 / P_BIT_PER_PIN) +#define P_0(__B, __P) (GRF->GPIO##__B##__P##_P_L) +#define P_1(__B, __P) (GRF->GPIO##__B##__P##_P_L) +#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_P_1(_B, _P, p, v, w) _PINCTRL_WRITE(P_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define RK_SET_P_1(B, P, p, v) SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define SET_P(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 4) { \ + RK_SET_P_0(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_P_3(_GPIO, _PORT, pin, val); \ + } \ +} + +#elif defined(GRF_GPIO0A_P_0_OFFSET) +#define P_BIT_PER_PIN (8) +#define P_PIN_PER_REG (16 / P_BIT_PER_PIN) +#define P_0(__B, __P) (GRF->GPIO##__B##__P##_P_0) +#define P_1(__B, __P) (GRF->GPIO##__B##__P##_P_1) +#define P_2(__B, __P) (GRF->GPIO##__B##__P##_P_2) +#define P_3(__B, __P) (GRF->GPIO##__B##__P##_P_3) +#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_P_1(_B, _P, p, v, w) _PINCTRL_WRITE(P_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_P_2(_B, _P, p, v, w) _PINCTRL_WRITE(P_2(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_P_3(_B, _P, p, v, w) _PINCTRL_WRITE(P_3(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define RK_SET_P_1(B, P, p, v) SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define RK_SET_P_2(B, P, p, v) SET_P_2(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define RK_SET_P_3(B, P, p, v) SET_P_3(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define SET_P(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 2) { \ + RK_SET_P_0(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 4) { \ + RK_SET_P_1(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 6) { \ + RK_SET_P_2(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_P_3(_GPIO, _PORT, pin, val); \ + } \ +} +#endif + +#ifdef SET_IOMUX +#define PINCTRL_SET_IOMUX(bank, pin, val) \ +{ \ + if (pin < 8) { \ + SET_IOMUX(bank, A, pin, val); \ + } else if (pin < 16) { \ + SET_IOMUX(bank, B, pin, val); \ + } else if (pin < 24) { \ + SET_IOMUX(bank, C, pin, val); \ + } else { \ + SET_IOMUX(bank, D, pin, val); \ + } \ +} +#endif + +#ifdef SET_DS +#define PINCTRL_SET_DS(bank, pin, val) \ +{ \ + if (pin < 8) { \ + SET_DS(bank, A, pin, val); \ + } else if (pin < 16) { \ + SET_DS(bank, B, pin, val); \ + } else if (pin < 24) { \ + SET_DS(bank, C, pin, val); \ + } else { \ + SET_DS(bank, D, pin, val); \ + } \ +} +#endif + +#ifdef SET_P +#define PINCTRL_SET_P(bank, pin, val) \ +{ \ + if (pin < 8) { \ + SET_P(bank, A, pin, val); \ + } else if (pin < 16) { \ + SET_P(bank, B, pin, val); \ + } else if (pin < 24) { \ + SET_P(bank, C, pin, val); \ + } else { \ + SET_P(bank, D, pin, val); \ + } \ +} +#endif + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** + * @brief Private function to set iomux for one pin. + * @param bank: pin bank channel. + * @param pin: pin index, 0~31. + * @param param: value to write. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetIOMUX(eGPIO_bankId bank, uint8_t pin, uint32_t data) +{ +#ifdef PINCTRL_SET_IOMUX + switch (bank) { +#ifdef GPIO0 + case 0: + PINCTRL_SET_IOMUX(0, pin, data); + break; +#endif +#ifdef GPIO1 + case 1: + PINCTRL_SET_IOMUX(1, pin, data); + break; +#endif +#ifdef GPIO2 + case 2: + PINCTRL_SET_IOMUX(2, pin, data); + break; +#endif +#ifdef GPIO3 + case 3: + PINCTRL_SET_IOMUX(3, pin, data); + break; +#endif +#ifdef GPIO4 + case 4: + #ifdef SOC_RV1126 + if (pin < 2) { + GRF->GPIO4A_IOMUX_L = RK_GEN_VAL(pin % IOMUX_PIN_PER_REG, data, IOMUX_BIT_PER_PIN); + } + #else + PINCTRL_SET_IOMUX(4, pin, data); + #endif + break; +#endif + default: + HAL_DBG("unknown gpio%d\n", bank); + break; + } + + return HAL_OK; +#else + + return HAL_ERROR; +#endif +} + +/** + * @brief Private function to set drive strength for one pin. + * @param bank: pin bank channel. + * @param pin: pin index, 0~31. + * @param param: value to write. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetDS(eGPIO_bankId bank, uint8_t pin, uint32_t data) +{ +#ifdef PINCTRL_SET_DS + switch (bank) { +#ifdef GPIO0 + case 0: + PINCTRL_SET_DS(0, pin, data); + break; +#endif +#ifdef GPIO1 + case 1: + PINCTRL_SET_DS(1, pin, data); + break; +#endif +#ifdef GPIO2 + case 2: + PINCTRL_SET_DS(2, pin, data); + break; +#endif +#ifdef GPIO3 + case 3: + PINCTRL_SET_DS(3, pin, data); + break; +#endif +#ifdef GPIO4 + case 4: + #ifdef SOC_RV1126 + if (pin < 2) { + GRF->GPIO4A_DS_L = RK_GEN_VAL(pin % DS_PIN_PER_REG, data, DS_BIT_PER_PIN); + } + #else + PINCTRL_SET_DS(4, pin, data); + #endif + break; +#endif + default: + HAL_DBG("unknown gpio%d\n", bank); + break; + } + + return HAL_OK; +#else + + return HAL_ERROR; +#endif +} + +/** + * @brief Private function to set pupd for one pin. + * @param bank: pin bank channel. + * @param pin: pin index, 0~31. + * @param param: value to write. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetPUPD(eGPIO_bankId bank, uint8_t pin, uint32_t data) +{ +#ifdef PINCTRL_SET_P + switch (bank) { +#ifdef GPIO0 + case 0: + #ifdef SOC_RV1126 + if (pin < 8) { + SET_P(0, A, pin, data); + } else if (pin < 16) { + SET_P(0, B, pin, data); + } else if (pin < 20) { + GRF->GPIO0C_P_L = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN); + } else if (pin < 24) { + GRF->GPIO0C_P_H = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN); + } else { + SET_P(0, D, pin, data); + } + #else + PINCTRL_SET_P(0, pin, data); + #endif + break; +#endif +#ifdef GPIO1 + case 1: + PINCTRL_SET_P(1, pin, data); + break; +#endif +#ifdef GPIO2 + case 2: + PINCTRL_SET_P(2, pin, data); + break; +#endif +#ifdef GPIO3 + case 3: + PINCTRL_SET_P(3, pin, data); + break; +#endif +#ifdef GPIO4 + case 4: + #ifdef SOC_RV1126 + if (pin < 2) { + GRF->GPIO4A_P = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN); + } + #else + PINCTRL_SET_P(4, pin, data); + #endif + break; +#endif + default: + HAL_DBG("unknown gpio%d\n", bank); + break; + } + + return HAL_OK; +#else + + return HAL_ERROR; +#endif +} + +/** + * @brief Private function to configure one pin. + * @param bank: pin bank channel defined in @ref eGPIO_bankId. + * @param pin: pin index, 0~31. + * @param param: multi params defined in @ref ePINCTRL_configParam, + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetPinParam(eGPIO_bankId bank, uint8_t pin, uint32_t param) +{ + HAL_Status rc = HAL_OK; + + if (param & FLAG_MUX) { + rc |= PINCTRL_SetIOMUX(bank, pin, (uint8_t)((param & MASK_MUX) >> SHIFT_MUX)); + } + + if (param & FLAG_PUL) { + rc |= PINCTRL_SetPUPD(bank, pin, (uint8_t)((param & MASK_PUL) >> SHIFT_PUL)); + } + + if (param & FLAG_DRV) { + rc |= PINCTRL_SetDS(bank, pin, (uint8_t)((param & MASK_DRV) >> SHIFT_DRV)); + } + + return rc; +} +/** @} */ + +/********************* Public Function Definition ****************************/ + +/** @defgroup PINCTRL_Exported_Functions_Group1 Suspend and Resume Functions + + This section provides functions allowing to suspend and resume the module: + + * @{ + */ + +/** @} */ + +/** @defgroup PINCTRL_Exported_Functions_Group2 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ +HAL_Status HAL_PINCTRL_Init(void) +{ + return HAL_OK; +} + +HAL_Status HAL_PINCTRL_DeInit(void) +{ + return HAL_OK; +} +/** @} */ + +/** @defgroup PINCTRL_Exported_Functions_Group3 IO Functions + + * @{ + */ + +/** + * @brief Public function to configure for multi pins. + * @param bank: pin bank channel defined in eGPIO_bankId. + * @param mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS. + * @param param: multi params defined in @ref ePINCTRL_configParam. + * @return HAL_Status. + */ +HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param) +{ + uint8_t pin; + HAL_Status rc; + + HAL_ASSERT(bank < GPIO_BANK_NUM); + + if (!(param & (FLAG_MUX | FLAG_PUL | FLAG_DRV | FLAG_SRT | FLAG_SMT))) { + return HAL_OK; + } + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = PINCTRL_SetPinParam(bank, pin, param); + if (rc) { + return rc; + } + } + } + + return HAL_OK; +} + +/** + * @brief Public function to set iomux for multi pins. + * @param bank: pin bank channel defined in eGPIO_bankId. + * @param mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS. + * @param param: multi params defined in @ref ePINCTRL_configParam. + * @return HAL_Status. + */ +HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param) +{ + return HAL_PINCTRL_SetParam(bank, mPins, param); +} +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_PINCTRL_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/pm/hal_pm_cpu.c b/bsp/rockchip/common/rk_hal/lib/hal/src/pm/hal_pm_cpu.c new file mode 100644 index 00000000000..88f0fe1733d --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/pm/hal_pm_cpu.c @@ -0,0 +1,285 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_PM_RUNTIME_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PM_CPU + * @{ + */ + +/** @defgroup PM_CPU_How_To_Use How To Use + * @{ + + The PM_CPU_SLEEP driver can be used as follows: + - Invoke HAL_NVIC_SuspendSave() when NVIC needs to be save. + - Invoke HAL_NVIC_ResumeRestore() when NVIC needs to be resume. + - Invoke HAL_CPU_SuspendSave() when cpu may need save some info. + + The PM_Runtime driver can be used as follows: + - Invoke HAL_PM_RuntimeRequest() when a device is in runtime. + - Invoke HAL_PM_RuntimeRelease() when a device is release runtime. + - Invoke HAL_PM_RuntimeGetData() when need get all of device status. + + @} */ + +static struct PM_RUNTIME_INFO runtimeStatus; + +/** @defgroup PM_PM_RUNTIME_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief request a runtime status by runtimeId. + * @param runtimeId: a runtime request id. + * @return HAL_Status + */ +HAL_Status HAL_PM_RuntimeRequest(ePM_RUNTIME_ID runtimeId) +{ + uint8_t runtimeType, typeOffset; + + HAL_ASSERT(runtimeId < PM_RUNTIME_ID_END); + + runtimeType = PM_RUNTIME_ID_TO_TYPE(runtimeId); + typeOffset = PM_RUNTIME_ID_TO_TYPE_OFFSET(runtimeId); + HAL_ASSERT(runtimeType < PM_RUNTIME_TYPE_END); + HAL_ASSERT(typeOffset < PM_RUNTIME_PER_TYPE_NUM); + + runtimeStatus.bits[runtimeType] |= HAL_BIT(typeOffset); + + return HAL_OK; +} + +/** + * @brief release a runtime status by runtimeId. + * @param runtimeId: a runtime request id. + * @return HAL_Status + */ +HAL_Status HAL_PM_RuntimeRelease(ePM_RUNTIME_ID runtimeId) +{ + uint8_t runtimeType, typeOffset; + + HAL_ASSERT(runtimeId < PM_RUNTIME_ID_END); + + runtimeType = PM_RUNTIME_ID_TO_TYPE(runtimeId); + typeOffset = PM_RUNTIME_ID_TO_TYPE_OFFSET(runtimeId); + + HAL_ASSERT(runtimeType < PM_RUNTIME_TYPE_END); + HAL_ASSERT(typeOffset < PM_RUNTIME_PER_TYPE_NUM); + + runtimeStatus.bits[runtimeType] &= ~HAL_BIT(typeOffset); + + return HAL_OK; +} + +/** + * @brief get the runitme data poiniter. + * @return the runitme data poiniter. + */ +const struct PM_RUNTIME_INFO *HAL_PM_RuntimeGetData(void) +{ + return &runtimeStatus; +} + +/** @} */ + +#endif + +#ifdef HAL_PM_SLEEP_MODULE_ENABLED + +/** @defgroup PM_Private_Definition Private Definition + * @{ + */ +/********************* Private Variable Definition ***************************/ +static struct SLEEP_CONFIG_DATA sleepConfigData; + +/** @} */ +/********************* Public Function Definition ***************************/ +/** @defgroup PM_CPU_SLEEP_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief get sleepConfigData. + * @return addr of sleepConfigData. + */ +struct SLEEP_CONFIG_DATA *HAL_SYS_GetSuspendConfig(void) +{ + return &sleepConfigData; +} + +/** + * @brief config parameters to control suspend flow. + * @param id: select parameters to be config. + * @param data: data assigned to parameters. + * @return HAL_Status. + */ +HAL_Status HAL_SYS_SuspendConfig(uint32_t id, uint32_t data) +{ + switch (id) { + case PM_SLEEP_MODE_CONFIG: + sleepConfigData.suspendMode = data; + break; + + case PM_SLEEP_WAKEUP_SOURCE: + sleepConfigData.suspendWkupSrc = data; + break; + + default: + break; + } + + return HAL_OK; +} + +/** @} */ + +#endif /* HAL_PM_SLEEP_MODULE_ENABLED */ + +#if defined(HAL_PM_CPU_SLEEP_MODULE_ENABLED) +#if defined(__CM3_REV) || defined(__CM4_REV) + +/** @defgroup PM_CPU_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define NVIC_EXT_ISER_NUM (8) +#define NVIC_EXT_IP_NUM (240) +#define SHP_NUM (12) +/********************* Private Structure Definition **************************/ + +struct NVIC_SAVE_S { + uint32_t iser[NVIC_EXT_ISER_NUM];/* Interrupt Set Enable Register */ + uint8_t ip[NVIC_EXT_IP_NUM]; /* Interrupt Priority Register */ + uint32_t pg; /* Interrupt Priority Group Register */ +}; + +/********************* Private Variable Definition ***************************/ + +static struct NVIC_SAVE_S nvicSave; +static NVIC_Type *pnvic = NVIC; +static SCB_Type scbSave; + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ***************************/ +/** @defgroup PM_CPU_SLEEP_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief save nvic registers for resume nvic. + */ +void HAL_NVIC_SuspendSave(void) +{ + int i; + + for (i = 0; i < NVIC_EXT_ISER_NUM; i++) { + nvicSave.iser[i] = pnvic->ISER[i]; + } + + for (i = 0; i < NVIC_EXT_IP_NUM; i++) { + nvicSave.ip[i] = pnvic->IP[i]; + } + + nvicSave.pg = NVIC_GetPriorityGrouping(); +} + +/** + * @brief resume nvic registers. + */ +void HAL_NVIC_ResumeRestore(void) +{ + int i; + + NVIC_SetPriorityGrouping(nvicSave.pg); + for (i = 0; i < NVIC_EXT_IP_NUM; i++) { + pnvic->IP[i] = nvicSave.ip[i]; + } + + for (i = 0; i < NVIC_EXT_ISER_NUM; i++) { + pnvic->ICER[i] = 0xffffffff; + } + + for (i = 0; i < NVIC_EXT_ISER_NUM; i++) { + pnvic->ISER[i] = nvicSave.iser[i]; + } +} + +/** + * @brief save scb registers for resume nvic. + */ +void HAL_SCB_SuspendSave(void) +{ + int i; + + scbSave.ICSR = SCB->ICSR; + scbSave.AIRCR = SCB->AIRCR; + scbSave.SCR = SCB->SCR; + for (i = 0; i < SHP_NUM; i++) { + scbSave.SHP[i] = SCB->SHP[i]; + } + scbSave.SHCSR = SCB->SHCSR; + scbSave.CFSR = SCB->CFSR; + scbSave.DFSR = SCB->DFSR; + scbSave.MMFAR = SCB->MMFAR; + scbSave.BFAR = SCB->BFAR; + scbSave.AFSR = SCB->AFSR; + scbSave.CPACR = SCB->CPACR; +} + +/** + * @brief resume nvic registers. + */ +void HAL_SCB_ResumeRestore(void) +{ + int i; + + SCB->ICSR = scbSave.ICSR; + SCB->AIRCR = scbSave.AIRCR; + SCB->SCR = scbSave.SCR; + for (i = 0; i < SHP_NUM; i++) { + SCB->SHP[i] = scbSave.SHP[i]; + } + SCB->SHCSR = scbSave.SHCSR; + SCB->CFSR = scbSave.CFSR; + SCB->DFSR = scbSave.DFSR; + SCB->MMFAR = scbSave.MMFAR; + SCB->BFAR = scbSave.BFAR; + SCB->AFSR = scbSave.AFSR; + SCB->CPACR = scbSave.CPACR; +} + +/** + * @brief it is for saving cpu's register. + * @param ptr: base addr for saving + * @param ptrsz: size of the mem for saving + * @param sp: the system stack needed be saved + * @param ptrSave: save the param ptr. + */ +void HAL_CPU_SuspendSave(uint32_t *ptr, uint32_t ptrsz, uint32_t sp, uint32_t *ptrSave) +{ + *ptrSave = (uint32_t)ptr; + *ptr++ = sp; + *ptr++ = (uint32_t)HAL_CPU_ArchResume + 1; + HAL_CPU_ArchSuspend(ptr); +} + +/** @} */ + +#endif /* __CM3_REV || __CM4_REV */ + +/** @} */ + +/** @} */ + +#endif /* HAL_PM_CPU_SLEEP_MODULE_ENABLED */ diff --git a/bsp/rockchip/common/rk_hal/lib/hal/src/pm/hal_pm_rk2108.c b/bsp/rockchip/common/rk_hal/lib/hal/src/pm/hal_pm_rk2108.c new file mode 100644 index 00000000000..c48f81c37e0 --- /dev/null +++ b/bsp/rockchip/common/rk_hal/lib/hal/src/pm/hal_pm_rk2108.c @@ -0,0 +1,740 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" +#include + +#if defined(RKMCU_RK2108) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PM + * @{ + */ + +/** @defgroup PM_How_To_Use How To Use + * @{ + + The PM driver can be used as follows: + + - Invoke HAL_SYS_Suspend() when system will enter suspend. + + @} */ + +/** @defgroup PM_Private_Definition Private Definition + * @{ + */ + +/********************* Private MACRO Definition ******************************/ + +/* for pm_runtime */ +#define SLEEP_INPUT_RATE 32000 +#define EXPONENT_OF_FRAC_PLL 24 +#define RK_PLL_MODE_SLOW 0 +#define RK_PLL_MODE_NORMAL 1 +#define RK_PLL_MODE_DEEP 2 + +#define PLL_POSTDIV1_SHIFT 12 +#define PLL_POSTDIV1_MASK 0x7 << PLL_POSTDIV1_SHIFT +#define PLL_POSTDIV2_SHIFT 6 +#define PLL_POSTDIV2_MASK 0x7 << PLL_POSTDIV2_SHIFT + +#define PLL_GET_POSTDIV1(x) \ + (((uint32_t)(x) & (PLL_POSTDIV1_MASK)) >> PLL_POSTDIV1_SHIFT) +#define PLL_GET_POSTDIV2(x) \ + (((uint32_t)(x) & (PLL_POSTDIV2_MASK)) >> PLL_POSTDIV2_SHIFT) +#define UART_CLK_GET_MUX(clk) HAL_CRU_ClkGetMux(CLK_GET_MUX((clk))) +#define GPLL_RUNTIME_RATE (PLL_INPUT_OSC_RATE * 2) + +#define PVTM_KHZ (1000) +#define PVTM_CALC_CNT_KHZ (PLL_INPUT_OSC_RATE / PVTM_KHZ) +#define PVTM_TARGET_KHZ (32) +#define PVTM_CALC_CNT 0x200 + +#define SLEEP_COUNT_TO_MS(ms) (ms * SLEEP_INPUT_RATE / 1000) +/********************* Private Structure Definition **************************/ +struct UART_REG_SAVE { + uint32_t DLL; + uint32_t DLH; + uint32_t IER; + uint32_t LCR; + uint32_t MCR; +}; +/********************* Private Variable Definition ***************************/ +HAL_UNUSED static uint64_t pmTimerLastCount; +HAL_UNUSED static uint64_t pmTimerLowCount; +HAL_UNUSED static uint32_t pmIRQPendingFlag; + +#if defined(HAL_PM_RUNTIME_MODULE_ENABLED) || defined(HAL_PM_SLEEP_MODULE_ENABLED) +static uint8_t pvtm32kEn = 0; +#endif +/********************* Private Function Definition ***************************/ +#if defined(HAL_PM_RUNTIME_MODULE_ENABLED) || defined(HAL_PM_SLEEP_MODULE_ENABLED) +static void PVTM_ClkEnable(void) +{ + struct GRF_REG *pGrf = GRF; + + pGrf->PVTM_CON0 = VAL_MASK_WE(GRF_PVTM_CON0_PVTM_OSC_EN_MASK, + GRF_PVTM_CON0_PVTM_OSC_EN_MASK); +} + +static void PVTM_ClkDisable(void) +{ + struct GRF_REG *pGrf = GRF; + + pGrf->PVTM_CON0 = VAL_MASK_WE(GRF_PVTM_CON0_PVTM_OSC_EN_MASK, + 0); +} + +static void PVTM_ClkRateConfig(uint32_t khz) +{ + uint32_t pvtm_freq_khz, pvtm_div; + struct GRF_REG *pGrf = GRF; + + pGrf->PVTM_CON0 = 0xffff0000; + PVTM_ClkEnable(); + + pGrf->PVTM_CON1 = PVTM_CALC_CNT; + + pGrf->PVTM_CON0 = VAL_MASK_WE(GRF_PVTM_CON0_PVTM_START_MASK, + GRF_PVTM_CON0_PVTM_START_MASK); + + /* pmugrf_pvtm_st0 will be clear after PVTM start, + * which will cost about 6 cycles of pvtm at least. + * So we wait 30 cycles of pvtm for security. + */ + while (pGrf->PVTM_STATUS1 < 30) { + ; + } + while (!(pGrf->PVTM_STATUS0 & GRF_PVTM_STATUS0_PVTM_FREQ_DONE_MASK)) { + ; + } + + pvtm_freq_khz = + ((pGrf->PVTM_STATUS1) * PVTM_CALC_CNT_KHZ + PVTM_CALC_CNT / 2) / PVTM_CALC_CNT; + pvtm_div = (pvtm_freq_khz + khz / 2) / khz; + + if (pvtm_div > 0xfff) { + pvtm_div = 0xfff; + } + + pGrf->PVTM_CON0 = VAL_MASK_WE(GRF_PVTM_CON0_PVTM_START_MASK, + 0); + pGrf->PVTM_CON0 = VAL_MASK_WE(GRF_PVTM_CON0_PVTM_CLKOUT_DIV_MASK, + pvtm_div << GRF_PVTM_CON0_PVTM_CLKOUT_DIV_SHIFT); +} +#endif + +#ifdef HAL_PM_RUNTIME_MODULE_ENABLED +static uint32_t PM_GetPllPostDivEven(uint32_t rateIn, uint32_t rateOut, uint32_t *postDiv1, uint32_t *postDiv2) +{ + uint32_t div1, div2, div; + + div = rateIn / rateOut; + if (div < 7) { + *postDiv1 = div; + *postDiv2 = 1; + + return 0; + } + + for (div2 = 2; div2 <= 6;) { + div1 = div / div2; + if (div1 <= 7) { + break; + } + div2 += 2; + } + if (div1 < div2) { + return 2; + } + + *postDiv1 = div1; + *postDiv2 = div2; + + if ((div1 * div2) != div) { + return 1; + } else { + return 0; + } +} + +static void PM_CruAsEnable(uint8_t en) +{ +#ifdef HAL_CRU_AS_FEATURE_ENABLED + HAL_CRU_AsEnable(1, en); + HAL_CRU_AsEnable(2, en); + HAL_CRU_AsEnable(3, en); + HAL_CRU_AsEnable(4, en); +#endif +} + +static uint32_t PM_RuntimeEnter(ePM_RUNTIME_idleMode idleMode) +{ + uint32_t gpllCon1, gpllDiv2, gpllDiv2New; + uint32_t gpllCon0 = 0, gpllDiv1, gpllDiv1New; + uint32_t clkSelCon2 = 0, clkSelCon33 = 0, clkSelCon40 = 0; + uint32_t cruMode; + uint32_t gpllRateNew; + uint32_t mDiv; + static uint32_t gpllRate; + const struct PM_RUNTIME_INFO *pdata = HAL_PM_RuntimeGetData(); + +#ifdef HAL_WDT_DYNFREQ_FEATURE_ENABLED + uint32_t tmpDiv; + static uint32_t pmDynWdtFreqNor; + static uint32_t pmWdtFreq; + static uint32_t pmDynWdtFreq; +#endif + + if (PM_DISPLAY_REQUESTED(pdata)) { + return HAL_BIT(PM_RUNTIME_TYPE_DISPLAY); + } + + if (PM_UART_REQUESTED(pdata)) { + if ((PM_UART_REQUESTED(pdata) & HAL_BIT(0)) && + (UART_CLK_GET_MUX(CLK_UART0) != SCLK_UART0_SEL_XIN_OSC0_FUNC)) { + return HAL_BIT(PM_RUNTIME_TYPE_UART); + } else if ((PM_UART_REQUESTED(pdata) & HAL_BIT(1)) && + (UART_CLK_GET_MUX(CLK_UART1) != SCLK_UART1_SEL_XIN_OSC0_FUNC)) { + return HAL_BIT(PM_RUNTIME_TYPE_UART); + } else if ((PM_UART_REQUESTED(pdata) & HAL_BIT(2)) && + (UART_CLK_GET_MUX(CLK_UART2) != SCLK_UART2_SEL_XIN_OSC0_FUNC)) { + return HAL_BIT(PM_RUNTIME_TYPE_UART); + } + } + + if (PM_I2C_REQUESTED(pdata)) { + return HAL_BIT(PM_RUNTIME_TYPE_I2C); + } + + if (PM_HS_INTF_REQUESTED(pdata)) { + return HAL_BIT(PM_RUNTIME_TYPE_HS_INTF); + } + + if (PM_SPI_REQUESTED(pdata)) { + return HAL_BIT(PM_RUNTIME_TYPE_SPI); + } + + if (idleMode == PM_RUNTIME_IDLE_DEEP1) { + if (!pvtm32kEn) { + PVTM_ClkRateConfig(PVTM_TARGET_KHZ / 8); + pvtm32kEn = 1; + } else { + PVTM_ClkEnable(); + } + } + + PM_CruAsEnable(0); + if (!gpllRate) { + gpllRate = HAL_CRU_ClkGetFreq(PLL_GPLL); + } + +#ifdef HAL_WDT_DYNFREQ_FEATURE_ENABLED + if (!pmWdtFreq) { + pmWdtFreq = HAL_CRU_ClkGetFreq(PCLK_WDT); + tmpDiv = (gpllRate / pmWdtFreq); + pmDynWdtFreq = PLL_INPUT_OSC_RATE / tmpDiv; + pmDynWdtFreqNor = GPLL_RUNTIME_RATE / tmpDiv; + } +#endif + if (idleMode == PM_RUNTIME_IDLE_DEEP || idleMode == PM_RUNTIME_IDLE_DEEP1) { + cruMode = CRU->CRU_MODE_CON00 | + MASK_TO_WE(CRU_CRU_MODE_CON00_CLK_GPLL_MODE_MASK); + gpllCon1 = CRU->GPLL_CON[1] | + MASK_TO_WE(CRU_GPLL_CON1_PLLPD0_MASK); + + clkSelCon33 = CRU->CRU_CLKSEL_CON[33] | + MASK_TO_WE(CRU_CRU_CLKSEL_CON33_HCLK_M4_DIV_MASK); + clkSelCon2 = CRU->CRU_CLKSEL_CON[2] | + MASK_TO_WE(CRU_CRU_CLKSEL_CON02_SCLK_SHRM_DIV_MASK); + clkSelCon40 = CRU->CRU_CLKSEL_CON[40] | + MASK_TO_WE(CRU_CRU_CLKSEL_CON40_ACLK_LOGIC_DIV_MASK); + + CRU->CRU_MODE_CON00 = + VAL_MASK_WE(CRU_CRU_MODE_CON00_CLK_GPLL_MODE_MASK, + RK_PLL_MODE_SLOW << CRU_CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT); + + CRU->CRU_CLKSEL_CON[33] = + VAL_MASK_WE(CRU_CRU_CLKSEL_CON33_HCLK_M4_DIV_MASK, 0); + CRU->CRU_CLKSEL_CON[2] = + VAL_MASK_WE(CRU_CRU_CLKSEL_CON02_SCLK_SHRM_DIV_MASK, 0); + CRU->CRU_CLKSEL_CON[40] = + VAL_MASK_WE(CRU_CRU_CLKSEL_CON40_ACLK_LOGIC_DIV_MASK, 0); + + HAL_ASSERT(!(CRU->GPLL_CON[1] & CRU_GPLL_CON1_PLLPD0_MASK)); + HAL_ASSERT(!(CRU->GPLL_CON[1] & CRU_GPLL_CON1_PLLPDSEL_MASK)); + +#ifdef HAL_WDT_DYNFREQ_FEATURE_ENABLED + HAL_WDT_DynFreqUpdata(pmDynWdtFreq); +#endif + + CRU->GPLL_CON[1] = VAL_MASK_WE(CRU_GPLL_CON1_PLLPD0_MASK, + CRU_GPLL_CON1_PLLPD0_MASK); + + if (idleMode == PM_RUNTIME_IDLE_DEEP1) { + CRU->CRU_MODE_CON00 = + VAL_MASK_WE(CRU_CRU_MODE_CON00_CLK_GPLL_MODE_MASK, + RK_PLL_MODE_DEEP << CRU_CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT); + } + } else if (idleMode == PM_RUNTIME_IDLE_NORMAL) { + cruMode = 0; + clkSelCon2 = 0; + + HAL_ASSERT(HAL_CRU_ClkGetFreq(HCLK_M4) > GPLL_RUNTIME_RATE); + gpllRate = HAL_CRU_ClkGetFreq(PLL_GPLL); + + gpllCon1 = CRU->GPLL_CON[1] | + MASK_TO_WE(CRU_GPLL_CON1_POSTDIV2_MASK); + gpllCon0 = CRU->GPLL_CON[0] | + MASK_TO_WE(CRU_GPLL_CON0_POSTDIV1_MASK); + + gpllDiv1 = PLL_GET_POSTDIV1(gpllCon0); + gpllDiv2 = PLL_GET_POSTDIV2(gpllCon1); + + gpllRate = (gpllRate * gpllDiv1 * gpllDiv2); + + if (PM_GetPllPostDivEven(gpllRate, GPLL_RUNTIME_RATE, &gpllDiv1New, &gpllDiv2New) >= 2) { + return UINT32_MAX; + } + + gpllRateNew = gpllRate / (gpllDiv1New * gpllDiv2New); + mDiv = gpllRateNew / GPLL_RUNTIME_RATE; + + HAL_ASSERT(mDiv > 0); + HAL_ASSERT((gpllRateNew * mDiv) >= GPLL_RUNTIME_RATE); + + if (mDiv > 0) { + mDiv -= 1; + } + +#ifdef HAL_WDT_DYNFREQ_FEATURE_ENABLED + HAL_WDT_DynFreqUpdata(pmDynWdtFreqNor); +#endif + + clkSelCon33 = CRU->CRU_CLKSEL_CON[33] | + MASK_TO_WE(CRU_CRU_CLKSEL_CON33_HCLK_M4_DIV_MASK); + + CRU->GPLL_CON[0] = VAL_MASK_WE(CRU_GPLL_CON0_POSTDIV1_MASK, + gpllDiv1New << CRU_GPLL_CON0_POSTDIV1_SHIFT); + + CRU->GPLL_CON[1] = VAL_MASK_WE(CRU_GPLL_CON1_POSTDIV2_MASK, + gpllDiv2New << CRU_GPLL_CON1_POSTDIV2_SHIFT); + + CRU->CRU_CLKSEL_CON[33] = VAL_MASK_WE(CRU_CRU_CLKSEL_CON33_HCLK_M4_DIV_MASK, + mDiv << CRU_CRU_CLKSEL_CON33_HCLK_M4_DIV_SHIFT); + } else { + goto _ret_err; + } + + __DSB(); + __WFI(); + + if (idleMode == PM_RUNTIME_IDLE_DEEP || idleMode == PM_RUNTIME_IDLE_DEEP1) { + CRU->GPLL_CON[1] = gpllCon1; + CRU->CRU_CLKSEL_CON[33] = clkSelCon33; + CRU->CRU_CLKSEL_CON[2] = clkSelCon2; + CRU->CRU_CLKSEL_CON[40] = clkSelCon40; + + while ((CRU->GPLL_CON[1] & CRU_CPLL_CON1_PLL_LOCK_MASK) != + CRU_CPLL_CON1_PLL_LOCK_MASK) { + ; + } + CRU->CRU_MODE_CON00 = cruMode; + if (idleMode == PM_RUNTIME_IDLE_DEEP1) { + PVTM_ClkDisable(); + } + } else if (idleMode == PM_RUNTIME_IDLE_NORMAL) { + CRU->CRU_CLKSEL_CON[33] = clkSelCon33; + CRU->GPLL_CON[1] = gpllCon1; + CRU->GPLL_CON[0] = gpllCon0; + } +#ifdef HAL_WDT_DYNFREQ_FEATURE_ENABLED + HAL_WDT_DynFreqResume(); +#endif + + PM_CruAsEnable(1); + + return 0; +_ret_err: + + return UINT32_MAX; +} + +uint32_t HAL_PM_RuntimeEnter(ePM_RUNTIME_idleMode idleMode) +{ + uint32_t ret; + + if (idleMode) { + ret = PM_RuntimeEnter(idleMode); + } else { + ret = UINT32_MAX; + } + + if (!idleMode || ret) { + __DSB(); + __WFI(); + } + + return ret; +} + +#endif + +#ifdef HAL_PM_SLEEP_MODULE_ENABLED +HAL_UNUSED static void SOC_GetWakeupStatus(struct PMU_REG *pPmu) +{ + HAL_DBG("\nwakeup source:\n"); + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_WAKEUP_PWRMODE_INT_STATUS_SHIFT)) { + HAL_DBG("\tPower mode state machine wakeup status by interrupt\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_GPIO_INT_STATUS_SHIFT)) { + HAL_DBG("\tPower mode state machine wakeup status by gpio interrupt\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_TIMEOUT_STATUS_SHIFT)) { + HAL_DBG("\tPower mode state machine wakeup status by timeout\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_DSP_SFT_STATUS_SHIFT)) { + HAL_DBG("\tPower mode state machine wakeup status by DSP software\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_TIMER_STATUS_SHIFT)) { + HAL_DBG("\tPower mode state machine wakeup status by timer interrupt\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_VAD_STATUS_SHIFT)) { + HAL_DBG("\tPower mode state machine wakeup status by vad\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_WAKEUP_DSP_INT_STATUS_SHIFT)) { + HAL_DBG("\tDSP auto power down state machine wakeup status by interrupt\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_DSP_WAKEUP_GPIO_INT_STATUS_SHIFT)) { + HAL_DBG("\tDSP auto power down state machine wakeup status by gpio interrupt\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_DSP_WAKEUP_TIMEOUT_STATUS_SHIFT)) { + HAL_DBG("\tDSP auto power down state machine wakeup status by timeout\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_DSP_WAKEUP_SFT_STATUS_SHIFT)) { + HAL_DBG("\tDSP auto power down state machine wakeup status by MCU software\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_DSP_WAKEUP_TIMER_STATUS_SHIFT)) { + HAL_DBG("\tauto power down state machine wakeup status by timer\n"); + } + if (pPmu->WAKEUP_STATUS & (1 << PMU_WAKEUP_STATUS_DSP_WAKEUP_VAD_STATUS_SHIFT)) { + HAL_DBG("\tDSP auto power down state machine wakeup status by vad\n"); + } + + pPmu->WAKEUP_STATUS = (1 << PMU_WAKEUP_STATUS_WAKEUP_PWRMODE_INT_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_GPIO_INT_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_TIMEOUT_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_DSP_SFT_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_TIMER_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_PWRMODE_WAKEUP_VAD_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_WAKEUP_DSP_INT_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_DSP_WAKEUP_GPIO_INT_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_DSP_WAKEUP_TIMEOUT_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_DSP_WAKEUP_SFT_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_DSP_WAKEUP_TIMER_STATUS_SHIFT) | + (1 << PMU_WAKEUP_STATUS_DSP_WAKEUP_VAD_STATUS_SHIFT); +} + +HAL_UNUSED static void SOC_FastBootEnable(struct GRF_REG *pGrf) +{ +#ifdef HAL_PM_CPU_SLEEP_MODULE_ENABLED + pGrf->FAST_BOOT_ADDR = (uint32_t)HAL_CPU_DoResume; + pGrf->FAST_BOOT_EN = 1; +#endif +} + +HAL_UNUSED static void SOC_FastBootDisable(struct GRF_REG *pGrf) +{ +#ifdef HAL_PM_CPU_SLEEP_MODULE_ENABLED + pGrf->FAST_BOOT_EN = 0; +#endif +} + +HAL_UNUSED static void SOC_SleepModeInit(struct PMU_REG *pPmu) +{ + uint32_t mask = 0, value = 0; + + mask = PMU_PWRMODE_CON_POWER_MODE_EN_MASK | + PMU_PWRMODE_CON_OSC_DISABLE_MASK | + PMU_PWRMODE_CON_PMU_USE_LF_MASK | + PMU_PWRMODE_CON_PLL_PD_EN_MASK | + PMU_PWRMODE_CON_LOGIC_PD_EN_MASK | + PMU_PWRMODE_CON_PWRMODE_LDO_ADJ_EN_MASK | + PMU_PWRMODE_CON_BYPASS_PLL_LOCK_MASK | + PMU_PWRMODE_CON_BYPASS_HF_EN_MASK | + PMU_PWRMODE_CON_GLOBAL_INT_DISABLE_CFG_MASK | + PMU_PWRMODE_CON_SHRM_PD_EN_MASK | + PMU_PWRMODE_CON_SHRM_MEM_RETPD_EN_MASK; + + value = (1 << PMU_PWRMODE_CON_POWER_MODE_EN_SHIFT) | + /*(1 << PMU_PWRMODE_CON_PMU_USE_LF_SHIFT) |*/ + (1 << PMU_PWRMODE_CON_PLL_PD_EN_SHIFT) | + (1 << PMU_PWRMODE_CON_LOGIC_PD_EN_SHIFT) | + (1 << PMU_PWRMODE_CON_PWRMODE_LDO_ADJ_EN_SHIFT) | + /*(1 << PMU_PWRMODE_CON_BYPASS_PLL_LOCK_SHIFT) |*/ + /*(1 << PMU_PWRMODE_CON_BYPASS_HF_EN_SHIFT) |*/ + (1 << PMU_PWRMODE_CON_SHRM_PD_EN_SHIFT) | + (1 << PMU_PWRMODE_CON_SHRM_MEM_RETPD_EN_SHIFT); + + /* if PD_DSP and PD_AUDIO power down, PMU low frequency mode enable */ + if (pPmu->PWRDN_ST & + ((1 << PMU_PWRDN_ST_PD_AUDIO_PWR_STAT_SHIFT) | (1 << PMU_PWRDN_ST_PD_DSP_PWR_STAT_SHIFT))) { + value |= (1 << PMU_PWRMODE_CON_PMU_USE_LF_SHIFT) | + (1 << PMU_PWRMODE_CON_OSC_DISABLE_SHIFT); + pPmu->PWRMODE_LDO_ADJ_CNT = SLEEP_COUNT_TO_MS(1); + pPmu->PLLLOCK_CNT = SLEEP_COUNT_TO_MS(1); + pPmu->DSP_LDO_ADJ_CNT = SLEEP_COUNT_TO_MS(1); + pPmu->OSC_CNT = SLEEP_COUNT_TO_MS(1); + + if (!pvtm32kEn) { + PVTM_ClkRateConfig(PVTM_TARGET_KHZ); + pvtm32kEn = 1; + } else { + PVTM_ClkEnable(); + } + } + pPmu->PWRMODE_CON = VAL_MASK_WE(mask, value); + + if (pPmu->PWRMODE_CON & (1 << PMU_PWRMODE_CON_LOGIC_PD_EN_SHIFT)) { + mask = PMU_BUS_CLR_CLR_LOGIC_MASK; + value = (1 << PMU_BUS_CLR_CLR_LOGIC_SHIFT); + pPmu->BUS_CLR |= VAL_MASK_WE(mask, value); + } + + if (pPmu->PWRMODE_CON & (1 << PMU_PWRMODE_CON_SHRM_MEM_RETPD_EN_SHIFT)) { + mask = PMU_SHRM_CON1_PWRMODE_SHRM_PWRDWN_EN_MASK | + PMU_SHRM_CON1_PWRMODE_SHRM_RET2N_MASK; + value = (0xf << PMU_SHRM_CON1_PWRMODE_SHRM_PWRDWN_EN_SHIFT); + pPmu->SHRM_CON1 = VAL_MASK_WE(mask, value); + + mask = PMU_BUS_CLR_CLR_SHRM_MASK; + value = (1 << PMU_BUS_CLR_CLR_SHRM_SHIFT); + pPmu->BUS_CLR |= VAL_MASK_WE(mask, value); + } + + if (pPmu->PWRMODE_CON & (1 << PMU_PWRMODE_CON_PWRMODE_LDO_ADJ_EN_SHIFT)) { + mask = PMU_LDO_CON1_PWRMODE_LDOCORE_ADJ_MASK; + pPmu->LDO_CON[1] = VAL_MASK_WE(mask, 0x10); + } + + if (pPmu->PWRMODE_CON & (1 << PMU_PWRMODE_CON_PLL_PD_EN_SHIFT)) { + mask = PMU_PLL_CON_PLL_PD_CFG_MASK; + /* if PD_DSP and PD_AUDIO power down, CPLL, GPLL and 32K PLL power down by hardware */ + if (pPmu->PWRDN_ST & + ((1 << PMU_PWRDN_ST_PD_AUDIO_PWR_STAT_SHIFT) | (1 << PMU_PWRDN_ST_PD_DSP_PWR_STAT_SHIFT))) { + pPmu->PLL_CON = VAL_MASK_WE(mask, 0x07); + } else { + pPmu->PLL_CON = VAL_MASK_WE(mask, 0x05); + } + } + + if (pPmu->PWRMODE_CON & (1 << PMU_PWRMODE_CON_PMU_USE_LF_SHIFT)) { + mask = PMU_SFT_CON_PMU_LF_MODE_CFG_MASK; + value = (1 << PMU_SFT_CON_PMU_LF_MODE_CFG_SHIFT); + pPmu->SFT_CON = VAL_MASK_WE(mask, value); + } +} + +HAL_UNUSED static void SOC_WakeupSourceConfig(struct PMU_REG *pPmu) +{ + uint32_t mask = 0, value = 0; + + mask = PMU_WAKEUP_CFG6_GPIO_INT_EN_MASK | + PMU_WAKEUP_CFG6_TIMER_EN_MASK; + value = (1 << PMU_WAKEUP_CFG6_GPIO_INT_EN_SHIFT) | + (1 << PMU_WAKEUP_CFG6_TIMER_EN_SHIFT); + pPmu->WAKEUP_CFG6 = VAL_MASK_WE(mask, value); +} + +HAL_UNUSED static void SOC_SleepModeReinit(struct PMU_REG *pPmu) +{ + uint32_t mask = 0, value = 0; + + mask = PMU_PWRMODE_CON_POWER_MODE_EN_MASK | + PMU_PWRMODE_CON_PLL_PD_EN_MASK | + PMU_PWRMODE_CON_LOGIC_PD_EN_MASK | + PMU_PWRMODE_CON_PWRMODE_LDO_ADJ_EN_MASK | + PMU_PWRMODE_CON_BYPASS_PLL_LOCK_MASK | + PMU_PWRMODE_CON_BYPASS_HF_EN_MASK | + PMU_PWRMODE_CON_GLOBAL_INT_DISABLE_CFG_MASK | + PMU_PWRMODE_CON_SHRM_PD_EN_MASK | + PMU_PWRMODE_CON_SHRM_MEM_RETPD_EN_MASK; + pPmu->PWRMODE_CON = VAL_MASK_WE(mask, value); + if (pPmu->PWRDN_ST & + ((1 << PMU_PWRDN_ST_PD_AUDIO_PWR_STAT_SHIFT) | (1 << PMU_PWRDN_ST_PD_DSP_PWR_STAT_SHIFT))) { + PVTM_ClkDisable(); + } +} + +HAL_UNUSED static void SOC_PutChar(char c, struct UART_REG *pUart) +{ + if (pUart) { + pUart->THR = c; + while ((pUart->USR & UART_USR_BUSY)) { + ; + } + } +} + +HAL_UNUSED static void SOC_UartSave(struct UART_REG_SAVE *pUartSave, struct UART_REG *pUart) +{ + if (pUartSave && pUart) { + while (!(pUart->USR & UART_USR_TX_FIFO_EMPTY)) { + ; + } + pUartSave->LCR = pUart->LCR; + pUartSave->IER = pUart->IER; + pUartSave->MCR = pUart->MCR; + if (pUart->USR & UART_USR_BUSY) { + HAL_DelayMs(10); + } + if (pUart->USR & UART_USR_BUSY) { + pUart->SRR = UART_SRR_XFR | UART_SRR_RFR; + } + pUart->LCR = UART_LCR_DLAB; + pUartSave->DLL = pUart->DLL; + pUartSave->DLH = pUart->DLH; + pUart->LCR = pUartSave->LCR; + } +} + +HAL_UNUSED static void SOC_UartRestore(struct UART_REG_SAVE *pUartSave, struct UART_REG *pUart) +{ + if (pUartSave && pUart) { + pUart->SRR = UART_SRR_XFR | UART_SRR_RFR | UART_SRR_UR; + pUart->MCR = UART_MCR_LOOP; + pUart->LCR = UART_LCR_DLAB; + pUart->DLL = pUartSave->DLL; + pUart->DLH = pUartSave->DLH; + pUart->LCR = pUartSave->LCR; + pUart->IER = pUartSave->IER; + pUart->FCR = UART_FCR_ENABLE_FIFO; + pUart->MCR = pUartSave->MCR; + } +} + +#ifdef HAL_PM_CPU_SLEEP_MODULE_ENABLED +static int SOC_SuspendEnter(uint32_t flag) +{ + HAL_DCACHE_CleanInvalidate(); + __WFI(); + + /* The PD_LOGIC power down when in power mode, the code will not execute + */ + pmIRQPendingFlag = 1; + HAL_CPU_DoResume(); + + return HAL_OK; +} +#endif + +/** @} */ +/********************* Public Function Definition ****************************/ +/** @defgroup PM_Exported_Functions_Group5 Other Functions + * @{ + */ + +HAL_Status HAL_PM_TimerStart(uint64_t timeoutCount, bool needTimeout) +{ + pmTimerLastCount = HAL_GetSysTimerCount(); + pmTimerLowCount = 0; + + return 0; +} + +HAL_Status HAL_PM_TimerStop(void) +{ + return 0; +} + +uint64_t HAL_PM_GetTimerCount(void) +{ + return HAL_GetSysTimerCount() - pmTimerLastCount; +} + +int HAL_SYS_Suspend(struct PM_SUSPEND_INFO *suspendInfo) +{ +#ifdef HAL_PM_CPU_SLEEP_MODULE_ENABLED + struct PMU_REG *pPmu = PMU; + struct GRF_REG *pGrf = GRF; + struct UART_REG *pUart = NULL; + struct UART_REG_SAVE pUartSave = { 0 }; + uint64_t timerCount; + + HAL_ASSERT(suspendInfo != NULL); + +#ifdef HAL_SYSTICK_MODULE_ENABLED + SysTick->CTRL &= (~SysTick_CTRL_ENABLE_Msk); +#endif + +#ifdef HAL_UART_MODULE_ENABLED + if (suspendInfo->flag.uartValid) { + if (suspendInfo->flag.uartChannel == 0) { + pUart = UART0; + } else if (suspendInfo->flag.uartChannel == 1) { + pUart = UART1; + } else if (suspendInfo->flag.uartChannel == 2) { + pUart = UART2; + } + } +#endif + + SOC_PutChar('0', pUart); + SOC_SleepModeInit(pPmu); + SOC_PutChar('1', pUart); + SOC_FastBootEnable(pGrf); + SOC_PutChar('2', pUart); + SOC_WakeupSourceConfig(pPmu); + SOC_PutChar('3', pUart); + HAL_NVIC_SuspendSave(); + SOC_PutChar('4', pUart); + HAL_SCB_SuspendSave(); + SOC_PutChar('5', pUart); + SOC_UartSave(&pUartSave, pUart); + timerCount = HAL_GetSysTimerCount(); + HAL_CPU_SuspendEnter(suspendInfo->suspendFlag, SOC_SuspendEnter); + pmTimerLowCount = HAL_GetSysTimerCount() - timerCount; + SOC_SleepModeReinit(pPmu); + SOC_UartRestore(&pUartSave, pUart); + SOC_PutChar('5', pUart); + if (pmIRQPendingFlag == 0) { + SOC_PutChar('4', pUart); + BSP_MPU_Init(); + HAL_DCACHE_Enable(); + HAL_DCACHE_EnableInt(); + HAL_ICACHE_Enable(); + HAL_ICACHE_EnableInt(); + } + pmIRQPendingFlag = 0; + SOC_PutChar('3', pUart); + HAL_SCB_ResumeRestore(); + SOC_PutChar('2', pUart); + HAL_NVIC_ResumeRestore(); + SOC_PutChar('1', pUart); + SOC_GetWakeupStatus(pPmu); + SOC_FastBootDisable(pGrf); + SOC_PutChar('0', pUart); +#ifdef HAL_SYSTICK_MODULE_ENABLED + HAL_SYSTICK_CLKSourceConfig(HAL_SYSTICK_CLKSRC_EXT); + HAL_SYSTICK_Enable(); +#endif + + HAL_DBG("\n"); +#endif + + return HAL_OK; +} + +/** @} */ +#endif + +/** @} */ + +/** @} */ + +#endif /* RKMCU_RK2108 */ diff --git a/bsp/rockchip/rk2108/.config b/bsp/rockchip/rk2108/.config new file mode 100644 index 00000000000..44cbb56851b --- /dev/null +++ b/bsp/rockchip/rk2108/.config @@ -0,0 +1,265 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_BIG_ENDIAN is not set +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +# CONFIG_RT_USING_ASM_MEMSET is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x40100 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +CONFIG_BSP_RK2108=y + +# +# RT-Thread board config +# +CONFIG_RT_BOARD_NAME="rk2108_evb" +CONFIG_RT_RUN_MEM_BASE=0x20000000 +CONFIG_RT_RUN_MEM_SIZE=0x00100000 +CONFIG_M4_JTAG_ENABLE=y + +# +# RT-Thread rockchip common drivers +# +# CONFIG_RT_USING_RESET is not set +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_UNCACHE_HEAP is not set +# CONFIG_RT_USING_LARGE_HEAP is not set +CONFIG_RT_USING_PM_RUNTIME=y + +# +# RT-Thread rockchip RK2108 drivers +# +CONFIG_RT_USING_CRU=y + +# +# Enable UART +# +CONFIG_RT_USING_UART=y +# CONFIG_RT_USING_UART0 is not set +# CONFIG_RT_USING_UART1 is not set +CONFIG_RT_USING_UART2=y +CONFIG_RT_USING_SYSTICK=y diff --git a/bsp/rockchip/rk2108/Kconfig b/bsp/rockchip/rk2108/Kconfig new file mode 100644 index 00000000000..75b27830932 --- /dev/null +++ b/bsp/rockchip/rk2108/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +source "$RTT_DIR/Kconfig" + +config BSP_RK2108 + bool + select ARCH_ARM + select ARCH_ARM_CORTEX_M + select ARCH_ARM_CORTEX_M4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "$BSP_DIR/board/Kconfig" +source "$BSP_DIR/driver/Kconfig" diff --git a/bsp/rockchip/rk2108/README_CN.md b/bsp/rockchip/rk2108/README_CN.md new file mode 100755 index 00000000000..2e730415c96 --- /dev/null +++ b/bsp/rockchip/rk2108/README_CN.md @@ -0,0 +1,88 @@ +# Rockchip RK2108 BSP说明 + +--- + +**目录** + +[TOC] + +--- + +## 简介 + +本文档为Rockchip RK2108 （ARM Cortex-M4F with Cache）的BSP说明。目录结构如下： + +```shell +bsp/rockchip +|-- common +| |-- drivers # RT-Thread OS适配层通用驱动 +| |-- rk_hal # Rockchip HAL 硬件抽象层实现 +| | |-- lib +| | | |-- bsp # 芯片相关的初始化和功能实现 +| | | |-- CMSIS # 标准CMSIS库 +| | | `-- hal # HAL 通用驱动 +|-- rk2108 +| |-- application # 应用程序 +| |-- board # 板级支持 +| | |-- common # 通用板级支持 +| | `-- rk2108_evb # rk2108_evb 板级支持 +| |-- driver # RK2108 私有驱动目录 +| `-- image # 存放打包固件 +`-- tools # Rockchip 通用工具 +``` + +## 开发流程 + +### 编译 + +在bsp/rockchip/rk2108下进行操作。 + +```shell +cd bsp/rockchip/rk2108 +./mkimage.sh +``` + +### 打包 + +使用Rockchip工具resource_header_tool和firmware_merger进行固件打包，分区配置文件为setting.ini。固件打包命令在脚本mkimage.sh中一起完成。完成固件打包后能得到Firmware.img。 + +这里对loader相关文件进行说明： + +- rk2108_loader.bin：用于启动引导的loader，将与rtthread.bin一起打包 +- rk2108_loader_fake.bin：由于Rockchip固件打包时IDBlock格式要求固定需要两个bin文件，因此在没有外挂psram使用psram.bin的情况下需要增加一个没有实际作用的loader_fake.bin文件。 +- rk2108_db_loader.bin：用于固件烧写的loader。 + +### 下载 + +保持maskrom按键按下的状态，然后重新上电或者按下reset按键，即可进入maskrom模式。 + +在Linux环境下，使用Rockchip工具upgrade_tool进行固件升级，脚本命令如下： + +```shell +sudo ./upgrade_firmware.sh +``` + +如果没有sudo权限，请联系管理员修改rule.d，让Rockchip的设备节点有rw权限。请管理员在/etc/udev/rules.d下面创建文件70-usbboot.rules。注意，不同的系统版本70-usbboot.rules文件命名的前缀数字不同。 + +```shell +cd /etc/udev/rules.d +sudo touch 70-usbboot.rules +``` + +在70-usbboot.rules文件中增加以下内容，其中“2207”为Rockchip USB设备的VID。 + +```shell +SUBSYSTEM=="usb", ATTRS{idVendor}=="2207", GROUP="plugdev", MODE="0666", ENV{ID_MM_DEVICE_IGNORE}="1" +``` + +完成以上修改后，普通用户使用Rockchip工具upgrade_tool进行固件升级，脚本命令如下： + +```shell +./upgrade_firmware.sh +``` + +在Windows环境下，使用Rockchip工具RKDevTool进行固件升级，首次使用前需要安装驱动程序DriverAssitant。工具获取请联系Rockchip。 + +## 维护 + +Steven Liu : steven.liu@rock-chips.com diff --git a/bsp/rockchip/rk2108/SConscript b/bsp/rockchip/rk2108/SConscript new file mode 100644 index 00000000000..467b041be5d --- /dev/null +++ b/bsp/rockchip/rk2108/SConscript @@ -0,0 +1,25 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +PROJECT = 'rk2108_evb' +Export('PROJECT') + +SOC = 'RK2108' +Export('SOC') + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +objs = SConscript(os.path.join(cwd, '../common/HalSConscript'), variant_dir = 'common/rk_hal', duplicate=0) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +objs = objs + SConscript(os.path.join(RTT_ROOT, 'bsp/rockchip/common/drivers/SConscript'), variant_dir = 'common/drivers', duplicate=0) + +Return('objs') diff --git a/bsp/rockchip/rk2108/SConstruct b/bsp/rockchip/rk2108/SConstruct new file mode 100644 index 00000000000..bf29cb287cc --- /dev/null +++ b/bsp/rockchip/rk2108/SConstruct @@ -0,0 +1,47 @@ +import os +import sys + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools'), os.path.join(os.getcwd(), '../tools')] + +from building import * +from buildutil import * + +import rtconfig + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +ld_dst = 'gcc_xip_off.ld' +cmd = '{cppcmd} -P -C -E -I. -D__ASSEMBLY__ {ld_src} -o {ld_dst}'.format( + cppcmd = os.path.join(rtconfig.EXEC_PATH, 'arm-none-eabi-gcc'), + ld_src = rtconfig.LINK_SCRIPT, + ld_dst = ld_dst) +if os.system(cmd) != 0: + print('failed to generate linker script %s' % ld_dst) + sys.exit(255) +# if the linker script changed, relink the target +Depends(TARGET, ld_dst) + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/rockchip/rk2108/applications/SConscript b/bsp/rockchip/rk2108/applications/SConscript new file mode 100644 index 00000000000..533df8ac31d --- /dev/null +++ b/bsp/rockchip/rk2108/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/rockchip/rk2108/applications/main.c b/bsp/rockchip/rk2108/applications/main.c new file mode 100644 index 00000000000..ef0a7a5300b --- /dev/null +++ b/bsp/rockchip/rk2108/applications/main.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-12 Steven Liu the first version + */ +#include +#include + +int main(int argc, char **argv) +{ + rt_kprintf("Hello RK2108 RT-Thread!\n"); + + return RT_EOK; +} + +void _start() +{ + extern int rtthread_startup(void); + + rtthread_startup(); +} diff --git a/bsp/rockchip/rk2108/board/Kconfig b/bsp/rockchip/rk2108/board/Kconfig new file mode 100644 index 00000000000..a1849746a34 --- /dev/null +++ b/bsp/rockchip/rk2108/board/Kconfig @@ -0,0 +1,21 @@ +menu "RT-Thread board config" + +config RT_BOARD_NAME + string "the board name you use" + default "rk2108_evb" + +config RT_RUN_MEM_BASE + hex "the memory base address you use" + default 0x20000000 + help + Set RK2108 SRAM MEM BASE. + +config RT_RUN_MEM_SIZE + hex "the memory size you use" + default 0x00100000 + help + Set RK2108 SRAM MEM SIZE + +source "$BSP_DIR/board/$RT_BOARD_NAME/Kconfig" + +endmenu diff --git a/bsp/rockchip/rk2108/board/SConscript b/bsp/rockchip/rk2108/board/SConscript new file mode 100644 index 00000000000..f3d89c90fe2 --- /dev/null +++ b/bsp/rockchip/rk2108/board/SConscript @@ -0,0 +1,12 @@ +# for board compiling +import os +import rtconfig +from building import * +from buildutil import * + +cwd = GetCurrentDir() +BOARD_NAME = GetStringFromConfig(cwd + '/..', 'RT_BOARD_NAME') +objs = SConscript(os.path.join(cwd, BOARD_NAME + '/SConscript'), variant_dir = 'board/' + BOARD_NAME, duplicate = 0) +objs += SConscript(os.path.join(cwd, 'common/SConscript'), variant_dir = 'board/common', duplicate = 0) + +Return('objs') diff --git a/bsp/rockchip/rk2108/board/common/SConscript b/bsp/rockchip/rk2108/board/common/SConscript new file mode 100644 index 00000000000..09f625bb698 --- /dev/null +++ b/bsp/rockchip/rk2108/board/common/SConscript @@ -0,0 +1,18 @@ +# for board compiling +import os +import rtconfig +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +list = os.listdir(cwd) +CPPPATH = [cwd] + +objs = DefineGroup('BoardCommon', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/rockchip/rk2108/board/common/board_base.c b/bsp/rockchip/rk2108/board/common/board_base.c new file mode 100644 index 00000000000..1da53b77578 --- /dev/null +++ b/bsp/rockchip/rk2108/board/common/board_base.c @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-12 Steven Liu first implementation + */ + +#include +#include + +#include "board.h" +#include "hal_base.h" +#include "hal_bsp.h" +#include "drv_cache.h" +#include "drv_heap.h" + +#ifdef RT_USING_CRU +#include "drv_clock.h" +#endif + +#ifdef RT_USING_PIN +#include "iomux.h" +#endif + +#ifdef RT_USING_UART +#include "drv_uart.h" +#endif + +#ifdef RT_USING_MODULE +#define DATA_EXEC_FLAG 0U +#else +#define DATA_EXEC_FLAG 1U +#endif + +#ifdef RT_USING_CRU +RT_WEAK const struct clk_init clk_inits[] = +{ + INIT_CLK("SCLK_SHRM", SCLK_SHRM, 10 * MHZ), + INIT_CLK("PCLK_SHRM", PCLK_SHRM, 10 * MHZ), + INIT_CLK("PCLK_ALIVE", PCLK_ALIVE, 10 * MHZ), + INIT_CLK("HCLK_ALIVE", HCLK_ALIVE, 10 * MHZ), + INIT_CLK("HCLK_M4", HCLK_M4, 10 * MHZ), + INIT_CLK("ACLK_LOGIC", ACLK_LOGIC, 10 * MHZ), + INIT_CLK("HCLK_LOGIC", HCLK_LOGIC, 10 * MHZ), + INIT_CLK("PCLK_LOGIC", PCLK_LOGIC, 10 * MHZ), + INIT_CLK("SCLK_SFC_SRC", SCLK_SFC_SRC, 5 * MHZ), + INIT_CLK("SCLK_SFC1_SRC", SCLK_SFC1_SRC, 5 * MHZ), + INIT_CLK("PLL_GPLL", PLL_GPLL, 1188 * MHZ), + INIT_CLK("PLL_CPLL", PLL_CPLL, 1188 * MHZ), + INIT_CLK("SCLK_SFC_SRC", SCLK_SFC_SRC, 50 * MHZ), + INIT_CLK("HCLK_M4", HCLK_M4, 300 * MHZ), + INIT_CLK("ACLK_DSP", ACLK_DSP, 400 * MHZ), + INIT_CLK("ACLK_LOGIC", ACLK_LOGIC, 300 * MHZ), + INIT_CLK("HCLK_LOGIC", HCLK_LOGIC, 150 * MHZ), + INIT_CLK("PCLK_LOGIC", PCLK_LOGIC, 150 * MHZ), + INIT_CLK("SCLK_SHRM", SCLK_SHRM, 300 * MHZ), + INIT_CLK("PCLK_SHRM", PCLK_SHRM, 100 * MHZ), + INIT_CLK("PCLK_ALIVE", PCLK_ALIVE, 100 * MHZ), + INIT_CLK("HCLK_ALIVE", HCLK_ALIVE, 100 * MHZ), + { /* sentinel */ }, +}; + +RT_WEAK const struct clk_unused clks_unused[] = +{ + {0, 0, 0x00030003}, + {0, 5, 0x00ee00ee}, + {0, 6, 0x048d048d}, + {0, 7, 0x00110011}, + {0, 11, 0x40e040e0}, + {0, 12, 0x90709070}, + {0, 13, 0xe203e203}, + {0, 14, 0xa6e1a6e1}, + { /* sentinel */ }, +}; +#endif + +#if defined(RT_USING_UART0) +RT_WEAK const struct uart_board g_uart0_board = +{ + .baud_rate = ROCKCHIP_UART_BAUD_RATE_DEFAULT, + .dev_flag = ROCKCHIP_UART_SUPPORT_FLAG_DEFAULT, + .bufer_size = RT_SERIAL_RB_BUFSZ, + .name = "uart0", +}; +#endif /* RT_USING_UART0 */ + +#if defined(RT_USING_UART1) +RT_WEAK const struct uart_board g_uart1_board = +{ + .baud_rate = ROCKCHIP_UART_BAUD_RATE_DEFAULT, + .dev_flag = ROCKCHIP_UART_SUPPORT_FLAG_DEFAULT, + .bufer_size = RT_SERIAL_RB_BUFSZ, + .name = "uart1", +}; +#endif /* RT_USING_UART1 */ + +#if defined(RT_USING_UART2) +RT_WEAK const struct uart_board g_uart2_board = +{ + .baud_rate = ROCKCHIP_UART_BAUD_RATE_DEFAULT, + .dev_flag = ROCKCHIP_UART_SUPPORT_FLAG_DEFAULT, + .bufer_size = RT_SERIAL_RB_BUFSZ, + .name = "uart2", +}; +#endif /* RT_USING_UART2 */ + +extern void SysTick_Handler(void); +RT_WEAK void tick_isr(int vector, void *param) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_IncTick(); + rt_tick_increase(); +#ifdef TICK_TIMER + HAL_TIMER_ClrInt(TICK_TIMER); +#endif + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void BSP_MPU_Init(void) +{ + static const ARM_MPU_Region_t table[] = + { + { + .RBAR = ARM_MPU_RBAR(0U, 0x04000000U), + .RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 1U, 0U, 0U, ARM_MPU_REGION_SIZE_1MB) + }, + { + .RBAR = ARM_MPU_RBAR(1U, 0x18000000U), + .RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 1U, 0U, 0U, ARM_MPU_REGION_SIZE_32MB) + }, + { + .RBAR = ARM_MPU_RBAR(2U, 0x20000000U), + .RASR = ARM_MPU_RASR(DATA_EXEC_FLAG, ARM_MPU_AP_FULL, 0U, 0U, 1U, 1U, 0U, ARM_MPU_REGION_SIZE_1MB) + }, + { + .RBAR = ARM_MPU_RBAR(3U, 0x40000000U), + .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_256MB) + }, + { + .RBAR = ARM_MPU_RBAR(4U, 0x60000000U), + .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 1U, 1U, 0U, ARM_MPU_REGION_SIZE_256MB) + }, + }; + + ARM_MPU_Load(&(table[0]), 5U); + +#ifdef RT_USING_UNCACHE_HEAP + ARM_MPU_Region_t uncache_region; + + uncache_region.RBAR = ARM_MPU_RBAR(5U, RK_UNCACHE_HEAP_START); + uncache_region.RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, RT_UNCACHE_HEAP_ORDER); + ARM_MPU_SetRegionEx(5, uncache_region.RBAR, uncache_region.RASR); +#endif + + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); +} + +/** + * Initialize the Hardware related stuffs. Called from rtthread_startup() + * after interrupt disabled. + */ +void rt_hw_board_init(void) +{ + /* HAL_Init */ + HAL_Init(); + + /* hal bsp init */ + BSP_Init(); + + /* tick init */ + HAL_SetTickFreq(1000 / RT_TICK_PER_SECOND); + rt_hw_interrupt_install(TICK_IRQn, tick_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(TICK_IRQn); + HAL_NVIC_SetPriority(TICK_IRQn, NVIC_PERIPH_PRIO_LOWEST, NVIC_PERIPH_SUB_PRIO_LOWEST); +#ifdef RT_USING_SYSTICK + HAL_SYSTICK_CLKSourceConfig(HAL_SYSTICK_CLKSRC_EXT); + HAL_SYSTICK_Config((PLL_INPUT_OSC_RATE / RT_TICK_PER_SECOND) - 1); + HAL_SYSTICK_Enable(); +#else + HAL_TIMER_Init(TICK_TIMER, TIMER_FREE_RUNNING); + HAL_TIMER_SetCount(TICK_TIMER, (PLL_INPUT_OSC_RATE / RT_TICK_PER_SECOND) - 1); + HAL_TIMER_Start_IT(TICK_TIMER); +#endif + + rt_hw_cpu_cache_init(); + +#ifdef RT_USING_PIN +#ifdef RK_BSP_TEMP + rt_hw_iomux_config(); +#endif +#endif + +#ifdef RT_USING_CRU +#ifdef RK_BSP_TEMP + clk_init(clk_inits, false); + + /* disable some clks when init, and enabled by device when needed */ + clk_disable_unused(clks_unused); + if (RT_CONSOLE_DEVICE_UART(0)) + CRU->CRU_CLKGATE_CON[2] = 0x08860886; + else if (RT_CONSOLE_DEVICE_UART(1)) + CRU->CRU_CLKGATE_CON[2] = 0x080d080d; + else if (RT_CONSOLE_DEVICE_UART(2)) + CRU->CRU_CLKGATE_CON[2] = 0x008b008b; + else + CRU->CRU_CLKGATE_CON[2] = 0x088f088f; +#endif +#endif + +#ifdef RT_USING_UART + rt_hw_usart_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_HEAP + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + diff --git a/bsp/rockchip/rk2108/board/common/board_base.h b/bsp/rockchip/rk2108/board/common/board_base.h new file mode 100644 index 00000000000..a4418e7d681 --- /dev/null +++ b/bsp/rockchip/rk2108/board/common/board_base.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-12 Steven Liu first implementation + */ + +#ifndef __BOARD_BASE_H__ +#define __BOARD_BASE_H__ + +#include "rtconfig.h" +#include "hal_base.h" + +extern uint32_t __heap_begin[]; +extern uint32_t __heap_end[]; + +#define RT_HW_HEAP_BEGIN (void*)&__heap_begin +#define RT_HW_HEAP_END (void*)&__heap_end + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/rockchip/rk2108/board/common/iomux_base.c b/bsp/rockchip/rk2108/board/common/iomux_base.c new file mode 100644 index 00000000000..0efb098c79e --- /dev/null +++ b/bsp/rockchip/rk2108/board/common/iomux_base.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-12 Steven Liu first implementation + */ + +#include "rtdef.h" +#include "iomux.h" +#include "hal_base.h" + +/** + * @brief Config iomux for M4 JTAG + */ +RT_WEAK void m4_jtag_iomux_config(void) +{ + HAL_PINCTRL_SetIOMUX(GPIO_BANK0, + GPIO_PIN_C7 | // M4_JTAG_TCK + GPIO_PIN_D0, // M4_JTAG_TMS + PIN_CONFIG_MUX_FUNC2); +} + +/** + * @brief Config iomux for UART0 + */ +RT_WEAK void uart0_iomux_config(void) +{ + HAL_PINCTRL_SetIOMUX(GPIO_BANK0, + GPIO_PIN_C7 | // UART0_RX + GPIO_PIN_D0, // UART0_TX + PIN_CONFIG_MUX_FUNC1); +} + +/** + * @brief Config iomux for UART1 + */ +RT_WEAK void uart1_m0_iomux_config(void) +{ + HAL_PINCTRL_SetIOMUX(GPIO_BANK0, + GPIO_PIN_D1 | // UART1_RX_M0 + GPIO_PIN_D2, // UART1_TX_M0 + PIN_CONFIG_MUX_FUNC2); + + WRITE_REG_MASK_WE(GRF->SOC_CON5, + GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_MASK, + (0 << GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_SHIFT)); +} + +RT_WEAK void uart1_m1_iomux_config(void) +{ + HAL_PINCTRL_SetIOMUX(GPIO_BANK0, + GPIO_PIN_A5 | // UART1_RX_M1 + GPIO_PIN_A4, // UART1_TX_M1 + PIN_CONFIG_MUX_FUNC2); + + WRITE_REG_MASK_WE(GRF->SOC_CON5, + GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_MASK, + (1 << GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_SHIFT)); +} + +RT_WEAK void uart1_m2_iomux_config(void) +{ + HAL_PINCTRL_SetIOMUX(GPIO_BANK1, + GPIO_PIN_B1 | // UART1_RX_M2 + GPIO_PIN_B0, // UART1_TX_M2 + PIN_CONFIG_MUX_FUNC3); + + WRITE_REG_MASK_WE(GRF->SOC_CON5, + GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_MASK, + (2 << GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_SHIFT)); +} + +RT_WEAK void uart1_m3_iomux_config(void) +{ + HAL_PINCTRL_SetIOMUX(GPIO_BANK0, + GPIO_PIN_A5, // UART1_RX_M3 + PIN_CONFIG_MUX_FUNC2); + + HAL_PINCTRL_SetIOMUX(GPIO_BANK0, + GPIO_PIN_B1, // UART1_TX_M3 + PIN_CONFIG_MUX_FUNC4); + + WRITE_REG_MASK_WE(GRF->SOC_CON5, + GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_MASK, + (3 << GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_SHIFT)); +} + +/** + * @brief Config iomux for UART2 + */ +RT_WEAK void uart2_iomux_config(void) +{ + HAL_PINCTRL_SetIOMUX(GPIO_BANK1, + GPIO_PIN_A0 | // UART2_RX + GPIO_PIN_A1 | // UART2_TX + GPIO_PIN_A2 | // UART2_CTS + GPIO_PIN_A3, // UART2_RTS + PIN_CONFIG_MUX_FUNC4); +} + +/** + * @brief Config iomux for RK2108 + */ +RT_WEAK void rt_hw_iomux_config(void) +{ + uart2_iomux_config(); + +#ifdef M4_JTAG_ENABLE + m4_jtag_iomux_config(); +#else + uart0_iomux_config(); +#endif +} diff --git a/bsp/rockchip/rk2108/board/common/iomux_base.h b/bsp/rockchip/rk2108/board/common/iomux_base.h new file mode 100644 index 00000000000..73d08893df7 --- /dev/null +++ b/bsp/rockchip/rk2108/board/common/iomux_base.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-12 Steven Liu first implementation + */ + +#ifndef __IOMUX_BASE_H__ +#define __IOMUX_BASE_H__ + +void m4_jtag_iomux_config(void); +void uart0_iomux_config(void); +void uart1_m0_iomux_config(void); +void uart1_m1_iomux_config(void); +void uart1_m2_iomux_config(void); +void uart1_m3_iomux_config(void); +void uart2_iomux_config(void); +void rt_hw_iomux_config(void); + +#endif diff --git a/bsp/rockchip/rk2108/board/common/setting.ini b/bsp/rockchip/rk2108/board/common/setting.ini new file mode 100755 index 00000000000..e517035ecaa --- /dev/null +++ b/bsp/rockchip/rk2108/board/common/setting.ini @@ -0,0 +1,34 @@ +#Flag: +#bits filed: +# [0] : skip : 0 - disabled(default), 1 - enable +# [2] : no partition size : 0 - diabled(default), 1 - enable +# [8, 9] : property : 0 - do not register(default), 1 - read only, 2 - write only, 3 - rw +# [10] : register type : 0 - block partition(default), 1 - MTD partition +#type can suppot 32 partiton types,0x0:undefined 0x1:Vendor 0x2:IDBlock ,bit3:bit31 are available +#PartSize and PartOffset unit by sector +#Gpt_Enable 1:compact gpt,0:normal gpt +#Backup_Partition_Enable 0:no backup,1:backup +#Loader_Encrypt 0:no encrypt,1:rc4 +#nano 1:generate idblock in nano format +[System] +FwVersion=1.0 +Gpt_Enable= +Backup_Partition_Enable= +Nano= +Loader_Encrypt=0 +Chip= +Model= +[UserPart1] +Name=IDBlock +Type=0x2 +PartOffset=0x80 +PartSize=0x80 +Flag= +File=../../image/rk2108_loader.bin,../../image/rk2108_loader_fake.bin +[UserPart2] +Name=RTTHREAD +Type=0x8 +PartOffset=0x100 +PartSize=0x100 +Flag= +File=../../image/rtthread.img diff --git a/bsp/rockchip/rk2108/board/rk2108_evb/Kconfig b/bsp/rockchip/rk2108/board/rk2108_evb/Kconfig new file mode 100644 index 00000000000..6ffc1969759 --- /dev/null +++ b/bsp/rockchip/rk2108/board/rk2108_evb/Kconfig @@ -0,0 +1,6 @@ +config M4_JTAG_ENABLE + bool "Enable Cortex M4 JTAG" + default n + select RT_USING_UART2 + help + you need set RT_CONSOLE_DEVICE_NAME=uart2 at the same time diff --git a/bsp/rockchip/rk2108/board/rk2108_evb/SConscript b/bsp/rockchip/rk2108/board/rk2108_evb/SConscript new file mode 100644 index 00000000000..36c48cc8c43 --- /dev/null +++ b/bsp/rockchip/rk2108/board/rk2108_evb/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('BoardConfig', src, depend = [], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/rockchip/rk2108/board/rk2108_evb/board.c b/bsp/rockchip/rk2108/board/rk2108_evb/board.c new file mode 100644 index 00000000000..0c669519a9f --- /dev/null +++ b/bsp/rockchip/rk2108/board/rk2108_evb/board.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-12 Steven Liu first implementation + */ + +#include +#include + +#include "board.h" + diff --git a/bsp/rockchip/rk2108/board/rk2108_evb/board.h b/bsp/rockchip/rk2108/board/rk2108_evb/board.h new file mode 100644 index 00000000000..a42c4dce3a9 --- /dev/null +++ b/bsp/rockchip/rk2108/board/rk2108_evb/board.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-12 Steven Liu first implementation + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "board_base.h" +#include "hal_base.h" + +#endif diff --git a/bsp/rockchip/rk2108/board/rk2108_evb/iomux.c b/bsp/rockchip/rk2108/board/rk2108_evb/iomux.c new file mode 100644 index 00000000000..17a9088e9f5 --- /dev/null +++ b/bsp/rockchip/rk2108/board/rk2108_evb/iomux.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-12 Steven Liu first implementation + */ + +#include "rtdef.h" +#include "iomux.h" +#include "hal_base.h" + +/** + * @brief Config iomux for RK3568 + */ +void rt_hw_iomux_config(void) +{ + uart2_iomux_config(); + +#ifdef M4_JTAG_ENABLE + m4_jtag_iomux_config(); +#else + uart0_iomux_config(); +#endif +} diff --git a/bsp/rockchip/rk2108/board/rk2108_evb/iomux.h b/bsp/rockchip/rk2108/board/rk2108_evb/iomux.h new file mode 100644 index 00000000000..0aaa5981591 --- /dev/null +++ b/bsp/rockchip/rk2108/board/rk2108_evb/iomux.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-12 Steven Liu first implementation + */ + +#ifndef __IOMUX_H__ +#define __IOMUX_H__ + +#include "iomux_base.h" + +#endif diff --git a/bsp/rockchip/rk2108/driver/Kconfig b/bsp/rockchip/rk2108/driver/Kconfig new file mode 100644 index 00000000000..abfbfdddfb8 --- /dev/null +++ b/bsp/rockchip/rk2108/driver/Kconfig @@ -0,0 +1,33 @@ +source "$BSP_DIR/../common/drivers/Kconfig" + +menu "RT-Thread rockchip RK2108 drivers" + +config RT_USING_CRU + bool "Enable CRU" + default n + +menu "Enable UART" + config RT_USING_UART + bool "Enable UART" + default y + + if RT_USING_UART + config RT_USING_UART0 + bool "Enable UART0" + default n + + config RT_USING_UART1 + bool "Enable UART1" + default n + + config RT_USING_UART2 + bool "Enable UART2" + default y + endif +endmenu + +config RT_USING_SYSTICK + bool "Enable SYSTICK" + default n + +endmenu diff --git a/bsp/rockchip/rk2108/driver/SConscript b/bsp/rockchip/rk2108/driver/SConscript new file mode 100644 index 00000000000..a29d4f6e2cf --- /dev/null +++ b/bsp/rockchip/rk2108/driver/SConscript @@ -0,0 +1,28 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +if rtconfig.CROSS_TOOL == 'gcc': + src += Glob(RTT_ROOT + '/bsp/rockchip/common/drivers/drv_cache_gcc.S') +elif rtconfig.CROSS_TOOL == 'keil': + src += Glob(RTT_ROOT + '/bsp/rockchip/common/drivers/drv_cache_arm.s') +elif rtconfig.CROSS_TOOL == 'iar': + src += Glob(RTT_ROOT + '/bsp/rockchip/common/drivers/drv_cache_iar.s') + +group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH) + +# build for sub-directory +list = os.listdir(cwd) +objs = [] + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +group = group + objs + +Return('group') diff --git a/bsp/rockchip/rk2108/gcc_xip_off.ld.S b/bsp/rockchip/rk2108/gcc_xip_off.ld.S new file mode 100644 index 00000000000..3685766aabd --- /dev/null +++ b/bsp/rockchip/rk2108/gcc_xip_off.ld.S @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "rtconfig.h" + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x18000000, LENGTH = 16M /* Nor Flash */ + SRAM_I (rxw) : ORIGIN = 0x04000000, LENGTH = 1M /* SRAM */ + SRAM_D (rxw) : ORIGIN = 0x20000000, LENGTH = 1M /* SRAM */ +} + +MAIN_STACK_SIZE = 0x400; + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + . = ALIGN(32); + KEEP(*(.vectors)) + . = ALIGN(32); + + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + *(.rodata*) + + *(COMMON) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + . = ALIGN(4); + + KEEP(*(.eh_frame*)) + } > SRAM_I + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > SRAM_I + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > SRAM_I + + .ctors : + { + . = ALIGN(32); + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + . = ALIGN(32); + PROVIDE(__ctors_end__ = .); + } > SRAM_I + + .dtors : + { + . = ALIGN(32); + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(32); + PROVIDE(__dtors_end__ = .); + } > SRAM_I + + .copy.table : + { + . = ALIGN(32); + PROVIDE(__copy_table_start__ = .); + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + PROVIDE(__copy_table_end__ = .); + } > SRAM_I + + .zero.table : + { + . = ALIGN(32); + PROVIDE(__zero_table_start__ = .); + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__) / 4) + PROVIDE(__zero_table_end__ = .); + } > SRAM_I + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned. In addition, 32byte cacheline alignment + * is required here, because of RK2108 with cache. + */ + __etext = ALIGN (32); + + SRAM_DATA_DEST = ORIGIN(SRAM_D) + __etext - ORIGIN(SRAM_I); + + .data SRAM_DATA_DEST : AT (__etext) + { + __data_start__ = ALIGN (32); + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + _gp = ABSOLUTE(.); /* Base of small data */ + + . = ALIGN(32); + /* All data end */ + __data_end__ = .; + } > SRAM_D + + .bss : + { + . = ALIGN(32); + PROVIDE(__bss_start__ = .); + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + . = ALIGN(32); + PROVIDE(__bss_end__ = .); + } > SRAM_D + + .stack : + { + . = ALIGN(32); + __StackLimit = .; + . = . + MAIN_STACK_SIZE; + . = ALIGN(32); + __StackTop = .; + __stack = __StackTop; + } > SRAM_D + + .heap : + { + . = ALIGN(32); + PROVIDE(__heap_begin = .); + __end__ = .; + PROVIDE(end = .); + . = ORIGIN(SRAM_D) + LENGTH(SRAM_D); + __HeapLimit = .; + PROVIDE(__heap_end = .); + } > SRAM_D +} diff --git a/bsp/rockchip/rk2108/hal_conf.h b/bsp/rockchip/rk2108/hal_conf.h new file mode 100644 index 00000000000..ba5b4ad43ab --- /dev/null +++ b/bsp/rockchip/rk2108/hal_conf.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-12 Steven Liu first implementation + */ + +#ifndef _HAL_CONF_H_ +#define _HAL_CONF_H_ + +#include "rtconfig.h" + +/* HAL CPU config */ +#define SOC_RK2108 +#define HAL_MCU_CORE +#define SYS_TIMER TIMER5 + +/* RT-Thread Tick Timer */ +#ifdef RT_USING_SYSTICK +#define TICK_IRQn SysTick_IRQn +#define HAL_SYSTICK_MODULE_ENABLED +#else +#define TICK_TIMER TIMER4 +#define TICK_IRQn TIMER4_IRQn +#endif + +#ifdef RT_USING_CACHE +#define HAL_DCACHE_MODULE_ENABLED +#define HAL_ICACHE_MODULE_ENABLED +#endif + +#ifdef RT_USING_CRU +#define HAL_CRU_MODULE_ENABLED +#endif + +#define HAL_NVIC_MODULE_ENABLED + +#ifdef RT_USING_PIN +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PINCTRL_MODULE_ENABLED +#endif + +#ifdef RT_USING_PM_RUNTIME +#define HAL_PM_RUNTIME_MODULE_ENABLED +#endif + +#define HAL_TIMER_MODULE_ENABLED + +#ifdef RT_USING_UART +#define HAL_UART_MODULE_ENABLED +#endif + +#endif diff --git a/bsp/rockchip/rk2108/image/config.json b/bsp/rockchip/rk2108/image/config.json new file mode 100755 index 00000000000..29b1d817ebe --- /dev/null +++ b/bsp/rockchip/rk2108/image/config.json @@ -0,0 +1,8 @@ +{ + "MAGIC": "RESC", + "CHIP": "RK2108", + "MODEL": "RT_THREAD", + "DESC": "RK2108 RT_THREAD", + "VERSION": "1.00.0000", + "DIGEST": "JSHASH" +} diff --git a/bsp/rockchip/rk2108/mkimage.sh b/bsp/rockchip/rk2108/mkimage.sh new file mode 100755 index 00000000000..24cc05e3fbb --- /dev/null +++ b/bsp/rockchip/rk2108/mkimage.sh @@ -0,0 +1,28 @@ +#! /bin/bash + +export LC_ALL=C.UTF-8 +export LANG=C.UTF-8 + +usage() { + echo "usage: ./mkimage.sh [partition_setting]" +} + +CUR_DIR=$(pwd) +TOOLS=$CUR_DIR/../tools +IMAGE=$CUR_DIR/image + +rm -rf $CUR_DIR/rtthread.bin $IMAGE/rtthread.img $IMAGE/Firmware* +scons -c +scons -j16 +cp -r $CUR_DIR/rtthread.bin $IMAGE/rtthread.img +$TOOLS/resource_header_tool pack --json $IMAGE/config.json $IMAGE/rtthread.img > /dev/null + +echo 'Image: rthread image is ready' + +if [ ! -n "$1" ] ;then + $TOOLS/firmware_merger -p $CUR_DIR/board/common/setting.ini $IMAGE/ +else + $TOOLS/firmware_merger -p $1 $IMAGE/ +fi + +echo 'Image: firmware image is ready' diff --git a/bsp/rockchip/rk2108/rtconfig.h b/bsp/rockchip/rk2108/rtconfig.h new file mode 100644 index 00000000000..d82aa699c5c --- /dev/null +++ b/bsp/rockchip/rk2108/rtconfig.h @@ -0,0 +1,153 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x40100 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + +#define BSP_RK2108 + +/* RT-Thread board config */ + +#define RT_BOARD_NAME "rk2108_evb" +#define RT_RUN_MEM_BASE 0x20000000 +#define RT_RUN_MEM_SIZE 0x00100000 +#define M4_JTAG_ENABLE + +/* RT-Thread rockchip common drivers */ + +#define RT_USING_CACHE +#define RT_USING_PM_RUNTIME + +/* RT-Thread rockchip RK2108 drivers */ + +#define RT_USING_CRU + +/* Enable UART */ + +#define RT_USING_UART +#define RT_USING_UART2 +#define RT_USING_SYSTICK + +#endif diff --git a/bsp/rockchip/rk2108/rtconfig.py b/bsp/rockchip/rk2108/rtconfig.py new file mode 100644 index 00000000000..01cad96919e --- /dev/null +++ b/bsp/rockchip/rk2108/rtconfig.py @@ -0,0 +1,59 @@ +import os +import sys + +from building import * + +# toolchains options +ARCH ='arm' +CPU ='cortex-m4' +CROSS_TOOL ='gcc' + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = r'../../..' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +PLATFORM = 'gcc' +EXEC_PATH = RTT_ROOT + '/../prebuilts/gcc/linux-x86/arm/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux/bin/' + +BUILD = 'release' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +if PLATFORM == 'gcc': + # toolchains + # PREFIX = 'arm-none-eabi-' + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections --specs=nano.specs' + CFLAGS = DEVICE + ' -std=gnu99 -Wall -g -Wno-stringop-truncation -Wall -Werror=maybe-uninitialized -Werror=implicit-function-declaration -Werror=return-type -Werror=address -Werror=int-to-pointer-cast -Werror=pointer-to-int-cast' + AFLAGS = DEVICE + ' -c -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__ASSEMBLY__' + LINK_SCRIPT = 'gcc_xip_off.ld.S' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T gcc_xip_off.ld' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + diff --git a/bsp/rockchip/rk2108/update_fimeware.sh b/bsp/rockchip/rk2108/update_fimeware.sh new file mode 100755 index 00000000000..c0db94a5ff9 --- /dev/null +++ b/bsp/rockchip/rk2108/update_fimeware.sh @@ -0,0 +1,15 @@ +#!/bin/sh + +export LC_ALL=C.UTF-8 +export LANG=C.UTF-8 + +usage() { + echo "usage: ./update_firmware.sh" +} + +CUR_DIR=$(pwd) +TOOLS=$CUR_DIR/../tools + +$TOOLS/upgrade_tool db $CUR_DIR/image/rk2108_db_loader.bin +$TOOLS/upgrade_tool wl 0 $CUR_DIR/image/Firmware.img +$TOOLS/upgrade_tool rd diff --git a/bsp/rockchip/tools/buildutil.py b/bsp/rockchip/tools/buildutil.py new file mode 100644 index 00000000000..ea51cfca6b5 --- /dev/null +++ b/bsp/rockchip/tools/buildutil.py @@ -0,0 +1,63 @@ +import os + +def GetStringFromConfig(bsp_dir, string): + try: + config = open(bsp_dir + '/rtconfig.h', 'r') + except IOError: + print('no found rtconfig.h, use scons --menuconfig before compile') + else: + cfg_list = config.readlines() + for cfg in cfg_list: + if cfg.find(string) != -1: + target = cfg[cfg.find('"'):-1] + target = eval(target) + config.close() + return target + print('no found ' + string + ' in rtconfig.h, you must define this in kconfig of board') + + return '' + +def GetRTConfigOption(bsp_dir, option): + value = False + try: + config = open(bsp_dir + '/rtconfig.h', 'r') + except IOError: + print('no found rtconfig.h, use scons --menuconfig before compile') + else: + cfg_list = config.readlines() + for cfg in cfg_list: + if cfg.find('#define ' + option) != -1: + cfg = cfg.rstrip('\n') + values = cfg.split(' ') + + if len(values) == 3: + value = values[2] + else: + value = True + + config.close() + return value + + return value + +def GetImageSetting(bsp_dir): + board = GetStringFromConfig(bsp_dir, 'RT_BOARD_NAME') + path = 'board/{dir}/setting.ini'.format(dir = board) + if (bsp_dir.endswith('/') == False): + bsp_dir += '/' + if os.path.exists(bsp_dir + path) == True: + return path + else: + return 'board/common/setting.ini' + +def ParsePartitionStart(bsp_dir, name): + start = -1 + path = GetImageSetting(bsp_dir) + configer = configparser.ConfigParser() + configer.read(path) + for section in configer.sections(): + if (configer.has_option(section, 'Name')): + if configer.get(section, 'Name') == name: + sector = int(configer.get(section, 'PartOffset'), 16) + start = (sector + 1) * 512 + return start diff --git a/bsp/rockchip/tools/config.ini b/bsp/rockchip/tools/config.ini new file mode 100755 index 00000000000..ea1eb033c05 --- /dev/null +++ b/bsp/rockchip/tools/config.ini @@ -0,0 +1,11 @@ +firmware= +loader= +parameter= +misc= +boot= +kernel= +system= +recovery= +rockusb_id= +msc_id= +rb_check_off=true diff --git a/bsp/rockchip/tools/firmware_merger b/bsp/rockchip/tools/firmware_merger new file mode 100755 index 00000000000..61c17be7b20 Binary files /dev/null and b/bsp/rockchip/tools/firmware_merger differ diff --git a/bsp/rockchip/tools/resource_header_tool b/bsp/rockchip/tools/resource_header_tool new file mode 100755 index 00000000000..f4411203643 Binary files /dev/null and b/bsp/rockchip/tools/resource_header_tool differ diff --git a/bsp/rockchip/tools/upgrade_tool b/bsp/rockchip/tools/upgrade_tool new file mode 100755 index 00000000000..7dc5d76bc40 Binary files /dev/null and b/bsp/rockchip/tools/upgrade_tool differ