diff --git a/bsp/nuvoton/README.md b/bsp/nuvoton/README.md
new file mode 100644
index 00000000000..f4dc8222235
--- /dev/null
+++ b/bsp/nuvoton/README.md
@@ -0,0 +1,7 @@
+# Nuvoton BSP descriptions
+Current supported BSP shown in below table:
+
+| **BSP folder** | **Board name** |
+|:------------------------- |:-------------------------- |
+| [numaker-iot-m487](numaker-iot-m487) | Nuvoton NuMaker-IoT-m487 |
+| [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-m487 |
diff --git a/bsp/nuvoton/libraries/Kconfig b/bsp/nuvoton/libraries/Kconfig
new file mode 100644
index 00000000000..5c406628837
--- /dev/null
+++ b/bsp/nuvoton/libraries/Kconfig
@@ -0,0 +1,2 @@
+config SOC_FAMILY_NUMICRO
+ bool
diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_common_tables.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 00000000000..8742a569915
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. October 2015
+* $Revision: V.1.4.5 a
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_const_structs.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 00000000000..726d06eb692
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_const_structs.h
+*
+* Description: This file has constant structs that are initialized for
+* user convenience. For example, some can be given as
+* arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_math.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_math.h
new file mode 100644
index 00000000000..d33f8a9b3b5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_math.h
@@ -0,0 +1,7154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date: 20. October 2015
+* $Revision: V1.4.5 b
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+ * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+ *
+ * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __GNUC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __ICCARM__
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+
+#elif defined __CSMC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+
+#elif defined __TASKING__
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+/*
+ #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+ #define __CLZ __clz
+ #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+ }
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+ }
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ */
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__)
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 00000000000..74c49c67def
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,734 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc_V6.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc_V6.h
new file mode 100644
index 00000000000..cd13240ce36
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc_V6.h
@@ -0,0 +1,1800 @@
+/**************************************************************************//**
+ * @file cmsis_armcc_V6.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_V6_H
+#define __CMSIS_ARMCC_V6_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get IPSR Register (non-secure)
+ \details Returns the content of the non-secure IPSR Register when in secure state.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get APSR Register (non-secure)
+ \details Returns the content of the non-secure APSR Register when in secure state.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get xPSR Register (non-secure)
+ \details Returns the content of the non-secure xPSR Register when in secure state.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority with condition (non_secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+
+#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */
+
+/**
+ \brief Get FPSCR
+ \details eturns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#define __get_FPSCR __builtin_arm_get_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get FPSCR (non-secure)
+ \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.
+ \return Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#define __set_FPSCR __builtin_arm_set_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set FPSCR (non-secure)
+ \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __builtin_bswap32
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+/*#define __SSAT __builtin_arm_ssat*/
+#define __SSAT(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+#if 0
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+#endif
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1U) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_V6_H */
diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_gcc.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 00000000000..bb89fbba9e4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,1373 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm0.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm0.h
new file mode 100644
index 00000000000..711dad55170
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm0.h
@@ -0,0 +1,798 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & 0x00000FF0UL) == 0x220UL)
+ {
+ return 2UL; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
+ {
+ return 1UL; /* Single precision FPU */
+ }
+ else
+ {
+ return 0UL; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmInstr.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 00000000000..f474b0e6f36
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmSimd.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmSimd.h
new file mode 100644
index 00000000000..66bf5c2a725
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file core_cmSimd.h
+ * @brief CMSIS Cortex-M SIMD Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_sc000.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_sc000.h
new file mode 100644
index 00000000000..514dbd81b9f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_sc000.h
@@ -0,0 +1,926 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .hIntroduction
+ *
+ * This user manual describes the usage of M480 Series MCU device driver
+ *
+ * Disclaimer
+ *
+ * The Software is furnished "AS IS", without warranty as to performance or results, and
+ * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+ * warranties, express, implied or otherwise, with regard to the Software, its use, or
+ * operation, including without limitation any and all warranties of merchantability, fitness
+ * for a particular purpose, and non-infringement of intellectual property rights.
+ *
+ * Important Notice
+ *
+ * Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
+ * any malfunction or failure of which may cause loss of human life, bodily injury or severe
+ * property damage. Such applications are deemed, "Insecure Usage".
+ *
+ * Insecure usage includes, but is not limited to: equipment for surgical implementation,
+ * atomic energy control instruments, airplane or spaceship instruments, the control or
+ * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
+ * instruments, all types of safety devices, and other applications intended to support or
+ * sustain life.
+ *
+ * All Insecure Usage shall be made at customer's risk, and in the event that third parties
+ * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
+ * the damages and liabilities thus incurred by Nuvoton.
+ *
+ * Please note that all data and specifications are subject to change without notice. All the
+ * trademarks of products and companies mentioned in this datasheet belong to their respective
+ * owners.
+ *
+ * Copyright Notice
+ *
+ * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ */
+#ifndef __M480_H__
+#define __M480_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup CMSIS_Device Device CMSIS Definitions
+ Configuration of the Cortex-M4 Processor and Core Peripherals
+ @{
+*/
+
+/**
+ * @details Interrupt Number Definition.
+ */
+typedef enum IRQn
+{
+ /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
+
+ /****** M480 Specific Interrupt Numbers ********************************************************/
+
+ BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
+ IRC_IRQn = 1, /*!< Internal RC Interrupt */
+ PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
+ RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
+ CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
+ RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
+ TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
+ WDT_IRQn = 8, /*!< Watchdog timer Interrupt */
+ WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */
+ EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
+ EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
+ EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
+ EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
+ EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
+ EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
+ GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
+ GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
+ GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
+ GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
+ GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
+ GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
+ QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */
+ SPI0_IRQn = 23, /*!< SPI0 Interrupt */
+ BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
+ EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */
+ EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */
+ EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */
+ BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
+ EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */
+ EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */
+ EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */
+ TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
+ TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
+ TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
+ TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
+ UART0_IRQn = 36, /*!< UART 0 Interrupt */
+ UART1_IRQn = 37, /*!< UART 1 Interrupt */
+ I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
+ I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
+ PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
+ DAC_IRQn = 41, /*!< DAC Interrupt */
+ EADC00_IRQn = 42, /*!< EADC00 Interrupt */
+ EADC01_IRQn = 43, /*!< EADC01 Interrupt */
+ ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
+ EADC02_IRQn = 46, /*!< EADC02 Interrupt */
+ EADC03_IRQn = 47, /*!< EADC03 Interrupt */
+ UART2_IRQn = 48, /*!< UART2 Interrupt */
+ UART3_IRQn = 49, /*!< UART3 Interrupt */
+ QSPI1_IRQn = 50, /*!< QSPI1 Interrupt */
+ SPI1_IRQn = 51, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 52, /*!< SPI2 Interrupt */
+ USBD_IRQn = 53, /*!< USB device Interrupt */
+ USBH_IRQn = 54, /*!< USB host Interrupt */
+ USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
+ CAN0_IRQn = 56, /*!< CAN0 Interrupt */
+ CAN1_IRQn = 57, /*!< CAN1 Interrupt */
+ SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
+ SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */
+ SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */
+ SPI3_IRQn = 62, /*!< SPI3 Interrupt */
+ EMAC_TX_IRQn = 66, /*!< Ethernet MAC TX Interrupt */
+ EMAC_RX_IRQn = 67, /*!< Ethernet MAC RX Interrupt */
+ SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */
+ USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */
+ I2S0_IRQn = 68, /*!< I2S0 Interrupt */
+ OPA_IRQn = 70, /*!< OPA Interrupt */
+ CRPT_IRQn = 71, /*!< CRPT Interrupt */
+ GPG_IRQn = 72, /*!< GPIO Port G Interrupt */
+ EINT6_IRQn = 73, /*!< External Input 6 Interrupt */
+ UART4_IRQn = 74, /*!< UART4 Interrupt */
+ UART5_IRQn = 75, /*!< UART5 Interrupt */
+ USCI0_IRQn = 76, /*!< USCI0 Interrupt */
+ USCI1_IRQn = 77, /*!< USCI1 Interrupt */
+ BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */
+ BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */
+ SPIM_IRQn = 80, /*!< SPIM Interrupt */
+ CCAP_IRQn = 81, /*!< CCAP Interrupt */
+ I2C2_IRQn = 82, /*!< I2C2 Interrupt */
+ QEI0_IRQn = 84, /*!< QEI0 Interrupt */
+ QEI1_IRQn = 85, /*!< QEI1 Interrupt */
+ ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */
+ ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */
+ GPH_IRQn = 88, /*!< GPIO Port H Interrupt */
+ EINT7_IRQn = 89, /*!< External Input 7 Interrupt */
+ SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */
+ HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */
+ USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */
+ TRNG_IRQn = 101, /*!< TRNG Interrupt */
+ UART6_IRQn = 102, /*!< UART6 Interrupt */
+ UART7_IRQn = 103, /*!< UART7 Interrupt */
+ EADC10_IRQn = 104, /*!< EADC10 Interrupt */
+ EADC11_IRQn = 105, /*!< EADC11 Interrupt */
+ EADC12_IRQn = 106, /*!< EADC12 Interrupt */
+ EADC13_IRQn = 107, /*!< EADC13 Interrupt */
+ CAN2_IRQn = 108, /*!< CAN2 Interrupt */
+}
+IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV 0x0201UL /*!< Core Revision r2p1 */
+#define __NVIC_PRIO_BITS 4UL /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0UL /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 1UL /*!< MPU present or not */
+#ifdef __FPU_PRESENT
+#undef __FPU_PRESENT
+#define __FPU_PRESENT 1UL /*!< FPU present or not */
+#else
+#define __FPU_PRESENT 1UL /*!< FPU present or not */
+#endif
+
+/*@}*/ /* end of group CMSIS_Device */
+
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_M480.h" /* System include file */
+#include
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/******************************************************************************/
+/* Register definitions */
+/******************************************************************************/
+
+#include "sys_reg.h"
+#include "clk_reg.h"
+#include "fmc_reg.h"
+#include "gpio_reg.h"
+#include "pdma_reg.h"
+#include "timer_reg.h"
+#include "wdt_reg.h"
+#include "wwdt_reg.h"
+#include "rtc_reg.h"
+#include "epwm_reg.h"
+#include "bpwm_reg.h"
+#include "qei_reg.h"
+#include "ecap_reg.h"
+#include "uart_reg.h"
+#include "emac_reg.h"
+#include "sc_reg.h"
+#include "i2s_reg.h"
+#include "spi_reg.h"
+#include "qspi_reg.h"
+#include "spim_reg.h"
+#include "i2c_reg.h"
+#include "uuart_reg.h"
+#include "uspi_reg.h"
+#include "ui2c_reg.h"
+#include "can_reg.h"
+#include "sdh_reg.h"
+#include "ebi_reg.h"
+#include "usbd_reg.h"
+#include "hsusbd_reg.h"
+#include "usbh_reg.h"
+#include "hsusbh_reg.h"
+#include "otg_reg.h"
+#include "hsotg_reg.h"
+#include "crc_reg.h"
+#include "crypto_reg.h"
+#include "trng_reg.h"
+#include "eadc_reg.h"
+#include "dac_reg.h"
+#include "acmp_reg.h"
+#include "opa_reg.h"
+#include "ccap_reg.h"
+
+
+/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base
+ Memory Mapped Structure for Peripherals
+ @{
+ */
+/* Peripheral and SRAM base address */
+#define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */
+#define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */
+#define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000) /*!< APB Base Address */
+
+/*!< AHB peripherals */
+#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL)
+#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL)
+#define NMI_BASE (AHBPERIPH_BASE + 0x00300UL)
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)
+#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)
+#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)
+#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)
+#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL)
+#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
+#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
+#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)
+#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL)
+#define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL)
+#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL)
+#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)
+#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)
+#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)
+#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
+#define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL)
+#define CCAP_BASE (AHBPERIPH_BASE + 0x30000UL)
+#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
+#define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL)
+
+/*!< APB2 peripherals */
+#define WDT_BASE (APBPERIPH_BASE + 0x00000UL)
+#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
+#define OPA_BASE (APBPERIPH_BASE + 0x06000UL)
+#define I2S_BASE (APBPERIPH_BASE + 0x08000UL)
+#define EADC1_BASE (APBPERIPH_BASE + 0x0B000UL)
+#define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL)
+#define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL)
+#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)
+#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)
+#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL)
+#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL)
+#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
+#define UART2_BASE (APBPERIPH_BASE + 0x32000UL)
+#define UART4_BASE (APBPERIPH_BASE + 0x34000UL)
+#define UART6_BASE (APBPERIPH_BASE + 0x36000UL)
+#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL)
+#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL)
+#define CAN2_BASE (APBPERIPH_BASE + 0x62000UL)
+#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL)
+#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)
+#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
+
+
+/*!< APB1 peripherals */
+#define RTC_BASE (APBPERIPH_BASE + 0x01000UL)
+#define EADC_BASE (APBPERIPH_BASE + 0x03000UL)
+#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)
+#define USBD_BASE (APBPERIPH_BASE + 0x80000UL)
+#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL)
+#define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL)
+#define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL)
+#define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL)
+#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)
+#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)
+#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL)
+#define QSPI1_BASE (APBPERIPH_BASE + 0x29000UL)
+#define UART1_BASE (APBPERIPH_BASE + 0x31000UL)
+#define UART3_BASE (APBPERIPH_BASE + 0x33000UL)
+#define UART5_BASE (APBPERIPH_BASE + 0x35000UL)
+#define UART7_BASE (APBPERIPH_BASE + 0x37000UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL)
+#define CAN1_BASE (APBPERIPH_BASE + 0x61000UL)
+#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL)
+#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)
+#define TRNG_BASE (APBPERIPH_BASE + 0x79000UL)
+#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL)
+#define CRPT_BASE (0x50080000UL)
+#define SPIM_BASE (0x40007000UL)
+
+#define SC0_BASE (APBPERIPH_BASE + 0x50000UL)
+#define SC1_BASE (APBPERIPH_BASE + 0x51000UL)
+#define SC2_BASE (APBPERIPH_BASE + 0x52000UL)
+#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL)
+#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL)
+#define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL)
+#define OPA0_BASE (APBPERIPH_BASE + 0x06000UL)
+
+/*@}*/ /* end of group PERIPHERAL_MEM_MAP */
+
+
+/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer
+ The Declaration of Peripherals
+ @{
+ */
+
+#define SYS ((SYS_T *) SYS_BASE)
+#define CLK ((CLK_T *) CLK_BASE)
+#define NMI ((NMI_T *) NMI_BASE)
+#define PA ((GPIO_T *) GPIOA_BASE)
+#define PB ((GPIO_T *) GPIOB_BASE)
+#define PC ((GPIO_T *) GPIOC_BASE)
+#define PD ((GPIO_T *) GPIOD_BASE)
+#define PE ((GPIO_T *) GPIOE_BASE)
+#define PF ((GPIO_T *) GPIOF_BASE)
+#define PG ((GPIO_T *) GPIOG_BASE)
+#define PH ((GPIO_T *) GPIOH_BASE)
+#define GPA ((GPIO_T *) GPIOA_BASE)
+#define GPB ((GPIO_T *) GPIOB_BASE)
+#define GPC ((GPIO_T *) GPIOC_BASE)
+#define GPD ((GPIO_T *) GPIOD_BASE)
+#define GPE ((GPIO_T *) GPIOE_BASE)
+#define GPF ((GPIO_T *) GPIOF_BASE)
+#define GPG ((GPIO_T *) GPIOG_BASE)
+#define GPH ((GPIO_T *) GPIOH_BASE)
+#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
+#define PDMA ((PDMA_T *) PDMA_BASE)
+#define USBH ((USBH_T *) USBH_BASE)
+#define HSUSBH ((HSUSBH_T *) HSUSBH_BASE)
+#define EMAC ((EMAC_T *) EMAC_BASE)
+#define FMC ((FMC_T *) FMC_BASE)
+#define SDH0 ((SDH_T *) SDH0_BASE)
+#define SDH1 ((SDH_T *) SDH1_BASE)
+#define EBI ((EBI_T *) EBI_BASE)
+#define CRC ((CRC_T *) CRC_BASE)
+#define TAMPER ((TAMPER_T *) TAMPER_BASE)
+
+#define WDT ((WDT_T *) WDT_BASE)
+#define WWDT ((WWDT_T *) WWDT_BASE)
+#define RTC ((RTC_T *) RTC_BASE)
+#define EADC ((EADC_T *) EADC_BASE)
+#define EADC0 ((EADC_T *) EADC_BASE)
+#define EADC1 ((EADC_T *) EADC1_BASE)
+#define ACMP01 ((ACMP_T *) ACMP01_BASE)
+
+#define I2S0 ((I2S_T *) I2S_BASE)
+#define USBD ((USBD_T *) USBD_BASE)
+#define OTG ((OTG_T *) OTG_BASE)
+#define HSUSBD ((HSUSBD_T *)HSUSBD_BASE)
+#define HSOTG ((HSOTG_T *) HSOTG_BASE)
+#define TIMER0 ((TIMER_T *) TIMER0_BASE)
+#define TIMER1 ((TIMER_T *) TIMER1_BASE)
+#define TIMER2 ((TIMER_T *) TIMER2_BASE)
+#define TIMER3 ((TIMER_T *) TIMER3_BASE)
+#define EPWM0 ((EPWM_T *) EPWM0_BASE)
+#define EPWM1 ((EPWM_T *) EPWM1_BASE)
+#define BPWM0 ((BPWM_T *) BPWM0_BASE)
+#define BPWM1 ((BPWM_T *) BPWM1_BASE)
+#define ECAP0 ((ECAP_T *) ECAP0_BASE)
+#define ECAP1 ((ECAP_T *) ECAP1_BASE)
+#define QEI0 ((QEI_T *) QEI0_BASE)
+#define QEI1 ((QEI_T *) QEI1_BASE)
+#define QSPI0 ((QSPI_T *) QSPI0_BASE)
+#define QSPI1 ((QSPI_T *) QSPI1_BASE)
+#define SPI0 ((SPI_T *) SPI0_BASE)
+#define SPI1 ((SPI_T *) SPI1_BASE)
+#define SPI2 ((SPI_T *) SPI2_BASE)
+#define SPI3 ((SPI_T *) SPI3_BASE)
+#define UART0 ((UART_T *) UART0_BASE)
+#define UART1 ((UART_T *) UART1_BASE)
+#define UART2 ((UART_T *) UART2_BASE)
+#define UART3 ((UART_T *) UART3_BASE)
+#define UART4 ((UART_T *) UART4_BASE)
+#define UART5 ((UART_T *) UART5_BASE)
+#define UART6 ((UART_T *) UART6_BASE)
+#define UART7 ((UART_T *) UART7_BASE)
+#define I2C0 ((I2C_T *) I2C0_BASE)
+#define I2C1 ((I2C_T *) I2C1_BASE)
+#define I2C2 ((I2C_T *) I2C2_BASE)
+#define SC0 ((SC_T *) SC0_BASE)
+#define SC1 ((SC_T *) SC1_BASE)
+#define SC2 ((SC_T *) SC2_BASE)
+#define CAN0 ((CAN_T *) CAN0_BASE)
+#define CAN1 ((CAN_T *) CAN1_BASE)
+#define CAN2 ((CAN_T *) CAN2_BASE)
+#define CRPT ((CRPT_T *) CRPT_BASE)
+#define TRNG ((TRNG_T *) TRNG_BASE)
+#define SPIM ((volatile SPIM_T *) SPIM_BASE)
+#define DAC0 ((DAC_T *) DAC0_BASE)
+#define DAC1 ((DAC_T *) DAC1_BASE)
+#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */
+#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Configuration Struct */
+#define OPA ((OPA_T *) OPA_BASE)
+#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */
+#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */
+#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */
+#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Configuration Struct */
+#define CCAP ((CCAP_T *) CCAP_BASE)
+
+/*@}*/ /* end of group ERIPHERAL_DECLARATION */
+
+/** @addtogroup IO_ROUTINE I/O Routines
+ The Declaration of I/O Routines
+ @{
+ */
+
+typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type
+typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type
+typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type
+
+/**
+ * @brief Get a 8-bit unsigned value from specified address
+ * @param[in] addr Address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified address
+ */
+#define M8(addr) (*((vu8 *) (addr)))
+
+/**
+ * @brief Get a 16-bit unsigned value from specified address
+ * @param[in] addr Address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified address
+ * @note The input address must be 16-bit aligned
+ */
+#define M16(addr) (*((vu16 *) (addr)))
+
+/**
+ * @brief Get a 32-bit unsigned value from specified address
+ * @param[in] addr Address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified address
+ * @note The input address must be 32-bit aligned
+ */
+#define M32(addr) (*((vu32 *) (addr)))
+
+/**
+ * @brief Set a 32-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 32-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 32-bit aligned
+ */
+#define outpw(port,value) *((volatile unsigned int *)(port)) = (value)
+
+/**
+ * @brief Get a 32-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified I/O port
+ * @note The input port must be 32-bit aligned
+ */
+#define inpw(port) (*((volatile unsigned int *)(port)))
+
+/**
+ * @brief Set a 16-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 16-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 16-bit aligned
+ */
+#define outps(port,value) *((volatile unsigned short *)(port)) = (value)
+
+/**
+ * @brief Get a 16-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified I/O port
+ * @note The input port must be 16-bit aligned
+ */
+#define inps(port) (*((volatile unsigned short *)(port)))
+
+/**
+ * @brief Set a 8-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 8-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ */
+#define outpb(port,value) *((volatile unsigned char *)(port)) = (value)
+
+/**
+ * @brief Get a 8-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified I/O port
+ */
+#define inpb(port) (*((volatile unsigned char *)(port)))
+
+/**
+ * @brief Set a 32-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 32-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 32-bit aligned
+ */
+#define outp32(port,value) *((volatile unsigned int *)(port)) = (value)
+
+/**
+ * @brief Get a 32-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified I/O port
+ * @note The input port must be 32-bit aligned
+ */
+#define inp32(port) (*((volatile unsigned int *)(port)))
+
+/**
+ * @brief Set a 16-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 16-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 16-bit aligned
+ */
+#define outp16(port,value) *((volatile unsigned short *)(port)) = (value)
+
+/**
+ * @brief Get a 16-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified I/O port
+ * @note The input port must be 16-bit aligned
+ */
+#define inp16(port) (*((volatile unsigned short *)(port)))
+
+/**
+ * @brief Set a 8-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 8-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ */
+#define outp8(port,value) *((volatile unsigned char *)(port)) = (value)
+
+/**
+ * @brief Get a 8-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified I/O port
+ */
+#define inp8(port) (*((volatile unsigned char *)(port)))
+
+
+/*@}*/ /* end of group IO_ROUTINE */
+
+/******************************************************************************/
+/* Legacy Constants */
+/******************************************************************************/
+/** @addtogroup Legacy_Constants Legacy Constants
+ Legacy Constants
+ @{
+*/
+
+#ifndef NULL
+#define NULL (0) ///< NULL pointer
+#endif
+
+#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value
+#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value
+
+#define ENABLE (1UL) ///< Enable, define to use in API parameters
+#define DISABLE (0UL) ///< Disable, define to use in API parameters
+
+/* Define one bit mask */
+#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer
+#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer
+#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer
+#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer
+#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer
+#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer
+#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer
+#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer
+#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer
+#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer
+#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer
+#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer
+#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer
+#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer
+#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer
+#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer
+#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer
+#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer
+#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer
+#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer
+#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer
+#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer
+#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer
+#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer
+#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer
+#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer
+#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer
+#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer
+#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer
+#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer
+#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer
+#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer
+
+/* Byte Mask Definitions */
+#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer
+#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer
+#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer
+#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer
+
+#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
+#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
+#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+/*@}*/ /* end of group Legacy_Constants */
+
+
+/******************************************************************************/
+/* Peripheral header files */
+/******************************************************************************/
+#include "nu_sys.h"
+#include "nu_clk.h"
+
+#include "nu_acmp.h"
+#include "nu_dac.h"
+#include "nu_emac.h"
+#include "nu_uart.h"
+#include "nu_usci_spi.h"
+#include "nu_gpio.h"
+#include "nu_ccap.h"
+#include "nu_ecap.h"
+#include "nu_qei.h"
+#include "nu_timer.h"
+#include "nu_timer_pwm.h"
+#include "nu_pdma.h"
+#include "nu_crypto.h"
+#include "nu_trng.h"
+#include "nu_fmc.h"
+#include "nu_spim.h"
+#include "nu_i2c.h"
+#include "nu_i2s.h"
+#include "nu_epwm.h"
+#include "nu_eadc.h"
+#include "nu_bpwm.h"
+#include "nu_wdt.h"
+#include "nu_wwdt.h"
+#include "nu_opa.h"
+#include "nu_crc.h"
+#include "nu_ebi.h"
+#include "nu_usci_i2c.h"
+#include "nu_scuart.h"
+#include "nu_sc.h"
+#include "nu_spi.h"
+#include "nu_qspi.h"
+#include "nu_can.h"
+#include "nu_rtc.h"
+#include "nu_usci_uart.h"
+#include "nu_sdh.h"
+#include "nu_usbd.h"
+#include "nu_hsusbd.h"
+#include "nu_otg.h"
+#include "nu_hsotg.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __M480_H__ */
+
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/NuMicro.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/NuMicro.h
new file mode 100644
index 00000000000..c627d8af7c4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/NuMicro.h
@@ -0,0 +1,17 @@
+/**************************************************************************//**
+ * @file NuMicro.h
+ * @version V1.00
+ * @brief NuMicro peripheral access layer header file.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NUMICRO_H__
+#define __NUMICRO_H__
+
+#include "nutool_clkcfg.h"
+#include "M480.h"
+
+#endif /* __NUMICRO_H__ */
+
+
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/acmp_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/acmp_reg.h
new file mode 100644
index 00000000000..663f86292a7
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/acmp_reg.h
@@ -0,0 +1,240 @@
+/**************************************************************************//**
+ * @file acmp_reg.h
+ * @version V1.00
+ * @brief ACMP register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __ACMP_REG_H__
+#define __ACMP_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup ACMP Analog Comparator Controller(ACMP)
+ Memory Mapped Structure for ACMP Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var ACMP_T::CTL
+ * Offset: 0x00~0x04 Analog Comparator 0/1 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ACMPEN |Comparator Enable Bit
+ * | | |0 = Comparator x Disabled.
+ * | | |1 = Comparator x Enabled.
+ * |[1] |ACMPIE |Comparator Interrupt Enable Bit
+ * | | |0 = Comparator x interrupt Disabled.
+ * | | |1 = Comparator x interrupt Enabled
+ * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
+ * |[3] |ACMPOINV |Comparator Output Inverse
+ * | | |0 = Comparator x output inverse Disabled.
+ * | | |1 = Comparator x output inverse Enabled.
+ * |[5:4] |NEGSEL |Comparator Negative Input Selection
+ * | | |00 = ACMPx_N pin.
+ * | | |01 = Internal comparator reference voltage (CRV).
+ * | | |10 = Band-gap voltage.
+ * | | |11 = DAC output.
+ * |[7:6] |POSSEL |Comparator Positive Input Selection
+ * | | |00 = Input from ACMPx_P0.
+ * | | |01 = Input from ACMPx_P1.
+ * | | |10 = Input from ACMPx_P2.
+ * | | |11 = Input from ACMPx_P3.
+ * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
+ * | | |ACMPIFx will be set to 1 when comparator output edge condition is detected.
+ * | | |00 = Rising edge or falling edge.
+ * | | |01 = Rising edge.
+ * | | |10 = Falling edge.
+ * | | |11 = Reserved.
+ * |[12] |OUTSEL |Comparator Output Select
+ * | | |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output.
+ * | | |1 = Comparator x output to ACMPx_O pin is from filter output.
+ * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
+ * | | |000 = Filter function is Disabled.
+ * | | |001 = ACMPx output is sampled 1 consecutive PCLK.
+ * | | |010 = ACMPx output is sampled 2 consecutive PCLKs.
+ * | | |011 = ACMPx output is sampled 4 consecutive PCLKs.
+ * | | |100 = ACMPx output is sampled 8 consecutive PCLKs.
+ * | | |101 = ACMPx output is sampled 16 consecutive PCLKs.
+ * | | |110 = ACMPx output is sampled 32 consecutive PCLKs.
+ * | | |111 = ACMPx output is sampled 64 consecutive PCLKs.
+ * |[16] |WKEN |Power-down Wake-up Enable Bit
+ * | | |0 = Wake-up function Disabled.
+ * | | |1 = Wake-up function Enabled.
+ * |[17] |WLATEN |Window Latch Mode Enable Bit
+ * | | |0 = Window Latch Mode Disabled.
+ * | | |1 = Window Latch Mode Enabled.
+ * |[18] |WCMPSEL |Window Compare Mode Selection
+ * | | |0 = Window Compare Mode Disabled.
+ * | | |1 = Window Compare Mode is Selected.
+ * |[25:24] |HYSSEL |Hysteresis Mode Selection
+ * | | |00 = Hysteresis is 0mV.
+ * | | |01 = Hysteresis is 10mV.
+ * | | |10 = Hysteresis is 20mV.
+ * | | |11 = Hysteresis is 30mV.
+ * |[29:28] |MODESEL |Propagation Delay Mode Selection
+ * | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
+ * | | |01 = Max propagation delay is 2uS, operation current is 3uA.
+ * | | |10 = Max propagation delay is 600nS, operation current is 10uA.
+ * | | |11 = Max propagation delay is 200nS, operation current is 75uA.
+ * @var ACMP_T::STATUS
+ * Offset: 0x08 Analog Comparator Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
+ * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8])
+ * | | |is detected on comparator 0 output.
+ * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
+ * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8])
+ * | | |is detected on comparator 1 output.
+ * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |ACMPO0 |Comparator 0 Output
+ * | | |Synchronized to the PCLK to allow reading by software
+ * | | |Cleared when the comparator 0 is disabled, i.e.
+ * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+ * |[5] |ACMPO1 |Comparator 1 Output
+ * | | |Synchronized to the PCLK to allow reading by software.
+ * | | |Cleared when the comparator 1 is disabled, i.e.
+ * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+ * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag
+ * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
+ * | | |0 = No power-down wake-up occurred.
+ * | | |1 = Power-down wake-up occurred.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag
+ * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
+ * | | |0 = No power-down wake-up occurred.
+ * | | |1 = Power-down wake-up occurred.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[12] |ACMPS0 |Comparator 0 Status
+ * | | |Synchronized to the PCLK to allow reading by software
+ * | | |Cleared when the comparator 0 is disabled, i.e.
+ * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+ * |[13] |ACMPS1 |Comparator 1 Status
+ * | | |Synchronized to the PCLK to allow reading by software
+ * | | |Cleared when the comparator 1 is disabled, i.e.
+ * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+ * |[16] |ACMPWO |Comparator Window Output
+ * | | |This bit shows the output status of window compare mode
+ * | | |0 = The positive input voltage is outside the window.
+ * | | |1 = The positive input voltage is in the window.
+ * @var ACMP_T::VREF
+ * Offset: 0x0C Analog Comparator Reference Voltage Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |CRVCTL |Comparator Reference Voltage Setting
+ * | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
+ * |[6] |CRVSSEL |CRV Source Voltage Selection
+ * | | |0 = VDDA is selected as CRV source voltage.
+ * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
+ */
+ __IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */
+ __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */
+ __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */
+
+} ACMP_T;
+
+/**
+ @addtogroup ACMP_CONST ACMP Bit Field Definition
+ Constant Definitions for ACMP Controller
+@{ */
+
+#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
+#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
+
+#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
+#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
+
+#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
+#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
+
+#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
+#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
+
+#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
+#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
+
+#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
+#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
+
+#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
+#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
+
+#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
+#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
+
+#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
+#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
+
+#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */
+#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */
+
+#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */
+#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */
+
+#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */
+#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */
+
+#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */
+#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */
+
+#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
+#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
+
+#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
+#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
+
+#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
+#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
+
+#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
+#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
+
+#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
+#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
+
+#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
+#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
+
+#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */
+#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */
+
+#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */
+#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */
+
+#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */
+#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */
+
+#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
+#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
+
+#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
+#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
+
+/**@}*/ /* ACMP_CONST */
+/**@}*/ /* end of ACMP register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __ACMP_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/bpwm_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/bpwm_reg.h
new file mode 100644
index 00000000000..3a4fc35fdd3
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/bpwm_reg.h
@@ -0,0 +1,1835 @@
+/**************************************************************************//**
+ * @file bpwm_reg.h
+ * @version V1.00
+ * @brief BPWM register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __BPWM_REG_H__
+#define __BPWM_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM)
+ Memory Mapped Structure for BPWM Controller
+@{ */
+
+typedef struct
+{
+ /**
+ * @var BCAPDAT_T::RCAPDAT
+ * Offset: 0x20C BPWM Rising Capture Data Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only)
+ * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
+ * @var BCAPDAT_T::FCAPDAT
+ * Offset: 0x210 BPWM Falling Capture Data Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only)
+ * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
+ */
+ __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */
+ __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */
+} BCAPDAT_T;
+
+typedef struct
+{
+
+
+ /**
+ * @var BPWM_T::CTL0
+ * Offset: 0x00 BPWM Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CTRLD0 |Center Re-load
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[1] |CTRLD1 |Center Re-load
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[2] |CTRLD2 |Center Re-load
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[3] |CTRLD3 |Center Re-load
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[4] |CTRLD4 |Center Re-load
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[5] |CTRLD5 |Center Re-load
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S)
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+ * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S)
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+ * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S)
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+ * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S)
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+ * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S)
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+ * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S)
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+ * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
+ * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
+ * | | |0 = ICE debug mode counter halt Disabled.
+ * | | |1 = ICE debug mode counter halt Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
+ * | | |0 = ICE debug mode acknowledgement effects BPWM output.
+ * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged.
+ * | | |1 = ICE debug mode acknowledgement Disabled.
+ * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * @var BPWM_T::CTL1
+ * Offset: 0x04 BPWM Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0
+ * | | |Each bit n controls corresponding BPWM channel n.
+ * | | |00 = Up counter type (supports in capture mode).
+ * | | |01 = Down count type (supports in capture mode).
+ * | | |10 = Up-down counter type.
+ * | | |11 = Reserved.
+ * @var BPWM_T::CLKSRC
+ * Offset: 0x10 BPWM Clock Source Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select
+ * | | |000 = BPWMx_CLK, x denotes 0 or 1.
+ * | | |001 = TIMER0 overflow.
+ * | | |010 = TIMER1 overflow.
+ * | | |011 = TIMER2 overflow.
+ * | | |100 = TIMER3 overflow.
+ * | | |Others = Reserved.
+ * @var BPWM_T::CLKPSC
+ * Offset: 0x14 BPWM Clock Prescale Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |CLKPSC |BPWM Counter Clock Prescale
+ * | | |The clock of BPWM counter is decided by clock prescaler
+ * | | |Each BPWM pair share one BPWM counter clock prescaler
+ * | | |The clock of BPWM counter is divided by (CLKPSC+ 1)
+ * @var BPWM_T::CNTEN
+ * Offset: 0x20 BPWM Counter Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit
+ * | | |0 = BPWM Counter and clock prescaler stop running.
+ * | | |1 = BPWM Counter and clock prescaler start running.
+ * @var BPWM_T::CNTCLR
+ * Offset: 0x24 BPWM Clear Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0
+ * | | |It is automatically cleared by hardware.
+ * | | |0 = No effect.
+ * | | |1 = Clear 16-bit BPWM counter to 0000H.
+ * @var BPWM_T::PERIOD
+ * Offset: 0x30 BPWM Period Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PERIOD |BPWM Period Register
+ * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
+ * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
+ * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period.
+ * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+ * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period.
+ * @var BPWM_T::CMPDAT[6]
+ * Offset: 0x50 BPWM Comparator Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMPDAT |BPWM Comparator Register
+ * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC.
+ * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
+ * @var BPWM_T::CNT
+ * Offset: 0x90 BPWM Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CNT |BPWM Data Register (Read Only)
+ * | | |User can monitor CNTR to know the current value in 16-bit period counter.
+ * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only)
+ * | | |0 = Counter is Down count.
+ * | | |1 = Counter is UP count.
+ * @var BPWM_T::WGCTL0
+ * Offset: 0xB0 BPWM Generation Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |ZPCTL0 |BPWM Zero Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM zero point output Low.
+ * | | |10 = BPWM zero point output High.
+ * | | |11 = BPWM zero point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to zero.
+ * |[3:2] |ZPCTL1 |BPWM Zero Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM zero point output Low.
+ * | | |10 = BPWM zero point output High.
+ * | | |11 = BPWM zero point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to zero.
+ * |[5:4] |ZPCTL2 |BPWM Zero Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM zero point output Low.
+ * | | |10 = BPWM zero point output High.
+ * | | |11 = BPWM zero point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to zero.
+ * |[7:6] |ZPCTL3 |BPWM Zero Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM zero point output Low.
+ * | | |10 = BPWM zero point output High.
+ * | | |11 = BPWM zero point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to zero.
+ * |[9:8] |ZPCTL4 |BPWM Zero Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM zero point output Low.
+ * | | |10 = BPWM zero point output High.
+ * | | |11 = BPWM zero point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to zero.
+ * |[11:10] |ZPCTL5 |BPWM Zero Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM zero point output Low.
+ * | | |10 = BPWM zero point output High.
+ * | | |11 = BPWM zero point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to zero.
+ * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM period (center) point output Low.
+ * | | |10 = BPWM period (center) point output High.
+ * | | |11 = BPWM period (center) point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+ * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM period (center) point output Low.
+ * | | |10 = BPWM period (center) point output High.
+ * | | |11 = BPWM period (center) point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+ * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM period (center) point output Low.
+ * | | |10 = BPWM period (center) point output High.
+ * | | |11 = BPWM period (center) point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+ * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM period (center) point output Low.
+ * | | |10 = BPWM period (center) point output High.
+ * | | |11 = BPWM period (center) point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+ * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM period (center) point output Low.
+ * | | |10 = BPWM period (center) point output High.
+ * | | |11 = BPWM period (center) point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+ * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM period (center) point output Low.
+ * | | |10 = BPWM period (center) point output High.
+ * | | |11 = BPWM period (center) point output Toggle.
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+ * @var BPWM_T::WGCTL1
+ * Offset: 0xB4 BPWM Generation Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare up point output Low.
+ * | | |10 = BPWM compare up point output High.
+ * | | |11 = BPWM compare up point output Toggle.
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
+ * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare up point output Low.
+ * | | |10 = BPWM compare up point output High.
+ * | | |11 = BPWM compare up point output Toggle.
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
+ * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare up point output Low.
+ * | | |10 = BPWM compare up point output High.
+ * | | |11 = BPWM compare up point output Toggle.
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
+ * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare up point output Low.
+ * | | |10 = BPWM compare up point output High.
+ * | | |11 = BPWM compare up point output Toggle.
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
+ * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare up point output Low.
+ * | | |10 = BPWM compare up point output High.
+ * | | |11 = BPWM compare up point output Toggle.
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
+ * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare up point output Low.
+ * | | |10 = BPWM compare up point output High.
+ * | | |11 = BPWM compare up point output Toggle.
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
+ * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare down point output Low.
+ * | | |10 = BPWM compare down point output High.
+ * | | |11 = BPWM compare down point output Toggle.
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
+ * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare down point output Low.
+ * | | |10 = BPWM compare down point output High.
+ * | | |11 = BPWM compare down point output Toggle.
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
+ * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare down point output Low.
+ * | | |10 = BPWM compare down point output High.
+ * | | |11 = BPWM compare down point output Toggle.
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
+ * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare down point output Low.
+ * | | |10 = BPWM compare down point output High.
+ * | | |11 = BPWM compare down point output Toggle.
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
+ * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare down point output Low.
+ * | | |10 = BPWM compare down point output High.
+ * | | |11 = BPWM compare down point output Toggle.
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
+ * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = BPWM compare down point output Low.
+ * | | |10 = BPWM compare down point output High.
+ * | | |11 = BPWM compare down point output Toggle.
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
+ * @var BPWM_T::MSKEN
+ * Offset: 0xB8 BPWM Mask Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MSKEN0 |BPWM Mask Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |The BPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+ * | | |0 = BPWM output signal is non-masked.
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.
+ * |[1] |MSKEN1 |BPWM Mask Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |The BPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+ * | | |0 = BPWM output signal is non-masked.
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.
+ * |[2] |MSKEN2 |BPWM Mask Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |The BPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+ * | | |0 = BPWM output signal is non-masked.
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.
+ * |[3] |MSKEN3 |BPWM Mask Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |The BPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+ * | | |0 = BPWM output signal is non-masked.
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.
+ * |[4] |MSKEN4 |BPWM Mask Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |The BPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+ * | | |0 = BPWM output signal is non-masked.
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.
+ * |[5] |MSKEN5 |BPWM Mask Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |The BPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+ * | | |0 = BPWM output signal is non-masked.
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.
+ * @var BPWM_T::MSK
+ * Offset: 0xBC BPWM Mask Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MSKDAT0 |BPWM Mask Data Bit
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Output logic low to BPWMn.
+ * | | |1 = Output logic high to BPWMn.
+ * |[1] |MSKDAT1 |BPWM Mask Data Bit
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Output logic low to BPWMn.
+ * | | |1 = Output logic high to BPWMn.
+ * |[2] |MSKDAT2 |BPWM Mask Data Bit
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Output logic low to BPWMn.
+ * | | |1 = Output logic high to BPWMn.
+ * |[3] |MSKDAT3 |BPWM Mask Data Bit
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Output logic low to BPWMn.
+ * | | |1 = Output logic high to BPWMn.
+ * |[4] |MSKDAT4 |BPWM Mask Data Bit
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Output logic low to BPWMn.
+ * | | |1 = Output logic high to BPWMn.
+ * |[5] |MSKDAT5 |BPWM Mask Data Bit
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Output logic low to BPWMn.
+ * | | |1 = Output logic high to BPWMn.
+ * @var BPWM_T::POLCTL
+ * Offset: 0xD4 BPWM Pin Polar Inverse Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PINV0 |BPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of BPWM output
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM output polar inverse Disabled.
+ * | | |1 = BPWM output polar inverse Enabled.
+ * |[1] |PINV1 |BPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of BPWM output
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM output polar inverse Disabled.
+ * | | |1 = BPWM output polar inverse Enabled.
+ * |[2] |PINV2 |BPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of BPWM output
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM output polar inverse Disabled.
+ * | | |1 = BPWM output polar inverse Enabled.
+ * |[3] |PINV3 |BPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of BPWM output
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM output polar inverse Disabled.
+ * | | |1 = BPWM output polar inverse Enabled.
+ * |[4] |PINV4 |BPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of BPWM output
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM output polar inverse Disabled.
+ * | | |1 = BPWM output polar inverse Enabled.
+ * |[5] |PINV5 |BPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of BPWM output
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM output polar inverse Disabled.
+ * | | |1 = BPWM output polar inverse Enabled.
+ * @var BPWM_T::POEN
+ * Offset: 0xD8 BPWM Output Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |POEN0 |BPWM Pin Output Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM pin at tri-state.
+ * | | |1 = BPWM pin in output mode.
+ * |[1] |POEN1 |BPWM Pin Output Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM pin at tri-state.
+ * | | |1 = BPWM pin in output mode.
+ * |[2] |POEN2 |BPWM Pin Output Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM pin at tri-state.
+ * | | |1 = BPWM pin in output mode.
+ * |[3] |POEN3 |BPWM Pin Output Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM pin at tri-state.
+ * | | |1 = BPWM pin in output mode.
+ * |[4] |POEN4 |BPWM Pin Output Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM pin at tri-state.
+ * | | |1 = BPWM pin in output mode.
+ * |[5] |POEN5 |BPWM Pin Output Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM pin at tri-state.
+ * | | |1 = BPWM pin in output mode.
+ * @var BPWM_T::INTEN
+ * Offset: 0xE0 BPWM Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit
+ * | | |0 = Zero point interrupt Disabled.
+ * | | |1 = Zero point interrupt Enabled.
+ * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit
+ * | | |0 = Period point interrupt Disabled.
+ * | | |1 = Period point interrupt Enabled.
+ * | | |Note: When up-down counter type period point means center point.
+ * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * @var BPWM_T::INTSTS
+ * Offset: 0xE8 BPWM Interrupt Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0
+ * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero.
+ * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0
+ * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero.
+ * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * @var BPWM_T::EADCTS0
+ * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select
+ * | | |0000 = BPWM_CH0 zero point.
+ * | | |0001 = BPWM_CH0 period point.
+ * | | |0010 = BPWM_CH0 zero or period point.
+ * | | |0011 = BPWM_CH0 up-count CMPDAT point.
+ * | | |0100 = BPWM_CH0 down-count CMPDAT point.
+ * | | |0101 = Reserved.
+ * | | |0110 = Reserved.
+ * | | |0111 = Reserved.
+ * | | |1000 = BPWM_CH1 up-count CMPDAT point.
+ * | | |1001 = BPWM_CH1 down-count CMPDAT point.
+ * | | |Others reserved
+ * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit
+ * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select
+ * | | |0000 = BPWM_CH0 zero point.
+ * | | |0001 = BPWM_CH0 period point.
+ * | | |0010 = BPWM_CH0 zero or period point.
+ * | | |0011 = BPWM_CH0 up-count CMPDAT point.
+ * | | |0100 = BPWM_CH0 down-count CMPDAT point.
+ * | | |0101 = Reserved.
+ * | | |0110 = Reserved.
+ * | | |0111 = Reserved.
+ * | | |1000 = BPWM_CH1 up-count CMPDAT point.
+ * | | |1001 = BPWM_CH1 down-count CMPDAT point.
+ * | | |Others reserved
+ * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit
+ * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select
+ * | | |0000 = BPWM_CH2 zero point.
+ * | | |0001 = BPWM_CH2 period point.
+ * | | |0010 = BPWM_CH2 zero or period point.
+ * | | |0011 = BPWM_CH2 up-count CMPDAT point.
+ * | | |0100 = BPWM_CH2 down-count CMPDAT point.
+ * | | |0101 = Reserved.
+ * | | |0110 = Reserved.
+ * | | |0111 = Reserved.
+ * | | |1000 = BPWM_CH3 up-count CMPDAT point.
+ * | | |1001 = BPWM_CH3 down-count CMPDAT point.
+ * | | |Others reserved
+ * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit
+ * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select
+ * | | |0000 = BPWM_CH2 zero point.
+ * | | |0001 = BPWM_CH2 period point.
+ * | | |0010 = BPWM_CH2 zero or period point.
+ * | | |0011 = BPWM_CH2 up-count CMPDAT point.
+ * | | |0100 = BPWM_CH2 down-count CMPDAT point.
+ * | | |0101 = Reserved.
+ * | | |0110 = Reserved.
+ * | | |0111 = Reserved.
+ * | | |1000 = BPWM_CH3 up-count CMPDAT point.
+ * | | |1001 = BPWM_CH3 down-count CMPDAT point.
+ * | | |Others reserved.
+ * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit
+ * @var BPWM_T::EADCTS1
+ * Offset: 0xFC BPWM Trigger EADC Source Select Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select
+ * | | |0000 = BPWM_CH4 zero point.
+ * | | |0001 = BPWM_CH4 period point.
+ * | | |0010 = BPWM_CH4 zero or period point.
+ * | | |0011 = BPWM_CH4 up-count CMPDAT point.
+ * | | |0100 = BPWM_CH4 down-count CMPDAT point.
+ * | | |0101 = Reserved.
+ * | | |0110 = Reserved.
+ * | | |0111 = Reserved.
+ * | | |1000 = BPWM_CH5 up-count CMPDAT point.
+ * | | |1001 = BPWM_CH5 down-count CMPDAT point.
+ * | | |Others reserved
+ * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit
+ * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select
+ * | | |0000 = BPWM_CH4 zero point.
+ * | | |0001 = BPWM_CH4 period point.
+ * | | |0010 = BPWM_CH4 zero or period point.
+ * | | |0011 = BPWM_CH4 up-count CMPDAT point.
+ * | | |0100 = BPWM_CH4 down-count CMPDAT point.
+ * | | |0101 = Reserved.
+ * | | |0110 = Reserved.
+ * | | |0111 = Reserved.
+ * | | |1000 = BPWM_CH5 up-count CMPDAT point.
+ * | | |1001 = BPWM_CH5 down-count CMPDAT point.
+ * | | |Others reserved
+ * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit
+ * @var BPWM_T::SSCTL
+ * Offset: 0x110 BPWM Synchronous Start Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit
+ * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
+ * | | |0 = BPWM synchronous start function Disabled.
+ * | | |1 = BPWM synchronous start function Enabled.
+ * |[9:8] |SSRC |BPWM Synchronous Start Source Select
+ * | | |00 = Synchronous start source come from PWM0.
+ * | | |01 = Synchronous start source come from PWM1.
+ * | | |10 = Synchronous start source come from BPWM0.
+ * | | |11 = Synchronous start source come from BPWM1.
+ * @var BPWM_T::SSTRG
+ * Offset: 0x114 BPWM Synchronous Start Trigger Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only)
+ * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.
+ * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
+ * @var BPWM_T::STATUS
+ * Offset: 0x120 BPWM Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+ * |[16] |EADCTRG0 |EADC Start of Conversion Status
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[17] |EADCTRG1 |EADC Start of Conversion Status
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[18] |EADCTRG2 |EADC Start of Conversion Status
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[19] |EADCTRG3 |EADC Start of Conversion Status
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[20] |EADCTRG4 |EADC Start of Conversion Status
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[21] |EADCTRG5 |EADC Start of Conversion Status
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * @var BPWM_T::CAPINEN
+ * Offset: 0x200 BPWM Capture Input Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAPINEN0 |Capture Input Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM Channel capture input path Disabled
+ * | | |The input of BPWM channel capture function is always regarded as 0.
+ * | | |1 = BPWM Channel capture input path Enabled
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
+ * |[1] |CAPINEN1 |Capture Input Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM Channel capture input path Disabled
+ * | | |The input of BPWM channel capture function is always regarded as 0.
+ * | | |1 = BPWM Channel capture input path Enabled
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
+ * |[2] |CAPINEN2 |Capture Input Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM Channel capture input path Disabled
+ * | | |The input of BPWM channel capture function is always regarded as 0.
+ * | | |1 = BPWM Channel capture input path Enabled
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
+ * |[3] |CAPINEN3 |Capture Input Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM Channel capture input path Disabled
+ * | | |The input of BPWM channel capture function is always regarded as 0.
+ * | | |1 = BPWM Channel capture input path Enabled
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
+ * |[4] |CAPINEN4 |Capture Input Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM Channel capture input path Disabled
+ * | | |The input of BPWM channel capture function is always regarded as 0.
+ * | | |1 = BPWM Channel capture input path Enabled
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
+ * |[5] |CAPINEN5 |Capture Input Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = BPWM Channel capture input path Disabled
+ * | | |The input of BPWM channel capture function is always regarded as 0.
+ * | | |1 = BPWM Channel capture input path Enabled
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
+ * @var BPWM_T::CAPCTL
+ * Offset: 0x204 BPWM Capture Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAPEN0 |Capture Function Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[1] |CAPEN1 |Capture Function Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[2] |CAPEN2 |Capture Function Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[3] |CAPEN3 |Capture Function Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[4] |CAPEN4 |Capture Function Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[5] |CAPEN5 |Capture Function Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[8] |CAPINV0 |Capture Inverter Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[9] |CAPINV1 |Capture Inverter Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[10] |CAPINV2 |Capture Inverter Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[11] |CAPINV3 |Capture Inverter Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[12] |CAPINV4 |Capture Inverter Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[13] |CAPINV5 |Capture Inverter Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * @var BPWM_T::CAPSTS
+ * Offset: 0x208 BPWM Capture Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+ * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+ * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+ * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+ * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+ * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+ * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+ * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+ * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+ * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+ * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+ * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+ * @var BPWM_T::CAPIEN
+ * Offset: 0x250 BPWM Capture Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture rising edge latch interrupt Disabled.
+ * | | |1 = Capture rising edge latch interrupt Enabled.
+ * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits
+ * | | |Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = Capture falling edge latch interrupt Disabled.
+ * | | |1 = Capture falling edge latch interrupt Enabled.
+ * @var BPWM_T::CAPIF
+ * Offset: 0x254 BPWM Capture Interrupt Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * @var BPWM_T::PBUF
+ * Offset: 0x304 BPWM PERIOD Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PBUF |BPWM Period Buffer (Read Only)
+ * | | |Used as PERIOD active register.
+ * @var BPWM_T::CMPBUF[6]
+ * Offset: 0x31C BPWM CMPDAT 0~5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only)
+ * | | |Used as CMP active register.
+ */
+ __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */
+ __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */
+ __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */
+ __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[7];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CMPDAT[6]; /*!< [0x0050] BPWM Comparator Register 0~5 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE4[10];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE5[7];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */
+ __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */
+ __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */
+ __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE6[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */
+ __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE7[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE8[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE9[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */
+ __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE10[4];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */
+ __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE11[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE12[55];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */
+ __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */
+ __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */
+ BCAPDAT_T CAPDAT[6]; /*!< [0x020C] BPWM Rising and Falling Capture Data Register 0~5 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE13[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */
+ __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE14[43];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE15[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t CMPBUF[6]; /*!< [0x031c] BPWM CMPDAT 0~5 Buffer */
+
+} BPWM_T;
+
+/**
+ @addtogroup BPWM_CONST BPWM Bit Field Definition
+ Constant Definitions for BPWM Controller
+@{ */
+
+#define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */
+#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */
+
+#define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */
+#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */
+
+#define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */
+#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */
+
+#define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */
+#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */
+
+#define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */
+#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */
+
+#define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */
+#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */
+
+#define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */
+#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */
+
+#define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */
+#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */
+
+#define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */
+#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */
+
+#define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */
+#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */
+
+#define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */
+#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */
+
+#define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */
+#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */
+
+#define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */
+#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */
+
+#define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */
+#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */
+
+#define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */
+#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */
+
+#define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */
+#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */
+
+#define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */
+#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */
+
+#define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */
+#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */
+
+#define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */
+#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */
+
+#define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */
+#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */
+
+#define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */
+#define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */
+
+#define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */
+#define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */
+
+#define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */
+#define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */
+
+#define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */
+#define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */
+
+#define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */
+#define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */
+
+#define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */
+#define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */
+
+#define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */
+#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */
+
+#define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */
+#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */
+
+#define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */
+#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */
+
+#define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */
+#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */
+
+#define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */
+#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */
+
+#define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */
+#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */
+
+#define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */
+#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */
+
+#define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */
+#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */
+
+#define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */
+#define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */
+
+#define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */
+#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */
+
+#define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */
+#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */
+
+#define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */
+#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */
+
+#define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */
+#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */
+
+#define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */
+#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */
+
+#define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */
+#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */
+
+#define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */
+#define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */
+
+#define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */
+#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */
+
+#define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */
+#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */
+
+#define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */
+#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */
+
+#define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */
+#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */
+
+#define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */
+#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */
+
+#define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */
+#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */
+
+#define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */
+#define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */
+
+#define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */
+#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */
+
+#define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */
+#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */
+
+#define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */
+#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */
+
+#define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */
+#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */
+
+#define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */
+#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */
+
+#define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */
+#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */
+
+#define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */
+#define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */
+
+#define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */
+#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */
+
+#define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */
+#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */
+
+#define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */
+#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */
+
+#define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */
+#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */
+
+#define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */
+#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */
+
+#define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */
+#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */
+
+#define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */
+#define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */
+
+#define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */
+#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */
+
+#define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */
+#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */
+
+#define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */
+#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */
+
+#define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */
+#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */
+
+#define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */
+#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */
+
+#define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */
+#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */
+
+#define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */
+#define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */
+
+#define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */
+#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */
+
+#define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */
+#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */
+
+#define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */
+#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */
+
+#define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */
+#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */
+
+#define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */
+#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */
+
+#define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */
+#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */
+
+#define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */
+#define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */
+
+#define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */
+#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */
+
+#define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */
+#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */
+
+#define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */
+#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */
+
+#define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */
+#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */
+
+#define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */
+#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */
+
+#define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */
+#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */
+
+#define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */
+#define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */
+
+#define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */
+#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */
+
+#define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */
+#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */
+
+#define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */
+#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */
+
+#define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */
+#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */
+
+#define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */
+#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */
+
+#define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */
+#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */
+
+#define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */
+#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */
+
+#define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */
+#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */
+
+#define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */
+#define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */
+
+#define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */
+#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */
+
+#define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */
+#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */
+
+#define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */
+#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */
+
+#define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */
+#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */
+
+#define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */
+#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */
+
+#define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */
+#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */
+
+#define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */
+#define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */
+
+#define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */
+#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */
+
+#define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */
+#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */
+
+#define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */
+#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */
+
+#define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */
+#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */
+
+#define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */
+#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */
+
+#define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */
+#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */
+
+#define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */
+#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */
+
+#define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */
+#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */
+
+#define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */
+#define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */
+
+#define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */
+#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */
+
+#define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */
+#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */
+
+#define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */
+#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */
+
+#define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */
+#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */
+
+#define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */
+#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */
+
+#define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */
+#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */
+
+#define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */
+#define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */
+
+#define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */
+#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */
+
+#define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */
+#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */
+
+#define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */
+#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */
+
+#define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */
+#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */
+
+#define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */
+#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */
+
+#define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */
+#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */
+
+#define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */
+#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */
+
+#define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */
+#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */
+
+#define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */
+#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */
+
+#define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */
+#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */
+
+#define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */
+#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */
+
+#define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */
+#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */
+
+#define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */
+#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */
+
+#define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */
+#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */
+
+#define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */
+#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */
+
+#define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */
+#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */
+
+#define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */
+#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */
+
+#define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */
+#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */
+
+#define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */
+#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */
+
+#define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */
+#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */
+
+#define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */
+#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */
+
+#define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */
+#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */
+
+#define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */
+#define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */
+
+#define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */
+#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */
+
+#define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */
+#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */
+
+#define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */
+#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */
+
+#define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */
+#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */
+
+#define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */
+#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */
+
+#define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */
+#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */
+
+#define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */
+#define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */
+
+#define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */
+#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */
+
+#define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */
+#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */
+
+#define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */
+#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */
+
+#define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */
+#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */
+
+#define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */
+#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */
+
+#define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */
+#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */
+
+#define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */
+#define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */
+
+#define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */
+#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */
+
+#define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */
+#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */
+
+#define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */
+#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */
+
+#define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */
+#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */
+
+#define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */
+#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */
+
+#define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */
+#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */
+
+#define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */
+#define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */
+
+#define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */
+#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */
+
+#define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */
+#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */
+
+#define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */
+#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */
+
+#define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */
+#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */
+
+#define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */
+#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */
+
+#define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */
+#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */
+
+#define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */
+#define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */
+
+#define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */
+#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */
+
+#define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */
+#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */
+
+#define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */
+#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */
+
+#define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */
+#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */
+
+#define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */
+#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */
+
+#define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */
+#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */
+
+#define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */
+#define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */
+
+#define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */
+#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */
+
+#define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */
+#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */
+
+#define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */
+#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */
+
+#define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */
+#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */
+
+#define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */
+#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */
+
+#define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */
+#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */
+
+#define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */
+#define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */
+
+#define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */
+#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */
+
+#define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */
+#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */
+
+#define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */
+#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */
+
+#define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */
+#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */
+
+#define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */
+#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */
+
+#define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */
+#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */
+
+#define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */
+#define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */
+
+#define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */
+#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */
+
+#define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */
+#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */
+
+#define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */
+#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */
+
+#define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */
+#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */
+
+#define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */
+#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */
+
+#define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */
+#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */
+
+#define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */
+#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */
+
+#define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */
+#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */
+
+#define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */
+#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */
+
+#define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */
+#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */
+
+#define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */
+#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */
+
+#define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */
+#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */
+
+#define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */
+#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */
+
+#define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */
+#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */
+
+#define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */
+#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */
+
+#define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */
+#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */
+
+#define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */
+#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */
+
+#define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */
+#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */
+
+#define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */
+#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */
+
+#define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */
+#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */
+
+#define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */
+#define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */
+
+#define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */
+#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */
+
+#define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */
+#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */
+
+#define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */
+#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */
+
+#define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */
+#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */
+
+#define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */
+#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */
+
+#define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */
+#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */
+
+#define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */
+#define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */
+
+#define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */
+#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */
+
+#define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */
+#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */
+
+#define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */
+#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */
+
+#define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */
+#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */
+
+#define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */
+#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */
+
+#define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */
+#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */
+
+#define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */
+#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */
+
+/**@}*/ /* BPWM_CONST */
+/**@}*/ /* end of BPWM register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __BPWM_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/can_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/can_reg.h
new file mode 100644
index 00000000000..86340d99d85
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/can_reg.h
@@ -0,0 +1,759 @@
+/**************************************************************************//**
+ * @file can_reg.h
+ * @version V1.00
+ * @brief CAN register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CAN_REG_H__
+#define __CAN_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup CAN Controller Area Network Controller(CAN)
+ Memory Mapped Structure for CAN Controller
+@{ */
+
+
+typedef struct
+{
+
+ /**
+ * @var CAN_IF_T::CREQ
+ * Offset: 0x20, 0x80 IFn Command Request Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |MessageNumber|Message Number
+ * | | |0x01-0x20: Valid Message Number, the Message Object in the Message
+ * | | |RAM is selected for data transfer.
+ * | | |0x00: Not a valid Message Number, interpreted as 0x20.
+ * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
+ * |[15] |Busy |Busy Flag
+ * | | |0 = Read/write action has finished.
+ * | | |1 = Writing to the IFn Command Request Register is in progress
+ * | | |This bit can only be read by the software.
+ * @var CAN_IF_T::CMASK
+ * Offset: 0x24, 0x84 IFn Command Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DAT_B |Access Data Bytes [7:4]
+ * | | |Write Operation:
+ * | | |0 = Data Bytes [7:4] unchanged.
+ * | | |1 = Transfer Data Bytes [7:4] to Message Object.
+ * | | |Read Operation:
+ * | | |0 = Data Bytes [7:4] unchanged.
+ * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
+ * |[1] |DAT_A |Access Data Bytes [3:0]
+ * | | |Write Operation:
+ * | | |0 = Data Bytes [3:0] unchanged.
+ * | | |1 = Transfer Data Bytes [3:0] to Message Object.
+ * | | |Read Operation:
+ * | | |0 = Data Bytes [3:0] unchanged.
+ * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
+ * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
+ * | | |0 = TxRqst bit unchanged.
+ * | | |1 = Set TxRqst bit.
+ * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
+ * | | |Access New Data Bit when Read Operation.
+ * | | |0 = NewDat bit remains unchanged.
+ * | | |1 = Clear NewDat bit in the Message Object.
+ * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat
+ * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
+ * |[3] |ClrIntPnd |Clear Interrupt Pending Bit
+ * | | |Write Operation:
+ * | | |When writing to a Message Object, this bit is ignored.
+ * | | |Read Operation:
+ * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
+ * | | |1 = Clear IntPnd bit in the Message Object.
+ * |[4] |Control |Control Access Control Bits
+ * | | |Write Operation:
+ * | | |0 = Control Bits unchanged.
+ * | | |1 = Transfer Control Bits to Message Object.
+ * | | |Read Operation:
+ * | | |0 = Control Bits unchanged.
+ * | | |1 = Transfer Control Bits to IFn Message Buffer Register.
+ * |[5] |Arb |Access Arbitration Bits
+ * | | |Write Operation:
+ * | | |0 = Arbitration bits unchanged.
+ * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object.
+ * | | |Read Operation:
+ * | | |0 = Arbitration bits unchanged.
+ * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
+ * |[6] |Mask |Access Mask Bits
+ * | | |Write Operation:
+ * | | |0 = Mask bits unchanged.
+ * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
+ * | | |Read Operation:
+ * | | |0 = Mask bits unchanged.
+ * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
+ * |[7] |WR_RD |Write / Read Mode
+ * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
+ * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
+ * @var CAN_IF_T::MASK1
+ * Offset: 0x28, 0x88 IFn Mask 1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |Msk |Identifier Mask 15-0
+ * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+ * | | |1 = The corresponding identifier bit is used for acceptance filtering.
+ * @var CAN_IF_T::MASK2
+ * Offset: 0x2C, 0x8C IFn Mask 2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[12:0] |Msk |Identifier Mask 28-16
+ * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+ * | | |1 = The corresponding identifier bit is used for acceptance filtering.
+ * |[14] |MDir |Mask Message Direction
+ * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
+ * | | |1 = The message direction bit (Dir) is used for acceptance filtering.
+ * |[15] |MXtd |Mask Extended Identifier
+ * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
+ * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
+ * | | |Note: When 11-bit (standard) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])
+ * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
+ * @var CAN_IF_T::ARB1
+ * Offset: 0x30, 0x90 IFn Arbitration 1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |ID |Message Identifier 15-0
+ * | | |ID28 - ID0, 29-bit Identifier (Extended Frame)
+ * | | |ID28 - ID18, 11-bit Identifier (Standard Frame)
+ * @var CAN_IF_T::ARB2
+ * Offset: 0x34, 0x94 IFn Arbitration 2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[12:0] |ID |Message Identifier 28-16
+ * | | |ID28 - ID0, 29-bit Identifier (Extended Frame)
+ * | | |ID28 - ID18, 11-bit Identifier (Standard Frame)
+ * |[13] |Dir |Message Direction
+ * | | |0 = Direction is receive.
+ * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted
+ * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
+ * | | |1 = Direction is transmit.
+ * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame
+ * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
+ * |[14] |Xtd |Extended Identifier
+ * | | |0 = The 11-bit (standard) Identifier will be used for this Message Object.
+ * | | |1 = The 29-bit (extended) Identifier will be used for this Message Object.
+ * |[15] |MsgVal |Message Valid
+ * | | |0 = The Message Object is ignored by the Message Handler.
+ * | | |1 = The Message Object is configured and should be considered by the Message Handler.
+ * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])
+ * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
+ * @var CAN_IF_T::MCON
+ * Offset: 0x38, 0x98 IFn Message Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DLC |Data Length Code
+ * | | |0-8: Data Frame has 0-8 data bytes.
+ * | | |9-15: Data Frame has 8 data bytes
+ * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes
+ * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
+ * | | |Data(0): 1st data byte of a CAN Data Frame
+ * | | |Data(1): 2nd data byte of a CAN Data Frame
+ * | | |Data(2): 3rd data byte of a CAN Data Frame
+ * | | |Data(3): 4th data byte of a CAN Data Frame
+ * | | |Data(4): 5th data byte of a CAN Data Frame
+ * | | |Data(5): 6th data byte of a CAN Data Frame
+ * | | |Data(6): 7th data byte of a CAN Data Frame
+ * | | |Data(7): 8th data byte of a CAN Data Frame
+ * | | |Note: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last
+ * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object
+ * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
+ * |[7] |EoB |End of Buffer
+ * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
+ * | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
+ * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer
+ * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one
+ * |[8] |TxRqst |Transmit Request
+ * | | |0 = This Message Object is not waiting for transmission.
+ * | | |1 = The transmission of this Message Object is requested and is not yet done.
+ * |[9] |RmtEn |Remote Enable Bit
+ * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
+ * | | |1 = At the reception of a Remote Frame, TxRqst is set.
+ * |[10] |RxIE |Receive Interrupt Enable Bit
+ * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
+ * | | |1 = IntPnd will be set after a successful reception of a frame.
+ * |[11] |TxIE |Transmit Interrupt Enable Bit
+ * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
+ * | | |1 = IntPnd will be set after a successful transmission of a frame.
+ * |[12] |UMask |Use Acceptance Mask
+ * | | |0 = Mask ignored.
+ * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
+ * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one.
+ * |[13] |IntPnd |Interrupt Pending
+ * | | |0 = This message object is not the source of an interrupt.
+ * | | |1 = This message object is the source of an interrupt
+ * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
+ * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
+ * | | |0 = No message lost since last time this bit was reset by the CPU.
+ * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
+ * |[15] |NewDat |New Data
+ * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
+ * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+ * @var CAN_IF_T::DAT_A1
+ * Offset: 0x3C, 0x9C IFn Data A1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |Data_0_ |Data Byte 0
+ * | | |1st data byte of a CAN Data Frame
+ * |[15:8] |Data_1_ |Data Byte 1
+ * | | |2nd data byte of a CAN Data Frame
+ * @var CAN_IF_T::DAT_A2
+ * Offset: 0x40, 0xA0 IFn Data A2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |Data_2_ |Data Byte 2
+ * | | |3rd data byte of CAN Data Frame
+ * |[15:8] |Data_3_ |Data Byte 3
+ * | | |4th data byte of CAN Data Frame
+ * @var CAN_IF_T::DAT_B1
+ * Offset: 0x44, 0xA4 IFn Data B1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |Data_4_ |Data Byte 4
+ * | | |5th data byte of CAN Data Frame
+ * |[15:8] |Data_5_ |Data Byte 5
+ * | | |6th data byte of CAN Data Frame
+ * @var CAN_IF_T::DAT_B2
+ * Offset: 0x48, 0xA8 IFn Data B2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |Data_6_ |Data Byte 6
+ * | | |7th data byte of CAN Data Frame.
+ * |[15:8] |Data_7_ |Data Byte 7
+ * | | |8th data byte of CAN Data Frame.
+ */
+ __IO uint32_t CREQ; /*!< [0x0020] IFn Command Request Register */
+ __IO uint32_t CMASK; /*!< [0x0024] IFn Command Mask Register */
+ __IO uint32_t MASK1; /*!< [0x0028] IFn Mask 1 Register */
+ __IO uint32_t MASK2; /*!< [0x002c] IFn Mask 2 Register */
+ __IO uint32_t ARB1; /*!< [0x0030] IFn Arbitration 1 Register */
+ __IO uint32_t ARB2; /*!< [0x0034] IFn Arbitration 2 Register */
+ __IO uint32_t MCON; /*!< [0x0038] IFn Message Control Register */
+ __IO uint32_t DAT_A1; /*!< [0x003c] IFn Data A1 Register */
+ __IO uint32_t DAT_A2; /*!< [0x0040] IFn Data A2 Register */
+ __IO uint32_t DAT_B1; /*!< [0x0044] IFn Data B1 Register */
+ __IO uint32_t DAT_B2; /*!< [0x0048] IFn Data B2 Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[13];
+ /// @endcond //HIDDEN_SYMBOLS
+} CAN_IF_T;
+
+
+typedef struct
+{
+
+
+ /**
+ * @var CAN_T::CON
+ * Offset: 0x00 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |Init |Init Initialization
+ * | | |0 = Normal Operation.
+ * | | |1 = Initialization is started.
+ * |[1] |IE |Module Interrupt Enable Bit
+ * | | |0 = Function interrupt is Disabled.
+ * | | |1 = Function interrupt is Enabled.
+ * |[2] |SIE |Status Change Interrupt Enable Bit
+ * | | |0 = Disabled - No Status Change Interrupt will be generated.
+ * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
+ * |[3] |EIE |Error Interrupt Enable Bit
+ * | | |0 = Disabled - No Error Status Interrupt will be generated.
+ * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
+ * |[5] |DAR |Automatic Re-transmission Disable Bit
+ * | | |0 = Automatic Retransmission of disturbed messages Enabled.
+ * | | |1 = Automatic Retransmission Disabled.
+ * |[6] |CCE |Configuration Change Enable Bit
+ * | | |0 = No write access to the Bit Timing Register.
+ * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
+ * |[7] |Test |Test Mode Enable Bit
+ * | | |0 = Normal Operation.
+ * | | |1 = Test Mode.
+ * @var CAN_T::STATUS
+ * Offset: 0x04 Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |LEC |Last Error Code (Type of the Last Error to Occur on the CAN Bus)
+ * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus
+ * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error
+ * | | |The unused code '7' may be written by the CPU to check for updates
+ * | | |The Error! Reference source not found
+ * | | |describes the error code.
+ * |[3] |TxOK |Transmitted a Message Successfully
+ * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted
+ * | | |This bit is never reset by the CAN Core.
+ * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
+ * |[4] |RxOK |Received a Message Successfully
+ * | | |0 = No message has been successfully received since this bit was last reset by the CPU
+ * | | |This bit is never reset by the CAN Core.
+ * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
+ * |[5] |EPass |Error Passive (Read Only)
+ * | | |0 = The CAN Core is error active.
+ * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
+ * |[6] |EWarn |Error Warning Status (Read Only)
+ * | | |0 = Both error counters are below the error warning limit of 96.
+ * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
+ * |[7] |BOff |Bus-off Status (Read Only)
+ * | | |0 = The CAN module is not in bus-off state.
+ * | | |1 = The CAN module is in bus-off state.
+ * @var CAN_T::ERR
+ * Offset: 0x08 Error Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TEC |Transmit Error Counter
+ * | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
+ * |[14:8] |REC |Receive Error Counter
+ * | | |Actual state of the Receive Error Counter. Values between 0 and 127.
+ * |[15] |RP |Receive Error Passive
+ * | | |0 = The Receive Error Counter is below the error passive level.
+ * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
+ * @var CAN_T::BTIME
+ * Offset: 0x0C Bit Timing Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |BRP |Baud Rate Prescaler
+ * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta
+ * | | |The bit time is built up from a multiple of this quanta
+ * | | |Valid values for the Baud Rate Prescaler are [0...63]
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+ * |[7:6] |SJW |(Re)Synchronization Jump Width
+ * | | |0x0-0x3: Valid programmed values are [0...3]
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+ * |[11:8] |TSeg1 |Time Segment Before the Sample Point Minus Sync_Seg
+ * | | |0x01-0x0F: valid values for TSeg1 are [1...15]
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
+ * |[14:12] |TSeg2 |Time Segment After Sample Point
+ * | | |0x0-0x7: Valid values for TSeg2 are [0...7]
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+ * @var CAN_T::IIDR
+ * Offset: 0x10 Interrupt Identifier Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |IntId |Interrupt Identifier (Indicates the Source of the Interrupt)
+ * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order
+ * | | |An interrupt remains pending until the application software has cleared it
+ * | | |If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active
+ * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
+ * | | |The Status Interrupt has the highest priority
+ * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
+ * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13])
+ * | | |The Status Interrupt is cleared by reading the Status Register.
+ * @var CAN_T::TEST
+ * Offset: 0x14 Test Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2] |Basic |Basic Mode
+ * | | |0 = Basic Mode Disabled.
+ * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+ * |[3] |Silent |Silent Mode
+ * | | |0 = Normal operation.
+ * | | |1 = The module is in Silent Mode.
+ * |[4] |LBack |Loop Back Mode Enable Bit
+ * | | |0 = Loop Back Mode is Disabled.
+ * | | |1 = Loop Back Mode is Enabled.
+ * |[6:5] |Tx |Tx[1:0]: Control of CAN_TX Pin
+ * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
+ * | | |01 = Sample Point can be monitored at CAN_TX pin.
+ * | | |10 = CAN_TX pin drives a dominant ('0') value.
+ * | | |11 = CAN_TX pin drives a recessive ('1') value.
+ * |[7] |Rx |Monitors the Actual Value of CAN_RX Pin (Read Only) *(1)
+ * | | |0 = The CAN bus is dominant (CAN_RX = '0').
+ * | | |1 = The CAN bus is recessive (CAN_RX = '1').
+ * @var CAN_T::BRPE
+ * Offset: 0x18 Baud Rate Prescaler Extension Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension
+ * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023
+ * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
+ * @var CAN_T::TXREQ1
+ * Offset: 0x100 Transmission Request Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |TxRqst16_1|Transmission Request Bits 16-1 (of All Message Objects)
+ * | | |0 = This Message Object is not waiting for transmission.
+ * | | |1 = The transmission of this Message Object is requested and is not yet done.
+ * | | |These bits are read only.
+ * @var CAN_T::TXREQ2
+ * Offset: 0x104 Transmission Request Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |TxRqst32_17|Transmission Request Bits 32-17 (of All Message Objects)
+ * | | |0 = This Message Object is not waiting for transmission.
+ * | | |1 = The transmission of this Message Object is requested and is not yet done.
+ * | | |These bits are read only.
+ * @var CAN_T::NDAT1
+ * Offset: 0x120 New Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |NewData16_1|New Data Bits 16-1 (of All Message Objects)
+ * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+ * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+ * @var CAN_T::NDAT2
+ * Offset: 0x124 New Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |NewData32_17|New Data Bits 32-17 (of All Message Objects)
+ * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+ * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+ * @var CAN_T::IPND1
+ * Offset: 0x140 Interrupt Pending Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |IntPnd16_1|Interrupt Pending Bits 16-1 (of All Message Objects)
+ * | | |0 = This message object is not the source of an interrupt.
+ * | | |1 = This message object is the source of an interrupt.
+ * @var CAN_T::IPND2
+ * Offset: 0x144 Interrupt Pending Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |IntPnd32_17|Interrupt Pending Bits 32-17 (of All Message Objects)
+ * | | |0 = This message object is not the source of an interrupt.
+ * | | |1 = This message object is the source of an interrupt.
+ * @var CAN_T::MVLD1
+ * Offset: 0x160 Message Valid Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |MsgVal16_1|Message Valid Bits 16-1 (of All Message Objects) (Read Only)
+ * | | |0 = This Message Object is ignored by the Message Handler.
+ * | | |1 = This Message Object is configured and should be considered by the Message Handler.
+ * | | |Ex
+ * | | |CAN_MVLD1[0] means Message object No.1 is valid or not
+ * | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
+ * @var CAN_T::MVLD2
+ * Offset: 0x164 Message Valid Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |MsgVal32_17|Message Valid Bits 32-17 (of All Message Objects) (Read Only)
+ * | | |0 = This Message Object is ignored by the Message Handler.
+ * | | |1 = This Message Object is configured and should be considered by the Message Handler.
+ * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not
+ * | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
+ * @var CAN_T::WU_EN
+ * Offset: 0x168 Wake-up Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WAKUP_EN |Wake-up Enable Bit
+ * | | |0 = The wake-up function Disabled.
+ * | | |1 = The wake-up function Enabled.
+ * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
+ * @var CAN_T::WU_STATUS
+ * Offset: 0x16C Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WAKUP_STS |Wake-up Status
+ * | | |0 = No wake-up event occurred.
+ * | | |1 = Wake-up event occurred.
+ * | | |Note: This bit can be cleared by writing '0'.
+ */
+ __IO uint32_t CON; /*!< [0x0000] Control Register */
+ __IO uint32_t STATUS; /*!< [0x0004] Status Register */
+ __I uint32_t ERR; /*!< [0x0008] Error Counter Register */
+ __IO uint32_t BTIME; /*!< [0x000c] Bit Timing Register */
+ __I uint32_t IIDR; /*!< [0x0010] Interrupt Identifier Register */
+ __IO uint32_t TEST; /*!< [0x0014] Test Register */
+ __IO uint32_t BRPE; /*!< [0x0018] Baud Rate Prescaler Extension Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO CAN_IF_T IF[2];
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[8];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t TXREQ1; /*!< [0x0100] Transmission Request Register 1 */
+ __I uint32_t TXREQ2; /*!< [0x0104] Transmission Request Register 2 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[6];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t NDAT1; /*!< [0x0120] New Data Register 1 */
+ __I uint32_t NDAT2; /*!< [0x0124] New Data Register 2 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE4[6];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t IPND1; /*!< [0x0140] Interrupt Pending Register 1 */
+ __I uint32_t IPND2; /*!< [0x0144] Interrupt Pending Register 2 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE5[6];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t MVLD1; /*!< [0x0160] Message Valid Register 1 */
+ __I uint32_t MVLD2; /*!< [0x0164] Message Valid Register 2 */
+ __IO uint32_t WU_EN; /*!< [0x0168] Wake-up Enable Control Register */
+ __IO uint32_t WU_STATUS; /*!< [0x016c] Wake-up Status Register */
+
+} CAN_T;
+
+/**
+ @addtogroup CAN_CONST CAN Bit Field Definition
+ Constant Definitions for CAN Controller
+@{ */
+
+#define CAN_CON_INIT_Pos (0) /*!< CAN_T::CON: Init Position */
+#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: Init Mask */
+
+#define CAN_CON_IE_Pos (1) /*!< CAN_T::CON: IE Position */
+#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
+
+#define CAN_CON_SIE_Pos (2) /*!< CAN_T::CON: SIE Position */
+#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
+
+#define CAN_CON_EIE_Pos (3) /*!< CAN_T::CON: EIE Position */
+#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
+
+#define CAN_CON_DAR_Pos (5) /*!< CAN_T::CON: DAR Position */
+#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
+
+#define CAN_CON_CCE_Pos (6) /*!< CAN_T::CON: CCE Position */
+#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
+
+#define CAN_CON_TEST_Pos (7) /*!< CAN_T::CON: Test Position */
+#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: Test Mask */
+
+#define CAN_STATUS_LEC_Pos (0) /*!< CAN_T::STATUS: LEC Position */
+#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
+
+#define CAN_STATUS_TXOK_Pos (3) /*!< CAN_T::STATUS: TxOK Position */
+#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TxOK Mask */
+
+#define CAN_STATUS_RXOK_Pos (4) /*!< CAN_T::STATUS: RxOK Position */
+#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RxOK Mask */
+
+#define CAN_STATUS_EPASS_Pos (5) /*!< CAN_T::STATUS: EPass Position */
+#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPass Mask */
+
+#define CAN_STATUS_EWARN_Pos (6) /*!< CAN_T::STATUS: EWarn Position */
+#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWarn Mask */
+
+#define CAN_STATUS_BOFF_Pos (7) /*!< CAN_T::STATUS: BOff Position */
+#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOff Mask */
+
+#define CAN_ERR_TEC_Pos (0) /*!< CAN_T::ERR: TEC Position */
+#define CAN_ERR_TEC_Msk (0xfful << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
+
+#define CAN_ERR_REC_Pos (8) /*!< CAN_T::ERR: REC Position */
+#define CAN_ERR_REC_Msk (0x7ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
+
+#define CAN_ERR_RP_Pos (15) /*!< CAN_T::ERR: RP Position */
+#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
+
+#define CAN_BTIME_BRP_Pos (0) /*!< CAN_T::BTIME: BRP Position */
+#define CAN_BTIME_BRP_Msk (0x3ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
+
+#define CAN_BTIME_SJW_Pos (6) /*!< CAN_T::BTIME: SJW Position */
+#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
+
+#define CAN_BTIME_TSEG1_Pos (8) /*!< CAN_T::BTIME: TSeg1 Position */
+#define CAN_BTIME_TSEG1_Msk (0xful << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSeg1 Mask */
+
+#define CAN_BTIME_TSEG2_Pos (12) /*!< CAN_T::BTIME: TSeg2 Position */
+#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSeg2 Mask */
+
+#define CAN_IIDR_IntId_Pos (0) /*!< CAN_T::IIDR: IntId Position */
+#define CAN_IIDR_IntId_Msk (0xfffful << CAN_IIDR_IntId_Pos) /*!< CAN_T::IIDR: IntId Mask */
+
+#define CAN_TEST_BASIC_Pos (2) /*!< CAN_T::TEST: Basic Position */
+#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
+
+#define CAN_TEST_SILENT_Pos (3) /*!< CAN_T::TEST: Silent Position */
+#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
+
+#define CAN_TEST_LBACK_Pos (4) /*!< CAN_T::TEST: LBack Position */
+#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBack Mask */
+
+#define CAN_TEST_Tx_Pos (5) /*!< CAN_T::TEST: Tx Position */
+#define CAN_TEST_Tx_Msk (0x3ul << CAN_TEST_Tx_Pos) /*!< CAN_T::TEST: Tx Mask */
+
+#define CAN_TEST_Rx_Pos (7) /*!< CAN_T::TEST: Rx Position */
+#define CAN_TEST_Rx_Msk (0x1ul << CAN_TEST_Rx_Pos) /*!< CAN_T::TEST: Rx Mask */
+
+#define CAN_BRPE_BRPE_Pos (0) /*!< CAN_T::BRPE: BRPE Position */
+#define CAN_BRPE_BRPE_Msk (0xful << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
+
+#define CAN_IF_CREQ_MSGNUM_Pos (0) /*!< CAN_IF_T::CREQ: MessageNumber Position*/
+#define CAN_IF_CREQ_MSGNUM_Msk (0x3ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MessageNumber Mask */
+
+#define CAN_IF_CREQ_BUSY_Pos (15) /*!< CAN_IF_T::CREQ: Busy Position */
+#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: Busy Mask */
+
+#define CAN_IF_CMASK_DATAB_Pos (0) /*!< CAN_IF_T::CMASK: DAT_B Position */
+#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DAT_B Mask */
+
+#define CAN_IF_CMASK_DATAA_Pos (1) /*!< CAN_IF_T::CMASK: DAT_A Position */
+#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DAT_A Mask */
+
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos (2) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Position*/
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Mask */
+
+#define CAN_IF_CMASK_CLRINTPND_Pos (3) /*!< CAN_IF_T::CMASK: ClrIntPnd Position */
+#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: ClrIntPnd Mask */
+
+#define CAN_IF_CMASK_CONTROL_Pos (4) /*!< CAN_IF_T::CMASK: Control Position */
+#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: Control Mask */
+
+#define CAN_IF_CMASK_ARB_Pos (5) /*!< CAN_IF_T::CMASK: Arb Position */
+#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: Arb Mask */
+
+#define CAN_IF_CMASK_MASK_Pos (6) /*!< CAN_IF_T::CMASK: Mask Position */
+#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: Mask Mask */
+
+#define CAN_IF_CMASK_WRRD_Pos (7) /*!< CAN_IF_T::CMASK: WR_RD Position */
+#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WR_RD Mask */
+
+#define CAN_IF_MASK1_Msk_Pos (0) /*!< CAN_IF_T::MASK1: Msk Position */
+#define CAN_IF_MASK1_Msk_Msk (0xfffful << CAN_IF_MASK1_Msk_Pos) /*!< CAN_IF_T::MASK1: Msk Mask */
+
+#define CAN_IF_MASK2_Msk_Pos (0) /*!< CAN_IF_T::MASK2: Msk Position */
+#define CAN_IF_MASK2_Msk_Msk (0x1ffful << CAN_IF_MASK2_Msk_Pos) /*!< CAN_IF_T::MASK2: Msk Mask */
+
+#define CAN_IF_MASK2_MDIR_Pos (14) /*!< CAN_IF_T::MASK2: MDir Position */
+#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDir Mask */
+
+#define CAN_IF_MASK2_MXTD_Pos (15) /*!< CAN_IF_T::MASK2: MXtd Position */
+#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXtd Mask */
+
+#define CAN_IF_ARB1_ID_Pos (0) /*!< CAN_IF_T::ARB1: ID Position */
+#define CAN_IF_ARB1_ID_Msk (0xfffful << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
+
+#define CAN_IF_ARB2_ID_Pos (0) /*!< CAN_IF_T::ARB2: ID Position */
+#define CAN_IF_ARB2_ID_Msk (0x1ffful << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
+
+#define CAN_IF_ARB2_DIR_Pos (13) /*!< CAN_IF_T::ARB2: Dir Position */
+#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: Dir Mask */
+
+#define CAN_IF_ARB2_XTD_Pos (14) /*!< CAN_IF_T::ARB2: Xtd Position */
+#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: Xtd Mask */
+
+#define CAN_IF_ARB2_MSGVAL_Pos (15) /*!< CAN_IF_T::ARB2: MsgVal Position */
+#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MsgVal Mask */
+
+#define CAN_IF_MCON_DLC_Pos (0) /*!< CAN_IF_T::MCON: DLC Position */
+#define CAN_IF_MCON_DLC_Msk (0xful << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
+
+#define CAN_IF_MCON_EOB_Pos (7) /*!< CAN_IF_T::MCON: EoB Position */
+#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EoB Mask */
+
+#define CAN_IF_MCON_TxRqst_Pos (8) /*!< CAN_IF_T::MCON: TxRqst Position */
+#define CAN_IF_MCON_TxRqst_Msk (0x1ul << CAN_IF_MCON_TxRqst_Pos) /*!< CAN_IF_T::MCON: TxRqst Mask */
+
+#define CAN_IF_MCON_RmtEn_Pos (9) /*!< CAN_IF_T::MCON: RmtEn Position */
+#define CAN_IF_MCON_RmtEn_Msk (0x1ul << CAN_IF_MCON_RmtEn_Pos) /*!< CAN_IF_T::MCON: RmtEn Mask */
+
+#define CAN_IF_MCON_RXIE_Pos (10) /*!< CAN_IF_T::MCON: RxIE Position */
+#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RxIE Mask */
+
+#define CAN_IF_MCON_TXIE_Pos (11) /*!< CAN_IF_T::MCON: TxIE Position */
+#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TxIE Mask */
+
+#define CAN_IF_MCON_UMASK_Pos (12) /*!< CAN_IF_T::MCON: UMask Position */
+#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMask Mask */
+
+#define CAN_IF_MCON_IntPnd_Pos (13) /*!< CAN_IF_T::MCON: IntPnd Position */
+#define CAN_IF_MCON_IntPnd_Msk (0x1ul << CAN_IF_MCON_IntPnd_Pos) /*!< CAN_IF_T::MCON: IntPnd Mask */
+
+#define CAN_IF_MCON_MsgLst_Pos (14) /*!< CAN_IF_T::MCON: MsgLst Position */
+#define CAN_IF_MCON_MsgLst_Msk (0x1ul << CAN_IF_MCON_MsgLst_Pos) /*!< CAN_IF_T::MCON: MsgLst Mask */
+
+#define CAN_IF_MCON_NEWDAT_Pos (15) /*!< CAN_IF_T::MCON: NewDat Position */
+#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NewDat Mask */
+
+#define CAN_IF_DAT_A1_DATA0_Pos (0) /*!< CAN_IF_T::DAT_A1: Data_0_ Position */
+#define CAN_IF_DAT_A1_DATA0_Msk (0xfful << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DAT_A1: Data_0_ Mask */
+
+#define CAN_IF_DAT_A1_DATA1_Pos (8) /*!< CAN_IF_T::DAT_A1: Data_1_ Position */
+#define CAN_IF_DAT_A1_DATA1_Msk (0xfful << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DAT_A1: Data_1_ Mask */
+
+#define CAN_IF_DAT_A2_DATA2_Pos (0) /*!< CAN_IF_T::DAT_A2: Data_2_ Position */
+#define CAN_IF_DAT_A2_DATA2_Msk (0xfful << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DAT_A2: Data_2_ Mask */
+
+#define CAN_IF_DAT_A2_DATA3_Pos (8) /*!< CAN_IF_T::DAT_A2: Data_3_ Position */
+#define CAN_IF_DAT_A2_DATA3_Msk (0xfful << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DAT_A2: Data_3_ Mask */
+
+#define CAN_IF_DAT_B1_DATA4_Pos (0) /*!< CAN_IF_T::DAT_B1: Data_4_ Position */
+#define CAN_IF_DAT_B1_DATA4_Msk (0xfful << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DAT_B1: Data_4_ Mask */
+
+#define CAN_IF_DAT_B1_DATA5_Pos (8) /*!< CAN_IF_T::DAT_B1: Data_5_ Position */
+#define CAN_IF_DAT_B1_DATA5_Msk (0xfful << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DAT_B1: Data_5_ Mask */
+
+#define CAN_IF_DAT_B2_DATA6_Pos (0) /*!< CAN_IF_T::DAT_B2: Data_6_ Position */
+#define CAN_IF_DAT_B2_DATA6_Msk (0xfful << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DAT_B2: Data_6_ Mask */
+
+#define CAN_IF_DAT_B2_DATA7_Pos (8) /*!< CAN_IF_T::DAT_B2: Data_7_ Position */
+#define CAN_IF_DAT_B2_DATA7_Msk (0xfful << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DAT_B2: Data_7_ Mask */
+
+#define CAN_TXREQ1_TXRQST16_1_Pos (0) /*!< CAN_T::TXREQ1: TxRqst16_1 Position */
+#define CAN_TXREQ1_TXRQST16_1_Msk (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos) /*!< CAN_T::TXREQ1: TxRqst16_1 Mask */
+
+#define CAN_TXREQ2_TXRQST32_17_Pos (0) /*!< CAN_T::TXREQ2: TxRqst32_17 Position */
+#define CAN_TXREQ2_TXRQST32_17_Msk (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos) /*!< CAN_T::TXREQ2: TxRqst32_17 Mask */
+
+#define CAN_NDAT1_NewData16_1_Pos (0) /*!< CAN_T::NDAT1: NewData16_1 Position */
+#define CAN_NDAT1_NewData16_1_Msk (0xfffful << CAN_NDAT1_NewData16_1_Pos) /*!< CAN_T::NDAT1: NewData16_1 Mask */
+
+#define CAN_NDAT2_NewData32_17_Pos (0) /*!< CAN_T::NDAT2: NewData32_17 Position */
+#define CAN_NDAT2_NewData32_17_Msk (0xfffful << CAN_NDAT2_NewData32_17_Pos) /*!< CAN_T::NDAT2: NewData32_17 Mask */
+
+#define CAN_IPND1_IntPnd16_1_Pos (0) /*!< CAN_T::IPND1: IntPnd16_1 Position */
+#define CAN_IPND1_IntPnd16_1_Msk (0xfffful << CAN_IPND1_IntPnd16_1_Pos) /*!< CAN_T::IPND1: IntPnd16_1 Mask */
+
+#define CAN_IPND2_IntPnd32_17_Pos (0) /*!< CAN_T::IPND2: IntPnd32_17 Position */
+#define CAN_IPND2_IntPnd32_17_Msk (0xfffful << CAN_IPND2_IntPnd32_17_Pos) /*!< CAN_T::IPND2: IntPnd32_17 Mask */
+
+#define CAN_MVLD1_MsgVal16_1_Pos (0) /*!< CAN_T::MVLD1: MsgVal16_1 Position */
+#define CAN_MVLD1_MsgVal16_1_Msk (0xfffful << CAN_MVLD1_MsgVal16_1_Pos) /*!< CAN_T::MVLD1: MsgVal16_1 Mask */
+
+#define CAN_MVLD2_MsgVal32_17_Pos (0) /*!< CAN_T::MVLD2: MsgVal32_17 Position */
+#define CAN_MVLD2_MsgVal32_17_Msk (0xfffful << CAN_MVLD2_MsgVal32_17_Pos) /*!< CAN_T::MVLD2: MsgVal32_17 Mask */
+
+#define CAN_WU_EN_WAKUP_EN_Pos (0) /*!< CAN_T::WU_EN: WAKUP_EN Position */
+#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
+
+#define CAN_WU_STATUS_WAKUP_STS_Pos (0) /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
+#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
+
+/**@}*/ /* CAN_CONST */
+/**@}*/ /* end of CAN register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CAN_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ccap_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ccap_reg.h
new file mode 100644
index 00000000000..3798f50b96e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ccap_reg.h
@@ -0,0 +1,496 @@
+/**************************************************************************//**
+ * @file ccap_reg.h
+ * @version V1.00
+ * @brief CCAP register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CCAP_REG_H__
+#define __CCAP_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup CCAP Camera Capture Interface Controller (CCAP)
+ Memory Mapped Structure for CCAP Controller
+@{ */
+
+
+typedef struct {
+
+
+ /**
+ * @var CCAP_T::CTL
+ * Offset: 0x00 Camera Capture Interface Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CCAPEN |Camera Capture Interface Enable
+ * | | |0 = Camera Capture Interface Disabled.
+ * | | |1 = Camera Capture Interface Enabled.
+ * |[3] |ADDRSW |Packet Buffer Address Switch
+ * | | |0 = Packet buffer address switch Disabled.
+ * | | |1 = Packet buffer address switch Enabled.
+ * |[6] |PKTEN |Packet Output Enable
+ * | | |0 = Packet output Disabled.
+ * | | |1 = Packet output Enabled.
+ * |[7] |MONO |Monochrome CMOS Sensor Select
+ * | | |0 = Color CMOS Sensor.
+ * | | |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled.
+ * |[16] |SHUTTER |Image Capture Interface Automatically Disable The Capture Interface After A Frame Had Been Captured
+ * | | |0 = Shutter Disabled.
+ * | | |1 = Shutter Enabled.
+ * |[20] |UPDATE |Update Register At New Frame
+ * | | |0 = Update register at new frame Disabled.
+ * | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated).
+ * |[24] |VPRST |Capture Interface Reset
+ * | | |0 = Capture interface reset Disabled.
+ * | | |1 = Capture interface reset Enabled.
+ * @var CCAP_T::PAR
+ * Offset: 0x04 Camera Capture Interface Parameter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INFMT |Sensor Input Data Format
+ * | | |0 = YCbCr422.
+ * | | |1 = RGB565.
+ * |[1] |SENTYPE |Sensor Input Type
+ * | | |0 = CCIR601.
+ * | | |1 = CCIR656, VSync & Hsync embedded in the data signal.
+ * |[2:3] |INDATORD |Sensor Input Data Order
+ * | | |If INFMT = 0 (YCbCr),.
+ * | | | Byte 0 1 2 3
+ * | | |00 = Y0 U0 Y1 V0.
+ * | | |01 = Y0 V0 Y1 U0.
+ * | | |10 = U0 Y0 V0 Y1.
+ * | | |11 = V0 Y0 U0 Y1.
+ * | | |If INFMT = 1 (RGB565),.
+ * | | |00 = Byte0[R[4:0] G[5:3]] Byte1[G[2:0] B[4:0]]
+ * | | |01 = Byte0[B[4:0] G[5:3]] Byte1[G[2:0] R[4:0]]
+ * | | |10 = Byte0[G[2:0] B[4:0]] Byte1[R[4:0] G[5:3]]
+ * | | |11 = Byte0[G[2:0] R[4:0]] Byte1[B[4:0] G[5:3]]
+ * |[4:5] |OUTFMT |Image Data Format Output To System Memory
+ * | | |00 = YCbCr422.
+ * | | |01 = Only output Y.
+ * | | |10 = RGB555.
+ * | | |11 = RGB565.
+ * |[6] |RANGE |Scale Input YUV CCIR601 Color Range To Full Range
+ * | | |0 = default.
+ * | | |1 = Scale to full range.
+ * |[8] |PCLKP |Sensor Pixel Clock Polarity
+ * | | |0 = Input video data and signals are latched by falling edge of Pixel Clock.
+ * | | |1 = Input video data and signals are latched by rising edge of Pixel Clock.
+ * |[9] |HSP |Sensor Hsync Polarity
+ * | | |0 = Sync Low.
+ * | | |1 = Sync High.
+ * |[10] |VSP |Sensor Vsync Polarity
+ * | | |0 = Sync Low.
+ * | | |1 = Sync High.
+ * |[18] |FBB |Field By Blank
+ * | | |Hardware will tag field0 or field1 by vertical blanking instead of FIELD flag in CCIR-656 mode.
+ * | | |0 = Field by blank Disabled.
+ * | | |1 = Field by blank Enabled.
+ * @var CCAP_T::INT
+ * Offset: 0x08 Camera Capture Interface Interrupt Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |VINTF |Video Frame End Interrupt
+ * | | |If this bit shows 1, receiving a frame completed.
+ * | | |Write 1 to clear it.
+ * |[1] |MEINTF |Bus Master Transfer Error Interrupt
+ * | | |If this bit shows 1, Transfer Error occurred. Write 1 to clear it.
+ * |[3] |ADDRMINTF |Memory Address Match Interrupt
+ * | | |If this bit shows 1, Memory Address Match Interrupt occurred.
+ * | | |Write 1 to clear it.
+ * |[4] |MDINTF |Motion Detection Output Finish Interrupt
+ * | | |If this bit shows 1, Motion Detection Output Finish Interrupt occurred.
+ * | | |Write 1 to clear it.
+ * |[16] |VIEN |Video Frame End Interrupt Enable
+ * | | |0 = Video frame end interrupt Disabled.
+ * | | |1 = Video frame end interrupt Enabled.
+ * |[17] |MEIEN |System Memory Error Interrupt Enable
+ * | | |0 = System memory error interrupt Disabled.
+ * | | |1 = System memory error interrupt Enabled.
+ * |[19] |ADDRMIEN |Address Match Interrupt Enable
+ * | | |0 = Address match interrupt Disabled.
+ * | | |1 = Address match interrupt Enabled.
+ * @var CCAP_T::POSTERIZE
+ * Offset: 0x0C YUV Component Posterizing Factor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:7] |VCOMP |V Component Posterizing Factor
+ * | | |Final_V_Out = Original_V[7:0] & V_Posterizing_Factor.
+ * |[8:15] |UCOMP |U Component Posterizing Factor
+ * | | |Final_U_Out = Original_U[7:0] & U_Posterizing_Factor.
+ * |[16:23] |YCOMP |Y Component Posterizing Factor
+ * | | |Final_Y_Out = Original_Y[7:0] & Y_Posterizing_Factor.
+ * @var CCAP_T::MD
+ * Offset: 0x10 Motion Detection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MDEN |Motion Detection Enable
+ * | | |0 = CCAP_MD Disabled.
+ * | | |1 = CCAP_MD Enabled.
+ * |[8] |MDBS |Motion Detection Block Size
+ * | | |0 = 16x16.
+ * | | |1 = 8x8.
+ * |[9] |MDSM |Motion Detection Save Mode
+ * | | |0 = 1 bit DIFF + 7 bit Y Differential.
+ * | | |1 = 1 bit DIFF only.
+ * |[10:11] |MDDF |Motion Detection Detect Frequency
+ * | | |00 = Each frame.
+ * | | |01 = Every 2 frame.
+ * | | |10 = Every 3 frame.
+ * | | |11 = Every 4 frame.
+ * |[16:20] |MDTHR |Motion Detection Differential Threshold
+ * @var CCAP_T::MDADDR
+ * Offset: 0x14 Motion Detection Output Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:31] |MDADDR |Motion Detection Output Address Register (Word Alignment)
+ * @var CCAP_T::MDYADDR
+ * Offset: 0x18 Motion Detection Temp Y Output Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:31] |MDYADDR |Motion Detection Temp Y Output Address Register (Word Alignment)
+ * @var CCAP_T::SEPIA
+ * Offset: 0x1C Sepia Effect Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:7] |VCOMP |Define the constant V component while Sepia color effect is turned on.
+ * |[8:15] |UCOMP |Define the constant U component while Sepia color effect is turned on.
+ * @var CCAP_T::CWSP
+ * Offset: 0x20 Cropping Window Starting Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:11] |CWSADDRH |Cropping Window Horizontal Starting Address
+ * |[16:26] |CWSADDRV |Cropping Window Vertical Starting Address
+ * @var CCAP_T::CWS
+ * Offset: 0x24 Cropping Window Size Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:11] |CIWW |Cropping Image Window Width
+ * |[16:26] |CIWH |Cropping Image Window Height
+ * @var CCAP_T::PKTSL
+ * Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:7] |PKTSHML |Packet Scaling Horizontal Factor M (Lower 8-Bit)
+ * | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.
+ * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.
+ * | | |The output image width will be equal to the image width * N/M.
+ * | | |Note: The value of N must be equal to or less than M.
+ * |[8:15] |PKTSHNL |Packet Scaling Horizontal Factor N (Lower 8-Bit)
+ * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
+ * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor.
+ * |[16:23] |PKTSVML |Packet Scaling Vertical Factor M (Lower 8-Bit)
+ * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
+ * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.
+ * | | |The output image width will be equal to the image height * N/M.
+ * | | |Note: The value of N must be equal to or less than M.
+ * |[24:31] |PKTSVNL |Packet Scaling Vertical Factor N (Lower 8-Bit)
+ * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
+ * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor
+ * @var CCAP_T::PLNSL
+ * Offset: 0x2C Planar Scaling Vertical/Horizontal Factor Register (LSB)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:7] |PLNSHML |Planar Scaling Horizontal Factor M (Lower 8-Bit)
+ * | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
+ * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical factor.
+ * | | |The output image width will be equal to the image width * N/M.
+ * | | |Note: The value of N must be equal to or less than M.
+ * |[8:15] |PLNSHNL |Planar Scaling Horizontal Factor N (Lower 8-Bit)
+ * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
+ * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor.
+ * |[16:23] |PLNSVML |Planar Scaling Vertical Factor M (Lower 8-Bit)
+ * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
+ * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical factor.
+ * | | |The output image width will be equal to the image height * N/M.
+ * | | |Note: The value of N must be equal to or less than M.
+ * |[24:31] |PLNSVNL |Planar Scaling Vertical Factor N (Lower 8-Bit)
+ * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
+ * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVNH) to form a 16-bit numerator of vertical factor.
+ * @var CCAP_T::FRCTL
+ * Offset: 0x30 Scaling Frame Rate Factor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:5] |FRM |Scaling Frame Rate Factor M
+ * | | |Specify the denominator part (M) of the frame rate scaling factor.
+ * | | |The output image frame rate will be equal to input image frame rate * (N/M).
+ * | | |Note: The value of N must be equal to or less than M.
+ * |[8:13] |FRN |Scaling Frame Rate Factor N
+ * | | |Specify the denominator part (N) of the frame rate scaling factor.
+ * @var CCAP_T::STRIDE
+ * Offset: 0x34 Frame Output Pixel Stride Width Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:13] |PKTSTRIDE |Packet Frame Output Pixel Stride Width
+ * | | |The output pixel stride size of packet pipe.
+ * |[16:29] |PLNSTRIDE |Planar Frame Output Pixel Stride Width
+ * | | |The output pixel stride size of planar pipe.
+ * @var CCAP_T::FIFOTH
+ * Offset: 0x3C FIFO Threshold Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:3] |PLNVFTH |Planar V FIFO Threshold
+ * |[8:11] |PLNUFTH |Planar U FIFO Threshold
+ * |[16:20] |PLNYFTH |Planar Y FIFO Threshold
+ * |[24:28] |PKTFTH |Packet FIFO Threshold
+ * |[31] |OVF |FIFO Overflow Flag
+ * @var CCAP_T::CMPADDR
+ * Offset: 0x40 Compare Memory Base Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:31] |CMPADDR |Compare Memory Base Address
+ * | | |Word aligns address; ignore the bits [1:0].
+ * @var CCAP_T::LUMA_Y1_THD
+ * Offset: 0x44 Luminance Y8 to Y1 Threshold Value Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :-----------: | :---- |
+ * |[0:8] |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value
+ * | | |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion.
+ * @var CCAP_T::PKTSM
+ * Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:7] |PKTSHMH |Packet Scaling Horizontal Factor M (Higher 8-Bit)
+ * | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
+ * | | |Please refer to the register CCAP_PKTSL?for the detailed operation.
+ * |[8:15] |PKTSHNH |Packet Scaling Horizontal Factor N (Higher 8-Bit)
+ * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
+ * | | |Please refer to the register CCAP_PKTSL for the detailed operation.
+ * |[16:23] |PKTSVMH |Packet Scaling Vertical Factor M (Higher 8-Bit)
+ * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
+ * | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers.
+ * |[24:31] |PKTSVNH |Packet Scaling Vertical Factor N (Higher 8-Bit)
+ * | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
+ * | | |Please refer to the register CCAP_PKTSL?to check the cooperation between these two registers.
+ * @var CCAP_T::PKTBA0
+ * Offset: 0x60 System Memory Packet Base Address 0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0:31] |BASEADDR |System Memory Packet Base Address 0
+ * | | |Word aligns address; ignore the bits [1:0].
+ */
+ __IO uint32_t CTL;
+ __IO uint32_t PAR;
+ __IO uint32_t INT;
+ __IO uint32_t POSTERIZE;
+ __IO uint32_t MD;
+ __IO uint32_t MDADDR;
+ __IO uint32_t MDYADDR;
+ __IO uint32_t SEPIA;
+ __IO uint32_t CWSP;
+ __IO uint32_t CWS;
+ __IO uint32_t PKTSL;
+ __IO uint32_t PLNSL;
+ __IO uint32_t FRCTL;
+ __IO uint32_t STRIDE;
+ /// @cond HIDDEN_SYMBOLS
+ uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t FIFOTH;
+ __IO uint32_t CMPADDR;
+ __IO uint32_t LUMA_Y1_THD;
+ __IO uint32_t PKTSM;
+ /// @cond HIDDEN_SYMBOLS
+ uint32_t RESERVE2[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t PKTBA0;
+} CCAP_T;
+
+/**
+ @addtogroup CCAP_CONST CCAP Bit Field Definition
+ Constant Definitions for CCAP Controller
+@{ */
+
+#define CCAP_CTL_CCAPEN_Pos (0) /*!< CCAP_T::CTL: CCAPEN Position */
+#define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) /*!< CCAP_T::CTL: CCAPEN Mask */
+
+#define CCAP_CTL_ADDRSW_Pos (3) /*!< CCAP_T::CTL: ADDRSW Position */
+#define CCAP_CTL_ADDRSW_Msk (0x1ul << CCAP_CTL_ADDRSW_Pos) /*!< CCAP_T::CTL: ADDRSW Mask */
+
+#define CCAP_CTL_PLNEN_Pos (5) /*!< CCAP_T::CTL: PLNEN Position */
+#define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos) /*!< CCAP_T::CTL: PLNEN Mask */
+
+#define CCAP_CTL_PKTEN_Pos (6) /*!< CCAP_T::CTL: PKTEN Position */
+#define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) /*!< CCAP_T::CTL: PKTEN Mask */
+
+#define CCAP_CTL_MONO_Pos (7) /*!< CCAP_T::CTL: MONO Position */
+#define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) /*!< CCAP_T::CTL: MONO Mask */
+
+#define CCAP_CTL_SHUTTER_Pos (16) /*!< CCAP_T::CTL: SHUTTER Position */
+#define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) /*!< CCAP_T::CTL: SHUTTER Mask */
+
+#define CCAP_CTL_MY4_SWAP_Pos (17) /*!< CCAP_T::CTL: MY4_SWAP Position */
+#define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) /*!< CCAP_T::CTL: MY4_SWAP Mask */
+
+#define CCAP_CTL_MY8_MY4_Pos (18) /*!< CCAP_T::CTL: MY8_MY4 Position */
+#define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) /*!< CCAP_T::CTL: MY8_MY4 Mask */
+
+#define CCAP_CTL_Luma_Y_One_Pos (19) /*!< CCAP_T::CTL: Luma_Y_One Position */
+#define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) /*!< CCAP_T::CTL: Luma_Y_One Mask */
+
+#define CCAP_CTL_UPDATE_Pos (20) /*!< CCAP_T::CTL: UPDATE Position */
+#define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) /*!< CCAP_T::CTL: UPDATE Mask */
+
+#define CCAP_CTL_VPRST_Pos (24) /*!< CCAP_T::CTL: VPRST Position */
+#define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) /*!< CCAP_T::CTL: VPRST Mask */
+
+#define CCAP_PAR_INFMT_Pos (0) /*!< CCAP_T::PAR: INFMT Position */
+#define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) /*!< CCAP_T::PAR: INFMT Mask */
+
+#define CCAP_PAR_SENTYPE_Pos (1) /*!< CCAP_T::PAR: SENTYPE Position */
+#define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) /*!< CCAP_T::PAR: SENTYPE Mask */
+
+#define CCAP_PAR_INDATORD_Pos (2) /*!< CCAP_T::PAR: INDATORD Position */
+#define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) /*!< CCAP_T::PAR: INDATORD Mask */
+
+#define CCAP_PAR_OUTFMT_Pos (4) /*!< CCAP_T::PAR: OUTFMT Position */
+#define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */
+
+#define CCAP_PAR_RANGE_Pos (6) /*!< CCAP_T::PAR: RANGE Position */
+#define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) /*!< CCAP_T::PAR: RANGE Mask */
+
+#define CCAP_PAR_PLNFMT_Pos (7) /*!< CCAP_T::PAR: PLNFMT Position */
+#define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_PLNFMT_Pos) /*!< CCAP_T::PAR: PLNFMT Mask */
+
+#define CCAP_PAR_PCLKP_Pos (8) /*!< CCAP_T::PAR: PCLKP Position */
+#define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) /*!< CCAP_T::PAR: PCLKP Mask */
+
+#define CCAP_PAR_HSP_Pos (9) /*!< CCAP_T::PAR: HSP Position */
+#define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) /*!< CCAP_T::PAR: HSP Mask */
+
+#define CCAP_PAR_VSP_Pos (10) /*!< CCAP_T::PAR: VSP Position */
+#define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) /*!< CCAP_T::PAR: VSP Mask */
+
+#define CCAP_PAR_COLORCTL_Pos (11) /*!< CCAP_T::PAR: COLORCTL Position */
+#define CCAP_PAR_COLORCTL_Msk (0x3ul << CCAP_PAR_COLORCTL_Pos) /*!< CCAP_T::PAR: COLORCTL Mask */
+
+#define CCAP_PAR_FBB_Pos (18) /*!< CCAP_T::PAR: FBB Position */
+#define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) /*!< CCAP_T::PAR: FBB Mask */
+
+#define CCAP_INT_VINTF_Pos (0) /*!< CCAP_T::INT: VINTF Position */
+#define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) /*!< CCAP_T::INT: VINTF Mask */
+
+#define CCAP_INT_MEINTF_Pos (1) /*!< CCAP_T::INT: MEINTF Position */
+#define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) /*!< CCAP_T::INT: MEINTF Mask */
+
+#define CCAP_INT_ADDRMINTF_Pos (3) /*!< CCAP_T::INT: ADDRMINTF Position */
+#define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) /*!< CCAP_T::INT: ADDRMINTF Mask */
+
+#define CCAP_INT_MDINTF_Pos (4) /*!< CCAP_T::INT: MDINTF Position */
+#define CCAP_INT_MDINTF_Msk (0x1ul << CCAP_INT_MDINTF_Pos) /*!< CCAP_T::INT: MDINTF Mask */
+
+#define CCAP_INT_VIEN_Pos (16) /*!< CCAP_T::INT: VIEN Position */
+#define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) /*!< CCAP_T::INT: VIEN Mask */
+
+#define CCAP_INT_MEIEN_Pos (17) /*!< CCAP_T::INT: MEIEN Position */
+#define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) /*!< CCAP_T::INT: MEIEN Mask */
+
+#define CCAP_INT_ADDRMIEN_Pos (19) /*!< CCAP_T::INT: ADDRMIEN Position */
+#define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) /*!< CCAP_T::INT: ADDRMIEN Mask */
+
+#define CCAP_CWSP_CWSADDRH_Pos (0) /*!< CCAP_T::CWSP: CWSADDRH Position */
+#define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) /*!< CCAP_T::CWSP: CWSADDRH Mask */
+
+#define CCAP_CWSP_CWSADDRV_Pos (16) /*!< CCAP_T::CWSP: CWSADDRV Position */
+#define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) /*!< CCAP_T::CWSP: CWSADDRV Mask */
+
+#define CCAP_CWS_CWW_Pos (0) /*!< CCAP_T::CWS: CWW Position */
+#define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) /*!< CCAP_T::CWS: CWW Mask */
+#define CCAP_CWS_CWH_Pos (16) /*!< CCAP_T::CWS: CIWH Position */
+#define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) /*!< CCAP_T::CWS: CIWH Mask */
+
+#define CCAP_PKTSL_PKTSHML_Pos (0) /*!< CCAP_T::PKTSL: PKTSHML Position */
+#define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) /*!< CCAP_T::PKTSL: PKTSHML Mask */
+
+#define CCAP_PKTSL_PKTSHNL_Pos (8) /*!< CCAP_T::PKTSL: PKTSHNL Position */
+#define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) /*!< CCAP_T::PKTSL: PKTSHNL Mask */
+
+#define CCAP_PKTSL_PKTSVML_Pos (16) /*!< CCAP_T::PKTSL: PKTSVML Position */
+#define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) /*!< CCAP_T::PKTSL: PKTSVML Mask */
+
+#define CCAP_PKTSL_PKTSVNL_Pos (24) /*!< CCAP_T::PKTSL: PKTSVNL Position */
+#define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) /*!< CCAP_T::PKTSL: PKTSVNL Mask */
+
+#define CCAP_FRCTL_FRM_Pos (0) /*!< CCAP_T::FRCTL: FRM Position */
+#define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) /*!< CCAP_T::FRCTL: FRM Mask */
+
+#define CCAP_FRCTL_FRN_Pos (8) /*!< CCAP_T::FRCTL: FRN Position */
+#define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) /*!< CCAP_T::FRCTL: FRN Mask */
+
+#define CCAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CCAP_T::STRIDE: PKTSTRIDE Position */
+#define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) /*!< CCAP_T::STRIDE: PKTSTRIDE Mask */
+
+#define CCAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CCAP_T::STRIDE: PLNSTRIDE Position */
+#define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos) /*!< CCAP_T::STRIDE: PLNSTRIDE Mask */
+
+#define CCAP_FIFOTH_PLNVFTH_Pos (0) /*!< CCAP_T::FIFOTH: PLNVFTH Position */
+#define CCAP_FIFOTH_PLNVFTH_Msk (0xful << CCAP_FIFOTH_PLNVFTH_Pos) /*!< CCAP_T::FIFOTH: PLNVFTH Mask */
+
+#define CCAP_FIFOTH_PLNUFTH_Pos (8) /*!< CCAP_T::FIFOTH: PLNUFTH Position */
+#define CCAP_FIFOTH_PLNUFTH_Msk (0xful << CCAP_FIFOTH_PLNUFTH_Pos) /*!< CCAP_T::FIFOTH: PLNUFTH Mask */
+
+#define CCAP_FIFOTH_PLNYFTH_Pos (16) /*!< CCAP_T::FIFOTH: PLNYFTH Position */
+#define CCAP_FIFOTH_PLNYFTH_Msk (0x1ful << CCAP_FIFOTH_PLNYFTH_Pos) /*!< CCAP_T::FIFOTH: PLNYFTH Mask */
+
+#define CCAP_FIFOTH_PKTFTH_Pos (24) /*!< CCAP_T::FIFOTH: PKTFTH Position */
+#define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) /*!< CCAP_T::FIFOTH: PKTFTH Mask */
+
+#define CCAP_FIFOTH_OVF_Pos (31) /*!< CCAP_T::FIFOTH: OVF Position */
+#define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) /*!< CCAP_T::FIFOTH: OVF Mask */
+
+#define CCAP_CMPADDR_CMPADDR_Pos (0) /*!< CCAP_T::CMPADDR: CMPADDR Position */
+#define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) /*!< CCAP_T::CMPADDR: CMPADDR Mask */
+
+#define CCAP_PKTSM_PKTSHMH_Pos (0) /*!< CCAP_T::PKTSM: PKTSHMH Position */
+#define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) /*!< CCAP_T::PKTSM: PKTSHMH Mask */
+
+#define CCAP_PKTSM_PKTSHNH_Pos (8) /*!< CCAP_T::PKTSM: PKTSHNH Position */
+#define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) /*!< CCAP_T::PKTSM: PKTSHNH Mask */
+
+#define CCAP_PKTSM_PKTSVMH_Pos (16) /*!< CCAP_T::PKTSM: PKTSVMH Position */
+#define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) /*!< CCAP_T::PKTSM: PKTSVMH Mask */
+
+#define CCAP_PKTSM_PKTSVNH_Pos (24) /*!< CCAP_T::PKTSM: PKTSVNH Position */
+#define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) /*!< CCAP_T::PKTSM: PKTSVNH Mask */
+
+#define CCAP_PKTBA0_BASEADDR_Pos (0) /*!< CCAP_T::PKTBA0: BASEADDR Position */
+#define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /*!< CCAP_T::PKTBA0: BASEADDR Mask */
+
+/**@}*/ /* CCAP_CONST */
+/**@}*/ /* end of CCAP register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CCAP_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/clk_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/clk_reg.h
new file mode 100644
index 00000000000..68016d805c5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/clk_reg.h
@@ -0,0 +1,1698 @@
+/**************************************************************************//**
+ * @file clk_reg.h
+ * @version V1.00
+ * @brief CLK register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CLK_REG_H__
+#define __CLK_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup CLK System Clock Controller(CLK)
+ Memory Mapped Structure for CLK Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var CLK_T::PWRCTL
+ * Offset: 0x00 System Power-down Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXTEN |HXT Enable Bit (Write Protect)
+ * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26]
+ * | | |When the default clock source is from HXT, this bit is set to 1 automatically.
+ * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled.
+ * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |LXTEN |LXT Enable Bit (Write Protect)
+ * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled.
+ * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |HIRCEN |HIRC Enable Bit (Write Protect)
+ * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled.
+ * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |LIRCEN |LIRC Enable Bit (Write Protect)
+ * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled.
+ * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect)
+ * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
+ * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC).
+ * | | |0 = Clock cycles delay Disabled.
+ * | | |1 = Clock cycles delay Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
+ * | | |0 = Power-down mode wake-up interrupt Disabled.
+ * | | |1 = Power-down mode wake-up interrupt Enabled.
+ * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status
+ * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
+ * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
+ * | | |Note1: Write 1 to clear the bit to 0.
+ * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
+ * |[7] |PDEN |System Power-down Enable (Write Protect)
+ * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
+ * | | |When chip wakes up from Power-down mode, this bit is auto cleared
+ * | | |Users need to set this bit again for next Power-down.
+ * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
+ * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection
+ * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
+ * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI.
+ * | | |1 = Chip enters Power-down mode after CPU sleep command WFI.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally
+ * | | |If gain control is enabled, crystal will consume more power than gain control off.
+ * | | |00 = HXT frequency is lower than from 8 MHz.
+ * | | |01 = HXT frequency is from 8 MHz to 12 MHz.
+ * | | |10 = HXT frequency is from 12 MHz to 16 MHz.
+ * | | |11 = HXT frequency is higher than 16 MHz.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Select INV type.
+ * | | |1 = Select GM type.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = HXT Crystal TURBO mode disabled.
+ * | | |1 = HXT Crystal TURBO mode enabled.
+ * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect)
+ * | | |00 = HIRC stable count is 64 clocks.
+ * | | |01 = HIRC stable count is 24 clocks.
+ * | | |others = Reserved.
+ * |[18] |HIRCEN |HIRC48M Enable Bit (Write Protect)
+ * | | |0 = 48 MHz internal high speed RC oscillator (HIRC) Disabled.
+ * | | |1 = 48 MHz internal high speed RC oscillator (HIRC) Enabled.
+ * @var CLK_T::AHBCLK
+ * Offset: 0x04 AHB Devices Clock Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit
+ * | | |0 = PDMA peripheral clock Disabled.
+ * | | |1 = PDMA peripheral clock Enabled.
+ * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit
+ * | | |0 = Flash ISP peripheral clock Disabled.
+ * | | |1 = Flash ISP peripheral clock Enabled.
+ * |[3] |EBICKEN |EBI Controller Clock Enable Bit
+ * | | |0 = EBI peripheral clock Disabled.
+ * | | |1 = EBI peripheral clock Enabled.
+ * |[5] |EMACCKEN |Ethernet Controller Clock Enable Bit
+ * | | |0 = Ethernet Controller engine clock Disabled.
+ * | | |1 = Ethernet Controller engine clock Enabled.
+ * |[6] |SDH0CKEN |SD0 Controller Clock Enable Bit
+ * | | |0 = SD0 engine clock Disabled.
+ * | | |1 = SD0 engine clock Enabled.
+ * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit
+ * | | |0 = CRC peripheral clock Disabled.
+ * | | |1 = CRC peripheral clock Enabled.
+ * |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit
+ * | | |0 = HSUSB device controller's clock Disabled.
+ * | | |1 = HSUSB device controller's clock Enabled.
+ * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit
+ * | | |0 = Cryptographic Accelerator clock Disabled.
+ * | | |1 = Cryptographic Accelerator clock Enabled.
+ * |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit
+ * | | |0 = SPIM controller clock Disabled.
+ * | | |1 = SPIM controller clock Enabled.
+ * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode
+ * | | |0 = FMC clock Disabled when chip is under IDLE mode.
+ * | | |1 = FMC clock Enabled when chip is under IDLE mode.
+ * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit
+ * | | |0 = USB HOST peripheral clock Disabled.
+ * | | |1 = USB HOST peripheral clock Enabled.
+ * |[17] |SDH1CKEN |SD1 Controller Clock Enable Bit
+ * | | |0 = SD1 engine clock Disabled.
+ * | | |1 = SD1 engine clock Enabled.
+ * @var CLK_T::APBCLK0
+ * Offset: 0x08 APB Devices Clock Enable Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect)
+ * | | |0 = Watchdog timer clock Disabled.
+ * | | |1 = Watchdog timer clock Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit
+ * | | |This bit is used to control the RTC APB clock only
+ * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8])
+ * | | |It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |0 = RTC clock Disabled.
+ * | | |1 = RTC clock Enabled.
+ * |[2] |TMR0CKEN |Timer0 Clock Enable Bit
+ * | | |0 = Timer0 clock Disabled.
+ * | | |1 = Timer0 clock Enabled.
+ * |[3] |TMR1CKEN |Timer1 Clock Enable Bit
+ * | | |0 = Timer1 clock Disabled.
+ * | | |1 = Timer1 clock Enabled.
+ * |[4] |TMR2CKEN |Timer2 Clock Enable Bit
+ * | | |0 = Timer2 clock Disabled.
+ * | | |1 = Timer2 clock Enabled.
+ * |[5] |TMR3CKEN |Timer3 Clock Enable Bit
+ * | | |0 = Timer3 clock Disabled.
+ * | | |1 = Timer3 clock Enabled.
+ * |[6] |CLKOCKEN |CLKO Clock Enable Bit
+ * | | |0 = CLKO clock Disabled.
+ * | | |1 = CLKO clock Enabled.
+ * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
+ * | | |0 = Analog comparator 0/1 clock Disabled.
+ * | | |1 = Analog comparator 0/1 clock Enabled.
+ * |[8] |I2C0CKEN |I2C0 Clock Enable Bit
+ * | | |0 = I2C0 clock Disabled.
+ * | | |1 = I2C0 clock Enabled.
+ * |[9] |I2C1CKEN |I2C1 Clock Enable Bit
+ * | | |0 = I2C1 clock Disabled.
+ * | | |1 = I2C1 clock Enabled.
+ * |[10] |I2C2CKEN |I2C2 Clock Enable Bit
+ * | | |0 = I2C2 clock Disabled.
+ * | | |1 = I2C2 clock Enabled.
+ * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit
+ * | | |0 = QSPI0 clock Disabled.
+ * | | |1 = QSPI0 clock Enabled.
+ * |[13] |SPI0CKEN |SPI0 Clock Enable Bit
+ * | | |0 = SPI0 clock Disabled.
+ * | | |1 = SPI0 clock Enabled.
+ * |[14] |SPI1CKEN |SPI1 Clock Enable Bit
+ * | | |0 = SPI1 clock Disabled.
+ * | | |1 = SPI1 clock Enabled.
+ * |[15] |SPI2CKEN |SPI2 Clock Enable Bit
+ * | | |0 = SPI2 clock Disabled.
+ * | | |1 = SPI2 clock Enabled.
+ * |[16] |UART0CKEN |UART0 Clock Enable Bit
+ * | | |0 = UART0 clock Disabled.
+ * | | |1 = UART0 clock Enabled.
+ * |[17] |UART1CKEN |UART1 Clock Enable Bit
+ * | | |0 = UART1 clock Disabled.
+ * | | |1 = UART1 clock Enabled.
+ * |[18] |UART2CKEN |UART2 Clock Enable Bit
+ * | | |0 = UART2 clock Disabled.
+ * | | |1 = UART2 clock Enabled.
+ * |[19] |UART3CKEN |UART3 Clock Enable Bit
+ * | | |0 = UART3 clock Disabled.
+ * | | |1 = UART3 clock Enabled.
+ * |[20] |UART4CKEN |UART4 Clock Enable Bit
+ * | | |0 = UART4 clock Disabled.
+ * | | |1 = UART4 clock Enabled.
+ * |[21] |UART5CKEN |UART5 Clock Enable Bit
+ * | | |0 = UART5 clock Disabled.
+ * | | |1 = UART5 clock Enabled.
+ * |[24] |CAN0CKEN |CAN0 Clock Enable Bit
+ * | | |0 = CAN0 clock Disabled.
+ * | | |1 = CAN0 clock Enabled.
+ * |[25] |CAN1CKEN |CAN1 Clock Enable Bit
+ * | | |0 = CAN1 clock Disabled.
+ * | | |1 = CAN1 clock Enabled.
+ * |[26] |OTGCKEN |USB OTG Clock Enable Bit
+ * | | |0 = USB OTG clock Disabled.
+ * | | |1 = USB OTG clock Enabled.
+ * |[27] |USBDCKEN |USB Device Clock Enable Bit
+ * | | |0 = USB Device clock Disabled.
+ * | | |1 = USB Device clock Enabled.
+ * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit
+ * | | |0 = EADC clock Disabled.
+ * | | |1 = EADC clock Enabled.
+ * |[29] |I2S0CKEN |I2S0 Clock Enable Bit
+ * | | |0 = I2S0 Clock Disabled.
+ * | | |1 = I2S0 Clock Enabled.
+ * |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit
+ * | | |0 = HSUSB OTG clock Disabled.
+ * | | |1 = HSUSB OTG clock Enabled.
+ * @var CLK_T::APBCLK1
+ * Offset: 0x0C APB Devices Clock Enable Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SC0CKEN |SC0 Clock Enable Bit
+ * | | |0 = SC0 clock Disabled.
+ * | | |1 = SC0 clock Enabled.
+ * |[1] |SC1CKEN |SC1 Clock Enable Bit
+ * | | |0 = SC1 clock Disabled.
+ * | | |1 = SC1 clock Enabled.
+ * |[2] |SC2CKEN |SC2 Clock Enable Bit
+ * | | |0 = SC2 clock Disabled.
+ * | | |1 = SC2 clock Enabled.
+ * |[6] |SPI3CKEN |SPI3 Clock Enable Bit
+ * | | |0 = SPI3 clock Disabled.
+ * | | |1 = SPI3 clock Enabled.
+ * |[8] |USCI0CKEN |USCI0 Clock Enable Bit
+ * | | |0 = USCI0 clock Disabled.
+ * | | |1 = USCI0 clock Enabled.
+ * |[9] |USCI1CKEN |USCI1 Clock Enable Bit
+ * | | |0 = USCI1 clock Disabled.
+ * | | |1 = USCI1 clock Enabled.
+ * |[12] |DACCKEN |DAC Clock Enable Bit
+ * | | |0 = DAC clock Disabled.
+ * | | |1 = DAC clock Enabled.
+ * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit
+ * | | |0 = EPWM0 clock Disabled.
+ * | | |1 = EPWM0 clock Enabled.
+ * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit
+ * | | |0 = EPWM1 clock Disabled.
+ * | | |1 = EPWM1 clock Enabled.
+ * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit
+ * | | |0 = BPWM0 clock Disabled.
+ * | | |1 = BPWM0 clock Enabled.
+ * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit
+ * | | |0 = BPWM1 clock Disabled.
+ * | | |1 = BPWM1 clock Enabled.
+ * |[22] |QEI0CKEN |QEI0 Clock Enable Bit
+ * | | |0 = QEI0 clock Disabled.
+ * | | |1 = QEI0 clock Enabled.
+ * |[23] |QEI1CKEN |QEI1 Clock Enable Bit
+ * | | |0 = QEI1 clock Disabled.
+ * | | |1 = QEI1 clock Enabled.
+ * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit
+ * | | |0 = ECAP0 clock Disabled.
+ * | | |1 = ECAP0 clock Enabled.
+ * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit
+ * | | |0 = ECAP1 clock Disabled.
+ * | | |1 = ECAP1 clock Enabled.
+ * |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Bit
+ * | | |0 = OPA clock Disabled.
+ * | | |1 = OPA clock Enabled.
+ * @var CLK_T::CLKSEL0
+ * Offset: 0x10 Clock Source Select Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
+ * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
+ * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset
+ * | | |Therefore the default value is either 000b or 111b.
+ * | | |000 = Clock source from HXT.
+ * | | |001 = Clock source from LXT.
+ * | | |010 = Clock source from PLL.
+ * | | |011 = Clock source from LIRC.
+ * | | |111 = Clock source from HIRC.
+ * | | |Other = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect)
+ * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
+ * | | |000 = Clock source from HXT.
+ * | | |001 = Clock source from LXT.
+ * | | |010 = Clock source from HXT/2.
+ * | | |011 = Clock source from HCLK/2.
+ * | | |111 = Clock source from HIRC/2.
+ * | | |Note: if SysTick clock source is not from HCLK (i.e
+ * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8] |USBSEL |USB Clock Source Selection (Write Protect)
+ * | | |0 = Clock source from RC48M.
+ * | | |1 = Clock source from PLL.
+ * |[21:20] |SDH0SEL |SD0 Engine Clock Source Selection (Write Protect)
+ * | | |00 = Clock source from HXT clock.
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from HCLK.
+ * | | |11 = Clock source from HIRC clock.
+ * |[23:22] |SDH1SEL |SD1 Engine Clock Source Selection (Write Protect)
+ * | | |00 = Clock source from HXT clock.
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from HCLK.
+ * | | |11 = Clock source from HIRC clock.
+ * @var CLK_T::CLKSEL1
+ * Offset: 0x14 Clock Source Select Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
+ * | | |00 = Reserved.
+ * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |10 = Clock source from HCLK/2048.
+ * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |010 = Clock source from PCLK0.
+ * | | |011 = Clock source from external clock TM0 pin.
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * | | |Others = Reserved.
+ * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |010 = Clock source from PCLK0.
+ * | | |011 = Clock source from external clock TM1 pin.
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * | | |Others = Reserved.
+ * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |010 = Clock source from PCLK1.
+ * | | |011 = Clock source from external clock TM2 pin.
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * | | |Others = Reserved.
+ * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |010 = Clock source from PCLK1.
+ * | | |011 = Clock source from external clock TM3 pin.
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * | | |Others = Reserved.
+ * |[25:24] |UART0SEL |UART0 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[27:26] |UART1SEL |UART1 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |10 = Clock source from HCLK.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection
+ * | | |10 = Clock source from HCLK/2048.
+ * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |Others = Reserved.
+ * @var CLK_T::CLKSEL2
+ * Offset: 0x18 Clock Source Select Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |EPWM0SEL |EPWM0 Clock Source Selection
+ * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL.
+ * | | |0 = Clock source from PLL.
+ * | | |1 = Clock source from PCLK0.
+ * |[1] |EPWM1SEL |EPWM1 Clock Source Selection
+ * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL.
+ * | | |0 = Clock source from PLL.
+ * | | |1 = Clock source from PCLK1.
+ * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[5:4] |SPI0SEL |SPI0 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK1.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[7:6] |SPI1SEL |SPI1 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[8] |BPWM0SEL |BPWM0 Clock Source Selection
+ * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL.
+ * | | |0 = Clock source from PLL.
+ * | | |1 = Clock source from PCLK0.
+ * |[9] |BPWM1SEL |BPWM1 Clock Source Selection
+ * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL.
+ * | | |0 = Clock source from PLL.
+ * | | |1 = Clock source from PCLK1.
+ * |[11:10] |SPI2SEL |SPI2 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK1.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[13:12] |SPI3SEL |SPI3 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * @var CLK_T::CLKSEL3
+ * Offset: 0x1C Clock Source Select Control Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |SC0SEL |SC0 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[3:2] |SC1SEL |SC0 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK1.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[5:4] |SC2SEL |SC2 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[8] |RTCSEL |RTC Clock Source Selection
+ * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * |[17:16] |I2S0SEL |I2S0 Clock Source Selection
+ * | | |00 = Clock source from HXT clock.
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from PCLK.
+ * | | |11 = Clock source from HIRC clock.
+ * |[25:24] |UART2SEL |UART2 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[27:26] |UART3SEL |UART3 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[29:28] |UART4SEL |UART4 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[31:30] |UART5SEL |UART5 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * @var CLK_T::CLKDIV0
+ * Offset: 0x20 Clock Divider Number Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
+ * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
+ * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock
+ * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).
+ * |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source
+ * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1).
+ * |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source
+ * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1).
+ * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source
+ * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
+ * |[31:24] |SDH0DIV |SD0 Clock Divide Number From SD0 Clock Source
+ * | | |SD0 clock frequency = (SD0 clock source frequency) / (SDH0DIV + 1).
+ * @var CLK_T::CLKDIV1
+ * Offset: 0x24 Clock Divider Number Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source
+ * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
+ * |[15:8] |SC1DIV |SC1 Clock Divide Number From SC1 Clock Source
+ * | | |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1).
+ * |[23:16] |SC2DIV |SC2 Clock Divide Number From SC2 Clock Source
+ * | | |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1).
+ * @var CLK_T::CLKDIV3
+ * Offset: 0x2C Clock Divider Number Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |EMACDIV |Ethernet Clock Divide Number Form HCLK
+ * | | |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1).
+ * |[31:24] |SDH1DIV |SD1 Clock Divide Number From SD1 Clock Source
+ * | | |SD1 clock frequency = (SD1 clock source frequency) / (SDH1DIV + 1).
+ * @var CLK_T::CLKDIV4
+ * Offset: 0x30 Clock Divider Number Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source
+ * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1).
+ * |[7:4] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source
+ * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1).
+ * |[11:8] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source
+ * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1).
+ * |[15:12] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source
+ * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1).
+ * @var CLK_T::PCLKDIV
+ * Offset: 0x34 APB Clock Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |APB0DIV |APB0 Clock Divider
+ * | | |APB0 clock can be divided from HCLK
+ * | | |000: PCLK0 = HCLK.
+ * | | |001: PCLK0 = 1/2 HCLK.
+ * | | |010: PCLK0 = 1/4 HCLK.
+ * | | |011: PCLK0 = 1/8 HCLK.
+ * | | |100: PCLK0 = 1/16 HCLK.
+ * | | |Others: Reserved.
+ * |[6:4] |APB1DIV |APB1 Clock Divider
+ * | | |APB1 clock can be divided from HCLK
+ * | | |000: PCLK1 = HCLK.
+ * | | |001: PCLK1 = 1/2 HCLK.
+ * | | |010: PCLK1 = 1/4 HCLK.
+ * | | |011: PCLK1 = 1/8 HCLK.
+ * | | |100: PCLK1 = 1/16 HCLK.
+ * | | |Others: Reserved.
+ * @var CLK_T::PLLCTL
+ * Offset: 0x40 PLL Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect)
+ * | | |Refer to the formulas below the table.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[13:9] |INDIV |PLL Input Divider Control (Write Protect)
+ * | | |Refer to the formulas below the table.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect)
+ * | | |Refer to the formulas below the table.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[16] |PD |Power-down Mode (Write Protect)
+ * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
+ * | | |0 = PLL is in normal mode.
+ * | | |1 = PLL is in Power-down mode (default).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[17] |BP |PLL Bypass Control (Write Protect)
+ * | | |0 = PLL is in normal mode (default).
+ * | | |1 = PLL clock output is same as PLL input clock FIN.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect)
+ * | | |0 = PLL FOUT Enabled.
+ * | | |1 = PLL FOUT is fixed low.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect)
+ * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT).
+ * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect)
+ * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz).
+ * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var CLK_T::STATUS
+ * Offset: 0x50 Clock Status Monitor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only)
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled.
+ * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only)
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled.
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled.
+ * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)
+ * | | |0 = Internal PLL clock is not stable or disabled.
+ * | | |1 = Internal PLL clock is stable and enabled.
+ * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only)
+ * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled.
+ * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled.
+ * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only)
+ * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled.
+ * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled.
+ * | | |Note: This bit is read only.
+ * |[6] |HIRC48MSTB|HIRC 48MHz Clock Source Stable Flag (Read Only)
+ * | | |0 = 48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled.
+ * | | |1 = 48 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled.
+ * | | |Note: This bit is read only.
+ * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only)
+ * | | |This bit is updated when software switches system clock source
+ * | | |If switch target clock is stable, this bit will be set to 0
+ * | | |If switch target clock is not stable, this bit will be set to 1.
+ * | | |0 = Clock switching success.
+ * | | |1 = Clock switching failure.
+ * | | |Note: Write 1 to clear the bit to 0.
+ * @var CLK_T::CLKOCTL
+ * Offset: 0x60 Clock Output Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |FREQSEL |Clock Output Frequency Selection
+ * | | |The formula of output frequency is
+ * | | |Fout = Fin/2(N+1).
+ * | | |Fin is the input clock frequency.
+ * | | |Fout is the frequency of divider output clock.
+ * | | |N is the 4-bit value of FREQSEL[3:0].
+ * |[4] |CLKOEN |Clock Output Enable Bit
+ * | | |0 = Clock Output function Disabled.
+ * | | |1 = Clock Output function Enabled.
+ * |[5] |DIV1EN |Clock Output Divide One Enable Bit
+ * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL.
+ * | | |1 = Clock Output will output clock with source frequency.
+ * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit
+ * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled.
+ * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled.
+ * @var CLK_T::CLKDCTL
+ * Offset: 0x70 Clock Fail Detector Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled.
+ * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled.
+ * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled.
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled.
+ * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled.
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled.
+ * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled.
+ * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled.
+ * @var CLK_T::CLKDSTS
+ * Offset: 0x74 Clock Fail Detector Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops.
+ * | | |Note: Write 1 to clear the bit to 0.
+ * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal.
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops.
+ * | | |Note: Write 1 to clear the bit to 0.
+ * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal.
+ * | | |Note: Write 1 to clear the bit to 0.
+ * @var CLK_T::CDUPB
+ * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value
+ * | | |The bits define the maximum value of frequency range detector window.
+ * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
+ * @var CLK_T::CDLOWB
+ * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value
+ * | | |The bits define the minimum value of frequency range detector window.
+ * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
+ * @var CLK_T::PMUCTL
+ * Offset: 0x90 Power Manager Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.
+ * | | |000 = Power-down mode is selected. (PD)
+ * | | |001 = Low leakage Power-down mode is selected (LLPD).
+ * | | |010 =Fast wake-up Power-down mode is selected (FWPD).
+ * | | |011 = Reserved.
+ * | | |100 = Standby Power-down mode 0 is selected (SPD0) (SRAM retention).
+ * | | |101 = Standby Power-down mode 1 is selected (SPD1).
+ * | | |110 = Deep Power-down mode is selected (DPD).
+ * | | |111 = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |DPDHOLDEN |Deep-Power-Down Mode GPIO Hold Enable
+ * | | |0 = When GPIO enters deep power-down mode, all I/O status are tri-state.
+ * | | |1 = When GPIO enters deep power-down mode, all I/O status are hold to keep normal operating status.
+ * | | | After chip was waked up from deep power-down mode, the I/O are still keep hold status until user set CLK_IOPDCTL[0]
+ * | | | to release I/O hold status.
+ * |[8] |WKTMREN |Wake-up Timer Enable (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Wake-up timer disable at DPD/SPD mode.
+ * | | |1 = Wake-up timer enabled at DPD/SPD mode.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode.
+ * | | |000 = Time-out interval is 128 OSC10K clocks (12.8 ms).
+ * | | |001 = Time-out interval is 256 OSC10K clocks (25.6 ms).
+ * | | |010 = Time-out interval is 512 OSC10K clocks (51.2 ms).
+ * | | |011 = Time-out interval is 1024 OSC10K clocks (102.4ms).
+ * | | |100 = Time-out interval is 4096 OSC10K clocks (409.6ms).
+ * | | |101 = Time-out interval is 8192 OSC10K clocks (819.2ms).
+ * | | |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms).
+ * | | |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |00 = Wake-up pin disable at Deep Power-down mode.
+ * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode.
+ * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode.
+ * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = ACMP wake-up disable at Standby Power-down mode.
+ * | | |1 = ACMP wake-up enabled at Standby Power-down mode.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode.
+ * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var CLK_T::PMUSTS
+ * Offset: 0x94 Power Manager Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PINWK |Pin Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0)
+ * | | |This flag is cleared when DPD mode is entered.
+ * |[1] |TMRWK |Timer Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out
+ * | | |This flag is cleared when DPD or SPD mode is entered.
+ * |[2] |RTCWK |RTC Wake-up Flag (Read Only)
+ * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened
+ * | | |This flag is cleared when DPD or SPD mode is entered.
+ * |[8] |GPAWK |GPA Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[9] |GPBWK |GPB Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[10] |GPCWK |GPC Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[11] |GPDWK |GPD Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[12] |LVRWK |LVR Wake-up Flag (Read Only)
+ * | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[13] |BODWK |BOD Wake-up Flag (Read Only)
+ * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only)
+ * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[31] |CLRWK |Clear Wake-up Flag
+ * | | |0 = No clear.
+ * | | |1 = Clear all wake-up flag.
+ * @var CLK_T::LDOCTL
+ * Offset: 0x98 LDO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[18] |PDBIASEN |Power-down Bias Enable Bit
+ * | | |0 = Reserved.
+ * | | |1 = Power-down bias enabled.
+ * | | |Note: This bit should set to 1 before chip enter power-down mode.
+ * @var CLK_T::SWKDBCTL
+ * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection
+ * | | |0000 = Sample wake-up input once per 1 clocks.
+ * | | |0001 = Sample wake-up input once per 2 clocks.
+ * | | |0010 = Sample wake-up input once per 4 clocks.
+ * | | |0011 = Sample wake-up input once per 8 clocks.
+ * | | |0100 = Sample wake-up input once per 16 clocks.
+ * | | |0101 = Sample wake-up input once per 32 clocks.
+ * | | |0110 = Sample wake-up input once per 64 clocks.
+ * | | |0111 = Sample wake-up input once per 128 clocks.
+ * | | |1000 = Sample wake-up input once per 256 clocks.
+ * | | |1001 = Sample wake-up input once per 2*256 clocks.
+ * | | |1010 = Sample wake-up input once per 4*256 clocks.
+ * | | |1011 = Sample wake-up input once per 8*256 clocks.
+ * | | |1100 = Sample wake-up input once per 16*256 clocks.
+ * | | |1101 = Sample wake-up input once per 32*256 clocks.
+ * | | |1110 = Sample wake-up input once per 64*256 clocks.
+ * | | |1111 = Sample wake-up input once per 128*256 clocks.
+ * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
+ * @var CLK_T::PASWKCTL
+ * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
+ * | | |0 = GPA group pin wake-up function disabled.
+ * | | |1 = GPA group pin wake-up function enabled.
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
+ * | | |0 = GPA group pin rising edge wake-up function disabled.
+ * | | |1 = GPA group pin rising edge wake-up function enabled.
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
+ * | | |0 = GPA group pin falling edge wake-up function disabled.
+ * | | |1 = GPA group pin falling edge wake-up function enabled.
+ * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select
+ * | | |0000 = GPA.0 wake-up function enabled.
+ * | | |0001 = GPA.1 wake-up function enabled.
+ * | | |0010 = GPA.2 wake-up function enabled.
+ * | | |0011 = GPA.3 wake-up function enabled.
+ * | | |0100 = GPA.4 wake-up function enabled.
+ * | | |0101 = GPA.5 wake-up function enabled.
+ * | | |0110 = GPA.6 wake-up function enabled.
+ * | | |0111 = GPA.7 wake-up function enabled.
+ * | | |1000 = GPA.8 wake-up function enabled.
+ * | | |1001 = GPA.9 wake-up function enabled.
+ * | | |1010 = GPA.10 wake-up function enabled.
+ * | | |1011 = GPA.11 wake-up function enabled.
+ * | | |1100 = GPA.12 wake-up function enabled.
+ * | | |1101 = GPA.13 wake-up function enabled.
+ * | | |1110 = GPA.14 wake-up function enabled.
+ * | | |1111 = GPA.15 wake-up function enabled.
+ * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+ * | | |0 = Standby power-down wake-up pin De-bounce function disable.
+ * | | |1 = Standby power-down wake-up pin De-bounce function enable.
+ * | | |The de-bounce function is valid only for edge triggered.
+ * @var CLK_T::PBSWKCTL
+ * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
+ * | | |0 = GPB group pin wake-up function disabled.
+ * | | |1 = GPB group pin wake-up function enabled.
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
+ * | | |0 = GPB group pin rising edge wake-up function disabled.
+ * | | |1 = GPB group pin rising edge wake-up function enabled.
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
+ * | | |0 = GPB group pin falling edge wake-up function disabled.
+ * | | |1 = GPB group pin falling edge wake-up function enabled.
+ * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select
+ * | | |0000 = GPB.0 wake-up function enabled.
+ * | | |0001 = GPB.1 wake-up function enabled.
+ * | | |0010 = GPB.2 wake-up function enabled.
+ * | | |0011 = GPB.3 wake-up function enabled.
+ * | | |0100 = GPB.4 wake-up function enabled.
+ * | | |0101 = GPB.5 wake-up function enabled.
+ * | | |0110 = GPB.6 wake-up function enabled.
+ * | | |0111 = GPB.7 wake-up function enabled.
+ * | | |1000 = GPB.8 wake-up function enabled.
+ * | | |1001 = GPB.9 wake-up function enabled.
+ * | | |1010 = GPB.10 wake-up function enabled.
+ * | | |1011 = GPB.11 wake-up function enabled.
+ * | | |1100 = GPB.12 wake-up function enabled.
+ * | | |1101 = GPB.13 wake-up function enabled.
+ * | | |1110 = GPB.14 wake-up function enabled.
+ * | | |1111 = GPB.15 wake-up function enabled.
+ * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+ * | | |0 = Standby power-down wake-up pin De-bounce function disable.
+ * | | |1 = Standby power-down wake-up pin De-bounce function enable.
+ * | | |The de-bounce function is valid only for edge triggered.
+ * @var CLK_T::PCSWKCTL
+ * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
+ * | | |0 = GPC group pin wake-up function disabled.
+ * | | |1 = GPC group pin wake-up function enabled.
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
+ * | | |0 = GPC group pin rising edge wake-up function disabled.
+ * | | |1 = GPC group pin rising edge wake-up function enabled.
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
+ * | | |0 = GPC group pin falling edge wake-up function disabled.
+ * | | |1 = GPC group pin falling edge wake-up function enabled.
+ * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select
+ * | | |0000 = GPC.0 wake-up function enabled.
+ * | | |0001 = GPC.1 wake-up function enabled.
+ * | | |0010 = GPC.2 wake-up function enabled.
+ * | | |0011 = GPC.3 wake-up function enabled.
+ * | | |0100 = GPC.4 wake-up function enabled.
+ * | | |0101 = GPC.5 wake-up function enabled.
+ * | | |0110 = GPC.6 wake-up function enabled.
+ * | | |0111 = GPC.7 wake-up function enabled.
+ * | | |1000 = GPC.8 wake-up function enabled.
+ * | | |1001 = GPC.9 wake-up function enabled.
+ * | | |1010 = GPC.10 wake-up function enabled.
+ * | | |1011 = GPC.11 wake-up function enabled.
+ * | | |1100 = GPC.12 wake-up function enabled.
+ * | | |1101 = GPC.13 wake-up function enabled.
+ * | | |1110 = GPC.14 wake-up function enabled.
+ * | | |1111 = GPC.15 wake-up function enabled.
+ * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+ * | | |0 = Standby power-down wake-up pin De-bounce function disable.
+ * | | |1 = Standby power-down wake-up pin De-bounce function enable.
+ * | | |The de-bounce function is valid only for edge triggered.
+ * @var CLK_T::PDSWKCTL
+ * Offset: 0xAC GPD Standby Power-down Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
+ * | | |0 = GPD group pin wake-up function disabled.
+ * | | |1 = GPD group pin wake-up function enabled.
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
+ * | | |0 = GPD group pin rising edge wake-up function disabled.
+ * | | |1 = GPD group pin rising edge wake-up function enabled.
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
+ * | | |0 = GPD group pin falling edge wake-up function disabled.
+ * | | |1 = GPD group pin falling edge wake-up function enabled.
+ * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select
+ * | | |0000 = GPD.0 wake-up function enabled.
+ * | | |0001 = GPD.1 wake-up function enabled.
+ * | | |0010 = GPD.2 wake-up function enabled.
+ * | | |0011 = GPD.3 wake-up function enabled.
+ * | | |0100 = GPD.4 wake-up function enabled.
+ * | | |0101 = GPD.5 wake-up function enabled.
+ * | | |0110 = GPD.6 wake-up function enabled.
+ * | | |0111 = GPD.7 wake-up function enabled.
+ * | | |1000 = GPD.8 wake-up function enabled.
+ * | | |1001 = GPD.9 wake-up function enabled.
+ * | | |1010 = GPD.10 wake-up function enabled.
+ * | | |1011 = GPD.11 wake-up function enabled.
+ * | | |1100 = GPD.12 wake-up function enabled.
+ * | | |1101 = GPD.13 wake-up function enabled.
+ * | | |1110 = GPD.14 wake-up function enabled.
+ * | | |1111 = GPD.15 wake-up function enabled.
+ * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+ * | | |0 = Standby power-down wake-up pin De-bounce function disable.
+ * | | |1 = Standby power-down wake-up pin De-bounce function enable.
+ * | | |The de-bounce function is valid only for edge triggered.
+ * @var CLK_T::IOPDCTL
+ * Offset: 0xB0 GPIO Standby Power-down Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |IOHR |GPIO Hold Release
+ * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status
+ * | | |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status.
+ * | | |This bit is auto cleared by hardware.
+ */
+ __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */
+ __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */
+ __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */
+ __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */
+ __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */
+ __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */
+ __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */
+ __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */
+ __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */
+ __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */
+ __IO uint32_t CLKDIV2; /*!< [0x0028] Clock Divider Number Register 2 */
+ __IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */
+ __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */
+ __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE1[2];
+ /** @endcond */
+ __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE2[3];
+ /** @endcond */
+ __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE3[3];
+ /** @endcond */
+ __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE4[3];
+ /** @endcond */
+ __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */
+ __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */
+ __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */
+ __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE5[4];
+ /** @endcond */
+ __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */
+ __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */
+ __IO uint32_t LDOCTL; /*!< [0x0098] LDO Control Register */
+ __IO uint32_t SWKDBCTL; /*!< [0x009c] Standby Power-down Wake-up De-bounce Control Register */
+ __IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */
+ __IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */
+ __IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */
+ __IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */
+ __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */
+
+} CLK_T;
+
+/**
+ @addtogroup CLK_CONST CLK Bit Field Definition
+ Constant Definitions for CLK Controller
+@{ */
+
+#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */
+#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */
+
+#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */
+#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */
+
+#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */
+#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */
+
+#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */
+#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */
+
+#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */
+#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */
+
+#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */
+#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */
+
+#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */
+#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */
+
+#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */
+#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */
+
+#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */
+#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */
+
+#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */
+#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */
+
+#define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */
+#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */
+
+#define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */
+#define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */
+
+#define CLK_PWRCTL_HIRC48MEN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48MEN Position */
+#define CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos) /*!< CLK_T::PWRCTL: HIRC48MEN Mask */
+
+#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */
+#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */
+
+#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */
+#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */
+
+#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */
+#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */
+
+#define CLK_AHBCLK_EMACCKEN_Pos (5) /*!< CLK_T::AHBCLK: EMACCKEN Position */
+#define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /*!< CLK_T::AHBCLK: EMACCKEN Mask */
+
+#define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */
+#define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */
+
+#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */
+#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */
+
+#define CLK_AHBCLK_CCAPCKEN_Pos (8) /*!< CLK_T::AHBCLK: CCAPCKEN Position */
+#define CLK_AHBCLK_CCAPCKEN_Msk (0x1ul << CLK_AHBCLK_CCAPCKEN_Pos) /*!< CLK_T::AHBCLK: CCAPCKEN Mask */
+
+#define CLK_AHBCLK_SENCKEN_Pos (9) /*!< CLK_T::AHBCLK: SENCKEN Position */
+#define CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos) /*!< CLK_T::AHBCLK: SENCKEN Mask */
+
+#define CLK_AHBCLK_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK: HSUSBDCKEN Position */
+#define CLK_AHBCLK_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK: HSUSBDCKEN Mask */
+
+#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */
+#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */
+
+#define CLK_AHBCLK_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK: SPIMCKEN Position */
+#define CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK: SPIMCKEN Mask */
+
+#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */
+#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */
+
+#define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */
+#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */
+
+#define CLK_AHBCLK_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK: SDH1CKEN Position */
+#define CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK: SDH1CKEN Mask */
+
+#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */
+#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */
+
+#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */
+#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */
+
+#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */
+#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */
+
+#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */
+#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */
+
+#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */
+#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */
+
+#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */
+#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */
+
+#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */
+#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */
+
+#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */
+#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */
+
+#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */
+#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */
+
+#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */
+#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */
+
+#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */
+#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */
+
+#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */
+#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */
+
+#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */
+#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */
+
+#define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */
+#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */
+
+#define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */
+#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */
+
+#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */
+#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */
+
+#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */
+#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */
+
+#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */
+#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */
+
+#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */
+#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */
+
+#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */
+#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */
+
+#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */
+#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */
+
+#define CLK_APBCLK0_UART6CKEN_Pos (22) /*!< CLK_T::APBCLK0: UART6CKEN Position */
+#define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos) /*!< CLK_T::APBCLK0: UART6CKEN Mask */
+
+#define CLK_APBCLK0_UART7CKEN_Pos (23) /*!< CLK_T::APBCLK0: UART7CKEN Position */
+#define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos) /*!< CLK_T::APBCLK0: UART7CKEN Mask */
+
+#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */
+#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */
+
+#define CLK_APBCLK0_CAN1CKEN_Pos (25) /*!< CLK_T::APBCLK0: CAN1CKEN Position */
+#define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /*!< CLK_T::APBCLK0: CAN1CKEN Mask */
+
+#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */
+#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */
+
+#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */
+#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */
+
+#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */
+#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */
+
+#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */
+#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */
+
+#define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */
+#define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */
+
+#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */
+#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */
+
+#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */
+#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */
+
+#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */
+#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */
+
+#define CLK_APBCLK1_QSPI1CKEN_Pos (4) /*!< CLK_T::APBCLK1: QSPI1CKEN Position */
+#define CLK_APBCLK1_QSPI1CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos) /*!< CLK_T::APBCLK1: QSPI1CKEN Mask */
+
+#define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */
+#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */
+
+#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */
+#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */
+
+#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */
+#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */
+
+#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */
+#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */
+
+#define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */
+#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */
+
+#define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */
+#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */
+
+#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */
+#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */
+
+#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */
+#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */
+
+#define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */
+#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */
+
+#define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */
+#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */
+
+#define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */
+#define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */
+
+#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */
+#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */
+
+#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */
+#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */
+
+#define CLK_APBCLK1_CAN2CKEN_Pos (28) /*!< CLK_T::APBCLK1: CAN2CKEN Position */
+#define CLK_APBCLK1_CAN2CKEN_Msk (0x1ul << CLK_APBCLK1_CAN2CKEN_Pos) /*!< CLK_T::APBCLK1: CAN2CKEN Mask */
+
+#define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK_T::APBCLK1: OPACKEN Position */
+#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK_T::APBCLK1: OPACKEN Mask */
+
+#define CLK_APBCLK1_EADC1CKEN_Pos (31) /*!< CLK_T::APBCLK1: EADC1CKEN Position */
+#define CLK_APBCLK1_EADC1CKEN_Msk (0x1ul << CLK_APBCLK1_EADC1CKEN_Pos) /*!< CLK_T::APBCLK1: EADC1CKEN Mask */
+
+#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */
+#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */
+
+#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */
+#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */
+
+#define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */
+#define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */
+
+#define CLK_CLKSEL0_CCAPSEL_Pos (16) /*!< CLK_T::CLKSEL0: CCAPSEL Position */
+#define CLK_CLKSEL0_CCAPSEL_Msk (0x3ul << CLK_CLKSEL0_CCAPSEL_Pos) /*!< CLK_T::CLKSEL0: CCAPSEL Mask */
+
+#define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */
+#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */
+
+#define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */
+#define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */
+
+#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */
+#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */
+
+#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */
+#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */
+
+#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */
+#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */
+
+#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */
+#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */
+
+#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */
+#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */
+
+#define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */
+#define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */
+
+#define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */
+#define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */
+
+#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */
+#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */
+
+#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */
+#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */
+
+#define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */
+#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */
+
+#define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */
+#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */
+
+#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */
+#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */
+
+#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */
+#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */
+
+#define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */
+#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */
+
+#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */
+#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */
+
+#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */
+#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */
+
+#define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */
+#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */
+
+#define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */
+#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */
+
+#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */
+#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */
+
+#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */
+#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */
+
+#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */
+#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */
+
+#define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */
+#define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */
+
+#define CLK_CLKSEL3_QSPI1SEL_Pos (12) /*!< CLK_T::CLKSEL3: QSPI1SEL Position */
+#define CLK_CLKSEL3_QSPI1SEL_Msk (0x3ul << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< CLK_T::CLKSEL3: QSPI1SEL Mask */
+
+#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */
+#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */
+
+#define CLK_CLKSEL3_UART6SEL_Pos (20) /*!< CLK_T::CLKSEL3: UART6SEL Position */
+#define CLK_CLKSEL3_UART6SEL_Msk (0x3ul << CLK_CLKSEL3_UART6SEL_Pos) /*!< CLK_T::CLKSEL3: UART6SEL Mask */
+
+#define CLK_CLKSEL3_UART7SEL_Pos (22) /*!< CLK_T::CLKSEL3: UART7SEL Position */
+#define CLK_CLKSEL3_UART7SEL_Msk (0x3ul << CLK_CLKSEL3_UART7SEL_Pos) /*!< CLK_T::CLKSEL3: UART7SEL Mask */
+
+#define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */
+#define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */
+
+#define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */
+#define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */
+
+#define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */
+#define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */
+
+#define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */
+#define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */
+
+#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */
+#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */
+
+#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */
+#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */
+
+#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */
+#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */
+
+#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */
+#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */
+
+#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */
+#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */
+
+#define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */
+#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */
+
+#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */
+#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */
+
+#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */
+#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */
+
+#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */
+#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */
+
+#define CLK_CLKDIV2_I2SDIV_Pos (0) /*!< CLK_T::CLKDIV2: I2SDIV Position */
+#define CLK_CLKDIV2_I2SDIV_Msk (0xful << CLK_CLKDIV2_I2SDIV_Pos) /*!< CLK_T::CLKDIV2: I2SDIV Mask */
+
+#define CLK_CLKDIV2_EADC1DIV_Pos (24) /*!< CLK_T::CLKDIV2: EADC1DIV Position */
+#define CLK_CLKDIV2_EADC1DIV_Msk (0xfful << CLK_CLKDIV2_EADC1DIV_Pos) /*!< CLK_T::CLKDIV2: EADC1DIV Mask */
+
+#define CLK_CLKDIV3_CCAPDIV_Pos (0) /*!< CLK_T::CLKDIV3: CCAPDIV Position */
+#define CLK_CLKDIV3_CCAPDIV_Msk (0xfful << CLK_CLKDIV3_CCAPDIV_Pos) /*!< CLK_T::CLKDIV3: CCAPDIV Mask */
+
+#define CLK_CLKDIV3_VSENSEDIV_Pos (8) /*!< CLK_T::CLKDIV3: VSENSEDIV Position */
+#define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLK_T::CLKDIV3: VSENSEDIV Mask */
+
+#define CLK_CLKDIV3_EMACDIV_Pos (16) /*!< CLK_T::CLKDIV3: EMACDIV Position */
+#define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLK_T::CLKDIV3: EMACDIV Mask */
+
+#define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */
+#define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */
+
+#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */
+#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */
+
+#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */
+#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */
+
+#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */
+#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */
+
+#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */
+#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */
+
+#define CLK_CLKDIV4_UART6DIV_Pos (16) /*!< CLK_T::CLKDIV4: UART6DIV Position */
+#define CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLK_T::CLKDIV4: UART6DIV Mask */
+
+#define CLK_CLKDIV4_UART7DIV_Pos (20) /*!< CLK_T::CLKDIV4: UART7DIV Position */
+#define CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLK_T::CLKDIV4: UART7DIV Mask */
+
+#define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */
+#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */
+
+#define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */
+#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */
+
+#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */
+#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */
+
+#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */
+#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */
+
+#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */
+#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */
+
+#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */
+#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */
+
+#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */
+#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */
+
+#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */
+#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */
+
+#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */
+#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */
+
+#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */
+#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */
+
+#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */
+#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */
+
+#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */
+#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */
+
+#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */
+#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */
+
+#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */
+#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */
+
+#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */
+#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */
+
+#define CLK_STATUS_HIRC48MSTB_Pos (6) /*!< CLK_T::STATUS: HIRC48MSTB Position */
+#define CLK_STATUS_HIRC48MSTB_Msk (0x1ul << CLK_STATUS_HIRC48MSTB_Pos) /*!< CLK_T::STATUS: HIRC48MSTB Mask */
+
+#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */
+#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */
+
+#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */
+#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */
+
+#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */
+#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */
+
+#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */
+#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */
+
+#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */
+#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */
+
+#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */
+#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */
+
+#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */
+#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */
+
+#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */
+#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */
+
+#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */
+#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */
+
+#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */
+#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */
+
+#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */
+#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */
+
+#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */
+#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */
+
+#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */
+#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */
+
+#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */
+#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */
+
+#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */
+#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */
+
+#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */
+#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */
+
+#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */
+#define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */
+
+#define CLK_PMUCTL_DPDHOLDEN_Pos (3) /*!< CLK_T::PMUCTL: DPDHOLDEN Position */
+#define CLK_PMUCTL_DPDHOLDEN_Msk (0x1ul << CLK_PMUCTL_DPDHOLDEN_Pos) /*!< CLK_T::PMUCTL: DPDHOLDEN Mask */
+
+#define CLK_PMUCTL_SRETSEL_Pos (4) /*!< CLK_T::PMUCTL: SRETSEL Position */
+#define CLK_PMUCTL_SRETSEL_Msk (0x7ul << CLK_PMUCTL_SRETSEL_Pos) /*!< CLK_T::PMUCTL: SRETSEL Mask */
+
+#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */
+#define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */
+
+#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */
+#define CLK_PMUCTL_WKTMRIS_Msk (0xful << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */
+
+#define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */
+#define CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */
+
+#define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */
+#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */
+
+#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */
+#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */
+
+#define CLK_PMUCTL_WKPINEN1_Pos (24) /*!< CLK_T::PMUCTL: WKPINEN1 Position */
+#define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) /*!< CLK_T::PMUCTL: WKPINEN1 Mask */
+
+#define CLK_PMUCTL_WKPINEN2_Pos (26) /*!< CLK_T::PMUCTL: WKPINEN2 Position */
+#define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) /*!< CLK_T::PMUCTL: WKPINEN2 Mask */
+
+#define CLK_PMUCTL_WKPINEN3_Pos (28) /*!< CLK_T::PMUCTL: WKPINEN3 Position */
+#define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) /*!< CLK_T::PMUCTL: WKPINEN3 Mask */
+
+#define CLK_PMUCTL_WKPINEN4_Pos (30) /*!< CLK_T::PMUCTL: WKPINEN4 Position */
+#define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) /*!< CLK_T::PMUCTL: WKPINEN4 Mask */
+
+#define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */
+#define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */
+
+#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */
+#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */
+
+#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */
+#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */
+
+#define CLK_PMUSTS_PINWK1_Pos (3) /*!< CLK_T::PMUSTS: PINWK1 Position */
+#define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) /*!< CLK_T::PMUSTS: PINWK1 Mask */
+
+#define CLK_PMUSTS_PINWK2_Pos (4) /*!< CLK_T::PMUSTS: PINWK2 Position */
+#define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) /*!< CLK_T::PMUSTS: PINWK2 Mask */
+
+#define CLK_PMUSTS_PINWK3_Pos (5) /*!< CLK_T::PMUSTS: PINWK3 Position */
+#define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) /*!< CLK_T::PMUSTS: PINWK3 Mask */
+
+#define CLK_PMUSTS_PINWK4_Pos (6) /*!< CLK_T::PMUSTS: PINWK4 Position */
+#define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) /*!< CLK_T::PMUSTS: PINWK4 Mask */
+
+#define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */
+#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */
+
+#define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */
+#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */
+
+#define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */
+#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */
+
+#define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */
+#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */
+
+#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */
+#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */
+
+#define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */
+#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */
+
+#define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */
+#define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */
+
+#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */
+#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */
+
+#define CLK_LDOCTL_PDBIASEN_Pos (18) /*!< CLK_T::LDOCTL: PDBIASEN Position */
+#define CLK_LDOCTL_PDBIASEN_Msk (0x1ul << CLK_LDOCTL_PDBIASEN_Pos) /*!< CLK_T::LDOCTL: PDBIASEN Mask */
+
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */
+
+#define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */
+#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */
+
+#define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */
+#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */
+
+#define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */
+#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */
+
+#define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */
+#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */
+
+#define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */
+#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */
+
+#define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */
+#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */
+
+#define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */
+#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */
+
+#define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */
+#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */
+
+#define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */
+#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */
+
+#define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */
+#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */
+
+#define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */
+#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */
+
+#define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */
+#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */
+
+#define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */
+#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */
+
+#define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */
+#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */
+
+#define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */
+#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */
+
+#define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */
+#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */
+
+#define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */
+#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */
+
+#define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */
+#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */
+
+#define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */
+#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */
+
+#define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */
+#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */
+
+#define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */
+#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */
+
+/**@}*/ /* CLK_CONST */
+/**@}*/ /* end of CLK register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CLK_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crc_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crc_reg.h
new file mode 100644
index 00000000000..118f79739a3
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crc_reg.h
@@ -0,0 +1,150 @@
+/**************************************************************************//**
+ * @file crc_reg.h
+ * @version V1.00
+ * @brief CRC register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRC_REG_H__
+#define __CRC_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
+ Memory Mapped Structure for CRC Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var CRC_T::CTL
+ * Offset: 0x00 CRC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CRCEN |CRC Channel Enable Bit
+ * | | |0 = No effect.
+ * | | |1 = CRC operation Enabled.
+ * |[1] |CHKSINIT |Checksum Initialization
+ * | | |0 = No effect.
+ * | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
+ * | | |Note: This bit will be cleared automatically.
+ * |[24] |DATREV |Write Data Bit Order Reverse
+ * | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
+ * | | |0 = Bit order reversed for CRC write data in Disabled.
+ * | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
+ * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
+ * |[25] |CHKSREV |Checksum Bit Order Reverse
+ * | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
+ * | | |0 = Bit order reverse for CRC checksum Disabled.
+ * | | |1 = Bit order reverse for CRC checksum Enabled.
+ * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
+ * |[26] |DATFMT |Write Data 1's Complement
+ * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
+ * | | |0 = 1's complement for CRC writes data in Disabled.
+ * | | |1 = 1's complement for CRC writes data in Enabled.
+ * |[27] |CHKSFMT |Checksum 1's Complement
+ * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
+ * | | |0 = 1's complement for CRC checksum Disabled.
+ * | | |1 = 1's complement for CRC checksum Enabled.
+ * |[29:28] |DATLEN |CPU Write Data Length
+ * | | |This field indicates the write data length.
+ * | | |00 = Data length is 8-bit mode.
+ * | | |01 = Data length is 16-bit mode.
+ * | | |1x = Data length is 32-bit mode.
+ * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
+ * |[31:30] |CRCMODE |CRC Polynomial Mode
+ * | | |This field indicates the CRC operation polynomial mode.
+ * | | |00 = CRC-CCITT Polynomial mode.
+ * | | |01 = CRC-8 Polynomial mode.
+ * | | |10 = CRC-16 Polynomial mode.
+ * | | |11 = CRC-32 Polynomial mode.
+ * @var CRC_T::DAT
+ * Offset: 0x04 CRC Write Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DATA |CRC Write Data Bits
+ * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
+ * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
+ * @var CRC_T::SEED
+ * Offset: 0x08 CRC Seed Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEED |CRC Seed Value
+ * | | |This field indicates the CRC seed value.
+ * | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
+ * @var CRC_T::CHECKSUM
+ * Offset: 0x0C CRC Checksum Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CHECKSUM |CRC Checksum Results
+ * | | |This field indicates the CRC checksum result.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
+ __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
+ __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
+ __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
+
+} CRC_T;
+
+/**
+ @addtogroup CRC_CONST CRC Bit Field Definition
+ Constant Definitions for CRC Controller
+@{ */
+
+#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
+#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
+
+#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
+#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
+
+#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
+#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
+
+#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
+#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
+
+#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
+#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
+
+#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
+#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
+
+#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
+#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
+
+#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
+#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
+
+#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
+#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
+
+#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
+#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
+
+#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
+#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
+
+/**@}*/ /* CRC_CONST */
+/**@}*/ /* end of CRC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CRC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crypto_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crypto_reg.h
new file mode 100644
index 00000000000..f385975cb4d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crypto_reg.h
@@ -0,0 +1,2219 @@
+/**************************************************************************//**
+ * @file crypto_reg.h
+ * @version V1.00
+ * @brief CRYPTO register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRYPTO_REG_H__
+#define __CRYPTO_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup CRPT Cryptographic Accelerator(CRPT)
+ Memory Mapped Structure for Cryptographic Accelerator
+@{ */
+
+typedef struct
+{
+
+ /**
+ * @var CRPT_T::INTEN
+ * Offset: 0x00 Crypto Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |AESIEN |AES Interrupt Enable Control
+ * | | |0 = AES interrupt Disabled.
+ * | | |1 = AES interrupt Enabled.
+ * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
+ * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
+ * |[1] |AESEIEN |AES Error Flag Enable Control
+ * | | |0 = AES error interrupt flag Disabled.
+ * | | |1 = AES error interrupt flag Enabled.
+ * |[8] |TDESIEN |TDES/DES Interrupt Enable Control
+ * | | |0 = TDES/DES interrupt Disabled.
+ * | | |1 = TDES/DES interrupt Enabled.
+ * | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.
+ * | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
+ * |[9] |TDESEIEN |TDES/DES Error Flag Enable Control
+ * | | |0 = TDES/DES error interrupt flag Disabled.
+ * | | |1 = TDES/DES error interrupt flag Enabled.
+ * |[16] |PRNGIEN |PRNG Interrupt Enable Control
+ * | | |0 = PRNG interrupt Disabled.
+ * | | |1 = PRNG interrupt Enabled.
+ * |[22] |ECCIEN |ECC Interrupt Enable Control
+ * | | |0 = ECC interrupt Disabled.
+ * | | |1 = ECC interrupt Enabled.
+ * | | |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine.
+ * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation.
+ * |[23] |ECCEIEN |ECC Error Interrupt Enable Control
+ * | | |0 = ECC error interrupt flag Disabled.
+ * | | |1 = ECC error interrupt flag Enabled.
+ * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Control
+ * | | |0 = SHA/HMAC interrupt Disabled.
+ * | | |1 = SHA/HMAC interrupt Enabled.
+ * | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine
+ * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation.
+ * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Control
+ * | | |0 = SHA/HMAC error interrupt flag Disabled.
+ * | | |1 = SHA/HMAC error interrupt flag Enabled.
+ * @var CRPT_T::INTSTS
+ * Offset: 0x04 Crypto Interrupt Flag
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |AESIF |AES Finish Interrupt Flag
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
+ * | | |0 = No AES interrupt.
+ * | | |= AES encryption/decryption done interrupt.
+ * |[1] |AESEIF |AES Error Flag
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
+ * | | |0 = No AES error.
+ * | | |1 = AES encryption/decryption done interrupt.
+ * |[8] |TDESIF |TDES/DES Finish Interrupt Flag
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
+ * | | |0 = No TDES/DES interrupt.
+ * | | |1 = TDES/DES encryption/decryption done interrupt.
+ * |[9] |TDESEIF |TDES/DES Error Flag
+ * | | |This bit includes the operating and setting error
+ * | | |The detailed flag is shown in the CRPT_TDES_STS register
+ * | | |This includes operating and setting error.
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
+ * | | |0 = No TDES/DES error.
+ * | | |1 = TDES/DES encryption/decryption error interrupt.
+ * |[16] |PRNGIF |PRNG Finish Interrupt Flag
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
+ * | | |0 = No PRNG interrupt.
+ * | | |1 = PRNG key generation done interrupt.
+ * |[22] |ECCIF |ECC Finish Interrupt Flag
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
+ * | | |0 = No ECC interrupt.
+ * | | |1 = ECC operation done interrupt.
+ * |[23] |ECCEIF |ECC Error Flag
+ * | | |This register includes operating and setting error. The detail flag is shown in CRPT_ECC_STS register.
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
+ * | | |0 = No ECC error.
+ * | | |1 = ECC error interrupt.
+ * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
+ * | | |0 = No SHA/HMAC interrupt.
+ * | | |1 = SHA/HMAC operation done interrupt.
+ * |[25] |HMACEIF |SHA/HMAC Error Flag
+ * | | |This register includes operating and setting error. The detail flag is shown in CRPT_HMAC_STS register.
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
+ * | | |0 = No SHA/HMAC error.
+ * | | |1 = SHA/HMAC error interrupt.
+ * @var CRPT_T::PRNG_CTL
+ * Offset: 0x08 PRNG Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |START |Start PRNG Engine
+ * | | |0 = Stop PRNG engine.
+ * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated.
+ * |[1] |SEEDRLD |Reload New Seed for PRNG Engine
+ * | | |0 = Generating key based on the current seed.
+ * | | |1 = Reload new seed.
+ * |[3:2] |KEYSZ |PRNG Generate Key Size
+ * | | |00 = 64 bits.
+ * | | |01 = 128 bits.
+ * | | |10 = 192 bits.
+ * | | |11 = 256 bits.
+ * |[8] |BUSY |PRNG Busy (Read Only)
+ * | | |0 = PRNG engine is idle.
+ * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
+ * @var CRPT_T::PRNG_SEED
+ * Offset: 0x0C Seed for PRNG
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEED |Seed for PRNG (Write Only)
+ * | | |The bits store the seed for PRNG engine.
+ * @var CRPT_T::PRNG_KEY[8]
+ * Offset: 0x10 ~ 0x2C PRNG Generated Key0 ~ Key7
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |Store PRNG Generated Key (Read Only)
+ * | | |The bits store the key that is generated by PRNG.
+ * @var CRPT_T::AES_FDBCK[4]
+ * Offset: 0x50 ~ 0x5C AES Engine Output Feedback Data after Cryptographic Operation
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |FDBCK |AES Feedback Information
+ * | | |The feedback value is 128 bits in size.
+ * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode.
+ * | | |The AES engine outputs feedback information for IV in the next block's operation
+ * | | |Software can use this feedback information to implement more than four DMA channels
+ * | | |Software can store that feedback value temporarily
+ * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
+ * @var CRPT_T::TDES_FDBCKH
+ * Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |FDBCK |TDES/DES Feedback
+ * | | |The feedback value is 64 bits in size.
+ * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode
+ * | | |The feedback register is for CBC, CFB, and OFB mode.
+ * | | |TDES/DES engine outputs feedback information for IV in the next block's operation
+ * | | |Software can use this feedback information to implement more than four DMA channels
+ * | | |Software can store that feedback value temporarily
+ * | | |After switching back, fill the stored feedback value to this register in the same channel operation
+ * | | |Then can continue the operation with the original setting.
+ * @var CRPT_T::TDES_FDBCKL
+ * Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |FDBCK |TDES/DES Feedback
+ * | | |The feedback value is 64 bits in size.
+ * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode
+ * | | |The feedback register is for CBC, CFB, and OFB mode.
+ * | | |TDES/DES engine outputs feedback information for IV in the next block's operation
+ * | | |Software can use this feedback information to implement more than four DMA channels
+ * | | |Software can store that feedback value temporarily
+ * | | |After switching back, fill the stored feedback value to this register in the same channel operation
+ * | | |Then can continue the operation with the original setting.
+ * @var CRPT_T::AES_CTL
+ * Offset: 0x100 AES Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |START |AES Engine Start
+ * | | |0 = No effect.
+ * | | |1 = Start AES engine. BUSY flag will be set.
+ * | | |Note: This bit is always 0 when it's read back.
+ * |[1] |STOP |AES Engine Stop
+ * | | |0 = No effect.
+ * | | |1 = Stop AES engine.
+ * | | |Note: This bit is always 0 when it's read back.
+ * |[3:2] |KEYSZ |AES Key Size
+ * | | |This bit defines three different key size for AES operation.
+ * | | |2'b00 = 128 bits key.
+ * | | |2'b01 = 192 bits key.
+ * | | |2'b10 = 256 bits key.
+ * | | |2'b11 = Reserved.
+ * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
+ * |[5] |DMALAST |AES Last Block
+ * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
+ * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
+ * | | |This bit is always 0 when it's read back. Must be written again once START is triggered.
+ * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode
+ * | | |0 = DMA cascade function Disabled.
+ * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
+ * |[7] |DMAEN |AES Engine DMA Enable Control
+ * | | |0 = AES DMA engine Disabled.
+ * | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN.
+ * | | |1 = AES_DMA engine Enabled.
+ * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+ * |[15:8] |OPMODE |AES Engine Operation Modes
+ * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode).
+ * | | |0x02 = CFB (Cipher Feedback Mode).
+ * | | |0x03 = OFB (Output Feedback Mode).
+ * | | |0x04 = CTR (Counter Mode).
+ * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).
+ * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).
+ * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).
+ * |[16] |ENCRPT |AES Encryption/Decryption
+ * | | |0 = AES engine executes decryption operation.
+ * | | |1 = AES engine executes encryption operation.
+ * |[22] |OUTSWAP |AES Engine Output Data Swap
+ * | | |0 = Keep the original order.
+ * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+ * |[23] |INSWAP |AES Engine Input Data Swap
+ * | | |0 = Keep the original order.
+ * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+ * |[25:24] |CHANNEL |AES Engine Working Channel
+ * | | |00 = Current control register setting is for channel 0.
+ * | | |01 = Current control register setting is for channel 1.
+ * | | |10 = Current control register setting is for channel 2.
+ * | | |11 = Current control register setting is for channel 3.
+ * |[30:26] |KEYUNPRT |Unprotect Key
+ * | | |Writing 0 to CRPT_AES_CTL[31] and "10110" to CRPT_AES_CTL[30:26] is to unprotect the AES key.
+ * | | |The KEYUNPRT can be read and written
+ * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
+ * |[31] |KEYPRT |Protect Key
+ * | | |Read as a flag to reflect KEYPRT.
+ * | | |0 = No effect.
+ * | | |1 = Protect the content of the AES key from reading
+ * | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx
+ * | | |Once it is set, it can be cleared by asserting KEYUNPRT
+ * | | |And the key content would be cleared as well.
+ * @var CRPT_T::AES_STS
+ * Offset: 0x104 AES Engine Flag
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSY |AES Engine Busy
+ * | | |0 = The AES engine is idle or finished.
+ * | | |1 = The AES engine is under processing.
+ * |[8] |INBUFEMPTY|AES Input Buffer Empty
+ * | | |0 = There are some data in input buffer waiting for the AES engine to process.
+ * | | |1 = AES input buffer is empty
+ * | | |Software needs to feed data to the AES engine
+ * | | |Otherwise, the AES engine will be pending to wait for input data.
+ * |[9] |INBUFFULL |AES Input Buffer Full Flag
+ * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine.
+ * | | |1 = AES input buffer is full
+ * | | |Software cannot feed data to the AES engine
+ * | | |Otherwise, the flag INBUFERR will be set to 1.
+ * |[10] |INBUFERR |AES Input Buffer Error Flag
+ * | | |0 = No error.
+ * | | |1 = Error happens during feeding data to the AES engine.
+ * |[12] |CNTERR |CRPT_AESn_CNT Setting Error
+ * | | |0 = No error in CRPT_AESn_CNT setting.
+ * | | |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode.
+ * |[16] |OUTBUFEMPTY|AES Out Buffer Empty
+ * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer.
+ * | | |1 = AES output buffer is empty
+ * | | |Software cannot get data from CRPT_AES_DATOUT
+ * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.
+ * |[17] |OUTBUFFULL|AES Out Buffer Full Flag
+ * | | |0 = AES output buffer is not full.
+ * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT
+ * | | |Otherwise, the AES engine will be pending since the output buffer is full.
+ * |[18] |OUTBUFERR |AES Out Buffer Error Flag
+ * | | |0 = No error.
+ * | | |1 = Error happens during getting the result from AES engine.
+ * |[20] |BUSERR |AES DMA Access Bus Error Flag
+ * | | |0 = No error.
+ * | | |1 = Bus error will stop DMA operation and AES engine.
+ * @var CRPT_T::AES_DATIN
+ * Offset: 0x108 AES Engine Data Input Port Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DATIN |AES Engine Input Port
+ * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
+ * @var CRPT_T::AES_DATOUT
+ * Offset: 0x10C AES Engine Data Output Port Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DATOUT |AES Engine Output Port
+ * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS
+ * | | |Get data as OUTBUFEMPTY is 0.
+ * @var CRPT_T::AES0_KEY[8]
+ * Offset: 0x110 ~ 0x12C AES Key Word 0 ~ 7 Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |CRPT_AESn_KEYx
+ * | | |The KEY keeps the security key for AES operation.
+ * | | |n = 0, 1..3.
+ * | | |x = 0, 1..7.
+ * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+ * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+ * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+ * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+ * @var CRPT_T::AES0_IV[4]
+ * Offset: 0x130 ~ 0x13C AES Initial Vector Word 0 ~ 3 Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |AES Initial Vectors
+ * | | |n = 0, 1..3.
+ * | | |x = 0, 1..3.
+ * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+ * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+ * @var CRPT_T::AES0_SADDR
+ * Offset: 0x140 AES DMA Source Address Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SADDR |AES DMA Source Address
+ * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+ * | | |The SADDR keeps the source address of the data buffer where the source text is stored
+ * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+ * | | |The start of source address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of SADDR are ignored.
+ * | | |SADDR can be read and written
+ * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of SADDR will be updated later on
+ * | | |Consequently, software can prepare the DMA source address for the next AES operation.
+ * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+ * @var CRPT_T::AES0_DADDR
+ * Offset: 0x144 AES DMA Destination Address Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DADDR |AES DMA Destination Address
+ * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+ * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+ * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+ * | | |The start of destination address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of DADDR are ignored.
+ * | | |DADDR can be read and written
+ * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of DADDR will be updated later on
+ * | | |Consequently, software can prepare the destination address for the next AES operation.
+ * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+ * @var CRPT_T::AES0_CNT
+ * Offset: 0x148 AES Byte Count Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNT |AES Byte Count
+ * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+ * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+ * | | |CRPT_AESn_CNT can be read and written
+ * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of CRPT_AESn_CNT will be updated later on
+ * | | |Consequently, software can prepare the byte count of data for the next AES operation.
+ * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+ * | | |Operations that are less than one block will output unexpected result.
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+ * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+ * @var CRPT_T::AES1_KEY[8]
+ * Offset: 0x14C ~ 0x168 AES Key Word 0 ~ 7 Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |CRPT_AESn_KEYx
+ * | | |The KEY keeps the security key for AES operation.
+ * | | |n = 0, 1..3.
+ * | | |x = 0, 1..7.
+ * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+ * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+ * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+ * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+ * @var CRPT_T::AES1_IV[4]
+ * Offset: 0x16C ~ 0x178 AES Initial Vector Word 0 ~ 3 Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |AES Initial Vectors
+ * | | |n = 0, 1..3.
+ * | | |x = 0, 1..3.
+ * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+ * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+ * @var CRPT_T::AES1_SADDR
+ * Offset: 0x17C AES DMA Source Address Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SADDR |AES DMA Source Address
+ * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+ * | | |The SADDR keeps the source address of the data buffer where the source text is stored
+ * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+ * | | |The start of source address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of SADDR are ignored.
+ * | | |SADDR can be read and written
+ * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of SADDR will be updated later on
+ * | | |Consequently, software can prepare the DMA source address for the next AES operation.
+ * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+ * @var CRPT_T::AES1_DADDR
+ * Offset: 0x180 AES DMA Destination Address Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DADDR |AES DMA Destination Address
+ * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+ * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+ * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+ * | | |The start of destination address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of DADDR are ignored.
+ * | | |DADDR can be read and written
+ * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of DADDR will be updated later on
+ * | | |Consequently, software can prepare the destination address for the next AES operation.
+ * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+ * @var CRPT_T::AES1_CNT
+ * Offset: 0x184 AES Byte Count Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNT |AES Byte Count
+ * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+ * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+ * | | |CRPT_AESn_CNT can be read and written
+ * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of CRPT_AESn_CNT will be updated later on
+ * | | |Consequently, software can prepare the byte count of data for the next AES operation.
+ * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+ * | | |Operations that are less than one block will output unexpected result.
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+ * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+ * @var CRPT_T::AES2_KEY[8]
+ * Offset: 0x188 ~ 0x1A4 AES Key Word 0 ~ 7 Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |CRPT_AESn_KEYx
+ * | | |The KEY keeps the security key for AES operation.
+ * | | |n = 0, 1..3.
+ * | | |x = 0, 1..7.
+ * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+ * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+ * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+ * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+ * @var CRPT_T::AES2_IV[4]
+ * Offset: 0x1A8 ~ 0x1B4 AES Initial Vector Word 0 ~ 3 Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |AES Initial Vectors
+ * | | |n = 0, 1..3.
+ * | | |x = 0, 1..3.
+ * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+ * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+ * @var CRPT_T::AES2_SADDR
+ * Offset: 0x1B8 AES DMA Source Address Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SADDR |AES DMA Source Address
+ * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+ * | | |The SADDR keeps the source address of the data buffer where the source text is stored
+ * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+ * | | |The start of source address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of SADDR are ignored.
+ * | | |SADDR can be read and written
+ * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of SADDR will be updated later on
+ * | | |Consequently, software can prepare the DMA source address for the next AES operation.
+ * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+ * @var CRPT_T::AES2_DADDR
+ * Offset: 0x1BC AES DMA Destination Address Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DADDR |AES DMA Destination Address
+ * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+ * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+ * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+ * | | |The start of destination address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of DADDR are ignored.
+ * | | |DADDR can be read and written
+ * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of DADDR will be updated later on
+ * | | |Consequently, software can prepare the destination address for the next AES operation.
+ * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+ * @var CRPT_T::AES2_CNT
+ * Offset: 0x1C0 AES Byte Count Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNT |AES Byte Count
+ * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+ * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+ * | | |CRPT_AESn_CNT can be read and written
+ * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of CRPT_AESn_CNT will be updated later on
+ * | | |Consequently, software can prepare the byte count of data for the next AES operation.
+ * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+ * | | |Operations that are less than one block will output unexpected result.
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+ * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+ * @var CRPT_T::AES3_KEY[8]
+ * Offset: 0x1C4 ~ 0x1E0 AES Key Word 0 ~ 7 Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |CRPT_AESn_KEYx
+ * | | |The KEY keeps the security key for AES operation.
+ * | | |n = 0, 1..3.
+ * | | |x = 0, 1..7.
+ * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+ * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+ * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+ * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+ * @var CRPT_T::AES3_IV[4]
+ * Offset: 0x1E4 ~ 0x1F0 AES Initial Vector Word 0 ~ 3 Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |AES Initial Vectors
+ * | | |n = 0, 1..3.
+ * | | |x = 0, 1..3.
+ * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+ * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+ * @var CRPT_T::AES3_SADDR
+ * Offset: 0x1F4 AES DMA Source Address Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SADDR |AES DMA Source Address
+ * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+ * | | |The SADDR keeps the source address of the data buffer where the source text is stored
+ * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+ * | | |The start of source address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of SADDR are ignored.
+ * | | |SADDR can be read and written
+ * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of SADDR will be updated later on
+ * | | |Consequently, software can prepare the DMA source address for the next AES operation.
+ * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+ * @var CRPT_T::AES3_DADDR
+ * Offset: 0x1F8 AES DMA Destination Address Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DADDR |AES DMA Destination Address
+ * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+ * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+ * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+ * | | |The start of destination address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of DADDR are ignored.
+ * | | |DADDR can be read and written
+ * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of DADDR will be updated later on
+ * | | |Consequently, software can prepare the destination address for the next AES operation.
+ * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+ * @var CRPT_T::AES3_CNT
+ * Offset: 0x1FC AES Byte Count Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNT |AES Byte Count
+ * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+ * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+ * | | |CRPT_AESn_CNT can be read and written
+ * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+ * | | |But the value of CRPT_AESn_CNT will be updated later on
+ * | | |Consequently, software can prepare the byte count of data for the next AES operation.
+ * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+ * | | |Operations that are less than one block will output unexpected result.
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+ * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+ * @var CRPT_T::TDES_CTL
+ * Offset: 0x200 TDES/DES Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |START |TDES/DES Engine Start
+ * | | |0 = No effect.
+ * | | |1 = Start TDES/DES engine. The flag BUSY would be set.
+ * | | |Note: The bit is always 0 when it's read back.
+ * |[1] |STOP |TDES/DES Engine Stop
+ * | | |0 = No effect.
+ * | | |1 = Stop TDES/DES engine.
+ * | | |Note: The bit is always 0 when it's read back.
+ * |[2] |TMODE |TDES/DES Engine Operating Mode
+ * | | |0 = Set DES mode for TDES/DES engine.
+ * | | |1 = Set Triple DES mode for TDES/DES engine.
+ * |[3] |3KEYS |TDES/DES Key Number
+ * | | |0 = Select KEY1 and KEY2 in TDES/DES engine.
+ * | | |1 = Triple keys in TDES/DES engine Enabled.
+ * |[5] |DMALAST |TDES/DES Engine Start for the Last Block
+ * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
+ * | | |In Non-DMA mode, this bit must be set as feeding in last block of data.
+ * |[6] |DMACSCAD |TDES/DES Engine DMA with Cascade Mode
+ * | | |0 = DMA cascade function Disabled.
+ * | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
+ * |[7] |DMAEN |TDES/DES Engine DMA Enable Control
+ * | | |0 = TDES_DMA engine Disabled.
+ * | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN.
+ * | | |1 = TDES_DMA engine Enabled.
+ * | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+ * |[10:8] |OPMODE |TDES/DES Engine Operation Mode
+ * | | |0x00 = ECB (Electronic Codebook Mode).
+ * | | |0x01 = CBC (Cipher Block Chaining Mode).
+ * | | |0x02 = CFB (Cipher Feedback Mode).
+ * | | |0x03 = OFB (Output Feedback Mode).
+ * | | |0x04 = CTR (Counter Mode).
+ * | | |Others = CTR (Counter Mode).
+ * |[16] |ENCRPT |TDES/DES Encryption/Decryption
+ * | | |0 = TDES engine executes decryption operation.
+ * | | |1 = TDES engine executes encryption operation.
+ * |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap
+ * | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}.
+ * | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}.
+ * |[22] |OUTSWAP |TDES/DES Engine Output Data Swap
+ * | | |0 = Keep the original order.
+ * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+ * |[23] |INSWAP |TDES/DES Engine Input Data Swap
+ * | | |0 = Keep the original order.
+ * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+ * |[25:24] |CHANNEL |TDES/DES Engine Working Channel
+ * | | |00 = Current control register setting is for channel 0.
+ * | | |01 = Current control register setting is for channel 1.
+ * | | |10 = Current control register setting is for channel 2.
+ * | | |11 = Current control register setting is for channel 3.
+ * |[30:26] |KEYUNPRT |Unprotect Key
+ * | | |Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key.
+ * | | |The KEYUNPRT can be read and written
+ * | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
+ * |[31] |KEYPRT |Protect Key
+ * | | |Read as a flag to reflect KEYPRT.
+ * | | |0 = No effect.
+ * | | |1 = This bit is to protect the content of TDES key from reading
+ * | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L
+ * | | |Once it is set, it can be cleared by asserting KEYUNPRT
+ * | | |The key content would be cleared as well.
+ * @var CRPT_T::TDES_STS
+ * Offset: 0x204 TDES/DES Engine Flag
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSY |TDES/DES Engine Busy
+ * | | |0 = TDES/DES engine is idle or finished.
+ * | | |1 = TDES/DES engine is under processing.
+ * |[8] |INBUFEMPTY|TDES/DES in Buffer Empty
+ * | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process.
+ * | | |1 = TDES/DES input buffer is empty
+ * | | |Software needs to feed data to the TDES/DES engine
+ * | | |Otherwise, the TDES/DES engine will be pending to wait for input data.
+ * |[9] |INBUFFULL |TDES/DES in Buffer Full Flag
+ * | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine.
+ * | | |1 = TDES input buffer is full
+ * | | |Software cannot feed data to the TDES/DES engine
+ * | | |Otherwise, the flag INBUFERR will be set to 1.
+ * |[10] |INBUFERR |TDES/DES in Buffer Error Flag
+ * | | |0 = No error.
+ * | | |1 = Error happens during feeding data to the TDES/DES engine.
+ * |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag
+ * | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer.
+ * | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT
+ * | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty.
+ * |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag
+ * | | |0 = TDES/DES output buffer is not full.
+ * | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT
+ * | | |Otherwise, the TDES/DES engine will be pending since output buffer is full.
+ * |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag
+ * | | |0 = No error.
+ * | | |1 = Error happens during getting test result from TDES/DES engine.
+ * |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag
+ * | | |0 = No error.
+ * | | |1 = Bus error will stop DMA operation and TDES/DES engine.
+ * @var CRPT_T::TDES0_KEY1H
+ * Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 1 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES0_KEY1L
+ * Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 1 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES0_KEY2H
+ * Offset: 0x210 TDES Key 2 High Word Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 2 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES0_KEY2L
+ * Offset: 0x214 TDES Key 2 Low Word Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 2 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES0_KEY3H
+ * Offset: 0x218 TDES Key 3 High Word Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 3 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES0_KEY3L
+ * Offset: 0x21C TDES Key 3 Low Word Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 3 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES0_IVH
+ * Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |TDES/DES Initial Vector High Word
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
+ * @var CRPT_T::TDES0_IVL
+ * Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |TDES/DES Initial Vector Low Word
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
+ * @var CRPT_T::TDES0_SA
+ * Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SADDR |TDES/DES DMA Source Address
+ * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+ * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+ * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+ * | | |The start of source address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+ * | | |CRPT_TDESn_SA can be read and written
+ * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_SA will be updated later on
+ * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+ * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+ * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+ * @var CRPT_T::TDES0_DA
+ * Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DADDR |TDES/DES DMA Destination Address
+ * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+ * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+ * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+ * | | |The start of destination address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+ * | | |CRPT_TDESn_DA can be read and written
+ * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_DA will be updated later on
+ * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
+ * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+ * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+ * @var CRPT_T::TDES0_CNT
+ * Offset: 0x230 TDES/DES Byte Count Register for Channel 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNT |TDES/DES Byte Count
+ * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+ * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+ * | | |CRPT_TDESn_CNT can be read and written
+ * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_CNT will be updated later on
+ * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+ * @var CRPT_T::TDES_DATIN
+ * Offset: 0x234 TDES/DES Engine Input data Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DATIN |TDES/DES Engine Input Port
+ * | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS
+ * | | |Feed data as INBUFFULL is 0.
+ * @var CRPT_T::TDES_DATOUT
+ * Offset: 0x238 TDES/DES Engine Output data Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DATOUT |TDES/DES Engine Output Port
+ * | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS
+ * | | |Get data as OUTBUFEMPTY is 0.
+ * @var CRPT_T::TDES1_KEY1H
+ * Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 1 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES1_KEY1L
+ * Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 1 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES1_KEY2H
+ * Offset: 0x250 TDES Key 2 High Word Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 2 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES1_KEY2L
+ * Offset: 0x254 TDES Key 2 Low Word Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 2 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES1_KEY3H
+ * Offset: 0x258 TDES Key 3 High Word Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 3 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES1_KEY3L
+ * Offset: 0x25C TDES Key 3 Low Word Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 3 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES1_IVH
+ * Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |TDES/DES Initial Vector High Word
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
+ * @var CRPT_T::TDES1_IVL
+ * Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |TDES/DES Initial Vector Low Word
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
+ * @var CRPT_T::TDES1_SA
+ * Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SADDR |TDES/DES DMA Source Address
+ * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+ * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+ * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+ * | | |The start of source address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+ * | | |CRPT_TDESn_SA can be read and written
+ * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_SA will be updated later on
+ * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+ * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+ * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+ * @var CRPT_T::TDES1_DA
+ * Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DADDR |TDES/DES DMA Destination Address
+ * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+ * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+ * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+ * | | |The start of destination address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+ * | | |CRPT_TDESn_DA can be read and written
+ * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_DA will be updated later on
+ * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
+ * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+ * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+ * @var CRPT_T::TDES1_CNT
+ * Offset: 0x270 TDES/DES Byte Count Register for Channel 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNT |TDES/DES Byte Count
+ * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+ * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+ * | | |CRPT_TDESn_CNT can be read and written
+ * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_CNT will be updated later on
+ * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+ * @var CRPT_T::TDES2_KEY1H
+ * Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 1 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES2_KEY1L
+ * Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 1 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES2_KEY2H
+ * Offset: 0x290 TDES Key 2 High Word Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 2 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES2_KEY2L
+ * Offset: 0x294 TDES Key 2 Low Word Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 2 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES2_KEY3H
+ * Offset: 0x298 TDES Key 3 High Word Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 3 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES2_KEY3L
+ * Offset: 0x29C TDES Key 3 Low Word Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 3 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES2_IVH
+ * Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |TDES/DES Initial Vector High Word
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
+ * @var CRPT_T::TDES2_IVL
+ * Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |TDES/DES Initial Vector Low Word
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
+ * @var CRPT_T::TDES2_SA
+ * Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SADDR |TDES/DES DMA Source Address
+ * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+ * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+ * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+ * | | |The start of source address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+ * | | |CRPT_TDESn_SA can be read and written
+ * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_SA will be updated later on
+ * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+ * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+ * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+ * @var CRPT_T::TDES2_DA
+ * Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DADDR |TDES/DES DMA Destination Address
+ * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+ * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+ * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+ * | | |The start of destination address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+ * | | |CRPT_TDESn_DA can be read and written
+ * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_DA will be updated later on
+ * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
+ * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+ * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+ * @var CRPT_T::TDES2_CNT
+ * Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNT |TDES/DES Byte Count
+ * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+ * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+ * | | |CRPT_TDESn_CNT can be read and written
+ * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_CNT will be updated later on
+ * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+ * @var CRPT_T::TDES3_KEY1H
+ * Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 1 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES3_KEY1L
+ * Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 1 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES3_KEY2H
+ * Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 2 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES3_KEY2L
+ * Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 2 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES3_KEY3H
+ * Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 3 High Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES3_KEY3L
+ * Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY |TDES/DES Key 3 Low Word
+ * | | |The key registers for TDES/DES algorithm calculation
+ * | | |The security key for the TDES/DES accelerator is 64 bits
+ * | | |Thus, it needs two 32-bit registers to store a security key
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+ * @var CRPT_T::TDES3_IVH
+ * Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |TDES/DES Initial Vector High Word
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
+ * @var CRPT_T::TDES3_IVL
+ * Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IV |TDES/DES Initial Vector Low Word
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
+ * @var CRPT_T::TDES3_SA
+ * Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SADDR |TDES/DES DMA Source Address
+ * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+ * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+ * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+ * | | |The start of source address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+ * | | |CRPT_TDESn_SA can be read and written
+ * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_SA will be updated later on
+ * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+ * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+ * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+ * @var CRPT_T::TDES3_DA
+ * Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DADDR |TDES/DES DMA Destination Address
+ * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+ * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+ * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+ * | | |The start of destination address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+ * | | |CRPT_TDESn_DA can be read and written
+ * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_DA will be updated later on
+ * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
+ * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+ * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+ * @var CRPT_T::TDES3_CNT
+ * Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNT |TDES/DES Byte Count
+ * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+ * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+ * | | |CRPT_TDESn_CNT can be read and written
+ * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+ * | | |But the value of CRPT_TDESn_CNT will be updated later on
+ * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+ * @var CRPT_T::HMAC_CTL
+ * Offset: 0x300 SHA/HMAC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |START |SHA/HMAC Engine Start
+ * | | |0 = No effect.
+ * | | |1 = Start SHA/HMAC engine. BUSY flag will be set.
+ * | | |This bit is always 0 when it's read back.
+ * |[1] |STOP |SHA/HMAC Engine Stop
+ * | | |0 = No effect.
+ * | | |1 = Stop SHA/HMAC engine.
+ * | | |This bit is always 0 when it's read back.
+ * |[4] |HMACEN |HMAC_SHA Engine Operating Mode
+ * | | |0 = execute SHA function.
+ * | | |1 = execute HMAC function.
+ * |[5] |DMALAST |SHA/HMAC Last Block
+ * | | |This bit must be set as feeding in last byte of data.
+ * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Control
+ * | | |0 = SHA/HMAC DMA engine Disabled.
+ * | | |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN.
+ * | | |1 = SHA/HMAC DMA engine Enabled.
+ * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+ * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes
+ * | | |0x0xx: SHA160
+ * | | |0x100: SHA256
+ * | | |0x101: SHA224
+ * | | |0x110: SHA512
+ * | | |0x111: SHA384
+ * | | |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1.
+ * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap
+ * | | |0 = Keep the original order.
+ * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+ * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap
+ * | | |0 = Keep the original order.
+ * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+ * @var CRPT_T::HMAC_STS
+ * Offset: 0x304 SHA/HMAC Status Flag
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSY |SHA/HMAC Engine Busy
+ * | | |0 = SHA/HMAC engine is idle or finished.
+ * | | |1 = SHA/HMAC engine is busy.
+ * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag
+ * | | |0 = SHA/HMAC DMA engine is idle or finished.
+ * | | |1 = SHA/HMAC DMA engine is busy.
+ * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag
+ * | | |0 = Show the SHA/HMAC engine access normal.
+ * | | |1 = Show the SHA/HMAC engine access error.
+ * |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request
+ * | | |0 = No effect.
+ * | | |1 = Request SHA/HMAC Non-DMA mode data input.
+ * @var CRPT_T::HMAC_DGST[16]
+ * Offset: 0x308 ~ 0x344 SHA/HMAC Digest Message 0 ~ 15
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DGST |SHA/HMAC Digest Message Output Register
+ * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4.
+ * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6.
+ * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7.
+ * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11.
+ * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15.
+ * @var CRPT_T::HMAC_KEYCNT
+ * Offset: 0x348 SHA/HMAC Key Byte Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count
+ * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates
+ * | | |The register is 32-bit and the maximum byte count is 4G bytes
+ * | | |It can be read and written.
+ * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation
+ * | | |But the value of CRPT_SHA _KEYCNT will be updated later on
+ * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation.
+ * @var CRPT_T::HMAC_SADDR
+ * Offset: 0x34C SHA/HMAC DMA Source Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SADDR |SHA/HMAC DMA Source Address
+ * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+ * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored
+ * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation
+ * | | |The start of source address should be located at word boundary
+ * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored.
+ * | | |CRPT_HMAC_SADDR can be read and written
+ * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation
+ * | | |But the value of CRPT_HMAC_SADDR will be updated later on
+ * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation.
+ * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START.
+ * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value.
+ * @var CRPT_T::HMAC_DMACNT
+ * Offset: 0x350 SHA/HMAC Byte Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count
+ * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode
+ * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes.
+ * | | |CRPT_HMAC_DMACNT can be read and written
+ * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation
+ * | | |But the value of CRPT_HMAC_DMACNT will be updated later on
+ * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation.
+ * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
+ * @var CRPT_T::HMAC_DATIN
+ * Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DATIN |SHA/HMAC Engine Input Port
+ * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS
+ * | | |Feed data as DATINREQ is 1.
+ * @var CRPT_T::ECC_CTL
+ * Offset: 0x800 ECC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |START |ECC Accelerator Start
+ * | | |0 = No effect.
+ * | | |1 = Start ECC accelerator. BUSY flag will be set.
+ * | | |This bit is always 0 when it's read back.
+ * | | |ECC accelerator will ignore this START signal when BUSY flag is 1.
+ * |[1] |STOP |ECC Accelerator Stop
+ * | | |0 = No effect.
+ * | | |1 = Abort ECC accelerator and make it into idle state.
+ * | | |This bit is always 0 when it's read back.
+ * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator.
+ * |[7] |DMAEN |ECC Accelerator DMA Enable Control
+ * | | |0 = ECC DMA engine Disabled.
+ * | | |1 = ECC DMA engine Enabled.
+ * | | |Only when START and DMAEN are 1, ECC DMA engine will be active
+ * |[8] |FSEL |Field Selection
+ * | | |0 = Binary Field (GF(2^m)).
+ * | | |1 = Prime Field (GF(p)).
+ * |[10:9] |ECCOP |Point Operation for BF and PF
+ * | | |00 = Point multiplication :.
+ * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1).
+ * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]).
+ * | | |10 = Point addition :.
+ * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +.
+ * | | |(POINTX2, POINTY2)
+ * | | |11 = Point doubling :.
+ * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1).
+ * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11
+ * |[12:11] |MODOP |Modulus Operation for PF
+ * | | |00 = Division :.
+ * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN.
+ * | | |01 = Multiplication :.
+ * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN.
+ * | | |10 = Addition :.
+ * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN.
+ * | | |11 = Subtraction :.
+ * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN.
+ * | | |MODOP is active only when ECCOP = 01.
+ * |[16] |LDP1 |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1)
+ * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user.
+ * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user.
+ * |[17] |LDP2 |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2)
+ * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user.
+ * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user.
+ * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve
+ * | | |0 = The register for CURVEA is not modified by DMA or user.
+ * | | |1 = The register for CURVEA is modified by DMA or user.
+ * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve
+ * | | |0 = The register for CURVEB is not modified by DMA or user.
+ * | | |1 = The register for CURVEB is modified by DMA or user.
+ * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve
+ * | | |0 = The register for CURVEN is not modified by DMA or user.
+ * | | |1 = The register for CURVEN is modified by DMA or user.
+ * |[21] |LDK |The Control Signal of Register for SCALARK
+ * | | |0 = The register for SCALARK is not modified by DMA or user.
+ * | | |1 = The register for SCALARK is modified by DMA or user.
+ * |[31:22] |CURVEM |The key length of elliptic curve.
+ * @var CRPT_T::ECC_STS
+ * Offset: 0x804 ECC Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSY |ECC Accelerator Busy Flag
+ * | | |0 = The ECC accelerator is idle or finished.
+ * | | |1 = The ECC accelerator is under processing and protects all registers.
+ * | | |Remember to clear ECC interrupt flag after ECC accelerator finished
+ * |[1] |DMABUSY |ECC DMA Busy Flag
+ * | | |0 = ECC DMA is idle or finished.
+ * | | |1 = ECC DMA is busy.
+ * |[16] |BUSERR |ECC DMA Access Bus Error Flag
+ * | | |0 = No error.
+ * | | |1 = Bus error will stop DMA operation and ECC accelerator.
+ * @var CRPT_T::ECC_X1[18]
+ * Offset: 0x808 ~ 0x84C ECC The X-coordinate word 0 ~ 17 of the first point
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |POINTX1 |ECC the x-coordinate Value of the First Point (POINTX1)
+ * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
+ * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
+ * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08
+ * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12
+ * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17
+ * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
+ * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06
+ * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
+ * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11
+ * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16
+ * @var CRPT_T::ECC_Y1[18]
+ * Offset: 0x850 ~ 0x894 ECC The Y-coordinate word 0 ~ 17 of the first point
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point (POINTY1)
+ * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
+ * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
+ * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08
+ * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12
+ * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17
+ * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
+ * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06
+ * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
+ * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11
+ * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16
+ * @var CRPT_T::ECC_X2[18]
+ * Offset: 0x898 ~ 0x8DC ECC The X-coordinate word 0 ~ 17 of the second point
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |POINTX2 |ECC the x-coordinate Value of the Second Point (POINTX2)
+ * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
+ * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
+ * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08
+ * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12
+ * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17
+ * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
+ * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06
+ * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
+ * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11
+ * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16
+ * @var CRPT_T::ECC_Y2[18]
+ * Offset: 0x8E0 ~ 0x924 ECC The Y-coordinate word 0 ~ 17 of the second point
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point (POINTY2)
+ * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
+ * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
+ * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08
+ * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12
+ * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17
+ * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
+ * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06
+ * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
+ * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11
+ * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16
+ * @var CRPT_T::ECC_A[18]
+ * Offset: 0x928 ~ 0x96C ECC The parameter CURVEA word 0 ~ 17 of elliptic curve
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)
+ * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m).
+ * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
+ * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
+ * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08
+ * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12
+ * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17
+ * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
+ * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06
+ * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
+ * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11
+ * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16
+ * @var CRPT_T::ECC_B[18]
+ * Offset: 0x970 ~ 0x9B4 ECC The parameter CURVEB word 0 ~ 17 of elliptic curve
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)
+ * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m).
+ * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
+ * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
+ * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08
+ * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12
+ * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17
+ * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
+ * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06
+ * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
+ * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11
+ * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16
+ * @var CRPT_T::ECC_N[18]
+ * Offset: 0x9B8 ~ 0x9FC ECC The parameter CURVEN word 0 ~ 17 of elliptic curve
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)
+ * | | |In GF(p), CURVEN is the prime p.
+ * | | |In GF(2^m), CURVEN is the irreducible polynomial.
+ * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05
+ * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07
+ * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08
+ * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12
+ * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17
+ * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05
+ * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06
+ * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07
+ * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11
+ * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16
+ * @var CRPT_T::ECC_K[18]
+ * Offset: 0xA00 ~ 0xA44 ECC The scalar SCALARK word0 of point multiplication
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)
+ * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK.
+ * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05
+ * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07
+ * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08
+ * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12
+ * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17
+ * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05
+ * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06
+ * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07
+ * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11
+ * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16
+ * @var CRPT_T::ECC_SADDR
+ * Offset: 0xA48 ECC DMA Source Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SADDR |ECC DMA Source Address
+ * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between
+ * | | |SRAM memory space and ECC accelerator. The SADDR keeps the source address of the data
+ * | | |buffer where the source text is stored. Based on the source address, the ECC accelerator
+ * | | |can read the DATA and PARAMETER from SRAM memory space and do ECC operation. The start
+ * | | |of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are
+ * | | |ignored. SADDR can be read and written. In DMA mode, software must update the CRPT_ECC_SADDR
+ * | | |before triggering START.
+ * @var CRPT_T::ECC_DADDR
+ * Offset: 0xA4C ECC DMA Destination Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DADDR |ECC DMA Destination Address
+ * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator
+ * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored
+ * | | |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished
+ * | | |The start of destination address should be located at word boundary
+ * | | |That is, bit 1 and 0 of DADDR are ignored
+ * | | |DADDR can be read and written
+ * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START
+ * @var CRPT_T::ECC_STARTREG
+ * Offset: 0xA50 ECC Starting Address of Updated Registers
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |STARTREG |ECC Starting Address of Updated Registers
+ * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine
+ * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG
+ * | | |For example, we want to updated input data from register CRPT_ECC POINTX1
+ * | | |Thus, the value of STARTREG is 0x808.
+ * @var CRPT_T::ECC_WORDCNT
+ * Offset: 0xA54 ECC DMA Word Count
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |WORDCNT |ECC DMA Word Count
+ * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode
+ * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words
+ * | | |CRPT_ECC_WORDCNT can be read and written
+ */
+ __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */
+ __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */
+ __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */
+ __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */
+ __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[8];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */
+ __I uint32_t TDES_FDBCKH; /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */
+ __I uint32_t TDES_FDBCKL; /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[38];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */
+ __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */
+ __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */
+ __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */
+ __IO uint32_t AES0_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */
+ __IO uint32_t AES0_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */
+ __IO uint32_t AES0_SADDR; /*!< [0x0140] AES DMA Source Address Register for Channel 0 */
+ __IO uint32_t AES0_DADDR; /*!< [0x0144] AES DMA Destination Address Register for Channel 0 */
+ __IO uint32_t AES0_CNT; /*!< [0x0148] AES Byte Count Register for Channel 0 */
+ __IO uint32_t AES1_KEY[8]; /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1 */
+ __IO uint32_t AES1_IV[4]; /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1 */
+ __IO uint32_t AES1_SADDR; /*!< [0x017c] AES DMA Source Address Register for Channel 1 */
+ __IO uint32_t AES1_DADDR; /*!< [0x0180] AES DMA Destination Address Register for Channel 1 */
+ __IO uint32_t AES1_CNT; /*!< [0x0184] AES Byte Count Register for Channel 1 */
+ __IO uint32_t AES2_KEY[8]; /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2 */
+ __IO uint32_t AES2_IV[4]; /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2 */
+ __IO uint32_t AES2_SADDR; /*!< [0x01b8] AES DMA Source Address Register for Channel 2 */
+ __IO uint32_t AES2_DADDR; /*!< [0x01bc] AES DMA Destination Address Register for Channel 2 */
+ __IO uint32_t AES2_CNT; /*!< [0x01c0] AES Byte Count Register for Channel 2 */
+ __IO uint32_t AES3_KEY[8]; /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3 */
+ __IO uint32_t AES3_IV[4]; /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3 */
+ __IO uint32_t AES3_SADDR; /*!< [0x01f4] AES DMA Source Address Register for Channel 3 */
+ __IO uint32_t AES3_DADDR; /*!< [0x01f8] AES DMA Destination Address Register for Channel 3 */
+ __IO uint32_t AES3_CNT; /*!< [0x01fc] AES Byte Count Register for Channel 3 */
+ __IO uint32_t TDES_CTL; /*!< [0x0200] TDES/DES Control Register */
+ __I uint32_t TDES_STS; /*!< [0x0204] TDES/DES Engine Flag */
+ __IO uint32_t TDES0_KEY1H; /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0 */
+ __IO uint32_t TDES0_KEY1L; /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0 */
+ __IO uint32_t TDES0_KEY2H; /*!< [0x0210] TDES Key 2 High Word Register for Channel 0 */
+ __IO uint32_t TDES0_KEY2L; /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0 */
+ __IO uint32_t TDES0_KEY3H; /*!< [0x0218] TDES Key 3 High Word Register for Channel 0 */
+ __IO uint32_t TDES0_KEY3L; /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0 */
+ __IO uint32_t TDES0_IVH; /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0 */
+ __IO uint32_t TDES0_IVL; /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0 */
+ __IO uint32_t TDES0_SA; /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0 */
+ __IO uint32_t TDES0_DA; /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0 */
+ __IO uint32_t TDES0_CNT; /*!< [0x0230] TDES/DES Byte Count Register for Channel 0 */
+ __IO uint32_t TDES_DATIN; /*!< [0x0234] TDES/DES Engine Input data Word Register */
+ __I uint32_t TDES_DATOUT; /*!< [0x0238] TDES/DES Engine Output data Word Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t TDES1_KEY1H; /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1 */
+ __IO uint32_t TDES1_KEY1L; /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1 */
+ __IO uint32_t TDES1_KEY2H; /*!< [0x0250] TDES Key 2 High Word Register for Channel 1 */
+ __IO uint32_t TDES1_KEY2L; /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1 */
+ __IO uint32_t TDES1_KEY3H; /*!< [0x0258] TDES Key 3 High Word Register for Channel 1 */
+ __IO uint32_t TDES1_KEY3L; /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1 */
+ __IO uint32_t TDES1_IVH; /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1 */
+ __IO uint32_t TDES1_IVL; /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1 */
+ __IO uint32_t TDES1_SA; /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1 */
+ __IO uint32_t TDES1_DA; /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1 */
+ __IO uint32_t TDES1_CNT; /*!< [0x0270] TDES/DES Byte Count Register for Channel 1 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t TDES2_KEY1H; /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2 */
+ __IO uint32_t TDES2_KEY1L; /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2 */
+ __IO uint32_t TDES2_KEY2H; /*!< [0x0290] TDES Key 2 High Word Register for Channel 2 */
+ __IO uint32_t TDES2_KEY2L; /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2 */
+ __IO uint32_t TDES2_KEY3H; /*!< [0x0298] TDES Key 3 High Word Register for Channel 2 */
+ __IO uint32_t TDES2_KEY3L; /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2 */
+ __IO uint32_t TDES2_IVH; /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2 */
+ __IO uint32_t TDES2_IVL; /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2 */
+ __IO uint32_t TDES2_SA; /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2 */
+ __IO uint32_t TDES2_DA; /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2 */
+ __IO uint32_t TDES2_CNT; /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE4[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t TDES3_KEY1H; /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3 */
+ __IO uint32_t TDES3_KEY1L; /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3 */
+ __IO uint32_t TDES3_KEY2H; /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3 */
+ __IO uint32_t TDES3_KEY2L; /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3 */
+ __IO uint32_t TDES3_KEY3H; /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3 */
+ __IO uint32_t TDES3_KEY3L; /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3 */
+ __IO uint32_t TDES3_IVH; /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3 */
+ __IO uint32_t TDES3_IVL; /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3 */
+ __IO uint32_t TDES3_SA; /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3 */
+ __IO uint32_t TDES3_DA; /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3 */
+ __IO uint32_t TDES3_CNT; /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE5[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */
+ __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */
+ __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */
+ __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */
+ __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */
+ __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */
+ __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE6[298];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */
+ __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */
+ __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point */
+ __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */
+ __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */
+ __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */
+ __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */
+ __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */
+ __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */
+ __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */
+ __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */
+ __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */
+ __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */
+ __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */
+
+} CRPT_T;
+
+/**
+ @addtogroup CRPT_CONST CRPT Bit Field Definition
+ Constant Definitions for CRPT Controller
+@{ */
+
+#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */
+#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */
+
+#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */
+#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */
+
+#define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT_T::INTEN: TDESIEN Position */
+#define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT_T::INTEN: TDESIEN Mask */
+
+#define CRPT_INTEN_TDESEIEN_Pos (9) /*!< CRPT_T::INTEN: TDESEIEN Position */
+#define CRPT_INTEN_TDESEIEN_Msk (0x1ul << CRPT_INTEN_TDESEIEN_Pos) /*!< CRPT_T::INTEN: TDESEIEN Mask */
+
+#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */
+#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */
+
+#define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */
+#define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */
+
+#define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */
+#define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */
+
+#define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */
+#define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */
+
+#define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */
+#define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */
+
+#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */
+#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */
+
+#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */
+#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */
+
+#define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT_T::INTSTS: TDESIF Position */
+#define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT_T::INTSTS: TDESIF Mask */
+
+#define CRPT_INTSTS_TDESEIF_Pos (9) /*!< CRPT_T::INTSTS: TDESEIF Position */
+#define CRPT_INTSTS_TDESEIF_Msk (0x1ul << CRPT_INTSTS_TDESEIF_Pos) /*!< CRPT_T::INTSTS: TDESEIF Mask */
+
+#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */
+#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */
+
+#define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */
+#define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */
+
+#define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */
+#define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */
+
+#define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */
+#define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */
+
+#define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */
+#define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */
+
+#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */
+#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */
+
+#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */
+#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */
+
+#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */
+#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */
+
+#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */
+#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */
+
+#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */
+#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */
+
+#define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */
+#define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY[8]: KEY Mask */
+
+#define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */
+#define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */
+
+#define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKH: FDBCK Position */
+#define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask */
+
+#define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKL: FDBCK Position */
+#define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask */
+
+#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */
+#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */
+
+#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */
+#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */
+
+#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */
+#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */
+
+#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */
+#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */
+
+#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */
+#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */
+
+#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */
+#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */
+
+#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */
+#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */
+
+#define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */
+#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */
+
+#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */
+#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */
+
+#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */
+#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */
+
+#define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::AES_CTL: CHANNEL Position */
+#define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT_T::AES_CTL: CHANNEL Mask */
+
+#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */
+#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */
+
+#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */
+#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */
+
+#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */
+#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */
+
+#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */
+#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */
+
+#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */
+#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */
+
+#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */
+#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */
+
+#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */
+#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */
+
+#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position */
+#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */
+
+#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */
+#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */
+
+#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */
+#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */
+
+#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */
+#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */
+
+#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */
+#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */
+
+#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */
+#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */
+
+#define CRPT_AES0_KEYx_KEY_Pos (0) /*!< CRPT_T::AES0_KEY[8]: KEY Position */
+#define CRPT_AES0_KEYx_KEY_Msk (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos) /*!< CRPT_T::AES0_KEY[8]: KEY Mask */
+
+#define CRPT_AES0_IVx_IV_Pos (0) /*!< CRPT_T::AES0_IV[4]: IV Position */
+#define CRPT_AES0_IVx_IV_Msk (0xfffffffful << CRPT_AES0_IVx_IV_Pos) /*!< CRPT_T::AES0_IV[4]: IV Mask */
+
+#define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES0_SADDR: SADDR Position */
+#define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT_T::AES0_SADDR: SADDR Mask */
+
+#define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES0_DADDR: DADDR Position */
+#define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT_T::AES0_DADDR: DADDR Mask */
+
+#define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT_T::AES0_CNT: CNT Position */
+#define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT_T::AES0_CNT: CNT Mask */
+
+#define CRPT_AES1_KEYx_KEY_Pos (0) /*!< CRPT_T::AES1_KEY[8]: KEY Position */
+#define CRPT_AES1_KEYx_KEY_Msk (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos) /*!< CRPT_T::AES1_KEY[8]: KEY Mask */
+
+#define CRPT_AES1_IVx_IV_Pos (0) /*!< CRPT_T::AES1_IV[4]: IV Position */
+#define CRPT_AES1_IVx_IV_Msk (0xfffffffful << CRPT_AES1_IVx_IV_Pos) /*!< CRPT_T::AES1_IV[4]: IV Mask */
+
+#define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES1_SADDR: SADDR Position */
+#define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT_T::AES1_SADDR: SADDR Mask */
+
+#define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES1_DADDR: DADDR Position */
+#define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT_T::AES1_DADDR: DADDR Mask */
+
+#define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT_T::AES1_CNT: CNT Position */
+#define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT_T::AES1_CNT: CNT Mask */
+
+#define CRPT_AES2_KEYx_KEY_Pos (0) /*!< CRPT_T::AES2_KEY[8]: KEY Position */
+#define CRPT_AES2_KEYx_KEY_Msk (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos) /*!< CRPT_T::AES2_KEY[8]: KEY Mask */
+
+#define CRPT_AES2_IVx_IV_Pos (0) /*!< CRPT_T::AES2_IV[4]: IV Position */
+#define CRPT_AES2_IVx_IV_Msk (0xfffffffful << CRPT_AES2_IVx_IV_Pos) /*!< CRPT_T::AES2_IV[4]: IV Mask */
+
+#define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES2_SADDR: SADDR Position */
+#define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT_T::AES2_SADDR: SADDR Mask */
+
+#define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES2_DADDR: DADDR Position */
+#define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT_T::AES2_DADDR: DADDR Mask */
+
+#define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT_T::AES2_CNT: CNT Position */
+#define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT_T::AES2_CNT: CNT Mask */
+
+#define CRPT_AES3_KEYx_KEY_Pos (0) /*!< CRPT_T::AES3_KEY[8]: KEY Position */
+#define CRPT_AES3_KEYx_KEY_Msk (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos) /*!< CRPT_T::AES3_KEY[8]: KEY Mask */
+
+#define CRPT_AES3_IVx_IV_Pos (0) /*!< CRPT_T::AES3_IV[4]: IV Position */
+#define CRPT_AES3_IVx_IV_Msk (0xfffffffful << CRPT_AES3_IVx_IV_Pos) /*!< CRPT_T::AES3_IV[4]: IV Mask */
+
+#define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES3_SADDR: SADDR Position */
+#define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT_T::AES3_SADDR: SADDR Mask */
+
+#define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES3_DADDR: DADDR Position */
+#define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT_T::AES3_DADDR: DADDR Mask */
+
+#define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT_T::AES3_CNT: CNT Position */
+#define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT_T::AES3_CNT: CNT Mask */
+
+#define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT_T::TDES_CTL: START Position */
+#define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT_T::TDES_CTL: START Mask */
+
+#define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT_T::TDES_CTL: STOP Position */
+#define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT_T::TDES_CTL: STOP Mask */
+
+#define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT_T::TDES_CTL: TMODE Position */
+#define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT_T::TDES_CTL: TMODE Mask */
+
+#define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT_T::TDES_CTL: 3KEYS Position */
+#define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT_T::TDES_CTL: 3KEYS Mask */
+
+#define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT_T::TDES_CTL: DMALAST Position */
+#define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT_T::TDES_CTL: DMALAST Mask */
+
+#define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::TDES_CTL: DMACSCAD Position */
+#define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT_T::TDES_CTL: DMACSCAD Mask */
+
+#define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT_T::TDES_CTL: DMAEN Position */
+#define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT_T::TDES_CTL: DMAEN Mask */
+
+#define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT_T::TDES_CTL: OPMODE Position */
+#define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT_T::TDES_CTL: OPMODE Mask */
+
+#define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::TDES_CTL: ENCRPT Position */
+#define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT_T::TDES_CTL: ENCRPT Mask */
+
+#define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT_T::TDES_CTL: BLKSWAP Position */
+#define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT_T::TDES_CTL: BLKSWAP Mask */
+
+#define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::TDES_CTL: OUTSWAP Position */
+#define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT_T::TDES_CTL: OUTSWAP Mask */
+
+#define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT_T::TDES_CTL: INSWAP Position */
+#define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT_T::TDES_CTL: INSWAP Mask */
+
+#define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::TDES_CTL: CHANNEL Position */
+#define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT_T::TDES_CTL: CHANNEL Mask */
+
+#define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::TDES_CTL: KEYUNPRT Position */
+#define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask */
+
+#define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::TDES_CTL: KEYPRT Position */
+#define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYPRT Mask */
+
+#define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT_T::TDES_STS: BUSY Position */
+#define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT_T::TDES_STS: BUSY Mask */
+
+#define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::TDES_STS: INBUFEMPTY Position */
+#define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask */
+
+#define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::TDES_STS: INBUFFULL Position */
+#define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT_T::TDES_STS: INBUFFULL Mask */
+
+#define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT_T::TDES_STS: INBUFERR Position */
+#define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT_T::TDES_STS: INBUFERR Mask */
+
+#define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */
+#define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask */
+
+#define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::TDES_STS: OUTBUFFULL Position */
+#define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask */
+
+#define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::TDES_STS: OUTBUFERR Position */
+#define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT_T::TDES_STS: OUTBUFERR Mask */
+
+#define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT_T::TDES_STS: BUSERR Position */
+#define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT_T::TDES_STS: BUSERR Mask */
+
+#define CRPT_TDES0_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxH: KEY Position */
+#define CRPT_TDES0_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos) /*!< CRPT_T::TDES0_KEYxH: KEY Mask */
+
+#define CRPT_TDES0_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxL: KEY Position */
+#define CRPT_TDES0_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos) /*!< CRPT_T::TDES0_KEYxL: KEY Mask */
+
+#define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT_T::TDES0_IVH: IV Position */
+#define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT_T::TDES0_IVH: IV Mask */
+
+#define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT_T::TDES0_IVL: IV Position */
+#define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT_T::TDES0_IVL: IV Mask */
+
+#define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES0_SADDR: SADDR Position */
+#define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT_T::TDES0_SADDR: SADDR Mask */
+
+#define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES0_DADDR: DADDR Position */
+#define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT_T::TDES0_DADDR: DADDR Mask */
+
+#define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT_T::TDES0_CNT: CNT Position */
+#define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT_T::TDES0_CNT: CNT Mask */
+
+#define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT_T::TDES_DATIN: DATIN Position */
+#define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT_T::TDES_DATIN: DATIN Mask */
+
+#define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::TDES_DATOUT: DATOUT Position */
+#define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT_T::TDES_DATOUT: DATOUT Mask */
+
+#define CRPT_TDES1_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxH: KEY Position */
+#define CRPT_TDES1_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos) /*!< CRPT_T::TDES1_KEYxH: KEY Mask */
+
+#define CRPT_TDES1_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxL: KEY Position */
+#define CRPT_TDES1_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT_T::TDES1_KEYxL: KEY Mask */
+
+#define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT_T::TDES1_IVH: IV Position */
+#define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT_T::TDES1_IVH: IV Mask */
+
+#define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT_T::TDES1_IVL: IV Position */
+#define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT_T::TDES1_IVL: IV Mask */
+
+#define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES1_SADDR: SADDR Position */
+#define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT_T::TDES1_SADDR: SADDR Mask */
+
+#define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES1_DADDR: DADDR Position */
+#define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT_T::TDES1_DADDR: DADDR Mask */
+
+#define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT_T::TDES1_CNT: CNT Position */
+#define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT_T::TDES1_CNT: CNT Mask */
+
+#define CRPT_TDES2_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxH: KEY Position */
+#define CRPT_TDES2_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos) /*!< CRPT_T::TDES2_KEYxH: KEY Mask */
+
+#define CRPT_TDES2_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxL: KEY Position */
+#define CRPT_TDES2_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos) /*!< CRPT_T::TDES2_KEYxL: KEY Mask */
+
+#define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT_T::TDES2_IVH: IV Position */
+#define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT_T::TDES2_IVH: IV Mask */
+
+#define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT_T::TDES2_IVL: IV Position */
+#define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT_T::TDES2_IVL: IV Mask */
+
+#define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES2_SADDR: SADDR Position */
+#define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT_T::TDES2_SADDR: SADDR Mask */
+
+#define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES2_DADDR: DADDR Position */
+#define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT_T::TDES2_DADDR: DADDR Mask */
+
+#define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT_T::TDES2_CNT: CNT Position */
+#define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT_T::TDES2_CNT: CNT Mask */
+
+#define CRPT_TDES3_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxH: KEY Position */
+#define CRPT_TDES3_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos) /*!< CRPT_T::TDES3_KEYxH: KEY Mask */
+
+#define CRPT_TDES3_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxL: KEY Position */
+#define CRPT_TDES3_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos) /*!< CRPT_T::TDES3_KEYxL: KEY Mask */
+
+#define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT_T::TDES3_IVH: IV Position */
+#define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT_T::TDES3_IVH: IV Mask */
+
+#define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT_T::TDES3_IVL: IV Position */
+#define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT_T::TDES3_IVL: IV Mask */
+
+#define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES3_SADDR: SADDR Position */
+#define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT_T::TDES3_SADDR: SADDR Mask */
+
+#define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES3_DADDR: DADDR Position */
+#define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT_T::TDES3_DADDR: DADDR Mask */
+
+#define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT_T::TDES3_CNT: CNT Position */
+#define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT_T::TDES3_CNT: CNT Mask */
+
+#define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */
+#define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */
+
+#define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */
+#define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */
+
+#define CRPT_HMAC_CTL_HMACEN_Pos (4) /*!< CRPT_T::HMAC_CTL: HMACEN Position */
+#define CRPT_HMAC_CTL_HMACEN_Msk (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos) /*!< CRPT_T::HMAC_CTL: HMACEN Mask */
+
+#define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */
+#define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */
+
+#define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */
+#define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */
+
+#define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */
+#define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */
+
+#define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */
+#define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */
+
+#define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */
+#define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */
+
+#define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */
+#define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */
+
+#define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */
+#define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */
+
+#define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */
+#define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */
+
+#define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */
+#define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */
+
+#define CRPT_HMAC_DGSTx_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST[16]: DGST Position */
+#define CRPT_HMAC_DGSTx_DGST_Msk (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos) /*!< CRPT_T::HMAC_DGST[16]: DGST Mask */
+
+#define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */
+#define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */
+
+#define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */
+#define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */
+
+#define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */
+#define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */
+
+#define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */
+#define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */
+
+#define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */
+#define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */
+
+#define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */
+#define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */
+
+#define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */
+#define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */
+
+#define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */
+#define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */
+
+#define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */
+#define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */
+
+#define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */
+#define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */
+
+#define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */
+#define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */
+
+#define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */
+#define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */
+
+#define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */
+#define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */
+
+#define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */
+#define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */
+
+#define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */
+#define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */
+
+#define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */
+#define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */
+
+#define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */
+#define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */
+
+#define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */
+#define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */
+
+#define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */
+#define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */
+
+#define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */
+#define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */
+
+#define CRPT_ECC_X1_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1[18]: POINTX1 Position */
+#define CRPT_ECC_X1_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos) /*!< CRPT_T::ECC_X1[18]: POINTX1 Mask */
+
+#define CRPT_ECC_Y1_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Position */
+#define CRPT_ECC_Y1_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Mask */
+
+#define CRPT_ECC_X2_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2[18]: POINTX2 Position */
+#define CRPT_ECC_X2_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos) /*!< CRPT_T::ECC_X2[18]: POINTX2 Mask */
+
+#define CRPT_ECC_Y2_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Position */
+#define CRPT_ECC_Y2_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Mask */
+
+#define CRPT_ECC_A_CURVEA_Pos (0) /*!< CRPT_T::ECC_A[18]: CURVEA Position */
+#define CRPT_ECC_A_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_CURVEA_Pos) /*!< CRPT_T::ECC_A[18]: CURVEA Mask */
+
+#define CRPT_ECC_B_CURVEB_Pos (0) /*!< CRPT_T::ECC_B[18]: CURVEB Position */
+#define CRPT_ECC_B_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_CURVEB_Pos) /*!< CRPT_T::ECC_B[18]: CURVEB Mask */
+
+#define CRPT_ECC_N_CURVEN_Pos (0) /*!< CRPT_T::ECC_N[18]: CURVEN Position */
+#define CRPT_ECC_N_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_CURVEN_Pos) /*!< CRPT_T::ECC_N[18]: CURVEN Mask */
+
+#define CRPT_ECC_K_SCALARK_Pos (0) /*!< CRPT_T::ECC_K[18]: SCALARK Position */
+#define CRPT_ECC_K_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_SCALARK_Pos) /*!< CRPT_T::ECC_K[18]: SCALARK Mask */
+
+#define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */
+#define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */
+
+#define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/
+#define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */
+
+#define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position */
+#define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */
+
+/**@}*/ /* CRPT_CONST CRYPTO */
+/**@}*/ /* end of CRYPTO register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CRYPTO_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/dac_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/dac_reg.h
new file mode 100644
index 00000000000..bf2f67a5f1f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/dac_reg.h
@@ -0,0 +1,210 @@
+/**************************************************************************//**
+ * @file dac_reg.h
+ * @version V1.00
+ * @brief DAC register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __DAC_REG_H__
+#define __DAC_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup DAC Digital to Analog Converter(DAC)
+ Memory Mapped Structure for DAC Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var DAC_T::CTL
+ * Offset: 0x00 DAC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DACEN |DAC Enable Bit
+ * | | |0 = DAC is Disabled.
+ * | | |1 = DAC is Enabled.
+ * |[1] |DACIEN |DAC Interrupt Enable Bit
+ * | | |0 = Interrupt is Disabled.
+ * | | |1 = Interrupt is Enabled.
+ * |[2] |DMAEN |DMA Mode Enable Bit
+ * | | |0 = DMA mode Disabled.
+ * | | |1 = DMA mode Enabled.
+ * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit
+ * | | |0 = DMA under-run interrupt Disabled.
+ * | | |1 = DMA under-run interrupt Enabled.
+ * |[4] |TRGEN |Trigger Mode Enable Bit
+ * | | |0 = DAC event trigger mode Disabled.
+ * | | |1 = DAC event trigger mode Enabled.
+ * |[7:5] |TRGSEL |Trigger Source Selection
+ * | | |000 = Software trigger.
+ * | | |001 = External pin DAC0_ST trigger.
+ * | | |010 = Timer 0 trigger.
+ * | | |011 = Timer 1 trigger.
+ * | | |100 = Timer 2 trigger.
+ * | | |101 = Timer 3 trigger.
+ * | | |110 = EPWM0 trigger.
+ * | | |111 = EPWM1 trigger.
+ * |[8] |BYPASS |Bypass Buffer Mode
+ * | | |0 = Output voltage buffer Enabled.
+ * | | |1 = Output voltage buffer Disabled.
+ * |[10] |LALIGN |DAC Data Left-aligned Enabled Control
+ * | | |0 = Right alignment.
+ * | | |1 = Left alignment.
+ * |[13:12] |ETRGSEL |External Pin Trigger Selection
+ * | | |00 = Low level trigger.
+ * | | |01 = High level trigger.
+ * | | |10 = Falling edge trigger.
+ * | | |11 = Rising edge trigger.
+ * |[15:14] |BWSEL |DAC Data Bit-width Selection
+ * | | |00 = data is 12 bits.
+ * | | |01 = data is 8 bits.
+ * | | |Others = reserved.
+ * |[16] |GRPEN |DAC Group Mode Enable Bit
+ * | | |0 = DAC0 and DAC1 are not grouped.
+ * | | |1 = DAC0 and DAC1 are grouped.
+ * @var DAC_T::SWTRG
+ * Offset: 0x04 DAC Software Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SWTRG |Software Trigger
+ * | | |0 = Software trigger Disabled.
+ * | | |1 = Software trigger Enabled.
+ * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
+ * @var DAC_T::DAT
+ * Offset: 0x08 DAC Data Holding Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DACDAT |DAC 12-bit Holding Data
+ * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output
+ * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
+ * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
+ * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
+ * @var DAC_T::DATOUT
+ * Offset: 0x0C DAC Data Output Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |DATOUT |DAC 12-bit Output Data
+ * | | |These bits are current digital data for DAC output conversion.
+ * | | |It is loaded from DAC_DAT register and user cannot write it directly.
+ * @var DAC_T::STATUS
+ * Offset: 0x10 DAC Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FINISH |DAC Conversion Complete Finish Flag
+ * | | |0 = DAC is in conversion state.
+ * | | |1 = DAC conversion finish.
+ * | | |This bit set to 1 when conversion time counter counts to SETTLET
+ * | | |It is cleared to 0 when DAC starts a new conversion
+ * | | |User writes 1 to clear this bit to 0.
+ * |[1] |DMAUDR |DMA Under-run Interrupt Flag
+ * | | |0 = No DMA under-run error condition occurred.
+ * | | |1 = DMA under-run error condition occurred.
+ * | | |User writes 1 to clear this bit.
+ * |[8] |BUSY |DAC Busy Flag (Read Only)
+ * | | |0 = DAC is ready for next conversion.
+ * | | |1 = DAC is busy in conversion.
+ * | | |This is read only bit.
+ * @var DAC_T::TCTL
+ * Offset: 0x14 DAC Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |SETTLET |DAC Output Settling Time
+ * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
+ * | | |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50.
+ * | | |SELTTLET = DAC controller clock speed x settling time.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */
+ __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */
+ __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */
+ __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */
+ __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */
+ __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */
+
+} DAC_T;
+
+/**
+ @addtogroup DAC_CONST DAC Bit Field Definition
+ Constant Definitions for DAC Controller
+@{ */
+
+#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
+#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
+
+#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
+#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
+
+#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
+#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
+
+#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
+#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
+
+#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
+#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
+
+#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
+#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
+
+#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
+#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
+
+#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
+#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
+
+#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
+#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
+
+#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */
+#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */
+
+#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */
+#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */
+
+#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
+#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
+
+#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */
+#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */
+
+#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
+#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
+
+#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
+#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
+
+#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
+#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
+
+#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
+#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
+
+#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
+#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
+
+/**@}*/ /* DAC_CONST */
+/**@}*/ /* end of DAC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __DAC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/eadc_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/eadc_reg.h
new file mode 100644
index 00000000000..ee500f6ec90
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/eadc_reg.h
@@ -0,0 +1,1714 @@
+/**************************************************************************//**
+ * @file eadc_reg.h
+ * @version V1.00
+ * @brief EADC register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EADC_REG_H__
+#define __EADC_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup EADC Enhanced Analog to Digital Converter(EADC)
+ Memory Mapped Structure for EADC Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var EADC_T::DAT[19]
+ * Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RESULT |ADC Conversion Result
+ * | | |This field contains 12 bits conversion result.
+ * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
+ * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
+ * |[16] |OV |Overrun Flag
+ * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
+ * | | |0 = Data in RESULT[11:0] is recent conversion result.
+ * | | |1 = Data in RESULT[11:0] is overwrite.
+ * | | |Note: It is cleared by hardware after EADC_DAT register is read.
+ * |[17] |VALID |Valid Flag
+ * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
+ * | | |0 = Data in RESULT[11:0] bits is not valid.
+ * | | |1 = Data in RESULT[11:0] bits is valid.
+ * @var EADC_T::CURDAT
+ * Offset: 0x4C ADC PDMA Current Transfer Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register
+ * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
+ * | | |This is a read only register.
+ * @var EADC_T::CTL
+ * Offset: 0x50 ADC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADCEN |ADC Converter Enable Bit
+ * | | |0 = Disabled EADC.
+ * | | |1 = Enabled EADC.
+ * | | |Note: Before starting ADC conversion function, this bit should be set to 1
+ * | | |Clear it to 0 to disable ADC converter analog circuit power consumption.
+ * |[1] |ADCRST |ADC Converter Control Circuits Reset
+ * | | |0 = No effect.
+ * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
+ * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
+ * |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit
+ * | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion
+ * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
+ * | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled.
+ * | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled.
+ * |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit
+ * | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion
+ * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
+ * | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled.
+ * | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled.
+ * |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit
+ * | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion
+ * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
+ * | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled.
+ * | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled.
+ * |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit
+ * | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion
+ * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
+ * | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled.
+ * | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled.
+ * |[7:6] |RESSEL |Resolution Selection
+ * | | |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]).
+ * | | |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]).
+ * | | |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]).
+ * | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]).
+ * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit
+ * | | |0 = Single-end analog input mode.
+ * | | |1 = Differential analog input mode.
+ * |[9] |DMOF |ADC Differential Input Mode Output Format
+ * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
+ * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
+ * |[11] |PDMAEN |PDMA Transfer Enable Bit
+ * | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
+ * | | |0 = PDMA data transfer Disabled.
+ * | | |1 = PDMA data transfer Enabled.
+ * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
+ * @var EADC_T::SWTRG
+ * Offset: 0x54 ADC Sample Module Software Start Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[18:0] |SWTRG |ADC Sample Module 0~18 Software Force to Start ADC Conversion
+ * | | |0 = No effect.
+ * | | |1 = Cause an ADC conversion when the priority is given to sample module.
+ * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion
+ * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
+ * @var EADC_T::PENDSTS
+ * Offset: 0x58 ADC Start of Conversion Pending Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[18:0] |STPF |ADC Sample Module 0~18 Start of Conversion Pending Flag
+ * | | |Read:
+ * | | |0 = There is no pending conversion for sample module.
+ * | | |1 = Sample module ADC start of conversion is pending.
+ * | | |Write:
+ * | | |1 = clear pending flag & cancel the conversion for sample module.
+ * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
+ * @var EADC_T::OVSTS
+ * Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[18:0] |SPOVF |ADC SAMPLE0~18 Overrun Flag
+ * | | |0 = No sample module event overrun.
+ * | | |1 = Indicates a new sample module event is generated while an old one event is pending.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * @var EADC_T::SCTL[19]
+ * Offset: 0x80 ADC Sample Module 0~18 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |CHSEL |ADC Sample Module Channel Selection
+ * | | |00H = EADC_CH0 (slow channel).
+ * | | |01H = EADC_CH1 (slow channel).
+ * | | |02H = EADC_CH2 (slow channel).
+ * | | |03H = EADC_CH3 (slow channel).
+ * | | |04H = EADC_CH4 (slow channel).
+ * | | |05H = EADC_CH5 (slow channel).
+ * | | |06H = EADC_CH6 (slow channel).
+ * | | |07H = EADC_CH7 (slow channel).
+ * | | |08H = EADC_CH8 (slow channel).
+ * | | |09H = EADC_CH9 (slow channel).
+ * | | |0AH = EADC_CH10 (fast channel).
+ * | | |0BH = EADC_CH11 (fast channel).
+ * | | |0CH = EADC_CH12 (fast channel).
+ * | | |0DH = EADC_CH13 (fast channel).
+ * | | |0EH = EADC_CH14 (fast channel).
+ * | | |0FH = EADC_CH15 (fast channel).
+ * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit
+ * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source.
+ * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source.
+ * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit
+ * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source.
+ * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source.
+ * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection
+ * | | |Trigger delay clock frequency:
+ * | | |00 = ADC_CLK/1.
+ * | | |01 = ADC_CLK/2.
+ * | | |10 = ADC_CLK/4.
+ * | | |11 = ADC_CLK/16.
+ * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time
+ * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
+ * |[20:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection
+ * | | |0H = Disable trigger.
+ * | | |1H = External trigger from EADC0_ST pin input.
+ * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
+ * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
+ * | | |4H = Timer0 overflow pulse trigger.
+ * | | |5H = Timer1 overflow pulse trigger.
+ * | | |6H = Timer2 overflow pulse trigger.
+ * | | |7H = Timer3 overflow pulse trigger.
+ * | | |8H = EPWM0TG0.
+ * | | |9H = EPWM0TG1.
+ * | | |AH = EPWM0TG2.
+ * | | |BH = EPWM0TG3.
+ * | | |CH = EPWM0TG4.
+ * | | |DH = EPWM0TG5.
+ * | | |EH = EPWM1TG0.
+ * | | |FH = EPWM1TG1.
+ * | | |10H = EPWM1TG2.
+ * | | |11H = EPWM1TG3.
+ * | | |12H = EPWM1TG4.
+ * | | |13H = EPWM1TG5.
+ * | | |14H = BPWM0TG.
+ * | | |15H = BPWM1TG.
+ * | | |other = Reserved.
+ * |[22] |INTPOS |Interrupt Flag Position Select
+ * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion.
+ * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion.
+ * |[23] |DBMEN |Double Buffer Mode Enable Bit
+ * | | |0 = Sample has one sample result register. (default).
+ * | | |1 = Sample has two sample result registers.
+ * |[31:24] |EXTSMPT |ADC Sampling Time Extend
+ * | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.
+ * | | |The range of start delay time is from 0~255 ADC clock.
+ * @var EADC_T::INTSRC[4]
+ * Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit
+ * | | |0 = Sample Module 0 interrupt Disabled.
+ * | | |1 = Sample Module 0 interrupt Enabled.
+ * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit
+ * | | |0 = Sample Module 1 interrupt Disabled.
+ * | | |1 = Sample Module 1 interrupt Enabled.
+ * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit
+ * | | |0 = Sample Module 2 interrupt Disabled.
+ * | | |1 = Sample Module 2 interrupt Enabled.
+ * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit
+ * | | |0 = Sample Module 3 interrupt Disabled.
+ * | | |1 = Sample Module 3 interrupt Enabled.
+ * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit
+ * | | |0 = Sample Module 4 interrupt Disabled.
+ * | | |1 = Sample Module 4 interrupt Enabled.
+ * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit
+ * | | |0 = Sample Module 5 interrupt Disabled.
+ * | | |1 = Sample Module 5 interrupt Enabled.
+ * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit
+ * | | |0 = Sample Module 6 interrupt Disabled.
+ * | | |1 = Sample Module 6 interrupt Enabled.
+ * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit
+ * | | |0 = Sample Module 7 interrupt Disabled.
+ * | | |1 = Sample Module 7 interrupt Enabled.
+ * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit
+ * | | |0 = Sample Module 8 interrupt Disabled.
+ * | | |1 = Sample Module 8 interrupt Enabled.
+ * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit
+ * | | |0 = Sample Module 9 interrupt Disabled.
+ * | | |1 = Sample Module 9 interrupt Enabled.
+ * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit
+ * | | |0 = Sample Module 10 interrupt Disabled.
+ * | | |1 = Sample Module 10 interrupt Enabled.
+ * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit
+ * | | |0 = Sample Module 11 interrupt Disabled.
+ * | | |1 = Sample Module 11 interrupt Enabled.
+ * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit
+ * | | |0 = Sample Module 12 interrupt Disabled.
+ * | | |1 = Sample Module 12 interrupt Enabled.
+ * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit
+ * | | |0 = Sample Module 13 interrupt Disabled.
+ * | | |1 = Sample Module 13 interrupt Enabled.
+ * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit
+ * | | |0 = Sample Module 14 interrupt Disabled.
+ * | | |1 = Sample Module 14 interrupt Enabled.
+ * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit
+ * | | |0 = Sample Module 15 interrupt Disabled.
+ * | | |1 = Sample Module 15 interrupt Enabled.
+ * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit
+ * | | |0 = Sample Module 16 interrupt Disabled.
+ * | | |1 = Sample Module 16 interrupt Enabled.
+ * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit
+ * | | |0 = Sample Module 17 interrupt Disabled.
+ * | | |1 = Sample Module 17 interrupt Enabled.
+ * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit
+ * | | |0 = Sample Module 18 interrupt Disabled.
+ * | | |1 = Sample Module 18 interrupt Enabled.
+ * @var EADC_T::CMP[4]
+ * Offset: 0xE0 ADC Result Compare Register 0~3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADCMPEN |ADC Result Compare Enable Bit
+ * | | |0 = Compare Disabled.
+ * | | |1 = Compare Enabled.
+ * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
+ * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit
+ * | | |0 = Compare function interrupt Disabled.
+ * | | |1 = Compare function interrupt Enabled.
+ * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
+ * |[2] |CMPCOND |Compare Condition
+ * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
+ * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
+ * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
+ * |[7:3] |CMPSPL |Compare Sample Module Selection
+ * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
+ * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
+ * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
+ * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
+ * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
+ * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
+ * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
+ * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
+ * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
+ * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
+ * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
+ * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
+ * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
+ * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
+ * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
+ * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
+ * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
+ * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
+ * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
+ * |[11:8] |CMPMCNT |Compare Match Count
+ * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1
+ * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0
+ * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
+ * |[15] |CMPWEN |Compare Window Mode Enable Bit
+ * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched
+ * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched
+ * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched
+ * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
+ * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
+ * |[27:16] |CMPDAT |Comparison Data
+ * | | |The 12 bits data is used to compare with conversion result of specified sample module
+ * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
+ * @var EADC_T::STATUS0
+ * Offset: 0xF0 ADC Status Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag
+ * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).
+ * |[31:16] |OV |EADC_DAT0~15 Overrun Flag
+ * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).
+ * @var EADC_T::STATUS1
+ * Offset: 0xF4 ADC Status Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag
+ * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).
+ * |[18:16] |OV |EADC_DAT16~18 Overrun Flag
+ * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).
+ * @var EADC_T::STATUS2
+ * Offset: 0xF8 ADC Status Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADIF0 |ADC ADINT0 Interrupt Flag
+ * | | |0 = No ADINT0 interrupt pulse received.
+ * | | |1 = ADINT0 interrupt pulse has been received.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+ * |[1] |ADIF1 |ADC ADINT1 Interrupt Flag
+ * | | |0 = No ADINT1 interrupt pulse received.
+ * | | |1 = ADINT1 interrupt pulse has been received.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+ * |[2] |ADIF2 |ADC ADINT2 Interrupt Flag
+ * | | |0 = No ADINT2 interrupt pulse received.
+ * | | |1 = ADINT2 interrupt pulse has been received.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+ * |[3] |ADIF3 |ADC ADINT3 Interrupt Flag
+ * | | |0 = No ADINT3 interrupt pulse received.
+ * | | |1 = ADINT3 interrupt pulse has been received.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+ * |[4] |ADCMPF0 |ADC Compare 0 Flag
+ * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[5] |ADCMPF1 |ADC Compare 1 Flag
+ * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[6] |ADCMPF2 |ADC Compare 2 Flag
+ * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[7] |ADCMPF3 |ADC Compare 3 Flag
+ * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun
+ * | | |0 = ADINT0 interrupt flag is not overwritten to 1.
+ * | | |1 = ADINT0 interrupt flag is overwritten to 1.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun
+ * | | |0 = ADINT1 interrupt flag is not overwritten to 1.
+ * | | |1 = ADINT1 interrupt flag is overwritten to 1.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun
+ * | | |0 = ADINT2 interrupt flag is not overwritten to 1.
+ * | | |1 = ADINT2 interrupt flag is s overwritten to 1.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun
+ * | | |0 = ADINT3 interrupt flag is not overwritten to 1.
+ * | | |1 = ADINT3 interrupt flag is overwritten to 1.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only)
+ * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module
+ * | | |User can use it to monitor the external analog input pin voltage status.
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting.
+ * |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only)
+ * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module
+ * | | |User can use it to monitor the external analog input pin voltage status.
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting.
+ * |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only)
+ * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module
+ * | | |User can use it to monitor the external analog input pin voltage status.
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting.
+ * |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only)
+ * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module
+ * | | |User can use it to monitor the external analog input pin voltage status.
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting.
+ * |[20:16] |CHANNEL |Current Conversion Channel (Read Only)
+ * | | |This filed reflects ADC current conversion channel when BUSY=1.
+ * | | |It is read only.
+ * | | |00H = EADC_CH0.
+ * | | |01H = EADC_CH1.
+ * | | |02H = EADC_CH2.
+ * | | |03H = EADC_CH3.
+ * | | |04H = EADC_CH4.
+ * | | |05H = EADC_CH5.
+ * | | |06H = EADC_CH6.
+ * | | |07H = EADC_CH7.
+ * | | |08H = EADC_CH8.
+ * | | |09H = EADC_CH9.
+ * | | |0AH = EADC_CH10.
+ * | | |0BH = EADC_CH11.
+ * | | |0CH = EADC_CH12.
+ * | | |0DH = EADC_CH13.
+ * | | |0EH = EADC_CH14.
+ * | | |0FH = EADC_CH15.
+ * | | |10H = VBG.
+ * | | |11H = VTEMP.
+ * | | |12H = VBAT/4.
+ * |[23] |BUSY |Busy/Idle (Read Only)
+ * | | |0 = EADC is in idle state.
+ * | | |1 = EADC is busy at conversion.
+ * |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only)
+ * | | |n=0~3.
+ * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+ * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+ * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
+ * |[25] |STOVF |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only)
+ * | | |n=0~18.
+ * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+ * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+ * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
+ * |[26] |AVALID |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)
+ * | | |n=0~18.
+ * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+ * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+ * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
+ * |[27] |AOV |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only)
+ * | | |n=0~18.
+ * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+ * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+ * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1.
+ * @var EADC_T::STATUS3
+ * Offset: 0xFC ADC Status Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |CURSPL |ADC Current Sample Module
+ * | | |This register show the current ADC is controlled by which sample module control logic modules.
+ * | | |If the ADC is Idle, this bit filed will set to 0x1F.
+ * | | |This is a read only register.
+ * @var EADC_T::DDAT[4]
+ * Offset: 0x100 ADC Double Data Register 0 for Sample Module 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RESULT |ADC Conversion Results
+ * | | |This field contains 12 bits conversion results.
+ * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
+ * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
+ * |[16] |OV |Overrun Flag
+ * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
+ * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
+ * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1
+ * | | |It is cleared by hardware after EADC_DDAT register is read.
+ * |[17] |VALID |Valid Flag
+ * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
+ * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
+ * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read
+ * | | |(n=0~3).
+ * @var EADC_T::PWRM
+ * Offset: 0x110 ADC Power Management Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only)
+ * | | |0 = ADC is not ready for conversion may be in power down state or in the progress of start up.
+ * | | |1 = ADC is ready for conversion.
+ * |[1] |PWUCALEN |Power Up Calibration Function Enable Control
+ * | | |0 = Disable the function of calibration at power up.
+ * | | |1 = Enable the function of calibration at power up.
+ * | | |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following
+ * | | |{PWUCALEN, CALSEL } Description:
+ * | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate.
+ * | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate.
+ * | | |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up.
+ * | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up.
+ * |[3:2] |PWDMOD |ADC Power-down Mode
+ * | | |Set this bit fields to select ADC power down mode when system power-down.
+ * | | |00 = ADC Deep power down mode.
+ * | | |01 = ADC Power down.
+ * | | |10 = ADC Standby mode.
+ * | | |11 = ADC Deep power down mode.
+ * | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up
+ * |[19:8] |LDOSUT |ADC Internal LDO Start-up Time
+ * | | |Set this bit fields to control LDO start-up time
+ * | | |The minimum required LDO start-up time is 20us
+ * | | |LDO start-up time = (1/ADC_CLK) x LDOSUT.
+ * @var EADC_T::CALCTL
+ * Offset: 0x114 ADC Calibration Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |CALSTART |Calibration Functional Block Start
+ * | | |0 = Stops calibration functional block.
+ * | | |1 = Starts calibration functional block.
+ * | | |Note: This bit is set by SW and clear by HW after re-calibration finish
+ * |[2] |CALDONE |Calibration Functional Block Complete (Read Only)
+ * | | |0 = During a calibration.
+ * | | |1 = Calibration is completed.
+ * |[3] |CALSEL |Select Calibration Functional Block
+ * | | |0 = Load calibration word when calibration functional block is active.
+ * | | |1 = Execute calibration when calibration functional block is active.
+ * @var EADC_T::CALDWRD
+ * Offset: 0x118 ADC Calibration Load Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |CALWORD |Calibration Word Bits
+ * | | |Write to this register with the previous calibration word before load calibration action.
+ * | | |Read this register after calibration done.
+ * | | |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.
+ */
+ __I uint32_t DAT[19]; /*!< [0x0000] ADC Data Register 0~18 for Sample Module 0~18 */
+ __I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */
+ __IO uint32_t CTL; /*!< [0x0050] ADC Control Register */
+ __O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */
+ __IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */
+ __IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[8];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t SCTL[19]; /*!< [0x0080] ADC Sample Module 0~18 Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t INTSRC[4]; /*!< [0x00d0] ADC interrupt 0~3 Source Enable Control Register. */
+ __IO uint32_t CMP[4]; /*!< [0x00e0] ADC Result Compare Register 0~3 */
+ __I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */
+ __I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */
+ __IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */
+ __I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */
+ __I uint32_t DDAT[4]; /*!< [0x0100] ADC Double Data Register 0~3 for Sample Module 0~3 */
+ __IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */
+ __IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */
+ __IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t PDMACTL; /*!< [0x0130] ADC PDMA Control Register */
+} EADC_T;
+
+/**
+ @addtogroup EADC_CONST EADC Bit Field Definition
+ Constant Definitions for EADC Controller
+@{ */
+
+#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */
+#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */
+
+#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */
+#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */
+
+#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */
+#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */
+
+#define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */
+#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */
+
+#define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */
+#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */
+
+#define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */
+#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */
+
+#define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */
+#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */
+
+#define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */
+#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */
+
+#define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */
+#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */
+
+#define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */
+#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */
+
+#define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */
+#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */
+
+#define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */
+#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */
+
+#define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */
+#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */
+
+#define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */
+#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */
+
+#define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */
+#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */
+
+#define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */
+#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */
+
+#define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */
+#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */
+
+#define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */
+#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */
+
+#define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */
+#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */
+
+#define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */
+#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */
+
+#define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */
+#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */
+
+#define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */
+#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */
+
+#define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */
+#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */
+
+#define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */
+#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */
+
+#define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */
+#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */
+
+#define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */
+#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */
+
+#define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */
+#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */
+
+#define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */
+#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */
+
+#define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */
+#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */
+
+#define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */
+#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */
+
+#define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */
+#define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */
+
+#define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */
+#define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */
+
+#define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */
+#define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */
+
+#define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */
+#define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */
+
+#define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */
+#define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */
+
+#define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */
+#define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */
+
+#define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */
+#define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */
+
+#define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */
+#define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */
+
+#define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */
+#define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */
+
+#define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */
+#define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */
+
+#define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */
+#define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */
+
+#define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */
+#define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */
+
+#define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */
+#define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */
+
+#define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */
+#define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */
+
+#define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */
+#define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */
+
+#define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */
+#define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */
+
+#define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */
+#define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */
+
+#define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */
+#define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */
+
+#define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */
+#define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */
+
+#define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */
+#define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */
+
+#define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */
+#define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */
+
+#define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */
+#define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */
+
+#define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */
+#define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */
+
+#define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */
+#define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */
+
+#define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */
+#define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */
+
+#define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */
+#define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */
+
+#define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */
+#define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */
+
+#define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */
+#define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */
+
+#define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */
+#define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */
+
+#define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */
+#define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */
+
+#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */
+#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */
+
+#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */
+#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */
+
+#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */
+#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */
+
+#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */
+#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */
+
+#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */
+#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */
+
+#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */
+#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */
+
+#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */
+#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */
+
+#define EADC_CTL_RESSEL_Pos (6) /*!< EADC_T::CTL: RESSEL Position */
+#define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /*!< EADC_T::CTL: RESSEL Mask */
+
+#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */
+#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */
+
+#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */
+#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */
+
+#define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */
+#define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */
+
+#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */
+#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */
+
+#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */
+#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */
+
+#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */
+#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */
+
+#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */
+#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */
+
+#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */
+#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */
+
+#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */
+#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */
+
+#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */
+#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */
+
+#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */
+#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */
+
+#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */
+#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */
+
+#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */
+#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */
+
+#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */
+#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */
+
+#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */
+#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */
+
+#define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */
+#define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */
+
+#define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */
+#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */
+
+#define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */
+#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */
+
+#define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */
+#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */
+
+#define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */
+#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */
+
+#define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */
+#define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */
+
+#define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */
+#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */
+
+#define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */
+#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */
+
+#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */
+#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */
+
+#define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */
+#define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */
+
+#define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */
+#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */
+
+#define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */
+#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */
+
+#define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */
+#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */
+
+#define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */
+#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */
+
+#define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */
+#define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */
+
+#define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */
+#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */
+
+#define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */
+#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */
+
+#define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */
+#define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */
+
+#define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */
+#define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */
+
+#define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */
+#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */
+
+#define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */
+#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */
+
+#define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */
+#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */
+
+#define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */
+#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */
+
+#define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */
+#define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */
+
+#define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */
+#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */
+
+#define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */
+#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */
+
+#define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */
+#define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */
+
+#define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */
+#define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */
+
+#define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */
+#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */
+
+#define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */
+#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */
+
+#define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */
+#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */
+
+#define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */
+#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */
+
+#define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */
+#define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */
+
+#define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */
+#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */
+
+#define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */
+#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */
+
+#define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */
+#define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */
+
+#define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */
+#define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */
+
+#define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */
+#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */
+
+#define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */
+#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */
+
+#define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */
+#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */
+
+#define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */
+#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */
+
+#define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */
+#define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */
+
+#define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */
+#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */
+
+#define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */
+#define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */
+
+#define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */
+#define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */
+
+#define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */
+#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */
+
+#define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */
+#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */
+
+#define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */
+#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */
+
+#define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */
+#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */
+
+#define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */
+#define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */
+
+#define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */
+#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */
+
+#define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */
+#define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */
+
+#define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */
+#define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */
+
+#define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */
+#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */
+
+#define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */
+#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */
+
+#define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */
+#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */
+
+#define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */
+#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */
+
+#define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */
+#define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */
+
+#define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */
+#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */
+
+#define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */
+#define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */
+
+#define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */
+#define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */
+
+#define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */
+#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */
+
+#define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */
+#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */
+
+#define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */
+#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */
+
+#define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */
+#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */
+
+#define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */
+#define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */
+
+#define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */
+#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */
+
+#define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */
+#define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */
+
+#define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */
+#define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */
+
+#define EADC_SCTL8_EXTREN_Pos (4) /*!< EADC_T::SCTL8: EXTREN Position */
+#define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */
+
+#define EADC_SCTL8_EXTFEN_Pos (5) /*!< EADC_T::SCTL8: EXTFEN Position */
+#define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */
+
+#define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */
+#define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */
+
+#define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */
+#define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */
+
+#define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */
+#define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */
+
+#define EADC_SCTL8_INTPOS_Pos (22) /*!< EADC_T::SCTL8: INTPOS Position */
+#define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */
+
+#define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */
+#define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */
+
+#define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */
+#define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */
+
+#define EADC_SCTL9_EXTREN_Pos (4) /*!< EADC_T::SCTL9: EXTREN Position */
+#define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */
+
+#define EADC_SCTL9_EXTFEN_Pos (5) /*!< EADC_T::SCTL9: EXTFEN Position */
+#define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */
+
+#define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */
+#define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */
+
+#define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */
+#define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */
+
+#define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */
+#define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */
+
+#define EADC_SCTL9_INTPOS_Pos (22) /*!< EADC_T::SCTL9: INTPOS Position */
+#define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */
+
+#define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */
+#define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */
+
+#define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */
+#define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */
+
+#define EADC_SCTL10_EXTREN_Pos (4) /*!< EADC_T::SCTL10: EXTREN Position */
+#define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */
+
+#define EADC_SCTL10_EXTFEN_Pos (5) /*!< EADC_T::SCTL10: EXTFEN Position */
+#define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */
+
+#define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */
+#define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */
+
+#define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */
+#define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */
+
+#define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */
+#define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */
+
+#define EADC_SCTL10_INTPOS_Pos (22) /*!< EADC_T::SCTL10: INTPOS Position */
+#define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */
+
+#define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */
+#define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */
+
+#define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */
+#define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */
+
+#define EADC_SCTL11_EXTREN_Pos (4) /*!< EADC_T::SCTL11: EXTREN Position */
+#define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */
+
+#define EADC_SCTL11_EXTFEN_Pos (5) /*!< EADC_T::SCTL11: EXTFEN Position */
+#define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */
+
+#define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */
+#define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */
+
+#define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */
+#define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */
+
+#define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */
+#define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */
+
+#define EADC_SCTL11_INTPOS_Pos (22) /*!< EADC_T::SCTL11: INTPOS Position */
+#define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */
+
+#define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */
+#define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */
+
+#define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */
+#define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */
+
+#define EADC_SCTL12_EXTREN_Pos (4) /*!< EADC_T::SCTL12: EXTREN Position */
+#define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */
+
+#define EADC_SCTL12_EXTFEN_Pos (5) /*!< EADC_T::SCTL12: EXTFEN Position */
+#define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */
+
+#define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */
+#define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */
+
+#define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */
+#define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */
+
+#define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */
+#define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */
+
+#define EADC_SCTL12_INTPOS_Pos (22) /*!< EADC_T::SCTL12: INTPOS Position */
+#define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */
+
+#define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */
+#define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */
+
+#define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */
+#define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */
+
+#define EADC_SCTL13_EXTREN_Pos (4) /*!< EADC_T::SCTL13: EXTREN Position */
+#define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */
+
+#define EADC_SCTL13_EXTFEN_Pos (5) /*!< EADC_T::SCTL13: EXTFEN Position */
+#define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */
+
+#define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */
+#define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */
+
+#define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */
+#define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */
+
+#define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */
+#define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */
+
+#define EADC_SCTL13_INTPOS_Pos (22) /*!< EADC_T::SCTL13: INTPOS Position */
+#define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */
+
+#define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */
+#define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */
+
+#define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */
+#define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */
+
+#define EADC_SCTL14_EXTREN_Pos (4) /*!< EADC_T::SCTL14: EXTREN Position */
+#define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */
+
+#define EADC_SCTL14_EXTFEN_Pos (5) /*!< EADC_T::SCTL14: EXTFEN Position */
+#define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */
+
+#define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */
+#define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */
+
+#define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */
+#define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */
+
+#define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */
+#define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */
+
+#define EADC_SCTL14_INTPOS_Pos (22) /*!< EADC_T::SCTL14: INTPOS Position */
+#define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */
+
+#define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */
+#define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */
+
+#define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */
+#define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */
+
+#define EADC_SCTL15_EXTREN_Pos (4) /*!< EADC_T::SCTL15: EXTREN Position */
+#define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */
+
+#define EADC_SCTL15_EXTFEN_Pos (5) /*!< EADC_T::SCTL15: EXTFEN Position */
+#define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */
+
+#define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */
+#define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */
+
+#define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */
+#define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */
+
+#define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */
+#define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */
+
+#define EADC_SCTL15_INTPOS_Pos (22) /*!< EADC_T::SCTL15: INTPOS Position */
+#define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */
+
+#define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */
+#define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */
+
+#define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */
+#define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */
+
+#define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */
+#define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */
+
+#define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */
+#define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */
+
+#define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */
+#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */
+
+#define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */
+#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */
+
+#define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */
+#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */
+
+#define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */
+#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */
+
+#define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */
+#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */
+
+#define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */
+#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */
+
+#define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */
+#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */
+
+#define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */
+#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */
+
+#define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */
+#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */
+
+#define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */
+#define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */
+
+#define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */
+#define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */
+
+#define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */
+#define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */
+
+#define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */
+#define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */
+
+#define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */
+#define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */
+
+#define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */
+#define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */
+
+#define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */
+#define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */
+
+#define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */
+#define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */
+
+#define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */
+#define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */
+
+#define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */
+#define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */
+
+#define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */
+#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */
+
+#define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */
+#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */
+
+#define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */
+#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */
+
+#define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */
+#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */
+
+#define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */
+#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */
+
+#define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */
+#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */
+
+#define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */
+#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */
+
+#define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */
+#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */
+
+#define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */
+#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */
+
+#define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */
+#define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */
+
+#define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */
+#define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */
+
+#define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */
+#define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */
+
+#define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */
+#define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */
+
+#define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */
+#define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */
+
+#define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */
+#define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */
+
+#define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */
+#define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */
+
+#define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */
+#define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */
+
+#define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */
+#define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */
+
+#define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */
+#define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */
+
+#define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */
+#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */
+
+#define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */
+#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */
+
+#define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */
+#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */
+
+#define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */
+#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */
+
+#define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */
+#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */
+
+#define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */
+#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */
+
+#define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */
+#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */
+
+#define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */
+#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */
+
+#define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */
+#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */
+
+#define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */
+#define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */
+
+#define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */
+#define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */
+
+#define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */
+#define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */
+
+#define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */
+#define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */
+
+#define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */
+#define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */
+
+#define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */
+#define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */
+
+#define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */
+#define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */
+
+#define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */
+#define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */
+
+#define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */
+#define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */
+
+#define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */
+#define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */
+
+#define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */
+#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */
+
+#define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */
+#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */
+
+#define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */
+#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */
+
+#define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */
+#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */
+
+#define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */
+#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */
+
+#define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */
+#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */
+
+#define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */
+#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */
+
+#define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */
+#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */
+
+#define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */
+#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */
+
+#define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */
+#define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */
+
+#define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */
+#define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */
+
+#define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */
+#define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */
+
+#define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */
+#define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */
+
+#define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */
+#define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */
+
+#define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */
+#define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */
+
+#define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */
+#define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */
+
+#define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */
+#define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */
+
+#define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */
+#define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */
+
+#define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */
+#define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */
+
+#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */
+#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */
+
+#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */
+#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */
+
+#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */
+#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */
+
+#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */
+#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */
+
+#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */
+#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */
+
+#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */
+#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */
+
+#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */
+#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */
+
+#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */
+#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */
+
+#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */
+#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */
+
+#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */
+#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */
+
+#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */
+#define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */
+
+#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */
+#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */
+
+#define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */
+#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */
+
+#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */
+#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */
+
+#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */
+#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */
+
+#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */
+#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */
+
+#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */
+#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */
+
+#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */
+#define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */
+
+#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */
+#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */
+
+#define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */
+#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */
+
+#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */
+#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */
+
+#define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */
+#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */
+
+#define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */
+#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */
+
+#define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */
+#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */
+
+#define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */
+#define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */
+
+#define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */
+#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */
+
+#define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */
+#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */
+
+#define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */
+#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */
+
+#define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */
+#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */
+
+#define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */
+#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */
+
+#define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */
+#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */
+
+#define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */
+#define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */
+
+#define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */
+#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */
+
+#define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */
+#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */
+
+#define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */
+#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */
+
+#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */
+#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */
+
+#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */
+#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */
+
+#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */
+#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */
+
+#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */
+#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */
+
+#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */
+#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */
+
+#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */
+#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */
+
+#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */
+#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */
+
+#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */
+#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */
+
+#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */
+#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */
+
+#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */
+#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */
+
+#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */
+#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */
+
+#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */
+#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */
+
+#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */
+#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */
+
+#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */
+#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */
+
+#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */
+#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */
+
+#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */
+#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */
+
+#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */
+#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */
+
+#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */
+#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */
+
+#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */
+#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */
+
+#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */
+#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */
+
+#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */
+#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */
+
+#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */
+#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */
+
+#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */
+#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */
+
+#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */
+#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */
+
+#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */
+#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */
+
+#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */
+#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */
+
+#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */
+#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */
+
+#define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */
+#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */
+
+#define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */
+#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */
+
+#define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */
+#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */
+
+#define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */
+#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */
+
+#define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */
+#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */
+
+#define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */
+#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */
+
+#define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */
+#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */
+
+#define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */
+#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */
+
+#define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */
+#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */
+
+#define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */
+#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */
+
+#define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */
+#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */
+
+#define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */
+#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */
+
+#define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */
+#define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */
+
+#define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */
+#define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */
+
+#define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */
+#define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */
+
+#define EADC_PWRM_LDOSUT_Pos (8) /*!< EADC_T::PWRM: LDOSUT Position */
+#define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /*!< EADC_T::PWRM: LDOSUT Mask */
+
+#define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */
+#define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */
+
+#define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */
+#define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */
+
+#define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */
+#define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */
+
+#define EADC_CALDWRD_CALWORD_Pos (0) /*!< EADC_T::CALDWRD: CALWORD Position */
+#define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /*!< EADC_T::CALDWRD: CALWORD Mask */
+
+/**@}*/ /* EADC_CONST */
+/**@}*/ /* end of EADC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __EADC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ebi_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ebi_reg.h
new file mode 100644
index 00000000000..9a48d3c286d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ebi_reg.h
@@ -0,0 +1,429 @@
+/**************************************************************************//**
+ * @file ebi_reg.h
+ * @version V1.00
+ * @brief EBI register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EBI_REG_H__
+#define __EBI_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup EBI External Bus Interface Controller(EBI)
+ Memory Mapped Structure for EBI Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var EBI_T::CTL0
+ * Offset: 0x00 External Bus Interface Bank0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |EN |EBI Enable Bit
+ * | | |This bit is the functional enable bit for EBI.
+ * | | |0 = EBI function Disabled.
+ * | | |1 = EBI function Enabled.
+ * |[1] |DW16 |EBI Data Width 16-bit Select
+ * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
+ * | | |0 = EBI data width is 8-bit.
+ * | | |1 = EBI data width is 16-bit.
+ * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
+ * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
+ * | | |0 = Chip select pin (EBI_nCS) is active low.
+ * | | |1 = Chip select pin (EBI_nCS) is active high.
+ * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
+ * | | |0 = Address/Data Bus Separating Mode Disabled.
+ * | | |1 = Address/Data Bus Separating Mode Enabled.
+ * |[4] |CACCESS |Continuous Data Access Mode
+ * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
+ * | | |0 = Continuous data access mode Disabled.
+ * | | |1 = Continuous data access mode Enabled.
+ * |[10:8] |MCLKDIV |External Output Clock Divider
+ * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+ * | | |000 = HCLK/1.
+ * | | |001 = HCLK/2.
+ * | | |010 = HCLK/4.
+ * | | |011 = HCLK/8.
+ * | | |100 = HCLK/16.
+ * | | |101 = HCLK/32.
+ * | | |110 = HCLK/64.
+ * | | |111 = HCLK/128.
+ * |[18:16] |TALE |Extend Time of ALE
+ * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+ * | | |tALE = (TALE+1)*EBI_MCLK.
+ * | | |Note: This field only available in EBI_CTL0 register
+ * |[24] |WBUFEN |EBI Write Buffer Enable Bit
+ * | | |0 = EBI write buffer Disabled.
+ * | | |1 = EBI write buffer Enabled.
+ * | | |Note: This bit only available in EBI_CTL0 register
+ * @var EBI_T::TCTL0
+ * Offset: 0x04 External Bus Interface Bank0 Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:3] |TACC |EBI Data Access Time
+ * | | |TACC define data access time (tACC).
+ * | | |tACC = (TACC +1) * EBI_MCLK.
+ * |[10:8] |TAHD |EBI Data Access Hold Time
+ * | | |TAHD define data access hold time (tAHD).
+ * | | |tAHD = (TAHD +1) * EBI_MCLK.
+ * |[15:12] |W2X |Idle Cycle After Write
+ * | | |This field defines the number of W2X idle cycle.
+ * | | |W2X idle cycle = (W2X * EBI_MCLK).
+ * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+ * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+ * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+ * |[27:24] |R2R |Idle Cycle Between Read-to-read
+ * | | |This field defines the number of R2R idle cycle.
+ * | | |R2R idle cycle = (R2R * EBI_MCLK).
+ * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+ * @var EBI_T::CTL1
+ * Offset: 0x10 External Bus Interface Bank1 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |EN |EBI Enable Bit
+ * | | |This bit is the functional enable bit for EBI.
+ * | | |0 = EBI function Disabled.
+ * | | |1 = EBI function Enabled.
+ * |[1] |DW16 |EBI Data Width 16-bit Select
+ * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
+ * | | |0 = EBI data width is 8-bit.
+ * | | |1 = EBI data width is 16-bit.
+ * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
+ * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
+ * | | |0 = Chip select pin (EBI_nCS) is active low.
+ * | | |1 = Chip select pin (EBI_nCS) is active high.
+ * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
+ * | | |0 = Address/Data Bus Separating Mode Disabled.
+ * | | |1 = Address/Data Bus Separating Mode Enabled.
+ * |[4] |CACCESS |Continuous Data Access Mode
+ * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
+ * | | |0 = Continuous data access mode Disabled.
+ * | | |1 = Continuous data access mode Enabled.
+ * |[10:8] |MCLKDIV |External Output Clock Divider
+ * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+ * | | |000 = HCLK/1.
+ * | | |001 = HCLK/2.
+ * | | |010 = HCLK/4.
+ * | | |011 = HCLK/8.
+ * | | |100 = HCLK/16.
+ * | | |101 = HCLK/32.
+ * | | |110 = HCLK/64.
+ * | | |111 = HCLK/128.
+ * |[18:16] |TALE |Extend Time of ALE
+ * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+ * | | |tALE = (TALE+1)*EBI_MCLK.
+ * | | |Note: This field only available in EBI_CTL0 register
+ * |[24] |WBUFEN |EBI Write Buffer Enable Bit
+ * | | |0 = EBI write buffer Disabled.
+ * | | |1 = EBI write buffer Enabled.
+ * | | |Note: This bit only available in EBI_CTL0 register
+ * @var EBI_T::TCTL1
+ * Offset: 0x14 External Bus Interface Bank1 Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:3] |TACC |EBI Data Access Time
+ * | | |TACC define data access time (tACC).
+ * | | |tACC = (TACC +1) * EBI_MCLK.
+ * |[10:8] |TAHD |EBI Data Access Hold Time
+ * | | |TAHD define data access hold time (tAHD).
+ * | | |tAHD = (TAHD +1) * EBI_MCLK.
+ * |[15:12] |W2X |Idle Cycle After Write
+ * | | |This field defines the number of W2X idle cycle.
+ * | | |W2X idle cycle = (W2X * EBI_MCLK).
+ * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+ * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+ * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+ * |[27:24] |R2R |Idle Cycle Between Read-to-read
+ * | | |This field defines the number of R2R idle cycle.
+ * | | |R2R idle cycle = (R2R * EBI_MCLK).
+ * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+ * @var EBI_T::CTL2
+ * Offset: 0x20 External Bus Interface Bank2 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |EN |EBI Enable Bit
+ * | | |This bit is the functional enable bit for EBI.
+ * | | |0 = EBI function Disabled.
+ * | | |1 = EBI function Enabled.
+ * |[1] |DW16 |EBI Data Width 16-bit Select
+ * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
+ * | | |0 = EBI data width is 8-bit.
+ * | | |1 = EBI data width is 16-bit.
+ * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
+ * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
+ * | | |0 = Chip select pin (EBI_nCS) is active low.
+ * | | |1 = Chip select pin (EBI_nCS) is active high.
+ * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
+ * | | |0 = Address/Data Bus Separating Mode Disabled.
+ * | | |1 = Address/Data Bus Separating Mode Enabled.
+ * |[4] |CACCESS |Continuous Data Access Mode
+ * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
+ * | | |0 = Continuous data access mode Disabled.
+ * | | |1 = Continuous data access mode Enabled.
+ * |[10:8] |MCLKDIV |External Output Clock Divider
+ * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+ * | | |000 = HCLK/1.
+ * | | |001 = HCLK/2.
+ * | | |010 = HCLK/4.
+ * | | |011 = HCLK/8.
+ * | | |100 = HCLK/16.
+ * | | |101 = HCLK/32.
+ * | | |110 = HCLK/64.
+ * | | |111 = HCLK/128.
+ * |[18:16] |TALE |Extend Time of ALE
+ * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+ * | | |tALE = (TALE+1)*EBI_MCLK.
+ * | | |Note: This field only available in EBI_CTL0 register
+ * |[24] |WBUFEN |EBI Write Buffer Enable Bit
+ * | | |0 = EBI write buffer Disabled.
+ * | | |1 = EBI write buffer Enabled.
+ * | | |Note: This bit only available in EBI_CTL0 register
+ * @var EBI_T::TCTL2
+ * Offset: 0x24 External Bus Interface Bank2 Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:3] |TACC |EBI Data Access Time
+ * | | |TACC define data access time (tACC).
+ * | | |tACC = (TACC +1) * EBI_MCLK.
+ * |[10:8] |TAHD |EBI Data Access Hold Time
+ * | | |TAHD define data access hold time (tAHD).
+ * | | |tAHD = (TAHD +1) * EBI_MCLK.
+ * |[15:12] |W2X |Idle Cycle After Write
+ * | | |This field defines the number of W2X idle cycle.
+ * | | |W2X idle cycle = (W2X * EBI_MCLK).
+ * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+ * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+ * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+ * |[27:24] |R2R |Idle Cycle Between Read-to-read
+ * | | |This field defines the number of R2R idle cycle.
+ * | | |R2R idle cycle = (R2R * EBI_MCLK).
+ * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+ */
+ __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
+ __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
+ __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
+ __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
+
+} EBI_T;
+
+/**
+ @addtogroup EBI_CONST EBI Bit Field Definition
+ Constant Definitions for EBI Controller
+@{ */
+
+#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */
+#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */
+
+#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */
+#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */
+
+#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */
+#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */
+
+#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */
+#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */
+
+#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */
+#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */
+
+#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */
+#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */
+
+#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */
+#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */
+
+#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */
+#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */
+
+#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */
+#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */
+
+#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */
+#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */
+
+#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */
+#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */
+
+#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */
+#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */
+
+#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */
+#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */
+
+#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */
+#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */
+
+#define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
+#define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
+
+#define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
+#define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
+
+#define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
+#define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
+
+#define EBI_CTL0_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */
+#define EBI_CTL0_ADSEPEN_Msk (0x1ul << EBI_CTL0_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */
+
+#define EBI_CTL0_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
+#define EBI_CTL0_CACCESS_Msk (0x1ul << EBI_CTL0_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
+
+#define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
+#define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
+
+#define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
+#define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
+
+#define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
+#define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
+
+#define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
+#define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
+
+#define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
+#define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
+
+#define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
+#define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
+
+#define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
+#define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
+
+#define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
+#define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
+
+#define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
+#define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
+
+#define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */
+#define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */
+
+#define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */
+#define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */
+
+#define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */
+#define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */
+
+#define EBI_CTL1_ADSEPEN_Pos (3) /*!< EBI_T::CTL1: ADSEPEN Position */
+#define EBI_CTL1_ADSEPEN_Msk (0x1ul << EBI_CTL1_ADSEPEN_Pos) /*!< EBI_T::CTL1: ADSEPEN Mask */
+
+#define EBI_CTL1_CACCESS_Pos (4) /*!< EBI_T::CTL1: CACCESS Position */
+#define EBI_CTL1_CACCESS_Msk (0x1ul << EBI_CTL1_CACCESS_Pos) /*!< EBI_T::CTL1: CACCESS Mask */
+
+#define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */
+#define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */
+
+#define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */
+#define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */
+
+#define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */
+#define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */
+
+#define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */
+#define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */
+
+#define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */
+#define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */
+
+#define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */
+#define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */
+
+#define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */
+#define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */
+
+#define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */
+#define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */
+
+#define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */
+#define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */
+
+#define EBI_CTL2_EN_Pos (0) /*!< EBI_T::CTL2: EN Position */
+#define EBI_CTL2_EN_Msk (0x1ul << EBI_CTL2_EN_Pos) /*!< EBI_T::CTL2: EN Mask */
+
+#define EBI_CTL2_DW16_Pos (1) /*!< EBI_T::CTL2: DW16 Position */
+#define EBI_CTL2_DW16_Msk (0x1ul << EBI_CTL2_DW16_Pos) /*!< EBI_T::CTL2: DW16 Mask */
+
+#define EBI_CTL2_CSPOLINV_Pos (2) /*!< EBI_T::CTL2: CSPOLINV Position */
+#define EBI_CTL2_CSPOLINV_Msk (0x1ul << EBI_CTL2_CSPOLINV_Pos) /*!< EBI_T::CTL2: CSPOLINV Mask */
+
+#define EBI_CTL2_ADSEPEN_Pos (3) /*!< EBI_T::CTL2: ADSEPEN Position */
+#define EBI_CTL2_ADSEPEN_Msk (0x1ul << EBI_CTL2_ADSEPEN_Pos) /*!< EBI_T::CTL2: ADSEPEN Mask */
+
+#define EBI_CTL2_CACCESS_Pos (4) /*!< EBI_T::CTL2: CACCESS Position */
+#define EBI_CTL2_CACCESS_Msk (0x1ul << EBI_CTL2_CACCESS_Pos) /*!< EBI_T::CTL2: CACCESS Mask */
+
+#define EBI_CTL2_MCLKDIV_Pos (8) /*!< EBI_T::CTL2: MCLKDIV Position */
+#define EBI_CTL2_MCLKDIV_Msk (0x7ul << EBI_CTL2_MCLKDIV_Pos) /*!< EBI_T::CTL2: MCLKDIV Mask */
+
+#define EBI_CTL2_TALE_Pos (16) /*!< EBI_T::CTL2: TALE Position */
+#define EBI_CTL2_TALE_Msk (0x7ul << EBI_CTL2_TALE_Pos) /*!< EBI_T::CTL2: TALE Mask */
+
+#define EBI_CTL2_WBUFEN_Pos (24) /*!< EBI_T::CTL2: WBUFEN Position */
+#define EBI_CTL2_WBUFEN_Msk (0x1ul << EBI_CTL2_WBUFEN_Pos) /*!< EBI_T::CTL2: WBUFEN Mask */
+
+#define EBI_TCTL2_TACC_Pos (3) /*!< EBI_T::TCTL2: TACC Position */
+#define EBI_TCTL2_TACC_Msk (0x1ful << EBI_TCTL2_TACC_Pos) /*!< EBI_T::TCTL2: TACC Mask */
+
+#define EBI_TCTL2_TAHD_Pos (8) /*!< EBI_T::TCTL2: TAHD Position */
+#define EBI_TCTL2_TAHD_Msk (0x7ul << EBI_TCTL2_TAHD_Pos) /*!< EBI_T::TCTL2: TAHD Mask */
+
+#define EBI_TCTL2_W2X_Pos (12) /*!< EBI_T::TCTL2: W2X Position */
+#define EBI_TCTL2_W2X_Msk (0xful << EBI_TCTL2_W2X_Pos) /*!< EBI_T::TCTL2: W2X Mask */
+
+#define EBI_TCTL2_RAHDOFF_Pos (22) /*!< EBI_T::TCTL2: RAHDOFF Position */
+#define EBI_TCTL2_RAHDOFF_Msk (0x1ul << EBI_TCTL2_RAHDOFF_Pos) /*!< EBI_T::TCTL2: RAHDOFF Mask */
+
+#define EBI_TCTL2_WAHDOFF_Pos (23) /*!< EBI_T::TCTL2: WAHDOFF Position */
+#define EBI_TCTL2_WAHDOFF_Msk (0x1ul << EBI_TCTL2_WAHDOFF_Pos) /*!< EBI_T::TCTL2: WAHDOFF Mask */
+
+#define EBI_TCTL2_R2R_Pos (24) /*!< EBI_T::TCTL2: R2R Position */
+#define EBI_TCTL2_R2R_Msk (0xful << EBI_TCTL2_R2R_Pos) /*!< EBI_T::TCTL2: R2R Mask */
+
+/**@}*/ /* EBI_CONST */
+/**@}*/ /* end of EBI register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __EBI_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ecap_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ecap_reg.h
new file mode 100644
index 00000000000..d22d9dc4de8
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ecap_reg.h
@@ -0,0 +1,390 @@
+/**************************************************************************//**
+ * @file ecap_reg.h
+ * @version V1.00
+ * @brief ECAP register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __ECAP_REG_H__
+#define __ECAP_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup ECAP Enhanced Input Capture Timer(ECAP)
+ Memory Mapped Structure for ECAP Controller
+@{ */
+
+typedef struct
+{
+
+ /**
+ * @var ECAP_T::CNT
+ * Offset: 0x00 Input Capture Counter (24-bit up counter)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CNT |Input Capture Timer/Counter
+ * | | |The input Capture Timer/Counter is a 24-bit up-counting counter
+ * | | |The clock source for the counter is from the clock divider
+ * @var ECAP_T::HLD0
+ * Offset: 0x04 Input Capture Hold Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |HOLD |Input Capture Counter Hold Register
+ * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+ * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+ * @var ECAP_T::HLD1
+ * Offset: 0x08 Input Capture Hold Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |HOLD |Input Capture Counter Hold Register
+ * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+ * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+ * @var ECAP_T::HLD2
+ * Offset: 0x0C Input Capture Hold Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |HOLD |Input Capture Counter Hold Register
+ * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+ * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+ * @var ECAP_T::CNTCMP
+ * Offset: 0x10 Input Capture Compare Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CNTCMP |Input Capture Counter Compare Register
+ * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
+ * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
+ * @var ECAP_T::CTL0
+ * Offset: 0x14 Input Capture Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
+ * | | |To determine the sampling frequency of the Noise Filter clock
+ * | | |000 = CAP_CLK.
+ * | | |001 = CAP_CLK/2.
+ * | | |010 = CAP_CLK/4.
+ * | | |011 = CAP_CLK/16.
+ * | | |100 = CAP_CLK/32.
+ * | | |101 = CAP_CLK/64.
+ * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control
+ * | | |0 = Noise filter of Input Capture Enabled.
+ * | | |1 = Noise filter of Input Capture Disabled (Bypass).
+ * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control
+ * | | |0 = IC0 input to Input Capture Unit Disabled.
+ * | | |1 = IC0 input to Input Capture Unit Enabled.
+ * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control
+ * | | |0 = IC1 input to Input Capture Unit Disabled.
+ * | | |1 = IC1 input to Input Capture Unit Enabled.
+ * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control
+ * | | |0 = IC2 input to Input Capture Unit Disabled.
+ * | | |1 = IC2 input to Input Capture Unit Enabled.
+ * |[9:8] |CAPSEL0 |CAP0 Input Source Selection
+ * | | |00 = CAP0 input is from port pin ICAP0.
+ * | | |01 = Reserved.
+ * | | |10 = CAP0 input is from signal CHA of QEI controller unit n.
+ * | | |11 = Reserved.
+ * | | |Note: Input capture unit n matches QEIn, where n = 0~1.
+ * |[11:10] |CAPSEL1 |CAP1 Input Source Selection
+ * | | |00 = CAP1 input is from port pin ICAP1.
+ * | | |01 = Reserved.
+ * | | |10 = CAP1 input is from signal CHB of QEI controller unit n.
+ * | | |11 = Reserved.
+ * | | |Note: Input capture unit n matches QEIn, where n = 0~1.
+ * |[13:12] |CAPSEL2 |CAP2 Input Source Selection
+ * | | |00 = CAP2 input is from port pin ICAP2.
+ * | | |01 = Reserved.
+ * | | |10 = CAP2 input is from signal CHX of QEI controller unit n.
+ * | | |11 = Reserved.
+ * | | |Note: Input capture unit n matches QEIn, where n = 0~1.
+ * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
+ * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
+ * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
+ * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
+ * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
+ * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
+ * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
+ * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
+ * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
+ * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control
+ * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
+ * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
+ * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control
+ * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
+ * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
+ * |[24] |CNTEN |Input Capture Counter Start Counting Control
+ * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
+ * | | |0 = ECAP_CNT stop counting.
+ * | | |1 = ECAP_CNT starts up-counting.
+ * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control
+ * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
+ * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
+ * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
+ * |[28] |CMPEN |Compare Function Enable Control
+ * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
+ * | | |0 = The compare function Disabled.
+ * | | |1 = The compare function Enabled.
+ * |[29] |CAPEN |Input Capture Timer/Counter Enable Control
+ * | | |0 = Input Capture function Disabled.
+ * | | |1 = Input Capture function Enabled.
+ * @var ECAP_T::CTL1
+ * Offset: 0x18 Input Capture Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection
+ * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change
+ * | | |00 = Detect rising edge only.
+ * | | |01 = Detect falling edge only.
+ * | | |1x = Detect both rising and falling edge.
+ * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection
+ * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change
+ * | | |00 = Detect rising edge only.
+ * | | |01 = Detect falling edge only.
+ * | | |1x = Detect both rising and falling edge.
+ * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection
+ * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
+ * | | |00 = Detect rising edge only.
+ * | | |01 = Detect falling edge only.
+ * | | |1x = Detect both rising and falling edge.
+ * |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
+ * | | |0 = The reload triggered by Event CAPTE0 Disabled.
+ * | | |1 = The reload triggered by Event CAPTE0 Enabled.
+ * |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
+ * | | |0 = The reload triggered by Event CAPTE1 Disabled.
+ * | | |1 = The reload triggered by Event CAPTE1 Enabled.
+ * |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
+ * | | |0 = The reload triggered by Event CAPTE2 Disabled.
+ * | | |1 = The reload triggered by Event CAPTE2 Enabled.
+ * |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
+ * | | |0 = The reload triggered by CAPOV Disabled.
+ * | | |1 = The reload triggered by CAPOV Enabled.
+ * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection
+ * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
+ * | | |000 = CAP_CLK/1.
+ * | | |001 = CAP_CLK/4.
+ * | | |010 = CAP_CLK/16.
+ * | | |011 = CAP_CLK/32.
+ * | | |100 = CAP_CLK/64.
+ * | | |101 = CAP_CLK/96.
+ * | | |110 = CAP_CLK/112.
+ * | | |111 = CAP_CLK/128.
+ * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
+ * | | |Select the capture timer/counter clock source.
+ * | | |00 = CAP_CLK (default).
+ * | | |01 = CAP0.
+ * | | |10 = CAP1.
+ * | | |11 = CAP2.
+ * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
+ * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
+ * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
+ * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
+ * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
+ * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
+ * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
+ * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
+ * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
+ * @var ECAP_T::STATUS
+ * Offset: 0x1C Input Capture Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag
+ * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
+ * | | |0 = No valid edge change has been detected at CAP0 input since last clear.
+ * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear.
+ * | | |Note: This bit is only cleared by writing 1 to it.
+ * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag
+ * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
+ * | | |0 = No valid edge change has been detected at CAP1 input since last clear.
+ * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear.
+ * | | |Note: This bit is only cleared by writing 1 to it.
+ * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag
+ * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
+ * | | |0 = No valid edge change has been detected at CAP2 input since last clear.
+ * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear.
+ * | | |Note: This bit is only cleared by writing 1 to it.
+ * |[4] |CAPCMPF |Input Capture Compare-match Flag
+ * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
+ * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
+ * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
+ * | | |Note: This bit is only cleared by writing 1 to it.
+ * |[5] |CAPOVF |Input Capture Counter Overflow Flag
+ * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
+ * | | |0 = No overflow event has occurred since last clear.
+ * | | |1 = Overflow event(s) has/have occurred since last clear.
+ * | | |Note: This bit is only cleared by writing 1 to it.
+ * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only)
+ * | | |Reflecting the value of input channel 0, CAP0
+ * | | |(The bit is read only and write is ignored)
+ * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only)
+ * | | |Reflecting the value of input channel 1, CAP1
+ * | | |(The bit is read only and write is ignored)
+ * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only)
+ * | | |Reflecting the value of input channel 2, CAP2.
+ * | | |(The bit is read only and write is ignored)
+ */
+ __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */
+ __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */
+ __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */
+ __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */
+ __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */
+ __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */
+ __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */
+ __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */
+
+} ECAP_T;
+
+/**
+ @addtogroup ECAP_CONST ECAP Bit Field Definition
+ Constant Definitions for ECAP Controller
+@{ */
+
+#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */
+#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */
+
+#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */
+#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */
+
+#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */
+#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */
+
+#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */
+#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */
+
+#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */
+#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */
+
+#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */
+#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */
+
+#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */
+#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */
+
+#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */
+#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */
+
+#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */
+#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */
+
+#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */
+#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */
+
+#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */
+#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */
+
+#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */
+#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */
+
+#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */
+#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */
+
+#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */
+#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */
+
+#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */
+#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */
+
+#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */
+#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */
+
+#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */
+#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */
+
+#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */
+#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */
+
+#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */
+#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */
+
+#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */
+#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */
+
+#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */
+#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */
+
+#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */
+#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */
+
+#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */
+#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */
+
+#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */
+#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */
+
+#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */
+#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */
+
+#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */
+#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */
+
+#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */
+#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */
+
+#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */
+#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */
+
+#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */
+#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */
+
+#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */
+#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */
+
+#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */
+#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */
+
+#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */
+#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */
+
+#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */
+#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */
+
+#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */
+#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */
+
+#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */
+#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */
+
+#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */
+#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */
+
+#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */
+#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */
+
+#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */
+#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */
+
+#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */
+#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */
+
+#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */
+#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */
+
+#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */
+#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */
+
+#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */
+#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */
+
+/**@}*/ /* ECAP_CONST */
+/**@}*/ /* end of ECAP register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __ECAP_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/emac_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/emac_reg.h
new file mode 100644
index 00000000000..831df4a3a1f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/emac_reg.h
@@ -0,0 +1,2063 @@
+/**************************************************************************//**
+ * @file emac_reg.h
+ * @version V1.00
+ * @brief EMAC register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EMAC_REG_H__
+#define __EMAC_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup EMAC Ethernet MAC Controller(EMAC)
+ Memory Mapped Structure for EMAC Controller
+@{ */
+
+typedef struct
+{
+
+ /**
+ * @var EMAC_T::CAMCTL
+ * Offset: 0x00 CAM Comparison Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |AUP |Accept Unicast Packet
+ * | | |The AUP controls the unicast packet reception
+ * | | |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.
+ * | | |0 = EMAC receives packet depends on the CAM comparison result.
+ * | | |1 = EMAC receives all unicast packets.
+ * |[1] |AMP |Accept Multicast Packet
+ * | | |The AMP controls the multicast packet reception
+ * | | |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.
+ * | | |0 = EMAC receives packet depends on the CAM comparison result.
+ * | | |1 = EMAC receives all multicast packets.
+ * |[2] |ABP |Accept Broadcast Packet
+ * | | |The ABP controls the broadcast packet reception
+ * | | |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.
+ * | | |0 = EMAC receives packet depends on the CAM comparison result.
+ * | | |1 = EMAC receives all broadcast packets.
+ * |[3] |COMPEN |Complement CAM Comparison Enable Bit
+ * | | |The COMPEN controls the complement of the CAM comparison result
+ * | | |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address
+ * | | |configured in CAM entry will be dropped
+ * | | |And the incoming packet with destination MAC address does not configured in any CAM entry will be received.
+ * | | |0 = Complement CAM comparison result Disabled.
+ * | | |1 = Complement CAM comparison result Enabled.
+ * |[4] |CMPEN |CAM Compare Enable Bit
+ * | | |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition
+ * | | |If software wants to receive a packet with specific destination MAC address, configures the MAC address
+ * | | |into CAM 12~0, then enables that CAM entry and set CMPEN to 1.
+ * | | |0 = CAM comparison function for destination MAC address recognition Disabled.
+ * | | |1 = CAM comparison function for destination MAC address recognition Enabled.
+ * @var EMAC_T::CAMEN
+ * Offset: 0x04 CAM Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAMxEN |CAM Entry X Enable Bit
+ * | | |The CAMxEN controls the validation of CAM entry x.
+ * | | |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission
+ * | | |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM
+ * | | |entries all must be enabled first.
+ * | | |0 = CAM entry x Disabled.
+ * | | |1 = CAM entry x Enabled.
+ * @var EMAC_T::CAM0M
+ * Offset: 0x08 CAM0 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM0L
+ * Offset: 0x0C CAM0 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM1M
+ * Offset: 0x10 CAM1 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM1L
+ * Offset: 0x14 CAM1 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM2M
+ * Offset: 0x18 CAM2 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM2L
+ * Offset: 0x1C CAM2 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM3M
+ * Offset: 0x20 CAM3 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM3L
+ * Offset: 0x24 CAM3 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM4M
+ * Offset: 0x28 CAM4 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM4L
+ * Offset: 0x2C CAM4 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM5M
+ * Offset: 0x30 CAM5 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM5L
+ * Offset: 0x34 CAM5 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM6M
+ * Offset: 0x38 CAM6 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM6L
+ * Offset: 0x3C CAM6 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM7M
+ * Offset: 0x40 CAM7 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM7L
+ * Offset: 0x44 CAM7 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM8M
+ * Offset: 0x48 CAM8 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM8L
+ * Offset: 0x4C CAM8 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM9M
+ * Offset: 0x50 CAM9 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM9L
+ * Offset: 0x54 CAM9 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM10M
+ * Offset: 0x58 CAM10 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM10L
+ * Offset: 0x5C CAM10 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM11M
+ * Offset: 0x60 CAM11 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM11L
+ * Offset: 0x64 CAM11 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM12M
+ * Offset: 0x68 CAM12 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM12L
+ * Offset: 0x6C CAM12 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM13M
+ * Offset: 0x70 CAM13 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM13L
+ * Offset: 0x74 CAM13 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM14M
+ * Offset: 0x78 CAM14 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM14L
+ * Offset: 0x7C CAM14 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM15MSB
+ * Offset: 0x80 CAM15 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |OPCODE |OP Code Field of PAUSE Control Frame
+ * | | |In the PAUSE control frame, an op code field defined and is 0x0001.
+ * |[31:16] |LENGTH |LENGTH Field of PAUSE Control Frame
+ * | | |In the PAUSE control frame, a LENGTH field defined and is 0x8808.
+ * @var EMAC_T::CAM15LSB
+ * Offset: 0x84 CAM15 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:24] |OPERAND |Pause Parameter
+ * | | |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination
+ * | | |Ethernet MAC Controller paused
+ * | | |The unit of the OPERAND is a slot time, the 512-bit time.
+ * @var EMAC_T::TXDSA
+ * Offset: 0x88 Transmit Descriptor Link List Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TXDSA |Transmit Descriptor Link-list Start Address
+ * | | |The TXDSA keeps the start address of transmit descriptor link-list
+ * | | |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the
+ * | | |current transmit descriptor start address register (EMAC_CTXDSA)
+ * | | |The TXDSA does not be updated by EMAC
+ * | | |During the operation, EMAC will ignore the bits [1:0] of TXDSA
+ * | | |This means that TX descriptors must locate at word boundary memory address.
+ * @var EMAC_T::RXDSA
+ * Offset: 0x8C Receive Descriptor Link List Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RXDSA |Receive Descriptor Link-list Start Address
+ * | | |The RXDSA keeps the start address of receive descriptor link-list
+ * | | |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current
+ * | | |receive descriptor start address register (EMAC_CRXDSA)
+ * | | |The RXDSA does not be updated by EMAC
+ * | | |During the operation, EMAC will ignore the bits [1:0] of RXDSA
+ * | | |This means that RX descriptors must locate at word boundary memory address.
+ * @var EMAC_T::CTL
+ * Offset: 0x90 MAC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXON |Frame Reception ON
+ * | | |The RXON controls the normal packet reception of EMAC
+ * | | |If the RXON is set to high, the EMAC starts the packet reception process, including the RX
+ * | | |descriptor fetching, packet reception and RX descriptor modification.
+ * | | |It is necessary to finish EMAC initial sequence before enable RXON
+ * | | |Otherwise, the EMAC operation is undefined.
+ * | | |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet
+ * | | |reception process after the current packet reception finished.
+ * | | |0 = Packet reception process stopped.
+ * | | |1 = Packet reception process started.
+ * |[1] |ALP |Accept Long Packet
+ * | | |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception
+ * | | |If the ALP is set to high, the EMAC will accept the long packet.
+ * | | |Otherwise, the long packet will be dropped.
+ * | | |0 = Ethernet MAC controller dropped the long packet.
+ * | | |1 = Ethernet MAC controller received the long packet.
+ * |[2] |ARP |Accept Runt Packet
+ * | | |The ARP controls the runt packet, which length is less than 64 bytes, reception
+ * | | |If the ARP is set to high, the EMAC will accept the runt packet.
+ * | | |Otherwise, the runt packet will be dropped.
+ * | | |0 = Ethernet MAC controller dropped the runt packet.
+ * | | |1 = Ethernet MAC controller received the runt packet.
+ * |[3] |ACP |Accept Control Packet
+ * | | |The ACP controls the control frame reception
+ * | | |If the ACP is set to high, the EMAC will accept the control frame
+ * | | |Otherwise, the control frame will be dropped
+ * | | |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.
+ * | | |0 = Ethernet MAC controller dropped the control frame.
+ * | | |1 = Ethernet MAC controller received the control frame.
+ * |[4] |AEP |Accept CRC Error Packet
+ * | | |The AEP controls the EMAC accepts or drops the CRC error packet
+ * | | |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.
+ * | | |0 = Ethernet MAC controller dropped the CRC error packet.
+ * | | |1 = Ethernet MAC controller received the CRC error packet.
+ * |[5] |STRIPCRC |Strip CRC Checksum
+ * | | |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum
+ * | | |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.
+ * | | |0 = The 4 bytes CRC checksum is included in packet length calculation.
+ * | | |1 = The 4 bytes CRC checksum is excluded in packet length calculation.
+ * |[6] |WOLEN |Wake on LAN Enable Bit
+ * | | |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet
+ * | | |is Magic Packet and wakeup system from Power-down mode.
+ * | | |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller
+ * | | |would generate a wakeup event to wake system up from Power-down mode.
+ * | | |0 = Wake-up by Magic Packet function Disabled.
+ * | | |1 = Wake-up by Magic Packet function Enabled.
+ * |[8] |TXON |Frame Transmission ON
+ * | | |The TXON controls the normal packet transmission of EMAC
+ * | | |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX
+ * | | |descriptor fetching, packet transmission and TX descriptor modification.
+ * | | |It is must to finish EMAC initial sequence before enable TXON
+ * | | |Otherwise, the EMAC operation is undefined.
+ * | | |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet
+ * | | |transmission process after the current packet transmission finished.
+ * | | |0 = Packet transmission process stopped.
+ * | | |1 = Packet transmission process started.
+ * |[9] |NODEF |No Deferral
+ * | | |The NODEF controls the enable of deferral exceed counter
+ * | | |If NODEF is set to high, the deferral exceed counter is disabled
+ * | | |The NODEF is only useful while EMAC is operating on half duplex mode.
+ * | | |0 = The deferral exceed counter Enabled.
+ * | | |1 = The deferral exceed counter Disabled.
+ * |[16] |SDPZ |Send PAUSE Frame
+ * | | |The SDPZ controls the PAUSE control frame transmission.
+ * | | |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured
+ * | | |first and the corresponding CAM enable bit of CAMEN register also must be set.
+ * | | |Then, set SDPZ to 1 enables the PAUSE control frame transmission.
+ * | | |The SDPZ is a self-clear bit
+ * | | |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.
+ * | | |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.
+ * | | |0 = PAUSE control frame transmission completed.
+ * | | |1 = PAUSE control frame transmission Enabled.
+ * |[17] |SQECHKEN |SQE Checking Enable Bit
+ * | | |The SQECHKEN controls the enable of SQE checking
+ * | | |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode
+ * | | |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps
+ * | | |or full duplex mode.
+ * | | |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode.
+ * | | |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode.
+ * |[18] |FUDUP |Full Duplex Mode Selection
+ * | | |The FUDUP controls that if EMAC is operating on full or half duplex mode.
+ * | | |0 = EMAC operates in half duplex mode.
+ * | | |1 = EMAC operates in full duplex mode.
+ * |[19] |RMIIRXCTL |RMII RX Control
+ * | | |The RMIIRXCTL control the receive data sample in RMII mode
+ * | | |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.
+ * | | |0 = RMII RX control disabled.
+ * | | |1 = RMII RX control enabled.
+ * |[20] |OPMODE |Operation Mode Selection
+ * | | |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode
+ * | | |The RST (EMAC_CTL[24]) would not affect OPMODE value.
+ * | | |0 = EMAC operates in 10Mbps mode.
+ * | | |1 = EMAC operates in 100Mbps mode.
+ * |[22] |RMIIEN |RMII Mode Enable Bit
+ * | | |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII
+ * | | |interface or RMII interface
+ * | | |The RST (EMAC_CTL[24]) would not affect RMIIEN value.
+ * | | |0 = Ethernet MAC controller RMII mode Disabled.
+ * | | |1 = Ethernet MAC controller RMII mode Enabled.
+ * | | |NOTE: This field must keep 1.
+ * |[24] |RST |Software Reset
+ * | | |The RST implements a reset function to make the EMAC return default state
+ * | | |The RST is a self-clear bit
+ * | | |This means after the software reset finished, the RST will be cleared automatically
+ * | | |Enable RST can also reset all control and status registers, exclusive of the control bits
+ * | | |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]).
+ * | | |The EMAC re-initial is necessary after the software reset completed.
+ * | | |0 = Software reset completed.
+ * | | |1 = Software reset Enabled.
+ * @var EMAC_T::MIIMDAT
+ * Offset: 0x94 MII Management Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DATA |MII Management Data
+ * | | |The DATA is the 16 bits data that will be written into the registers of external PHY for MII
+ * | | |Management write command or the data from the registers of external PHY for MII Management read command.
+ * @var EMAC_T::MIIMCTL
+ * Offset: 0x98 MII Management Control and Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |PHYREG |PHY Register Address
+ * | | |The PHYREG keeps the address to indicate which register of external PHY is the target of the
+ * | | |MII management command.
+ * |[12:8] |PHYADDR |PHY Address
+ * | | |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
+ * |[16] |WRITE |Write Command
+ * | | |The Write defines the MII management command is a read or write.
+ * | | |0 = MII management command is a read command.
+ * | | |1 = MII management command is a write command.
+ * |[17] |BUSY |Busy Bit
+ * | | |The BUSY controls the enable of the MII management frame generation
+ * | | |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates
+ * | | |the MII management frame to external PHY through MII Management I/F
+ * | | |The BUSY is a self-clear bit
+ * | | |This means the BUSY will be cleared automatically after the MII management command finished.
+ * | | |0 = MII management command generation finished.
+ * | | |1 = MII management command generation Enabled.
+ * |[18] |PREAMSP |Preamble Suppress
+ * | | |The PREAMSP controls the preamble field generation of MII management frame
+ * | | |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.
+ * | | |0 = Preamble field generation of MII management frame not skipped.
+ * | | |1 = Preamble field generation of MII management frame skipped.
+ * |[19] |MDCON |MDC Clock ON
+ * | | |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on.
+ * | | |0 = MDC clock off.
+ * | | |1 = MDC clock on.
+ * @var EMAC_T::FIFOCTL
+ * Offset: 0x9C FIFO Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |RXFIFOTH |RXFIFO Low Threshold
+ * | | |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO
+ * | | |and system memory
+ * | | |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold
+ * | | |The low threshold is the half of high threshold always
+ * | | |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to
+ * | | |transfer frame data from RXFIFO to system memory
+ * | | |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame
+ * | | |data to system memory.
+ * | | |00 = Depend on the burst length setting
+ * | | |If the burst length is 8 words, high threshold is 8 words, too.
+ * | | |01 = RXFIFO high threshold is 64B and low threshold is 32B.
+ * | | |10 = RXFIFO high threshold is 128B and low threshold is 64B.
+ * | | |11 = RXFIFO high threshold is 192B and low threshold is 96B.
+ * |[9:8] |TXFIFOTH |TXFIFO Low Threshold
+ * | | |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system
+ * | | |memory and TXFIFO
+ * | | |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold
+ * | | |The high threshold is the twice of low threshold always
+ * | | |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops
+ * | | |generate request to transfer frame data from system memory to TXFIFO
+ * | | |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data
+ * | | |from system memory to TXFIFO.
+ * | | |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network
+ * | | |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold
+ * | | |during the transmission of the frame
+ * | | |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame
+ * | | |out after the frame data are all inside the TXFIFO.
+ * | | |00 = Undefined.
+ * | | |01 = TXFIFO low threshold is 64B and high threshold is 128B.
+ * | | |10 = TXFIFO low threshold is 80B and high threshold is 160B.
+ * | | |11 = TXFIFO low threshold is 96B and high threshold is 192B.
+ * |[21:20] |BURSTLEN |DMA Burst Length
+ * | | |This defines the burst length of AHB bus cycle while EMAC accesses system memory.
+ * | | |00 = 4 words.
+ * | | |01 = 8 words.
+ * | | |10 = 16 words.
+ * | | |11 = 16 words.
+ * @var EMAC_T::TXST
+ * Offset: 0xA0 Transmit Start Demand Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TXST |Transmit Start Demand
+ * | | |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled,
+ * | | |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted
+ * | | |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write
+ * | | |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.
+ * | | |The EMAC_TXST is a write only register and read from this register is undefined.
+ * | | |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
+ * @var EMAC_T::RXST
+ * Offset: 0xA4 Receive Start Demand Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RXST |Receive Start Demand
+ * | | |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled,
+ * | | |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted
+ * | | |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write
+ * | | |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.
+ * | | |The EMAC_RXST is a write only register and read from this register is undefined.
+ * | | |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
+ * @var EMAC_T::MRFL
+ * Offset: 0xA8 Maximum Receive Frame Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |MRFL |Maximum Receive Frame Length
+ * | | |The MRFL defines the maximum frame length for received frame
+ * | | |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8])
+ * | | |is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered.
+ * | | |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to
+ * | | |receive a frame which length is greater than 1518 bytes.
+ * @var EMAC_T::INTEN
+ * Offset: 0xAC MAC Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXIEN |Receive Interrupt Enable Bit
+ * | | |The RXIEN controls the RX interrupt generation.
+ * | | |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU
+ * | | |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1]
+ * | | |is set and the corresponding bit of EMAC_INTEN is enabled
+ * | | |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled
+ * | | |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.
+ * | | |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled.
+ * | | |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled.
+ * |[1] |CRCEIEN |CRC Error Interrupt Enable Bit
+ * | | |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation
+ * | | |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |CRCEIF (EMAC_INTSTS[1]) is set.
+ * | | |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled.
+ * | | |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled.
+ * |[2] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Bit
+ * | | |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation
+ * | | |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |RXOVIF (EMAC_INTSTS[2]) is set.
+ * | | |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled.
+ * | | |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled.
+ * |[3] |LPIEN |Long Packet Interrupt Enable Bit
+ * | | |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation
+ * | | |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC
+ * | | |generates the RX interrupt to CPU
+ * | | |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF
+ * | | |(EMAC_INTSTS[3]) is set.
+ * | | |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled.
+ * | | |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled.
+ * |[4] |RXGDIEN |Receive Good Interrupt Enable Bit
+ * | | |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation
+ * | | |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |RXGDIF (EMAC_INTSTS[4]) is set.
+ * | | |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled.
+ * | | |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled.
+ * |[5] |ALIEIEN |Alignment Error Interrupt Enable Bit
+ * | | |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation
+ * | | |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |ALIEIF (EMAC_INTSTS[5]) is set.
+ * | | |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled.
+ * | | |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled.
+ * |[6] |RPIEN |Runt Packet Interrupt Enable Bit
+ * | | |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation
+ * | | |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC
+ * | | |generates the RX interrupt to CPU
+ * | | |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |RPIF (EMAC_INTSTS[6]) is set.
+ * | | |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled.
+ * | | |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled.
+ * |[7] |MPCOVIEN |Miss Packet Counter Overrun Interrupt Enable Bit
+ * | | |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation
+ * | | |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled,
+ * | | |the EMAC generates the RX interrupt to CPU
+ * | | |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |MPCOVIF (EMAC_INTSTS[7]) is set.
+ * | | |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled.
+ * | | |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled.
+ * |[8] |MFLEIEN |Maximum Frame Length Exceed Interrupt Enable Bit
+ * | | |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation
+ * | | |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |MFLEIF (EMAC_INTSTS[8]) is set.
+ * | | |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled.
+ * | | |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled.
+ * |[9] |DENIEN |DMA Early Notification Interrupt Enable Bit
+ * | | |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation
+ * | | |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |DENIF (EMAC_INTSTS[9]) is set.
+ * | | |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled.
+ * | | |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled.
+ * |[10] |RDUIEN |Receive Descriptor Unavailable Interrupt Enable Bit
+ * | | |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation
+ * | | |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |RDUIF (EMAC_MIOSTA[10]) register is set.
+ * | | |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled.
+ * | | |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled.
+ * |[11] |RXBEIEN |Receive Bus Error Interrupt Enable Bit
+ * | | |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation
+ * | | |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |RXBEIF (EMAC_INTSTS[11]) is set.
+ * | | |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled.
+ * | | |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled.
+ * |[14] |CFRIEN |Control Frame Receive Interrupt Enable Bit
+ * | | |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation
+ * | | |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |CFRIF (EMAC_INTSTS[14]) register is set.
+ * | | |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled.
+ * | | |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled.
+ * |[15] |WOLIEN |Wake on LAN Interrupt Enable Bit
+ * | | |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation
+ * | | |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled,
+ * | | |the EMAC generates the RX interrupt to CPU
+ * | | |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |WOLIF (EMAC_INTSTS[15]) is set.
+ * | | |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled.
+ * | | |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled.
+ * |[16] |TXIEN |Transmit Interrupt Enable Bit
+ * | | |The TXIEN controls the TX interrupt generation.
+ * | | |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU
+ * | | |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of
+ * | | |EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled
+ * | | |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled
+ * | | |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.
+ * | | |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled.
+ * | | |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled.
+ * |[17] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Bit
+ * | | |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation
+ * | | |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+ * | | |the EMAC generates the TX interrupt to CPU
+ * | | |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even
+ * | | |the TXUDIF (EMAC_INTSTS[17]) is set.
+ * | | |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled.
+ * | | |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled.
+ * |[18] |TXCPIEN |Transmit Completion Interrupt Enable Bit
+ * | | |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation
+ * | | |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+ * | | |the EMAC generates the TX interrupt to CPU
+ * | | |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |TXCPIF (EMAC_INTSTS[18]) is set.
+ * | | |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled.
+ * | | |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled.
+ * |[19] |EXDEFIEN |Defer Exceed Interrupt Enable Bit
+ * | | |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation
+ * | | |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+ * | | |the EMAC generates the TX interrupt to CPU
+ * | | |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |EXDEFIF (EMAC_INTSTS[19]) is set.
+ * | | |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled.
+ * | | |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled.
+ * |[20] |NCSIEN |No Carrier Sense Interrupt Enable Bit
+ * | | |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation
+ * | | |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+ * | | |EMAC generates the TX interrupt to CPU
+ * | | |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |NCSIF (EMAC_INTSTS[20]) is set.
+ * | | |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled.
+ * | | |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled.
+ * |[21] |TXABTIEN |Transmit Abort Interrupt Enable Bit
+ * | | |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation
+ * | | |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+ * | | |the EMAC generates the TX interrupt to CPU
+ * | | |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |TXABTIF (EMAC_INTSTS[21]) is set.
+ * | | |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled.
+ * | | |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled.
+ * |[22] |LCIEN |Late Collision Interrupt Enable Bit
+ * | | |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation
+ * | | |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+ * | | |EMAC generates the TX interrupt to CPU
+ * | | |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |LCIF (EMAC_INTSTS[22]) is set.
+ * | | |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled.
+ * | | |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled.
+ * |[23] |TDUIEN |Transmit Descriptor Unavailable Interrupt Enable Bit
+ * | | |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation
+ * | | |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+ * | | |EMAC generates the TX interrupt to CPU
+ * | | |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |TDUIF (EMAC_INTSTS[23]) is set.
+ * | | |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled.
+ * | | |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled.
+ * |[24] |TXBEIEN |Transmit Bus Error Interrupt Enable Bit
+ * | | |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation
+ * | | |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+ * | | |EMAC generates the TX interrupt to CPU
+ * | | |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |TXBEIF (EMAC_INTSTS[24]) is set.
+ * | | |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled.
+ * | | |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled.
+ * |[28] |TSALMIEN |Time Stamp Alarm Interrupt Enable Bit
+ * | | |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation
+ * | | |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the
+ * | | |EMAC generates the TX interrupt to CPU
+ * | | |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the
+ * | | |TXTSALMIF (EMAC_INTEN[28]) is set.
+ * | | |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled.
+ * | | |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled.
+ * @var EMAC_T::INTSTS
+ * Offset: 0xB0 MAC Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXIF |Receive Interrupt
+ * | | |The RXIF indicates the RX interrupt status.
+ * | | |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates
+ * | | |the EMAC generates RX interrupt to CPU
+ * | | |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated.
+ * | | |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1]
+ * | | |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in
+ * | | |EMAC_INTEN[15:1] is also enabled, the RXIF will be high.
+ * | | |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too.
+ * | | |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled.
+ * | | |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in
+ * | | |EMAC_INTEN[15:1] is enabled, too.
+ * |[1] |CRCEIF |CRC Error Interrupt
+ * | | |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped
+ * | | |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and
+ * | | |CRCEIF will not be set.
+ * | | |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the CRCEIF status.
+ * | | |0 = The frame does not incur CRC error.
+ * | | |1 = The frame incurred CRC error.
+ * |[2] |RXOVIF |Receive FIFO Overflow Interrupt
+ * | | |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception
+ * | | |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer
+ * | | |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control,
+ * | | |the RXFIFOTH of FFTCR register, to higher level.
+ * | | |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the RXOVIF status.
+ * | | |0 = No RXFIFO overflow occurred during packet reception.
+ * | | |1 = RXFIFO overflow occurred during packet reception.
+ * |[3] |LPIF |Long Packet Interrupt Flag
+ * | | |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the
+ * | | |incoming packet is dropped
+ * | | |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.
+ * | | |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the LPIF status.
+ * | | |0 = The incoming frame is not a long frame or S/W wants to receive a long frame.
+ * | | |1 = The incoming frame is a long frame and dropped.
+ * |[4] |RXGDIF |Receive Good Interrupt
+ * | | |The RXGDIF high indicates the frame reception has completed.
+ * | | |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the RXGDIF status.
+ * | | |0 = The frame reception has not complete yet.
+ * | | |1 = The frame reception has completed.
+ * |[5] |ALIEIF |Alignment Error Interrupt
+ * | | |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte
+ * | | |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the ALIEIF status.
+ * | | |0 = The frame length is a multiple of byte.
+ * | | |1 = The frame length is not a multiple of byte.
+ * |[6] |RPIF |Runt Packet Interrupt
+ * | | |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped
+ * | | |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.
+ * | | |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the RPIF status.
+ * | | |0 = The incoming frame is not a short frame or S/W wants to receive a short frame.
+ * | | |1 = The incoming frame is a short frame and dropped.
+ * |[7] |MPCOVIF |Missed Packet Counter Overrun Interrupt Flag
+ * | | |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow
+ * | | |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the MPCOVIF status.
+ * | | |0 = The MPCNT has not rolled over yet.
+ * | | |1 = The MPCNT has rolled over yet.
+ * |[8] |MFLEIF |Maximum Frame Length Exceed Interrupt Flag
+ * | | |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation
+ * | | |configured in DMARFC register and the incoming packet is dropped
+ * | | |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the MFLEIF status.
+ * | | |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC.
+ * | | |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC.
+ * |[9] |DENIF |DMA Early Notification Interrupt
+ * | | |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.
+ * | | |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the DENIF status.
+ * | | |0 = The LENGTH field of incoming packet has not received yet.
+ * | | |1 = The LENGTH field of incoming packet has received.
+ * |[10] |RDUIF |Receive Descriptor Unavailable Interrupt
+ * | | |The RDUIF high indicates that there is no available RX descriptor for packet reception and
+ * | | |RXDMA will stay at Halt state
+ * | | |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to
+ * | | |make RXDMA leave Halt state while new RX descriptor is available.
+ * | | |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the RDUIF status.
+ * | | |0 = RX descriptor is available.
+ * | | |1 = RX descriptor is unavailable.
+ * |[11] |RXBEIF |Receive Bus Error Interrupt
+ * | | |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access
+ * | | |system memory through RXDMA during packet reception process
+ * | | |Reset EMAC is recommended while RXBEIF status is high.
+ * | | |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the RXBEIF status.
+ * | | |0 = No ERROR response is received.
+ * | | |1 = ERROR response is received.
+ * |[14] |CFRIF |Control Frame Receive Interrupt
+ * | | |The CFRIF high indicates EMAC receives a flow control frame
+ * | | |The CFRIF only available while EMAC is operating on full duplex mode.
+ * | | |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the CFRIF status.
+ * | | |0 = The EMAC does not receive the flow control frame.
+ * | | |1 = The EMAC receives a flow control frame.
+ * |[15] |WOLIF |Wake on LAN Interrupt Flag
+ * | | |The WOLIF high indicates EMAC receives a Magic Packet
+ * | | |The CFRIF only available while system is in power down mode and WOLEN is set high.
+ * | | |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the WOLIF status.
+ * | | |0 = The EMAC does not receive the Magic Packet.
+ * | | |1 = The EMAC receives a Magic Packet.
+ * |[16] |TXIF |Transmit Interrupt
+ * | | |The TXIF indicates the TX interrupt status.
+ * | | |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates
+ * | | |the EMAC generates TX interrupt to CPU
+ * | | |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated.
+ * | | |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17]
+ * | | |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit
+ * | | |in EMAC_INTEN[28:17] is also enabled, the TXIF will be high
+ * | | |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too.
+ * | | |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled.
+ * | | |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit
+ * | | |in EMAC_INTEN[28:17] is enabled, too.
+ * |[17] |TXUDIF |Transmit FIFO Underflow Interrupt
+ * | | |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission
+ * | | |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically
+ * | | |without S/W intervention
+ * | | |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control,
+ * | | |the TXFIFOTH of FFTCR register, to higher level.
+ * | | |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high
+ * | | |Write 1 to this bit clears the TXUDIF status.
+ * | | |0 = No TXFIFO underflow occurred during packet transmission.
+ * | | |1 = TXFIFO underflow occurred during packet transmission.
+ * |[18] |TXCPIF |Transmit Completion Interrupt
+ * | | |The TXCPIF indicates the packet transmission has completed correctly.
+ * | | |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high
+ * | | |Write 1 to this bit clears the TXCPIF status.
+ * | | |0 = The packet transmission not completed.
+ * | | |1 = The packet transmission has completed.
+ * |[19] |EXDEFIF |Defer Exceed Interrupt
+ * | | |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms
+ * | | |on 100Mbps mode, or 3.2768ms on 10Mbps mode.
+ * | | |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC
+ * | | |is operating on half-duplex mode.
+ * | | |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high
+ * | | |Write 1 to this bit clears the EXDEFIF status.
+ * | | |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
+ * | | |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
+ * |[20] |NCSIF |No Carrier Sense Interrupt
+ * | | |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during
+ * | | |the packet transmission
+ * | | |The NCSIF is only available while EMAC is operating on half-duplex mode
+ * | | |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high.
+ * | | |Write 1 to this bit clears the NCSIF status.
+ * | | |0 = CRS signal actives correctly.
+ * | | |1 = CRS signal does not active at the start of or during the packet transmission.
+ * |[21] |TXABTIF |Transmit Abort Interrupt
+ * | | |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission,
+ * | | |and then the transmission process for this packet is aborted
+ * | | |The transmission abort is only available while EMAC is operating on half-duplex mode.
+ * | | |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high
+ * | | |Write 1 to this bit clears the TXABTIF status.
+ * | | |0 = Packet does not incur 16 consecutive collisions during transmission.
+ * | | |1 = Packet incurred 16 consecutive collisions during transmission.
+ * |[22] |LCIF |Late Collision Interrupt
+ * | | |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window
+ * | | |This means after the 64 bytes of a frame has been transmitted out to the network, the collision
+ * | | |still occurred.
+ * | | |The late collision check will only be done while EMAC is operating on half-duplex mode
+ * | | |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high.
+ * | | |Write 1 to this bit clears the LCIF status.
+ * | | |0 = No collision occurred in the outside of 64 bytes collision window.
+ * | | |1 = Collision occurred in the outside of 64 bytes collision window.
+ * |[23] |TDUIF |Transmit Descriptor Unavailable Interrupt
+ * | | |The TDUIF high indicates that there is no available TX descriptor for packet transmission and
+ * | | |TXDMA will stay at Halt state.
+ * | | |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make
+ * | | |TXDMA leave Halt state while new TX descriptor is available.
+ * | | |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high.
+ * | | |Write 1 to this bit clears the TDUIF status.
+ * | | |0 = TX descriptor is available.
+ * | | |1 = TX descriptor is unavailable.
+ * |[24] |TXBEIF |Transmit Bus Error Interrupt
+ * | | |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system
+ * | | |memory through TXDMA during packet transmission process
+ * | | |Reset EMAC is recommended while TXBEIF status is high.
+ * | | |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high.
+ * | | |Write 1 to this bit clears the TXBEIF status.
+ * | | |0 = No ERROR response is received.
+ * | | |1 = ERROR response is received.
+ * |[28] |TSALMIF |Time Stamp Alarm Interrupt
+ * | | |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and
+ * | | |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR.
+ * | | |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high.
+ * | | |Write 1 to this bit clears the TSALMIF status.
+ * | | |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC.
+ * | | |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC.
+ * @var EMAC_T::GENSTS
+ * Offset: 0xB4 MAC General Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CFR |Control Frame Received
+ * | | |The CFRIF high indicates EMAC receives a flow control frame
+ * | | |The CFRIF only available while EMAC is operating on full duplex mode.
+ * | | |0 = The EMAC does not receive the flow control frame.
+ * | | |1 = The EMAC receives a flow control frame.
+ * |[1] |RXHALT |Receive Halted
+ * | | |The RXHALT high indicates the next normal packet reception process will be halted because
+ * | | |the bit RXON of MCMDR is disabled be S/W.
+ * | | |0 = Next normal packet reception process will go on.
+ * | | |1 = Next normal packet reception process will be halted.
+ * |[2] |RXFFULL |RXFIFO Full
+ * | | |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO
+ * | | |and the following incoming packet will be dropped.
+ * | | |0 = The RXFIFO is not full.
+ * | | |1 = The RXFIFO is full and the following incoming packet will be dropped.
+ * |[7:4] |COLCNT |Collision Count
+ * | | |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission
+ * | | |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be
+ * | | |0 and bit TXABTIF will be set to 1.
+ * |[8] |DEF |Deferred Transmission
+ * | | |The DEF high indicates the packet transmission has deferred once
+ * | | |The DEF is only available while EMAC is operating on half-duplex mode.
+ * | | |0 = Packet transmission does not defer.
+ * | | |1 = Packet transmission has deferred once.
+ * |[9] |TXPAUSED |Transmission Paused
+ * | | |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally
+ * | | |because EMAC received a PAUSE control frame.
+ * | | |0 = Next normal packet transmission process will go on.
+ * | | |1 = Next normal packet transmission process will be paused.
+ * |[10] |SQE |Signal Quality Error
+ * | | |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode
+ * | | |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC
+ * | | |is operating on 10Mbps half-duplex mode.
+ * | | |0 = No SQE error found at end of packet transmission.
+ * | | |1 = SQE error found at end of packet transmission.
+ * |[11] |TXHALT |Transmission Halted
+ * | | |The TXHALT high indicates the next normal packet transmission process will be halted because
+ * | | |the bit TXON (EMAC_CTL[8]) is disabled be S/W.
+ * | | |0 = Next normal packet transmission process will go on.
+ * | | |1 = Next normal packet transmission process will be halted.
+ * |[12] |RPSTS |Remote Pause Status
+ * | | |The RPSTS indicates that remote pause counter down counting actives.
+ * | | |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause
+ * | | |counter down counting
+ * | | |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet
+ * | | |transmission until the down counting done.
+ * | | |0 = Remote pause counter down counting done.
+ * | | |1 = Remote pause counter down counting actives.
+ * @var EMAC_T::MPCNT
+ * Offset: 0xB8 Missed Packet Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |MPCNT |Miss Packet Count
+ * | | |The MPCNT indicates the number of packets that were dropped due to various types of receive errors
+ * | | |The following type of receiving error makes missed packet counter increase:
+ * | | |1. Incoming packet is incurred RXFIFO overflow.
+ * | | |2. Incoming packet is dropped due to RXON is disabled.
+ * | | |3. Incoming packet is incurred CRC error.
+ * @var EMAC_T::RPCNT
+ * Offset: 0xBC MAC Receive Pause Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RPCNT |MAC Receive Pause Count
+ * | | |The RPCNT keeps the OPERAND field of the PAUSE control frame
+ * | | |It indicates how many slot time (512 bit time) the TX of EMAC will be paused.
+ * @var EMAC_T::FRSTS
+ * Offset: 0xC8 DMA Receive Frame Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RXFLT |Receive Frame LENGTH
+ * | | |The RXFLT keeps the LENGTH field of each incoming Ethernet packet
+ * | | |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has
+ * | | |received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt.
+ * | | |And, the content of LENGTH field will be stored in RXFLT.
+ * @var EMAC_T::CTXDSA
+ * Offset: 0xCC Current Transmit Descriptor Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CTXDSA |Current Transmit Descriptor Start Address
+ * | | |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently
+ * | | |The CTXDSA is read only and write to this register has no effect.
+ * @var EMAC_T::CTXBSA
+ * Offset: 0xD0 Current Transmit Buffer Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CTXBSA |Current Transmit Buffer Start Address
+ * | | |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently
+ * | | |The CTXBSA is read only and write to this register has no effect.
+ * @var EMAC_T::CRXDSA
+ * Offset: 0xD4 Current Receive Descriptor Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CRXDSA |Current Receive Descriptor Start Address
+ * | | |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently
+ * | | |The CRXDSA is read only and write to this register has no effect.
+ * @var EMAC_T::CRXBSA
+ * Offset: 0xD8 Current Receive Buffer Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CRXBSA |Current Receive Buffer Start Address
+ * | | |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently
+ * | | |The CRXBSA is read only and write to this register has no effect.
+ * @var EMAC_T::TSCTL
+ * Offset: 0x100 Time Stamp Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TSEN |Time Stamp Function Enable Bit
+ * | | |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not.
+ * | | |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low
+ * | | |to disable IEEE 1588 PTP time stamp function.
+ * | | |0 = I EEE 1588 PTP time stamp function Disabled.
+ * | | |1 = IEEE 1588 PTP time stamp function Enabled.
+ * |[1] |TSIEN |Time Stamp Counter Initialization Enable Bit
+ * | | |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC
+ * | | |and EMAC_UPDSUBSEC to PTP time stamp counter.
+ * | | |After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
+ * | | |0 = Time stamp counter initialization done.
+ * | | |1 = Time stamp counter initialization Enabled.
+ * |[2] |TSMODE |Time Stamp Fine Update Enable Bit
+ * | | |This bit chooses the time stamp counter update mode.
+ * | | |0 = Time stamp counter is in coarse update mode.
+ * | | |1 = Time stamp counter is in fine update mode.
+ * |[3] |TSUPDATE |Time Stamp Counter Time Update Enable Bit
+ * | | |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and
+ * | | |EMAC_UPDSUBSEC to PTP time stamp counter.
+ * | | |After the add operation finished, Ethernet MAC controller clear this bit to low automatically.
+ * | | |0 = No action.
+ * | | |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC.
+ * |[5] |TSALMEN |Time Stamp Alarm Enable Bit
+ * | | |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when
+ * | | |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+ * | | |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+ * | | |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+ * @var EMAC_T::TSSEC
+ * Offset: 0x110 Time Stamp Counter Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEC |Time Stamp Counter Second
+ * | | |This register reflects the bit [63:32] value of 64-bit reference timing counter
+ * | | |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
+ * @var EMAC_T::TSSUBSEC
+ * Offset: 0x114 Time Stamp Counter Sub Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SUBSEC |Time Stamp Counter Sub-second
+ * | | |This register reflects the bit [31:0] value of 64-bit reference timing counter
+ * | | |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
+ * @var EMAC_T::TSINC
+ * Offset: 0x118 Time Stamp Increment Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CNTINC |Time Stamp Counter Increment
+ * | | |Time stamp counter increment value.
+ * | | |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every
+ * | | |time when it wants to increase the EMAC_TSSUBSEC value.
+ * @var EMAC_T::TSADDEND
+ * Offset: 0x11C Time Stamp Addend Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ADDEND |Time Stamp Counter Addend
+ * | | |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.
+ * | | |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator
+ * | | |with this 32-bit value in each HCLK
+ * | | |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit
+ * | | |value kept in register EMAC_TSINC.
+ * @var EMAC_T::UPDSEC
+ * Offset: 0x120 Time Stamp Update Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEC |Time Stamp Counter Second Update
+ * | | |When TSIEN (EMAC_TSCTL[1]) is high
+ * | | |EMAC loads this 32-bit value to EMAC_TSSEC directly
+ * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value.
+ * @var EMAC_T::UPDSUBSEC
+ * Offset: 0x124 Time Stamp Update Sub Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Update
+ * | | |When TSIEN (EMAC_TSCTL[1]) is high
+ * | | |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly
+ * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value.
+ * @var EMAC_T::ALMSEC
+ * Offset: 0x128 Time Stamp Alarm Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEC |Time Stamp Counter Second Alarm
+ * | | |Time stamp counter second part alarm value.
+ * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
+ * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
+ * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
+ * @var EMAC_T::ALMSUBSEC
+ * Offset: 0x12C Time Stamp Alarm Sub Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Alarm
+ * | | |Time stamp counter sub-second part alarm value.
+ * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
+ * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
+ * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
+ */
+ __IO uint32_t CAMCTL; /*!< [0x0000] CAM Comparison Control Register */
+ __IO uint32_t CAMEN; /*!< [0x0004] CAM Enable Register */
+ __IO uint32_t CAM0M; /*!< [0x0008] CAM0 Most Significant Word Register */
+ __IO uint32_t CAM0L; /*!< [0x000c] CAM0 Least Significant Word Register */
+ __IO uint32_t CAM1M; /*!< [0x0010] CAM1 Most Significant Word Register */
+ __IO uint32_t CAM1L; /*!< [0x0014] CAM1 Least Significant Word Register */
+ __IO uint32_t CAM2M; /*!< [0x0018] CAM2 Most Significant Word Register */
+ __IO uint32_t CAM2L; /*!< [0x001c] CAM2 Least Significant Word Register */
+ __IO uint32_t CAM3M; /*!< [0x0020] CAM3 Most Significant Word Register */
+ __IO uint32_t CAM3L; /*!< [0x0024] CAM3 Least Significant Word Register */
+ __IO uint32_t CAM4M; /*!< [0x0028] CAM4 Most Significant Word Register */
+ __IO uint32_t CAM4L; /*!< [0x002c] CAM4 Least Significant Word Register */
+ __IO uint32_t CAM5M; /*!< [0x0030] CAM5 Most Significant Word Register */
+ __IO uint32_t CAM5L; /*!< [0x0034] CAM5 Least Significant Word Register */
+ __IO uint32_t CAM6M; /*!< [0x0038] CAM6 Most Significant Word Register */
+ __IO uint32_t CAM6L; /*!< [0x003c] CAM6 Least Significant Word Register */
+ __IO uint32_t CAM7M; /*!< [0x0040] CAM7 Most Significant Word Register */
+ __IO uint32_t CAM7L; /*!< [0x0044] CAM7 Least Significant Word Register */
+ __IO uint32_t CAM8M; /*!< [0x0048] CAM8 Most Significant Word Register */
+ __IO uint32_t CAM8L; /*!< [0x004c] CAM8 Least Significant Word Register */
+ __IO uint32_t CAM9M; /*!< [0x0050] CAM9 Most Significant Word Register */
+ __IO uint32_t CAM9L; /*!< [0x0054] CAM9 Least Significant Word Register */
+ __IO uint32_t CAM10M; /*!< [0x0058] CAM10 Most Significant Word Register */
+ __IO uint32_t CAM10L; /*!< [0x005c] CAM10 Least Significant Word Register */
+ __IO uint32_t CAM11M; /*!< [0x0060] CAM11 Most Significant Word Register */
+ __IO uint32_t CAM11L; /*!< [0x0064] CAM11 Least Significant Word Register */
+ __IO uint32_t CAM12M; /*!< [0x0068] CAM12 Most Significant Word Register */
+ __IO uint32_t CAM12L; /*!< [0x006c] CAM12 Least Significant Word Register */
+ __IO uint32_t CAM13M; /*!< [0x0070] CAM13 Most Significant Word Register */
+ __IO uint32_t CAM13L; /*!< [0x0074] CAM13 Least Significant Word Register */
+ __IO uint32_t CAM14M; /*!< [0x0078] CAM14 Most Significant Word Register */
+ __IO uint32_t CAM14L; /*!< [0x007c] CAM14 Least Significant Word Register */
+ __IO uint32_t CAM15MSB; /*!< [0x0080] CAM15 Most Significant Word Register */
+ __IO uint32_t CAM15LSB; /*!< [0x0084] CAM15 Least Significant Word Register */
+ __IO uint32_t TXDSA; /*!< [0x0088] Transmit Descriptor Link List Start Address Register */
+ __IO uint32_t RXDSA; /*!< [0x008c] Receive Descriptor Link List Start Address Register */
+ __IO uint32_t CTL; /*!< [0x0090] MAC Control Register */
+ __IO uint32_t MIIMDAT; /*!< [0x0094] MII Management Data Register */
+ __IO uint32_t MIIMCTL; /*!< [0x0098] MII Management Control and Address Register */
+ __IO uint32_t FIFOCTL; /*!< [0x009c] FIFO Threshold Control Register */
+ __O uint32_t TXST; /*!< [0x00a0] Transmit Start Demand Register */
+ __O uint32_t RXST; /*!< [0x00a4] Receive Start Demand Register */
+ __IO uint32_t MRFL; /*!< [0x00a8] Maximum Receive Frame Control Register */
+ __IO uint32_t INTEN; /*!< [0x00ac] MAC Interrupt Enable Register */
+ __IO uint32_t INTSTS; /*!< [0x00b0] MAC Interrupt Status Register */
+ __IO uint32_t GENSTS; /*!< [0x00b4] MAC General Status Register */
+ __IO uint32_t MPCNT; /*!< [0x00b8] Missed Packet Count Register */
+ __I uint32_t RPCNT; /*!< [0x00bc] MAC Receive Pause Count Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE0[2];
+ /** @endcond */
+ __IO uint32_t FRSTS; /*!< [0x00c8] DMA Receive Frame Status Register */
+ __I uint32_t CTXDSA; /*!< [0x00cc] Current Transmit Descriptor Start Address Register */
+ __I uint32_t CTXBSA; /*!< [0x00d0] Current Transmit Buffer Start Address Register */
+ __I uint32_t CRXDSA; /*!< [0x00d4] Current Receive Descriptor Start Address Register */
+ __I uint32_t CRXBSA; /*!< [0x00d8] Current Receive Buffer Start Address Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE1[9];
+ /** @endcond */
+ __IO uint32_t TSCTL; /*!< [0x0100] Time Stamp Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE2[3];
+ /** @endcond */
+ __I uint32_t TSSEC; /*!< [0x0110] Time Stamp Counter Second Register */
+ __I uint32_t TSSUBSEC; /*!< [0x0114] Time Stamp Counter Sub Second Register */
+ __IO uint32_t TSINC; /*!< [0x0118] Time Stamp Increment Register */
+ __IO uint32_t TSADDEND; /*!< [0x011c] Time Stamp Addend Register */
+ __IO uint32_t UPDSEC; /*!< [0x0120] Time Stamp Update Second Register */
+ __IO uint32_t UPDSUBSEC; /*!< [0x0124] Time Stamp Update Sub Second Register */
+ __IO uint32_t ALMSEC; /*!< [0x0128] Time Stamp Alarm Second Register */
+ __IO uint32_t ALMSUBSEC; /*!< [0x012c] Time Stamp Alarm Sub Second Register */
+
+} EMAC_T;
+
+/**
+ @addtogroup EMAC_CONST EMAC Bit Field Definition
+ Constant Definitions for EMAC Controller
+@{ */
+
+#define EMAC_CAMCTL_AUP_Pos (0) /*!< EMAC_T::CAMCTL: AUP Position */
+#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /*!< EMAC_T::CAMCTL: AUP Mask */
+
+#define EMAC_CAMCTL_AMP_Pos (1) /*!< EMAC_T::CAMCTL: AMP Position */
+#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /*!< EMAC_T::CAMCTL: AMP Mask */
+
+#define EMAC_CAMCTL_ABP_Pos (2) /*!< EMAC_T::CAMCTL: ABP Position */
+#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /*!< EMAC_T::CAMCTL: ABP Mask */
+
+#define EMAC_CAMCTL_COMPEN_Pos (3) /*!< EMAC_T::CAMCTL: COMPEN Position */
+#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /*!< EMAC_T::CAMCTL: COMPEN Mask */
+
+#define EMAC_CAMCTL_CMPEN_Pos (4) /*!< EMAC_T::CAMCTL: CMPEN Position */
+#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /*!< EMAC_T::CAMCTL: CMPEN Mask */
+
+#define EMAC_CAMEN_CAMxEN_Pos (0) /*!< EMAC_T::CAMEN: CAMxEN Position */
+#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /*!< EMAC_T::CAMEN: CAMxEN Mask */
+
+#define EMAC_CAM0M_MACADDR2_Pos (0) /*!< EMAC_T::CAM0M: MACADDR2 Position */
+#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /*!< EMAC_T::CAM0M: MACADDR2 Mask */
+
+#define EMAC_CAM0M_MACADDR3_Pos (8) /*!< EMAC_T::CAM0M: MACADDR3 Position */
+#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /*!< EMAC_T::CAM0M: MACADDR3 Mask */
+
+#define EMAC_CAM0M_MACADDR4_Pos (16) /*!< EMAC_T::CAM0M: MACADDR4 Position */
+#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /*!< EMAC_T::CAM0M: MACADDR4 Mask */
+
+#define EMAC_CAM0M_MACADDR5_Pos (24) /*!< EMAC_T::CAM0M: MACADDR5 Position */
+#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /*!< EMAC_T::CAM0M: MACADDR5 Mask */
+
+#define EMAC_CAM0L_MACADDR0_Pos (16) /*!< EMAC_T::CAM0L: MACADDR0 Position */
+#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /*!< EMAC_T::CAM0L: MACADDR0 Mask */
+
+#define EMAC_CAM0L_MACADDR1_Pos (24) /*!< EMAC_T::CAM0L: MACADDR1 Position */
+#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /*!< EMAC_T::CAM0L: MACADDR1 Mask */
+
+#define EMAC_CAM1M_MACADDR2_Pos (0) /*!< EMAC_T::CAM1M: MACADDR2 Position */
+#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /*!< EMAC_T::CAM1M: MACADDR2 Mask */
+
+#define EMAC_CAM1M_MACADDR3_Pos (8) /*!< EMAC_T::CAM1M: MACADDR3 Position */
+#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /*!< EMAC_T::CAM1M: MACADDR3 Mask */
+
+#define EMAC_CAM1M_MACADDR4_Pos (16) /*!< EMAC_T::CAM1M: MACADDR4 Position */
+#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /*!< EMAC_T::CAM1M: MACADDR4 Mask */
+
+#define EMAC_CAM1M_MACADDR5_Pos (24) /*!< EMAC_T::CAM1M: MACADDR5 Position */
+#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /*!< EMAC_T::CAM1M: MACADDR5 Mask */
+
+#define EMAC_CAM1L_MACADDR0_Pos (16) /*!< EMAC_T::CAM1L: MACADDR0 Position */
+#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /*!< EMAC_T::CAM1L: MACADDR0 Mask */
+
+#define EMAC_CAM1L_MACADDR1_Pos (24) /*!< EMAC_T::CAM1L: MACADDR1 Position */
+#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /*!< EMAC_T::CAM1L: MACADDR1 Mask */
+
+#define EMAC_CAM2M_MACADDR2_Pos (0) /*!< EMAC_T::CAM2M: MACADDR2 Position */
+#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /*!< EMAC_T::CAM2M: MACADDR2 Mask */
+
+#define EMAC_CAM2M_MACADDR3_Pos (8) /*!< EMAC_T::CAM2M: MACADDR3 Position */
+#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /*!< EMAC_T::CAM2M: MACADDR3 Mask */
+
+#define EMAC_CAM2M_MACADDR4_Pos (16) /*!< EMAC_T::CAM2M: MACADDR4 Position */
+#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /*!< EMAC_T::CAM2M: MACADDR4 Mask */
+
+#define EMAC_CAM2M_MACADDR5_Pos (24) /*!< EMAC_T::CAM2M: MACADDR5 Position */
+#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /*!< EMAC_T::CAM2M: MACADDR5 Mask */
+
+#define EMAC_CAM2L_MACADDR0_Pos (16) /*!< EMAC_T::CAM2L: MACADDR0 Position */
+#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /*!< EMAC_T::CAM2L: MACADDR0 Mask */
+
+#define EMAC_CAM2L_MACADDR1_Pos (24) /*!< EMAC_T::CAM2L: MACADDR1 Position */
+#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /*!< EMAC_T::CAM2L: MACADDR1 Mask */
+
+#define EMAC_CAM3M_MACADDR2_Pos (0) /*!< EMAC_T::CAM3M: MACADDR2 Position */
+#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /*!< EMAC_T::CAM3M: MACADDR2 Mask */
+
+#define EMAC_CAM3M_MACADDR3_Pos (8) /*!< EMAC_T::CAM3M: MACADDR3 Position */
+#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /*!< EMAC_T::CAM3M: MACADDR3 Mask */
+
+#define EMAC_CAM3M_MACADDR4_Pos (16) /*!< EMAC_T::CAM3M: MACADDR4 Position */
+#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /*!< EMAC_T::CAM3M: MACADDR4 Mask */
+
+#define EMAC_CAM3M_MACADDR5_Pos (24) /*!< EMAC_T::CAM3M: MACADDR5 Position */
+#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /*!< EMAC_T::CAM3M: MACADDR5 Mask */
+
+#define EMAC_CAM3L_MACADDR0_Pos (16) /*!< EMAC_T::CAM3L: MACADDR0 Position */
+#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /*!< EMAC_T::CAM3L: MACADDR0 Mask */
+
+#define EMAC_CAM3L_MACADDR1_Pos (24) /*!< EMAC_T::CAM3L: MACADDR1 Position */
+#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /*!< EMAC_T::CAM3L: MACADDR1 Mask */
+
+#define EMAC_CAM4M_MACADDR2_Pos (0) /*!< EMAC_T::CAM4M: MACADDR2 Position */
+#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /*!< EMAC_T::CAM4M: MACADDR2 Mask */
+
+#define EMAC_CAM4M_MACADDR3_Pos (8) /*!< EMAC_T::CAM4M: MACADDR3 Position */
+#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /*!< EMAC_T::CAM4M: MACADDR3 Mask */
+
+#define EMAC_CAM4M_MACADDR4_Pos (16) /*!< EMAC_T::CAM4M: MACADDR4 Position */
+#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /*!< EMAC_T::CAM4M: MACADDR4 Mask */
+
+#define EMAC_CAM4M_MACADDR5_Pos (24) /*!< EMAC_T::CAM4M: MACADDR5 Position */
+#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /*!< EMAC_T::CAM4M: MACADDR5 Mask */
+
+#define EMAC_CAM4L_MACADDR0_Pos (16) /*!< EMAC_T::CAM4L: MACADDR0 Position */
+#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /*!< EMAC_T::CAM4L: MACADDR0 Mask */
+
+#define EMAC_CAM4L_MACADDR1_Pos (24) /*!< EMAC_T::CAM4L: MACADDR1 Position */
+#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /*!< EMAC_T::CAM4L: MACADDR1 Mask */
+
+#define EMAC_CAM5M_MACADDR2_Pos (0) /*!< EMAC_T::CAM5M: MACADDR2 Position */
+#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /*!< EMAC_T::CAM5M: MACADDR2 Mask */
+
+#define EMAC_CAM5M_MACADDR3_Pos (8) /*!< EMAC_T::CAM5M: MACADDR3 Position */
+#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /*!< EMAC_T::CAM5M: MACADDR3 Mask */
+
+#define EMAC_CAM5M_MACADDR4_Pos (16) /*!< EMAC_T::CAM5M: MACADDR4 Position */
+#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /*!< EMAC_T::CAM5M: MACADDR4 Mask */
+
+#define EMAC_CAM5M_MACADDR5_Pos (24) /*!< EMAC_T::CAM5M: MACADDR5 Position */
+#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /*!< EMAC_T::CAM5M: MACADDR5 Mask */
+
+#define EMAC_CAM5L_MACADDR0_Pos (16) /*!< EMAC_T::CAM5L: MACADDR0 Position */
+#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /*!< EMAC_T::CAM5L: MACADDR0 Mask */
+
+#define EMAC_CAM5L_MACADDR1_Pos (24) /*!< EMAC_T::CAM5L: MACADDR1 Position */
+#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /*!< EMAC_T::CAM5L: MACADDR1 Mask */
+
+#define EMAC_CAM6M_MACADDR2_Pos (0) /*!< EMAC_T::CAM6M: MACADDR2 Position */
+#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /*!< EMAC_T::CAM6M: MACADDR2 Mask */
+
+#define EMAC_CAM6M_MACADDR3_Pos (8) /*!< EMAC_T::CAM6M: MACADDR3 Position */
+#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /*!< EMAC_T::CAM6M: MACADDR3 Mask */
+
+#define EMAC_CAM6M_MACADDR4_Pos (16) /*!< EMAC_T::CAM6M: MACADDR4 Position */
+#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /*!< EMAC_T::CAM6M: MACADDR4 Mask */
+
+#define EMAC_CAM6M_MACADDR5_Pos (24) /*!< EMAC_T::CAM6M: MACADDR5 Position */
+#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /*!< EMAC_T::CAM6M: MACADDR5 Mask */
+
+#define EMAC_CAM6L_MACADDR0_Pos (16) /*!< EMAC_T::CAM6L: MACADDR0 Position */
+#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /*!< EMAC_T::CAM6L: MACADDR0 Mask */
+
+#define EMAC_CAM6L_MACADDR1_Pos (24) /*!< EMAC_T::CAM6L: MACADDR1 Position */
+#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /*!< EMAC_T::CAM6L: MACADDR1 Mask */
+
+#define EMAC_CAM7M_MACADDR2_Pos (0) /*!< EMAC_T::CAM7M: MACADDR2 Position */
+#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /*!< EMAC_T::CAM7M: MACADDR2 Mask */
+
+#define EMAC_CAM7M_MACADDR3_Pos (8) /*!< EMAC_T::CAM7M: MACADDR3 Position */
+#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /*!< EMAC_T::CAM7M: MACADDR3 Mask */
+
+#define EMAC_CAM7M_MACADDR4_Pos (16) /*!< EMAC_T::CAM7M: MACADDR4 Position */
+#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /*!< EMAC_T::CAM7M: MACADDR4 Mask */
+
+#define EMAC_CAM7M_MACADDR5_Pos (24) /*!< EMAC_T::CAM7M: MACADDR5 Position */
+#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /*!< EMAC_T::CAM7M: MACADDR5 Mask */
+
+#define EMAC_CAM7L_MACADDR0_Pos (16) /*!< EMAC_T::CAM7L: MACADDR0 Position */
+#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /*!< EMAC_T::CAM7L: MACADDR0 Mask */
+
+#define EMAC_CAM7L_MACADDR1_Pos (24) /*!< EMAC_T::CAM7L: MACADDR1 Position */
+#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /*!< EMAC_T::CAM7L: MACADDR1 Mask */
+
+#define EMAC_CAM8M_MACADDR2_Pos (0) /*!< EMAC_T::CAM8M: MACADDR2 Position */
+#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /*!< EMAC_T::CAM8M: MACADDR2 Mask */
+
+#define EMAC_CAM8M_MACADDR3_Pos (8) /*!< EMAC_T::CAM8M: MACADDR3 Position */
+#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /*!< EMAC_T::CAM8M: MACADDR3 Mask */
+
+#define EMAC_CAM8M_MACADDR4_Pos (16) /*!< EMAC_T::CAM8M: MACADDR4 Position */
+#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /*!< EMAC_T::CAM8M: MACADDR4 Mask */
+
+#define EMAC_CAM8M_MACADDR5_Pos (24) /*!< EMAC_T::CAM8M: MACADDR5 Position */
+#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /*!< EMAC_T::CAM8M: MACADDR5 Mask */
+
+#define EMAC_CAM8L_MACADDR0_Pos (16) /*!< EMAC_T::CAM8L: MACADDR0 Position */
+#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /*!< EMAC_T::CAM8L: MACADDR0 Mask */
+
+#define EMAC_CAM8L_MACADDR1_Pos (24) /*!< EMAC_T::CAM8L: MACADDR1 Position */
+#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /*!< EMAC_T::CAM8L: MACADDR1 Mask */
+
+#define EMAC_CAM9M_MACADDR2_Pos (0) /*!< EMAC_T::CAM9M: MACADDR2 Position */
+#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /*!< EMAC_T::CAM9M: MACADDR2 Mask */
+
+#define EMAC_CAM9M_MACADDR3_Pos (8) /*!< EMAC_T::CAM9M: MACADDR3 Position */
+#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /*!< EMAC_T::CAM9M: MACADDR3 Mask */
+
+#define EMAC_CAM9M_MACADDR4_Pos (16) /*!< EMAC_T::CAM9M: MACADDR4 Position */
+#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /*!< EMAC_T::CAM9M: MACADDR4 Mask */
+
+#define EMAC_CAM9M_MACADDR5_Pos (24) /*!< EMAC_T::CAM9M: MACADDR5 Position */
+#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /*!< EMAC_T::CAM9M: MACADDR5 Mask */
+
+#define EMAC_CAM9L_MACADDR0_Pos (16) /*!< EMAC_T::CAM9L: MACADDR0 Position */
+#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /*!< EMAC_T::CAM9L: MACADDR0 Mask */
+
+#define EMAC_CAM9L_MACADDR1_Pos (24) /*!< EMAC_T::CAM9L: MACADDR1 Position */
+#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /*!< EMAC_T::CAM9L: MACADDR1 Mask */
+
+#define EMAC_CAM10M_MACADDR2_Pos (0) /*!< EMAC_T::CAM10M: MACADDR2 Position */
+#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /*!< EMAC_T::CAM10M: MACADDR2 Mask */
+
+#define EMAC_CAM10M_MACADDR3_Pos (8) /*!< EMAC_T::CAM10M: MACADDR3 Position */
+#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /*!< EMAC_T::CAM10M: MACADDR3 Mask */
+
+#define EMAC_CAM10M_MACADDR4_Pos (16) /*!< EMAC_T::CAM10M: MACADDR4 Position */
+#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /*!< EMAC_T::CAM10M: MACADDR4 Mask */
+
+#define EMAC_CAM10M_MACADDR5_Pos (24) /*!< EMAC_T::CAM10M: MACADDR5 Position */
+#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /*!< EMAC_T::CAM10M: MACADDR5 Mask */
+
+#define EMAC_CAM10L_MACADDR0_Pos (16) /*!< EMAC_T::CAM10L: MACADDR0 Position */
+#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /*!< EMAC_T::CAM10L: MACADDR0 Mask */
+
+#define EMAC_CAM10L_MACADDR1_Pos (24) /*!< EMAC_T::CAM10L: MACADDR1 Position */
+#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /*!< EMAC_T::CAM10L: MACADDR1 Mask */
+
+#define EMAC_CAM11M_MACADDR2_Pos (0) /*!< EMAC_T::CAM11M: MACADDR2 Position */
+#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /*!< EMAC_T::CAM11M: MACADDR2 Mask */
+
+#define EMAC_CAM11M_MACADDR3_Pos (8) /*!< EMAC_T::CAM11M: MACADDR3 Position */
+#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /*!< EMAC_T::CAM11M: MACADDR3 Mask */
+
+#define EMAC_CAM11M_MACADDR4_Pos (16) /*!< EMAC_T::CAM11M: MACADDR4 Position */
+#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /*!< EMAC_T::CAM11M: MACADDR4 Mask */
+
+#define EMAC_CAM11M_MACADDR5_Pos (24) /*!< EMAC_T::CAM11M: MACADDR5 Position */
+#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /*!< EMAC_T::CAM11M: MACADDR5 Mask */
+
+#define EMAC_CAM11L_MACADDR0_Pos (16) /*!< EMAC_T::CAM11L: MACADDR0 Position */
+#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /*!< EMAC_T::CAM11L: MACADDR0 Mask */
+
+#define EMAC_CAM11L_MACADDR1_Pos (24) /*!< EMAC_T::CAM11L: MACADDR1 Position */
+#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /*!< EMAC_T::CAM11L: MACADDR1 Mask */
+
+#define EMAC_CAM12M_MACADDR2_Pos (0) /*!< EMAC_T::CAM12M: MACADDR2 Position */
+#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /*!< EMAC_T::CAM12M: MACADDR2 Mask */
+
+#define EMAC_CAM12M_MACADDR3_Pos (8) /*!< EMAC_T::CAM12M: MACADDR3 Position */
+#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /*!< EMAC_T::CAM12M: MACADDR3 Mask */
+
+#define EMAC_CAM12M_MACADDR4_Pos (16) /*!< EMAC_T::CAM12M: MACADDR4 Position */
+#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /*!< EMAC_T::CAM12M: MACADDR4 Mask */
+
+#define EMAC_CAM12M_MACADDR5_Pos (24) /*!< EMAC_T::CAM12M: MACADDR5 Position */
+#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /*!< EMAC_T::CAM12M: MACADDR5 Mask */
+
+#define EMAC_CAM12L_MACADDR0_Pos (16) /*!< EMAC_T::CAM12L: MACADDR0 Position */
+#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /*!< EMAC_T::CAM12L: MACADDR0 Mask */
+
+#define EMAC_CAM12L_MACADDR1_Pos (24) /*!< EMAC_T::CAM12L: MACADDR1 Position */
+#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /*!< EMAC_T::CAM12L: MACADDR1 Mask */
+
+#define EMAC_CAM13M_MACADDR2_Pos (0) /*!< EMAC_T::CAM13M: MACADDR2 Position */
+#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /*!< EMAC_T::CAM13M: MACADDR2 Mask */
+
+#define EMAC_CAM13M_MACADDR3_Pos (8) /*!< EMAC_T::CAM13M: MACADDR3 Position */
+#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /*!< EMAC_T::CAM13M: MACADDR3 Mask */
+
+#define EMAC_CAM13M_MACADDR4_Pos (16) /*!< EMAC_T::CAM13M: MACADDR4 Position */
+#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /*!< EMAC_T::CAM13M: MACADDR4 Mask */
+
+#define EMAC_CAM13M_MACADDR5_Pos (24) /*!< EMAC_T::CAM13M: MACADDR5 Position */
+#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /*!< EMAC_T::CAM13M: MACADDR5 Mask */
+
+#define EMAC_CAM13L_MACADDR0_Pos (16) /*!< EMAC_T::CAM13L: MACADDR0 Position */
+#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /*!< EMAC_T::CAM13L: MACADDR0 Mask */
+
+#define EMAC_CAM13L_MACADDR1_Pos (24) /*!< EMAC_T::CAM13L: MACADDR1 Position */
+#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /*!< EMAC_T::CAM13L: MACADDR1 Mask */
+
+#define EMAC_CAM14M_MACADDR2_Pos (0) /*!< EMAC_T::CAM14M: MACADDR2 Position */
+#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /*!< EMAC_T::CAM14M: MACADDR2 Mask */
+
+#define EMAC_CAM14M_MACADDR3_Pos (8) /*!< EMAC_T::CAM14M: MACADDR3 Position */
+#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /*!< EMAC_T::CAM14M: MACADDR3 Mask */
+
+#define EMAC_CAM14M_MACADDR4_Pos (16) /*!< EMAC_T::CAM14M: MACADDR4 Position */
+#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /*!< EMAC_T::CAM14M: MACADDR4 Mask */
+
+#define EMAC_CAM14M_MACADDR5_Pos (24) /*!< EMAC_T::CAM14M: MACADDR5 Position */
+#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /*!< EMAC_T::CAM14M: MACADDR5 Mask */
+
+#define EMAC_CAM14L_MACADDR0_Pos (16) /*!< EMAC_T::CAM14L: MACADDR0 Position */
+#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /*!< EMAC_T::CAM14L: MACADDR0 Mask */
+
+#define EMAC_CAM14L_MACADDR1_Pos (24) /*!< EMAC_T::CAM14L: MACADDR1 Position */
+#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /*!< EMAC_T::CAM14L: MACADDR1 Mask */
+
+#define EMAC_CAM15MSB_OPCODE_Pos (0) /*!< EMAC_T::CAM15MSB: OPCODE Position */
+#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /*!< EMAC_T::CAM15MSB: OPCODE Mask */
+
+#define EMAC_CAM15MSB_LENGTH_Pos (16) /*!< EMAC_T::CAM15MSB: LENGTH Position */
+#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /*!< EMAC_T::CAM15MSB: LENGTH Mask */
+
+#define EMAC_CAM15LSB_OPERAND_Pos (24) /*!< EMAC_T::CAM15LSB: OPERAND Position */
+#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /*!< EMAC_T::CAM15LSB: OPERAND Mask */
+
+#define EMAC_TXDSA_TXDSA_Pos (0) /*!< EMAC_T::TXDSA: TXDSA Position */
+#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /*!< EMAC_T::TXDSA: TXDSA Mask */
+
+#define EMAC_RXDSA_RXDSA_Pos (0) /*!< EMAC_T::RXDSA: RXDSA Position */
+#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /*!< EMAC_T::RXDSA: RXDSA Mask */
+
+#define EMAC_CTL_RXON_Pos (0) /*!< EMAC_T::CTL: RXON Position */
+#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /*!< EMAC_T::CTL: RXON Mask */
+
+#define EMAC_CTL_ALP_Pos (1) /*!< EMAC_T::CTL: ALP Position */
+#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /*!< EMAC_T::CTL: ALP Mask */
+
+#define EMAC_CTL_ARP_Pos (2) /*!< EMAC_T::CTL: ARP Position */
+#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /*!< EMAC_T::CTL: ARP Mask */
+
+#define EMAC_CTL_ACP_Pos (3) /*!< EMAC_T::CTL: ACP Position */
+#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /*!< EMAC_T::CTL: ACP Mask */
+
+#define EMAC_CTL_AEP_Pos (4) /*!< EMAC_T::CTL: AEP Position */
+#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /*!< EMAC_T::CTL: AEP Mask */
+
+#define EMAC_CTL_STRIPCRC_Pos (5) /*!< EMAC_T::CTL: STRIPCRC Position */
+#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /*!< EMAC_T::CTL: STRIPCRC Mask */
+
+#define EMAC_CTL_WOLEN_Pos (6) /*!< EMAC_T::CTL: WOLEN Position */
+#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /*!< EMAC_T::CTL: WOLEN Mask */
+
+#define EMAC_CTL_TXON_Pos (8) /*!< EMAC_T::CTL: TXON Position */
+#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /*!< EMAC_T::CTL: TXON Mask */
+
+#define EMAC_CTL_NODEF_Pos (9) /*!< EMAC_T::CTL: NODEF Position */
+#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /*!< EMAC_T::CTL: NODEF Mask */
+
+#define EMAC_CTL_SDPZ_Pos (16) /*!< EMAC_T::CTL: SDPZ Position */
+#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /*!< EMAC_T::CTL: SDPZ Mask */
+
+#define EMAC_CTL_SQECHKEN_Pos (17) /*!< EMAC_T::CTL: SQECHKEN Position */
+#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /*!< EMAC_T::CTL: SQECHKEN Mask */
+
+#define EMAC_CTL_FUDUP_Pos (18) /*!< EMAC_T::CTL: FUDUP Position */
+#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /*!< EMAC_T::CTL: FUDUP Mask */
+
+#define EMAC_CTL_RMIIRXCTL_Pos (19) /*!< EMAC_T::CTL: RMIIRXCTL Position */
+#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /*!< EMAC_T::CTL: RMIIRXCTL Mask */
+
+#define EMAC_CTL_OPMODE_Pos (20) /*!< EMAC_T::CTL: OPMODE Position */
+#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /*!< EMAC_T::CTL: OPMODE Mask */
+
+#define EMAC_CTL_RMIIEN_Pos (22) /*!< EMAC_T::CTL: RMIIEN Position */
+#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /*!< EMAC_T::CTL: RMIIEN Mask */
+
+#define EMAC_CTL_RST_Pos (24) /*!< EMAC_T::CTL: RST Position */
+#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /*!< EMAC_T::CTL: RST Mask */
+
+#define EMAC_MIIMDAT_DATA_Pos (0) /*!< EMAC_T::MIIMDAT: DATA Position */
+#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /*!< EMAC_T::MIIMDAT: DATA Mask */
+
+#define EMAC_MIIMCTL_PHYREG_Pos (0) /*!< EMAC_T::MIIMCTL: PHYREG Position */
+#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /*!< EMAC_T::MIIMCTL: PHYREG Mask */
+
+#define EMAC_MIIMCTL_PHYADDR_Pos (8) /*!< EMAC_T::MIIMCTL: PHYADDR Position */
+#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /*!< EMAC_T::MIIMCTL: PHYADDR Mask */
+
+#define EMAC_MIIMCTL_WRITE_Pos (16) /*!< EMAC_T::MIIMCTL: WRITE Position */
+#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /*!< EMAC_T::MIIMCTL: WRITE Mask */
+
+#define EMAC_MIIMCTL_BUSY_Pos (17) /*!< EMAC_T::MIIMCTL: BUSY Position */
+#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /*!< EMAC_T::MIIMCTL: BUSY Mask */
+
+#define EMAC_MIIMCTL_PREAMSP_Pos (18) /*!< EMAC_T::MIIMCTL: PREAMSP Position */
+#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /*!< EMAC_T::MIIMCTL: PREAMSP Mask */
+
+#define EMAC_MIIMCTL_MDCON_Pos (19) /*!< EMAC_T::MIIMCTL: MDCON Position */
+#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /*!< EMAC_T::MIIMCTL: MDCON Mask */
+
+#define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /*!< EMAC_T::FIFOCTL: RXFIFOTH Position */
+#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: RXFIFOTH Mask */
+
+#define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /*!< EMAC_T::FIFOCTL: TXFIFOTH Position */
+#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: TXFIFOTH Mask */
+
+#define EMAC_FIFOCTL_BURSTLEN_Pos (20) /*!< EMAC_T::FIFOCTL: BURSTLEN Position */
+#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /*!< EMAC_T::FIFOCTL: BURSTLEN Mask */
+
+#define EMAC_TXST_TXST_Pos (0) /*!< EMAC_T::TXST: TXST Position */
+#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /*!< EMAC_T::TXST: TXST Mask */
+
+#define EMAC_RXST_RXST_Pos (0) /*!< EMAC_T::RXST: RXST Position */
+#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /*!< EMAC_T::RXST: RXST Mask */
+
+#define EMAC_MRFL_MRFL_Pos (0) /*!< EMAC_T::MRFL: MRFL Position */
+#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /*!< EMAC_T::MRFL: MRFL Mask */
+
+#define EMAC_INTEN_RXIEN_Pos (0) /*!< EMAC_T::INTEN: RXIEN Position */
+#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /*!< EMAC_T::INTEN: RXIEN Mask */
+
+#define EMAC_INTEN_CRCEIEN_Pos (1) /*!< EMAC_T::INTEN: CRCEIEN Position */
+#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /*!< EMAC_T::INTEN: CRCEIEN Mask */
+
+#define EMAC_INTEN_RXOVIEN_Pos (2) /*!< EMAC_T::INTEN: RXOVIEN Position */
+#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /*!< EMAC_T::INTEN: RXOVIEN Mask */
+
+#define EMAC_INTEN_LPIEN_Pos (3) /*!< EMAC_T::INTEN: LPIEN Position */
+#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /*!< EMAC_T::INTEN: LPIEN Mask */
+
+#define EMAC_INTEN_RXGDIEN_Pos (4) /*!< EMAC_T::INTEN: RXGDIEN Position */
+#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /*!< EMAC_T::INTEN: RXGDIEN Mask */
+
+#define EMAC_INTEN_ALIEIEN_Pos (5) /*!< EMAC_T::INTEN: ALIEIEN Position */
+#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /*!< EMAC_T::INTEN: ALIEIEN Mask */
+
+#define EMAC_INTEN_RPIEN_Pos (6) /*!< EMAC_T::INTEN: RPIEN Position */
+#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /*!< EMAC_T::INTEN: RPIEN Mask */
+
+#define EMAC_INTEN_MPCOVIEN_Pos (7) /*!< EMAC_T::INTEN: MPCOVIEN Position */
+#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /*!< EMAC_T::INTEN: MPCOVIEN Mask */
+
+#define EMAC_INTEN_MFLEIEN_Pos (8) /*!< EMAC_T::INTEN: MFLEIEN Position */
+#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /*!< EMAC_T::INTEN: MFLEIEN Mask */
+
+#define EMAC_INTEN_DENIEN_Pos (9) /*!< EMAC_T::INTEN: DENIEN Position */
+#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /*!< EMAC_T::INTEN: DENIEN Mask */
+
+#define EMAC_INTEN_RDUIEN_Pos (10) /*!< EMAC_T::INTEN: RDUIEN Position */
+#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /*!< EMAC_T::INTEN: RDUIEN Mask */
+
+#define EMAC_INTEN_RXBEIEN_Pos (11) /*!< EMAC_T::INTEN: RXBEIEN Position */
+#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /*!< EMAC_T::INTEN: RXBEIEN Mask */
+
+#define EMAC_INTEN_CFRIEN_Pos (14) /*!< EMAC_T::INTEN: CFRIEN Position */
+#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /*!< EMAC_T::INTEN: CFRIEN Mask */
+
+#define EMAC_INTEN_WOLIEN_Pos (15) /*!< EMAC_T::INTEN: WOLIEN Position */
+#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /*!< EMAC_T::INTEN: WOLIEN Mask */
+
+#define EMAC_INTEN_TXIEN_Pos (16) /*!< EMAC_T::INTEN: TXIEN Position */
+#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /*!< EMAC_T::INTEN: TXIEN Mask */
+
+#define EMAC_INTEN_TXUDIEN_Pos (17) /*!< EMAC_T::INTEN: TXUDIEN Position */
+#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /*!< EMAC_T::INTEN: TXUDIEN Mask */
+
+#define EMAC_INTEN_TXCPIEN_Pos (18) /*!< EMAC_T::INTEN: TXCPIEN Position */
+#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /*!< EMAC_T::INTEN: TXCPIEN Mask */
+
+#define EMAC_INTEN_EXDEFIEN_Pos (19) /*!< EMAC_T::INTEN: EXDEFIEN Position */
+#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /*!< EMAC_T::INTEN: EXDEFIEN Mask */
+
+#define EMAC_INTEN_NCSIEN_Pos (20) /*!< EMAC_T::INTEN: NCSIEN Position */
+#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /*!< EMAC_T::INTEN: NCSIEN Mask */
+
+#define EMAC_INTEN_TXABTIEN_Pos (21) /*!< EMAC_T::INTEN: TXABTIEN Position */
+#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /*!< EMAC_T::INTEN: TXABTIEN Mask */
+
+#define EMAC_INTEN_LCIEN_Pos (22) /*!< EMAC_T::INTEN: LCIEN Position */
+#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /*!< EMAC_T::INTEN: LCIEN Mask */
+
+#define EMAC_INTEN_TDUIEN_Pos (23) /*!< EMAC_T::INTEN: TDUIEN Position */
+#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /*!< EMAC_T::INTEN: TDUIEN Mask */
+
+#define EMAC_INTEN_TXBEIEN_Pos (24) /*!< EMAC_T::INTEN: TXBEIEN Position */
+#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /*!< EMAC_T::INTEN: TXBEIEN Mask */
+
+#define EMAC_INTEN_TSALMIEN_Pos (28) /*!< EMAC_T::INTEN: TSALMIEN Position */
+#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /*!< EMAC_T::INTEN: TSALMIEN Mask */
+
+#define EMAC_INTSTS_RXIF_Pos (0) /*!< EMAC_T::INTSTS: RXIF Position */
+#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /*!< EMAC_T::INTSTS: RXIF Mask */
+
+#define EMAC_INTSTS_CRCEIF_Pos (1) /*!< EMAC_T::INTSTS: CRCEIF Position */
+#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /*!< EMAC_T::INTSTS: CRCEIF Mask */
+
+#define EMAC_INTSTS_RXOVIF_Pos (2) /*!< EMAC_T::INTSTS: RXOVIF Position */
+#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /*!< EMAC_T::INTSTS: RXOVIF Mask */
+
+#define EMAC_INTSTS_LPIF_Pos (3) /*!< EMAC_T::INTSTS: LPIF Position */
+#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /*!< EMAC_T::INTSTS: LPIF Mask */
+
+#define EMAC_INTSTS_RXGDIF_Pos (4) /*!< EMAC_T::INTSTS: RXGDIF Position */
+#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /*!< EMAC_T::INTSTS: RXGDIF Mask */
+
+#define EMAC_INTSTS_ALIEIF_Pos (5) /*!< EMAC_T::INTSTS: ALIEIF Position */
+#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /*!< EMAC_T::INTSTS: ALIEIF Mask */
+
+#define EMAC_INTSTS_RPIF_Pos (6) /*!< EMAC_T::INTSTS: RPIF Position */
+#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /*!< EMAC_T::INTSTS: RPIF Mask */
+
+#define EMAC_INTSTS_MPCOVIF_Pos (7) /*!< EMAC_T::INTSTS: MPCOVIF Position */
+#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /*!< EMAC_T::INTSTS: MPCOVIF Mask */
+
+#define EMAC_INTSTS_MFLEIF_Pos (8) /*!< EMAC_T::INTSTS: MFLEIF Position */
+#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /*!< EMAC_T::INTSTS: MFLEIF Mask */
+
+#define EMAC_INTSTS_DENIF_Pos (9) /*!< EMAC_T::INTSTS: DENIF Position */
+#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /*!< EMAC_T::INTSTS: DENIF Mask */
+
+#define EMAC_INTSTS_RDUIF_Pos (10) /*!< EMAC_T::INTSTS: RDUIF Position */
+#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /*!< EMAC_T::INTSTS: RDUIF Mask */
+
+#define EMAC_INTSTS_RXBEIF_Pos (11) /*!< EMAC_T::INTSTS: RXBEIF Position */
+#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /*!< EMAC_T::INTSTS: RXBEIF Mask */
+
+#define EMAC_INTSTS_CFRIF_Pos (14) /*!< EMAC_T::INTSTS: CFRIF Position */
+#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /*!< EMAC_T::INTSTS: CFRIF Mask */
+
+#define EMAC_INTSTS_WOLIF_Pos (15) /*!< EMAC_T::INTSTS: WOLIF Position */
+#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /*!< EMAC_T::INTSTS: WOLIF Mask */
+
+#define EMAC_INTSTS_TXIF_Pos (16) /*!< EMAC_T::INTSTS: TXIF Position */
+#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /*!< EMAC_T::INTSTS: TXIF Mask */
+
+#define EMAC_INTSTS_TXUDIF_Pos (17) /*!< EMAC_T::INTSTS: TXUDIF Position */
+#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /*!< EMAC_T::INTSTS: TXUDIF Mask */
+
+#define EMAC_INTSTS_TXCPIF_Pos (18) /*!< EMAC_T::INTSTS: TXCPIF Position */
+#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /*!< EMAC_T::INTSTS: TXCPIF Mask */
+
+#define EMAC_INTSTS_EXDEFIF_Pos (19) /*!< EMAC_T::INTSTS: EXDEFIF Position */
+#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /*!< EMAC_T::INTSTS: EXDEFIF Mask */
+
+#define EMAC_INTSTS_NCSIF_Pos (20) /*!< EMAC_T::INTSTS: NCSIF Position */
+#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /*!< EMAC_T::INTSTS: NCSIF Mask */
+
+#define EMAC_INTSTS_TXABTIF_Pos (21) /*!< EMAC_T::INTSTS: TXABTIF Position */
+#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /*!< EMAC_T::INTSTS: TXABTIF Mask */
+
+#define EMAC_INTSTS_LCIF_Pos (22) /*!< EMAC_T::INTSTS: LCIF Position */
+#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /*!< EMAC_T::INTSTS: LCIF Mask */
+
+#define EMAC_INTSTS_TDUIF_Pos (23) /*!< EMAC_T::INTSTS: TDUIF Position */
+#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /*!< EMAC_T::INTSTS: TDUIF Mask */
+
+#define EMAC_INTSTS_TXBEIF_Pos (24) /*!< EMAC_T::INTSTS: TXBEIF Position */
+#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /*!< EMAC_T::INTSTS: TXBEIF Mask */
+
+#define EMAC_INTSTS_TSALMIF_Pos (28) /*!< EMAC_T::INTSTS: TSALMIF Position */
+#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /*!< EMAC_T::INTSTS: TSALMIF Mask */
+
+#define EMAC_GENSTS_CFR_Pos (0) /*!< EMAC_T::GENSTS: CFR Position */
+#define EMAC_GENSTS_CFR_Msk (0x1ul << EMAC_GENSTS_CFR_Pos) /*!< EMAC_T::GENSTS: CFR Mask */
+
+#define EMAC_GENSTS_RXHALT_Pos (1) /*!< EMAC_T::GENSTS: RXHALT Position */
+#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /*!< EMAC_T::GENSTS: RXHALT Mask */
+
+#define EMAC_GENSTS_RXFFULL_Pos (2) /*!< EMAC_T::GENSTS: RXFFULL Position */
+#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /*!< EMAC_T::GENSTS: RXFFULL Mask */
+
+#define EMAC_GENSTS_COLCNT_Pos (4) /*!< EMAC_T::GENSTS: COLCNT Position */
+#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /*!< EMAC_T::GENSTS: COLCNT Mask */
+
+#define EMAC_GENSTS_DEF_Pos (8) /*!< EMAC_T::GENSTS: DEF Position */
+#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /*!< EMAC_T::GENSTS: DEF Mask */
+
+#define EMAC_GENSTS_TXPAUSED_Pos (9) /*!< EMAC_T::GENSTS: TXPAUSED Position */
+#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /*!< EMAC_T::GENSTS: TXPAUSED Mask */
+
+#define EMAC_GENSTS_SQE_Pos (10) /*!< EMAC_T::GENSTS: SQE Position */
+#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /*!< EMAC_T::GENSTS: SQE Mask */
+
+#define EMAC_GENSTS_TXHALT_Pos (11) /*!< EMAC_T::GENSTS: TXHALT Position */
+#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /*!< EMAC_T::GENSTS: TXHALT Mask */
+
+#define EMAC_GENSTS_RPSTS_Pos (12) /*!< EMAC_T::GENSTS: RPSTS Position */
+#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /*!< EMAC_T::GENSTS: RPSTS Mask */
+
+#define EMAC_MPCNT_MPCNT_Pos (0) /*!< EMAC_T::MPCNT: MPCNT Position */
+#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /*!< EMAC_T::MPCNT: MPCNT Mask */
+
+#define EMAC_RPCNT_RPCNT_Pos (0) /*!< EMAC_T::RPCNT: RPCNT Position */
+#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /*!< EMAC_T::RPCNT: RPCNT Mask */
+
+#define EMAC_FRSTS_RXFLT_Pos (0) /*!< EMAC_T::FRSTS: RXFLT Position */
+#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /*!< EMAC_T::FRSTS: RXFLT Mask */
+
+#define EMAC_CTXDSA_CTXDSA_Pos (0) /*!< EMAC_T::CTXDSA: CTXDSA Position */
+#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /*!< EMAC_T::CTXDSA: CTXDSA Mask */
+
+#define EMAC_CTXBSA_CTXBSA_Pos (0) /*!< EMAC_T::CTXBSA: CTXBSA Position */
+#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /*!< EMAC_T::CTXBSA: CTXBSA Mask */
+
+#define EMAC_CRXDSA_CRXDSA_Pos (0) /*!< EMAC_T::CRXDSA: CRXDSA Position */
+#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /*!< EMAC_T::CRXDSA: CRXDSA Mask */
+
+#define EMAC_CRXBSA_CRXBSA_Pos (0) /*!< EMAC_T::CRXBSA: CRXBSA Position */
+#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /*!< EMAC_T::CRXBSA: CRXBSA Mask */
+
+#define EMAC_TSCTL_TSEN_Pos (0) /*!< EMAC_T::TSCTL: TSEN Position */
+#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /*!< EMAC_T::TSCTL: TSEN Mask */
+
+#define EMAC_TSCTL_TSIEN_Pos (1) /*!< EMAC_T::TSCTL: TSIEN Position */
+#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /*!< EMAC_T::TSCTL: TSIEN Mask */
+
+#define EMAC_TSCTL_TSMODE_Pos (2) /*!< EMAC_T::TSCTL: TSMODE Position */
+#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /*!< EMAC_T::TSCTL: TSMODE Mask */
+
+#define EMAC_TSCTL_TSUPDATE_Pos (3) /*!< EMAC_T::TSCTL: TSUPDATE Position */
+#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /*!< EMAC_T::TSCTL: TSUPDATE Mask */
+
+#define EMAC_TSCTL_TSALMEN_Pos (5) /*!< EMAC_T::TSCTL: TSALMEN Position */
+#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /*!< EMAC_T::TSCTL: TSALMEN Mask */
+
+#define EMAC_TSSEC_SEC_Pos (0) /*!< EMAC_T::TSSEC: SEC Position */
+#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /*!< EMAC_T::TSSEC: SEC Mask */
+
+#define EMAC_TSSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::TSSUBSEC: SUBSEC Position */
+#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /*!< EMAC_T::TSSUBSEC: SUBSEC Mask */
+
+#define EMAC_TSINC_CNTINC_Pos (0) /*!< EMAC_T::TSINC: CNTINC Position */
+#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /*!< EMAC_T::TSINC: CNTINC Mask */
+
+#define EMAC_TSADDEND_ADDEND_Pos (0) /*!< EMAC_T::TSADDEND: ADDEND Position */
+#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /*!< EMAC_T::TSADDEND: ADDEND Mask */
+
+#define EMAC_UPDSEC_SEC_Pos (0) /*!< EMAC_T::UPDSEC: SEC Position */
+#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /*!< EMAC_T::UPDSEC: SEC Mask */
+
+#define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::UPDSUBSEC: SUBSEC Position */
+#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /*!< EMAC_T::UPDSUBSEC: SUBSEC Mask */
+
+#define EMAC_ALMSEC_SEC_Pos (0) /*!< EMAC_T::ALMSEC: SEC Position */
+#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /*!< EMAC_T::ALMSEC: SEC Mask */
+
+#define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::ALMSUBSEC: SUBSEC Position */
+#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /*!< EMAC_T::ALMSUBSEC: SUBSEC Mask */
+
+/**@}*/ /* EMAC_CONST */
+/**@}*/ /* end of EMAC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __EMAC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/epwm_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/epwm_reg.h
new file mode 100644
index 00000000000..aa4ba4a478b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/epwm_reg.h
@@ -0,0 +1,4023 @@
+/**************************************************************************//**
+ * @file epwm_reg.h
+ * @version V1.00
+ * @brief EPWM register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EPWM_REG_H__
+#define __EPWM_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup EPWM Pulse Width Modulation Controller(EPWM)
+ Memory Mapped Structure for EPWM Controller
+@{ */
+
+typedef struct
+{
+ /**
+ * @var ECAPDAT_T::RCAPDAT
+ * Offset: 0x20C EPWM Rising Capture Data Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only)
+ * | | |When rising capture condition happened, the EPWM counter value will be saved in this register.
+ * @var ECAPDAT_T::FCAPDAT
+ * Offset: 0x210 EPWM Falling Capture Data Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only)
+ * | | |When falling capture condition happened, the EPWM counter value will be saved in this register.
+ */
+ __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */
+ __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */
+} ECAPDAT_T;
+
+typedef struct
+{
+
+
+ /**
+ * @var EPWM_T::CTL0
+ * Offset: 0x00 EPWM Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CTRLD0 |Center Re-load
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[1] |CTRLD1 |Center Re-load
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[2] |CTRLD2 |Center Re-load
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[3] |CTRLD3 |Center Re-load
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[4] |CTRLD4 |Center Re-load
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[5] |CTRLD5 |Center Re-load
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the center point of a period
+ * |[8] |WINLDEN0 |Window Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+ * |[9] |WINLDEN1 |Window Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+ * |[10] |WINLDEN2 |Window Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+ * |[11] |WINLDEN3 |Window Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+ * |[12] |WINLDEN4 |Window Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+ * |[13] |WINLDEN5 |Window Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+ * |[16] |IMMLDEN0 |Immediately Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+ * |[17] |IMMLDEN1 |Immediately Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+ * |[18] |IMMLDEN2 |Immediately Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+ * |[19] |IMMLDEN3 |Immediately Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+ * |[20] |IMMLDEN4 |Immediately Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+ * |[21] |IMMLDEN5 |Immediately Load Enable Bits
+ * | | |0 = PERIOD will load to PBUF at the end point of each period
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+ * |[24] |GROUPEN |Group Function Enable Bit(S)
+ * | | |0 = The output waveform of each EPWM channel are independent.
+ * | | |1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1.
+ * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
+ * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode.
+ * | | |0 = ICE debug mode counter halt disable.
+ * | | |1 = ICE debug mode counter halt enable.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
+ * | | |0 = ICE debug mode acknowledgement effects EPWM output.
+ * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged.
+ * | | |1 = ICE debug mode acknowledgement disabled.
+ * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * @var EPWM_T::CTL1
+ * Offset: 0x04 EPWM Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type
+ * | | |00 = Up counter type (supports in capture mode).
+ * | | |01 = Down count type (supports in capture mode).
+ * | | |10 = Up-down counter type.
+ * | | |11 = Reserved.
+ * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type
+ * | | |00 = Up counter type (supports in capture mode).
+ * | | |01 = Down count type (supports in capture mode).
+ * | | |10 = Up-down counter type.
+ * | | |11 = Reserved.
+ * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type
+ * | | |00 = Up counter type (supports in capture mode).
+ * | | |01 = Down count type (supports in capture mode).
+ * | | |10 = Up-down counter type.
+ * | | |11 = Reserved.
+ * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type
+ * | | |00 = Up counter type (supports in capture mode).
+ * | | |01 = Down count type (supports in capture mode).
+ * | | |10 = Up-down counter type.
+ * | | |11 = Reserved.
+ * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type
+ * | | |00 = Up counter type (supports in capture mode).
+ * | | |01 = Down count type (supports in capture mode).
+ * | | |10 = Up-down counter type.
+ * | | |11 = Reserved.
+ * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type
+ * | | |00 = Up counter type (supports in capture mode).
+ * | | |01 = Down count type (supports in capture mode).
+ * | | |10 = Up-down counter type.
+ * | | |11 = Reserved.
+ * |[16] |CNTMODE0 |EPWM Counter Mode
+ * | | |0 = Auto-reload mode.
+ * | | |1 = One-shot mode.
+ * |[17] |CNTMODE1 |EPWM Counter Mode
+ * | | |0 = Auto-reload mode.
+ * | | |1 = One-shot mode.
+ * |[18] |CNTMODE2 |EPWM Counter Mode
+ * | | |0 = Auto-reload mode.
+ * | | |1 = One-shot mode.
+ * |[19] |CNTMODE3 |EPWM Counter Mode
+ * | | |0 = Auto-reload mode.
+ * | | |1 = One-shot mode.
+ * |[20] |CNTMODE4 |EPWM Counter Mode
+ * | | |0 = Auto-reload mode.
+ * | | |1 = One-shot mode.
+ * |[21] |CNTMODE5 |EPWM Counter Mode
+ * | | |0 = Auto-reload mode.
+ * | | |1 = One-shot mode.
+ * |[24] |OUTMODE0 |EPWM Output Mode
+ * | | |Each bit n controls the output mode of corresponding EPWM channel n.
+ * | | |0 = EPWM independent mode.
+ * | | |1 = EPWM complementary mode.
+ * | | |Note: When operating in group function, these bits must all set to the same mode.
+ * |[25] |OUTMODE2 |EPWM Output Mode
+ * | | |Each bit n controls the output mode of corresponding EPWM channel n.
+ * | | |0 = EPWM independent mode.
+ * | | |1 = EPWM complementary mode.
+ * | | |Note: When operating in group function, these bits must all set to the same mode.
+ * |[26] |OUTMODE4 |EPWM Output Mode
+ * | | |Each bit n controls the output mode of corresponding EPWM channel n.
+ * | | |0 = EPWM independent mode.
+ * | | |1 = EPWM complementary mode.
+ * | | |Note: When operating in group function, these bits must all set to the same mode.
+ * @var EPWM_T::SYNC
+ * Offset: 0x08 EPWM Synchronization Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PHSEN0 |SYNC Phase Enable Bits
+ * | | |0 = EPWM counter disable to load PHS value.
+ * | | |1 = EPWM counter enable to load PHS value.
+ * |[1] |PHSEN2 |SYNC Phase Enable Bits
+ * | | |0 = EPWM counter disable to load PHS value.
+ * | | |1 = EPWM counter enable to load PHS value.
+ * |[2] |PHSEN4 |SYNC Phase Enable Bits
+ * | | |0 = EPWM counter disable to load PHS value.
+ * | | |1 = EPWM counter enable to load PHS value.
+ * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection
+ * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
+ * | | |01 = Counter equal to 0.
+ * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
+ * | | |11 = SYNC_OUT will not be generated.
+ * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection
+ * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
+ * | | |01 = Counter equal to 0.
+ * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
+ * | | |11 = SYNC_OUT will not be generated.
+ * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection
+ * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
+ * | | |01 = Counter equal to 0.
+ * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
+ * | | |11 = SYNC_OUT will not be generated.
+ * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits
+ * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled.
+ * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled.
+ * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection
+ * | | |000 = Filter clock = HCLK.
+ * | | |001 = Filter clock = HCLK/2.
+ * | | |010 = Filter clock = HCLK/4.
+ * | | |011 = Filter clock = HCLK/8.
+ * | | |100 = Filter clock = HCLK/16.
+ * | | |101 = Filter clock = HCLK/32.
+ * | | |110 = Filter clock = HCLK/64.
+ * | | |111 = Filter clock = HCLK/128.
+ * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count
+ * | | |The register bits control the counter number of edge detector.
+ * |[23] |SINPINV |SYNC Input Pin Inverse
+ * | | |0 = The state of pin SYNC is passed to the negative edge detector.
+ * | | |1 = The inversed state of pin SYNC is passed to the negative edge detector.
+ * |[24] |PHSDIR0 |EPWM Phase Direction Control
+ * | | |0 = Control EPWM counter count decrement after synchronizing.
+ * | | |1 = Control EPWM counter count increment after synchronizing.
+ * |[25] |PHSDIR2 |EPWM Phase Direction Control
+ * | | |0 = Control EPWM counter count decrement after synchronizing.
+ * | | |1 = Control EPWM counter count increment after synchronizing.
+ * |[26] |PHSDIR4 |EPWM Phase Direction Control
+ * | | |0 = Control EPWM counter count decrement after synchronizing.
+ * | | |1 = Control EPWM counter count increment after synchronizing.
+ * @var EPWM_T::SWSYNC
+ * Offset: 0x0C EPWM Software Control Synchronization Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SWSYNC0 |Software SYNC Function
+ * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+ * |[1] |SWSYNC2 |Software SYNC Function
+ * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+ * |[2] |SWSYNC4 |Software SYNC Function
+ * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+ * @var EPWM_T::CLKSRC
+ * Offset: 0x10 EPWM Clock Source Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select
+ * | | |000 = EPWMx_CLK, x denotes 0 or 1.
+ * | | |001 = TIMER0 overflow.
+ * | | |010 = TIMER1 overflow.
+ * | | |011 = TIMER2 overflow.
+ * | | |100 = TIMER3 overflow.
+ * | | |Others = Reserved.
+ * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select
+ * | | |000 = EPWMx_CLK, x denotes 0 or 1.
+ * | | |001 = TIMER0 overflow.
+ * | | |010 = TIMER1 overflow.
+ * | | |011 = TIMER2 overflow.
+ * | | |100 = TIMER3 overflow.
+ * | | |Others = Reserved.
+ * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select
+ * | | |000 = EPWMx_CLK, x denotes 0 or 1.
+ * | | |001 = TIMER0 overflow.
+ * | | |010 = TIMER1 overflow.
+ * | | |011 = TIMER2 overflow.
+ * | | |100 = TIMER3 overflow.
+ * | | |Others = Reserved.
+ * @var EPWM_T::CLKPSC[3]
+ * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |CLKPSC |EPWM Counter Clock Prescale
+ * | | |The clock of EPWM counter is decided by clock prescaler
+ * | | |Each EPWM pair share one EPWM counter clock prescaler
+ * | | |The clock of EPWM counter is divided by (CLKPSC+ 1)
+ * @var EPWM_T::CNTEN
+ * Offset: 0x20 EPWM Counter Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTEN0 |EPWM Counter Enable Bits
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.
+ * | | |1 = EPWM Counter and clock prescaler Start Running.
+ * |[1] |CNTEN1 |EPWM Counter Enable Bits
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.
+ * | | |1 = EPWM Counter and clock prescaler Start Running.
+ * |[2] |CNTEN2 |EPWM Counter Enable Bits
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.
+ * | | |1 = EPWM Counter and clock prescaler Start Running.
+ * |[3] |CNTEN3 |EPWM Counter Enable Bits
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.
+ * | | |1 = EPWM Counter and clock prescaler Start Running.
+ * |[4] |CNTEN4 |EPWM Counter Enable Bits
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.
+ * | | |1 = EPWM Counter and clock prescaler Start Running.
+ * |[5] |CNTEN5 |EPWM Counter Enable Bits
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.
+ * | | |1 = EPWM Counter and clock prescaler Start Running.
+ * @var EPWM_T::CNTCLR
+ * Offset: 0x24 EPWM Clear Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit
+ * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+ * | | |0 = No effect.
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.
+ * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit
+ * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+ * | | |0 = No effect.
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.
+ * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit
+ * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+ * | | |0 = No effect.
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.
+ * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit
+ * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+ * | | |0 = No effect.
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.
+ * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit
+ * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+ * | | |0 = No effect.
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.
+ * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit
+ * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+ * | | |0 = No effect.
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.
+ * @var EPWM_T::LOAD
+ * Offset: 0x28 EPWM Load Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+ * | | |This bit is software write, hardware clear when current EPWM period end.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set load window of window loading mode.
+ * | | |Read Operation:
+ * | | |0 = No load window is set.
+ * | | |1 = Load window is set.
+ * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+ * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+ * | | |This bit is software write, hardware clear when current EPWM period end.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set load window of window loading mode.
+ * | | |Read Operation:
+ * | | |0 = No load window is set.
+ * | | |1 = Load window is set.
+ * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+ * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+ * | | |This bit is software write, hardware clear when current EPWM period end.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set load window of window loading mode.
+ * | | |Read Operation:
+ * | | |0 = No load window is set.
+ * | | |1 = Load window is set.
+ * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+ * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+ * | | |This bit is software write, hardware clear when current EPWM period end.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set load window of window loading mode.
+ * | | |Read Operation:
+ * | | |0 = No load window is set.
+ * | | |1 = Load window is set.
+ * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+ * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+ * | | |This bit is software write, hardware clear when current EPWM period end.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set load window of window loading mode.
+ * | | |Read Operation:
+ * | | |0 = No load window is set.
+ * | | |1 = Load window is set.
+ * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+ * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+ * | | |This bit is software write, hardware clear when current EPWM period end.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set load window of window loading mode.
+ * | | |Read Operation:
+ * | | |0 = No load window is set.
+ * | | |1 = Load window is set.
+ * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+ * @var EPWM_T::PERIOD[6]
+ * Offset: 0x30 EPWM Period Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PERIOD |EPWM Period Register
+ * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0.
+ * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD.
+ * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period.
+ * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+ * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period.
+ * @var EPWM_T::CMPDAT[6]
+ * Offset: 0x50 EPWM Comparator Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMP |EPWM Comparator Register
+ * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC.
+ * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.
+ * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
+ * @var EPWM_T::DTCTL[3]
+ * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |DTCNT |Dead-time Counter (Write Protect)
+ * | | |The dead-time can be calculated from the following formula:
+ * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect)
+ * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled
+ * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
+ * | | |0 = Dead-time insertion Disabled on the pin pair.
+ * | | |1 = Dead-time insertion Enabled on the pin pair.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect)
+ * | | |0 = Dead-time clock source from EPWM_CLK.
+ * | | |1 = Dead-time clock source from prescaler output.
+ * | | |Note: This register is write protected. Refer toREGWRPROT register.
+ * @var EPWM_T::PHS[3]
+ * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PHS |EPWM Synchronous Start Phase Bits
+ * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function.
+ * @var EPWM_T::CNT[6]
+ * Offset: 0x90 EPWM Counter Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CNT |EPWM Data Register (Read Only)
+ * | | |User can monitor CNTR to know the current value in 16-bit period counter.
+ * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only)
+ * | | |0 = Counter is Down count.
+ * | | |1 = Counter is UP count.
+ * @var EPWM_T::WGCTL0
+ * Offset: 0xB0 EPWM Generation Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |ZPCTL0 |EPWM Zero Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM zero point output Low.
+ * | | |10 = EPWM zero point output High.
+ * | | |11 = EPWM zero point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to zero.
+ * |[3:2] |ZPCTL1 |EPWM Zero Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM zero point output Low.
+ * | | |10 = EPWM zero point output High.
+ * | | |11 = EPWM zero point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to zero.
+ * |[5:4] |ZPCTL2 |EPWM Zero Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM zero point output Low.
+ * | | |10 = EPWM zero point output High.
+ * | | |11 = EPWM zero point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to zero.
+ * |[7:6] |ZPCTL3 |EPWM Zero Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM zero point output Low.
+ * | | |10 = EPWM zero point output High.
+ * | | |11 = EPWM zero point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to zero.
+ * |[9:8] |ZPCTL4 |EPWM Zero Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM zero point output Low.
+ * | | |10 = EPWM zero point output High.
+ * | | |11 = EPWM zero point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to zero.
+ * |[11:10] |ZPCTL5 |EPWM Zero Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM zero point output Low.
+ * | | |10 = EPWM zero point output High.
+ * | | |11 = EPWM zero point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to zero.
+ * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM period (center) point output Low.
+ * | | |10 = EPWM period (center) point output High.
+ * | | |11 = EPWM period (center) point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+ * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM period (center) point output Low.
+ * | | |10 = EPWM period (center) point output High.
+ * | | |11 = EPWM period (center) point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+ * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM period (center) point output Low.
+ * | | |10 = EPWM period (center) point output High.
+ * | | |11 = EPWM period (center) point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+ * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM period (center) point output Low.
+ * | | |10 = EPWM period (center) point output High.
+ * | | |11 = EPWM period (center) point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+ * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM period (center) point output Low.
+ * | | |10 = EPWM period (center) point output High.
+ * | | |11 = EPWM period (center) point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+ * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM period (center) point output Low.
+ * | | |10 = EPWM period (center) point output High.
+ * | | |11 = EPWM period (center) point output Toggle.
+ * | | |EPWM can control output level when EPWM counter count to (PERIODn+1).
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+ * @var EPWM_T::WGCTL1
+ * Offset: 0xB4 EPWM Generation Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare up point output Low.
+ * | | |10 = EPWM compare up point output High.
+ * | | |11 = EPWM compare up point output Toggle.
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+ * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare up point output Low.
+ * | | |10 = EPWM compare up point output High.
+ * | | |11 = EPWM compare up point output Toggle.
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+ * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare up point output Low.
+ * | | |10 = EPWM compare up point output High.
+ * | | |11 = EPWM compare up point output Toggle.
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+ * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare up point output Low.
+ * | | |10 = EPWM compare up point output High.
+ * | | |11 = EPWM compare up point output Toggle.
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+ * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare up point output Low.
+ * | | |10 = EPWM compare up point output High.
+ * | | |11 = EPWM compare up point output Toggle.
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+ * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare up point output Low.
+ * | | |10 = EPWM compare up point output High.
+ * | | |11 = EPWM compare up point output Toggle.
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+ * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare down point output Low.
+ * | | |10 = EPWM compare down point output High.
+ * | | |11 = EPWM compare down point output Toggle.
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+ * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare down point output Low.
+ * | | |10 = EPWM compare down point output High.
+ * | | |11 = EPWM compare down point output Toggle.
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+ * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare down point output Low.
+ * | | |10 = EPWM compare down point output High.
+ * | | |11 = EPWM compare down point output Toggle.
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+ * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare down point output Low.
+ * | | |10 = EPWM compare down point output High.
+ * | | |11 = EPWM compare down point output Toggle.
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+ * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare down point output Low.
+ * | | |10 = EPWM compare down point output High.
+ * | | |11 = EPWM compare down point output Toggle.
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+ * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control
+ * | | |00 = Do nothing.
+ * | | |01 = EPWM compare down point output Low.
+ * | | |10 = EPWM compare down point output High.
+ * | | |11 = EPWM compare down point output Toggle.
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+ * @var EPWM_T::MSKEN
+ * Offset: 0xB8 EPWM Mask Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MSKEN0 |EPWM Mask Enable Bits
+ * | | |The EPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+ * | | |0 = EPWM output signal is non-masked.
+ * | | |1 = EPWM output signal is masked and output MSKDATn data.
+ * |[1] |MSKEN1 |EPWM Mask Enable Bits
+ * | | |The EPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+ * | | |0 = EPWM output signal is non-masked.
+ * | | |1 = EPWM output signal is masked and output MSKDATn data.
+ * |[2] |MSKEN2 |EPWM Mask Enable Bits
+ * | | |The EPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+ * | | |0 = EPWM output signal is non-masked.
+ * | | |1 = EPWM output signal is masked and output MSKDATn data.
+ * |[3] |MSKEN3 |EPWM Mask Enable Bits
+ * | | |The EPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+ * | | |0 = EPWM output signal is non-masked.
+ * | | |1 = EPWM output signal is masked and output MSKDATn data.
+ * |[4] |MSKEN4 |EPWM Mask Enable Bits
+ * | | |The EPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+ * | | |0 = EPWM output signal is non-masked.
+ * | | |1 = EPWM output signal is masked and output MSKDATn data.
+ * |[5] |MSKEN5 |EPWM Mask Enable Bits
+ * | | |The EPWM output signal will be masked when this bit is enabled
+ * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+ * | | |0 = EPWM output signal is non-masked.
+ * | | |1 = EPWM output signal is masked and output MSKDATn data.
+ * @var EPWM_T::MSK
+ * Offset: 0xBC EPWM Mask Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MSKDAT0 |EPWM Mask Data Bit
+ * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+ * | | |0 = Output logic low to EPWM channel n.
+ * | | |1 = Output logic high to EPWM channel n.
+ * |[1] |MSKDAT1 |EPWM Mask Data Bit
+ * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+ * | | |0 = Output logic low to EPWM channel n.
+ * | | |1 = Output logic high to EPWM channel n.
+ * |[2] |MSKDAT2 |EPWM Mask Data Bit
+ * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+ * | | |0 = Output logic low to EPWM channel n.
+ * | | |1 = Output logic high to EPWM channel n.
+ * |[3] |MSKDAT3 |EPWM Mask Data Bit
+ * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+ * | | |0 = Output logic low to EPWM channel n.
+ * | | |1 = Output logic high to EPWM channel n.
+ * |[4] |MSKDAT4 |EPWM Mask Data Bit
+ * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+ * | | |0 = Output logic low to EPWM channel n.
+ * | | |1 = Output logic high to EPWM channel n.
+ * |[5] |MSKDAT5 |EPWM Mask Data Bit
+ * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+ * | | |0 = Output logic low to EPWM channel n.
+ * | | |1 = Output logic high to EPWM channel n.
+ * @var EPWM_T::BNF
+ * Offset: 0xC0 EPWM Brake Noise Filter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit
+ * | | |0 = Noise filter of EPWM Brake 0 Disabled.
+ * | | |1 = Noise filter of EPWM Brake 0 Enabled.
+ * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
+ * | | |000 = Filter clock = HCLK.
+ * | | |001 = Filter clock = HCLK/2.
+ * | | |010 = Filter clock = HCLK/4.
+ * | | |011 = Filter clock = HCLK/8.
+ * | | |100 = Filter clock = HCLK/16.
+ * | | |101 = Filter clock = HCLK/32.
+ * | | |110 = Filter clock = HCLK/64.
+ * | | |111 = Filter clock = HCLK/128.
+ * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count
+ * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
+ * |[7] |BRK0PINV |Brake 0 Pin Inverse
+ * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector.
+ * | | |1 = The inversed state of pin EPWMx_BRAKE10 is passed to the negative edge detector.
+ * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit
+ * | | |0 = Noise filter of EPWM Brake 1 Disabled.
+ * | | |1 = Noise filter of EPWM Brake 1 Enabled.
+ * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
+ * | | |000 = Filter clock = HCLK.
+ * | | |001 = Filter clock = HCLK/2.
+ * | | |010 = Filter clock = HCLK/4.
+ * | | |011 = Filter clock = HCLK/8.
+ * | | |100 = Filter clock = HCLK/16.
+ * | | |101 = Filter clock = HCLK/32.
+ * | | |110 = Filter clock = HCLK/64.
+ * | | |111 = Filter clock = HCLK/128.
+ * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count
+ * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
+ * |[15] |BRK1PINV |Brake 1 Pin Inverse
+ * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
+ * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
+ * |[16] |BK0SRC |Brake 0 Pin Source Select
+ * | | |For EPWM0 setting:
+ * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0.
+ * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0.
+ * | | |For EPWM1 setting:
+ * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0.
+ * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0.
+ * |[24] |BK1SRC |Brake 1 Pin Source Select
+ * | | |For EPWM0 setting:
+ * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1.
+ * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1.
+ * | | |For EPWM1 setting:
+ * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1.
+ * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1.
+ * @var EPWM_T::FAILBRK
+ * Offset: 0xC4 EPWM System Fail Brake Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit
+ * | | |0 = Brake Function triggered by CSS detection Disabled.
+ * | | |1 = Brake Function triggered by CSS detection Enabled.
+ * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit
+ * | | |0 = Brake Function triggered by BOD Disabled.
+ * | | |1 = Brake Function triggered by BOD Enabled.
+ * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit
+ * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
+ * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
+ * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit
+ * | | |0 = Brake Function triggered by Core lockup detection Disabled.
+ * | | |1 = Brake Function triggered by Core lockup detection Enabled.
+ * @var EPWM_T::BRKCTL[3]
+ * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
+ * | | |0 = ACMP0_O as edge-detect brake source Disabled.
+ * | | |1 = ACMP0_O as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
+ * | | |0 = ACMP1_O as edge-detect brake source Disabled.
+ * | | |1 = ACMP1_O as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)
+ * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled.
+ * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)
+ * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled.
+ * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect)
+ * | | |0 = System Fail condition as edge-detect brake source Disabled.
+ * | | |1 = System Fail condition as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
+ * | | |0 = ACMP0_O as level-detect brake source Disabled.
+ * | | |1 = ACMP0_O as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
+ * | | |0 = ACMP1_O as level-detect brake source Disabled.
+ * | | |1 = ACMP1_O as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
+ * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled.
+ * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
+ * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled.
+ * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect)
+ * | | |0 = System Fail condition as level-detect brake source Disabled.
+ * | | |1 = System Fail condition as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect)
+ * | | |00 = EPWMx brake event will not affect even channels output.
+ * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened.
+ * | | |10 = EPWM even channel output low level when EPWMx brake event happened.
+ * | | |11 = EPWM even channel output high level when EPWMx brake event happened.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect)
+ * | | |00 = EPWMx brake event will not affect odd channels output.
+ * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened.
+ * | | |10 = EPWM odd channel output low level when EPWMx brake event happened.
+ * | | |11 = EPWM odd channel output high level when EPWMx brake event happened.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)
+ * | | |0 = EADCRM as edge-detect brake source Disabled.
+ * | | |1 = EADCRM as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)
+ * | | |0 = EADCRM as level-detect brake source Disabled.
+ * | | |1 = EADCRM as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * @var EPWM_T::POLCTL
+ * Offset: 0xD4 EPWM Pin Polar Inverse Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PINV0 |EPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of EPWM output.
+ * | | |0 = EPWM output polar inverse Disabled.
+ * | | |1 = EPWM output polar inverse Enabled.
+ * |[1] |PINV1 |EPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of EPWM output.
+ * | | |0 = EPWM output polar inverse Disabled.
+ * | | |1 = EPWM output polar inverse Enabled.
+ * |[2] |PINV2 |EPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of EPWM output.
+ * | | |0 = EPWM output polar inverse Disabled.
+ * | | |1 = EPWM output polar inverse Enabled.
+ * |[3] |PINV3 |EPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of EPWM output.
+ * | | |0 = EPWM output polar inverse Disabled.
+ * | | |1 = EPWM output polar inverse Enabled.
+ * |[4] |PINV4 |EPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of EPWM output.
+ * | | |0 = EPWM output polar inverse Disabled.
+ * | | |1 = EPWM output polar inverse Enabled.
+ * |[5] |PINV5 |EPWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of EPWM output.
+ * | | |0 = EPWM output polar inverse Disabled.
+ * | | |1 = EPWM output polar inverse Enabled.
+ * @var EPWM_T::POEN
+ * Offset: 0xD8 EPWM Output Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |POEN0 |EPWM Pin Output Enable Bits
+ * | | |0 = EPWM pin at tri-state.
+ * | | |1 = EPWM pin in output mode.
+ * |[1] |POEN1 |EPWM Pin Output Enable Bits
+ * | | |0 = EPWM pin at tri-state.
+ * | | |1 = EPWM pin in output mode.
+ * |[2] |POEN2 |EPWM Pin Output Enable Bits
+ * | | |0 = EPWM pin at tri-state.
+ * | | |1 = EPWM pin in output mode.
+ * |[3] |POEN3 |EPWM Pin Output Enable Bits
+ * | | |0 = EPWM pin at tri-state.
+ * | | |1 = EPWM pin in output mode.
+ * |[4] |POEN4 |EPWM Pin Output Enable Bits
+ * | | |0 = EPWM pin at tri-state.
+ * | | |1 = EPWM pin in output mode.
+ * |[5] |POEN5 |EPWM Pin Output Enable Bits
+ * | | |0 = EPWM pin at tri-state.
+ * | | |1 = EPWM pin in output mode.
+ * @var EPWM_T::SWBRK
+ * Offset: 0xDC EPWM Software Brake Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
+ * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
+ * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
+ * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
+ * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
+ * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
+ * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * @var EPWM_T::INTEN0
+ * Offset: 0xE0 EPWM Interrupt Enable Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits
+ * | | |0 = Zero point interrupt Disabled.
+ * | | |1 = Zero point interrupt Enabled.
+ * | | |Note: Odd channels will read always 0 at complementary mode.
+ * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits
+ * | | |0 = Zero point interrupt Disabled.
+ * | | |1 = Zero point interrupt Enabled.
+ * | | |Note: Odd channels will read always 0 at complementary mode.
+ * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits
+ * | | |0 = Zero point interrupt Disabled.
+ * | | |1 = Zero point interrupt Enabled.
+ * | | |Note: Odd channels will read always 0 at complementary mode.
+ * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits
+ * | | |0 = Zero point interrupt Disabled.
+ * | | |1 = Zero point interrupt Enabled.
+ * | | |Note: Odd channels will read always 0 at complementary mode.
+ * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits
+ * | | |0 = Zero point interrupt Disabled.
+ * | | |1 = Zero point interrupt Enabled.
+ * | | |Note: Odd channels will read always 0 at complementary mode.
+ * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits
+ * | | |0 = Zero point interrupt Disabled.
+ * | | |1 = Zero point interrupt Enabled.
+ * | | |Note: Odd channels will read always 0 at complementary mode.
+ * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits
+ * | | |0 = Period point interrupt Disabled.
+ * | | |1 = Period point interrupt Enabled.
+ * | | |Note1: When up-down counter type period point means center point.
+ * | | |Note2: Odd channels will read always 0 at complementary mode.
+ * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits
+ * | | |0 = Period point interrupt Disabled.
+ * | | |1 = Period point interrupt Enabled.
+ * | | |Note1: When up-down counter type period point means center point.
+ * | | |Note2: Odd channels will read always 0 at complementary mode.
+ * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits
+ * | | |0 = Period point interrupt Disabled.
+ * | | |1 = Period point interrupt Enabled.
+ * | | |Note1: When up-down counter type period point means center point.
+ * | | |Note2: Odd channels will read always 0 at complementary mode.
+ * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits
+ * | | |0 = Period point interrupt Disabled.
+ * | | |1 = Period point interrupt Enabled.
+ * | | |Note1: When up-down counter type period point means center point.
+ * | | |Note2: Odd channels will read always 0 at complementary mode.
+ * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits
+ * | | |0 = Period point interrupt Disabled.
+ * | | |1 = Period point interrupt Enabled.
+ * | | |Note1: When up-down counter type period point means center point.
+ * | | |Note2: Odd channels will read always 0 at complementary mode.
+ * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits
+ * | | |0 = Period point interrupt Disabled.
+ * | | |1 = Period point interrupt Enabled.
+ * | | |Note1: When up-down counter type period point means center point.
+ * | | |Note2: Odd channels will read always 0 at complementary mode.
+ * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+ * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+ * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+ * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+ * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+ * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+ * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+ * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+ * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+ * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+ * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+ * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+ * @var EPWM_T::INTEN1
+ * Offset: 0xE4 EPWM Interrupt Enable Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
+ * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
+ * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
+ * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
+ * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
+ * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
+ * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
+ * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled.
+ * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
+ * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled.
+ * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
+ * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled.
+ * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * @var EPWM_T::INTSTS0
+ * Offset: 0xE8 EPWM Interrupt Flag Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+ * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+ * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+ * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+ * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+ * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+ * |[8] |PIF0 |EPWM Period Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+ * |[9] |PIF1 |EPWM Period Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+ * |[10] |PIF2 |EPWM Period Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+ * |[11] |PIF3 |EPWM Period Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+ * |[12] |PIF4 |EPWM Period Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+ * |[13] |PIF5 |EPWM Period Point Interrupt Flag
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+ * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+ * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+ * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+ * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+ * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+ * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+ * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+ * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+ * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+ * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+ * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+ * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+ * @var EPWM_T::INTSTS1
+ * Offset: 0xEC EPWM Interrupt Flag Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel0 edge-detect brake event do not happened.
+ * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel1 edge-detect brake event do not happened.
+ * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel2 edge-detect brake event do not happened.
+ * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel3 edge-detect brake event do not happened.
+ * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel4 edge-detect brake event do not happened.
+ * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel5 edge-detect brake event do not happened.
+ * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel0 level-detect brake event do not happened.
+ * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel1 level-detect brake event do not happened.
+ * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel2 level-detect brake event do not happened.
+ * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel3 level-detect brake event do not happened.
+ * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel4 level-detect brake event do not happened.
+ * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = EPWM channel5 level-detect brake event do not happened.
+ * | | |1 = When EEPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel0 edge-detect brake state is released.
+ * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear.
+ * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel1 edge-detect brake state is released.
+ * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear.
+ * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel2 edge-detect brake state is released.
+ * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear.
+ * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel3 edge-detect brake state is released.
+ * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear.
+ * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel4 edge-detect brake state is released.
+ * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear.
+ * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel5 edge-detect brake state is released.
+ * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear.
+ * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel0 level-detect brake state is released.
+ * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+ * | | |The EPWM waveform will start output from next full EPWM period.
+ * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel1 level-detect brake state is released.
+ * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+ * | | |The EPWM waveform will start output from next full EPWM period.
+ * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel2 level-detect brake state is released.
+ * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+ * | | |The EPWM waveform will start output from next full EPWM period.
+ * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel3 level-detect brake state is released.
+ * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+ * | | |The EPWM waveform will start output from next full EPWM period.
+ * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel4 level-detect brake state is released.
+ * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+ * | | |The EPWM waveform will start output from next full EPWM period.
+ * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only)
+ * | | |0 = EPWM channel5 level-detect brake state is released.
+ * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+ * | | |The EPWM waveform will start output from next full EPWM period.
+ * @var EPWM_T::DACTRGEN
+ * Offset: 0xF4 EPWM Trigger DAC Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+ * | | |0 = EPWM period point trigger DAC function Disabled.
+ * | | |1 = EPWM period point trigger DAC function Enabled.
+ * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+ * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+ * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+ * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+ * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+ * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+ * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+ * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+ * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+ * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+ * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+ * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+ * @var EPWM_T::EADCTS0
+ * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select
+ * | | |0000 = EPWM_CH0 zero point.
+ * | | |0001 = EPWM_CH0 period point.
+ * | | |0010 = EPWM_CH0 zero or period point.
+ * | | |0011 = EPWM_CH0 up-count CMPDAT point.
+ * | | |0100 = EPWM_CH0 down-count CMPDAT point.
+ * | | |0101 = EPWM_CH1 zero point.
+ * | | |0110 = EPWM_CH1 period point.
+ * | | |0111 = EPWM_CH1 zero or period point.
+ * | | |1000 = EPWM_CH1 up-count CMPDAT point.
+ * | | |1001 = EPWM_CH1 down-count CMPDAT point.
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
+ * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit
+ * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select
+ * | | |0000 = EPWM_CH0 zero point.
+ * | | |0001 = EPWM_CH0 period point.
+ * | | |0010 = EPWM_CH0 zero or period point.
+ * | | |0011 = EPWM_CH0 up-count CMPDAT point.
+ * | | |0100 = EPWM_CH0 down-count CMPDAT point.
+ * | | |0101 = EPWM_CH1 zero point.
+ * | | |0110 = EPWM_CH1 period point.
+ * | | |0111 = EPWM_CH1 zero or period point.
+ * | | |1000 = EPWM_CH1 up-count CMPDAT point.
+ * | | |1001 = EPWM_CH1 down-count CMPDAT point.
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
+ * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit
+ * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select
+ * | | |0000 = EPWM_CH2 zero point.
+ * | | |0001 = EPWM_CH2 period point.
+ * | | |0010 = EPWM_CH2 zero or period point.
+ * | | |0011 = EPWM_CH2 up-count CMPDAT point.
+ * | | |0100 = EPWM_CH2 down-count CMPDAT point.
+ * | | |0101 = EPWM_CH3 zero point.
+ * | | |0110 = EPWM_CH3 period point.
+ * | | |0111 = EPWM_CH3 zero or period point.
+ * | | |1000 = EPWM_CH3 up-count CMPDAT point.
+ * | | |1001 = EPWM_CH3 down-count CMPDAT point.
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
+ * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit
+ * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select
+ * | | |0000 = EPWM_CH2 zero point.
+ * | | |0001 = EPWM_CH2 period point.
+ * | | |0010 = EPWM_CH2 zero or period point.
+ * | | |0011 = EPWM_CH2 up-count CMPDAT point.
+ * | | |0100 = EPWM_CH2 down-count CMPDAT point.
+ * | | |0101 = EPWM_CH3 zero point.
+ * | | |0110 = EPWM_CH3 period point.
+ * | | |0111 = EPWM_CH3 zero or period point.
+ * | | |1000 = EPWM_CH3 up-count CMPDAT point.
+ * | | |1001 = EPWM_CH3 down-count CMPDAT point.
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
+ * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit
+ * @var EPWM_T::EADCTS1
+ * Offset: 0xFC EPWM Trigger EADC Source Select Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select
+ * | | |0000 = EPWM_CH4 zero point.
+ * | | |0001 = EPWM_CH4 period point.
+ * | | |0010 = EPWM_CH4 zero or period point.
+ * | | |0011 = EPWM_CH4 up-count CMPDAT point.
+ * | | |0100 = EPWM_CH4 down-count CMPDAT point.
+ * | | |0101 = EPWM_CH5 zero point.
+ * | | |0110 = EPWM_CH5 period point.
+ * | | |0111 = EPWM_CH5 zero or period point.
+ * | | |1000 = EPWM_CH5 up-count CMPDAT point.
+ * | | |1001 = EPWM_CH5 down-count CMPDAT point.
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
+ * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit
+ * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select
+ * | | |0000 = EPWM_CH4 zero point.
+ * | | |0001 = EPWM_CH4 period point.
+ * | | |0010 = EPWM_CH4 zero or period point.
+ * | | |0011 = EPWM_CH4 up-count CMPDAT point.
+ * | | |0100 = EPWM_CH4 down-count CMPDAT point.
+ * | | |0101 = EPWM_CH5 zero point.
+ * | | |0110 = EPWM_CH5 period point.
+ * | | |0111 = EPWM_CH5 zero or period point.
+ * | | |1000 = EPWM_CH5 up-count CMPDAT point.
+ * | | |1001 = EPWM_CH5 down-count CMPDAT point.
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
+ * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit
+ * @var EPWM_T::FTCMPDAT[3]
+ * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FTCMP |EPWM Free Trigger Compare Register
+ * | | |FTCMP use to compare with even CNTR to trigger EADC
+ * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
+ * @var EPWM_T::SSCTL
+ * Offset: 0x110 EPWM Synchronous Start Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+ * | | |0 = EPWM synchronous start function Disabled.
+ * | | |1 = EPWM synchronous start function Enabled.
+ * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+ * | | |0 = EPWM synchronous start function Disabled.
+ * | | |1 = EPWM synchronous start function Enabled.
+ * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+ * | | |0 = EPWM synchronous start function Disabled.
+ * | | |1 = EPWM synchronous start function Enabled.
+ * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+ * | | |0 = EPWM synchronous start function Disabled.
+ * | | |1 = EPWM synchronous start function Enabled.
+ * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+ * | | |0 = EPWM synchronous start function Disabled.
+ * | | |1 = EPWM synchronous start function Enabled.
+ * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+ * | | |0 = EPWM synchronous start function Disabled.
+ * | | |1 = EPWM synchronous start function Enabled.
+ * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits
+ * | | |00 = Synchronous start source come from EPWM0.
+ * | | |01 = Synchronous start source come from EPWM1.
+ * | | |10 = Synchronous start source come from BPWM0.
+ * | | |11 = Synchronous start source come from BPWM1.
+ * @var EPWM_T::SSTRG
+ * Offset: 0x114 EPWM Synchronous Start Trigger Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only)
+ * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.
+ * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled.
+ * @var EPWM_T::LEBCTL
+ * Offset: 0x118 EPWM Leading Edge Blanking Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit
+ * | | |0 = EPWM Leading Edge Blanking Disabled.
+ * | | |1 = EPWM Leading Edge Blanking Enabled.
+ * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit
+ * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled.
+ * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled.
+ * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit
+ * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled.
+ * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled.
+ * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit
+ * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled.
+ * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled.
+ * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type
+ * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting.
+ * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting.
+ * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting.
+ * | | |3 = Reserved.
+ * @var EPWM_T::LEBCNT
+ * Offset: 0x11C EPWM Leading Edge Blanking Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter
+ * | | |This counter value decides leading edge blanking window size
+ * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK.
+ * @var EPWM_T::STATUS
+ * Offset: 0x120 EPWM Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+ * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+ * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+ * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+ * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+ * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+ * |[8] |SYNCINF0 |Input Synchronization Latched Flag
+ * | | |0 = Indicates no SYNC_IN event has occurred.
+ * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+ * |[9] |SYNCINF2 |Input Synchronization Latched Flag
+ * | | |0 = Indicates no SYNC_IN event has occurred.
+ * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+ * |[10] |SYNCINF4 |Input Synchronization Latched Flag
+ * | | |0 = Indicates no SYNC_IN event has occurred.
+ * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+ * |[16] |EADCTRGF0 |EADC Start of Conversion Flag
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[17] |EADCTRGF1 |EADC Start of Conversion Flag
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[18] |EADCTRGF2 |EADC Start of Conversion Flag
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[19] |EADCTRGF3 |EADC Start of Conversion Flag
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[20] |EADCTRGF4 |EADC Start of Conversion Flag
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[21] |EADCTRGF5 |EADC Start of Conversion Flag
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[24] |DACTRGF |DAC Start of Conversion Flag
+ * | | |0 = Indicates no DAC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
+ * @var EPWM_T::IFA[6]
+ * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter
+ * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.
+ * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period.
+ * |[24] |STPMOD |EPWM_CHn Interrupt Flag Accumulator Stop Mode Enable Bits
+ * | | |0 = EPWM_CHn interrupt flag accumulator stop mode disable.
+ * | | |1 = EPWM_CHn interrupt flag accumulator stop mode enable.
+ * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select
+ * | | |00 = CNT equal to Zero in channel n.
+ * | | |01 = CNT equal to PERIOD in channel n.
+ * | | |10 = CNT equal to CMPU in channel n.
+ * | | |11 = CNT equal to CMPD in channel n.
+ * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits
+ * | | |0 = EPWM_CHn interrupt flag accumulator disable.
+ * | | |1 = EPWM_CHn interrupt flag accumulator enable.
+ * @var EPWM_T::AINTSTS
+ * Offset: 0x150 EPWM Accumulator Interrupt Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+ * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+ * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+ * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+ * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+ * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+ * @var EPWM_T::AINTEN
+ * Offset: 0x154 EPWM Accumulator Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.
+ * @var EPWM_T::APDMACTL
+ * Offset: 0x158 EPWM Accumulator PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits
+ * | | |0 = Channel n PDMA function Disabled.
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+ * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits
+ * | | |0 = Channel n PDMA function Disabled.
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+ * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits
+ * | | |0 = Channel n PDMA function Disabled.
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+ * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits
+ * | | |0 = Channel n PDMA function Disabled.
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+ * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits
+ * | | |0 = Channel n PDMA function Disabled.
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+ * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits
+ * | | |0 = Channel n PDMA function Disabled.
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+ * @var EPWM_T::CAPINEN
+ * Offset: 0x200 EPWM Capture Input Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAPINEN0 |Capture Input Enable Bits
+ * | | |0 = EPWM Channel capture input path Disabled
+ * | | |The input of EPWM channel capture function is always regarded as 0.
+ * | | |1 = EPWM Channel capture input path Enabled
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
+ * |[1] |CAPINEN1 |Capture Input Enable Bits
+ * | | |0 = EPWM Channel capture input path Disabled
+ * | | |The input of EPWM channel capture function is always regarded as 0.
+ * | | |1 = EPWM Channel capture input path Enabled
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
+ * |[2] |CAPINEN2 |Capture Input Enable Bits
+ * | | |0 = EPWM Channel capture input path Disabled
+ * | | |The input of EPWM channel capture function is always regarded as 0.
+ * | | |1 = EPWM Channel capture input path Enabled
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
+ * |[3] |CAPINEN3 |Capture Input Enable Bits
+ * | | |0 = EPWM Channel capture input path Disabled
+ * | | |The input of EPWM channel capture function is always regarded as 0.
+ * | | |1 = EPWM Channel capture input path Enabled
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
+ * |[4] |CAPINEN4 |Capture Input Enable Bits
+ * | | |0 = EPWM Channel capture input path Disabled
+ * | | |The input of EPWM channel capture function is always regarded as 0.
+ * | | |1 = EPWM Channel capture input path Enabled
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
+ * |[5] |CAPINEN5 |Capture Input Enable Bits
+ * | | |0 = EPWM Channel capture input path Disabled
+ * | | |The input of EPWM channel capture function is always regarded as 0.
+ * | | |1 = EPWM Channel capture input path Enabled
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
+ * @var EPWM_T::CAPCTL
+ * Offset: 0x204 EPWM Capture Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAPEN0 |Capture Function Enable Bits
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[1] |CAPEN1 |Capture Function Enable Bits
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[2] |CAPEN2 |Capture Function Enable Bits
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[3] |CAPEN3 |Capture Function Enable Bits
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[4] |CAPEN4 |Capture Function Enable Bits
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[5] |CAPEN5 |Capture Function Enable Bits
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[8] |CAPINV0 |Capture Inverter Enable Bits
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[9] |CAPINV1 |Capture Inverter Enable Bits
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[10] |CAPINV2 |Capture Inverter Enable Bits
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[11] |CAPINV3 |Capture Inverter Enable Bits
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[12] |CAPINV4 |Capture Inverter Enable Bits
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[13] |CAPINV5 |Capture Inverter Enable Bits
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * @var EPWM_T::CAPSTS
+ * Offset: 0x208 EPWM Capture Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+ * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+ * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+ * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+ * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+ * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+ * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+ * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+ * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+ * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+ * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+ * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+ * @var EPWM_T::PDMACTL
+ * Offset: 0x23C EPWM PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable
+ * | | |0 = Channel 0/1 PDMA function Disabled.
+ * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
+ * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer
+ * | | |00 = Reserved.
+ * | | |01 = EPWM_RCAPDAT0/1.
+ * | | |10 = EPWM_FCAPDAT0/1.
+ * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1.
+ * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
+ * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11.
+ * | | |0 = EPWM_FCAPDAT0/1 is the first captured data to memory.
+ * | | |1 = EPWM_RCAPDAT0/1 is the first captured data to memory.
+ * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer
+ * | | |0 = Channel0.
+ * | | |1 = Channel1.
+ * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable
+ * | | |0 = Channel 2/3 PDMA function Disabled.
+ * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
+ * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer
+ * | | |00 = Reserved.
+ * | | |01 = EPWM_RCAPDAT2/3.
+ * | | |10 = EPWM_FCAPDAT2/3.
+ * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3.
+ * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
+ * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11.
+ * | | |0 = EPWM_FCAPDAT2/3 is the first captured data to memory.
+ * | | |1 = EPWM_RCAPDAT2/3 is the first captured data to memory.
+ * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer
+ * | | |0 = Channel2.
+ * | | |1 = Channel3.
+ * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable
+ * | | |0 = Channel 4/5 PDMA function Disabled.
+ * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
+ * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer
+ * | | |00 = Reserved.
+ * | | |01 = EPWM_RCAPDAT4/5.
+ * | | |10 = EPWM_FCAPDAT4/5.
+ * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5.
+ * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
+ * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11.
+ * | | |0 = EPWM_FCAPDAT4/5 is the first captured data to memory.
+ * | | |1 = EPWM_RCAPDAT4/5 is the first captured data to memory.
+ * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer
+ * | | |0 = Channel4.
+ * | | |1 = Channel5.
+ * @var EPWM_T::PDMACAP[3]
+ * Offset: 0x240 EPWM Capture Channel 01 PDMA Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only)
+ * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA.
+ * @var EPWM_T::CAPIEN
+ * Offset: 0x250 EPWM Capture Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits
+ * | | |0 = Capture rising edge latch interrupt Disabled.
+ * | | |1 = Capture rising edge latch interrupt Enabled.
+ * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits
+ * | | |0 = Capture rising edge latch interrupt Disabled.
+ * | | |1 = Capture rising edge latch interrupt Enabled.
+ * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits
+ * | | |0 = Capture rising edge latch interrupt Disabled.
+ * | | |1 = Capture rising edge latch interrupt Enabled.
+ * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits
+ * | | |0 = Capture rising edge latch interrupt Disabled.
+ * | | |1 = Capture rising edge latch interrupt Enabled.
+ * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits
+ * | | |0 = Capture rising edge latch interrupt Disabled.
+ * | | |1 = Capture rising edge latch interrupt Enabled.
+ * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits
+ * | | |0 = Capture rising edge latch interrupt Disabled.
+ * | | |1 = Capture rising edge latch interrupt Enabled.
+ * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits
+ * | | |0 = Capture falling edge latch interrupt Disabled.
+ * | | |1 = Capture falling edge latch interrupt Enabled.
+ * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits
+ * | | |0 = Capture falling edge latch interrupt Disabled.
+ * | | |1 = Capture falling edge latch interrupt Enabled.
+ * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits
+ * | | |0 = Capture falling edge latch interrupt Disabled.
+ * | | |1 = Capture falling edge latch interrupt Enabled.
+ * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits
+ * | | |0 = Capture falling edge latch interrupt Disabled.
+ * | | |1 = Capture falling edge latch interrupt Enabled.
+ * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits
+ * | | |0 = Capture falling edge latch interrupt Disabled.
+ * | | |1 = Capture falling edge latch interrupt Enabled.
+ * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits
+ * | | |0 = Capture falling edge latch interrupt Disabled.
+ * | | |1 = Capture falling edge latch interrupt Enabled.
+ * @var EPWM_T::CAPIF
+ * Offset: 0x254 EPWM Capture Interrupt Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+ * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+ * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+ * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+ * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+ * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+ * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+ * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+ * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+ * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+ * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+ * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+ * @var EPWM_T::PBUF[6]
+ * Offset: 0x304 EPWM PERIOD0~5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only)
+ * | | |Used as PERIOD active register.
+ * @var EPWM_T::CMPBUF[6]
+ * Offset: 0x31C EPWM CMPDAT0~5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only)
+ * | | |Used as CMP active register.
+ * @var EPWM_T::CPSCBUF[3]
+ * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer
+ * | | |Use as EPWM counter clock prescale active register.
+ * @var EPWM_T::FTCBUF[3]
+ * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only)
+ * | | |Used as FTCMPDAT active register.
+ * @var EPWM_T::FTCI
+ * Offset: 0x34C EPWM FTCMPDAT Indicator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
+ * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
+ * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
+ * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
+ * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
+ * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
+ */
+ __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */
+ __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */
+ __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */
+ __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */
+ __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */
+ __IO uint32_t CLKPSC[3]; /*!< [0x0014] EPWM Clock Prescale Register 0/1,2/3,4/5 */
+ __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */
+ __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */
+ __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t PERIOD[6]; /*!< [0x0030] EPWM Period Register 0~5 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CMPDAT[6]; /*!< [0x0050] EPWM Comparator Register 0~5 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DTCTL[3]; /*!< [0x0070] EPWM Dead-Time Control Register 0/1,2/3,4/5 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t PHS[3]; /*!< [0x0080] EPWM Counter Phase Register 0/1,2/3,4/5 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE4[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t CNT[6]; /*!< [0x0090] EPWM Counter Register 0~5 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE5[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */
+ __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */
+ __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */
+ __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */
+ __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */
+ __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */
+ __IO uint32_t BRKCTL[3]; /*!< [0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 */
+ __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */
+ __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */
+ __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */
+ __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */
+ __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */
+ __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */
+ __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE6[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */
+ __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */
+ __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */
+ __IO uint32_t FTCMPDAT[3]; /*!< [0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE7[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */
+ __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */
+ __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */
+ __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */
+ __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE8[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t IFA[6]; /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE9[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */
+ __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */
+ __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE10[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t FDEN; /*!< [0x0160] EPWM Fault Detect Enable Register */
+ __IO uint32_t FDCTL[6]; /*!< [0x0164~0x178] EPWM Fault Detect Control Register 0~5 */
+ __IO uint32_t FDIEN; /*!< [0x017C] EPWM Fault Detect Interrupt Enable Register */
+ __IO uint32_t FDSTS; /*!< [0x0180] EPWM Fault Detect Interrupt Flag Register */
+ __IO uint32_t EADCPSCCTL; /*!< [0x0184] EPWM Trigger EADC Prescale Control Register */
+ __IO uint32_t EADCPSC0; /*!< [0x0188] EPWM Trigger EADC Prescale Register 0 */
+ __IO uint32_t EADCPSC1; /*!< [0x018C] EPWM Trigger EADC Prescale Register 1 */
+ __IO uint32_t EADCPSCNT0; /*!< [0x0190] EPWM Trigger EADC Prescale Counter Register 0 */
+ __IO uint32_t EADCPSCNT1; /*!< [0x0194] EPWM Trigger EADC Prescale Counter Register 1 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE11[26];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */
+ __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */
+ __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */
+ ECAPDAT_T CAPDAT[6]; /*!< [0x020C] EPWM Rising and Falling Capture Data Register 0~5 */
+ __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */
+ __I uint32_t PDMACAP[3]; /*!< [0x0240] EPWM Capture Channel 01,23,45 PDMA Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE12[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */
+ __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE13[43];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t PBUF[6]; /*!< [0x0304] EPWM PERIOD0~5 Buffer */
+ __I uint32_t CMPBUF[6]; /*!< [0x031c] EPWM CMPDAT0~5 Buffer */
+ __I uint32_t CPSCBUF[3]; /*!< [0x0334] EPWM CLKPSC0_1/2_3/4_5 Buffer */
+ __I uint32_t FTCBUF[3]; /*!< [0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer */
+ __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */
+
+} EPWM_T;
+
+/**
+ @addtogroup EPWM_CONST EPWM Bit Field Definition
+ Constant Definitions for EPWM Controller
+@{ */
+
+#define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */
+#define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */
+
+#define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */
+#define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */
+
+#define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */
+#define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */
+
+#define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */
+#define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */
+
+#define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */
+#define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */
+
+#define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */
+#define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */
+
+#define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */
+#define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */
+
+#define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */
+#define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */
+
+#define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */
+#define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */
+
+#define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */
+#define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */
+
+#define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */
+#define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */
+
+#define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */
+#define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */
+
+#define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */
+#define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */
+
+#define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */
+#define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */
+
+#define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */
+#define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */
+
+#define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */
+#define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */
+
+#define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */
+#define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */
+
+#define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */
+#define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */
+
+#define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */
+#define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */
+
+#define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */
+#define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */
+
+#define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */
+#define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */
+
+#define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */
+#define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */
+
+#define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */
+#define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */
+
+#define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */
+#define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */
+
+#define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */
+#define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */
+
+#define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */
+#define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */
+
+#define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */
+#define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */
+
+#define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */
+#define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */
+
+#define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */
+#define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */
+
+#define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */
+#define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */
+
+#define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */
+#define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */
+
+#define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */
+#define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */
+
+#define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */
+#define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */
+
+#define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */
+#define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */
+
+#define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */
+#define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */
+
+#define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */
+#define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */
+
+#define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */
+#define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */
+
+#define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */
+#define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */
+
+#define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */
+#define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */
+
+#define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */
+#define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */
+
+#define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */
+#define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */
+
+#define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */
+#define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */
+
+#define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */
+#define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */
+
+#define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */
+#define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */
+
+#define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */
+#define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */
+
+#define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */
+#define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */
+
+#define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */
+#define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */
+
+#define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */
+#define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */
+
+#define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */
+#define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */
+
+#define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */
+#define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */
+
+#define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */
+#define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */
+
+#define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */
+#define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */
+
+#define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */
+#define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */
+
+#define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */
+#define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */
+
+#define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */
+#define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */
+
+#define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */
+#define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */
+
+#define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */
+#define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */
+
+#define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */
+#define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */
+
+#define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */
+#define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */
+
+#define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */
+#define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */
+
+#define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */
+#define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */
+
+#define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */
+#define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */
+
+#define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */
+#define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */
+
+#define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */
+#define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */
+
+#define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */
+#define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */
+
+#define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */
+#define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */
+
+#define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */
+#define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */
+
+#define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */
+#define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */
+
+#define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */
+#define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */
+
+#define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */
+#define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */
+
+#define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */
+#define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */
+
+#define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */
+#define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */
+
+#define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */
+#define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */
+
+#define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */
+#define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */
+
+#define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */
+#define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */
+
+#define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */
+#define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */
+
+#define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */
+#define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */
+
+#define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */
+#define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */
+
+#define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */
+#define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */
+
+#define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */
+#define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */
+
+#define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */
+#define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */
+
+#define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */
+#define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */
+
+#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */
+#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */
+
+#define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */
+#define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */
+
+#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */
+#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */
+
+#define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */
+#define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */
+
+#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */
+#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */
+
+#define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */
+#define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */
+
+#define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */
+#define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */
+
+#define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */
+#define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */
+
+#define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */
+#define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */
+
+#define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */
+#define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */
+
+#define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */
+#define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */
+
+#define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */
+#define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */
+
+#define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */
+#define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */
+
+#define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */
+#define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */
+
+#define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */
+#define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */
+
+#define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */
+#define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */
+
+#define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */
+#define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */
+
+#define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */
+#define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */
+
+#define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */
+#define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */
+
+#define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */
+#define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */
+
+#define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */
+#define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */
+
+#define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */
+#define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */
+
+#define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */
+#define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */
+
+#define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */
+#define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */
+
+#define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */
+#define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */
+
+#define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */
+#define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */
+
+#define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */
+#define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */
+
+#define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */
+#define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */
+
+#define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */
+#define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */
+
+#define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */
+#define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */
+
+#define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */
+#define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */
+
+#define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */
+#define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */
+
+#define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */
+#define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */
+
+#define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */
+#define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */
+
+#define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */
+#define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */
+
+#define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */
+#define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */
+
+#define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */
+#define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */
+
+#define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */
+#define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */
+
+#define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */
+#define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */
+
+#define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */
+#define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */
+
+#define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */
+#define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */
+
+#define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */
+#define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */
+
+#define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */
+#define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */
+
+#define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */
+#define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */
+
+#define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */
+#define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */
+
+#define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */
+#define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */
+
+#define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */
+#define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */
+
+#define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */
+#define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */
+
+#define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */
+#define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */
+
+#define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */
+#define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */
+
+#define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */
+#define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */
+
+#define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */
+#define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */
+
+#define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */
+#define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */
+
+#define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */
+#define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */
+
+#define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */
+#define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */
+
+#define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */
+#define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */
+
+#define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */
+#define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */
+
+#define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */
+#define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */
+
+#define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */
+#define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */
+
+#define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */
+#define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */
+
+#define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */
+#define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */
+
+#define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */
+#define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */
+
+#define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */
+#define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */
+
+#define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */
+#define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */
+
+#define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */
+#define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */
+
+#define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */
+#define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */
+
+#define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */
+#define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */
+
+#define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */
+#define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */
+
+#define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */
+#define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */
+
+#define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */
+#define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */
+
+#define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */
+#define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */
+
+#define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */
+#define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */
+
+#define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */
+#define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */
+
+#define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */
+#define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */
+
+#define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */
+#define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */
+
+#define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */
+#define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */
+
+#define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */
+#define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */
+
+#define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */
+#define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */
+
+#define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */
+#define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */
+
+#define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */
+#define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */
+
+#define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */
+#define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */
+
+#define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */
+#define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */
+
+#define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */
+#define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */
+
+#define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */
+#define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */
+
+#define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */
+#define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */
+
+#define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */
+#define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */
+
+#define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */
+#define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */
+
+#define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */
+#define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */
+
+#define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */
+#define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */
+
+#define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */
+#define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */
+
+#define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */
+#define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */
+
+#define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */
+#define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */
+
+#define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */
+#define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */
+
+#define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */
+#define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */
+
+#define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */
+#define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */
+
+#define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */
+#define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */
+
+#define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */
+#define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */
+
+#define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */
+#define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */
+
+#define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */
+#define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */
+
+#define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */
+#define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */
+
+#define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */
+#define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */
+
+#define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */
+#define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */
+
+#define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */
+#define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */
+
+#define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */
+#define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */
+
+#define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */
+#define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */
+
+#define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */
+#define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */
+
+#define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */
+#define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */
+
+#define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */
+#define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */
+
+#define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */
+#define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */
+
+#define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */
+#define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */
+
+#define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */
+#define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */
+
+#define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */
+#define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */
+
+#define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */
+#define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */
+
+#define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */
+#define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */
+
+#define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */
+#define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */
+
+#define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */
+#define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */
+
+#define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */
+#define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */
+
+#define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */
+#define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */
+
+#define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */
+#define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */
+
+#define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */
+#define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */
+
+#define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */
+#define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */
+
+#define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */
+#define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */
+
+#define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */
+#define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */
+
+#define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */
+#define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */
+
+#define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */
+#define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */
+
+#define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */
+#define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */
+
+#define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */
+#define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */
+
+#define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */
+#define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */
+
+#define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */
+#define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */
+
+#define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */
+#define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */
+
+#define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */
+#define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */
+
+#define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */
+#define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */
+
+#define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */
+#define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */
+
+#define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */
+#define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */
+
+#define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */
+#define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */
+
+#define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */
+#define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */
+
+#define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */
+#define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */
+
+#define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */
+#define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */
+
+#define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */
+#define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */
+
+#define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */
+#define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */
+
+#define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */
+#define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */
+
+#define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */
+#define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */
+
+#define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */
+#define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */
+
+#define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */
+#define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */
+
+#define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */
+#define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */
+
+#define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */
+#define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */
+
+#define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */
+#define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */
+
+#define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */
+#define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */
+
+#define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */
+#define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */
+
+#define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */
+#define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */
+
+#define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */
+#define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */
+
+#define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */
+#define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */
+
+#define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */
+#define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */
+
+#define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */
+#define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */
+
+#define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */
+#define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */
+
+#define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */
+#define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */
+
+#define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */
+#define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */
+
+#define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */
+#define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */
+
+#define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */
+#define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */
+
+#define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */
+#define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */
+
+#define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */
+#define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */
+
+#define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */
+#define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */
+
+#define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */
+#define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */
+
+#define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */
+#define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */
+
+#define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */
+#define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */
+
+#define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */
+#define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */
+
+#define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */
+#define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */
+
+#define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */
+#define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */
+
+#define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */
+#define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */
+
+#define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */
+#define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */
+
+#define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */
+#define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */
+
+#define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */
+#define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */
+
+#define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */
+#define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */
+
+#define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */
+#define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */
+
+#define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */
+#define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */
+
+#define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */
+#define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */
+
+#define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */
+#define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */
+
+#define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */
+#define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */
+
+#define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */
+#define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */
+
+#define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */
+#define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */
+
+#define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */
+#define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */
+
+#define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */
+#define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */
+
+#define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */
+#define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */
+
+#define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */
+#define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */
+
+#define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */
+#define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */
+
+#define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */
+#define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */
+
+#define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */
+#define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */
+
+#define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */
+#define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */
+
+#define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */
+#define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */
+
+#define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */
+#define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */
+
+#define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */
+#define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */
+
+#define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */
+#define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */
+
+#define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */
+#define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */
+
+#define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */
+#define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */
+
+#define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */
+#define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */
+
+#define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */
+#define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */
+
+#define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */
+#define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */
+
+#define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */
+#define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */
+
+#define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */
+#define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */
+
+#define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */
+#define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */
+
+#define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */
+#define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */
+
+#define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */
+#define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */
+
+#define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */
+#define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */
+
+#define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */
+#define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */
+
+#define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */
+#define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */
+
+#define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */
+#define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */
+
+#define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */
+#define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */
+
+#define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */
+#define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */
+
+#define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */
+#define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */
+
+#define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */
+#define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */
+
+#define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */
+#define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */
+
+#define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */
+#define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */
+
+#define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */
+#define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */
+
+#define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */
+#define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */
+
+#define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */
+#define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */
+
+#define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */
+#define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */
+
+#define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */
+#define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */
+
+#define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */
+#define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */
+
+#define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */
+#define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */
+
+#define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */
+#define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */
+
+#define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */
+#define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */
+
+#define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */
+#define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */
+
+#define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */
+#define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */
+
+#define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */
+#define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */
+
+#define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */
+#define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */
+
+#define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */
+#define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */
+
+#define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */
+#define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */
+
+#define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */
+#define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */
+
+#define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */
+#define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */
+
+#define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */
+#define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */
+
+#define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */
+#define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */
+
+#define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */
+#define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */
+
+#define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */
+#define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */
+
+#define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */
+#define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */
+
+#define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */
+#define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */
+
+#define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */
+#define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */
+
+#define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */
+#define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */
+
+#define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */
+#define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */
+
+#define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */
+#define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */
+
+#define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */
+#define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */
+
+#define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */
+#define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */
+
+#define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */
+#define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */
+
+#define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */
+#define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */
+
+#define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */
+#define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */
+
+#define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */
+#define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */
+
+#define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */
+#define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */
+
+#define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */
+#define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */
+
+#define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */
+#define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */
+
+#define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */
+#define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */
+
+#define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */
+#define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */
+
+#define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */
+#define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */
+
+#define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */
+#define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */
+
+#define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */
+#define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */
+
+#define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */
+#define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */
+
+#define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */
+#define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */
+
+#define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */
+#define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */
+
+#define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */
+#define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */
+
+#define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */
+#define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */
+
+#define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */
+#define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */
+
+#define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */
+#define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */
+
+#define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */
+#define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */
+
+#define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */
+#define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */
+
+#define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */
+#define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */
+
+#define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */
+#define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */
+
+#define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */
+#define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */
+
+#define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */
+#define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */
+
+#define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */
+#define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */
+
+#define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */
+#define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */
+
+#define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */
+#define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */
+
+#define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */
+#define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */
+
+#define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */
+#define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */
+
+#define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */
+#define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */
+
+#define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */
+#define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */
+
+#define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */
+#define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */
+
+#define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */
+#define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */
+
+#define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */
+#define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */
+
+#define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */
+#define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */
+
+#define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */
+#define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */
+
+#define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */
+#define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */
+
+#define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */
+#define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */
+
+#define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */
+#define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */
+
+#define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */
+#define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */
+
+#define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */
+#define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */
+
+#define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */
+#define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */
+
+#define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */
+#define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */
+
+#define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */
+#define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */
+
+#define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */
+#define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */
+
+#define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */
+#define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */
+
+#define EPWM_IFA0_STPMOD_Pos (24) /*!< EPWM_T::IFA0: STPMOD Position */
+#define EPWM_IFA0_STPMOD_Msk (0x1ul << EPWM_IFA0_STPMOD_Pos) /*!< EPWM_T::IFA0: STPMOD Mask */
+
+#define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */
+#define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */
+
+#define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */
+#define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */
+
+#define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */
+#define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */
+
+#define EPWM_IFA1_STPMOD_Pos (24) /*!< EPWM_T::IFA1: STPMOD Position */
+#define EPWM_IFA1_STPMOD_Msk (0x1ul << EPWM_IFA1_STPMOD_Pos) /*!< EPWM_T::IFA1: STPMOD Mask */
+
+#define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */
+#define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */
+
+#define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */
+#define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */
+
+#define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */
+#define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */
+
+#define EPWM_IFA2_STPMOD_Pos (24) /*!< EPWM_T::IFA2: STPMOD Position */
+#define EPWM_IFA2_STPMOD_Msk (0x1ul << EPWM_IFA2_STPMOD_Pos) /*!< EPWM_T::IFA2: STPMOD Mask */
+
+#define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */
+#define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */
+
+#define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */
+#define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */
+
+#define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */
+#define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */
+
+#define EPWM_IFA3_STPMOD_Pos (24) /*!< EPWM_T::IFA3: STPMOD Position */
+#define EPWM_IFA3_STPMOD_Msk (0x1ul << EPWM_IFA3_STPMOD_Pos) /*!< EPWM_T::IFA3: STPMOD Mask */
+
+#define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */
+#define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */
+
+#define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */
+#define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */
+
+#define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */
+#define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */
+
+#define EPWM_IFA4_STPMOD_Pos (24) /*!< EPWM_T::IFA4: STPMOD Position */
+#define EPWM_IFA4_STPMOD_Msk (0x1ul << EPWM_IFA4_STPMOD_Pos) /*!< EPWM_T::IFA4: STPMOD Mask */
+
+#define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */
+#define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */
+
+#define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */
+#define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */
+
+#define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */
+#define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */
+
+#define EPWM_IFA5_STPMOD_Pos (24) /*!< EPWM_T::IFA5: STPMOD Position */
+#define EPWM_IFA5_STPMOD_Msk (0x1ul << EPWM_IFA5_STPMOD_Pos) /*!< EPWM_T::IFA5: STPMOD Mask */
+
+#define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */
+#define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */
+
+#define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */
+#define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */
+
+#define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */
+#define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */
+
+#define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */
+#define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */
+
+#define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */
+#define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */
+
+#define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */
+#define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */
+
+#define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */
+#define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */
+
+#define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */
+#define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */
+
+#define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */
+#define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */
+
+#define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */
+#define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */
+
+#define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */
+#define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */
+
+#define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */
+#define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */
+
+#define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */
+#define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */
+
+#define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */
+#define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */
+
+#define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */
+#define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */
+
+#define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */
+#define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */
+
+#define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */
+#define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */
+
+#define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */
+#define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */
+
+#define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */
+#define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */
+
+#define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */
+#define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */
+
+#define EPWM_FDEN_FDEN0_Pos (0) /*!< EPWM_T::FDEN: FDEN0 Position */
+#define EPWM_FDEN_FDEN0_Msk (0x1ul << EPWM_FDEN_FDEN0_Pos) /*!< EPWM_T::FDEN: FDEN0 Mask */
+
+#define EPWM_FDEN_FDEN1_Pos (1) /*!< EPWM_T::FDEN: FDEN1 Position */
+#define EPWM_FDEN_FDEN1_Msk (0x1ul << EPWM_FDEN_FDEN1_Pos) /*!< EPWM_T::FDEN: FDEN1 Mask */
+
+#define EPWM_FDEN_FDEN2_Pos (2) /*!< EPWM_T::FDEN: FDEN2 Position */
+#define EPWM_FDEN_FDEN2_Msk (0x1ul << EPWM_FDEN_FDEN2_Pos) /*!< EPWM_T::FDEN: FDEN2 Mask */
+
+#define EPWM_FDEN_FDEN3_Pos (3) /*!< EPWM_T::FDEN: FDEN3 Position */
+#define EPWM_FDEN_FDEN3_Msk (0x1ul << EPWM_FDEN_FDEN3_Pos) /*!< EPWM_T::FDEN: FDEN3 Mask */
+
+#define EPWM_FDEN_FDEN4_Pos (4) /*!< EPWM_T::FDEN: FDEN4 Position */
+#define EPWM_FDEN_FDEN4_Msk (0x1ul << EPWM_FDEN_FDEN4_Pos) /*!< EPWM_T::FDEN: FDEN4 Mask */
+
+#define EPWM_FDEN_FDEN5_Pos (5) /*!< EPWM_T::FDEN: FDEN5 Position */
+#define EPWM_FDEN_FDEN5_Msk (0x1ul << EPWM_FDEN_FDEN5_Pos) /*!< EPWM_T::FDEN: FDEN5 Mask */
+
+#define EPWM_FDEN_FDODIS0_Pos (8) /*!< EPWM_T::FDEN: FDODIS0 Position */
+#define EPWM_FDEN_FDODIS0_Msk (0x1ul << EPWM_FDEN_FDODIS0_Pos) /*!< EPWM_T::FDEN: FDODIS0 Mask */
+
+#define EPWM_FDEN_FDODIS1_Pos (9) /*!< EPWM_T::FDEN: FDODIS1 Position */
+#define EPWM_FDEN_FDODIS1_Msk (0x1ul << EPWM_FDEN_FDODIS1_Pos) /*!< EPWM_T::FDEN: FDODIS1 Mask */
+
+#define EPWM_FDEN_FDODIS2_Pos (10) /*!< EPWM_T::FDEN: FDODIS2 Position */
+#define EPWM_FDEN_FDODIS2_Msk (0x1ul << EPWM_FDEN_FDODIS2_Pos) /*!< EPWM_T::FDEN: FDODIS2 Mask */
+
+#define EPWM_FDEN_FDODIS3_Pos (11) /*!< EPWM_T::FDEN: FDODIS3 Position */
+#define EPWM_FDEN_FDODIS3_Msk (0x1ul << EPWM_FDEN_FDODIS3_Pos) /*!< EPWM_T::FDEN: FDODIS3 Mask */
+
+#define EPWM_FDEN_FDODIS4_Pos (12) /*!< EPWM_T::FDEN: FDODIS4 Position */
+#define EPWM_FDEN_FDODIS4_Msk (0x1ul << EPWM_FDEN_FDODIS4_Pos) /*!< EPWM_T::FDEN: FDODIS4 Mask */
+
+#define EPWM_FDEN_FDODIS5_Pos (13) /*!< EPWM_T::FDEN: FDODIS5 Position */
+#define EPWM_FDEN_FDODIS5_Msk (0x1ul << EPWM_FDEN_FDODIS5_Pos) /*!< EPWM_T::FDEN: FDODIS5 Mask */
+
+#define EPWM_FDEN_FDCKS0_Pos (16) /*!< EPWM_T::FDEN: FDCKS0 Position */
+#define EPWM_FDEN_FDCKS0_Msk (0x1ul << EPWM_FDEN_FDCKS0_Pos) /*!< EPWM_T::FDEN: FDCKS0 Mask */
+
+#define EPWM_FDEN_FDCKS1_Pos (17) /*!< EPWM_T::FDEN: FDCKS1 Position */
+#define EPWM_FDEN_FDCKS1_Msk (0x1ul << EPWM_FDEN_FDCKS1_Pos) /*!< EPWM_T::FDEN: FDCKS1 Mask */
+
+#define EPWM_FDEN_FDCKS2_Pos (18) /*!< EPWM_T::FDEN: FDCKS2 Position */
+#define EPWM_FDEN_FDCKS2_Msk (0x1ul << EPWM_FDEN_FDCKS2_Pos) /*!< EPWM_T::FDEN: FDCKS2 Mask */
+
+#define EPWM_FDEN_FDCKS3_Pos (19) /*!< EPWM_T::FDEN: FDCKS3 Position */
+#define EPWM_FDEN_FDCKS3_Msk (0x1ul << EPWM_FDEN_FDCKS3_Pos) /*!< EPWM_T::FDEN: FDCKS3 Mask */
+
+#define EPWM_FDEN_FDCKS4_Pos (20) /*!< EPWM_T::FDEN: FDCKS4 Position */
+#define EPWM_FDEN_FDCKS4_Msk (0x1ul << EPWM_FDEN_FDCKS4_Pos) /*!< EPWM_T::FDEN: FDCKS4 Mask */
+
+#define EPWM_FDEN_FDCKS5_Pos (21) /*!< EPWM_T::FDEN: FDCKS5 Position */
+#define EPWM_FDEN_FDCKS5_Msk (0x1ul << EPWM_FDEN_FDCKS5_Pos) /*!< EPWM_T::FDEN: FDCKS5 Mask */
+
+#define EPWM_FDCTL0_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL0: TRMSKCNT Position */
+#define EPWM_FDCTL0_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL0: TRMSKCNT Mask */
+
+#define EPWM_FDCTL0_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL0: FDMSKEN Position */
+#define EPWM_FDCTL0_FDMSKEN_Msk (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos) /*!< EPWM_T::FDCTL0: FDMSKEN Mask */
+
+#define EPWM_FDCTL0_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL0: DGSMPCYC Position */
+#define EPWM_FDCTL0_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL0: DGSMPCYC Mask */
+
+#define EPWM_FDCTL0_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL0: FDCKSEL Position */
+#define EPWM_FDCTL0_FDCKSEL_Msk (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos) /*!< EPWM_T::FDCTL0: FDCKSEL Mask */
+
+#define EPWM_FDCTL0_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL0: FDDGEN Position */
+#define EPWM_FDCTL0_FDDGEN_Msk (0x1ul << EPWM_FDCTL0_FDDGEN_Pos) /*!< EPWM_T::FDCTL0: FDDGEN Mask */
+
+#define EPWM_FDCTL1_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL1: TRMSKCNT Position */
+#define EPWM_FDCTL1_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL1: TRMSKCNT Mask */
+
+#define EPWM_FDCTL1_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL1: FDMSKEN Position */
+#define EPWM_FDCTL1_FDMSKEN_Msk (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos) /*!< EPWM_T::FDCTL1: FDMSKEN Mask */
+
+#define EPWM_FDCTL1_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL1: DGSMPCYC Position */
+#define EPWM_FDCTL1_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL1: DGSMPCYC Mask */
+
+#define EPWM_FDCTL1_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL1: FDCKSEL Position */
+#define EPWM_FDCTL1_FDCKSEL_Msk (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos) /*!< EPWM_T::FDCTL1: FDCKSEL Mask */
+
+#define EPWM_FDCTL1_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL1: FDDGEN Position */
+#define EPWM_FDCTL1_FDDGEN_Msk (0x1ul << EPWM_FDCTL1_FDDGEN_Pos) /*!< EPWM_T::FDCTL1: FDDGEN Mask */
+
+#define EPWM_FDCTL2_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL2: TRMSKCNT Position */
+#define EPWM_FDCTL2_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL2: TRMSKCNT Mask */
+
+#define EPWM_FDCTL2_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL2: FDMSKEN Position */
+#define EPWM_FDCTL2_FDMSKEN_Msk (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos) /*!< EPWM_T::FDCTL2: FDMSKEN Mask */
+
+#define EPWM_FDCTL2_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL2: DGSMPCYC Position */
+#define EPWM_FDCTL2_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL2: DGSMPCYC Mask */
+
+#define EPWM_FDCTL2_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL2: FDCKSEL Position */
+#define EPWM_FDCTL2_FDCKSEL_Msk (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos) /*!< EPWM_T::FDCTL2: FDCKSEL Mask */
+
+#define EPWM_FDCTL2_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL2: FDDGEN Position */
+#define EPWM_FDCTL2_FDDGEN_Msk (0x1ul << EPWM_FDCTL2_FDDGEN_Pos) /*!< EPWM_T::FDCTL2: FDDGEN Mask */
+
+#define EPWM_FDCTL3_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL3: TRMSKCNT Position */
+#define EPWM_FDCTL3_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL3: TRMSKCNT Mask */
+
+#define EPWM_FDCTL3_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL3: FDMSKEN Position */
+#define EPWM_FDCTL3_FDMSKEN_Msk (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos) /*!< EPWM_T::FDCTL3: FDMSKEN Mask */
+
+#define EPWM_FDCTL3_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL3: DGSMPCYC Position */
+#define EPWM_FDCTL3_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL3: DGSMPCYC Mask */
+
+#define EPWM_FDCTL3_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL3: FDCKSEL Position */
+#define EPWM_FDCTL3_FDCKSEL_Msk (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos) /*!< EPWM_T::FDCTL3: FDCKSEL Mask */
+
+#define EPWM_FDCTL3_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL3: FDDGEN Position */
+#define EPWM_FDCTL3_FDDGEN_Msk (0x1ul << EPWM_FDCTL3_FDDGEN_Pos) /*!< EPWM_T::FDCTL3: FDDGEN Mask */
+
+#define EPWM_FDCTL4_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL4: TRMSKCNT Position */
+#define EPWM_FDCTL4_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL4: TRMSKCNT Mask */
+
+#define EPWM_FDCTL4_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL4: FDMSKEN Position */
+#define EPWM_FDCTL4_FDMSKEN_Msk (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos) /*!< EPWM_T::FDCTL4: FDMSKEN Mask */
+
+#define EPWM_FDCTL4_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL4: DGSMPCYC Position */
+#define EPWM_FDCTL4_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL4: DGSMPCYC Mask */
+
+#define EPWM_FDCTL4_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL4: FDCKSEL Position */
+#define EPWM_FDCTL4_FDCKSEL_Msk (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos) /*!< EPWM_T::FDCTL4: FDCKSEL Mask */
+
+#define EPWM_FDCTL4_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL4: FDDGEN Position */
+#define EPWM_FDCTL4_FDDGEN_Msk (0x1ul << EPWM_FDCTL4_FDDGEN_Pos) /*!< EPWM_T::FDCTL4: FDDGEN Mask */
+
+#define EPWM_FDCTL5_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL5: TRMSKCNT Position */
+#define EPWM_FDCTL5_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL5: TRMSKCNT Mask */
+
+#define EPWM_FDCTL5_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL5: FDMSKEN Position */
+#define EPWM_FDCTL5_FDMSKEN_Msk (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos) /*!< EPWM_T::FDCTL5: FDMSKEN Mask */
+
+#define EPWM_FDCTL5_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL5: DGSMPCYC Position */
+#define EPWM_FDCTL5_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL5: DGSMPCYC Mask */
+
+#define EPWM_FDCTL5_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL5: FDCKSEL Position */
+#define EPWM_FDCTL5_FDCKSEL_Msk (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos) /*!< EPWM_T::FDCTL5: FDCKSEL Mask */
+
+#define EPWM_FDCTL5_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL5: FDDGEN Position */
+#define EPWM_FDCTL5_FDDGEN_Msk (0x1ul << EPWM_FDCTL5_FDDGEN_Pos) /*!< EPWM_T::FDCTL5: FDDGEN Mask */
+
+#define EPWM_FDIEN_FDIEN0_Pos (0) /*!< EPWM_T::FDIEN: FDIEN0 Position */
+#define EPWM_FDIEN_FDIEN0_Msk (0x1ul << EPWM_FDIEN_FDIEN0_Pos) /*!< EPWM_T::FDIEN: FDIEN0 Mask */
+
+#define EPWM_FDIEN_FDIEN1_Pos (1) /*!< EPWM_T::FDIEN: FDIEN1 Position */
+#define EPWM_FDIEN_FDIEN1_Msk (0x1ul << EPWM_FDIEN_FDIEN1_Pos) /*!< EPWM_T::FDIEN: FDIEN1 Mask */
+
+#define EPWM_FDIEN_FDIEN2_Pos (2) /*!< EPWM_T::FDIEN: FDIEN2 Position */
+#define EPWM_FDIEN_FDIEN2_Msk (0x1ul << EPWM_FDIEN_FDIEN2_Pos) /*!< EPWM_T::FDIEN: FDIEN2 Mask */
+
+#define EPWM_FDIEN_FDIEN3_Pos (3) /*!< EPWM_T::FDIEN: FDIEN3 Position */
+#define EPWM_FDIEN_FDIEN3_Msk (0x1ul << EPWM_FDIEN_FDIEN3_Pos) /*!< EPWM_T::FDIEN: FDIEN3 Mask */
+
+#define EPWM_FDIEN_FDIEN4_Pos (4) /*!< EPWM_T::FDIEN: FDIEN4 Position */
+#define EPWM_FDIEN_FDIEN4_Msk (0x1ul << EPWM_FDIEN_FDIEN4_Pos) /*!< EPWM_T::FDIEN: FDIEN4 Mask */
+
+#define EPWM_FDIEN_FDIEN5_Pos (5) /*!< EPWM_T::FDIEN: FDIEN5 Position */
+#define EPWM_FDIEN_FDIEN5_Msk (0x1ul << EPWM_FDIEN_FDIEN5_Pos) /*!< EPWM_T::FDIEN: FDIEN5 Mask */
+
+#define EPWM_FDSTS_FDIF0_Pos (0) /*!< EPWM_T::FDSTS: FDIF0 Position */
+#define EPWM_FDSTS_FDIF0_Msk (0x1ul << EPWM_FDSTS_FDIF0_Pos) /*!< EPWM_T::FDSTS: FDIF0 Mask */
+
+#define EPWM_FDSTS_FDIF1_Pos (1) /*!< EPWM_T::FDSTS: FDIF1 Position */
+#define EPWM_FDSTS_FDIF1_Msk (0x1ul << EPWM_FDSTS_FDIF1_Pos) /*!< EPWM_T::FDSTS: FDIF1 Mask */
+
+#define EPWM_FDSTS_FDIF2_Pos (2) /*!< EPWM_T::FDSTS: FDIF2 Position */
+#define EPWM_FDSTS_FDIF2_Msk (0x1ul << EPWM_FDSTS_FDIF2_Pos) /*!< EPWM_T::FDSTS: FDIF2 Mask */
+
+#define EPWM_FDSTS_FDIF3_Pos (3) /*!< EPWM_T::FDSTS: FDIF3 Position */
+#define EPWM_FDSTS_FDIF3_Msk (0x1ul << EPWM_FDSTS_FDIF3_Pos) /*!< EPWM_T::FDSTS: FDIF3 Mask */
+
+#define EPWM_FDSTS_FDIF4_Pos (4) /*!< EPWM_T::FDSTS: FDIF4 Position */
+#define EPWM_FDSTS_FDIF4_Msk (0x1ul << EPWM_FDSTS_FDIF4_Pos) /*!< EPWM_T::FDSTS: FDIF4 Mask */
+
+#define EPWM_FDSTS_FDIF5_Pos (5) /*!< EPWM_T::FDSTS: FDIF5 Position */
+#define EPWM_FDSTS_FDIF5_Msk (0x1ul << EPWM_FDSTS_FDIF5_Pos) /*!< EPWM_T::FDSTS: FDIF5 Mask */
+
+#define EPWM_EADCPSCCTL_PSCEN0_Pos (0) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Position */
+#define EPWM_EADCPSCCTL_PSCEN0_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Mask */
+
+#define EPWM_EADCPSCCTL_PSCEN1_Pos (1) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Position */
+#define EPWM_EADCPSCCTL_PSCEN1_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Mask */
+
+#define EPWM_EADCPSCCTL_PSCEN2_Pos (2) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Position */
+#define EPWM_EADCPSCCTL_PSCEN2_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Mask */
+
+#define EPWM_EADCPSCCTL_PSCEN3_Pos (3) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Position */
+#define EPWM_EADCPSCCTL_PSCEN3_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Mask */
+
+#define EPWM_EADCPSCCTL_PSCEN4_Pos (4) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Position */
+#define EPWM_EADCPSCCTL_PSCEN4_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Mask */
+
+#define EPWM_EADCPSCCTL_PSCEN5_Pos (5) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Position */
+#define EPWM_EADCPSCCTL_PSCEN5_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Mask */
+
+#define EPWM_EADCPSC0_EADCPSC0_Pos (0) /*!< EPWM_T::EADCPSC0: EADCPSC0 Position */
+#define EPWM_EADCPSC0_EADCPSC0_Msk (0xful << EPWM_EADCPSC0_EADCPSC0_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC0 Mask */
+
+#define EPWM_EADCPSC0_EADCPSC1_Pos (8) /*!< EPWM_T::EADCPSC0: EADCPSC1 Position */
+#define EPWM_EADCPSC0_EADCPSC1_Msk (0xful << EPWM_EADCPSC0_EADCPSC1_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC1 Mask */
+
+#define EPWM_EADCPSC0_EADCPSC2_Pos (16) /*!< EPWM_T::EADCPSC0: EADCPSC2 Position */
+#define EPWM_EADCPSC0_EADCPSC2_Msk (0xful << EPWM_EADCPSC0_EADCPSC2_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC2 Mask */
+
+#define EPWM_EADCPSC0_EADCPSC3_Pos (24) /*!< EPWM_T::EADCPSC0: EADCPSC3 Position */
+#define EPWM_EADCPSC0_EADCPSC3_Msk (0xful << EPWM_EADCPSC0_EADCPSC3_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC3 Mask */
+
+#define EPWM_EADCPSC1_EADCPSC4_Pos (0) /*!< EPWM_T::EADCPSC1: EADCPSC4 Position */
+#define EPWM_EADCPSC1_EADCPSC4_Msk (0xful << EPWM_EADCPSC1_EADCPSC4_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC4 Mask */
+
+#define EPWM_EADCPSC1_EADCPSC5_Pos (8) /*!< EPWM_T::EADCPSC1: EADCPSC5 Position */
+#define EPWM_EADCPSC1_EADCPSC5_Msk (0xful << EPWM_EADCPSC1_EADCPSC5_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC5 Mask */
+
+#define EPWM_EADCPSCNT0_PSCNT0_Pos (0) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Position */
+#define EPWM_EADCPSCNT0_PSCNT0_Msk (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Mask */
+
+#define EPWM_EADCPSCNT0_PSCNT1_Pos (8) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Position */
+#define EPWM_EADCPSCNT0_PSCNT1_Msk (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Mask */
+
+#define EPWM_EADCPSCNT0_PSCNT2_Pos (16) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Position */
+#define EPWM_EADCPSCNT0_PSCNT2_Msk (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Mask */
+
+#define EPWM_EADCPSCNT0_PSCNT3_Pos (24) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Position */
+#define EPWM_EADCPSCNT0_PSCNT3_Msk (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Mask */
+
+#define EPWM_EADCPSCNT1_PSCNT4_Pos (0) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Position */
+#define EPWM_EADCPSCNT1_PSCNT4_Msk (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Mask */
+
+#define EPWM_EADCPSCNT1_PSCNT5_Pos (8) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Position */
+#define EPWM_EADCPSCNT1_PSCNT5_Msk (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Mask */
+
+#define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */
+#define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */
+
+#define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */
+#define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */
+
+#define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */
+#define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */
+
+#define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */
+#define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */
+
+#define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */
+#define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */
+
+#define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */
+#define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */
+
+#define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */
+#define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */
+
+#define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */
+#define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */
+
+#define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */
+#define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */
+
+#define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */
+#define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */
+
+#define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */
+#define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */
+
+#define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */
+#define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */
+
+#define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */
+#define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */
+
+#define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */
+#define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */
+
+#define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */
+#define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */
+
+#define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */
+#define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */
+
+#define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */
+#define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */
+
+#define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */
+#define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */
+
+#define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */
+#define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */
+
+#define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */
+#define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */
+
+#define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */
+#define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */
+
+#define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */
+#define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */
+
+#define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */
+#define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */
+
+#define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */
+#define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */
+
+#define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */
+#define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */
+
+#define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */
+#define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */
+
+#define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */
+#define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */
+
+#define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */
+#define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */
+
+#define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */
+#define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */
+
+#define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */
+#define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */
+
+#define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */
+#define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */
+
+#define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */
+#define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */
+
+#define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */
+#define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */
+
+#define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */
+#define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */
+
+#define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */
+#define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */
+
+#define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */
+#define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */
+
+#define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */
+#define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */
+
+#define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */
+#define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */
+
+#define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */
+#define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */
+
+#define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */
+#define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */
+
+#define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */
+#define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */
+
+#define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */
+#define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */
+
+#define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */
+#define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */
+
+#define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */
+#define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */
+
+#define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */
+#define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */
+
+#define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */
+#define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */
+
+#define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */
+#define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */
+
+#define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */
+#define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */
+
+#define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */
+#define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */
+
+#define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */
+#define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */
+
+#define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */
+#define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */
+
+#define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */
+#define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */
+
+#define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */
+#define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */
+
+#define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */
+#define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */
+
+#define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */
+#define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */
+
+#define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */
+#define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */
+
+#define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */
+#define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */
+
+#define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */
+#define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */
+
+#define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */
+#define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */
+
+#define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */
+#define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */
+
+#define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */
+#define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */
+
+#define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */
+#define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */
+
+#define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */
+#define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */
+
+#define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */
+#define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */
+
+#define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */
+#define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */
+
+#define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */
+#define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */
+
+#define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */
+#define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */
+
+#define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */
+#define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */
+
+#define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */
+#define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */
+
+#define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */
+#define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */
+
+#define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */
+#define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */
+
+#define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */
+#define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */
+
+#define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */
+#define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */
+
+#define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */
+#define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */
+
+#define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */
+#define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */
+
+#define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */
+#define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */
+
+#define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */
+#define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */
+
+#define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */
+#define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */
+
+#define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */
+#define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */
+
+#define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */
+#define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */
+
+#define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */
+#define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */
+
+#define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */
+#define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */
+
+#define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */
+#define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */
+
+#define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */
+#define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */
+
+#define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */
+#define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */
+
+#define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */
+#define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */
+
+#define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */
+#define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */
+
+#define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */
+#define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */
+
+#define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */
+#define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */
+
+#define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */
+#define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */
+
+#define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */
+#define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */
+
+#define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */
+#define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */
+
+#define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */
+#define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */
+
+#define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */
+#define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */
+
+#define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */
+#define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */
+
+#define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */
+#define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */
+
+#define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */
+#define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */
+
+#define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */
+#define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */
+
+#define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */
+#define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */
+
+#define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */
+#define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */
+
+#define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */
+#define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */
+
+#define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */
+#define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */
+
+#define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */
+#define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */
+
+#define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */
+#define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */
+
+#define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */
+#define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */
+
+#define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */
+#define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */
+
+#define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */
+#define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */
+
+#define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */
+#define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */
+
+#define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */
+#define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */
+
+#define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */
+#define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */
+
+#define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */
+#define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */
+
+#define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */
+#define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */
+
+#define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */
+#define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */
+
+#define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */
+#define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */
+
+#define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */
+#define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */
+
+#define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */
+#define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */
+
+#define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */
+#define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */
+
+/**@}*/ /* EPWM_CONST */
+/**@}*/ /* end of EPWM register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __EPWM_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/fmc_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/fmc_reg.h
new file mode 100644
index 00000000000..af50c0bfb39
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/fmc_reg.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file fmc_reg.h
+ * @version V1.00
+ * @brief FMC register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __FMC_REG_H__
+#define __FMC_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup FMC Flash Memory Controller(FMC)
+ Memory Mapped Structure for FMC Controller
+@{ */
+
+typedef struct
+{
+ /**
+ * @var FMC_T::ISPCTL
+ * Offset: 0x00 ISP Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPEN |ISP Enable Bit (Write Protect)
+ * | | |ISP function enable bit. Set this bit to enable ISP function.
+ * | | |0 = ISP function Disabled.
+ * | | |1 = ISP function Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |BS |Boot Select (Write Protect)
+ * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively
+ * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from
+ * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
+ * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
+ * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |SPUEN |SPROM Update Enable Bit (Write Protect)
+ * | | |0 = SPROM cannot be updated.
+ * | | |1 = SPROM can be updated.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |APUEN |APROM Update Enable Bit (Write Protect)
+ * | | |0 = APROM cannot be updated when the chip runs in APROM.
+ * | | |1 = APROM can be updated when the chip runs in APROM.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
+ * | | |0 = CONFIG cannot be updated.
+ * | | |1 = CONFIG can be updated.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
+ * | | |LDROM update enable bit.
+ * | | |0 = LDROM cannot be updated.
+ * | | |1 = LDROM can be updated.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |ISPFF |ISP Fail Flag (Write Protect)
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |This bit needs to be cleared by writing 1 to it.
+ * | | |(1) APROM writes to itself if APUEN is set to 0.
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * | | |(5) SPROM is programmed at SPROM secured mode.
+ * | | |(6) Page Erase command at LOCK mode with ICE connection
+ * | | |(7) Erase or Program command at brown-out detected
+ * | | |(8) Destination address is illegal, such as over an available range.
+ * | | |(9) Invalid ISP commands
+ * | | |(10) Vector address is mapping to SPROM region
+ * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1
+ * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1
+ * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1
+ * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
+ * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1
+ * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A
+ * | | |(17) Read any content of boot loader with ICE connection
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[16] |BL |Boot Loader Booting (Write Protect)
+ * | | |This bit is initiated with the inversed value of MBS (CONFIG0[5])
+ * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded
+ * | | |This bit is used to check chip boot from Boot Loader or not
+ * | | |User should keep original value of this bit when updating FMC_ISPCTL register.
+ * | | |0 = Booting from APROM or LDROM.
+ * | | |1 = Booting from Boot Loader.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var FMC_T::ISPADDR
+ * Offset: 0x04 ISP Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPADDR |ISP Address
+ * | | |The NuMicro M480 series is equipped with embedded flash
+ * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation
+ * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
+ * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation.
+ * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)
+ * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).
+ * @var FMC_T::ISPDAT
+ * Offset: 0x08 ISP Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT |ISP Data
+ * | | |Write data to this register before ISP program operation.
+ * | | |Read data from this register after ISP read operation.
+ * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff
+ * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment
+ * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result
+ * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect
+ * @var FMC_T::ISPCMD
+ * Offset: 0x0C ISP Command Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |CMD |ISP Command
+ * | | |ISP command table is shown below:
+ * | | |0x00= FLASH Read.
+ * | | |0x04= Read Unique ID.
+ * | | |0x08= Read Flash All-One Result.
+ * | | |0x0B= Read Company ID.
+ * | | |0x0C= Read Device ID.
+ * | | |0x0D= Read Checksum.
+ * | | |0x21= FLASH 32-bit Program.
+ * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.
+ * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.
+ * | | |0x25= FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1..
+ * | | |0x27= FLASH Multi-Word Program.
+ * | | |0x28= Run Flash All-One Verification.
+ * | | |0x2D= Run Checksum Calculation.
+ * | | |0x2E= Vector Remap.
+ * | | |0x40= FLASH 64-bit Read.
+ * | | |0x61= FLASH 64-bit Program.
+ * | | |The other commands are invalid.
+ * @var FMC_T::ISPTRG
+ * Offset: 0x10 ISP Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPGO |ISP Start Trigger (Write Protect)
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+ * | | |0 = ISP operation is finished.
+ * | | |1 = ISP is progressed.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var FMC_T::DFBA
+ * Offset: 0x14 Data Flash Base Address
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DFBA |Data Flash Base Address
+ * | | |This register indicates Data Flash start address. It is a read only register.
+ * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
+ * | | |This register is valid when DFEN (CONFIG0[0]) =0 .
+ * @var FMC_T::ISPSTS
+ * Offset: 0x40 ISP Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPBUSY |ISP Busy Flag (Read Only)
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+ * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+ * | | |0 = ISP operation is finished.
+ * | | |1 = ISP is progressed.
+ * |[2:1] |CBS |Boot Selection of CONFIG (Read Only)
+ * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
+ * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
+ * | | |00 = LDROM with IAP mode.
+ * | | |01 = LDROM without IAP mode.
+ * | | |10 = APROM with IAP mode.
+ * | | |11 = APROM without IAP mode.
+ * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
+ * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
+ * | | |0 = Booting from Boot Loader.
+ * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting)
+ * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only)
+ * | | |This bit is set if flash access cycle auto-tuning function is disabled
+ * | | |The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
+ * | | |0 = Flash access cycle auto-tuning is enabled.
+ * | | |1 = Flash access cycle auto-tuning is disabled.
+ * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)
+ * | | |This bit is set if data is mismatched at ISP programming verification
+ * | | |This bit is clear by performing ISP flash erase or ISP read CID operation
+ * | | |0 = Flash Program is success.
+ * | | |1 = Flash Program is fail. Program data is different with data in the flash memory
+ * |[6] |ISPFF |ISP Fail Flag (Write Protect)
+ * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |(1) APROM writes to itself if APUEN is set to 0.
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * | | |(5) SPROM is programmed at SPROM secured mode.
+ * | | |(6) Page Erase command at LOCK mode with ICE connection
+ * | | |(7) Erase or Program command at brown-out detected
+ * | | |(8) Destination address is illegal, such as over an available range.
+ * | | |(9) Invalid ISP commands
+ * | | |(10) Vector address is mapping to SPROM region.
+ * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1
+ * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1
+ * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1
+ * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
+ * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
+ * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A
+ * | | |(17) Read any content of boot loader with ICE connection
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |ALLONE |Flash All-one Verification Flag
+ * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1
+ * | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete.
+ * | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete.
+ * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
+ * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF}
+ * |[31] |SCODE |Security Code Active Flag
+ * | | |This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation.
+ * | | |0 = Secured code is inactive.
+ * | | |1 = Secured code is active.
+ * @var FMC_T::CYCCTL
+ * Offset: 0x4C Flash Access Cycle Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)
+ * | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;.
+ * | | |The HCLK working frequency range range is<27MHz
+ * | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;.
+ * | | | The optimized HCLK working frequency range is 27~54 MHz
+ * | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;.
+ * | | |The optimized HCLK working frequency range is 54~81MHz
+ * | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;.
+ * | | | The optimized HCLK working frequency range is81~108MHz
+ * | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;.
+ * | | |The optimized HCLK working frequency range is 108~135MHz
+ * | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;.
+ * | | | The optimized HCLK working frequency range is 135~162MHz
+ * | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;.
+ * | | | The optimized HCLK working frequency range is 162~192MHz
+ * | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;.
+ * | | |The optimized HCLK working frequency range is >192MHz
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var FMC_T::KPKEY0
+ * Offset: 0x50 KPROM KEY0 Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only)
+ * | | |Write KPKEY0 data to this register before KEY Comparison operation.
+ * @var FMC_T::KPKEY1
+ * Offset: 0x54 KPROM KEY1 Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only)
+ * | | |Write KPKEY1 data to this register before KEY Comparison operation.
+ * @var FMC_T::KPKEY2
+ * Offset: 0x58 KPROM KEY2 Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only)
+ * | | |Write KPKEY2 data to this register before KEY Comparison operation.
+ * @var FMC_T::KPKEYTRG
+ * Offset: 0x5C KPROM KEY Comparison Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection)
+ * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished
+ * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0.
+ * | | |0 = KEY comparison operation is finished.
+ * | | |1 = KEY comparison is progressed.
+ * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
+ * |[1] |TCEN |Timeout Counting Enable (Write Protection)
+ * | | |0 = Timeout counting is disabled.
+ * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish.
+ * | | |10 minutes is at least for timeout, and average is about 20 minutes.
+ * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
+ * @var FMC_T::KPKEYSTS
+ * Offset: 0x60 KPROM KEY Comparison Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |KEYBUSY |KEY Comparison Busy (Read Only)
+ * | | |0 = KEY comparison is finished.
+ * | | |1 = KEY comparison is busy.
+ * |[1] |KEYLOCK |KEY LOCK Flag
+ * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection
+ * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0
+ * | | |This bit also can be set to 1 while
+ * | | | - CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
+ * | | | - KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or
+ * | | | - KEYENROM is programmed a non-0xFF value or
+ * | | | - Timeout event or
+ * | | | - FORBID(FMC_KPKEYSTS[3]) is 1
+ * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection.
+ * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection.
+ * | | |SPROM write protect is depended on SPFLAG.
+ * | | |CONFIG write protect is depended on CFGFLAG
+ * |[2] |KEYMATCH |KEY Match Flag (Read Only)
+ * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched
+ * | | |This bit is also cleared to 0 while
+ * | | | - CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
+ * | | | - Timeout event or
+ * | | | - KPROM is erased or
+ * | | | - KEYENROM is programmed to a non-0xFF value.
+ * | | | - Chip is in power down mode.
+ * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting.
+ * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting.
+ * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only)
+ * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]).
+ * | | |0 = KEY comparison is not forbidden.
+ * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger.
+ * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only)
+ * | | |This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset
+ * | | |This bit is cleared to 0 by hardware while KPROM is erased
+ * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value.
+ * | | |0 = Security Key protection is disabled.
+ * | | |1 = Security Key protection is enabled.
+ * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only)
+ * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset
+ * | | |This bit is cleared to 0 by hardware while KPROM is erased
+ * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0.
+ * | | |0 = CONFIG write-protection is disabled.
+ * | | |1 = CONFIG write-protection is enabled.
+ * |[6] |SPFLAG |SPROM Write-protection Enabled Flag (Read Only)
+ * | | |This bit is set while the KEYENROM [1] is 0 at power-on or reset
+ * | | |This bit is cleared to 0 by hardware while KPROM is erased
+ * | | |This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0.
+ * | | |0 = SPROM write-protection is disabled.
+ * | | |1 = SPROM write-protection is enabled.
+ * @var FMC_T::KPKEYCNT
+ * Offset: 0x64 KPROM KEY-Unmatched Counting Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only)
+ * | | |KPKECNT is increased when entry keys is wrong in Security Key protection
+ * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on.
+ * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only)
+ * | | |KPKEMAX is the maximum error key entry number at each power-on
+ * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated
+ * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting
+ * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX.
+ * @var FMC_T::KPCNT
+ * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only)
+ * | | |KPCNT is the power-on counting for error key entry in Security Key protection
+ * | | |KPCNT is cleared to 0 if key comparison is matched.
+ * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only)
+ * | | |KPMAX is the power-on maximum number for error key entry
+ * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated
+ * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting
+ * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX
+ * @var FMC_T::MPDAT0
+ * Offset: 0x80 ISP Data0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT0 |ISP Data 0
+ * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
+ * @var FMC_T::MPDAT1
+ * Offset: 0x84 ISP Data1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT1 |ISP Data 1
+ * | | |This register is the second 32-bit data for 64-bit/multi-word programming.
+ * @var FMC_T::MPDAT2
+ * Offset: 0x88 ISP Data2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT2 |ISP Data 2
+ * | | |This register is the third 32-bit data for multi-word programming.
+ * @var FMC_T::MPDAT3
+ * Offset: 0x8C ISP Data3 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT3 |ISP Data 3
+ * | | |This register is the fourth 32-bit data for multi-word programming.
+ * @var FMC_T::MPSTS
+ * Offset: 0xC0 ISP Multi-Program Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)
+ * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
+ * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+ * | | |0 = ISP Multi-Word program operation is finished.
+ * | | |1 = ISP Multi-Word program operation is progressed.
+ * |[1] |PPGO |ISP Multi-program Status (Read Only)
+ * | | |0 = ISP multi-word program operation is not active.
+ * | | |1 = ISP multi-word program operation is in progress.
+ * |[2] |ISPFF |ISP Fail Flag (Read Only)
+ * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |(1) APROM writes to itself if APUEN is set to 0.
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * | | |(5) SPROM is programmed at SPROM secured mode.
+ * | | |(6) Page Erase command at LOCK mode with ICE connection
+ * | | |(7) Erase or Program command at brown-out detected
+ * | | |(8) Destination address is illegal, such as over an available range.
+ * | | |(9) Invalid ISP commands
+ * | | |(10) Vector address is mapping to SPROM region.
+ * |[4] |D0 |ISP DATA 0 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
+ * |[5] |D1 |ISP DATA 1 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
+ * |[6] |D2 |ISP DATA 2 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
+ * |[7] |D3 |ISP DATA 3 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
+ * @var FMC_T::MPADDR
+ * Offset: 0xC4 ISP Multi-Program Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |MPADDR |ISP Multi-word Program Address
+ * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
+ * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
+ */
+ __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
+ __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
+ __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
+ __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */
+ __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
+ __I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[10];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */
+ __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */
+ __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */
+ __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */
+ __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */
+ __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */
+ __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */
+ __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
+ __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
+ __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
+ __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[12];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */
+ __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE4[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */
+ __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */
+ __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */
+ __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */
+ __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */
+
+} FMC_T;
+
+/**
+ @addtogroup FMC_CONST FMC Bit Field Definition
+ Constant Definitions for FMC Controller
+@{ */
+
+#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
+#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
+
+#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
+#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
+
+#define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */
+#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */
+
+#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
+#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
+
+#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
+#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
+
+#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
+#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
+
+#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
+#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
+
+#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
+#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
+
+#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
+#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
+
+#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
+#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
+
+#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
+#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
+
+#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
+#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
+
+#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
+#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
+
+#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
+#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
+
+#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
+#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
+
+#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
+#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
+
+#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */
+#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */
+
+#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
+#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
+
+#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
+#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
+
+#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */
+#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */
+
+#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
+#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
+
+#define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */
+#define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */
+
+#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */
+#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */
+
+#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */
+#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */
+
+#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */
+#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */
+
+#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */
+#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */
+
+#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */
+#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */
+
+#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */
+#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */
+
+#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */
+#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */
+
+#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */
+#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */
+
+#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */
+#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */
+
+#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */
+#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */
+
+#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */
+#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */
+
+#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */
+#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */
+
+#define FMC_KPKEYSTS_SPFLAG_Pos (6) /*!< FMC_T::KPKEYSTS: SPFLAG Position */
+#define FMC_KPKEYSTS_SPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SPFLAG Mask */
+
+#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */
+#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */
+
+#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */
+#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */
+
+#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */
+#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */
+
+#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */
+#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */
+
+#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
+#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
+
+#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
+#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
+
+#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
+#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
+
+#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
+#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
+
+#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
+#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
+
+#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
+#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
+
+#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
+#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
+
+#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
+#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
+
+#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
+#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
+
+#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
+#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
+
+#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
+#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
+
+#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
+#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
+
+#define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */
+#define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */
+
+#define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */
+#define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */
+
+#define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */
+#define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */
+
+#define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */
+#define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */
+
+#define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */
+#define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */
+
+#define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */
+#define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOM20STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */
+
+#define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */
+#define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */
+
+#define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */
+#define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */
+
+#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */
+#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */
+
+#define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */
+#define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */
+
+#define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */
+#define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */
+
+#define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */
+#define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */
+
+#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */
+#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */
+
+/**@}*/ /* FMC_CONST */
+/**@}*/ /* end of FMC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __FMC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/gpio_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/gpio_reg.h
new file mode 100644
index 00000000000..9876f972845
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/gpio_reg.h
@@ -0,0 +1,936 @@
+/**************************************************************************//**
+ * @file gpio_reg.h
+ * @version V1.00
+ * @brief GPIO register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __GPIO_REG_H__
+#define __GPIO_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
+ Memory Mapped Structure for GPIO Controller
+@{ */
+
+
+typedef struct
+{
+
+ /**
+ * @var GPIO_T::MODE
+ * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control
+ * | | |Determine each I/O mode of Px.n pins.
+ * | | |00 = Px.n is in Input mode.
+ * | | |01 = Px.n is in Push-pull Output mode.
+ * | | |10 = Px.n is in Open-drain Output mode.
+ * | | |11 = Px.n is in Quasi-bidirectional mode.
+ * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
+ * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
+ * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
+ * | | |Note2:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::DINOFF
+ * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control
+ * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
+ * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
+ * | | |0 = Px.n digital input path Enabled.
+ * | | |1 = Px.n digital input path Disabled (digital input tied to low).
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::DOUT
+ * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |DOUTn |Port A-H Pin[n] Output Value
+ * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+ * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+ * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::DATMSK
+ * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask
+ * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
+ * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
+ * | | |If the write signal is masked, writing data to the protect bit is ignored.
+ * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
+ * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
+ * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[n]) bit.
+ * | | |Note2:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::PIN
+ * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |PINn |Port A-H Pin[n] Pin Value
+ * | | |Each bit of the register reflects the actual status of the respective Px.n pin.
+ * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::DBEN
+ * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |DBENn |Port A-H Pin[n] Input Signal De-Bounce Enable Bit
+ * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
+ * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
+ * | | |0 = Px.n de-bounce function Disabled.
+ * | | |1 = Px.n de-bounce function Enabled.
+ * | | |The de-bounce function is valid only for edge triggered interrupt.
+ * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::INTTYPE
+ * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
+ * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
+ * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
+ * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
+ * | | |0 = Edge trigger interrupt.
+ * | | |1 = Level trigger interrupt.
+ * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
+ * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid only for edge triggered interrupt.
+ * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::INTEN
+ * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
+ * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
+ * | | |Set bit to 1 also enable the pin wake-up function.
+ * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
+ * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
+ * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
+ * | | |0 = Px.n level low or high to low interrupt Disabled.
+ * | | |1 = Px.n level low or high to low interrupt Enabled.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
+ * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
+ * | | |Set bit to 1 also enable the pin wake-up function.
+ * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
+ * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
+ * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
+ * | | |0 = Px.n level high or low to high interrupt Disabled.
+ * | | |1 = Px.n level high or low to high interrupt Enabled.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::INTSRC
+ * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag
+ * | | |Write Operation :
+ * | | |0 = No action.
+ * | | |1 = Clear the corresponding pending interrupt.
+ * | | |Read Operation :
+ * | | |0 = No interrupt at Px.n.
+ * | | |1 = Px.n generates an interrupt.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::SMTEN
+ * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit
+ * | | |0 = Px.n input Schmitt trigger function Disabled.
+ * | | |1 = Px.n input Schmitt trigger function Enabled.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::SLEWCTL
+ * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control
+ * | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V).
+ * | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V).
+ * | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V.
+ * | | |11 = Reserved.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::PUSEL
+ * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Selection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register
+ * | | |Determine each I/O Pull-up/pull-down of Px.n pins.
+ * | | |00 = Px.n pull-up and pull-up disable.
+ * | | |01 = Px.n pull-up enable.
+ * | | |10 = Px.n pull-down enable.
+ * | | |11 = Reserved.
+ * | | |Note1:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation
+ * | | |The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
+ * | | |The independent pull-down control register only valid when MODEn set as tri-state mode
+ * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode
+ * | | |Note2:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ */
+
+ __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control */
+ __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control */
+ __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value */
+ __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask */
+ __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value */
+ __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register */
+ __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control */
+ __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register */
+ __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag */
+ __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register */
+ __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t PUSEL; /* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Enable Register */
+
+} GPIO_T;
+
+typedef struct
+{
+
+ /**
+ * @var GPIO_DBCTL_T::DBCTL
+ * Offset: 0x440 Interrupt De-bounce Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection
+ * | | |0000 = Sample interrupt input once per 1 clocks.
+ * | | |0001 = Sample interrupt input once per 2 clocks.
+ * | | |0010 = Sample interrupt input once per 4 clocks.
+ * | | |0011 = Sample interrupt input once per 8 clocks.
+ * | | |0100 = Sample interrupt input once per 16 clocks.
+ * | | |0101 = Sample interrupt input once per 32 clocks.
+ * | | |0110 = Sample interrupt input once per 64 clocks.
+ * | | |0111 = Sample interrupt input once per 128 clocks.
+ * | | |1000 = Sample interrupt input once per 256 clocks.
+ * | | |1001 = Sample interrupt input once per 2*256 clocks.
+ * | | |1010 = Sample interrupt input once per 4*256 clocks.
+ * | | |1011 = Sample interrupt input once per 8*256 clocks.
+ * | | |1100 = Sample interrupt input once per 16*256 clocks.
+ * | | |1101 = Sample interrupt input once per 32*256 clocks.
+ * | | |1110 = Sample interrupt input once per 64*256 clocks.
+ * | | |1111 = Sample interrupt input once per 128*256 clocks.
+ * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
+ * | | |0 = De-bounce counter clock source is the HCLK.
+ * | | |1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
+ * |[5] |ICLKON |Interrupt Clock On Mode
+ * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
+ * | | |1 = All I/O pins edge detection circuit is always active after reset.
+ * | | |Note: It is recommended to disable this bit to save system power if no special application concern.
+ */
+
+ __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */
+
+} GPIO_DBCTL_T;
+
+/**
+ @addtogroup GPIO_CONST GPIO Bit Field Definition
+ Constant Definitions for GPIO Controller
+@{ */
+
+#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
+#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
+
+#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
+#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
+
+#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
+#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
+
+#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
+#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
+
+#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
+#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
+
+#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
+#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
+
+#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
+#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
+
+#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
+#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
+
+#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
+#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
+
+#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
+#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
+
+#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
+#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
+
+#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
+#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
+
+#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
+#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
+
+#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
+#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
+
+#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
+#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
+
+#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
+#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
+
+#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
+#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
+
+#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
+#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
+
+#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
+#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
+
+#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
+#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
+
+#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
+#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
+
+#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
+#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
+
+#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
+#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
+
+#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
+#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
+
+#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
+#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
+
+#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
+#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
+
+#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
+#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
+
+#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
+#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
+
+#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
+#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
+
+#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
+#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
+
+#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
+#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
+
+#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
+#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
+
+#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
+#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
+
+#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
+#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
+
+#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
+#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
+
+#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
+#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
+
+#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
+#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
+
+#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
+#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
+
+#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
+#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
+
+#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
+#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
+
+#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
+#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
+
+#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
+#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
+
+#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
+#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
+
+#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
+#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
+
+#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
+#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
+
+#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
+#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
+
+#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
+#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
+
+#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
+#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
+
+#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */
+#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */
+
+#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */
+#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */
+
+#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */
+#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */
+
+#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */
+#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */
+
+#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */
+#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */
+
+#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */
+#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */
+
+#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */
+#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */
+
+#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */
+#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */
+
+#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */
+#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */
+
+#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */
+#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */
+
+#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */
+#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */
+
+#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */
+#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */
+
+#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */
+#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */
+
+#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */
+#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */
+
+#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */
+#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */
+
+#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */
+#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */
+
+#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
+#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
+
+#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
+#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
+
+#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
+#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
+
+#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
+#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
+
+#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
+#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
+
+#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
+#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
+
+#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
+#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
+
+#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
+#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
+
+#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
+#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
+
+#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
+#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
+
+#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
+#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
+
+#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
+#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
+
+#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
+#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
+
+#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
+#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
+
+#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
+#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
+
+#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
+#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
+
+#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
+#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
+
+#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
+#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
+
+#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
+#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
+
+#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
+#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
+
+#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
+#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
+
+#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
+#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
+
+#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
+#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
+
+#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
+#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
+
+#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
+#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
+
+#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
+#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
+
+#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
+#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
+
+#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
+#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
+
+#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
+#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
+
+#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
+#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
+
+#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
+#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
+
+#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
+#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
+
+#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
+#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
+
+#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
+#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
+
+#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
+#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
+
+#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
+#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
+
+#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
+#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
+
+#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
+#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
+
+#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
+#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
+
+#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
+#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
+
+#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
+#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
+
+#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
+#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
+
+#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
+#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
+
+#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
+#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
+
+#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
+#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
+
+#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
+#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
+
+#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
+#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
+
+#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
+#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
+
+#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
+#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
+
+#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
+#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
+
+#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
+#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
+
+#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
+#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
+
+#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
+#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
+
+#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
+#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
+
+#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
+#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
+
+#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
+#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
+
+#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
+#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
+
+#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
+#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
+
+#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
+#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
+
+#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
+#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
+
+#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
+#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
+
+#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
+#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
+
+#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
+#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
+
+#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
+#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
+
+#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
+#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
+
+#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
+#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
+
+#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
+#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
+
+#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
+#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
+
+#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
+#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
+
+#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
+#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
+
+#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
+#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
+
+#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
+#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
+
+#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
+#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
+
+#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
+#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
+
+#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
+#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
+
+#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
+#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
+
+#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
+#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
+
+#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
+#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
+
+#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
+#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
+
+#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
+#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
+
+#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
+#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
+
+#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
+#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
+
+#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
+#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
+
+#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
+#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
+
+#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
+#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
+
+#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
+#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
+
+#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
+#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
+
+#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
+#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
+
+#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
+#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
+
+#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
+#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
+
+#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
+#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
+
+#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
+#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
+
+#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
+#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
+
+#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
+#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
+
+#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
+#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
+
+#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
+#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
+
+#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
+#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
+
+#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
+#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
+
+#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
+#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
+
+#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
+#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
+
+#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
+#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
+
+#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
+#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
+
+#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
+#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
+
+#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
+#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
+
+#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
+#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
+
+#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
+#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
+
+#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
+#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
+
+#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
+#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
+
+#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
+#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
+
+#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
+#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
+
+#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
+#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
+
+#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
+#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
+
+#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
+#define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
+
+#define GPIO_SLEWCTL_HSREN1_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
+#define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
+
+#define GPIO_SLEWCTL_HSREN2_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
+#define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
+
+#define GPIO_SLEWCTL_HSREN3_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
+#define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
+
+#define GPIO_SLEWCTL_HSREN4_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
+#define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
+
+#define GPIO_SLEWCTL_HSREN5_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
+#define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
+
+#define GPIO_SLEWCTL_HSREN6_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
+#define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
+
+#define GPIO_SLEWCTL_HSREN7_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
+#define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
+
+#define GPIO_SLEWCTL_HSREN8_Pos (16) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
+#define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
+
+#define GPIO_SLEWCTL_HSREN9_Pos (18) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
+#define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
+
+#define GPIO_SLEWCTL_HSREN10_Pos (20) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
+#define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
+
+#define GPIO_SLEWCTL_HSREN11_Pos (22) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
+#define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
+
+#define GPIO_SLEWCTL_HSREN12_Pos (24) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
+#define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
+
+#define GPIO_SLEWCTL_HSREN13_Pos (26) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
+#define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
+
+#define GPIO_SLEWCTL_HSREN14_Pos (28) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
+#define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
+
+#define GPIO_SLEWCTL_HSREN15_Pos (30) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
+#define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
+
+#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */
+#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */
+
+#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */
+#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */
+
+#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */
+#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */
+
+#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */
+#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */
+
+#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */
+#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */
+
+#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */
+#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */
+
+#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */
+#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */
+
+#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */
+#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */
+
+#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */
+#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */
+
+#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */
+#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */
+
+#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */
+#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */
+
+#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */
+#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */
+
+#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */
+#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */
+
+#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */
+#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */
+
+#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */
+#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */
+
+#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */
+#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */
+
+#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
+#define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
+
+#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
+#define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
+
+#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */
+#define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */
+
+/**@}*/ /* GPIO_CONST */
+/**@}*/ /* end of GPIO register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __GPIO_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsotg_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsotg_reg.h
new file mode 100644
index 00000000000..52c6a434155
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsotg_reg.h
@@ -0,0 +1,398 @@
+/**************************************************************************//**
+ * @file hsotg_reg.h
+ * @version V1.00
+ * @brief HSOTG register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __HSOTG_REG_H__
+#define __HSOTG_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup HSOTG High Speed USB On-The-Go Controller(HSOTG)
+ Memory Mapped Structure for HSOTG Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var HSOTG_T::CTL
+ * Offset: 0x00 HSOTG Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |VBUSDROP |Drop VBUS Control
+ * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
+ * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
+ * | | |0 = Not drop the VBUS.
+ * | | |1 = Drop the VBUS.
+ * |[1] |BUSREQ |OTG Bus Request
+ * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
+ * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power
+ * | | |This bit will be cleared when A-device goes to A_wait_vfall state
+ * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
+ * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
+ * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification)
+ * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
+ * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
+ * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
+ * |[2] |HNPREQEN |OTG HNP Request Enable Bit
+ * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
+ * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
+ * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
+ * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
+ * | | |0 = HNP request Disabled.
+ * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
+ * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
+ * |[4] |OTGEN |OTG Function Enable Bit
+ * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device
+ * | | |When USB frame not configured as OTG device, this bit is must be low.
+ * | | |0= OTG function Disabled.
+ * | | |1 = OTG function Enabled.
+ * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit
+ * | | |0 = OTG ID pin status change wake-up function Disabled.
+ * | | |1 = OTG ID pin status change wake-up function Enabled.
+ * @var HSOTG_T::PHYCTL
+ * Offset: 0x04 HSOTG PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |OTGPHYEN |OTG PHY Enable
+ * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
+ * | | |If device is not configured as OTG-device nor ID-dependent, this bit is "don't care".
+ * | | |0 = OTG PHY Disabled.
+ * | | |1 = OTG PHY Enabled.
+ * |[1] |IDDETEN |ID Detection Enable Bit
+ * | | |0 = Detect ID pin status Disabled.
+ * | | |1 = Detect ID pin status Enabled.
+ * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity
+ * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
+ * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
+ * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
+ * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+ * | | |0 = The off-chip USB VBUS power switch enable is active high.
+ * | | |1 = The off-chip USB VBUS power switch enable is active low.
+ * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity
+ * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
+ * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
+ * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+ * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
+ * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
+ * @var HSOTG_T::INTEN
+ * Offset: 0x08 HSOTG Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
+ * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: Going to idle state means going to a_idle or b_idle state
+ * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
+ * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
+ * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
+ * | | |0 = This device as a peripheral interrupt Disabled.
+ * | | |1 = This device as a peripheral interrupt Enabled.
+ * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
+ * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
+ * | | |0 = This device as a host interrupt Disabled.
+ * | | |1 = This device as a host interrupt Enabled.
+ * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * @var HSOTG_T::INTSTS
+ * Offset: 0x0C HSOTG Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ROLECHGIF |OTG Role Change Interrupt Status
+ * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
+ * | | |0 = OTG device role not changed.
+ * | | |1 = OTG device role changed.
+ * | | |Note: Write 1 to clear this flag.
+ * |[1] |VBEIF |VBUS Error Interrupt Status
+ * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
+ * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
+ * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
+ * | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
+ * |[2] |SRPFIF |SRP Fail Interrupt Status
+ * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
+ * | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
+ * | | |0 = OTG B-device gets VBUS high before this interval.
+ * | | |1 = OTG B-device does not get VBUS high before this interval.
+ * | | |Note: Write 1 to clear this flag.
+ * |[3] |HNPFIF |HNP Fail Interrupt Status
+ * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
+ * | | |0 = A-device connects to B-device before specified interval expires.
+ * | | |1 = A-device does not connect to B-device before specified interval expires.
+ * | | |Note: Write 1 to clear this flag.
+ * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
+ * | | |Flag is set if the OTG device transfers from non-idle state to idle state
+ * | | |The OTG device will be neither a host nor a peripheral.
+ * | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
+ * | | |1 = OTG device goes back to idle state(a_idle or b_idle).
+ * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
+ * | | |Note 2: Write 1 to clear this flag.
+ * |[5] |IDCHGIF |ID State Change Interrupt Status
+ * | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
+ * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
+ * | | |Note: Write 1 to clear this flag.
+ * |[6] |PDEVIF |Act As Peripheral Interrupt Status
+ * | | |0= This device does not act as a peripheral.
+ * | | |1 = This device acts as a peripheral.
+ * | | |Note: Write 1 to clear this flag.
+ * |[7] |HOSTIF |Act As Host Interrupt Status
+ * | | |0= This device does not act as a host.
+ * | | |1 = This device acts as a host.
+ * | | |Note: Write 1 to clear this flag.
+ * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
+ * | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
+ * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
+ * | | |Note: Write 1 to clear this status.
+ * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
+ * | | |0 = AVLD (OTG_STATUS[4]) not toggled.
+ * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
+ * | | |Note: Write 1 to clear this status.
+ * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
+ * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
+ * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
+ * | | |Note: Write 1 to clear this status.
+ * |[11] |SECHGIF |SESSEND State Change Interrupt Status
+ * | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
+ * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
+ * | | |Note: Write 1 to clear this flag.
+ * |[13] |SRPDETIF |SRP Detected Interrupt Status
+ * | | |0 = SRP not detected.
+ * | | |1 = SRP detected.
+ * | | |Note: Write 1 to clear this status.
+ * @var HSOTG_T::STATUS
+ * Offset: 0x10 HSOTG Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |OVERCUR |over Current Condition
+ * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
+ * | | |0 = OTG A-device drives VBUS successfully.
+ * | | |1 = OTG A-device cannot drives VBUS high in this interval.
+ * |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug
+ * | | |0 = Mini-A/Micro-A plug is attached.
+ * | | |1 = Mini-B/Micro-B plug is attached.
+ * |[2] |SESSEND |Session End Status
+ * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1
+ * | | |Session end means no meaningful power on VBUS.
+ * | | |0 = Session is not end.
+ * | | |1 = Session is end.
+ * |[3] |BVLD |B-device Session Valid Status
+ * | | |0 = B-device session is not valid.
+ * | | |1 = B-device session is valid.
+ * |[4] |AVLD |A-device Session Valid Status
+ * | | |0 = A-device session is not valid.
+ * | | |1 = A-device session is valid.
+ * |[5] |VBUSVLD |VBUS Valid Status
+ * | | |When VBUS is larger than 4.7V and A-device drives VBUS , this bit will be set to 1.
+ * | | |0 = VBUS is not valid.
+ * | | |1 = VBUS is valid.
+ * |[6] |ASPERI |As Peripheral Status
+ * | | |When OTG as peripheral, this bit is set.
+ * | | |0: OTG not as peripheral
+ * | | |1: OTG as peripheral
+ * |[7] |ASHOST |As Host Status
+ * | | |When OTG as Host, this bit is set.
+ * | | |0: OTG not as Host
+ * | | |1: OTG as Host
+ */
+ __IO uint32_t CTL; /*!< [0x0000] HSOTG Control Register */
+ __IO uint32_t PHYCTL; /*!< [0x0004] HSOTG PHY Control Register */
+ __IO uint32_t INTEN; /*!< [0x0008] HSOTG Interrupt Enable Register */
+ __IO uint32_t INTSTS; /*!< [0x000c] HSOTG Interrupt Status Register */
+ __I uint32_t STATUS; /*!< [0x0010] HSOTG Status Register */
+
+} HSOTG_T;
+
+/**
+ @addtogroup HSOTG_CONST HSOTG Bit Field Definition
+ Constant Definitions for HSOTG Controller
+@{ */
+
+#define HSOTG_CTL_VBUSDROP_Pos (0) /*!< HSOTG_T::CTL: VBUSDROP Position */
+#define HSOTG_CTL_VBUSDROP_Msk (0x1ul << HSOTG_CTL_VBUSDROP_Pos) /*!< HSOTG_T::CTL: VBUSDROP Mask */
+
+#define HSOTG_CTL_BUSREQ_Pos (1) /*!< HSOTG_T::CTL: BUSREQ Position */
+#define HSOTG_CTL_BUSREQ_Msk (0x1ul << HSOTG_CTL_BUSREQ_Pos) /*!< HSOTG_T::CTL: BUSREQ Mask */
+
+#define HSOTG_CTL_HNPREQEN_Pos (2) /*!< HSOTG_T::CTL: HNPREQEN Position */
+#define HSOTG_CTL_HNPREQEN_Msk (0x1ul << HSOTG_CTL_HNPREQEN_Pos) /*!< HSOTG_T::CTL: HNPREQEN Mask */
+
+#define HSOTG_CTL_OTGEN_Pos (4) /*!< HSOTG_T::CTL: OTGEN Position */
+#define HSOTG_CTL_OTGEN_Msk (0x1ul << HSOTG_CTL_OTGEN_Pos) /*!< HSOTG_T::CTL: OTGEN Mask */
+
+#define HSOTG_CTL_WKEN_Pos (5) /*!< HSOTG_T::CTL: WKEN Position */
+#define HSOTG_CTL_WKEN_Msk (0x1ul << HSOTG_CTL_WKEN_Pos) /*!< HSOTG_T::CTL: WKEN Mask */
+
+#define HSOTG_PHYCTL_OTGPHYEN_Pos (0) /*!< HSOTG_T::PHYCTL: OTGPHYEN Position */
+#define HSOTG_PHYCTL_OTGPHYEN_Msk (0x1ul << HSOTG_PHYCTL_OTGPHYEN_Pos) /*!< HSOTG_T::PHYCTL: OTGPHYEN Mask */
+
+#define HSOTG_PHYCTL_IDDETEN_Pos (1) /*!< HSOTG_T::PHYCTL: IDDETEN Position */
+#define HSOTG_PHYCTL_IDDETEN_Msk (0x1ul << HSOTG_PHYCTL_IDDETEN_Pos) /*!< HSOTG_T::PHYCTL: IDDETEN Mask */
+
+#define HSOTG_PHYCTL_VBENPOL_Pos (4) /*!< HSOTG_T::PHYCTL: VBENPOL Position */
+#define HSOTG_PHYCTL_VBENPOL_Msk (0x1ul << HSOTG_PHYCTL_VBENPOL_Pos) /*!< HSOTG_T::PHYCTL: VBENPOL Mask */
+
+#define HSOTG_PHYCTL_VBSTSPOL_Pos (5) /*!< HSOTG_T::PHYCTL: VBSTSPOL Position */
+#define HSOTG_PHYCTL_VBSTSPOL_Msk (0x1ul << HSOTG_PHYCTL_VBSTSPOL_Pos) /*!< HSOTG_T::PHYCTL: VBSTSPOL Mask */
+
+#define HSOTG_INTEN_ROLECHGIEN_Pos (0) /*!< HSOTG_T::INTEN: ROLECHGIEN Position */
+#define HSOTG_INTEN_ROLECHGIEN_Msk (0x1ul << HSOTG_INTEN_ROLECHGIEN_Pos) /*!< HSOTG_T::INTEN: ROLECHGIEN Mask */
+
+#define HSOTG_INTEN_VBEIEN_Pos (1) /*!< HSOTG_T::INTEN: VBEIEN Position */
+#define HSOTG_INTEN_VBEIEN_Msk (0x1ul << HSOTG_INTEN_VBEIEN_Pos) /*!< HSOTG_T::INTEN: VBEIEN Mask */
+
+#define HSOTG_INTEN_SRPFIEN_Pos (2) /*!< HSOTG_T::INTEN: SRPFIEN Position */
+#define HSOTG_INTEN_SRPFIEN_Msk (0x1ul << HSOTG_INTEN_SRPFIEN_Pos) /*!< HSOTG_T::INTEN: SRPFIEN Mask */
+
+#define HSOTG_INTEN_HNPFIEN_Pos (3) /*!< HSOTG_T::INTEN: HNPFIEN Position */
+#define HSOTG_INTEN_HNPFIEN_Msk (0x1ul << HSOTG_INTEN_HNPFIEN_Pos) /*!< HSOTG_T::INTEN: HNPFIEN Mask */
+
+#define HSOTG_INTEN_GOIDLEIEN_Pos (4) /*!< HSOTG_T::INTEN: GOIDLEIEN Position */
+#define HSOTG_INTEN_GOIDLEIEN_Msk (0x1ul << HSOTG_INTEN_GOIDLEIEN_Pos) /*!< HSOTG_T::INTEN: GOIDLEIEN Mask */
+
+#define HSOTG_INTEN_IDCHGIEN_Pos (5) /*!< HSOTG_T::INTEN: IDCHGIEN Position */
+#define HSOTG_INTEN_IDCHGIEN_Msk (0x1ul << HSOTG_INTEN_IDCHGIEN_Pos) /*!< HSOTG_T::INTEN: IDCHGIEN Mask */
+
+#define HSOTG_INTEN_PDEVIEN_Pos (6) /*!< HSOTG_T::INTEN: PDEVIEN Position */
+#define HSOTG_INTEN_PDEVIEN_Msk (0x1ul << HSOTG_INTEN_PDEVIEN_Pos) /*!< HSOTG_T::INTEN: PDEVIEN Mask */
+
+#define HSOTG_INTEN_HOSTIEN_Pos (7) /*!< HSOTG_T::INTEN: HOSTIEN Position */
+#define HSOTG_INTEN_HOSTIEN_Msk (0x1ul << HSOTG_INTEN_HOSTIEN_Pos) /*!< HSOTG_T::INTEN: HOSTIEN Mask */
+
+#define HSOTG_INTEN_BVLDCHGIEN_Pos (8) /*!< HSOTG_T::INTEN: BVLDCHGIEN Position */
+#define HSOTG_INTEN_BVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_BVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: BVLDCHGIEN Mask */
+
+#define HSOTG_INTEN_AVLDCHGIEN_Pos (9) /*!< HSOTG_T::INTEN: AVLDCHGIEN Position */
+#define HSOTG_INTEN_AVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_AVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: AVLDCHGIEN Mask */
+
+#define HSOTG_INTEN_VBCHGIEN_Pos (10) /*!< HSOTG_T::INTEN: VBCHGIEN Position */
+#define HSOTG_INTEN_VBCHGIEN_Msk (0x1ul << HSOTG_INTEN_VBCHGIEN_Pos) /*!< HSOTG_T::INTEN: VBCHGIEN Mask */
+
+#define HSOTG_INTEN_SECHGIEN_Pos (11) /*!< HSOTG_T::INTEN: SECHGIEN Position */
+#define HSOTG_INTEN_SECHGIEN_Msk (0x1ul << HSOTG_INTEN_SECHGIEN_Pos) /*!< HSOTG_T::INTEN: SECHGIEN Mask */
+
+#define HSOTG_INTEN_SRPDETIEN_Pos (13) /*!< HSOTG_T::INTEN: SRPDETIEN Position */
+#define HSOTG_INTEN_SRPDETIEN_Msk (0x1ul << HSOTG_INTEN_SRPDETIEN_Pos) /*!< HSOTG_T::INTEN: SRPDETIEN Mask */
+
+#define HSOTG_INTSTS_ROLECHGIF_Pos (0) /*!< HSOTG_T::INTSTS: ROLECHGIF Position */
+#define HSOTG_INTSTS_ROLECHGIF_Msk (0x1ul << HSOTG_INTSTS_ROLECHGIF_Pos) /*!< HSOTG_T::INTSTS: ROLECHGIF Mask */
+
+#define HSOTG_INTSTS_VBEIF_Pos (1) /*!< HSOTG_T::INTSTS: VBEIF Position */
+#define HSOTG_INTSTS_VBEIF_Msk (0x1ul << HSOTG_INTSTS_VBEIF_Pos) /*!< HSOTG_T::INTSTS: VBEIF Mask */
+
+#define HSOTG_INTSTS_SRPFIF_Pos (2) /*!< HSOTG_T::INTSTS: SRPFIF Position */
+#define HSOTG_INTSTS_SRPFIF_Msk (0x1ul << HSOTG_INTSTS_SRPFIF_Pos) /*!< HSOTG_T::INTSTS: SRPFIF Mask */
+
+#define HSOTG_INTSTS_HNPFIF_Pos (3) /*!< HSOTG_T::INTSTS: HNPFIF Position */
+#define HSOTG_INTSTS_HNPFIF_Msk (0x1ul << HSOTG_INTSTS_HNPFIF_Pos) /*!< HSOTG_T::INTSTS: HNPFIF Mask */
+
+#define HSOTG_INTSTS_GOIDLEIF_Pos (4) /*!< HSOTG_T::INTSTS: GOIDLEIF Position */
+#define HSOTG_INTSTS_GOIDLEIF_Msk (0x1ul << HSOTG_INTSTS_GOIDLEIF_Pos) /*!< HSOTG_T::INTSTS: GOIDLEIF Mask */
+
+#define HSOTG_INTSTS_IDCHGIF_Pos (5) /*!< HSOTG_T::INTSTS: IDCHGIF Position */
+#define HSOTG_INTSTS_IDCHGIF_Msk (0x1ul << HSOTG_INTSTS_IDCHGIF_Pos) /*!< HSOTG_T::INTSTS: IDCHGIF Mask */
+
+#define HSOTG_INTSTS_PDEVIF_Pos (6) /*!< HSOTG_T::INTSTS: PDEVIF Position */
+#define HSOTG_INTSTS_PDEVIF_Msk (0x1ul << HSOTG_INTSTS_PDEVIF_Pos) /*!< HSOTG_T::INTSTS: PDEVIF Mask */
+
+#define HSOTG_INTSTS_HOSTIF_Pos (7) /*!< HSOTG_T::INTSTS: HOSTIF Position */
+#define HSOTG_INTSTS_HOSTIF_Msk (0x1ul << HSOTG_INTSTS_HOSTIF_Pos) /*!< HSOTG_T::INTSTS: HOSTIF Mask */
+
+#define HSOTG_INTSTS_BVLDCHGIF_Pos (8) /*!< HSOTG_T::INTSTS: BVLDCHGIF Position */
+#define HSOTG_INTSTS_BVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_BVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: BVLDCHGIF Mask */
+
+#define HSOTG_INTSTS_AVLDCHGIF_Pos (9) /*!< HSOTG_T::INTSTS: AVLDCHGIF Position */
+#define HSOTG_INTSTS_AVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_AVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: AVLDCHGIF Mask */
+
+#define HSOTG_INTSTS_VBCHGIF_Pos (10) /*!< HSOTG_T::INTSTS: VBCHGIF Position */
+#define HSOTG_INTSTS_VBCHGIF_Msk (0x1ul << HSOTG_INTSTS_VBCHGIF_Pos) /*!< HSOTG_T::INTSTS: VBCHGIF Mask */
+
+#define HSOTG_INTSTS_SECHGIF_Pos (11) /*!< HSOTG_T::INTSTS: SECHGIF Position */
+#define HSOTG_INTSTS_SECHGIF_Msk (0x1ul << HSOTG_INTSTS_SECHGIF_Pos) /*!< HSOTG_T::INTSTS: SECHGIF Mask */
+
+#define HSOTG_INTSTS_SRPDETIF_Pos (13) /*!< HSOTG_T::INTSTS: SRPDETIF Position */
+#define HSOTG_INTSTS_SRPDETIF_Msk (0x1ul << HSOTG_INTSTS_SRPDETIF_Pos) /*!< HSOTG_T::INTSTS: SRPDETIF Mask */
+
+#define HSOTG_STATUS_OVERCUR_Pos (0) /*!< HSOTG_T::STATUS: OVERCUR Position */
+#define HSOTG_STATUS_OVERCUR_Msk (0x1ul << HSOTG_STATUS_OVERCUR_Pos) /*!< HSOTG_T::STATUS: OVERCUR Mask */
+
+#define HSOTG_STATUS_IDSTS_Pos (1) /*!< HSOTG_T::STATUS: IDSTS Position */
+#define HSOTG_STATUS_IDSTS_Msk (0x1ul << HSOTG_STATUS_IDSTS_Pos) /*!< HSOTG_T::STATUS: IDSTS Mask */
+
+#define HSOTG_STATUS_SESSEND_Pos (2) /*!< HSOTG_T::STATUS: SESSEND Position */
+#define HSOTG_STATUS_SESSEND_Msk (0x1ul << HSOTG_STATUS_SESSEND_Pos) /*!< HSOTG_T::STATUS: SESSEND Mask */
+
+#define HSOTG_STATUS_BVLD_Pos (3) /*!< HSOTG_T::STATUS: BVLD Position */
+#define HSOTG_STATUS_BVLD_Msk (0x1ul << HSOTG_STATUS_BVLD_Pos) /*!< HSOTG_T::STATUS: BVLD Mask */
+
+#define HSOTG_STATUS_AVLD_Pos (4) /*!< HSOTG_T::STATUS: AVLD Position */
+#define HSOTG_STATUS_AVLD_Msk (0x1ul << HSOTG_STATUS_AVLD_Pos) /*!< HSOTG_T::STATUS: AVLD Mask */
+
+#define HSOTG_STATUS_VBUSVLD_Pos (5) /*!< HSOTG_T::STATUS: VBUSVLD Position */
+#define HSOTG_STATUS_VBUSVLD_Msk (0x1ul << HSOTG_STATUS_VBUSVLD_Pos) /*!< HSOTG_T::STATUS: VBUSVLD Mask */
+
+#define HSOTG_STATUS_ASPERI_Pos (6) /*!< HSOTG_T::STATUS: ASPERI Position */
+#define HSOTG_STATUS_ASPERI_Msk (0x1ul << HSOTG_STATUS_ASPERI_Pos) /*!< HSOTG_T::STATUS: ASPERI Mask */
+
+#define HSOTG_STATUS_ASHOST_Pos (7) /*!< HSOTG_T::STATUS: ASHOST Position */
+#define HSOTG_STATUS_ASHOST_Msk (0x1ul << HSOTG_STATUS_ASHOST_Pos) /*!< HSOTG_T::STATUS: ASHOST Mask */
+
+/**@}*/ /* HSOTG_CONST */
+/**@}*/ /* end of HSOTG register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __HSOTG_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbd_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbd_reg.h
new file mode 100644
index 00000000000..7c301802397
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbd_reg.h
@@ -0,0 +1,1381 @@
+/**************************************************************************//**
+ * @file hsusbd_reg.h
+ * @version V1.00
+ * @brief HSUSBD register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __HSUSBD_REG_H__
+#define __HSUSBD_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup HSUSBD USB 2.0 Device Controller(HSUSBD)
+ Memory Mapped Structure for HSUSBD Controller
+@{ */
+
+typedef struct
+{
+
+ /**
+ * @var HSUSBD_EP_T::EPDAT
+ * Offset: 0x00 Endpoint n Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |EPDAT |Endpoint A~L Data Register
+ * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
+ * | | |Note: Only word access is supported.
+ * @var HSUSBD_EP_T::EPDAT_BYTE
+ * Offset: 0x00 Endpoint n Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |EPDAT |Endpoint A~L Data Register
+ * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
+ * | | |Note: Only byte access is supported.
+ * @var HSUSBD_EP_T::EPINTSTS
+ * Offset: 0x04 Endpoint n Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUFFULLIF |Buffer Full
+ * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write)
+ * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
+ * | | |0 = The endpoint packet buffer is not full.
+ * | | |1 = The endpoint packet buffer is full.
+ * | | |Note: This bit is read-only.
+ * |[1] |BUFEMPTYIF|Buffer Empty
+ * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
+ * | | |0 = The endpoint buffer is not empty.
+ * | | |1 = The endpoint buffer is empty.
+ * | | |For an OUT endpoint:
+ * | | |0 = The currently selected buffer has not a count of 0.
+ * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
+ * | | |Note: This bit is read-only.
+ * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
+ * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
+ * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[3] |TXPKIF |Data Packet Transmitted Interrupt
+ * | | |0 = Not a data packet is transmitted from the endpoint to the host.
+ * | | |1 = A data packet is transmitted from the endpoint to the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |RXPKIF |Data Packet Received Interrupt
+ * | | |0 = No data packet is received from the host by the endpoint.
+ * | | |1 = A data packet is received from the host by the endpoint.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |OUTTKIF |Data OUT Token Interrupt
+ * | | |0 = A Data OUT token has not been received from the host.
+ * | | |1 = A Data OUT token has been received from the host
+ * | | |This bit also set by PING token (in high-speed only).
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[6] |INTKIF |Data IN Token Interrupt
+ * | | |0 = Not Data IN token has been received from the host.
+ * | | |1 = A Data IN token has been received from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[7] |PINGIF |PING Token Interrupt
+ * | | |0 = A Data PING token has not been received from the host.
+ * | | |1 = A Data PING token has been received from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[8] |NAKIF |USB NAK Sent
+ * | | |0 = The last USB IN packet could be provided, and was acknowledged with an ACK.
+ * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[9] |STALLIF |USB STALL Sent
+ * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
+ * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[10] |NYETIF |NYET Sent
+ * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
+ * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[11] |ERRIF |ERR Sent
+ * | | |0 = No any error in the transaction.
+ * | | |1 = There occurs any error in the transaction.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[12] |SHORTRXIF |Bulk Out Short Packet Received
+ * | | |0 = No bulk out short packet is received.
+ * | | |1 = Received bulk out short packet (including zero length packet).
+ * | | |Note: Write 1 to clear this bit to 0.
+ * @var HSUSBD_EP_T::EPINTEN
+ * Offset: 0x08 Endpoint n Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUFFULLIEN|Buffer Full Interrupt
+ * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
+ * | | |0 = Buffer full interrupt Disabled.
+ * | | |1 = Buffer full interrupt Enabled.
+ * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
+ * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
+ * | | |0 = Buffer empty interrupt Disabled.
+ * | | |1 = Buffer empty interrupt Enabled.
+ * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
+ * | | |0 = Short data packet interrupt Disabled.
+ * | | |1 = Short data packet interrupt Enabled.
+ * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
+ * | | |0 = Data packet has been received from the host interrupt Disabled.
+ * | | |1 = Data packet has been received from the host interrupt Enabled.
+ * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
+ * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
+ * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
+ * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
+ * | | |0 = Data OUT token interrupt Disabled.
+ * | | |1 = Data OUT token interrupt Enabled.
+ * |[6] |INTKIEN |Data IN Token Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
+ * | | |0 = Data IN token interrupt Disabled.
+ * | | |1 = Data IN token interrupt Enabled.
+ * |[7] |PINGIEN |PING Token Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
+ * | | |0 = PING token interrupt Disabled.
+ * | | |1 = PING token interrupt Enabled.
+ * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
+ * | | |0 = NAK token interrupt Disabled.
+ * | | |1 = NAK token interrupt Enabled.
+ * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
+ * | | |0 = STALL token interrupt Disabled.
+ * | | |1 = STALL token interrupt Enabled.
+ * |[10] |NYETIEN |NYET Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
+ * | | |0 = NYET condition interrupt Disabled.
+ * | | |1 = NYET condition interrupt Enabled.
+ * |[11] |ERRIEN |ERR Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
+ * | | |0 = Error event interrupt Disabled.
+ * | | |1 = Error event interrupt Enabled.
+ * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
+ * | | |0 = Bulk out interrupt Disabled.
+ * | | |1 = Bulk out interrupt Enabled.
+ * @var HSUSBD_EP_T::EPDATCNT
+ * Offset: 0x0C Endpoint n Data Available Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DATCNT |Data Count
+ * | | |For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer.
+ * | | |For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer.
+ * |[30:16] |DMALOOP |DMA Loop
+ * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
+ * @var HSUSBD_EP_T::EPRSPCTL
+ * Offset: 0x10 Endpoint n Response Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FLUSH |Buffer Flush
+ * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared
+ * | | |This bit is self-clearing
+ * | | |This bit should always be written after an configuration event.
+ * | | |0 = The packet buffer is not flushed.
+ * | | |1 = The packet buffer is flushed by user.
+ * |[2:1] |MODE |Mode Control
+ * | | |The two bits decide the operation mode of the in-endpoint.
+ * | | |00: Auto-Validate Mode
+ * | | |01: Manual-Validate Mode
+ * | | |10: Fly Mode
+ * | | |11: Reserved
+ * | | |These bits are not valid for an out-endpoint
+ * | | |The auto validate mode will be activated when the reserved mode is selected
+ * |[3] |TOGGLE |Endpoint Toggle
+ * | | |This bit is used to clear the endpoint data toggle bit
+ * | | |Reading this bit returns the current state of the endpoint data toggle bit.
+ * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host
+ * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
+ * | | |0 = Not clear the endpoint data toggle bit.
+ * | | |1 = Clear the endpoint data toggle bit.
+ * |[4] |HALT |Endpoint Halt
+ * | | |This bit is used to send a STALL handshake as response to the token from the host
+ * | | |When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit.
+ * | | |0 = Not send a STALL handshake as response to the token from the host.
+ * | | |1 = Send a STALL handshake as response to the token from the host.
+ * |[5] |ZEROLEN |Zero Length
+ * | | |This bit is used to send a zero-length packet response to an IN-token
+ * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token
+ * | | |This bit gets cleared once the zero length data packet is sent.
+ * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
+ * | | |1 = A zero packet is sent to the host on reception of an IN-token.
+ * |[6] |SHORTTXEN |Short Packet Transfer Enable
+ * | | |This bit is applicable only in case of Auto-Validate Method
+ * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer
+ * | | |This bit gets cleared once the data packet is sent.
+ * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
+ * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
+ * |[7] |DISBUF |Buffer Disable Bit
+ * | | |This bit is used to receive unknown size OUT short packet
+ * | | |The received packet size is reference USBD_EPxDATCNT register.
+ * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
+ * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
+ * @var HSUSBD_EP_T::EPMPS
+ * Offset: 0x14 Endpoint n Maximum Packet Size Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[10:0] |EPMPS |Endpoint Maximum Packet Size
+ * | | |This field determines the Maximum Packet Size of the Endpoint.
+ * @var HSUSBD_EP_T::EPTXCNT
+ * Offset: 0x18 Endpoint n Transfer Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[10:0] |TXCNT |Endpoint Transfer Count
+ * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
+ * | | |For OUT endpoints, this field has no effect.
+ * @var HSUSBD_EP_T::EPCFG
+ * Offset: 0x1C Endpoint n Configuration Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |EPEN |Endpoint Valid
+ * | | |When set, this bit enables this endpoint
+ * | | |This bit has no effect on Endpoint 0, which is always enabled.
+ * | | |0 = The endpoint Disabled.
+ * | | |1 = The endpoint Enabled.
+ * |[2:1] |EPTYPE |Endpoint Type
+ * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
+ * | | |00 = Reserved.
+ * | | |01 = Bulk.
+ * | | |10 = Interrupt.
+ * | | |11 = Isochronous.
+ * |[3] |EPDIR |Endpoint Direction
+ * | | |0 = out-endpoint (Host OUT to Device).
+ * | | |1 = in-endpoint (Host IN to Device).
+ * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
+ * |[7:4] |EPNUM |Endpoint Number
+ * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
+ * | | |Note: Do not support two endpoints have same endpoint number.
+ * @var HSUSBD_EP_T::EPBUFST
+ * Offset: 0x20 Endpoint n RAM Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |SADDR |Endpoint Start Address
+ * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
+ * @var HSUSBD_EP_T::EPBUFEND
+ * Offset: 0x24 Endpoint n RAM End Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |EADDR |Endpoint End Address
+ * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
+ */
+
+ union
+ {
+ __IO uint32_t EPDAT;
+ __IO uint8_t EPDAT_BYTE;
+
+ }; /*!< [0x0000] Endpoint n Data Register */
+
+ __IO uint32_t EPINTSTS; /*!< [0x0004] Endpoint n Interrupt Status Register */
+ __IO uint32_t EPINTEN; /*!< [0x0008] Endpoint n Interrupt Enable Register */
+ __I uint32_t EPDATCNT; /*!< [0x000c] Endpoint n Data Available Count Register */
+ __IO uint32_t EPRSPCTL; /*!< [0x0010] Endpoint n Response Control Register */
+ __IO uint32_t EPMPS; /*!< [0x0014] Endpoint n Maximum Packet Size Register */
+ __IO uint32_t EPTXCNT; /*!< [0x0018] Endpoint n Transfer Count Register */
+ __IO uint32_t EPCFG; /*!< [0x001c] Endpoint n Configuration Register */
+ __IO uint32_t EPBUFST; /*!< [0x0020] Endpoint n RAM Start Address Register */
+ __IO uint32_t EPBUFEND; /*!< [0x0024] Endpoint n RAM End Address Register */
+
+} HSUSBD_EP_T;
+
+typedef struct
+{
+
+ /**
+ * @var HSUSBD_T::GINTSTS
+ * Offset: 0x00 Global Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |USBIF |USB Interrupt
+ * | | |This bit conveys the interrupt status for USB specific events endpoint
+ * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[1] |CEPIF |Control Endpoint Interrupt
+ * | | |This bit conveys the interrupt status for control endpoint
+ * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[2] |EPAIF |Endpoint a Interrupt
+ * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[3] |EPBIF |Endpoint B Interrupt
+ * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[4] |EPCIF |Endpoint C Interrupt
+ * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[5] |EPDIF |Endpoint D Interrupt
+ * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[6] |EPEIF |Endpoint E Interrupt
+ * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[7] |EPFIF |Endpoint F Interrupt
+ * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[8] |EPGIF |Endpoint G Interrupt
+ * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[9] |EPHIF |Endpoint H Interrupt
+ * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[10] |EPIIF |Endpoint I Interrupt
+ * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[11] |EPJIF |Endpoint J Interrupt
+ * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[12] |EPKIF |Endpoint K Interrupt
+ * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[13] |EPLIF |Endpoint L Interrupt
+ * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * @var HSUSBD_T::GINTEN
+ * Offset: 0x08 Global Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |USBIEN |USB Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus.
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[1] |CEPIEN |Control Endpoint Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[2] |EPAIEN |Interrupt Enable Control for Endpoint a
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[3] |EPBIEN |Interrupt Enable Control for Endpoint B
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[4] |EPCIEN |Interrupt Enable Control for Endpoint C
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[5] |EPDIEN |Interrupt Enable Control for Endpoint D
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[6] |EPEIEN |Interrupt Enable Control for Endpoint E
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[7] |EPFIEN |Interrupt Enable Control for Endpoint F
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[8] |EPGIEN |Interrupt Enable Control for Endpoint G
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[9] |EPHIEN |Interrupt Enable Control for Endpoint H
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[10] |EPIIEN |Interrupt Enable Control for Endpoint I
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[11] |EPJIEN |Interrupt Enable Control for Endpoint J
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[12] |EPKIEN |Interrupt Enable Control for Endpoint K
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[13] |EPLIEN |Interrupt Enable Control for Endpoint L
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * @var HSUSBD_T::BUSINTSTS
+ * Offset: 0x10 USB Bus Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SOFIF |SOF Receive Control
+ * | | |This bit indicates when a start-of-frame packet has been received.
+ * | | |0 = No start-of-frame packet has been received.
+ * | | |1 = Start-of-frame packet has been received.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[1] |RSTIF |Reset Status
+ * | | |When set, this bit indicates that either the USB root port reset is end.
+ * | | |0 = No USB root port reset is end.
+ * | | |1 = USB root port reset is end.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[2] |RESUMEIF |Resume
+ * | | |When set, this bit indicates that a device resume has occurred.
+ * | | |0 = No device resume has occurred.
+ * | | |1 = Device resume has occurred.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[3] |SUSPENDIF |Suspend Request
+ * | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset
+ * | | |This bit is also set when a USB Suspend request is detected from the host.
+ * | | |0 = No USB Suspend request is detected from the host.
+ * | | |1= USB Suspend request is detected from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |HISPDIF |High-speed Settle
+ * | | |0 = No valid high-speed reset protocol is detected.
+ * | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |DMADONEIF |DMA Completion Interrupt
+ * | | |0 = No DMA transfer over.
+ * | | |1 = DMA transfer is over.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[6] |PHYCLKVLDIF|Usable Clock Interrupt
+ * | | |0 = Usable clock is not available.
+ * | | |1 = Usable clock is available from the transceiver.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[8] |VBUSDETIF |VBUS Detection Interrupt Status
+ * | | |0 = No VBUS is plug-in.
+ * | | |1 = VBUS is plug-in.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * @var HSUSBD_T::BUSINTEN
+ * Offset: 0x14 USB Bus Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SOFIEN |SOF Interrupt
+ * | | |This bit enables the SOF interrupt.
+ * | | |0 = SOF interrupt Disabled.
+ * | | |1 = SOF interrupt Enabled.
+ * |[1] |RSTIEN |Reset Status
+ * | | |This bit enables the USB-Reset interrupt.
+ * | | |0 = USB-Reset interrupt Disabled.
+ * | | |1 = USB-Reset interrupt Enabled.
+ * |[2] |RESUMEIEN |Resume
+ * | | |This bit enables the Resume interrupt.
+ * | | |0 = Resume interrupt Disabled.
+ * | | |1 = Resume interrupt Enabled.
+ * |[3] |SUSPENDIEN|Suspend Request
+ * | | |This bit enables the Suspend interrupt.
+ * | | |0 = Suspend interrupt Disabled.
+ * | | |1 = Suspend interrupt Enabled.
+ * |[4] |HISPDIEN |High-speed Settle
+ * | | |This bit enables the high-speed settle interrupt.
+ * | | |0 = High-speed settle interrupt Disabled.
+ * | | |1 = High-speed settle interrupt Enabled.
+ * |[5] |DMADONEIEN|DMA Completion Interrupt
+ * | | |This bit enables the DMA completion interrupt
+ * | | |0 = DMA completion interrupt Disabled.
+ * | | |1 = DMA completion interrupt Enabled.
+ * |[6] |PHYCLKVLDIEN|Usable Clock Interrupt
+ * | | |This bit enables the usable clock interrupt.
+ * | | |0 = Usable clock interrupt Disabled.
+ * | | |1 = Usable clock interrupt Enabled.
+ * |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Bit
+ * | | |This bit enables the VBUS floating detection interrupt.
+ * | | |0 = VBUS floating detection interrupt Disabled.
+ * | | |1 = VBUS floating detection interrupt Enabled.
+ * @var HSUSBD_T::OPER
+ * Offset: 0x18 USB Operational Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RESUMEEN |Generate Resume
+ * | | |0 = No Resume sequence to be initiated to the host.
+ * | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled
+ * | | |This bit is self-clearing.
+ * |[1] |HISPDEN |USB High-speed
+ * | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host.
+ * | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol.
+ * |[2] |CURSPD |USB Current Speed
+ * | | |0 = The device has settled in Full Speed.
+ * | | |1 = The USB device controller has settled in High-speed.
+ * @var HSUSBD_T::FRAMECNT
+ * Offset: 0x1C USB Frame Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |MFRAMECNT |Micro-frame Counter
+ * | | |This field contains the micro-frame number for the frame number in the frame counter field.
+ * |[13:3] |FRAMECNT |Frame Counter
+ * | | |This field contains the frame count from the most recent start-of-frame packet.
+ * @var HSUSBD_T::FADDR
+ * Offset: 0x20 USB Function Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |FADDR |USB Function Address
+ * | | |This field contains the current USB address of the device
+ * | | |This field is cleared when a root port reset is detected
+ * @var HSUSBD_T::TEST
+ * Offset: 0x24 USB Test Mode Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |TESTMODE |Test Mode Selection
+ * | | |000 = Normal Operation.
+ * | | |001 = Test_J.
+ * | | |010 = Test_K.
+ * | | |011 = Test_SE0_NAK.
+ * | | |100 = Test_Packet.
+ * | | |101 = Test_Force_Enable.
+ * | | |110 = Reserved.
+ * | | |111 = Reserved.
+ * | | |Note: This field is cleared when root port reset is detected.
+ * @var HSUSBD_T::CEPDAT
+ * Offset: 0x28 Control-Endpoint Data Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DAT |Control-endpoint Data Buffer
+ * | | |Control endpoint data buffer for the buffer transaction (read or write).
+ * | | |Note: Only word access is supported.
+ * @var HSUSBD_T::CEPDAT_BYTE
+ * Offset: 0x28 Control-Endpoint Data Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DAT |Control-endpoint Data Buffer
+ * | | |Control endpoint data buffer for the buffer transaction (read or write).
+ * | | |Note: Only byte access is supported.
+ * @var HSUSBD_T::CEPCTL
+ * Offset: 0x2C Control-Endpoint Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |NAKCLR |No Acknowledge Control
+ * | | |This bit plays a crucial role in any control transfer.
+ * | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase
+ * | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request.
+ * | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received
+ * | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit.
+ * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
+ * |[1] |STALLEN |Stall Enable Bit
+ * | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter
+ * | | |This is typically used for response to invalid/unsupported requests
+ * | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL
+ * | | |It is automatically cleared on receipt of a next setup-token
+ * | | |So, the local CPU need not write again to clear this bit.
+ * | | |0 = No sends a stall handshake in response to any in or out token thereafter.
+ * | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter.
+ * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
+ * |[2] |ZEROLEN |Zero Packet Length
+ * | | |This bit is valid for Auto Validation mode only.
+ * | | |0 = No zero length packet to the host during Data stage to an IN token.
+ * | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token
+ * | | |This bit gets cleared once the zero length data packet is sent
+ * | | |So, the local CPU need not write again to clear this bit.
+ * |[3] |FLUSH |CEP-flush Bit
+ * | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared.
+ * | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared
+ * | | |This bit is self-cleaning.
+ * @var HSUSBD_T::CEPINTEN
+ * Offset: 0x30 Control-Endpoint Interrupt Enable
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SETUPTKIEN|Setup Token Interrupt Enable Bit
+ * | | |0 = The SETUP token interrupt in Control Endpoint Disabled.
+ * | | |1 = The SETUP token interrupt in Control Endpoint Enabled.
+ * |[1] |SETUPPKIEN|Setup Packet Interrupt
+ * | | |0 = The SETUP packet interrupt in Control Endpoint Disabled.
+ * | | |1 = The SETUP packet interrupt in Control Endpoint Enabled.
+ * |[2] |OUTTKIEN |Out Token Interrupt
+ * | | |0 = The OUT token interrupt in Control Endpoint Disabled.
+ * | | |1 = The OUT token interrupt in Control Endpoint Enabled.
+ * |[3] |INTKIEN |In Token Interrupt
+ * | | |0 = The IN token interrupt in Control Endpoint Disabled.
+ * | | |1 = The IN token interrupt in Control Endpoint Enabled.
+ * |[4] |PINGIEN |Ping Token Interrupt
+ * | | |0 = The ping token interrupt in Control Endpoint Disabled.
+ * | | |1 = The ping token interrupt Control Endpoint Enabled.
+ * |[5] |TXPKIEN |Data Packet Transmitted Interrupt
+ * | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled.
+ * | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled.
+ * |[6] |RXPKIEN |Data Packet Received Interrupt
+ * | | |0 = The data received interrupt in Control Endpoint Disabled.
+ * | | |1 = The data received interrupt in Control Endpoint Enabled.
+ * |[7] |NAKIEN |NAK Sent Interrupt
+ * | | |0 = The NAK sent interrupt in Control Endpoint Disabled.
+ * | | |1 = The NAK sent interrupt in Control Endpoint Enabled.
+ * |[8] |STALLIEN |STALL Sent Interrupt
+ * | | |0 = The STALL sent interrupt in Control Endpoint Disabled.
+ * | | |1 = The STALL sent interrupt in Control Endpoint Enabled.
+ * |[9] |ERRIEN |USB Error Interrupt
+ * | | |0 = The USB Error interrupt in Control Endpoint Disabled.
+ * | | |1 = The USB Error interrupt in Control Endpoint Enabled.
+ * |[10] |STSDONEIEN|Status Completion Interrupt
+ * | | |0 = The Status Completion interrupt in Control Endpoint Disabled.
+ * | | |1 = The Status Completion interrupt in Control Endpoint Enabled.
+ * |[11] |BUFFULLIEN|Buffer Full Interrupt
+ * | | |0 = The buffer full interrupt in Control Endpoint Disabled.
+ * | | |1 = The buffer full interrupt in Control Endpoint Enabled.
+ * |[12] |BUFEMPTYIEN|Buffer Empty Interrupt
+ * | | |0 = The buffer empty interrupt in Control Endpoint Disabled.
+ * | | |1= The buffer empty interrupt in Control Endpoint Enabled.
+ * @var HSUSBD_T::CEPINTSTS
+ * Offset: 0x34 Control-Endpoint Interrupt Status
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SETUPTKIF |Setup Token Interrupt
+ * | | |0 = Not a Setup token is received.
+ * | | |1 = A Setup token is received. Writing 1 clears this status bit
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[1] |SETUPPKIF |Setup Packet Interrupt
+ * | | |This bit must be cleared (by writing 1) before the next setup packet can be received
+ * | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer.
+ * | | |0 = Not a Setup packet has been received from the host.
+ * | | |1 = A Setup packet has been received from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[2] |OUTTKIF |Out Token Interrupt
+ * | | |0 = The control-endpoint does not received an OUT token from the host.
+ * | | |1 = The control-endpoint receives an OUT token from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[3] |INTKIF |in Token Interrupt
+ * | | |0 = The control-endpoint does not received an IN token from the host.
+ * | | |1 = The control-endpoint receives an IN token from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |PINGIF |Ping Token Interrupt
+ * | | |0 = The control-endpoint does not received a ping token from the host.
+ * | | |1 = The control-endpoint receives a ping token from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |TXPKIF |Data Packet Transmitted Interrupt
+ * | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
+ * | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[6] |RXPKIF |Data Packet Received Interrupt
+ * | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
+ * | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[7] |NAKIF |NAK Sent Interrupt
+ * | | |0 = Not a NAK-token is sent in response to an IN/OUT token.
+ * | | |1 = A NAK-token is sent in response to an IN/OUT token.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[8] |STALLIF |STALL Sent Interrupt
+ * | | |0 = Not a stall-token is sent in response to an IN/OUT token.
+ * | | |1 = A stall-token is sent in response to an IN/OUT token.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[9] |ERRIF |USB Error Interrupt
+ * | | |0 = No error had occurred during the transaction.
+ * | | |1 = An error had occurred during the transaction.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[10] |STSDONEIF |Status Completion Interrupt
+ * | | |0 = Not a USB transaction has completed successfully.
+ * | | |1 = The status stage of a USB transaction has completed successfully.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[11] |BUFFULLIF |Buffer Full Interrupt
+ * | | |0 = The control-endpoint buffer is not full.
+ * | | |1 = The control-endpoint buffer is full.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[12] |BUFEMPTYIF|Buffer Empty Interrupt
+ * | | |0 = The control-endpoint buffer is not empty.
+ * | | |1 = The control-endpoint buffer is empty.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * @var HSUSBD_T::CEPTXCNT
+ * Offset: 0x38 Control-Endpoint In-transfer Data Count
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TXCNT |In-transfer Data Count
+ * | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register
+ * | | |When zero is written into this field, a zero length packet is sent to the host
+ * | | |When the count written in the register is more than the MPS, the data sent will be of only MPS.
+ * @var HSUSBD_T::CEPRXCNT
+ * Offset: 0x3C Control-Endpoint Out-transfer Data Count
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |RXCNT |Out-transfer Data Count
+ * | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
+ * @var HSUSBD_T::CEPDATCNT
+ * Offset: 0x40 Control-Endpoint data count
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DATCNT |Control-endpoint Data Count
+ * | | |The USB device controller maintains the count of the data of control-endpoint.
+ * @var HSUSBD_T::SETUP1_0
+ * Offset: 0x44 Setup1 & Setup0 bytes
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SETUP0 |Setup Byte 0[7:0]
+ * | | |This register provides byte 0 of the last setup packet received
+ * | | |For a Standard Device Request, the following bmRequestType information is returned.
+ * | | |Bit 7(Direction):
+ * | | | 0: Host to device
+ * | | | 1: Device to host
+ * | | |Bit 6-5 (Type):
+ * | | | 00: Standard
+ * | | | 01: Class
+ * | | | 10: Vendor
+ * | | | 11: Reserved
+ * | | |Bit 4-0 (Recipient)
+ * | | | 00000: Device
+ * | | | 00001: Interface
+ * | | | 00010: Endpoint
+ * | | | 00011: Other
+ * | | | Others: Reserved
+ * |[15:8] |SETUP1 |Setup Byte 1[15:8]
+ * | | |This register provides byte 1 of the last setup packet received
+ * | | |For a Standard Device Request, the following bRequest Code information is returned.
+ * | | |00000000 = Get Status.
+ * | | |00000001 = Clear Feature.
+ * | | |00000010 = Reserved.
+ * | | |00000011 = Set Feature.
+ * | | |00000100 = Reserved.
+ * | | |00000101 = Set Address.
+ * | | |00000110 = Get Descriptor.
+ * | | |00000111 = Set Descriptor.
+ * | | |00001000 = Get Configuration.
+ * | | |00001001 = Set Configuration.
+ * | | |00001010 = Get Interface.
+ * | | |00001011 = Set Interface.
+ * | | |00001100 = Sync Frame.
+ * @var HSUSBD_T::SETUP3_2
+ * Offset: 0x48 Setup3 & Setup2 Bytes
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SETUP2 |Setup Byte 2 [7:0]
+ * | | |This register provides byte 2 of the last setup packet received
+ * | | |For a Standard Device Request, the least significant byte of the wValue field is returned
+ * |[15:8] |SETUP3 |Setup Byte 3 [15:8]
+ * | | |This register provides byte 3 of the last setup packet received
+ * | | |For a Standard Device Request, the most significant byte of the wValue field is returned.
+ * @var HSUSBD_T::SETUP5_4
+ * Offset: 0x4C Setup5 & Setup4 Bytes
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SETUP4 |Setup Byte 4[7:0]
+ * | | |This register provides byte 4 of the last setup packet received
+ * | | |For a Standard Device Request, the least significant byte of the wIndex is returned.
+ * |[15:8] |SETUP5 |Setup Byte 5[15:8]
+ * | | |This register provides byte 5 of the last setup packet received
+ * | | |For a Standard Device Request, the most significant byte of the wIndex field is returned.
+ * @var HSUSBD_T::SETUP7_6
+ * Offset: 0x50 Setup7 & Setup6 Bytes
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SETUP6 |Setup Byte 6[7:0]
+ * | | |This register provides byte 6 of the last setup packet received
+ * | | |For a Standard Device Request, the least significant byte of the wLength field is returned.
+ * |[15:8] |SETUP7 |Setup Byte 7[15:8]
+ * | | |This register provides byte 7 of the last setup packet received
+ * | | |For a Standard Device Request, the most significant byte of the wLength field is returned.
+ * @var HSUSBD_T::CEPBUFST
+ * Offset: 0x54 Control Endpoint RAM Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |SADDR |Control-endpoint Start Address
+ * | | |This is the start-address of the RAM space allocated for the control-endpoint.
+ * @var HSUSBD_T::CEPBUFEND
+ * Offset: 0x58 Control Endpoint RAM End Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |EADDR |Control-endpoint End Address
+ * | | |This is the end-address of the RAM space allocated for the control-endpoint.
+ * @var HSUSBD_T::DMACTL
+ * Offset: 0x5C DMA Control Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |EPNUM |DMA Endpoint Address Bits
+ * | | |Used to define the Endpoint Address
+ * |[4] |DMARD |DMA Operation
+ * | | |0 : The operation is a DMA write (read from USB buffer)
+ * | | |DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation.
+ * | | |1 : The operation is a DMA read (write to USB buffer).
+ * |[5] |DMAEN |DMA Enable Bit
+ * | | |0 : DMA function Disabled.
+ * | | |1 : DMA function Enabled.
+ * |[6] |SGEN |Scatter Gather Function Enable Bit
+ * | | |0 : Scatter gather function Disabled.
+ * | | |1 : Scatter gather function Enabled.
+ * |[7] |DMARST |Reset DMA State Machine
+ * | | |0 : No reset the DMA state machine.
+ * | | |1 : Reset the DMA state machine.
+ * |[8] |SVINEP |Serve IN Endpoint
+ * | | |This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint.
+ * | | |0: DMA serves OUT endpoint
+ * | | |1: DMA serves IN endpoint
+ * @var HSUSBD_T::DMACNT
+ * Offset: 0x60 DMA Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[19:0] |DMACNT |DMA Transfer Count
+ * | | |The transfer count of the DMA operation to be performed is written to this register.
+ * @var HSUSBD_T::DMAADDR
+ * Offset: 0x700 AHB DMA Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DMAADDR |DMAADDR
+ * | | |The register specifies the address from which the DMA has to read / write
+ * | | |The address must WORD (32-bit) aligned.
+ * @var HSUSBD_T::PHYCTL
+ * Offset: 0x704 USB PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8] |DPPUEN |DP Pull-up
+ * | | |0 = Pull-up resistor on D+ Disabled.
+ * | | |1 = Pull-up resistor on D+ Enabled.
+ * |[9] |PHYEN |PHY Suspend Enable Bit
+ * | | |0 = The USB PHY is suspend.
+ * | | |1 = The USB PHY is not suspend.
+ * |[24] |WKEN |Wake-up Enable Bit
+ * | | |0 = The wake-up function Disabled.
+ * | | |1 = The wake-up function Enabled.
+ * |[31] |VBUSDET |VBUS Status
+ * | | |0 = The VBUS is not detected yet.
+ * | | |1 = The VBUS is detected.
+ */
+
+ __I uint32_t GINTSTS; /*!< [0x0000] Global Interrupt Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t GINTEN; /*!< [0x0008] Global Interrupt Enable Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t BUSINTSTS; /*!< [0x0010] USB Bus Interrupt Status Register */
+ __IO uint32_t BUSINTEN; /*!< [0x0014] USB Bus Interrupt Enable Register */
+ __IO uint32_t OPER; /*!< [0x0018] USB Operational Register */
+ __I uint32_t FRAMECNT; /*!< [0x001c] USB Frame Count Register */
+ __IO uint32_t FADDR; /*!< [0x0020] USB Function Address Register */
+ __IO uint32_t TEST; /*!< [0x0024] USB Test Mode Register */
+
+ union
+ {
+ __IO uint32_t CEPDAT;
+ __IO uint8_t CEPDAT_BYTE;
+
+ }; /*!< [0x0028] Control-Endpoint Data Buffer */
+
+ __IO uint32_t CEPCTL; /*!< [0x002c] Control-Endpoint Control Register */
+ __IO uint32_t CEPINTEN; /*!< [0x0030] Control-Endpoint Interrupt Enable */
+ __IO uint32_t CEPINTSTS; /*!< [0x0034] Control-Endpoint Interrupt Status */
+ __IO uint32_t CEPTXCNT; /*!< [0x0038] Control-Endpoint In-transfer Data Count */
+ __I uint32_t CEPRXCNT; /*!< [0x003c] Control-Endpoint Out-transfer Data Count */
+ __I uint32_t CEPDATCNT; /*!< [0x0040] Control-Endpoint data count */
+ __I uint32_t SETUP1_0; /*!< [0x0044] Setup1 & Setup0 bytes */
+ __I uint32_t SETUP3_2; /*!< [0x0048] Setup3 & Setup2 Bytes */
+ __I uint32_t SETUP5_4; /*!< [0x004c] Setup5 & Setup4 Bytes */
+ __I uint32_t SETUP7_6; /*!< [0x0050] Setup7 & Setup6 Bytes */
+ __IO uint32_t CEPBUFST; /*!< [0x0054] Control Endpoint RAM Start Address Register */
+ __IO uint32_t CEPBUFEND; /*!< [0x0058] Control Endpoint RAM End Address Register */
+ __IO uint32_t DMACTL; /*!< [0x005c] DMA Control Status Register */
+ __IO uint32_t DMACNT; /*!< [0x0060] DMA Count Register */
+
+ HSUSBD_EP_T EP[12];
+
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[303];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DMAADDR; /*!< [0x0700] AHB DMA Address Register */
+ __IO uint32_t PHYCTL; /*!< [0x0704] USB PHY Control Register */
+
+} HSUSBD_T;
+
+/**
+ @addtogroup HSUSBD_CONST HSUSBD Bit Field Definition
+ Constant Definitions for HSUSBD Controller
+@{ */
+
+#define HSUSBD_GINTSTS_USBIF_Pos (0) /*!< HSUSBD_T::GINTSTS: USBIF Position */
+#define HSUSBD_GINTSTS_USBIF_Msk (0x1ul << HSUSBD_GINTSTS_USBIF_Pos) /*!< HSUSBD_T::GINTSTS: USBIF Mask */
+
+#define HSUSBD_GINTSTS_CEPIF_Pos (1) /*!< HSUSBD_T::GINTSTS: CEPIF Position */
+#define HSUSBD_GINTSTS_CEPIF_Msk (0x1ul << HSUSBD_GINTSTS_CEPIF_Pos) /*!< HSUSBD_T::GINTSTS: CEPIF Mask */
+
+#define HSUSBD_GINTSTS_EPAIF_Pos (2) /*!< HSUSBD_T::GINTSTS: EPAIF Position */
+#define HSUSBD_GINTSTS_EPAIF_Msk (0x1ul << HSUSBD_GINTSTS_EPAIF_Pos) /*!< HSUSBD_T::GINTSTS: EPAIF Mask */
+
+#define HSUSBD_GINTSTS_EPBIF_Pos (3) /*!< HSUSBD_T::GINTSTS: EPBIF Position */
+#define HSUSBD_GINTSTS_EPBIF_Msk (0x1ul << HSUSBD_GINTSTS_EPBIF_Pos) /*!< HSUSBD_T::GINTSTS: EPBIF Mask */
+
+#define HSUSBD_GINTSTS_EPCIF_Pos (4) /*!< HSUSBD_T::GINTSTS: EPCIF Position */
+#define HSUSBD_GINTSTS_EPCIF_Msk (0x1ul << HSUSBD_GINTSTS_EPCIF_Pos) /*!< HSUSBD_T::GINTSTS: EPCIF Mask */
+
+#define HSUSBD_GINTSTS_EPDIF_Pos (5) /*!< HSUSBD_T::GINTSTS: EPDIF Position */
+#define HSUSBD_GINTSTS_EPDIF_Msk (0x1ul << HSUSBD_GINTSTS_EPDIF_Pos) /*!< HSUSBD_T::GINTSTS: EPDIF Mask */
+
+#define HSUSBD_GINTSTS_EPEIF_Pos (6) /*!< HSUSBD_T::GINTSTS: EPEIF Position */
+#define HSUSBD_GINTSTS_EPEIF_Msk (0x1ul << HSUSBD_GINTSTS_EPEIF_Pos) /*!< HSUSBD_T::GINTSTS: EPEIF Mask */
+
+#define HSUSBD_GINTSTS_EPFIF_Pos (7) /*!< HSUSBD_T::GINTSTS: EPFIF Position */
+#define HSUSBD_GINTSTS_EPFIF_Msk (0x1ul << HSUSBD_GINTSTS_EPFIF_Pos) /*!< HSUSBD_T::GINTSTS: EPFIF Mask */
+
+#define HSUSBD_GINTSTS_EPGIF_Pos (8) /*!< HSUSBD_T::GINTSTS: EPGIF Position */
+#define HSUSBD_GINTSTS_EPGIF_Msk (0x1ul << HSUSBD_GINTSTS_EPGIF_Pos) /*!< HSUSBD_T::GINTSTS: EPGIF Mask */
+
+#define HSUSBD_GINTSTS_EPHIF_Pos (9) /*!< HSUSBD_T::GINTSTS: EPHIF Position */
+#define HSUSBD_GINTSTS_EPHIF_Msk (0x1ul << HSUSBD_GINTSTS_EPHIF_Pos) /*!< HSUSBD_T::GINTSTS: EPHIF Mask */
+
+#define HSUSBD_GINTSTS_EPIIF_Pos (10) /*!< HSUSBD_T::GINTSTS: EPIIF Position */
+#define HSUSBD_GINTSTS_EPIIF_Msk (0x1ul << HSUSBD_GINTSTS_EPIIF_Pos) /*!< HSUSBD_T::GINTSTS: EPIIF Mask */
+
+#define HSUSBD_GINTSTS_EPJIF_Pos (11) /*!< HSUSBD_T::GINTSTS: EPJIF Position */
+#define HSUSBD_GINTSTS_EPJIF_Msk (0x1ul << HSUSBD_GINTSTS_EPJIF_Pos) /*!< HSUSBD_T::GINTSTS: EPJIF Mask */
+
+#define HSUSBD_GINTSTS_EPKIF_Pos (12) /*!< HSUSBD_T::GINTSTS: EPKIF Position */
+#define HSUSBD_GINTSTS_EPKIF_Msk (0x1ul << HSUSBD_GINTSTS_EPKIF_Pos) /*!< HSUSBD_T::GINTSTS: EPKIF Mask */
+
+#define HSUSBD_GINTSTS_EPLIF_Pos (13) /*!< HSUSBD_T::GINTSTS: EPLIF Position */
+#define HSUSBD_GINTSTS_EPLIF_Msk (0x1ul << HSUSBD_GINTSTS_EPLIF_Pos) /*!< HSUSBD_T::GINTSTS: EPLIF Mask */
+
+#define HSUSBD_GINTEN_USBIEN_Pos (0) /*!< HSUSBD_T::GINTEN: USBIEN Position */
+#define HSUSBD_GINTEN_USBIEN_Msk (0x1ul << HSUSBD_GINTEN_USBIEN_Pos) /*!< HSUSBD_T::GINTEN: USBIEN Mask */
+
+#define HSUSBD_GINTEN_CEPIEN_Pos (1) /*!< HSUSBD_T::GINTEN: CEPIEN Position */
+#define HSUSBD_GINTEN_CEPIEN_Msk (0x1ul << HSUSBD_GINTEN_CEPIEN_Pos) /*!< HSUSBD_T::GINTEN: CEPIEN Mask */
+
+#define HSUSBD_GINTEN_EPAIEN_Pos (2) /*!< HSUSBD_T::GINTEN: EPAIEN Position */
+#define HSUSBD_GINTEN_EPAIEN_Msk (0x1ul << HSUSBD_GINTEN_EPAIEN_Pos) /*!< HSUSBD_T::GINTEN: EPAIEN Mask */
+
+#define HSUSBD_GINTEN_EPBIEN_Pos (3) /*!< HSUSBD_T::GINTEN: EPBIEN Position */
+#define HSUSBD_GINTEN_EPBIEN_Msk (0x1ul << HSUSBD_GINTEN_EPBIEN_Pos) /*!< HSUSBD_T::GINTEN: EPBIEN Mask */
+
+#define HSUSBD_GINTEN_EPCIEN_Pos (4) /*!< HSUSBD_T::GINTEN: EPCIEN Position */
+#define HSUSBD_GINTEN_EPCIEN_Msk (0x1ul << HSUSBD_GINTEN_EPCIEN_Pos) /*!< HSUSBD_T::GINTEN: EPCIEN Mask */
+
+#define HSUSBD_GINTEN_EPDIEN_Pos (5) /*!< HSUSBD_T::GINTEN: EPDIEN Position */
+#define HSUSBD_GINTEN_EPDIEN_Msk (0x1ul << HSUSBD_GINTEN_EPDIEN_Pos) /*!< HSUSBD_T::GINTEN: EPDIEN Mask */
+
+#define HSUSBD_GINTEN_EPEIEN_Pos (6) /*!< HSUSBD_T::GINTEN: EPEIEN Position */
+#define HSUSBD_GINTEN_EPEIEN_Msk (0x1ul << HSUSBD_GINTEN_EPEIEN_Pos) /*!< HSUSBD_T::GINTEN: EPEIEN Mask */
+
+#define HSUSBD_GINTEN_EPFIEN_Pos (7) /*!< HSUSBD_T::GINTEN: EPFIEN Position */
+#define HSUSBD_GINTEN_EPFIEN_Msk (0x1ul << HSUSBD_GINTEN_EPFIEN_Pos) /*!< HSUSBD_T::GINTEN: EPFIEN Mask */
+
+#define HSUSBD_GINTEN_EPGIEN_Pos (8) /*!< HSUSBD_T::GINTEN: EPGIEN Position */
+#define HSUSBD_GINTEN_EPGIEN_Msk (0x1ul << HSUSBD_GINTEN_EPGIEN_Pos) /*!< HSUSBD_T::GINTEN: EPGIEN Mask */
+
+#define HSUSBD_GINTEN_EPHIEN_Pos (9) /*!< HSUSBD_T::GINTEN: EPHIEN Position */
+#define HSUSBD_GINTEN_EPHIEN_Msk (0x1ul << HSUSBD_GINTEN_EPHIEN_Pos) /*!< HSUSBD_T::GINTEN: EPHIEN Mask */
+
+#define HSUSBD_GINTEN_EPIIEN_Pos (10) /*!< HSUSBD_T::GINTEN: EPIIEN Position */
+#define HSUSBD_GINTEN_EPIIEN_Msk (0x1ul << HSUSBD_GINTEN_EPIIEN_Pos) /*!< HSUSBD_T::GINTEN: EPIIEN Mask */
+
+#define HSUSBD_GINTEN_EPJIEN_Pos (11) /*!< HSUSBD_T::GINTEN: EPJIEN Position */
+#define HSUSBD_GINTEN_EPJIEN_Msk (0x1ul << HSUSBD_GINTEN_EPJIEN_Pos) /*!< HSUSBD_T::GINTEN: EPJIEN Mask */
+
+#define HSUSBD_GINTEN_EPKIEN_Pos (12) /*!< HSUSBD_T::GINTEN: EPKIEN Position */
+#define HSUSBD_GINTEN_EPKIEN_Msk (0x1ul << HSUSBD_GINTEN_EPKIEN_Pos) /*!< HSUSBD_T::GINTEN: EPKIEN Mask */
+
+#define HSUSBD_GINTEN_EPLIEN_Pos (13) /*!< HSUSBD_T::GINTEN: EPLIEN Position */
+#define HSUSBD_GINTEN_EPLIEN_Msk (0x1ul << HSUSBD_GINTEN_EPLIEN_Pos) /*!< HSUSBD_T::GINTEN: EPLIEN Mask */
+
+#define HSUSBD_BUSINTSTS_SOFIF_Pos (0) /*!< HSUSBD_T::BUSINTSTS: SOFIF Position */
+#define HSUSBD_BUSINTSTS_SOFIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SOFIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SOFIF Mask */
+
+#define HSUSBD_BUSINTSTS_RSTIF_Pos (1) /*!< HSUSBD_T::BUSINTSTS: RSTIF Position */
+#define HSUSBD_BUSINTSTS_RSTIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RSTIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RSTIF Mask */
+
+#define HSUSBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Position */
+#define HSUSBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RESUMEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Mask */
+
+#define HSUSBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Position*/
+#define HSUSBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SUSPENDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Mask */
+
+#define HSUSBD_BUSINTSTS_HISPDIF_Pos (4) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Position */
+#define HSUSBD_BUSINTSTS_HISPDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_HISPDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Mask */
+
+#define HSUSBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Position*/
+#define HSUSBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_DMADONEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Mask */
+
+#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Position*/
+#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Mask */
+
+#define HSUSBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Position*/
+#define HSUSBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << HSUSBD_BUSINTSTS_VBUSDETIF_Pos) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Mask */
+
+#define HSUSBD_BUSINTEN_SOFIEN_Pos (0) /*!< HSUSBD_T::BUSINTEN: SOFIEN Position */
+#define HSUSBD_BUSINTEN_SOFIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SOFIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SOFIEN Mask */
+
+#define HSUSBD_BUSINTEN_RSTIEN_Pos (1) /*!< HSUSBD_T::BUSINTEN: RSTIEN Position */
+#define HSUSBD_BUSINTEN_RSTIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RSTIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RSTIEN Mask */
+
+#define HSUSBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Position */
+#define HSUSBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RESUMEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Mask */
+
+#define HSUSBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Position*/
+#define HSUSBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SUSPENDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Mask */
+
+#define HSUSBD_BUSINTEN_HISPDIEN_Pos (4) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Position */
+#define HSUSBD_BUSINTEN_HISPDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_HISPDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Mask */
+
+#define HSUSBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Position*/
+#define HSUSBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_DMADONEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Mask */
+
+#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Position*/
+#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Mask */
+
+#define HSUSBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Position*/
+#define HSUSBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << HSUSBD_BUSINTEN_VBUSDETIEN_Pos) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Mask */
+
+#define HSUSBD_OPER_RESUMEEN_Pos (0) /*!< HSUSBD_T::OPER: RESUMEEN Position */
+#define HSUSBD_OPER_RESUMEEN_Msk (0x1ul << HSUSBD_OPER_RESUMEEN_Pos) /*!< HSUSBD_T::OPER: RESUMEEN Mask */
+
+#define HSUSBD_OPER_HISPDEN_Pos (1) /*!< HSUSBD_T::OPER: HISPDEN Position */
+#define HSUSBD_OPER_HISPDEN_Msk (0x1ul << HSUSBD_OPER_HISPDEN_Pos) /*!< HSUSBD_T::OPER: HISPDEN Mask */
+
+#define HSUSBD_OPER_CURSPD_Pos (2) /*!< HSUSBD_T::OPER: CURSPD Position */
+#define HSUSBD_OPER_CURSPD_Msk (0x1ul << HSUSBD_OPER_CURSPD_Pos) /*!< HSUSBD_T::OPER: CURSPD Mask */
+
+#define HSUSBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Position */
+#define HSUSBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << HSUSBD_FRAMECNT_MFRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Mask */
+
+#define HSUSBD_FRAMECNT_FRAMECNT_Pos (3) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Position */
+#define HSUSBD_FRAMECNT_FRAMECNT_Msk (0x7fful << HSUSBD_FRAMECNT_FRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Mask */
+
+#define HSUSBD_FADDR_FADDR_Pos (0) /*!< HSUSBD_T::FADDR: FADDR Position */
+#define HSUSBD_FADDR_FADDR_Msk (0x7ful << HSUSBD_FADDR_FADDR_Pos) /*!< HSUSBD_T::FADDR: FADDR Mask */
+
+#define HSUSBD_TEST_TESTMODE_Pos (0) /*!< HSUSBD_T::TEST: TESTMODE Position */
+#define HSUSBD_TEST_TESTMODE_Msk (0x7ul << HSUSBD_TEST_TESTMODE_Pos) /*!< HSUSBD_T::TEST: TESTMODE Mask */
+
+#define HSUSBD_CEPDAT_DAT_Pos (0) /*!< HSUSBD_T::CEPDAT: DAT Position */
+#define HSUSBD_CEPDAT_DAT_Msk (0xfffffffful << HSUSBD_CEPDAT_DAT_Pos) /*!< HSUSBD_T::CEPDAT: DAT Mask */
+
+#define HSUSBD_CEPCTL_NAKCLR_Pos (0) /*!< HSUSBD_T::CEPCTL: NAKCLR Position */
+#define HSUSBD_CEPCTL_NAKCLR_Msk (0x1ul << HSUSBD_CEPCTL_NAKCLR_Pos) /*!< HSUSBD_T::CEPCTL: NAKCLR Mask */
+
+#define HSUSBD_CEPCTL_STALLEN_Pos (1) /*!< HSUSBD_T::CEPCTL: STALLEN Position */
+#define HSUSBD_CEPCTL_STALLEN_Msk (0x1ul << HSUSBD_CEPCTL_STALLEN_Pos) /*!< HSUSBD_T::CEPCTL: STALLEN Mask */
+
+#define HSUSBD_CEPCTL_ZEROLEN_Pos (2) /*!< HSUSBD_T::CEPCTL: ZEROLEN Position */
+#define HSUSBD_CEPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_CEPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::CEPCTL: ZEROLEN Mask */
+
+#define HSUSBD_CEPCTL_FLUSH_Pos (3) /*!< HSUSBD_T::CEPCTL: FLUSH Position */
+#define HSUSBD_CEPCTL_FLUSH_Msk (0x1ul << HSUSBD_CEPCTL_FLUSH_Pos) /*!< HSUSBD_T::CEPCTL: FLUSH Mask */
+
+#define HSUSBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Position*/
+#define HSUSBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Mask */
+
+#define HSUSBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Position*/
+#define HSUSBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Mask */
+
+#define HSUSBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Position */
+#define HSUSBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Mask */
+
+#define HSUSBD_CEPINTEN_INTKIEN_Pos (3) /*!< HSUSBD_T::CEPINTEN: INTKIEN Position */
+#define HSUSBD_CEPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: INTKIEN Mask */
+
+#define HSUSBD_CEPINTEN_PINGIEN_Pos (4) /*!< HSUSBD_T::CEPINTEN: PINGIEN Position */
+#define HSUSBD_CEPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_CEPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::CEPINTEN: PINGIEN Mask */
+
+#define HSUSBD_CEPINTEN_TXPKIEN_Pos (5) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Position */
+#define HSUSBD_CEPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Mask */
+
+#define HSUSBD_CEPINTEN_RXPKIEN_Pos (6) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Position */
+#define HSUSBD_CEPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Mask */
+
+#define HSUSBD_CEPINTEN_NAKIEN_Pos (7) /*!< HSUSBD_T::CEPINTEN: NAKIEN Position */
+#define HSUSBD_CEPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: NAKIEN Mask */
+
+#define HSUSBD_CEPINTEN_STALLIEN_Pos (8) /*!< HSUSBD_T::CEPINTEN: STALLIEN Position */
+#define HSUSBD_CEPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STALLIEN Mask */
+
+#define HSUSBD_CEPINTEN_ERRIEN_Pos (9) /*!< HSUSBD_T::CEPINTEN: ERRIEN Position */
+#define HSUSBD_CEPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_CEPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::CEPINTEN: ERRIEN Mask */
+
+#define HSUSBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Position*/
+#define HSUSBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STSDONEIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Mask */
+
+#define HSUSBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Position*/
+#define HSUSBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Mask */
+
+#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Position*/
+#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Mask */
+
+#define HSUSBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Position*/
+#define HSUSBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Mask */
+
+#define HSUSBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Position*/
+#define HSUSBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Mask */
+
+#define HSUSBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Position */
+#define HSUSBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Mask */
+
+#define HSUSBD_CEPINTSTS_INTKIF_Pos (3) /*!< HSUSBD_T::CEPINTSTS: INTKIF Position */
+#define HSUSBD_CEPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: INTKIF Mask */
+
+#define HSUSBD_CEPINTSTS_PINGIF_Pos (4) /*!< HSUSBD_T::CEPINTSTS: PINGIF Position */
+#define HSUSBD_CEPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_CEPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::CEPINTSTS: PINGIF Mask */
+
+#define HSUSBD_CEPINTSTS_TXPKIF_Pos (5) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Position */
+#define HSUSBD_CEPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Mask */
+
+#define HSUSBD_CEPINTSTS_RXPKIF_Pos (6) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Position */
+#define HSUSBD_CEPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Mask */
+
+#define HSUSBD_CEPINTSTS_NAKIF_Pos (7) /*!< HSUSBD_T::CEPINTSTS: NAKIF Position */
+#define HSUSBD_CEPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: NAKIF Mask */
+
+#define HSUSBD_CEPINTSTS_STALLIF_Pos (8) /*!< HSUSBD_T::CEPINTSTS: STALLIF Position */
+#define HSUSBD_CEPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STALLIF Mask */
+
+#define HSUSBD_CEPINTSTS_ERRIF_Pos (9) /*!< HSUSBD_T::CEPINTSTS: ERRIF Position */
+#define HSUSBD_CEPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_CEPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::CEPINTSTS: ERRIF Mask */
+
+#define HSUSBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Position*/
+#define HSUSBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STSDONEIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Mask */
+
+#define HSUSBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Position*/
+#define HSUSBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Mask */
+
+#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Position*/
+#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Mask */
+
+#define HSUSBD_CEPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::CEPTXCNT: TXCNT Position */
+#define HSUSBD_CEPTXCNT_TXCNT_Msk (0xfful << HSUSBD_CEPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::CEPTXCNT: TXCNT Mask */
+
+#define HSUSBD_CEPRXCNT_RXCNT_Pos (0) /*!< HSUSBD_T::CEPRXCNT: RXCNT Position */
+#define HSUSBD_CEPRXCNT_RXCNT_Msk (0xfful << HSUSBD_CEPRXCNT_RXCNT_Pos) /*!< HSUSBD_T::CEPRXCNT: RXCNT Mask */
+
+#define HSUSBD_CEPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::CEPDATCNT: DATCNT Position */
+#define HSUSBD_CEPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_CEPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::CEPDATCNT: DATCNT Mask */
+
+#define HSUSBD_SETUP1_0_SETUP0_Pos (0) /*!< HSUSBD_T::SETUP1_0: SETUP0 Position */
+#define HSUSBD_SETUP1_0_SETUP0_Msk (0xfful << HSUSBD_SETUP1_0_SETUP0_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP0 Mask */
+
+#define HSUSBD_SETUP1_0_SETUP1_Pos (8) /*!< HSUSBD_T::SETUP1_0: SETUP1 Position */
+#define HSUSBD_SETUP1_0_SETUP1_Msk (0xfful << HSUSBD_SETUP1_0_SETUP1_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP1 Mask */
+
+#define HSUSBD_SETUP3_2_SETUP2_Pos (0) /*!< HSUSBD_T::SETUP3_2: SETUP2 Position */
+#define HSUSBD_SETUP3_2_SETUP2_Msk (0xfful << HSUSBD_SETUP3_2_SETUP2_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP2 Mask */
+
+#define HSUSBD_SETUP3_2_SETUP3_Pos (8) /*!< HSUSBD_T::SETUP3_2: SETUP3 Position */
+#define HSUSBD_SETUP3_2_SETUP3_Msk (0xfful << HSUSBD_SETUP3_2_SETUP3_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP3 Mask */
+
+#define HSUSBD_SETUP5_4_SETUP4_Pos (0) /*!< HSUSBD_T::SETUP5_4: SETUP4 Position */
+#define HSUSBD_SETUP5_4_SETUP4_Msk (0xfful << HSUSBD_SETUP5_4_SETUP4_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP4 Mask */
+
+#define HSUSBD_SETUP5_4_SETUP5_Pos (8) /*!< HSUSBD_T::SETUP5_4: SETUP5 Position */
+#define HSUSBD_SETUP5_4_SETUP5_Msk (0xfful << HSUSBD_SETUP5_4_SETUP5_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP5 Mask */
+
+#define HSUSBD_SETUP7_6_SETUP6_Pos (0) /*!< HSUSBD_T::SETUP7_6: SETUP6 Position */
+#define HSUSBD_SETUP7_6_SETUP6_Msk (0xfful << HSUSBD_SETUP7_6_SETUP6_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP6 Mask */
+
+#define HSUSBD_SETUP7_6_SETUP7_Pos (8) /*!< HSUSBD_T::SETUP7_6: SETUP7 Position */
+#define HSUSBD_SETUP7_6_SETUP7_Msk (0xfful << HSUSBD_SETUP7_6_SETUP7_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP7 Mask */
+
+#define HSUSBD_CEPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::CEPBUFST: SADDR Position */
+#define HSUSBD_CEPBUFST_SADDR_Msk (0xffful << HSUSBD_CEPBUFST_SADDR_Pos) /*!< HSUSBD_T::CEPBUFST: SADDR Mask */
+
+#define HSUSBD_CEPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::CEPBUFEND: EADDR Position */
+#define HSUSBD_CEPBUFEND_EADDR_Msk (0xffful << HSUSBD_CEPBUFEND_EADDR_Pos) /*!< HSUSBD_T::CEPBUFEND: EADDR Mask */
+
+#define HSUSBD_DMACTL_EPNUM_Pos (0) /*!< HSUSBD_T::DMACTL: EPNUM Position */
+#define HSUSBD_DMACTL_EPNUM_Msk (0xful << HSUSBD_DMACTL_EPNUM_Pos) /*!< HSUSBD_T::DMACTL: EPNUM Mask */
+
+#define HSUSBD_DMACTL_DMARD_Pos (4) /*!< HSUSBD_T::DMACTL: DMARD Position */
+#define HSUSBD_DMACTL_DMARD_Msk (0x1ul << HSUSBD_DMACTL_DMARD_Pos) /*!< HSUSBD_T::DMACTL: DMARD Mask */
+
+#define HSUSBD_DMACTL_DMAEN_Pos (5) /*!< HSUSBD_T::DMACTL: DMAEN Position */
+#define HSUSBD_DMACTL_DMAEN_Msk (0x1ul << HSUSBD_DMACTL_DMAEN_Pos) /*!< HSUSBD_T::DMACTL: DMAEN Mask */
+
+#define HSUSBD_DMACTL_SGEN_Pos (6) /*!< HSUSBD_T::DMACTL: SGEN Position */
+#define HSUSBD_DMACTL_SGEN_Msk (0x1ul << HSUSBD_DMACTL_SGEN_Pos) /*!< HSUSBD_T::DMACTL: SGEN Mask */
+
+#define HSUSBD_DMACTL_DMARST_Pos (7) /*!< HSUSBD_T::DMACTL: DMARST Position */
+#define HSUSBD_DMACTL_DMARST_Msk (0x1ul << HSUSBD_DMACTL_DMARST_Pos) /*!< HSUSBD_T::DMACTL: DMARST Mask */
+
+#define HSUSBD_DMACTL_SVINEP_Pos (8) /*!< HSUSBD_T::DMACTL: SVINEP Position */
+#define HSUSBD_DMACTL_SVINEP_Msk (0x1ul << HSUSBD_DMACTL_SVINEP_Pos) /*!< HSUSBD_T::DMACTL: SVINEP Mask */
+
+#define HSUSBD_DMACNT_DMACNT_Pos (0) /*!< HSUSBD_T::DMACNT: DMACNT Position */
+#define HSUSBD_DMACNT_DMACNT_Msk (0xffffful << HSUSBD_DMACNT_DMACNT_Pos) /*!< HSUSBD_T::DMACNT: DMACNT Mask */
+
+#define HSUSBD_EPDAT_EPDAT_Pos (0) /*!< HSUSBD_T::EPDAT: EPDAT Position */
+#define HSUSBD_EPDAT_EPDAT_Msk (0xfffffffful << HSUSBD_EPDAT_EPDAT_Pos) /*!< HSUSBD_T::EPDAT: EPDAT Mask */
+
+#define HSUSBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Position */
+#define HSUSBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Mask */
+
+#define HSUSBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Position*/
+#define HSUSBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Mask */
+
+#define HSUSBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Position */
+#define HSUSBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTTXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Mask */
+
+#define HSUSBD_EPINTSTS_TXPKIF_Pos (3) /*!< HSUSBD_T::EPINTSTS: TXPKIF Position */
+#define HSUSBD_EPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: TXPKIF Mask */
+
+#define HSUSBD_EPINTSTS_RXPKIF_Pos (4) /*!< HSUSBD_T::EPINTSTS: RXPKIF Position */
+#define HSUSBD_EPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: RXPKIF Mask */
+
+#define HSUSBD_EPINTSTS_OUTTKIF_Pos (5) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Position */
+#define HSUSBD_EPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Mask */
+
+#define HSUSBD_EPINTSTS_INTKIF_Pos (6) /*!< HSUSBD_T::EPINTSTS: INTKIF Position */
+#define HSUSBD_EPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: INTKIF Mask */
+
+#define HSUSBD_EPINTSTS_PINGIF_Pos (7) /*!< HSUSBD_T::EPINTSTS: PINGIF Position */
+#define HSUSBD_EPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_EPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::EPINTSTS: PINGIF Mask */
+
+#define HSUSBD_EPINTSTS_NAKIF_Pos (8) /*!< HSUSBD_T::EPINTSTS: NAKIF Position */
+#define HSUSBD_EPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_EPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::EPINTSTS: NAKIF Mask */
+
+#define HSUSBD_EPINTSTS_STALLIF_Pos (9) /*!< HSUSBD_T::EPINTSTS: STALLIF Position */
+#define HSUSBD_EPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_EPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::EPINTSTS: STALLIF Mask */
+
+#define HSUSBD_EPINTSTS_NYETIF_Pos (10) /*!< HSUSBD_T::EPINTSTS: NYETIF Position */
+#define HSUSBD_EPINTSTS_NYETIF_Msk (0x1ul << HSUSBD_EPINTSTS_NYETIF_Pos) /*!< HSUSBD_T::EPINTSTS: NYETIF Mask */
+
+#define HSUSBD_EPINTSTS_ERRIF_Pos (11) /*!< HSUSBD_T::EPINTSTS: ERRIF Position */
+#define HSUSBD_EPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_EPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::EPINTSTS: ERRIF Mask */
+
+#define HSUSBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Position */
+#define HSUSBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTRXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Mask */
+
+#define HSUSBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Position */
+#define HSUSBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Mask */
+
+#define HSUSBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Position*/
+#define HSUSBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Mask */
+
+#define HSUSBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Position */
+#define HSUSBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTTXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Mask */
+
+#define HSUSBD_EPINTEN_TXPKIEN_Pos (3) /*!< HSUSBD_T::EPINTEN: TXPKIEN Position */
+#define HSUSBD_EPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: TXPKIEN Mask */
+
+#define HSUSBD_EPINTEN_RXPKIEN_Pos (4) /*!< HSUSBD_T::EPINTEN: RXPKIEN Position */
+#define HSUSBD_EPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: RXPKIEN Mask */
+
+#define HSUSBD_EPINTEN_OUTTKIEN_Pos (5) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Position */
+#define HSUSBD_EPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Mask */
+
+#define HSUSBD_EPINTEN_INTKIEN_Pos (6) /*!< HSUSBD_T::EPINTEN: INTKIEN Position */
+#define HSUSBD_EPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: INTKIEN Mask */
+
+#define HSUSBD_EPINTEN_PINGIEN_Pos (7) /*!< HSUSBD_T::EPINTEN: PINGIEN Position */
+#define HSUSBD_EPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_EPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::EPINTEN: PINGIEN Mask */
+
+#define HSUSBD_EPINTEN_NAKIEN_Pos (8) /*!< HSUSBD_T::EPINTEN: NAKIEN Position */
+#define HSUSBD_EPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_EPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::EPINTEN: NAKIEN Mask */
+
+#define HSUSBD_EPINTEN_STALLIEN_Pos (9) /*!< HSUSBD_T::EPINTEN: STALLIEN Position */
+#define HSUSBD_EPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_EPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::EPINTEN: STALLIEN Mask */
+
+#define HSUSBD_EPINTEN_NYETIEN_Pos (10) /*!< HSUSBD_T::EPINTEN: NYETIEN Position */
+#define HSUSBD_EPINTEN_NYETIEN_Msk (0x1ul << HSUSBD_EPINTEN_NYETIEN_Pos) /*!< HSUSBD_T::EPINTEN: NYETIEN Mask */
+
+#define HSUSBD_EPINTEN_ERRIEN_Pos (11) /*!< HSUSBD_T::EPINTEN: ERRIEN Position */
+#define HSUSBD_EPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_EPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::EPINTEN: ERRIEN Mask */
+
+#define HSUSBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Position */
+#define HSUSBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTRXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Mask */
+
+#define HSUSBD_EPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::EPDATCNT: DATCNT Position */
+#define HSUSBD_EPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_EPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::EPDATCNT: DATCNT Mask */
+
+#define HSUSBD_EPDATCNT_DMALOOP_Pos (16) /*!< HSUSBD_T::EPDATCNT: DMALOOP Position */
+#define HSUSBD_EPDATCNT_DMALOOP_Msk (0x7ffful << HSUSBD_EPDATCNT_DMALOOP_Pos) /*!< HSUSBD_T::EPDATCNT: DMALOOP Mask */
+
+#define HSUSBD_EPRSPCTL_FLUSH_Pos (0) /*!< HSUSBD_T::EPRSPCTL: FLUSH Position */
+#define HSUSBD_EPRSPCTL_FLUSH_Msk (0x1ul << HSUSBD_EPRSPCTL_FLUSH_Pos) /*!< HSUSBD_T::EPRSPCTL: FLUSH Mask */
+
+#define HSUSBD_EPRSPCTL_MODE_Pos (1) /*!< HSUSBD_T::EPRSPCTL: MODE Position */
+#define HSUSBD_EPRSPCTL_MODE_Msk (0x3ul << HSUSBD_EPRSPCTL_MODE_Pos) /*!< HSUSBD_T::EPRSPCTL: MODE Mask */
+
+#define HSUSBD_EPRSPCTL_TOGGLE_Pos (3) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Position */
+#define HSUSBD_EPRSPCTL_TOGGLE_Msk (0x1ul << HSUSBD_EPRSPCTL_TOGGLE_Pos) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Mask */
+
+#define HSUSBD_EPRSPCTL_HALT_Pos (4) /*!< HSUSBD_T::EPRSPCTL: HALT Position */
+#define HSUSBD_EPRSPCTL_HALT_Msk (0x1ul << HSUSBD_EPRSPCTL_HALT_Pos) /*!< HSUSBD_T::EPRSPCTL: HALT Mask */
+
+#define HSUSBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Position */
+#define HSUSBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_EPRSPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Mask */
+
+#define HSUSBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Position */
+#define HSUSBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << HSUSBD_EPRSPCTL_SHORTTXEN_Pos) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Mask */
+
+#define HSUSBD_EPRSPCTL_DISBUF_Pos (7) /*!< HSUSBD_T::EPRSPCTL: DISBUF Position */
+#define HSUSBD_EPRSPCTL_DISBUF_Msk (0x1ul << HSUSBD_EPRSPCTL_DISBUF_Pos) /*!< HSUSBD_T::EPRSPCTL: DISBUF Mask */
+
+#define HSUSBD_EPMPS_EPMPS_Pos (0) /*!< HSUSBD_T::EPMPS: EPMPS Position */
+#define HSUSBD_EPMPS_EPMPS_Msk (0x7fful << HSUSBD_EPMPS_EPMPS_Pos) /*!< HSUSBD_T::EPMPS: EPMPS Mask */
+
+#define HSUSBD_EPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::EPTXCNT: TXCNT Position */
+#define HSUSBD_EPTXCNT_TXCNT_Msk (0x7fful << HSUSBD_EPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::EPTXCNT: TXCNT Mask */
+
+#define HSUSBD_EPCFG_EPEN_Pos (0) /*!< HSUSBD_T::EPCFG: EPEN Position */
+#define HSUSBD_EPCFG_EPEN_Msk (0x1ul << HSUSBD_EPCFG_EPEN_Pos) /*!< HSUSBD_T::EPCFG: EPEN Mask */
+
+#define HSUSBD_EPCFG_EPTYPE_Pos (1) /*!< HSUSBD_T::EPCFG: EPTYPE Position */
+#define HSUSBD_EPCFG_EPTYPE_Msk (0x3ul << HSUSBD_EPCFG_EPTYPE_Pos) /*!< HSUSBD_T::EPCFG: EPTYPE Mask */
+
+#define HSUSBD_EPCFG_EPDIR_Pos (3) /*!< HSUSBD_T::EPCFG: EPDIR Position */
+#define HSUSBD_EPCFG_EPDIR_Msk (0x1ul << HSUSBD_EPCFG_EPDIR_Pos) /*!< HSUSBD_T::EPCFG: EPDIR Mask */
+
+#define HSUSBD_EPCFG_EPNUM_Pos (4) /*!< HSUSBD_T::EPCFG: EPNUM Position */
+#define HSUSBD_EPCFG_EPNUM_Msk (0xful << HSUSBD_EPCFG_EPNUM_Pos) /*!< HSUSBD_T::EPCFG: EPNUM Mask */
+
+#define HSUSBD_EPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::EPBUFST: SADDR Position */
+#define HSUSBD_EPBUFST_SADDR_Msk (0xffful << HSUSBD_EPBUFST_SADDR_Pos) /*!< HSUSBD_T::EPBUFST: SADDR Mask */
+
+#define HSUSBD_EPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::EPBUFEND: EADDR Position */
+#define HSUSBD_EPBUFEND_EADDR_Msk (0xffful << HSUSBD_EPBUFEND_EADDR_Pos) /*!< HSUSBD_T::EPBUFEND: EADDR Mask */
+
+#define HSUSBD_DMAADDR_DMAADDR_Pos (0) /*!< HSUSBD_T::DMAADDR: DMAADDR Position */
+#define HSUSBD_DMAADDR_DMAADDR_Msk (0xfffffffful << HSUSBD_DMAADDR_DMAADDR_Pos) /*!< HSUSBD_T::DMAADDR: DMAADDR Mask */
+
+#define HSUSBD_PHYCTL_DPPUEN_Pos (8) /*!< HSUSBD_T::PHYCTL: DPPUEN Position */
+#define HSUSBD_PHYCTL_DPPUEN_Msk (0x1ul << HSUSBD_PHYCTL_DPPUEN_Pos) /*!< HSUSBD_T::PHYCTL: DPPUEN Mask */
+
+#define HSUSBD_PHYCTL_PHYEN_Pos (9) /*!< HSUSBD_T::PHYCTL: PHYEN Position */
+#define HSUSBD_PHYCTL_PHYEN_Msk (0x1ul << HSUSBD_PHYCTL_PHYEN_Pos) /*!< HSUSBD_T::PHYCTL: PHYEN Mask */
+
+#define HSUSBD_PHYCTL_WKEN_Pos (24) /*!< HSUSBD_T::PHYCTL: WKEN Position */
+#define HSUSBD_PHYCTL_WKEN_Msk (0x1ul << HSUSBD_PHYCTL_WKEN_Pos) /*!< HSUSBD_T::PHYCTL: WKEN Mask */
+
+#define HSUSBD_PHYCTL_VBUSDET_Pos (31) /*!< HSUSBD_T::PHYCTL: VBUSDET Position */
+#define HSUSBD_PHYCTL_VBUSDET_Msk (0x1ul << HSUSBD_PHYCTL_VBUSDET_Pos) /*!< HSUSBD_T::PHYCTL: VBUSDET Mask */
+
+/**@}*/ /* HSUSBD_CONST */
+/**@}*/ /* end of HSUSBD register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __HSUSBD_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbh_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbh_reg.h
new file mode 100644
index 00000000000..57cc5d03760
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbh_reg.h
@@ -0,0 +1,653 @@
+/**************************************************************************//**
+ * @file hsusbh_reg.h
+ * @version V1.00
+ * @brief HSUSBH register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __HSUSBH_REG_H__
+#define __HSUSBH_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup HSUSBH High Speed USB Host Controller (HSUSBH)
+ Memory Mapped Structure for HSUSBH Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var HSUSBH_T::EHCVNR
+ * Offset: 0x00 EHCI Version Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CRLEN |Capability Registers Length
+ * | | |This register is used as an offset to add to register base to find the beginning of the Operational Register Space.
+ * |[31:16] |VERSION |Host Controller Interface Version Number
+ * | | |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller
+ * | | |The most significant byte of this register represents a major revision and the least significant byte is the minor revision.
+ * @var HSUSBH_T::EHCSPR
+ * Offset: 0x04 EHCI Structural Parameters Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |N_PORTS |Number of Physical Downstream Ports
+ * | | |This field specifies the number of physical downstream ports implemented on this host controller
+ * | | |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8)
+ * | | |Valid values are in the range of 1H to FH.
+ * | | |A zero in this field is undefined.
+ * |[4] |PPC |Port Power Control
+ * | | |This field indicates whether the host controller implementation includes port power control
+ * | | |A one in this bit indicates the ports have port power switches
+ * | | |A zero in this bit indicates the port do not have port power stitches
+ * | | |The value of this field affects the functionality of the Port Power field in each port status and control register.
+ * |[11:8] |N_PCC |Number of Ports Per Companion Controller
+ * | | |This field indicates the number of ports supported per companion host controller
+ * | | |It is used to indicate the port routing configuration to system software.
+ * | | |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3
+ * | | |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc
+ * | | |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2.
+ * | | |The number in this field must be consistent with N_PORTS and N_CC.
+ * |[15:12] |N_CC |Number of Companion Controller
+ * | | |This field indicates the number of companion controllers associated with this USB 2.0 host controller.
+ * | | |A zero in this field indicates there are no companion host controllers
+ * | | |Port-ownership hand-off is not supported
+ * | | |Only high-speed devices are supported on the host controller root ports.
+ * | | |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s)
+ * | | |Port-ownership hand-offs are supported
+ * | | |High, Full- and Low-speed devices are supported on the host controller root ports.
+ * @var HSUSBH_T::EHCCPR
+ * Offset: 0x08 EHCI Capability Parameters Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |AC64 |64-bit Addressing Capability
+ * | | |0 = Data structure using 32-bit address memory pointers.
+ * |[1] |PFLF |Programmable Frame List Flag
+ * | | |0 = System software must use a frame list length of 1024 elements with this EHCI host controller.
+ * |[2] |ASPC |Asynchronous Schedule Park Capability
+ * | | |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule.
+ * |[7:4] |IST |Isochronous Scheduling Threshold
+ * | | |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule.
+ * | | |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state.
+ * |[15:8] |EECP |EHCI Extended Capabilities Pointer (EECP)
+ * | | |0 = No extended capabilities are implemented.
+ * @var HSUSBH_T::UCMDR
+ * Offset: 0x20 USB Command Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RUN |Run/Stop (R/W)
+ * | | |When set to a 1, the Host Controller proceeds with execution of the schedule
+ * | | |The Host Controller continues execution as long as this bit is set to a 1
+ * | | |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts
+ * | | |The Host Controller must halt within 16 micro-frames after software clears the Run bit
+ * | | |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state
+ * | | |Software must not write a one to this field unless the host controller is in the Halted state (i.e.
+ * | | |HCHalted in the USBSTS register is a one)
+ * | | |Doing so will yield undefined results.
+ * | | |0 = Stop.
+ * | | |1 = Run.
+ * |[1] |HCRST |Host Controller Reset (HCRESET) (R/W)
+ * | | |This control bit is used by software to reset the host controller
+ * | | |The effects of this on Root Hub registers are similar to a Chip Hardware Reset.
+ * | | |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc
+ * | | |to their initial value
+ * | | |Any transaction currently in progress on USB is immediately terminated
+ * | | |A USB reset is not driven on downstream ports.
+ * | | |All operational registers, including port registers and port state machines are set to their initial values
+ * | | |Port ownership reverts to the companion host controller(s), with the side effects
+ * | | |Software must reinitialize the host controller in order to return the host controller to an operational state.
+ * | | |This bit is set to zero by the Host Controller when the reset process is complete
+ * | | |Software cannot terminate the reset process early by writing a zero to this register.
+ * | | |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero
+ * | | |Attempting to reset an actively running host controller will result in undefined behavior.
+ * |[3:2] |FLSZ |Frame List Size (R/W or RO)
+ * | | |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one
+ * | | |This field specifies the size of the frame list
+ * | | |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index
+ * | | |Values mean:
+ * | | |00 = 1024 elements (4096 bytes) Default value.
+ * | | |01 = 512 elements (2048 bytes).
+ * | | |10 = 256 elements (1024 bytes) u2013 for resource-constrained environment.
+ * | | |11 = Reserved.
+ * |[4] |PSEN |Periodic Schedule Enable (R/W)
+ * | | |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean:
+ * | | |0 = Do not process the Periodic Schedule.
+ * | | |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
+ * |[5] |ASEN |Asynchronous Schedule Enable (R/W)
+ * | | |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean:
+ * | | |0 = Do not process the Asynchronous Schedule.
+ * | | |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
+ * |[6] |IAAD |Interrupt on Asynchronous Advance Doorbell (R/W)
+ * | | |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule
+ * | | |Software must write a 1 to this bit to ring the doorbell.
+ * | | |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register
+ * | | |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.
+ * | | |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one.
+ * | | |Software should not write a one to this bit when the asynchronous schedule is disabled
+ * | | |Doing so will yield undefined results.
+ * |[23:16] |ITC |Interrupt Threshold Control (R/W)
+ * | | |This field is used by system software to select the maximum rate at which the host controller will issue interrupts
+ * | | |The only valid values are defined below
+ * | | |If software writes an invalid value to this register, the results are undefined
+ * | | |Value Maximum Interrupt Interval
+ * | | |0x00 = Reserved.
+ * | | |0x01 = 1 micro-frame.
+ * | | |0x02 = 2 micro-frames.
+ * | | |0x04 = 4 micro-frames.
+ * | | |0x08 = 8 micro-frames (default, equates to 1 ms).
+ * | | |0x10 = 16 micro-frames (2 ms).
+ * | | |0x20 = 32 micro-frames (4 ms).
+ * | | |0x40 = 64 micro-frames (8 ms).
+ * | | |Any other value in this register yields undefined results.
+ * | | |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior.
+ * @var HSUSBH_T::USTSR
+ * Offset: 0x24 USB Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |USBINT |USB Interrupt (USBINT) (R/WC)
+ * | | |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set.
+ * | | |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes).
+ * |[1] |UERRINT |USB Error Interrupt (USBERRINT) (R/WC)
+ * | | |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow)
+ * | | |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set.
+ * |[2] |PCD |Port Change Detect (R/WC)
+ * | | |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port
+ * | | |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit.
+ * | | |This bit is allowed to be maintained in the Auxiliary power well
+ * | | |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change).
+ * |[3] |FLR |Frame List Rollover (R/WC)
+ * | | |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero
+ * | | |The exact value at which the rollover occurs depends on the frame list size
+ * | | |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles
+ * | | |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles.
+ * |[4] |HSERR |Host System Error (R/WC)
+ * | | |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module.
+ * |[5] |IAA |Interrupt on Asynchronous Advance (R/WC)
+ * | | |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register
+ * | | |This status bit indicates the assertion of that interrupt source.
+ * |[12] |HCHalted |HCHalted (RO)
+ * | | |This bit is a zero whenever the Run/Stop bit is a one
+ * | | |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g.
+ * | | |internal error).
+ * |[13] |RECLA |Reclamation (RO)
+ * | | |This is a read-only status bit, which is used to detect an empty asynchronous schedule.
+ * |[14] |PSS |Periodic Schedule Status (RO)
+ * | | |The bit reports the current real status of the Periodic Schedule
+ * | | |If this bit is a zero then the status of the Periodic Schedule is disabled
+ * | | |If this bit is a one then the status of the Periodic Schedule is enabled
+ * | | |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register
+ * | | |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).
+ * |[15] |ASS |Asynchronous Schedule Status (RO)
+ * | | |The bit reports the current real status of the Asynchronous Schedule
+ * | | |If this bit is a zero then the status of them Asynchronous Schedule is disabled
+ * | | |If this bit is a one then the status of the Asynchronous Schedule is enabled
+ * | | |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register
+ * | | |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
+ * @var HSUSBH_T::UIENR
+ * Offset: 0x28 USB Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |USBIEN |USB Interrupt Enable or Disable Bit
+ * | | |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
+ * | | |The interrupt is acknowledged by software clearing the USBINT bit.
+ * | | |0 = USB interrupt Disabled.
+ * | | |1 = USB interrupt Enabled.
+ * |[1] |UERRIEN |USB Error Interrupt Enable or Disable Bit
+ * | | |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold
+ * | | |The interrupt is acknowledged by software clearing the USBERRINT bit.
+ * | | |0 = USB Error interrupt Disabled.
+ * | | |1 = USB Error interrupt Enabled.
+ * |[2] |PCIEN |Port Change Interrupt Enable or Disable Bit
+ * | | |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt
+ * | | |The interrupt is acknowledged by software clearing the Port Change Detect bit.
+ * | | |0 = Port Change interrupt Disabled.
+ * | | |1 = Port Change interrupt Enabled.
+ * |[3] |FLREN |Frame List Rollover Enable or Disable Bit
+ * | | |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt
+ * | | |The interrupt is acknowledged by software clearing the Frame List Rollover bit.
+ * | | |0 = Frame List Rollover interrupt Disabled.
+ * | | |1 = Frame List Rollover interrupt Enabled.
+ * |[4] |HSERREN |Host System Error Enable or Disable Bit
+ * | | |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt
+ * | | |The interrupt is acknowledged by software clearing the Host System Error bit.
+ * | | |0 = Host System Error interrupt Disabled.
+ * | | |1 = Host System Error interrupt Enabled.
+ * |[5] |IAAEN |Interrupt on Asynchronous Advance Enable or Disable Bit
+ * | | |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
+ * | | |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit.
+ * | | |0 = Interrupt on Asynchronous Advance Disabled.
+ * | | |1 = Interrupt on Asynchronous Advance Enabled.
+ * @var HSUSBH_T::UFINDR
+ * Offset: 0x2C USB Frame Index Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[13:0] |FI |Frame Index
+ * | | |The value in this register increment at the end of each time frame (e.g.
+ * | | |micro-frame)
+ * | | |Bits [N:3] are used for the Frame List current index
+ * | | |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index
+ * | | |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register.
+ * | | |FLSZ (UCMDR[3:2] Number Elements N
+ * | | |0x0 1024 12
+ * | | |0x1 512 11
+ * | | |0x2 256 10
+ * | | |0x3 Reserved
+ * @var HSUSBH_T::UPFLBAR
+ * Offset: 0x34 USB Periodic Frame List Base Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:12] |BADDR |Base Address
+ * | | |These bits correspond to memory address signals [31:12], respectively.
+ * @var HSUSBH_T::UCALAR
+ * Offset: 0x38 USB Current Asynchronous List Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:5] |LPL |Link Pointer Low (LPL)
+ * | | |These bits correspond to memory address signals [31:5], respectively
+ * | | |This field may only reference a Queue Head (QH).
+ * @var HSUSBH_T::UASSTR
+ * Offset: 0x3C USB Asynchronous Schedule Sleep Timer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |ASSTMR |Asynchronous Schedule Sleep Timer
+ * | | |This field defines the AsyncSchedSleepTime of EHCI spec.
+ * | | |The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty.
+ * | | |The default value of this timer is 12'hBD6
+ * | | |Because this timer is implemented in UTMI clock (30MHz) domain, the default sleeping time will be about 100us.
+ * @var HSUSBH_T::UCFGR
+ * Offset: 0x60 USB Configure Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CF |Configure Flag (CF)
+ * | | |Host software sets this bit as the last action in its process of configuring the Host Controller
+ * | | |This bit controls the default port-routing control logic
+ * | | |Bit values and side-effects are listed below.
+ * | | |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller.
+ * | | |1 = Port routing control logic default-routes all ports to this host controller.
+ * @var HSUSBH_T::UPSCR[2]
+ * Offset: 0x64~0x68 USB Port 0~1 Status and Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CCS |Current Connect Status (RO)
+ * | | |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
+ * | | |This field is zero if Port Power is zero.
+ * | | |0 = No device is present.
+ * | | |1 = Device is present on port.
+ * |[1] |CSC |Connect Status Change (R/W)
+ * | | |Indicates a change has occurred in the port's Current Connect Status
+ * | | |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change
+ * | | |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it.
+ * | | |This field is zero if Port Power is zero.
+ * | | |0 = No change.
+ * | | |1 = Change in Current Connect Status.
+ * |[2] |PE |Port Enabled/Disabled (R/W)
+ * | | |Ports can only be enabled by the host controller as a part of the reset and enable
+ * | | |Software cannot enable a port by writing a one to this field
+ * | | |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device.
+ * | | |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software
+ * | | |Note that the bit status does not change until the port state actually changes
+ * | | |There may be a delay in disabling or enabling a port due to other host controller and bus events.
+ * | | |When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset.
+ * | | |This field is zero if Port Power is zero.
+ * | | |0 = Port Disabled.
+ * | | |1 = Port Enabled.
+ * |[3] |PEC |Port Enable/Disable Change (R/WC)
+ * | | |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error)
+ * | | |Software clears this bit by writing a 1 to it.
+ * | | |This field is zero if Port Power is zero.
+ * | | |0 = No change.
+ * | | |1 = Port enabled/disabled status has changed.
+ * |[4] |OCA |Over-current Active (RO)
+ * | | |This bit will automatically transition from a one to a zero when the over current condition is removed.
+ * | | |0 = This port does not have an over-current condition.
+ * | | |1 = This port currently has an over-current condition.
+ * |[5] |OCC |Over-current Change (R/WC)
+ * | | |1 = This bit gets set to a one when there is a change to Over-current Active
+ * | | |Software clears this bit by writing a one to this bit position.
+ * |[6] |FPR |Force Port Resume (R/W)
+ * | | |This functionality defined for manipulating this bit depends on the value of the Suspend bit
+ * | | |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined.
+ * | | |Software sets this bit to a 1 to drive resume signaling
+ * | | |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state
+ * | | |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one
+ * | | |If software sets this bit to a one, the host controller must not set the Port Change Detect bit.
+ * | | |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0
+ * | | |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one
+ * | | |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed
+ * | | |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle)
+ * | | |This bit will remain a one until the port has switched to the high-speed idle
+ * | | |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.
+ * | | |This field is zero if Port Power is zero.
+ * | | |0 = No resume (K-state) detected/driven on port.
+ * | | |1 = Resume detected/driven on port.
+ * |[7] |SUSPEND |Suspend (R/W)
+ * | | |Port Enabled Bit and Suspend bit of this register define the port states as follows:
+ * | | |Port enable is 0 and suspend is 0 = Disable.
+ * | | |Port enable is 0 and suspend is 1 = Disable.
+ * | | |Port enable is 1 and suspend is 0 = Enable.
+ * | | |Port enable is 1 and suspend is 1 = Suspend.
+ * | | |When in suspend state, downstream propagation of data is blocked on this port, except for port reset
+ * | | |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1
+ * | | |In the suspend state, the port is sensitive to resume detection
+ * | | |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.
+ * | | |A write of zero to this bit is ignored by the host controller
+ * | | |The host controller will unconditionally set this bit to a zero when:
+ * | | |Software sets the Force Port Resume bit to a zero (from a one).
+ * | | |Software sets the Port Reset bit to a one (from a zero).
+ * | | |If host software sets this bit to a one when the port is not enabled (i.e.
+ * | | |Port enabled bit is a zero) the results are undefined.
+ * | | |This field is zero if Port Power is zero.
+ * | | |0 = Port not in suspend state.
+ * | | |1 = Port in suspend state.
+ * |[8] |PRST |Port Reset (R/W)
+ * | | |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started
+ * | | |Software writes a zero to this bit to terminate the bus reset sequence
+ * | | |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes
+ * | | |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit.
+ * | | |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero
+ * | | |The bit status will not read as a zero until after the reset has completed
+ * | | |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g.
+ * | | |set the Port Enable bit to a one)
+ * | | |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero
+ * | | |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero.
+ * | | |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit
+ * | | |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one.
+ * | | |This field is zero if Port Power is zero.
+ * | | |0 = Port is not in Reset.
+ * | | |1 = Port is in Reset.
+ * |[11:10] |LSTS |Line Status (RO)
+ * | | |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines
+ * | | |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence
+ * | | |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one.
+ * | | |The encoding of the bits are:
+ * | | |Bits[11:10] USB State Interpretation
+ * | | |00 = SE0 Not Low-speed device, perform EHCI reset.
+ * | | |01 = K-state Low-speed device, release ownership of port.
+ * | | |10 = J-state Not Low-speed device, perform EHCI reset.
+ * | | |11 = Undefined Not Low-speed device, perform EHCI reset.
+ * | | |This value of this field is undefined if Port Power is zero.
+ * |[12] |PP |Port Power (PP)
+ * | | |Host controller has port power control switches
+ * | | |This bit represents the Current setting of the switch (0 = off, 1 = on)
+ * | | |When power is not available on a port (i.e.
+ * | | |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc.
+ * | | |When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port).
+ * |[13] |PO |Port Owner (R/W)
+ * | | |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition
+ * | | |This bit unconditionally goes to 1 whenever the Configured bit is zero.
+ * | | |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device)
+ * | | |Software writes a one to this bit when the attached device is not a high-speed device
+ * | | |A one in this bit means that a companion host controller owns and controls the port.
+ * |[19:16] |PTC |Port Test Control (R/W)
+ * | | |When this field is zero, the port is NOT operating in a test mode
+ * | | |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value
+ * | | |The encoding of the test mode bits are (0x6 ~ 0xF are reserved):
+ * | | |Bits Test Mode
+ * | | |0x0 = Test mode not enabled.
+ * | | |0x1 = Test J_STATE.
+ * | | |0x2 = Test K_STATE.
+ * | | |0x3 = Test SE0_NAK.
+ * | | |0x4 = Test Packet.
+ * | | |0x5 = Test FORCE_ENABLE.
+ * @var HSUSBH_T::USBPCR0
+ * Offset: 0xC4 USB PHY 0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8] |SUSPEND |Suspend Assertion
+ * | | |This bit controls the suspend mode of USB PHY 0.
+ * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.
+ * | | |This bit is 1'b0 in default
+ * | | |This means the USB PHY 0 is suspended in default
+ * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
+ * | | |0 = USB PHY 0 was suspended.
+ * | | |1 = USB PHY 0 was not suspended.
+ * |[11] |CLKVALID |UTMI Clock Valid
+ * | | |This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready
+ * | | |S/W program must prevent to write other control registers before this UTMI clock valid flag is active.
+ * | | |0 = UTMI clock is not valid.
+ * | | |1 = UTMI clock is valid.
+ * @var HSUSBH_T::USBPCR1
+ * Offset: 0xC8 USB PHY 1 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8] |SUSPEND |Suspend Assertion
+ * | | |This bit controls the suspend mode of USB PHY 1.
+ * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.
+ * | | |This bit is 1'b0 in default
+ * | | |This means the USB PHY 0 is suspended in default
+ * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
+ * | | |0 = USB PHY 1 was suspended.
+ * | | |1 = USB PHY 1 was not suspended.
+ */
+ __I uint32_t EHCVNR; /*!< [0x0000] EHCI Version Number Register */
+ __I uint32_t EHCSPR; /*!< [0x0004] EHCI Structural Parameters Register */
+ __I uint32_t EHCCPR; /*!< [0x0008] EHCI Capability Parameters Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t UCMDR; /*!< [0x0020] USB Command Register */
+ __IO uint32_t USTSR; /*!< [0x0024] USB Status Register */
+ __IO uint32_t UIENR; /*!< [0x0028] USB Interrupt Enable Register */
+ __IO uint32_t UFINDR; /*!< [0x002c] USB Frame Index Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t UPFLBAR; /*!< [0x0034] USB Periodic Frame List Base Address Register */
+ __IO uint32_t UCALAR; /*!< [0x0038] USB Current Asynchronous List Address Register */
+ __IO uint32_t UASSTR; /*!< [0x003c] USB Asynchronous Schedule Sleep Timer Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[8];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t UCFGR; /*!< [0x0060] USB Configure Flag Register */
+ __IO uint32_t UPSCR[2]; /*!< [0x0064] ~ [0x0068] USB Port 0 & 1 Status and Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[22];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t USBPCR0; /*!< [0x00c4] USB PHY 0 Control Register */
+ __IO uint32_t USBPCR1; /*!< [0x00c8] USB PHY 1 Control Register */
+
+} HSUSBH_T;
+
+/**
+ @addtogroup HSUSBH_CONST HSUSBH Bit Field Definition
+ Constant Definitions for HSUSBH Controller
+@{ */
+
+#define HSUSBH_EHCVNR_CRLEN_Pos (0) /*!< HSUSBH_T::EHCVNR: CRLEN Position */
+#define HSUSBH_EHCVNR_CRLEN_Msk (0xfful << HSUSBH_EHCVNR_CRLEN_Pos) /*!< HSUSBH_T::EHCVNR: CRLEN Mask */
+
+#define HSUSBH_EHCVNR_VERSION_Pos (16) /*!< HSUSBH_T::EHCVNR: VERSION Position */
+#define HSUSBH_EHCVNR_VERSION_Msk (0xfffful << HSUSBH_EHCVNR_VERSION_Pos) /*!< HSUSBH_T::EHCVNR: VERSION Mask */
+
+#define HSUSBH_EHCSPR_N_PORTS_Pos (0) /*!< HSUSBH_T::EHCSPR: N_PORTS Position */
+#define HSUSBH_EHCSPR_N_PORTS_Msk (0xful << HSUSBH_EHCSPR_N_PORTS_Pos) /*!< HSUSBH_T::EHCSPR: N_PORTS Mask */
+
+#define HSUSBH_EHCSPR_PPC_Pos (4) /*!< HSUSBH_T::EHCSPR: PPC Position */
+#define HSUSBH_EHCSPR_PPC_Msk (0x1ul << HSUSBH_EHCSPR_PPC_Pos) /*!< HSUSBH_T::EHCSPR: PPC Mask */
+
+#define HSUSBH_EHCSPR_N_PCC_Pos (8) /*!< HSUSBH_T::EHCSPR: N_PCC Position */
+#define HSUSBH_EHCSPR_N_PCC_Msk (0xful << HSUSBH_EHCSPR_N_PCC_Pos) /*!< HSUSBH_T::EHCSPR: N_PCC Mask */
+
+#define HSUSBH_EHCSPR_N_CC_Pos (12) /*!< HSUSBH_T::EHCSPR: N_CC Position */
+#define HSUSBH_EHCSPR_N_CC_Msk (0xful << HSUSBH_EHCSPR_N_CC_Pos) /*!< HSUSBH_T::EHCSPR: N_CC Mask */
+
+#define HSUSBH_EHCCPR_AC64_Pos (0) /*!< HSUSBH_T::EHCCPR: AC64 Position */
+#define HSUSBH_EHCCPR_AC64_Msk (0x1ul << HSUSBH_EHCCPR_AC64_Pos) /*!< HSUSBH_T::EHCCPR: AC64 Mask */
+
+#define HSUSBH_EHCCPR_PFLF_Pos (1) /*!< HSUSBH_T::EHCCPR: PFLF Position */
+#define HSUSBH_EHCCPR_PFLF_Msk (0x1ul << HSUSBH_EHCCPR_PFLF_Pos) /*!< HSUSBH_T::EHCCPR: PFLF Mask */
+
+#define HSUSBH_EHCCPR_ASPC_Pos (2) /*!< HSUSBH_T::EHCCPR: ASPC Position */
+#define HSUSBH_EHCCPR_ASPC_Msk (0x1ul << HSUSBH_EHCCPR_ASPC_Pos) /*!< HSUSBH_T::EHCCPR: ASPC Mask */
+
+#define HSUSBH_EHCCPR_IST_Pos (4) /*!< HSUSBH_T::EHCCPR: IST Position */
+#define HSUSBH_EHCCPR_IST_Msk (0xful << HSUSBH_EHCCPR_IST_Pos) /*!< HSUSBH_T::EHCCPR: IST Mask */
+
+#define HSUSBH_EHCCPR_EECP_Pos (8) /*!< HSUSBH_T::EHCCPR: EECP Position */
+#define HSUSBH_EHCCPR_EECP_Msk (0xfful << HSUSBH_EHCCPR_EECP_Pos) /*!< HSUSBH_T::EHCCPR: EECP Mask */
+
+#define HSUSBH_UCMDR_RUN_Pos (0) /*!< HSUSBH_T::UCMDR: RUN Position */
+#define HSUSBH_UCMDR_RUN_Msk (0x1ul << HSUSBH_UCMDR_RUN_Pos) /*!< HSUSBH_T::UCMDR: RUN Mask */
+
+#define HSUSBH_UCMDR_HCRST_Pos (1) /*!< HSUSBH_T::UCMDR: HCRST Position */
+#define HSUSBH_UCMDR_HCRST_Msk (0x1ul << HSUSBH_UCMDR_HCRST_Pos) /*!< HSUSBH_T::UCMDR: HCRST Mask */
+
+#define HSUSBH_UCMDR_FLSZ_Pos (2) /*!< HSUSBH_T::UCMDR: FLSZ Position */
+#define HSUSBH_UCMDR_FLSZ_Msk (0x3ul << HSUSBH_UCMDR_FLSZ_Pos) /*!< HSUSBH_T::UCMDR: FLSZ Mask */
+
+#define HSUSBH_UCMDR_PSEN_Pos (4) /*!< HSUSBH_T::UCMDR: PSEN Position */
+#define HSUSBH_UCMDR_PSEN_Msk (0x1ul << HSUSBH_UCMDR_PSEN_Pos) /*!< HSUSBH_T::UCMDR: PSEN Mask */
+
+#define HSUSBH_UCMDR_ASEN_Pos (5) /*!< HSUSBH_T::UCMDR: ASEN Position */
+#define HSUSBH_UCMDR_ASEN_Msk (0x1ul << HSUSBH_UCMDR_ASEN_Pos) /*!< HSUSBH_T::UCMDR: ASEN Mask */
+
+#define HSUSBH_UCMDR_IAAD_Pos (6) /*!< HSUSBH_T::UCMDR: IAAD Position */
+#define HSUSBH_UCMDR_IAAD_Msk (0x1ul << HSUSBH_UCMDR_IAAD_Pos) /*!< HSUSBH_T::UCMDR: IAAD Mask */
+
+#define HSUSBH_UCMDR_ITC_Pos (16) /*!< HSUSBH_T::UCMDR: ITC Position */
+#define HSUSBH_UCMDR_ITC_Msk (0xfful << HSUSBH_UCMDR_ITC_Pos) /*!< HSUSBH_T::UCMDR: ITC Mask */
+
+#define HSUSBH_USTSR_USBINT_Pos (0) /*!< HSUSBH_T::USTSR: USBINT Position */
+#define HSUSBH_USTSR_USBINT_Msk (0x1ul << HSUSBH_USTSR_USBINT_Pos) /*!< HSUSBH_T::USTSR: USBINT Mask */
+
+#define HSUSBH_USTSR_UERRINT_Pos (1) /*!< HSUSBH_T::USTSR: UERRINT Position */
+#define HSUSBH_USTSR_UERRINT_Msk (0x1ul << HSUSBH_USTSR_UERRINT_Pos) /*!< HSUSBH_T::USTSR: UERRINT Mask */
+
+#define HSUSBH_USTSR_PCD_Pos (2) /*!< HSUSBH_T::USTSR: PCD Position */
+#define HSUSBH_USTSR_PCD_Msk (0x1ul << HSUSBH_USTSR_PCD_Pos) /*!< HSUSBH_T::USTSR: PCD Mask */
+
+#define HSUSBH_USTSR_FLR_Pos (3) /*!< HSUSBH_T::USTSR: FLR Position */
+#define HSUSBH_USTSR_FLR_Msk (0x1ul << HSUSBH_USTSR_FLR_Pos) /*!< HSUSBH_T::USTSR: FLR Mask */
+
+#define HSUSBH_USTSR_HSERR_Pos (4) /*!< HSUSBH_T::USTSR: HSERR Position */
+#define HSUSBH_USTSR_HSERR_Msk (0x1ul << HSUSBH_USTSR_HSERR_Pos) /*!< HSUSBH_T::USTSR: HSERR Mask */
+
+#define HSUSBH_USTSR_IAA_Pos (5) /*!< HSUSBH_T::USTSR: IAA Position */
+#define HSUSBH_USTSR_IAA_Msk (0x1ul << HSUSBH_USTSR_IAA_Pos) /*!< HSUSBH_T::USTSR: IAA Mask */
+
+#define HSUSBH_USTSR_HCHalted_Pos (12) /*!< HSUSBH_T::USTSR: HCHalted Position */
+#define HSUSBH_USTSR_HCHalted_Msk (0x1ul << HSUSBH_USTSR_HCHalted_Pos) /*!< HSUSBH_T::USTSR: HCHalted Mask */
+
+#define HSUSBH_USTSR_RECLA_Pos (13) /*!< HSUSBH_T::USTSR: RECLA Position */
+#define HSUSBH_USTSR_RECLA_Msk (0x1ul << HSUSBH_USTSR_RECLA_Pos) /*!< HSUSBH_T::USTSR: RECLA Mask */
+
+#define HSUSBH_USTSR_PSS_Pos (14) /*!< HSUSBH_T::USTSR: PSS Position */
+#define HSUSBH_USTSR_PSS_Msk (0x1ul << HSUSBH_USTSR_PSS_Pos) /*!< HSUSBH_T::USTSR: PSS Mask */
+
+#define HSUSBH_USTSR_ASS_Pos (15) /*!< HSUSBH_T::USTSR: ASS Position */
+#define HSUSBH_USTSR_ASS_Msk (0x1ul << HSUSBH_USTSR_ASS_Pos) /*!< HSUSBH_T::USTSR: ASS Mask */
+
+#define HSUSBH_UIENR_USBIEN_Pos (0) /*!< HSUSBH_T::UIENR: USBIEN Position */
+#define HSUSBH_UIENR_USBIEN_Msk (0x1ul << HSUSBH_UIENR_USBIEN_Pos) /*!< HSUSBH_T::UIENR: USBIEN Mask */
+
+#define HSUSBH_UIENR_UERRIEN_Pos (1) /*!< HSUSBH_T::UIENR: UERRIEN Position */
+#define HSUSBH_UIENR_UERRIEN_Msk (0x1ul << HSUSBH_UIENR_UERRIEN_Pos) /*!< HSUSBH_T::UIENR: UERRIEN Mask */
+
+#define HSUSBH_UIENR_PCIEN_Pos (2) /*!< HSUSBH_T::UIENR: PCIEN Position */
+#define HSUSBH_UIENR_PCIEN_Msk (0x1ul << HSUSBH_UIENR_PCIEN_Pos) /*!< HSUSBH_T::UIENR: PCIEN Mask */
+
+#define HSUSBH_UIENR_FLREN_Pos (3) /*!< HSUSBH_T::UIENR: FLREN Position */
+#define HSUSBH_UIENR_FLREN_Msk (0x1ul << HSUSBH_UIENR_FLREN_Pos) /*!< HSUSBH_T::UIENR: FLREN Mask */
+
+#define HSUSBH_UIENR_HSERREN_Pos (4) /*!< HSUSBH_T::UIENR: HSERREN Position */
+#define HSUSBH_UIENR_HSERREN_Msk (0x1ul << HSUSBH_UIENR_HSERREN_Pos) /*!< HSUSBH_T::UIENR: HSERREN Mask */
+
+#define HSUSBH_UIENR_IAAEN_Pos (5) /*!< HSUSBH_T::UIENR: IAAEN Position */
+#define HSUSBH_UIENR_IAAEN_Msk (0x1ul << HSUSBH_UIENR_IAAEN_Pos) /*!< HSUSBH_T::UIENR: IAAEN Mask */
+
+#define HSUSBH_UFINDR_FI_Pos (0) /*!< HSUSBH_T::UFINDR: FI Position */
+#define HSUSBH_UFINDR_FI_Msk (0x3ffful << HSUSBH_UFINDR_FI_Pos) /*!< HSUSBH_T::UFINDR: FI Mask */
+
+#define HSUSBH_UPFLBAR_BADDR_Pos (12) /*!< HSUSBH_T::UPFLBAR: BADDR Position */
+#define HSUSBH_UPFLBAR_BADDR_Msk (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos) /*!< HSUSBH_T::UPFLBAR: BADDR Mask */
+
+#define HSUSBH_UCALAR_LPL_Pos (5) /*!< HSUSBH_T::UCALAR: LPL Position */
+#define HSUSBH_UCALAR_LPL_Msk (0x7fffffful << HSUSBH_UCALAR_LPL_Pos) /*!< HSUSBH_T::UCALAR: LPL Mask */
+
+#define HSUSBH_UASSTR_ASSTMR_Pos (0) /*!< HSUSBH_T::UASSTR: ASSTMR Position */
+#define HSUSBH_UASSTR_ASSTMR_Msk (0xffful << HSUSBH_UASSTR_ASSTMR_Pos) /*!< HSUSBH_T::UASSTR: ASSTMR Mask */
+
+#define HSUSBH_UCFGR_CF_Pos (0) /*!< HSUSBH_T::UCFGR: CF Position */
+#define HSUSBH_UCFGR_CF_Msk (0x1ul << HSUSBH_UCFGR_CF_Pos) /*!< HSUSBH_T::UCFGR: CF Mask */
+
+#define HSUSBH_UPSCR_CCS_Pos (0) /*!< HSUSBH_T::UPSCR[2]: CCS Position */
+#define HSUSBH_UPSCR_CCS_Msk (0x1ul << HSUSBH_UPSCR_CCS_Pos) /*!< HSUSBH_T::UPSCR[2]: CCS Mask */
+
+#define HSUSBH_UPSCR_CSC_Pos (1) /*!< HSUSBH_T::UPSCR[2]: CSC Position */
+#define HSUSBH_UPSCR_CSC_Msk (0x1ul << HSUSBH_UPSCR_CSC_Pos) /*!< HSUSBH_T::UPSCR[2]: CSC Mask */
+
+#define HSUSBH_UPSCR_PE_Pos (2) /*!< HSUSBH_T::UPSCR[2]: PE Position */
+#define HSUSBH_UPSCR_PE_Msk (0x1ul << HSUSBH_UPSCR_PE_Pos) /*!< HSUSBH_T::UPSCR[2]: PE Mask */
+
+#define HSUSBH_UPSCR_PEC_Pos (3) /*!< HSUSBH_T::UPSCR[2]: PEC Position */
+#define HSUSBH_UPSCR_PEC_Msk (0x1ul << HSUSBH_UPSCR_PEC_Pos) /*!< HSUSBH_T::UPSCR[2]: PEC Mask */
+
+#define HSUSBH_UPSCR_OCA_Pos (4) /*!< HSUSBH_T::UPSCR[2]: OCA Position */
+#define HSUSBH_UPSCR_OCA_Msk (0x1ul << HSUSBH_UPSCR_OCA_Pos) /*!< HSUSBH_T::UPSCR[2]: OCA Mask */
+
+#define HSUSBH_UPSCR_OCC_Pos (5) /*!< HSUSBH_T::UPSCR[2]: OCC Position */
+#define HSUSBH_UPSCR_OCC_Msk (0x1ul << HSUSBH_UPSCR_OCC_Pos) /*!< HSUSBH_T::UPSCR[2]: OCC Mask */
+
+#define HSUSBH_UPSCR_FPR_Pos (6) /*!< HSUSBH_T::UPSCR[2]: FPR Position */
+#define HSUSBH_UPSCR_FPR_Msk (0x1ul << HSUSBH_UPSCR_FPR_Pos) /*!< HSUSBH_T::UPSCR[2]: FPR Mask */
+
+#define HSUSBH_UPSCR_SUSPEND_Pos (7) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Position */
+#define HSUSBH_UPSCR_SUSPEND_Msk (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Mask */
+
+#define HSUSBH_UPSCR_PRST_Pos (8) /*!< HSUSBH_T::UPSCR[2]: PRST Position */
+#define HSUSBH_UPSCR_PRST_Msk (0x1ul << HSUSBH_UPSCR_PRST_Pos) /*!< HSUSBH_T::UPSCR[2]: PRST Mask */
+
+#define HSUSBH_UPSCR_LSTS_Pos (10) /*!< HSUSBH_T::UPSCR[2]: LSTS Position */
+#define HSUSBH_UPSCR_LSTS_Msk (0x3ul << HSUSBH_UPSCR_LSTS_Pos) /*!< HSUSBH_T::UPSCR[2]: LSTS Mask */
+
+#define HSUSBH_UPSCR_PP_Pos (12) /*!< HSUSBH_T::UPSCR[2]: PP Position */
+#define HSUSBH_UPSCR_PP_Msk (0x1ul << HSUSBH_UPSCR_PP_Pos) /*!< HSUSBH_T::UPSCR[2]: PP Mask */
+
+#define HSUSBH_UPSCR_PO_Pos (13) /*!< HSUSBH_T::UPSCR[2]: PO Position */
+#define HSUSBH_UPSCR_PO_Msk (0x1ul << HSUSBH_UPSCR_PO_Pos) /*!< HSUSBH_T::UPSCR[2]: PO Mask */
+
+#define HSUSBH_UPSCR_PTC_Pos (16) /*!< HSUSBH_T::UPSCR[2]: PTC Position */
+#define HSUSBH_UPSCR_PTC_Msk (0xful << HSUSBH_UPSCR_PTC_Pos) /*!< HSUSBH_T::UPSCR[2]: PTC Mask */
+
+#define HSUSBH_USBPCR0_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR0: SUSPEND Position */
+#define HSUSBH_USBPCR0_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR0: SUSPEND Mask */
+
+#define HSUSBH_USBPCR0_CLKVALID_Pos (11) /*!< HSUSBH_T::USBPCR0: CLKVALID Position */
+#define HSUSBH_USBPCR0_CLKVALID_Msk (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos) /*!< HSUSBH_T::USBPCR0: CLKVALID Mask */
+
+#define HSUSBH_USBPCR1_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR1: SUSPEND Position */
+#define HSUSBH_USBPCR1_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR1: SUSPEND Mask */
+
+/**@}*/ /* HSUSBH_CONST */
+/**@}*/ /* end of HSUSBH register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __HSUSBH_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2c_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2c_reg.h
new file mode 100644
index 00000000000..adbd03fa572
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2c_reg.h
@@ -0,0 +1,725 @@
+/**************************************************************************//**
+ * @file i2c_reg.h
+ * @version V1.00
+ * @brief I2C register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __I2C_REG_H__
+#define __I2C_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup I2C Inter-IC Bus Controller(I2C)
+ Memory Mapped Structure for I2C Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var I2C_T::CTL0
+ * Offset: 0x00 I2C Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2] |AA |Assert Acknowledge Control
+ * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
+ * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line
+ * |[3] |SI |I2C Interrupt Flag
+ * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware
+ * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested
+ * | | |SI must be cleared by software
+ * | | |Clear SI by writing 1 to this bit.
+ * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
+ * |[4] |STO |I2C STOP Control
+ * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected
+ * | | |This bit will be cleared by hardware automatically.
+ * |[5] |STA |I2C START Control
+ * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
+ * |[6] |I2CEN |I2C Controller Enable Bit
+ * | | |Set to enable I2C serial function controller
+ * | | |When I2CEN=1 the I2C serial function enable
+ * | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
+ * | | |0 = I2C controller Disabled.
+ * | | |1 = I2C controller Enabled.
+ * |[7] |INTEN |Enable Interrupt
+ * | | |0 = I2C interrupt Disabled.
+ * | | |1 = I2C interrupt Enabled.
+ * @var I2C_T::ADDR0
+ * Offset: 0x04 I2C Slave Address Register0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[10:1] |ADDR |I2C Address
+ * | | |The content of this register is irrelevant when I2C is in Master mode
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+ * | | |The I2C hardware will react if either of the address is matched.
+ * | | |Note: When software set 10'h000, the address can not be used.
+ * @var I2C_T::DAT
+ * Offset: 0x08 I2C Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DAT |I2C Data
+ * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
+ * @var I2C_T::STATUS0
+ * Offset: 0x0C I2C Status Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |STATUS |I2C Status
+ * | | |The three least significant bits are always 0
+ * | | |The five most significant bits contain the status code
+ * | | |There are 28 possible status codes
+ * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested
+ * | | |Others I2C_STATUS values correspond to defined I2C states
+ * | | |When each of these states is entered, a status interrupt is requested (SI = 1)
+ * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software
+ * | | |In addition, states 00H stands for a Bus Error
+ * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
+ * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
+ * @var I2C_T::CLKDIV
+ * Offset: 0x10 I2C Clock Divided Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |DIVIDER |I2C Clock Divided
+ * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
+ * | | |Note: The minimum value of I2C_CLKDIV is 4.
+ * @var I2C_T::TOCTL
+ * Offset: 0x14 I2C Time-out Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TOIF |Time-out Flag
+ * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
+ * | | |Note: Software can write 1 to clear this bit.
+ * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4
+ * | | |When Enabled, The time-out period is extend 4 times.
+ * | | |0 = Time-out period is extend 4 times Disabled.
+ * | | |1 = Time-out period is extend 4 times Enabled.
+ * |[2] |TOCEN |Time-out Counter Enable Bit
+ * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear
+ * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
+ * | | |0 = Time-out counter Disabled.
+ * | | |1 = Time-out counter Enabled.
+ * @var I2C_T::ADDR1
+ * Offset: 0x18 I2C Slave Address Register1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[10:1] |ADDR |I2C Address
+ * | | |The content of this register is irrelevant when I2C is in Master mode
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+ * | | |The I2C hardware will react if either of the address is matched.
+ * | | |Note: When software set 10'h000, the address can not be used.
+ * @var I2C_T::ADDR2
+ * Offset: 0x1C I2C Slave Address Register2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[10:1] |ADDR |I2C Address
+ * | | |The content of this register is irrelevant when I2C is in Master mode
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+ * | | |The I2C hardware will react if either of the address is matched.
+ * | | |Note: When software set 10'h000, the address can not be used.
+ * @var I2C_T::ADDR3
+ * Offset: 0x20 I2C Slave Address Register3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[10:1] |ADDR |I2C Address
+ * | | |The content of this register is irrelevant when I2C is in Master mode
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+ * | | |The I2C hardware will react if either of the address is matched.
+ * | | |Note: When software set 10'h000, the address can not be used.
+ * @var I2C_T::ADDRMSK0
+ * Offset: 0x24 I2C Slave Address Mask Register0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[10:1] |ADDRMSK |I2C Address Mask
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * | | |I2C bus controllers support multiple address recognition with four address mask register
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * | | |Note: The wake-up function can not use address mask.
+ * @var I2C_T::ADDRMSK1
+ * Offset: 0x28 I2C Slave Address Mask Register1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[10:1] |ADDRMSK |I2C Address Mask
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * | | |I2C bus controllers support multiple address recognition with four address mask register
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * | | |Note: The wake-up function can not use address mask.
+ * @var I2C_T::ADDRMSK2
+ * Offset: 0x2C I2C Slave Address Mask Register2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[10:1] |ADDRMSK |I2C Address Mask
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * | | |I2C bus controllers support multiple address recognition with four address mask register
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * | | |Note: The wake-up function can not use address mask.
+ * @var I2C_T::ADDRMSK3
+ * Offset: 0x30 I2C Slave Address Mask Register3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[10:1] |ADDRMSK |I2C Address Mask
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * | | |I2C bus controllers support multiple address recognition with four address mask register
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * | | |Note: The wake-up function can not use address mask.
+ * @var I2C_T::WKCTL
+ * Offset: 0x3C I2C Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |I2C Wake-up Enable Bit
+ * | | |0 = I2C wake-up function Disabled.
+ * | | |1 = I2C wake-up function Enabled.
+ * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit
+ * | | |0 = I2C hold bus after wake-up.
+ * | | |1 = I2C don't hold bus after wake-up.
+ * | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received
+ * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
+ * @var I2C_T::WKSTS
+ * Offset: 0x40 I2C Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKIF |I2C Wake-up Flag
+ * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1
+ * | | |Software can write 1 to clear this bit.
+ * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
+ * | | |0 = The ACK bit cycle of address match frame isn't done.
+ * | | |1 = The ACK bit cycle of address match frame is done in power-down.
+ * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit.
+ * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
+ * | | |0 = Write command be record on the address match wakeup frame.
+ * | | |1 = Read command be record on the address match wakeup frame.
+ * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit.
+ * @var I2C_T::CTL1
+ * Offset: 0x44 I2C Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TXPDMAEN |PDMA Transmit Channel Available
+ * | | |0 = Transmit PDMA function disable.
+ * | | |1 = Transmit PDMA function enable.
+ * |[1] |RXPDMAEN |PDMA Receive Channel Available
+ * | | |0 = Receive PDMA function disable.
+ * | | |1 = Receive PDMA function enable.
+ * |[2] |PDMARST |PDMA Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the I2C request to PDMA.
+ * |[8] |PDMASTR |PDMA Stretch Bit
+ * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
+ * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared
+ * | | |(only master TX)
+ * |[9] |ADDR10EN |Address 10-bit Function Enable
+ * | | |0 = Address match 10-bit function is disabled.
+ * | | |1 = Address match 10-bit function is enabled.
+ * @var I2C_T::STATUS1
+ * Offset: 0x48 I2C Status Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADMAT0 |I2C Address 0 Match Status Register
+ * | | |When address 0 is matched, hardware will inform which address used
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.
+ * |[1] |ADMAT1 |I2C Address 1 Match Status Register
+ * | | |When address 1 is matched, hardware will inform which address used
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.
+ * |[2] |ADMAT2 |I2C Address 2 Match Status Register
+ * | | |When address 2 is matched, hardware will inform which address used
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.
+ * |[3] |ADMAT3 |I2C Address 3 Match Status Register
+ * | | |When address 3 is matched, hardware will inform which address used
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.
+ * |[8] |ONBUSY |On Bus Busy
+ * | | |Indicates that a communication is in progress on the bus
+ * | | |It is set by hardware when a START condition is detected
+ * | | |It is cleared by hardware when a STOP condition is detected.
+ * | | |0 = The bus is IDLE (both SCLK and SDA High).
+ * | | |1 = The bus is busy.
+ * | | |Note:This bit is read only.
+ * @var I2C_T::TMCTL
+ * Offset: 0x4C I2C Timing Configure Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |STCTL |Setup Time Configure Control Register
+ * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
+ * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK.
+ * | | |Note: Setup time setting should not make SCL output less than three PCLKs.
+ * |[24:16] |HTCTL |Hold Time Configure Control Register
+ * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
+ * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.
+ * @var I2C_T::BUSCTL
+ * Offset: 0x50 I2C Bus Management Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ACKMEN |Acknowledge Control by Manual
+ * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
+ * | | |0 = Slave byte control Disabled.
+ * | | |1 = Slave byte control Enabled
+ * | | |The 9th bit can response the ACK or NACK according the received data by user
+ * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
+ * | | |Note: If the BMDEN=1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
+ * |[1] |PECEN |Packet Error Checking Calculation Enable Bit
+ * | | |0 = Packet Error Checking Calculation Disabled.
+ * | | |1 = Packet Error Checking Calculation Enabled.
+ * | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation.
+ * |[2] |BMDEN |Bus Management Device Default Address Enable Bit
+ * | | |0 = Device default address Disable
+ * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
+ * | | |1 = Device default address Enabled
+ * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
+ * |[3] |BMHEN |Bus Management Host Enable Bit
+ * | | |0 = Host function Disabled.
+ * | | |1 = Host function Enabled.
+ * |[4] |ALERTEN |Bus Management Alert Enable Bit
+ * | | |Device Mode (BMHEN=0).
+ * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
+ * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
+ * | | |Host Mode (BMHEN=1).
+ * | | |0 = BM_ALERT pin not supported.
+ * | | |1 = BM_ALERT pin supported.
+ * |[5] |SCTLOSTS |Suspend/Control Data Output Status
+ * | | |0 = The output of SUSCON pin is low.
+ * | | |1 = The output of SUSCON pin is high.
+ * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit
+ * | | |0 = The SUSCON pin in input.
+ * | | |1 = The output enable is active on the SUSCON pin.
+ * |[7] |BUSEN |BUS Enable Bit
+ * | | |0 = The system management function is Disabled.
+ * | | |1 = The system management function is Enable.
+ * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
+ * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
+ * | | |0 = No PEC transfer.
+ * | | |1 = PEC transmission is requested.
+ * | | |Note: This bit has no effect in slave mode when ACKMEN=0.
+ * |[9] |TIDLE |Timer Check in Idle State
+ * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle
+ * | | |This bit is used to define which condition is enabled.
+ * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.
+ * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
+ * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
+ * |[10] |PECCLR |PEC Clear at Repeat Start
+ * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected
+ * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
+ * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
+ * | | |1 = The PEC calculation is cleared by "Repeat Start"" function is Enabled.
+ * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
+ * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1.
+ * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1.
+ * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
+ * | | |0 = Indicates the byte count done interrupt is Disabled.
+ * | | |1 = Indicates the byte count done interrupt is Enabled.
+ * | | |Note: This bit is used in PECEN=1.
+ * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit
+ * | | |0 = Indicates the PEC transfer done interrupt is Disabled.
+ * | | |1 = Indicates the PEC transfer done interrupt is Enabled.
+ * | | |Note: This bit is used in PECEN=1.
+ * @var I2C_T::BUSTCTL
+ * Offset: 0x54 I2C Bus Management Timer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSTOEN |Bus Time Out Enable Bit
+ * | | |0 = Indicates the bus clock low time-out detection is Disabled.
+ * | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1)
+ * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
+ * | | |0 = Indicates the cumulative clock low time-out detection is Disabled.
+ * | | |1 = Indicates the cumulative clock low time-out detection is Enabled.
+ * | | |For Master, it calculates the period from START to ACK
+ * | | |For Slave, it calculates the period from START to STOP
+ * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit
+ * | | |BUSY =1.
+ * | | |0 = Indicates the SCLK low time-out interrupt is Disabled.
+ * | | |1 = Indicates the SCLK low time-out interrupt is Enabled.
+ * | | |BUSY =0.
+ * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.
+ * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.
+ * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
+ * | | |0 = Indicates the clock time out interrupt is Disabled.
+ * | | |1 = Indicates the clock time out interrupt is Enabled.
+ * |[4] |TORSTEN |Time Out Reset Enable Bit
+ * | | |0 = Indicates the I2C state machine reset is Disable.
+ * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
+ * @var I2C_T::BUSSTS
+ * Offset: 0x58 I2C Bus Management Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSY |Bus Busy
+ * | | |Indicates that a communication is in progress on the bus
+ * | | |It is set by hardware when a START condition is detected
+ * | | |It is cleared by hardware when a STOP condition is detected
+ * | | |0 = The bus is IDLE (both SCLK and SDA High).
+ * | | |1 = The bus is busy.
+ * |[1] |BCDONE |Byte Count Transmission/Receive Done
+ * | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set.
+ * | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set.
+ * | | |Note: Software can write 1 to clear this bit.
+ * |[2] |PECERR |PEC Error in Reception
+ * | | |0 = Indicates the PEC value equal the received PEC data packet.
+ * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.
+ * | | |Note: Software can write 1 to clear this bit.
+ * |[3] |ALERT |SMBus Alert Status
+ * | | |Device Mode (BMHEN =0).
+ * | | |0 = Indicates SMBALERT pin state is low.
+ * | | |1 = Indicates SMBALERT pin state is high.
+ * | | |Host Mode (BMHEN =1).
+ * | | |0 = No SMBALERT event.
+ * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
+ * | | |Note:
+ * | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system
+ * | | |2. Software can write 1 to clear this bit.
+ * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status
+ * | | |0 = The input status of SUSCON pin is 0.
+ * | | |1 = The input status of SUSCON pin is 1.
+ * |[5] |BUSTO |Bus Time-out Status
+ * | | |0 = Indicates that there is no any time-out or external clock time-out.
+ * | | |1 = Indicates that a time-out or external clock time-out occurred.
+ * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
+ * | | |Note: Software can write 1 to clear this bit.
+ * |[6] |CLKTO |Clock Low Cumulate Time-out Status
+ * | | |0 = Indicates that the cumulative clock low is no any time-out.
+ * | | |1 = Indicates that the cumulative clock low time-out occurred.
+ * | | |Note: Software can write 1 to clear this bit.
+ * |[7] |PECDONE |PEC Byte Transmission/Receive Done
+ * | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set.
+ * | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set.
+ * | | |Note: Software can write 1 to clear this bit.
+ * @var I2C_T::PKTSIZE
+ * Offset: 0x5C I2C Packet Error Checking Byte Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |PLDSIZE |Transfer Byte Number
+ * | | |The transmission or receive byte number in one transaction when the PECEN is set
+ * | | |The maximum transaction or receive byte is 256 Bytes.
+ * | | |Notice: The byte number counting includes address, command code, and data frame.
+ * @var I2C_T::PKTCRC
+ * Offset: 0x60 I2C Packet Error Checking Byte Value Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |PECCRC |Packet Error Checking Byte Value
+ * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1
+ * | | |It is read only.
+ * @var I2C_T::BUSTOUT
+ * Offset: 0x64 I2C Bus Management Timer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |BUSTO |Bus Management Time-out Value
+ * | | |Indicate the bus time-out value in bus is IDLE or SCLK low.
+ * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
+ * @var I2C_T::CLKTOUT
+ * Offset: 0x68 I2C Bus Management Clock Low Timer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CLKTO |Bus Clock Low Timer
+ * | | |The field is used to configure the cumulative clock extension time-out.
+ * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
+ */
+ __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */
+ __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */
+ __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */
+ __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */
+ __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */
+ __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */
+ __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */
+ __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */
+ __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */
+ __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */
+ __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */
+ __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */
+ __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */
+ __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */
+ __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */
+ __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */
+ __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */
+ __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */
+ __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */
+ __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */
+ __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */
+ __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */
+ __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */
+ __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */
+
+} I2C_T;
+
+/**
+ @addtogroup I2C_CONST I2C Bit Field Definition
+ Constant Definitions for I2C Controller
+@{ */
+
+#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL: AA Position */
+#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL: AA Mask */
+
+#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL: SI Position */
+#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL: SI Mask */
+
+#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL: STO Position */
+#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL: STO Mask */
+
+#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL: STA Position */
+#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL: STA Mask */
+
+#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */
+#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */
+
+#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */
+#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */
+
+#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
+#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
+
+#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
+#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
+
+#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
+#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
+
+#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */
+#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos) /*!< I2C_T::STATUS: STATUS Mask */
+
+#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
+#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
+
+#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
+#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
+
+#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
+#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
+
+#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
+#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
+
+#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
+#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
+
+#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
+#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
+
+#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
+#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
+
+#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
+#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
+
+#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
+#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
+
+#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
+#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
+
+#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
+#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
+
+#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
+#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
+
+#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
+#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
+
+#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
+#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
+
+#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
+#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
+
+#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */
+#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */
+
+#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
+#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
+
+#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */
+#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */
+
+#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */
+#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */
+
+#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */
+#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */
+
+#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */
+#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */
+
+#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */
+#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */
+
+#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */
+#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */
+
+#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */
+#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */
+
+#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */
+#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */
+
+#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */
+#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */
+
+#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */
+#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */
+
+#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */
+#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */
+
+#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */
+#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */
+
+#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */
+#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */
+
+#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */
+#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */
+
+#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
+#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
+
+#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
+#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
+
+#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
+#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
+
+#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
+#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
+
+#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
+#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
+
+#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
+#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
+
+#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
+#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
+
+#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
+#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
+
+#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
+#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
+
+#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
+#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
+
+#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
+#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
+
+#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
+#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
+
+#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */
+#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */
+
+#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */
+#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */
+
+#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
+#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
+
+#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
+#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
+
+#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
+#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
+
+#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
+#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
+
+#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
+#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
+
+#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
+#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
+
+#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
+#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
+
+#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
+#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
+
+#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
+#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
+
+#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
+#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
+
+#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
+#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
+
+#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
+#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
+
+#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */
+#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */
+
+#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
+#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
+
+#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
+#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
+
+#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
+#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
+
+#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
+#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
+
+/**@}*/ /* I2C_CONST */
+/**@}*/ /* end of I2C register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __I2C_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2s_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2s_reg.h
new file mode 100644
index 00000000000..ed8e34b6c32
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2s_reg.h
@@ -0,0 +1,707 @@
+/**************************************************************************//**
+ * @file i2s_reg.h
+ * @version V1.00
+ * @brief I2S register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __I2S_REG_H__
+#define __I2S_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup I2S I2S Interface Controller(I2S)
+ Memory Mapped Structure for I2S Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var I2S_T::CTL0
+ * Offset: 0x00 I2S Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |I2SEN |I2S Controller Enable Control
+ * | | |0 = I2S controller Disabled.
+ * | | |1 = I2S controller Enabled.
+ * |[1] |TXEN |Transmit Enable Control
+ * | | |0 = Data transmission Disabled.
+ * | | |1 = Data transmission Enabled.
+ * |[2] |RXEN |Receive Enable Control
+ * | | |0 = Data receiving Disabled.
+ * | | |1 = Data receiving Enabled.
+ * |[3] |MUTE |Transmit Mute Enable Control
+ * | | |0 = Transmit data is shifted from buffer.
+ * | | |1 = Send zero on transmit channel.
+ * |[5:4] |DATWIDTH |Data Width
+ * | | |This bit field is used to define the bit-width of data word in each audio channel
+ * | | |00 = The bit-width of data word is 8-bit.
+ * | | |01 = The bit-width of data word is 16-bit.
+ * | | |10 = The bit-width of data word is 24-bit.
+ * | | |11 = The bit-width of data word is 32-bit.
+ * |[6] |MONO |Monaural Data Control
+ * | | |0 = Data is stereo format.
+ * | | |1 = Data is monaural format.
+ * | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
+ * |[7] |ORDER |Stereo Data Order in FIFO
+ * | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte
+ * | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
+ * | | |0 = Even channel data at high byte in 8-bit/16-bit data width.
+ * | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries.
+ * | | |1 = Even channel data at low byte.
+ * | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
+ * |[8] |SLAVE |Slave Mode Enable Control
+ * | | |0 = Master mode.
+ * | | |1 = Slave mode.
+ * | | |Note: I2S can operate as master or slave
+ * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip
+ * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
+ * |[15] |MCLKEN |Master Clock Enable Control
+ * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
+ * | | |0 = Master clock Disabled.
+ * | | |1 = Master clock Enabled.
+ * |[18] |TXFBCLR |Transmit FIFO Buffer Clear
+ * | | |0 = No Effect.
+ * | | |1 = Clear TX FIFO.
+ * | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
+ * | | |Note2: This bit is clear by hardware automatically, read it return zero.
+ * |[19] |RXFBCLR |Receive FIFO Buffer Clear
+ * | | |0 = No Effect.
+ * | | |1 = Clear RX FIFO.
+ * | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.
+ * | | |Note2: This bit is cleared by hardware automatically, read it return zero.
+ * |[20] |TXPDMAEN |Transmit PDMA Enable Control
+ * | | |0 = Transmit PDMA function Disabled.
+ * | | |1 = Transmit PDMA function Enabled.
+ * |[21] |RXPDMAEN |Receive PDMA Enable Control
+ * | | |0 = Receiver PDMA function Disabled.
+ * | | |1 = Receiver PDMA function Enabled.
+ * |[23] |RXLCH |Receive Left Channel Enable Control
+ * | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1.
+ * | | |0 = Receives channel1 data in MONO mode.
+ * | | |1 = Receives channel0 data in MONO mode.
+ * |[26:24] |FORMAT |Data Format Selection
+ * | | |000 = I2S standard data format.
+ * | | |001 = I2S with MSB justified.
+ * | | |010 = I2S with LSB justified.
+ * | | |011 = Reserved.
+ * | | |100 = PCM standard data format.
+ * | | |101 = PCM with MSB justified.
+ * | | |110 = PCM with LSB justified.
+ * | | |111 = Reserved.
+ * |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection
+ * | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol
+ * | | |0 = One BCLK period.
+ * | | |1 = One channel period.
+ * | | |Note: This bit is only available in master mode
+ * |[29:28] |CHWIDTH |Channel Width
+ * | | |This bit fields are used to define the length of audio channel
+ * | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
+ * | | |00 = The bit-width of each audio channel is 8-bit.
+ * | | |01 = The bit-width of each audio channel is 16-bit.
+ * | | |10 = The bit-width of each audio channel is 24-bit.
+ * | | |11 = The bit-width of each audio channel is 32-bit.
+ * |[31:30] |TDMCHNUM |TDM Channel Number
+ * | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1).
+ * | | |00 = 2 channels in audio frame.
+ * | | |01 = 4 channels in audio frame.
+ * | | |10 = 6 channels in audio frame.
+ * | | |11 = 8 channels in audio frame.
+ * @var I2S_T::CLKDIV
+ * Offset: 0x04 I2S Clock Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |MCLKDIV |Master Clock Divider
+ * | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip
+ * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input.
+ * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
+ * | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ).
+ * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).
+ * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK
+ * |[16:8] |BCLKDIV |Bit Clock Divider
+ * | | |The I2S controller will generate bit clock in Master mode
+ * | | |Software can program these bit fields to generate sampling rate clock frequency.
+ * | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)).
+ * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
+ * @var I2S_T::IEN
+ * Offset: 0x08 I2S Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.
+ * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1
+ * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1
+ * | | |If RXTHIEN bit is enabled, interrupt occur.
+ * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
+ * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1
+ * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).
+ * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross
+ * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+ * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross
+ * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+ * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * @var I2S_T::STATUS0
+ * Offset: 0x0C I2S Status Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |I2SINT |I2S Interrupt Flag (Read Only)
+ * | | |0 = No I2S interrupt.
+ * | | |1 = I2S interrupt.
+ * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits.
+ * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only)
+ * | | |0 = No receive interrupt.
+ * | | |1 = Receive interrupt.
+ * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only)
+ * | | |0 = No transmit interrupt.
+ * | | |1 = Transmit interrupt.
+ * |[5:3] |DATACH |Transmission Data Channel (Read Only)
+ * | | |This bit fields are used to indicate which audio channel is current transmit data belong.
+ * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode).
+ * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode).
+ * | | |010 = channel2 (available while 4-channel TDM PCM mode).
+ * | | |011 = channel3 (available while 4-channel TDM PCM mode).
+ * | | |100 = channel4 (available while 6-channel TDM PCM mode).
+ * | | |101 = channel5 (available while 6-channel TDM PCM mode).
+ * | | |110 = channel6 (available while 8-channel TDM PCM mode).
+ * | | |111 = channel7 (available while 8-channel TDM PCM mode).
+ * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag
+ * | | |0 = No underflow occur.
+ * | | |1 = Underflow occur.
+ * | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again
+ * | | |This bit will be set to 1, and it indicates underflow situation occurs.
+ * | | |Note2: Write 1 to clear this bit to zero
+ * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag
+ * | | |0 = No overflow occur.
+ * | | |1 = Overflow occur.
+ * | | |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
+ * | | |Note2: Write 1 to clear this bit to 0.
+ * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = Data word(s) in FIFO is not higher than threshold level.
+ * | | |1 = Data word(s) in FIFO is higher than threshold level.
+ * | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1
+ * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
+ * |[11] |RXFULL |Receive FIFO Full (Read Only)
+ * | | |0 = Not full.
+ * | | |1 = Full.
+ * | | |Note: This bit reflects data words number in receive FIFO is 16.
+ * |[12] |RXEMPTY |Receive FIFO Empty (Read Only)
+ * | | |0 = Not empty.
+ * | | |1 = Empty.
+ * | | |Note: This bit reflects data words number in receive FIFO is zero
+ * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag
+ * | | |0 = No underflow.
+ * | | |1 = Underflow.
+ * | | |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
+ * | | |Note2: Write 1 to clear this bit to 0.
+ * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag
+ * | | |0 = No overflow.
+ * | | |1 = Overflow.
+ * | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1
+ * | | |Note2: Write 1 to clear this bit to 0.
+ * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = Data word(s) in FIFO is higher than threshold level.
+ * | | |1 = Data word(s) in FIFO is equal or lower than threshold level.
+ * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1
+ * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
+ * |[19] |TXFULL |Transmit FIFO Full (Read Only)
+ * | | |This bit reflect data word number in transmit FIFO is 16
+ * | | |0 = Not full.
+ * | | |1 = Full.
+ * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only)
+ * | | |This bit reflect data word number in transmit FIFO is zero
+ * | | |0 = Not empty.
+ * | | |1 = Empty.
+ * |[21] |TXBUSY |Transmit Busy (Read Only)
+ * | | |0 = Transmit shift buffer is empty.
+ * | | |1 = Transmit shift buffer is busy.
+ * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out
+ * | | |And set to 1 when 1st data is load to shift buffer
+ * @var I2S_T::TXFIFO
+ * Offset: 0x10 I2S Transmit FIFO Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TXFIFO |Transmit FIFO Bits
+ * | | |I2S contains 16 words (16x32 bit) data buffer for data transmit
+ * | | |Write data to this register to prepare data for transmit
+ * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
+ * @var I2S_T::RXFIFO
+ * Offset: 0x14 I2S Receive FIFO Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RXFIFO |Receive FIFO Bits
+ * | | |I2S contains 16 words (16x32 bit) data buffer for data receive
+ * | | |Read this register to get data in FIFO
+ * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
+ * @var I2S_T::CTL1
+ * Offset: 0x20 I2S Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control
+ * | | |0 = channel0 zero-cross detect Disabled.
+ * | | |1 = channel0 zero-cross detect Enabled.
+ * | | |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+ * | | |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.
+ * | | |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.
+ * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control
+ * | | |0 = channel1 zero-cross detect Disabled.
+ * | | |1 = channel1 zero-cross detect Enabled.
+ * | | |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+ * | | |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.
+ * | | |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.
+ * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control
+ * | | |0 = channel2 zero-cross detect Disabled.
+ * | | |1 = channel2 zero-cross detect Enabled.
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * | | |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.
+ * | | |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute.
+ * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control
+ * | | |0 = channel3 zero-cross detect Disabled.
+ * | | |1 = channel3 zero-cross detect Enabled.
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * | | |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.
+ * | | |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute.
+ * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control
+ * | | |0 = channel4 zero-cross detect Disabled.
+ * | | |1 = channel4 zero-cross detect Enabled.
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * | | |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
+ * | | |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute.
+ * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control
+ * | | |0 = channel5 zero-cross detect Disabled.
+ * | | |1 = channel5 zero-cross detect Enabled.
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * | | |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.
+ * | | |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute.
+ * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control
+ * | | |0 = channel6 zero-cross detect Disabled.
+ * | | |1 = channel6 zero-cross detect Enabled.
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * | | |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.
+ * | | |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute.
+ * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control
+ * | | |0 = channel7 zero-cross detect Disabled.
+ * | | |1 = channel7 zero-cross detect Enabled.
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * | | |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.
+ * | | |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute.
+ * |[11:8] |TXTH |Transmit FIFO Threshold Level
+ * | | |0000 = 0 data word in transmit FIFO.
+ * | | |0001 = 1 data word in transmit FIFO.
+ * | | |0010 = 2 data words in transmit FIFO.
+ * | | |...
+ * | | |1110 = 14 data words in transmit FIFO.
+ * | | |1111 = 15 data words in transmit FIFO.
+ * | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
+ * |[19:16] |RXTH |Receive FIFO Threshold Level
+ * | | |0000 = 1 data word in receive FIFO.
+ * | | |0001 = 2 data words in receive FIFO.
+ * | | |0010 = 3 data words in receive FIFO.
+ * | | |...
+ * | | |1110 = 15 data words in receive FIFO.
+ * | | |1111 = 16 data words in receive FIFO.
+ * | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
+ * |[24] |PBWIDTH |Peripheral Bus Data Width Selection
+ * | | |This bit is used to choice the available data width of APB bus
+ * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
+ * | | |0 = 32 bits data width.
+ * | | |1 = 16 bits data width.
+ * | | |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available.
+ * | | |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations.
+ * | | |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations.
+ * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus
+ * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access
+ * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries.
+ * | | |0 = Low 16-bit read/write access first.
+ * | | |1 = High 16-bit read/write access first.
+ * | | |Note: This bit is available while PBWIDTH = 1.
+ * @var I2S_T::STATUS1
+ * Offset: 0x24 I2S Status Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag
+ * | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero.
+ * | | |0 = No zero-cross in channel0.
+ * | | |1 = Channel0 zero-cross is detected.
+ * | | |Note1: Write 1 to clear this bit to 0.
+ * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+ * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag
+ * | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero.
+ * | | |0 = No zero-cross in channel1.
+ * | | |1 = Channel1 zero-cross is detected.
+ * | | |Note1: Write 1 to clear this bit to 0.
+ * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+ * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag
+ * | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero.
+ * | | |0 = No zero-cross in channel2.
+ * | | |1 = Channel2 zero-cross is detected.
+ * | | |Note1: Write 1 to clear this bit to 0.
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag
+ * | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero.
+ * | | |0 = No zero-cross in channel3.
+ * | | |1 = Channel3 zero-cross is detected.
+ * | | |Note1: Write 1 to clear this bit to 0.
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag
+ * | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero.
+ * | | |0 = No zero-cross in channel4.
+ * | | |1 = Channel4 zero-cross is detected.
+ * | | |Note1: Write 1 to clear this bit to 0.
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag
+ * | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero.
+ * | | |0 = No zero-cross in channel5.
+ * | | |1 = Channel5 zero-cross is detected.
+ * | | |Note1: Write 1 to clear this bit to 0.
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag
+ * | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero.
+ * | | |0 = No zero-cross in channel6.
+ * | | |1 = Channel6 zero-cross is detected.
+ * | | |Note1: Write 1 to clear this bit to 0.
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag
+ * | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero.
+ * | | |0 = No zero-cross in channel7.
+ * | | |1 = Channel7 zero-cross is detected.
+ * | | |Note1: Write 1 to clear this bit to 0.
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+ * |[12:8] |TXCNT |Transmit FIFO Level (Read Only)
+ * | | |These bits indicate the number of available entries in transmit FIFO
+ * | | |00000 = No data.
+ * | | |00001 = 1 word in transmit FIFO.
+ * | | |00010 = 2 words in transmit FIFO.
+ * | | |...
+ * | | |01110 = 14 words in transmit FIFO.
+ * | | |01111 = 15 words in transmit FIFO.
+ * | | |10000 = 16 words in transmit FIFO.
+ * | | |Others are reserved.
+ * |[20:16] |RXCNT |Receive FIFO Level (Read Only)
+ * | | |These bits indicate the number of available entries in receive FIFO
+ * | | |00000 = No data.
+ * | | |00001 = 1 word in receive FIFO.
+ * | | |00010 = 2 words in receive FIFO.
+ * | | |...
+ * | | |01110 = 14 words in receive FIFO.
+ * | | |01111 = 15 words in receive FIFO.
+ * | | |10000 = 16 words in receive FIFO.
+ * | | |Others are reserved.
+ */
+ __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */
+ __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */
+ __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */
+ __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */
+ __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */
+ __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */
+ __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */
+
+} I2S_T;
+
+/**
+ @addtogroup I2S_CONST I2S Bit Field Definition
+ Constant Definitions for I2S Controller
+@{ */
+
+#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */
+#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */
+
+#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */
+#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */
+
+#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */
+#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */
+
+#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */
+#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */
+
+#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */
+#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */
+
+#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */
+#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */
+
+#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */
+#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */
+
+#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */
+#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */
+
+#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */
+#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */
+
+#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */
+#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */
+
+#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */
+#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */
+
+#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */
+#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */
+
+#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */
+#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */
+
+#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */
+#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */
+
+#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */
+#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */
+
+#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */
+#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */
+
+#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */
+#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */
+
+#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */
+#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */
+
+#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */
+#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */
+
+#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */
+#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */
+
+#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */
+#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */
+
+#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */
+#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */
+
+#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */
+#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */
+
+#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */
+#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */
+
+#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */
+#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */
+
+#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */
+#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */
+
+#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */
+#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */
+
+#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */
+#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */
+
+#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */
+#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */
+
+#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */
+#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */
+
+#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */
+#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */
+
+#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */
+#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */
+
+#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */
+#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */
+
+#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */
+#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */
+
+#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */
+#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */
+
+#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */
+#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */
+
+#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */
+#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */
+
+#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */
+#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */
+
+#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */
+#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */
+
+#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */
+#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */
+
+#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */
+#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */
+
+#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */
+#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */
+
+#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */
+#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */
+
+#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */
+#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */
+
+#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */
+#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */
+
+#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */
+#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */
+
+#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */
+#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */
+
+#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */
+#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */
+
+#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */
+#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */
+
+#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */
+#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */
+
+#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */
+#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */
+
+#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */
+#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */
+
+#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */
+#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */
+
+#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */
+#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */
+
+#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */
+#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */
+
+#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */
+#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */
+
+#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */
+#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */
+
+#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */
+#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */
+
+#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */
+#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */
+
+#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */
+#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */
+
+#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */
+#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */
+
+#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */
+#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */
+
+#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */
+#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */
+
+#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */
+#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */
+
+#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */
+#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */
+
+#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */
+#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */
+
+#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */
+#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */
+
+#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */
+#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */
+
+#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */
+#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */
+
+#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */
+#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */
+
+#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */
+#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */
+
+#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */
+#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */
+
+#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */
+#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */
+
+/**@}*/ /* I2S_CONST */
+/**@}*/ /* end of I2S register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __I2S_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/opa_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/opa_reg.h
new file mode 100644
index 00000000000..c28268a8236
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/opa_reg.h
@@ -0,0 +1,268 @@
+/**************************************************************************//**
+ * @file opa_reg.h
+ * @version V1.00
+ * @brief OPA register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __OPA_REG_H__
+#define __OPA_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup OPA OP Amplifier(OPA)
+ Memory Mapped Structure for OPA Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var OPA_T::CTL
+ * Offset: 0x00 OP Amplifier Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |OPEN0 |OP Amplifier 0 Enable Bit
+ * | | |0 = OP amplifier0 Disabled.
+ * | | |1 = OP amplifier0 Enabled.
+ * | | |Note: OP Amplifier 0 output needs wait stable 20u03BCs after OPEN0 is set.
+ * |[1] |OPEN1 |OP Amplifier 1 Enable Bit
+ * | | |0 = OP amplifier1 Disabled.
+ * | | |1 = OP amplifier1 Enabled.
+ * | | |Note: OP Amplifier 1 output needs wait stable 20u03BCs after OPEN1 is set.
+ * |[2] |OPEN2 |OP Amplifier 2 Enable Bit
+ * | | |0 = OP amplifier2 Disabled.
+ * | | |1 = OP amplifier2 Enabled.
+ * | | |Note: OP Amplifier 2 output needs wait stable 20u03BCs after OPEN2 is set.
+ * |[4] |OPDOEN0 |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit
+ * | | |0 = OP amplifier0 Schmitt Trigger non-invert buffer Disabled.
+ * | | |1 = OP amplifier0 Schmitt Trigger non-invert buffer Enabled.
+ * |[5] |OPDOEN1 |OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit
+ * | | |0 = OP amplifier1 Schmitt Trigger non-invert buffer Disabled.
+ * | | |1 = OP amplifier1 Schmitt Trigger non-invert buffer Enabled.
+ * |[6] |OPDOEN2 |OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit
+ * | | |0 = OP amplifier2 Schmitt Trigger non-invert buffer Disabled.
+ * | | |1 = OP amplifier2 Schmitt Trigger non-invert buffer Enabled.
+ * |[8] |OPDOIEN0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit
+ * | | |0 = OP Amplifier 0 digital output interrupt function Disabled.
+ * | | |1 = OP Amplifier 0 digital output interrupt function Enabled.
+ * | | |The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated.
+ * |[9] |OPDOIEN1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit
+ * | | |0 = OP Amplifier 1 digital output interrupt function Disabled.
+ * | | |1 = OP Amplifier 1 digital output interrupt function Enabled.
+ * | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN1 is set to 1, a comparator interrupt request is generated.
+ * |[10] |OPDOIEN2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit
+ * | | |0 = OP Amplifier 2 digital output interrupt function Disabled.
+ * | | |1 = OP Amplifier 2 digital output interrupt function Enabled.
+ * | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN2 is set to 1, a comparator interrupt request is generated.
+ * @var OPA_T::STATUS
+ * Offset: 0x04 OP Amplifier Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |OPDO0 |OP Amplifier 0 Digital Output
+ * | | |Synchronized to the APB clock to allow reading by software
+ * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN0 = 0)
+ * |[1] |OPDO1 |OP Amplifier 1 Digital Output
+ * | | |Synchronized to the APB clock to allow reading by software
+ * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN1 = 0)
+ * |[2] |OPDO2 |OP Amplifier 2 Digital Output
+ * | | |Synchronized to the APB clock to allow reading by software
+ * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN2 = 0)
+ * |[4] |OPDOIF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag
+ * | | |OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state
+ * | | |This bit is cleared by writing 1 to it.
+ * |[5] |OPDOIF1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag
+ * | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt Trigger non-inverting buffer digital output changes state
+ * | | |This bit is cleared by writing 1 to it.
+ * |[6] |OPDOIF2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag
+ * | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state
+ * | | |This bit is cleared by writing 1 to it.
+ * @var OPA_T::CALCTL
+ * Offset: 0x08 OP Amplifier Calibration Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CALTRG0 |OP Amplifier 0 Calibration Trigger Bit
+ * | | |0 = Stop, hardware auto clear.
+ * | | |1 = Start. Note: Before enable this bit, it should set OPEN0 in advance.
+ * |[1] |CALTRG1 |OP Amplifier 1 Calibration Trigger Bit
+ * | | |0 = Stop, hardware auto clear.
+ * | | |1 = Start. Note: Before enable this bit, it should set OPEN1 in advance.
+ * |[2] |CALTRG2 |OP Amplifier 2 Calibration Trigger Bit
+ * | | |0 = Stop, hardware auto clear.
+ * | | |1 = Start. Note: Before enable this bit, it should set OPEN2 in advance.
+ * |[16] |CALRVS0 |OPA0 Calibration Reference Voltage Selection
+ * | | |0 = VREF is AVDD.
+ * | | |1 = VREF from high vcm to low vcm.
+ * |[17] |CALRVS1 |OPA1 Calibration Reference Voltage Selection
+ * | | |0 = VREF is AVDD.
+ * | | |1 = VREF from high vcm to low vcm.
+ * |[18] |CALRVS2 |OPA2 Calibration Reference Voltage Selection
+ * | | |0 = VREF is AVDD.
+ * | | |1 = VREF from high vcm to low vcm.
+ * @var OPA_T::CALST
+ * Offset: 0x0C OP Amplifier Calibration Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DONE0 |OP Amplifier 0 Calibration Done Status
+ * | | |0 = Calibrating.
+ * | | |1 = Calibration Done.
+ * |[1] |CALNS0 |OP Amplifier 0 Calibration Result Status for NMOS
+ * | | |0 = Pass.
+ * | | |1 = Fail.
+ * |[2] |CALPS0 |OP Amplifier 0 Calibration Result Status for PMOS
+ * | | |0 = Pass.
+ * | | |1 = Fail.
+ * |[4] |DONE1 |OP Amplifier 1 Calibration Done Status
+ * | | |0 = Calibrating.
+ * | | |1 = Calibration Done.
+ * |[5] |CALNS1 |OP Amplifier 1 Calibration Result Status for NMOS
+ * | | |0 = Pass.
+ * | | |1 = Fail.
+ * |[6] |CALPS1 |OP Amplifier 1 Calibration Result Status for PMOS
+ * | | |0 = Pass.
+ * | | |1 = Fail.
+ * |[8] |DONE2 |OP Amplifier 2 Calibration Done Status
+ * | | |0 = Calibrating.
+ * | | |1 = Calibration Done.
+ * |[9] |CALNS2 |OP Amplifier 2 Calibration Result Status for NMOS
+ * | | |0 = Pass.
+ * | | |1 = Fail.
+ * |[10] |CALPS2 |OP Amplifier 2 Calibration Result Status for PMOS
+ * | | |0 = Pass.
+ * | | |1 = Fail.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] OP Amplifier Control Register */
+ __IO uint32_t STATUS; /*!< [0x0004] OP Amplifier Status Register */
+ __IO uint32_t CALCTL; /*!< [0x0008] OP Amplifier Calibration Control Register */
+ __I uint32_t CALST; /*!< [0x000c] OP Amplifier Calibration Status Register */
+
+} OPA_T;
+
+/**
+ @addtogroup OPA_CONST OPA Bit Field Definition
+ Constant Definitions for OPA Controller
+@{ */
+
+#define OPA_CTL_OPEN0_Pos (0) /*!< OPA_T::CTL: OPEN0 Position */
+#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA_T::CTL: OPEN0 Mask */
+
+#define OPA_CTL_OPEN1_Pos (1) /*!< OPA_T::CTL: OPEN1 Position */
+#define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /*!< OPA_T::CTL: OPEN1 Mask */
+
+#define OPA_CTL_OPEN2_Pos (2) /*!< OPA_T::CTL: OPEN2 Position */
+#define OPA_CTL_OPEN2_Msk (0x1ul << OPA_CTL_OPEN2_Pos) /*!< OPA_T::CTL: OPEN2 Mask */
+
+#define OPA_CTL_OPDOEN0_Pos (4) /*!< OPA_T::CTL: OPDOEN0 Position */
+#define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) /*!< OPA_T::CTL: OPDOEN0 Mask */
+
+#define OPA_CTL_OPDOEN1_Pos (5) /*!< OPA_T::CTL: OPDOEN1 Position */
+#define OPA_CTL_OPDOEN1_Msk (0x1ul << OPA_CTL_OPDOEN1_Pos) /*!< OPA_T::CTL: OPDOEN1 Mask */
+
+#define OPA_CTL_OPDOEN2_Pos (6) /*!< OPA_T::CTL: OPDOEN2 Position */
+#define OPA_CTL_OPDOEN2_Msk (0x1ul << OPA_CTL_OPDOEN2_Pos) /*!< OPA_T::CTL: OPDOEN2 Mask */
+
+#define OPA_CTL_OPDOIEN0_Pos (8) /*!< OPA_T::CTL: OPDOIEN0 Position */
+#define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) /*!< OPA_T::CTL: OPDOIEN0 Mask */
+
+#define OPA_CTL_OPDOIEN1_Pos (9) /*!< OPA_T::CTL: OPDOIEN1 Position */
+#define OPA_CTL_OPDOIEN1_Msk (0x1ul << OPA_CTL_OPDOIEN1_Pos) /*!< OPA_T::CTL: OPDOIEN1 Mask */
+
+#define OPA_CTL_OPDOIEN2_Pos (10) /*!< OPA_T::CTL: OPDOIEN2 Position */
+#define OPA_CTL_OPDOIEN2_Msk (0x1ul << OPA_CTL_OPDOIEN2_Pos) /*!< OPA_T::CTL: OPDOIEN2 Mask */
+
+#define OPA_STATUS_OPDO0_Pos (0) /*!< OPA_T::STATUS: OPDO0 Position */
+#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA_T::STATUS: OPDO0 Mask */
+
+#define OPA_STATUS_OPDO1_Pos (1) /*!< OPA_T::STATUS: OPDO1 Position */
+#define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /*!< OPA_T::STATUS: OPDO1 Mask */
+
+#define OPA_STATUS_OPDO2_Pos (2) /*!< OPA_T::STATUS: OPDO2 Position */
+#define OPA_STATUS_OPDO2_Msk (0x1ul << OPA_STATUS_OPDO2_Pos) /*!< OPA_T::STATUS: OPDO2 Mask */
+
+#define OPA_STATUS_OPDOIF0_Pos (4) /*!< OPA_T::STATUS: OPDOIF0 Position */
+#define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) /*!< OPA_T::STATUS: OPDOIF0 Mask */
+
+#define OPA_STATUS_OPDOIF1_Pos (5) /*!< OPA_T::STATUS: OPDOIF1 Position */
+#define OPA_STATUS_OPDOIF1_Msk (0x1ul << OPA_STATUS_OPDOIF1_Pos) /*!< OPA_T::STATUS: OPDOIF1 Mask */
+
+#define OPA_STATUS_OPDOIF2_Pos (6) /*!< OPA_T::STATUS: OPDOIF2 Position */
+#define OPA_STATUS_OPDOIF2_Msk (0x1ul << OPA_STATUS_OPDOIF2_Pos) /*!< OPA_T::STATUS: OPDOIF2 Mask */
+
+#define OPA_CALCTL_CALTRG0_Pos (0) /*!< OPA_T::CALCTL: CALTRG0 Position */
+#define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) /*!< OPA_T::CALCTL: CALTRG0 Mask */
+
+#define OPA_CALCTL_CALTRG1_Pos (1) /*!< OPA_T::CALCTL: CALTRG1 Position */
+#define OPA_CALCTL_CALTRG1_Msk (0x1ul << OPA_CALCTL_CALTRG1_Pos) /*!< OPA_T::CALCTL: CALTRG1 Mask */
+
+#define OPA_CALCTL_CALTRG2_Pos (2) /*!< OPA_T::CALCTL: CALTRG2 Position */
+#define OPA_CALCTL_CALTRG2_Msk (0x1ul << OPA_CALCTL_CALTRG2_Pos) /*!< OPA_T::CALCTL: CALTRG2 Mask */
+
+#define OPA_CALCTL_CALCLK0_Pos (4) /*!< OPA_T::CALCTL: CALCLK0 Position */
+#define OPA_CALCTL_CALCLK0_Msk (0x3ul << OPA_CALCTL_CALCLK0_Pos) /*!< OPA_T::CALCTL: CALCLK0 Mask */
+
+#define OPA_CALCTL_CALCLK1_Pos (6) /*!< OPA_T::CALCTL: CALCLK1 Position */
+#define OPA_CALCTL_CALCLK1_Msk (0x3ul << OPA_CALCTL_CALCLK1_Pos) /*!< OPA_T::CALCTL: CALCLK1 Mask */
+
+#define OPA_CALCTL_CALCLK2_Pos (8) /*!< OPA_T::CALCTL: CALCLK2 Position */
+#define OPA_CALCTL_CALCLK2_Msk (0x3ul << OPA_CALCTL_CALCLK2_Pos) /*!< OPA_T::CALCTL: CALCLK2 Mask */
+
+#define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */
+#define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */
+
+#define OPA_CALCTL_CALRVS1_Pos (17) /*!< OPA_T::CALCTL: CALRVS1 Position */
+#define OPA_CALCTL_CALRVS1_Msk (0x1ul << OPA_CALCTL_CALRVS1_Pos) /*!< OPA_T::CALCTL: CALRVS1 Mask */
+
+#define OPA_CALCTL_CALRVS2_Pos (18) /*!< OPA_T::CALCTL: CALRVS2 Position */
+#define OPA_CALCTL_CALRVS2_Msk (0x1ul << OPA_CALCTL_CALRVS2_Pos) /*!< OPA_T::CALCTL: CALRVS2 Mask */
+
+#define OPA_CALST_DONE0_Pos (0) /*!< OPA_T::CALST: DONE0 Position */
+#define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) /*!< OPA_T::CALST: DONE0 Mask */
+
+#define OPA_CALST_CALNS0_Pos (1) /*!< OPA_T::CALST: CALNS0 Position */
+#define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) /*!< OPA_T::CALST: CALNS0 Mask */
+
+#define OPA_CALST_CALPS0_Pos (2) /*!< OPA_T::CALST: CALPS0 Position */
+#define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) /*!< OPA_T::CALST: CALPS0 Mask */
+
+#define OPA_CALST_DONE1_Pos (4) /*!< OPA_T::CALST: DONE1 Position */
+#define OPA_CALST_DONE1_Msk (0x1ul << OPA_CALST_DONE1_Pos) /*!< OPA_T::CALST: DONE1 Mask */
+
+#define OPA_CALST_CALNS1_Pos (5) /*!< OPA_T::CALST: CALNS1 Position */
+#define OPA_CALST_CALNS1_Msk (0x1ul << OPA_CALST_CALNS1_Pos) /*!< OPA_T::CALST: CALNS1 Mask */
+
+#define OPA_CALST_CALPS1_Pos (6) /*!< OPA_T::CALST: CALPS1 Position */
+#define OPA_CALST_CALPS1_Msk (0x1ul << OPA_CALST_CALPS1_Pos) /*!< OPA_T::CALST: CALPS1 Mask */
+
+#define OPA_CALST_DONE2_Pos (8) /*!< OPA_T::CALST: DONE2 Position */
+#define OPA_CALST_DONE2_Msk (0x1ul << OPA_CALST_DONE2_Pos) /*!< OPA_T::CALST: DONE2 Mask */
+
+#define OPA_CALST_CALNS2_Pos (9) /*!< OPA_T::CALST: CALNS2 Position */
+#define OPA_CALST_CALNS2_Msk (0x1ul << OPA_CALST_CALNS2_Pos) /*!< OPA_T::CALST: CALNS2 Mask */
+
+#define OPA_CALST_CALPS2_Pos (10) /*!< OPA_T::CALST: CALPS2 Position */
+#define OPA_CALST_CALPS2_Msk (0x1ul << OPA_CALST_CALPS2_Pos) /*!< OPA_T::CALST: CALPS2 Mask */
+
+/**@}*/ /* OPA_CONST */
+/**@}*/ /* end of OPA register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __OPA_REG_H__ */
+
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/otg_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/otg_reg.h
new file mode 100644
index 00000000000..03900262008
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/otg_reg.h
@@ -0,0 +1,399 @@
+/**************************************************************************//**
+ * @file otg_reg.h
+ * @version V1.00
+ * @brief OTG register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __OTG_REG_H__
+#define __OTG_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup OTG USB On-The-Go Controller(OTG)
+ Memory Mapped Structure for OTG Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var OTG_T::CTL
+ * Offset: 0x00 OTG Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |VBUSDROP |Drop VBUS Control
+ * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
+ * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
+ * | | |0 = Not drop the VBUS.
+ * | | |1 = Drop the VBUS.
+ * |[1] |BUSREQ |OTG Bus Request
+ * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
+ * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power
+ * | | |This bit will be cleared when A-device goes to A_wait_vfall state
+ * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
+ * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
+ * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification)
+ * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
+ * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
+ * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
+ * |[2] |HNPREQEN |OTG HNP Request Enable Bit
+ * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
+ * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
+ * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
+ * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
+ * | | |0 = HNP request Disabled.
+ * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
+ * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
+ * |[4] |OTGEN |OTG Function Enable Bit
+ * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device
+ * | | |When USB frame not configured as OTG device, this bit is must be low.
+ * | | |0= OTG function Disabled.
+ * | | |1 = OTG function Enabled.
+ * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit
+ * | | |0 = OTG ID pin status change wake-up function Disabled.
+ * | | |1 = OTG ID pin status change wake-up function Enabled.
+ * @var OTG_T::PHYCTL
+ * Offset: 0x04 OTG PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |OTGPHYEN |OTG PHY Enable
+ * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
+ * | | |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care".
+ * | | |0 = OTG PHY Disabled.
+ * | | |1 = OTG PHY Enabled.
+ * |[1] |IDDETEN |ID Detection Enable Bit
+ * | | |0 = Detect ID pin status Disabled.
+ * | | |1 = Detect ID pin status Enabled.
+ * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity
+ * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
+ * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
+ * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
+ * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+ * | | |0 = The off-chip USB VBUS power switch enable is active high.
+ * | | |1 = The off-chip USB VBUS power switch enable is active low.
+ * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity
+ * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
+ * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
+ * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+ * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
+ * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
+ * @var OTG_T::INTEN
+ * Offset: 0x08 OTG Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
+ * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: Going to idle state means going to a_idle or b_idle state
+ * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
+ * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
+ * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
+ * | | |0 = This device as a peripheral interrupt Disabled.
+ * | | |1 = This device as a peripheral interrupt Enabled.
+ * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
+ * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
+ * | | |0 = This device as a host interrupt Disabled.
+ * | | |1 = This device as a host interrupt Enabled.
+ * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * @var OTG_T::INTSTS
+ * Offset: 0x0C OTG Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ROLECHGIF |OTG Role Change Interrupt Status
+ * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
+ * | | |0 = OTG device role not changed.
+ * | | |1 = OTG device role changed.
+ * | | |Note: Write 1 to clear this flag.
+ * |[1] |VBEIF |VBUS Error Interrupt Status
+ * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
+ * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
+ * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
+ * | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
+ * |[2] |SRPFIF |SRP Fail Interrupt Status
+ * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
+ * | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
+ * | | |0 = OTG B-device gets VBUS high before this interval.
+ * | | |1 = OTG B-device does not get VBUS high before this interval.
+ * | | |Note: Write 1 to clear this flag.
+ * |[3] |HNPFIF |HNP Fail Interrupt Status
+ * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
+ * | | |0 = A-device connects to B-device before specified interval expires.
+ * | | |1 = A-device does not connect to B-device before specified interval expires.
+ * | | |Note: Write 1 to clear this flag.
+ * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
+ * | | |Flag is set if the OTG device transfers from non-idle state to idle state
+ * | | |The OTG device will be neither a host nor a peripheral.
+ * | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
+ * | | |1 = OTG device goes back to idle state(a_idle or b_idle).
+ * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
+ * | | |Note 2: Write 1 to clear this flag.
+ * |[5] |IDCHGIF |ID State Change Interrupt Status
+ * | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
+ * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
+ * | | |Note: Write 1 to clear this flag.
+ * |[6] |PDEVIF |Act As Peripheral Interrupt Status
+ * | | |0= This device does not act as a peripheral.
+ * | | |1 = This device acts as a peripheral.
+ * | | |Note: Write 1 to clear this flag.
+ * |[7] |HOSTIF |Act As Host Interrupt Status
+ * | | |0= This device does not act as a host.
+ * | | |1 = This device acts as a host.
+ * | | |Note: Write 1 to clear this flag.
+ * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
+ * | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
+ * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
+ * | | |Note: Write 1 to clear this status.
+ * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
+ * | | |0 = AVLD (OTG_STATUS[4]) not toggled.
+ * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
+ * | | |Note: Write 1 to clear this status.
+ * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
+ * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
+ * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
+ * | | |Note: Write 1 to clear this status.
+ * |[11] |SECHGIF |SESSEND State Change Interrupt Status
+ * | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
+ * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
+ * | | |Note: Write 1 to clear this flag.
+ * |[13] |SRPDETIF |SRP Detected Interrupt Status
+ * | | |0 = SRP not detected.
+ * | | |1 = SRP detected.
+ * | | |Note: Write 1 to clear this status.
+ * @var OTG_T::STATUS
+ * Offset: 0x10 OTG Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |OVERCUR |over Current Condition
+ * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
+ * | | |0 = OTG A-device drives VBUS successfully.
+ * | | |1 = OTG A-device cannot drives VBUS high in this interval.
+ * |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug
+ * | | |0 = Mini-A/Micro-A plug is attached.
+ * | | |1 = Mini-B/Micro-B plug is attached.
+ * |[2] |SESSEND |Session End Status
+ * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1
+ * | | |Session end means no meaningful power on VBUS.
+ * | | |0 = Session is not end.
+ * | | |1 = Session is end.
+ * |[3] |BVLD |B-device Session Valid Status
+ * | | |0 = B-device session is not valid.
+ * | | |1 = B-device session is valid.
+ * |[4] |AVLD |A-device Session Valid Status
+ * | | |0 = A-device session is not valid.
+ * | | |1 = A-device session is valid.
+ * |[5] |VBUSVLD |VBUS Valid Status
+ * | | |When VBUS is larger than 4.7V, this bit will be set to 1.
+ * | | |0 = VBUS is not valid.
+ * | | |1 = VBUS is valid.
+ * |[6] |ASPERI |As Peripheral Status
+ * | | |When OTG as peripheral, this bit is set.
+ * | | |0: OTG not as peripheral
+ * | | |1: OTG as peripheral
+ * |[7] |ASHOST |As Host Status
+ * | | |When OTG as Host, this bit is set.
+ * | | |0: OTG not as Host
+ * | | |1: OTG as Host
+ */
+ __IO uint32_t CTL; /*!< [0x0000] OTG Control Register */
+ __IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */
+ __IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */
+ __IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */
+ __I uint32_t STATUS; /*!< [0x0010] OTG Status Register */
+
+} OTG_T;
+
+
+/**
+ @addtogroup OTG_CONST OTG Bit Field Definition
+ Constant Definitions for OTG Controller
+@{ */
+
+#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
+#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
+
+#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
+#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
+
+#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
+#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
+
+#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
+#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
+
+#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
+#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
+
+#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
+#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
+
+#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
+#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
+
+#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
+#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
+
+#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
+#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
+
+#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
+#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
+
+#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
+#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
+
+#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
+#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
+
+#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
+#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
+
+#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
+#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
+
+#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
+#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
+
+#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
+#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
+
+#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
+#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
+
+#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
+#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
+
+#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
+#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
+
+#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
+#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
+
+#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
+#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
+
+#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
+#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
+
+#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
+#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
+
+#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
+#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
+
+#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
+#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
+
+#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
+#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
+
+#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
+#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
+
+#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
+#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
+
+#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
+#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
+
+#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
+#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
+
+#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
+#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
+
+#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
+#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
+
+#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
+#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
+
+#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
+#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
+
+#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
+#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
+
+#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
+#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
+
+#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
+#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
+
+#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
+#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
+
+#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
+#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
+
+#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
+#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
+
+#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
+#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
+
+#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */
+#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */
+
+#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */
+#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */
+
+/**@}*/ /* OTG_CONST */
+/**@}*/ /* end of OTG register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __OTG_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/pdma_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/pdma_reg.h
new file mode 100644
index 00000000000..a849d6bdcf5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/pdma_reg.h
@@ -0,0 +1,886 @@
+/**************************************************************************//**
+ * @file pdma_reg.h
+ * @version V1.00
+ * @brief PDMA register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __PDMA_REG_H__
+#define __PDMA_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
+ Memory Mapped Structure for PDMA Controller
+@{ */
+
+
+typedef struct
+{
+
+ /**
+ * @var DSCT_T::CTL
+ * Offset: 0x00 Descriptor Table Control Register of PDMA Channel n.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |OPMODE |PDMA Operation Mode Selection
+ * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
+ * | | |01 = Basic mode: The descriptor table only has one task
+ * | | |When this task is finished, the PDMA_INTSTS[n] will be asserted.
+ * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
+ * | | |11 = Reserved.
+ * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
+ * |[2] |TXTYPE |Transfer Type
+ * | | |0 = Burst transfer type.
+ * | | |1 = Single transfer type.
+ * |[6:4] |BURSIZE |Burst Size
+ * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
+ * | | |000 = 128 Transfers.
+ * | | |001 = 64 Transfers.
+ * | | |010 = 32 Transfers.
+ * | | |011 = 16 Transfers.
+ * | | |100 = 8 Transfers.
+ * | | |101 = 4 Transfers.
+ * | | |110 = 2 Transfers.
+ * | | |111 = 1 Transfers.
+ * | | |Note: This field is only useful in burst transfer type.
+ * |[7] |TBINTDIS |Table Interrupt Disable Bit
+ * | | |This field can be used to decide whether to enable table interrupt or not
+ * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
+ * | | |0 = Table interrupt Enabled.
+ * | | |1 = Table interrupt Disabled.
+ * |[9:8] |SAINC |Source Address Increment
+ * | | |This field is used to set the source address increment size.
+ * | | |11 = No increment (fixed address).
+ * | | |Others = Increment and size is depended on TXWIDTH selection.
+ * |[11:10] |DAINC |Destination Address Increment
+ * | | |This field is used to set the destination address increment size.
+ * | | |11 = No increment (fixed address).
+ * | | |Others = Increment and size is depended on TXWIDTH selection.
+ * |[13:12] |TXWIDTH |Transfer Width Selection
+ * | | |This field is used for transfer width.
+ * | | |00 = One byte (8 bit) is transferred for every operation.
+ * | | |01= One half-word (16 bit) is transferred for every operation.
+ * | | |10 = One word (32-bit) is transferred for every operation.
+ * | | |11 = Reserved.
+ * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
+ * |[14] |TXACK |Transfer Acknowledge Selection
+ * | | |0 = transfer ack when transfer done.
+ * | | |1 = transfer ack when PDMA get transfer data.
+ * |[15] |STRIDEEN |Stride Mode Enable Bit
+ * | | |0 = Stride transfer mode Disabled.
+ * | | |1 = Stride transfer mode Enabled.
+ * |[31:16] |TXCNT |Transfer Count
+ * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
+ * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
+ * @var DSCT_T::SA
+ * Offset: 0x04 Source Address Register of PDMA Channel n
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SA |PDMA Transfer Source Address Register
+ * | | |This field indicates a 32-bit source address of PDMA controller.
+ * @var DSCT_T::DA
+ * Offset: 0x08 Destination Address Register of PDMA Channel n
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DA |PDMA Transfer Destination Address Register
+ * | | |This field indicates a 32-bit destination address of PDMA controller.
+ * @var DSCT_T::NEXT
+ * Offset: 0x0C Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |EXENEXT |PDMA Execution Next Descriptor Table Offset
+ * | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory.
+ * | | |Note: write operation is useless in this field.
+ * |[31:16] |NEXT |PDMA Next Descriptor Table Offset.
+ * | | |This field indicates the offset of the next descriptor table address in system memory.
+ * | | |Write Operation:
+ * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
+ * | | |Read Operation:
+ * | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.
+ * | | |Note1: The descriptor table address must be word boundary.
+ * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */
+ __IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */
+ __IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */
+ __IO uint32_t NEXT; /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */
+} DSCT_T;
+
+
+typedef struct
+{
+ /**
+ * @var STRIDE_T::STCR
+ * Offset: 0x500 Stride Transfer Count Register of PDMA Channel n
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |STC |PDMA Stride Transfer Count
+ * | | |The 16-bit register defines the stride transfer count of each row.
+ * @var STRIDE_T::ASOCR
+ * Offset: 0x504 Address Stride Offset Register of PDMA Channel n
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |SASOL |VDMA Source Address Stride Offset Length
+ * | | |The 16-bit register defines the source address stride transfer offset count of each row.
+ * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length
+ * | | |The 16-bit register defines the destination address stride transfer offset count of each row.
+ */
+ __IO uint32_t STCR; /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0 */
+ __IO uint32_t ASOCR; /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0 */
+} STRIDE_T;
+
+typedef struct
+{
+ /**
+ * @var REPEAT_T::AICTL
+ * Offset: 0x600 Address Interval Control Register of PDMA Channel n
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |SAICNT |PDMA Source Address Interval Count
+ * | | |The 16-bit register defines the source address interval count of each row.
+ * |[31:16] |DAICNT |PDMA Destination Address Interval Count
+ * | | |The 16-bit register defines the destination address interval count of each row.
+ * @var REPEAT_T::RCNT
+ * Offset: 0x604 Repeat Count Register of PDMA Channe n
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RCNT |PDMA Repeat Count
+ * | | |The 16-bit register defines the repeat times of block transfer.
+ */
+ __IO uint32_t AICTL; /*!< [0x0600] Address Interval Control Register of PDMA Channel 0 */
+ __IO uint32_t RCNT; /*!< [0x0604] Repeat Count Register of PDMA Channel 0 */
+} REPEAT_T;
+
+typedef struct
+{
+
+
+ /**
+ * @var PDMA_T::CURSCAT
+ * Offset: 0x100 Current Scatter-Gather Descriptor Table Address of PDMA Channel n
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)
+ * | | |This field indicates a 32-bit current external description address of PDMA controller.
+ * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
+ * @var PDMA_T::CHCTL
+ * Offset: 0x400 PDMA Channel Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CHENn |PDMA Channel Enable Bit
+ * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
+ * | | |0 = PDMA channel [n] Disabled.
+ * | | |1 = PDMA channel [n] Enabled.
+ * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
+ * @var PDMA_T::PAUSE
+ * Offset: 0x404 PDMA Transfer Stop Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only)
+ * | | |User can set PAUSEn bit field to pause the PDMA transfer
+ * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag
+ * | | |If re-enable the paused channel again, the remaining transfers will be processed.
+ * | | |0 = No effect.
+ * | | |1 = Pause PDMA channel n transfer.
+ * @var PDMA_T::SWREQ
+ * Offset: 0x408 PDMA Software Request Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |SWREQn |PDMA Software Request Register (Write Only)
+ * | | |Set this bit to 1 to generate a software request to PDMA [n].
+ * | | |0 = No effect.
+ * | | |1 = Generate a software request.
+ * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active
+ * | | |Active flag may be triggered by software request or peripheral request.
+ * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
+ * @var PDMA_T::TRGSTS
+ * Offset: 0x40C PDMA Channel Request Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only)
+ * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral
+ * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
+ * | | |0 = PDMA Channel n has no request.
+ * | | |1 = PDMA Channel n has a request.
+ * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
+ * @var PDMA_T::PRISET
+ * Offset: 0x410 PDMA Fixed Priority Setting Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register
+ * | | |Set this bit to 1 to enable fixed priority level.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set PDMA channel [n] to fixed priority channel.
+ * | | |Read Operation:
+ * | | |0 = Corresponding PDMA channel is round-robin priority.
+ * | | |1 = Corresponding PDMA channel is fixed priority.
+ * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
+ * @var PDMA_T::PRICLR
+ * Offset: 0x414 PDMA Fixed Priority Clear Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)
+ * | | |Set this bit to 1 to clear fixed priority level.
+ * | | |0 = No effect.
+ * | | |1 = Clear PDMA channel [n] fixed priority setting.
+ * | | |Note: User can read PDMA_PRISET register to know the channel priority.
+ * @var PDMA_T::INTEN
+ * Offset: 0x418 PDMA Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |INTENn |PDMA Interrupt Enable Register
+ * | | |This field is used for enabling PDMA channel[n] interrupt.
+ * | | |0 = PDMA channel n interrupt Disabled.
+ * | | |1 = PDMA channel n interrupt Enabled.
+ * @var PDMA_T::INTSTS
+ * Offset: 0x41C PDMA Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-only)
+ * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
+ * | | |0 = No AHB bus ERROR response received.
+ * | | |1 = AHB bus ERROR response received.
+ * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
+ * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
+ * | | |0 = Not finished yet.
+ * | | |1 = PDMA channel has finished transmission.
+ * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only)
+ * | | |0 = PDMA channel source address and destination address both follow transfer width setting.
+ * | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
+ * |[8] |REQTOF0 |Request Time-out Flag for Channel 0
+ * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
+ * | | |0 = No request time-out.
+ * | | |1 = Peripheral request time-out.
+ * |[9] |REQTOF1 |Request Time-out Flag for Channel 1
+ * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
+ * | | |0 = No request time-out.
+ * | | |1 = Peripheral request time-out.
+ * @var PDMA_T::ABTSTS
+ * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
+ * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
+ * | | |0 = No AHB bus ERROR response received when channel n transfer.
+ * | | |1 = AHB bus ERROR response received when channel n transfer.
+ * @var PDMA_T::TDSTS
+ * Offset: 0x424 PDMA Channel Transfer Done Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |TDIFn |Transfer Done Flag Register
+ * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
+ * | | |0 = PDMA channel transfer has not finished.
+ * | | |1 = PDMA channel has finished transmission.
+ * @var PDMA_T::ALIGN
+ * Offset: 0x428 PDMA Transfer Alignment Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |ALIGNn |Transfer Alignment Flag Register
+ * | | |0 = PDMA channel source address and destination address both follow transfer width setting.
+ * | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
+ * @var PDMA_T::TACTSTS
+ * Offset: 0x42C PDMA Transfer Active Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only)
+ * | | |This bit indicates which PDMA channel is in active.
+ * | | |0 = PDMA channel is not finished.
+ * | | |1 = PDMA channel is active.
+ * @var PDMA_T::TOUTPSC
+ * Offset: 0x430 PDMA Time-out Prescaler Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits
+ * | | |000 = PDMA channel 0 time-out clock source is HCLK/28.
+ * | | |001 = PDMA channel 0 time-out clock source is HCLK/29.
+ * | | |010 = PDMA channel 0 time-out clock source is HCLK/210.
+ * | | |011 = PDMA channel 0 time-out clock source is HCLK/211.
+ * | | |100 = PDMA channel 0 time-out clock source is HCLK/212.
+ * | | |101 = PDMA channel 0 time-out clock source is HCLK/213.
+ * | | |110 = PDMA channel 0 time-out clock source is HCLK/214.
+ * | | |111 = PDMA channel 0 time-out clock source is HCLK/215.
+ * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits
+ * | | |000 = PDMA channel 1 time-out clock source is HCLK/28.
+ * | | |001 = PDMA channel 1 time-out clock source is HCLK/29.
+ * | | |010 = PDMA channel 1 time-out clock source is HCLK/210.
+ * | | |011 = PDMA channel 1 time-out clock source is HCLK/211.
+ * | | |100 = PDMA channel 1 time-out clock source is HCLK/212.
+ * | | |101 = PDMA channel 1 time-out clock source is HCLK/213.
+ * | | |110 = PDMA channel 1 time-out clock source is HCLK/214.
+ * | | |111 = PDMA channel 1 time-out clock source is HCLK/215.
+ * @var PDMA_T::TOUTEN
+ * Offset: 0x434 PDMA Time-out Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |TOUTENn |PDMA Time-out Enable Bits
+ * | | |0 = PDMA Channel n time-out function Disable.
+ * | | |1 = PDMA Channel n time-out function Enable.
+ * @var PDMA_T::TOUTIEN
+ * Offset: 0x438 PDMA Time-out Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits
+ * | | |0 = PDMA Channel n time-out interrupt Disable.
+ * | | |1 = PDMA Channel n time-out interrupt Enable.
+ * @var PDMA_T::SCATBA
+ * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register
+ * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address
+ * | | |The next link address equation is
+ * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
+ * | | |Note: Only useful in Scatter-Gather mode.
+ * @var PDMA_T::TOC0_1
+ * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |TOC0 |Time-out Counter for Channel 0
+ * | | |This controls the period of time-out function for channel 0
+ * | | |The calculation unit is based on 10 kHz clock.
+ * |[31:16] |TOC1 |Time-out Counter for Channel 1
+ * | | |This controls the period of time-out function for channel 1
+ * | | |The calculation unit is based on 10 kHz clock.
+ * @var PDMA_T::CHRST
+ * Offset: 0x460 PDMA Channel Reset Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CHnRST |Channel N Reset
+ * | | |0 = corresponding channel n not reset.
+ * | | |1 = corresponding channel n is reset.
+ * @var PDMA_T::REQSEL0_3
+ * Offset: 0x480 PDMA Request Source Select Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |REQSRC0 |Channel 0 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 0
+ * | | |User can configure the peripheral by setting REQSRC0.
+ * | | |0 = Disable PDMA peripheral request.
+ * | | |1 = Reserved.
+ * | | |2 = Channel connects to USB_TX.
+ * | | |3 = Channel connects to USB_RX.
+ * | | |4 = Channel connects to UART0_TX.
+ * | | |5 = Channel connects to UART0_RX.
+ * | | |6 = Channel connects to UART1_TX.
+ * | | |7 = Channel connects to UART1_RX.
+ * | | |8 = Channel connects to UART2_TX.
+ * | | |9 = Channel connects to UART2_RX.
+ * | | |10=Channel connects to UART3_TX.
+ * | | |11 = Channel connects to UART3_RX.
+ * | | |12 = Channel connects to UART4_TX.
+ * | | |13 = Channel connects to UART4_RX.
+ * | | |14 = Channel connects to UART5_TX.
+ * | | |15 = Channel connects to UART5_RX.
+ * | | |16 = Channel connects to USCI0_TX.
+ * | | |17 = Channel connects to USCI0_RX.
+ * | | |18 = Channel connects to USCI1_TX.
+ * | | |19 = Channel connects to USCI1_RX.
+ * | | |20 = Channel connects to QSPI0_TX.
+ * | | |21 = Channel connects to QSPI0_RX.
+ * | | |22 = Channel connects to SPI0_TX.
+ * | | |23 = Channel connects to SPI0_RX.
+ * | | |24 = Channel connects to SPI1_TX.
+ * | | |25 = Channel connects to SPI1_RX.
+ * | | |26 = Channel connects to SPI2_TX.
+ * | | |27 = Channel connects to SPI2_RX.
+ * | | |28 = Channel connects to SPI3_TX.
+ * | | |29 = Channel connects to SPI3_RX.
+ * | | |30 = Reserved.
+ * | | |31 = Reserved.
+ * | | |32 = Channel connects to EPWM0_P1_RX.
+ * | | |33 = Channel connects to EPWM0_P2_RX.
+ * | | |34 = Channel connects to EPWM0_P3_RX.
+ * | | |35 = Channel connects to EPWM1_P1_RX.
+ * | | |36 = Channel connects to EPWM1_P2_RX.
+ * | | |37 = Channel connects to EPWM1_P3_RX.
+ * | | |38 = Channel connects to I2C0_TX.
+ * | | |39 = Channel connects to I2C0_RX.
+ * | | |40 = Channel connects to I2C1_TX.
+ * | | |41 = Channel connects to I2C1_RX.
+ * | | |42 = Channel connects to I2C2_TX.
+ * | | |43 = Channel connects to I2C2_RX.
+ * | | |44 = Channel connects to I2S0_TX.
+ * | | |45 = Channel connects to I2S0_RX.
+ * | | |46 = Channel connects to TMR0.
+ * | | |47 = Channel connects to TMR1.
+ * | | |48 = Channel connects to TMR2.
+ * | | |49 = Channel connects to TMR3.
+ * | | |50 = Channel connects to ADC_RX.
+ * | | |51 = Channel connects to DAC0_TX.
+ * | | |52 = Channel connects to DAC1_TX.
+ * | | |53 = Channel connects to EPWM0_CH0_TX.
+ * | | |54 = Channel connects to EPWM0_CH1_TX.
+ * | | |55 = Channel connects to EPWM0_CH2_TX.
+ * | | |56 = Channel connects to EPWM0_CH3_TX.
+ * | | |57 = Channel connects to EPWM0_CH4_TX.
+ * | | |58 = Channel connects to EPWM0_CH5_TX.
+ * | | |59 = Channel connects to EPWM1_CH0_TX.
+ * | | |60 = Channel connects to EPWM1_CH1_TX.
+ * | | |61 = Channel connects to EPWM1_CH2_TX.
+ * | | |62 = Channel connects to EPWM1_CH3_TX.
+ * | | |63 = Channel connects to EPWM1_CH4_TX.
+ * | | |64 = Channel connects to EPWM1_CH5_TX.
+ * | | |65 = Channel connects to ETMC_RX.
+ * | | |Others = Reserved.
+ * | | |Note 1: A peripheral can't assign to two channels at the same time.
+ * | | |Note 2: This field is useless when transfer between memory and memory.
+ * |[14:8] |REQSRC1 |Channel 1 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 1
+ * | | |User can configure the peripheral setting by REQSRC1.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[22:16] |REQSRC2 |Channel 2 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 2
+ * | | |User can configure the peripheral setting by REQSRC2.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[30:24] |REQSRC3 |Channel 3 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 3
+ * | | |User can configure the peripheral setting by REQSRC3.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * @var PDMA_T::REQSEL4_7
+ * Offset: 0x484 PDMA Request Source Select Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |REQSRC4 |Channel 4 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 4
+ * | | |User can configure the peripheral setting by REQSRC4.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[14:8] |REQSRC5 |Channel 5 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 5
+ * | | |User can configure the peripheral setting by REQSRC5.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[22:16] |REQSRC6 |Channel 6 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 6
+ * | | |User can configure the peripheral setting by REQSRC6.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[30:24] |REQSRC7 |Channel 7 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 7
+ * | | |User can configure the peripheral setting by REQSRC7.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * @var PDMA_T::REQSEL8_11
+ * Offset: 0x488 PDMA Request Source Select Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |REQSRC8 |Channel 8 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 8
+ * | | |User can configure the peripheral setting by REQSRC8.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[14:8] |REQSRC9 |Channel 9 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 9
+ * | | |User can configure the peripheral setting by REQSRC9.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[22:16] |REQSRC10 |Channel 10 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 10
+ * | | |User can configure the peripheral setting by REQSRC10.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[30:24] |REQSRC11 |Channel 11 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 11
+ * | | |User can configure the peripheral setting by REQSRC11.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * @var PDMA_T::REQSEL12_15
+ * Offset: 0x48C PDMA Request Source Select Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |REQSRC12 |Channel 12 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 12
+ * | | |User can configure the peripheral setting by REQSRC12.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[14:8] |REQSRC13 |Channel 13 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 13
+ * | | |User can configure the peripheral setting by REQSRC13.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[22:16] |REQSRC14 |Channel 14 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 14
+ * | | |User can configure the peripheral setting by REQSRC14.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[30:24] |REQSRC15 |Channel 15 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 15
+ * | | |User can configure the peripheral setting by REQSRC15.
+ * | | |Note: The channel configuration is the same as REQSRC0 field
+ * | | |Please refer to the explanation of REQSRC0.
+ */
+ DSCT_T DSCT[16];
+ __I uint32_t CURSCAT[16]; /*!< [0x0100] Current Scatter-Gather Descriptor Table Address of PDMA Channel n */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[176];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */
+ __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */
+ __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */
+ __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */
+ __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */
+ __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */
+ __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */
+ __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */
+ __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */
+ __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */
+ __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */
+ __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */
+ __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */
+ __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */
+ __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */
+ __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */
+ __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch1 and Ch0 Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[7];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[7];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */
+ __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */
+ __IO uint32_t REQSEL8_11; /*!< [0x0488] PDMA Request Source Select Register 2 */
+ __IO uint32_t REQSEL12_15; /*!< [0x048c] PDMA Request Source Select Register 3 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE4[28];
+ /// @endcond //HIDDEN_SYMBOLS
+ STRIDE_T STRIDE[6];
+ /// @cond HIDDEN_SYMBOLS
+ __IO uint32_t RESERVE5[52];
+ /// @endcond //HIDDEN_SYMBOLS
+ REPEAT_T REPEAT[2];
+} PDMA_T;
+
+/**
+ @addtogroup PDMA_CONST PDMA Bit Field Definition
+ Constant Definitions for PDMA Controller
+@{ */
+
+#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */
+#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */
+
+#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */
+#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */
+
+#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */
+#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */
+
+#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */
+#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */
+
+#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */
+#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */
+
+#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */
+#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */
+
+#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */
+#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */
+
+#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */
+#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */
+
+#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */
+#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */
+
+#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */
+#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */
+
+#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */
+#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */
+
+#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */
+#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */
+
+#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */
+#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */
+
+#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */
+#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */
+
+#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
+#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
+
+#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
+#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
+
+#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */
+#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */
+
+#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
+#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
+
+#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
+#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
+
+#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
+#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
+
+#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
+#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
+
+#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
+#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
+
+#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
+#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
+
+#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
+#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
+
+#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */
+#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */
+
+#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */
+#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */
+
+#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */
+#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */
+
+#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */
+#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */
+
+#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */
+#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */
+
+#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */
+#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */
+
+#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */
+#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */
+
+#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */
+#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */
+
+#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */
+#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */
+
+#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */
+#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */
+
+#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */
+#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */
+
+#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */
+#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */
+
+#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */
+#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */
+
+#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */
+#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */
+
+#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */
+#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */
+
+#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */
+#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */
+
+#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */
+#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */
+
+#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */
+#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */
+
+#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */
+#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */
+
+#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */
+#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */
+
+#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */
+#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */
+
+#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */
+#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */
+
+#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */
+#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */
+
+#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */
+#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */
+
+#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */
+#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */
+
+#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */
+#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */
+
+#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */
+#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */
+
+#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */
+#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */
+
+#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */
+#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */
+
+#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */
+#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */
+
+#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */
+#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */
+
+#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */
+#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */
+
+#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */
+#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */
+
+#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */
+#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */
+
+#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */
+#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */
+
+#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */
+#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */
+
+#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
+#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
+
+#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */
+#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */
+
+#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */
+#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */
+
+#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
+#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
+
+#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
+#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
+
+#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
+#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
+
+#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
+#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
+
+#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
+#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
+
+#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */
+#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */
+
+#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
+#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
+
+#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
+#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
+
+#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
+#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
+
+#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
+#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
+
+#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
+#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
+
+#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
+#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
+
+#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
+#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
+
+#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
+#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
+
+#define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */
+#define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */
+
+#define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */
+#define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */
+
+#define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */
+#define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */
+
+#define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */
+#define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */
+
+#define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA_T::REQSEL12_15: REQSRC12 Position */
+#define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC12 Mask */
+
+#define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA_T::REQSEL12_15: REQSRC13 Position */
+#define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC13 Mask */
+
+#define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA_T::REQSEL12_15: REQSRC14 Position */
+#define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC14 Mask */
+
+#define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA_T::REQSEL12_15: REQSRC15 Position */
+#define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC15 Mask */
+
+#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */
+#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */
+
+#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */
+#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */
+
+#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */
+#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */
+
+#define PDMA_RCNTn_RCNT_Pos (0) /*!< PDMA_T::RCNTn: RCNT Position */
+#define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos) /*!< PDMA_T::RCNTn: RCNT Mask */
+
+#define PDMA_AICTLn_SAICNT_Pos (0) /*!< PDMA_T::AICTLn: SAICNT Position */
+#define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::AICTLn: SAICNT Mask */
+
+#define PDMA_AICTLn_DAICNT_Pos (16) /*!< PDMA_T::AICTLn: DAICNT Position */
+#define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::AICTLn: DAICNT Mask */
+
+/**@}*/ /* PDMA_CONST */
+/**@}*/ /* end of PDMA register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __PDMA_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qei_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qei_reg.h
new file mode 100644
index 00000000000..19de07545e2
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qei_reg.h
@@ -0,0 +1,315 @@
+/**************************************************************************//**
+ * @file qei_reg.h
+ * @version V1.00
+ * @brief QEI register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __QEI_REG_H__
+#define __QEI_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup QEI Quadrature Encoder Interface(QEI)
+ Memory Mapped Structure for QEI Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var QEI_T::CNT
+ * Offset: 0x00 QEI Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNT |Quadrature Encoder Interface Counter
+ * | | |A 32-bit up/down counter
+ * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF(QEI_STATUS[8]) is zero
+ * | | |This register performs an integrator which count value is proportional to the encoder position
+ * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:
+ * | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0.
+ * | | |2. Compare-match event if QEIEN(QEI_CTL[29])=1 and QEI is in compare-counting mode.
+ * | | |3. Index signal change if QEIEN(QEI_CTL[29])=1 and IDXRLDEN (QEI_CTL[27])=1.
+ * @var QEI_T::CNTHOLD
+ * Offset: 0x04 QEI Counter Hold Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold
+ * | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.
+ * @var QEI_T::CNTLATCH
+ * Offset: 0x08 QEI Counter Index Latch Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch
+ * | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.
+ * @var QEI_T::CNTCMP
+ * Offset: 0x0C QEI Counter Compare Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare
+ * | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set
+ * | | |This register is software writable.
+ * @var QEI_T::CNTMAX
+ * Offset: 0x14 QEI Pre-set Maximum Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count
+ * | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode
+ * @var QEI_T::CTL
+ * Offset: 0x18 QEI Controller Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
+ * | | |To determine the sampling frequency of the Noise Filter clock .
+ * | | |000 = QEI_CLK.
+ * | | |001 = QEI_CLK/2.
+ * | | |010 = QEI_CLK/4.
+ * | | |011 = QEI_CLK/16.
+ * | | |100 = QEI_CLK/32.
+ * | | |101 = QEI_CLK/64.
+ * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit
+ * | | |0 = The noise filter of QEI controller Enabled.
+ * | | |1 = The noise filter of QEI controller Disabled.
+ * |[4] |CHAEN |QEA Input to QEI Controller Enable Bit
+ * | | |0 = QEA input to QEI Controller Disabled.
+ * | | |1 = QEA input to QEI Controller Enabled.
+ * |[5] |CHBEN |QEB Input to QEI Controller Enable Bit
+ * | | |0 = QEB input to QEI Controller Disabled.
+ * | | |1 = QEB input to QEI Controller Enabled.
+ * |[6] |IDXEN |IDX Input to QEI Controller Enable Bit
+ * | | |0 = IDX input to QEI Controller Disabled.
+ * | | |1 = IDX input to QEI Controller Enabled.
+ * |[9:8] |MODE |QEI Counting Mode Selection
+ * | | |There are four quadrature encoder pulse counter operation modes.
+ * | | |00 = X4 Free-counting Mode.
+ * | | |01 = X2 Free-counting Mode.
+ * | | |10 = X4 Compare-counting Mode.
+ * | | |11 = X2 Compare-counting Mode.
+ * |[12] |CHAINV |Inverse QEA Input Polarity
+ * | | |0 = Not inverse QEA input polarity.
+ * | | |1 = QEA input polarity is inversed to QEI controller.
+ * |[13] |CHBINV |Inverse QEB Input Polarity
+ * | | |0 = Not inverse QEB input polarity.
+ * | | |1 = QEB input polarity is inversed to QEI controller.
+ * |[14] |IDXINV |Inverse IDX Input Polarity
+ * | | |0 = Not inverse IDX input polarity.
+ * | | |1 = IDX input polarity is inversed to QEI controller.
+ * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit
+ * | | |0 = OVUNF can trigger QEI controller interrupt Disabled.
+ * | | |1 = OVUNF can trigger QEI controller interrupt Enabled.
+ * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit
+ * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
+ * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
+ * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit
+ * | | |0 = CMPF can trigger QEI controller interrupt Disabled.
+ * | | |1 = CMPF can trigger QEI controller interrupt Enabled.
+ * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit
+ * | | |0 = The IDXF can trigger QEI interrupt Disabled.
+ * | | |1 = The IDXF can trigger QEI interrupt Enabled.
+ * |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0
+ * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
+ * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
+ * |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1
+ * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
+ * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
+ * |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2
+ * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
+ * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
+ * |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3
+ * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
+ * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
+ * |[24] |HOLDCNT |Hold QEI_CNT Control
+ * | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0])
+ * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
+ * | | |0 = No operation.
+ * | | |1 = QEI_CNT content is captured and stored in CNTHOLD(QEI_CNTHOLD[31:0]).
+ * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
+ * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit
+ * | | |If this bit is set to high, the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX.
+ * | | |0 = The index signal latch QEI counter function Disabled.
+ * | | |1 = The index signal latch QEI counter function Enabled.
+ * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit
+ * | | |When this bit is high and a rising edge comes on signal CHX, the CNT(QEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(QEI_STATUS[8]) = 1); while the CNT(QEI_CNT[31:0]) will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(QEI_STATUS[8]) = 0).
+ * | | |0 = Reload function Disabled.
+ * | | |1 = QEI_CNT re-initialized by Index signal Enabled.
+ * |[28] |CMPEN |The Compare Function Enable Bit
+ * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.
+ * | | |0 = Compare function Disabled.
+ * | | |1 = Compare function Enabled.
+ * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit
+ * | | |0 = QEI controller function Disabled.
+ * | | |1 = QEI controller function Enabled.
+ * @var QEI_T::STATUS
+ * Offset: 0x2C QEI Controller Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |IDXF |IDX Detected Flag
+ * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
+ * | | |0 = No rising edge detected on signal CHX.
+ * | | |1 = A rising edge occurs on signal CHX.
+ * | | |Note: This bit is only cleared by writing 1 to it.
+ * |[1] |CMPF |Compare-match Flag
+ * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).
+ * | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]).
+ * | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]).
+ * | | |Note: This bit is only cleared by writing 1 to it.
+ * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag
+ * | | |Flag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode
+ * | | |Similarly, the flag is set while QEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).
+ * | | |0 = No overflow or underflow occurs in QEI counter.
+ * | | |1 = QEI counter occurs counting overflow or underflow.
+ * | | |Note: This bit is only cleared by writing 1 to it.
+ * |[3] |DIRCHGF |Direction Change Flag
+ * | | |Flag is set by hardware while QEI counter counting direction is changed.
+ * | | |Software can clear this bit by writing 1 to it.
+ * | | |0 = No change in QEI counter counting direction.
+ * | | |1 = QEI counter counting direction is changed.
+ * | | |Note: This bit is only cleared by writing 1 to it.
+ * |[8] |DIRF |QEI Counter Counting Direction Indication
+ * | | |0 = QEI Counter is in down-counting.
+ * | | |1 = QEI Counter is in up-counting.
+ * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
+ */
+ __IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */
+ __IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */
+ __IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */
+ __IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */
+ __IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[4];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */
+
+} QEI_T;
+
+/**
+ @addtogroup QEI_CONST QEI Bit Field Definition
+ Constant Definitions for QEI Controller
+@{ */
+
+#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */
+#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */
+
+#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */
+#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */
+
+#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */
+#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */
+
+#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */
+#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */
+
+#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */
+#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */
+
+#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */
+#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */
+
+#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */
+#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */
+
+#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */
+#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */
+
+#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */
+#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */
+
+#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */
+#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */
+
+#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */
+#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */
+
+#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */
+#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */
+
+#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */
+#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */
+
+#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */
+#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */
+
+#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */
+#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */
+
+#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */
+#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */
+
+#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */
+#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */
+
+#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */
+#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */
+
+#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */
+#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */
+
+#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */
+#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */
+
+#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */
+#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */
+
+#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */
+#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */
+
+#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */
+#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */
+
+#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */
+#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */
+
+#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */
+#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */
+
+#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */
+#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */
+
+#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */
+#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */
+
+#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */
+#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */
+
+#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */
+#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */
+
+#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */
+#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */
+
+#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */
+#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */
+
+#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */
+#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */
+
+/**@}*/ /* QEI_CONST */
+/**@}*/ /* end of QEI register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __QEI_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qspi_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qspi_reg.h
new file mode 100644
index 00000000000..890fe5c78de
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qspi_reg.h
@@ -0,0 +1,592 @@
+/**************************************************************************//**
+ * @file qspi_reg.h
+ * @version V1.00
+ * @brief QSPI register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __QSPI_REG_H__
+#define __QSPI_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup QSPI Serial Peripheral Interface Controller(QSPI)
+ Memory Mapped Structure for QSPI Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var QSPI_T::CTL
+ * Offset: 0x00 QSPI Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |QSPIEN |QSPI Transfer Control Enable Bit
+ * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
+ * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
+ * | | |0 = Transfer control Disabled.
+ * | | |1 = Transfer control Enabled.
+ * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the QSPIEN (QSPIx_CTL[0]) and confirm the QSPIENSTS (QSPIx_STATUS[15]) is 0.
+ * |[1] |RXNEG |Receive on Negative Edge
+ * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock.
+ * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock.
+ * |[2] |TXNEG |Transmit on Negative Edge
+ * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock.
+ * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.
+ * |[3] |CLKPOL |Clock Polarity
+ * | | |0 = QSPI bus clock is idle low.
+ * | | |1 = QSPI bus clock is idle high.
+ * |[7:4] |SUSPITV |Suspend Interval (Master Only)
+ * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
+ * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
+ * | | |The default value is 0x3
+ * | | |The period of the suspend interval is obtained according to the following equation.
+ * | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle
+ * | | |Example:
+ * | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle.
+ * | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle.
+ * | | |.....
+ * | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle.
+ * | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle.
+ * |[12:8] |DWIDTH |Data Width
+ * | | |This field specifies how many bits can be transmitted / received in one transaction
+ * | | |The minimum bit length is 8 bits and can up to 32 bits.
+ * | | |DWIDTH = 0x08 .... 8 bits.
+ * | | |DWIDTH = 0x09 .... 9 bits.
+ * | | |.....
+ * | | |DWIDTH = 0x1F .... 31 bits.
+ * | | |DWIDTH = 0x00 .... 32 bits.
+ * |[13] |LSB |Send LSB First
+ * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
+ * | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX).
+ * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit
+ * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer
+ * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
+ * | | |0 = QSPI operates in full-duplex transfer.
+ * | | |1 = QSPI operates in half-duplex transfer.
+ * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
+ * | | |This bit field is only available in Master mode
+ * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status.
+ * | | |0 = Receive-only mode Disabled.
+ * | | |1 = Receive-only mode Enabled.
+ * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in QSPI0)
+ * | | |0 = 2-Bit Transfer mode Disabled.
+ * | | |1 = 2-Bit Transfer mode Enabled.
+ * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
+ * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
+ * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
+ * | | |0 = QSPI unit transfer interrupt Disabled.
+ * | | |1 = QSPI unit transfer interrupt Enabled.
+ * |[18] |SLAVE |Slave Mode Control
+ * | | |0 = Master mode.
+ * | | |1 = Slave mode.
+ * |[19] |REORDER |Byte Reorder Function Enable Bit
+ * | | |0 = Byte Reorder function Disabled.
+ * | | |1 = Byte Reorder function Enabled
+ * | | |A byte suspend interval will be inserted among each byte
+ * | | |The period of the byte suspend interval depends on the setting of SUSPITV.
+ * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
+ * |[20] |DATDIR |Data Port Direction Control
+ * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
+ * | | |0 = QSPI data is input direction.
+ * | | |1 = QSPI data is output direction.
+ * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in QSPI0)
+ * | | |0 = Dual I/O mode Disabled.
+ * | | |1 = Dual I/O mode Enabled.
+ * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in QSPI0)
+ * | | |0 = Quad I/O mode Disabled.
+ * | | |1 = Quad I/O mode Enabled.
+ * @var QSPI_T::CLKDIV
+ * Offset: 0x04 QSPI Clock Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |DIVIDER |Clock Divider
+ * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master
+ * | | |The frequency is obtained according to the following equation.
+ * | | |where
+ * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
+ * @var QSPI_T::SSCTL
+ * Offset: 0x08 QSPI Slave Select Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SS |Slave Selection Control (Master Only)
+ * | | |If AUTOSS bit is cleared to 0,
+ * | | |0 = set the QSPIx_SS line to inactive state.
+ * | | |1 = set the QSPIx_SS line to active state.
+ * | | |If the AUTOSS bit is set to 1,
+ * | | |0 = Keep the QSPIx_SS line at inactive state.
+ * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
+ * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]).
+ * |[2] |SSACTPOL |Slave Selection Active Polarity
+ * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS).
+ * | | |0 = The slave selection signal QSPIx_SS is active low.
+ * | | |1 = The slave selection signal QSPIx_SS is active high.
+ * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
+ * | | |0 = Automatic slave selection function Disabled
+ * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]).
+ * | | |1 = Automatic slave selection function Enabled.
+ * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in QSPI0)
+ * | | |Slave 3-wire mode is only available in QSPI0
+ * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins.
+ * | | |0 = 4-wire bi-direction interface.
+ * | | |1 = 3-wire bi-direction interface.
+ * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in QSPI0)
+ * | | |0 = Slave mode time-out interrupt Disabled.
+ * | | |1 = Slave mode time-out interrupt Enabled.
+ * |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in QSPI0)
+ * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
+ * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
+ * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
+ * | | |0 = Slave mode bit count error interrupt Disabled.
+ * | | |1 = Slave mode bit count error interrupt Enabled.
+ * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
+ * | | |0 = Slave mode TX under run interrupt Disabled.
+ * | | |1 = Slave mode TX under run interrupt Enabled.
+ * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
+ * | | |0 = Slave select active interrupt Disabled.
+ * | | |1 = Slave select active interrupt Enabled.
+ * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
+ * | | |0 = Slave select inactive interrupt Disabled.
+ * | | |1 = Slave select inactive interrupt Enabled.
+ * |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in QSPI0)
+ * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
+ * | | |The clock source of the time-out counter is Slave peripheral clock
+ * | | |If the value is 0, it indicates the slave mode time-out function is disabled.
+ * @var QSPI_T::PDMACTL
+ * Offset: 0x0C QSPI PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TXPDMAEN |Transmit PDMA Enable Bit
+ * | | |0 = Transmit PDMA function Disabled.
+ * | | |1 = Transmit PDMA function Enabled.
+ * | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
+ * | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
+ * |[1] |RXPDMAEN |Receive PDMA Enable Bit
+ * | | |0 = Receive PDMA function Disabled.
+ * | | |1 = Receive PDMA function Enabled.
+ * |[2] |PDMARST |PDMA Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.
+ * @var QSPI_T::FIFOCTL
+ * Offset: 0x10 QSPI FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXRST |Receive Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset receive FIFO pointer and receive circuit
+ * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
+ * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
+ * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
+ * |[1] |TXRST |Transmit Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset transmit FIFO pointer and transmit circuit
+ * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
+ * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
+ * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
+ * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
+ * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
+ * | | |0 = RX FIFO threshold interrupt Disabled.
+ * | | |1 = RX FIFO threshold interrupt Enabled.
+ * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
+ * | | |0 = TX FIFO threshold interrupt Disabled.
+ * | | |1 = TX FIFO threshold interrupt Enabled.
+ * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
+ * | | |0 = Receive time-out interrupt Disabled.
+ * | | |1 = Receive time-out interrupt Enabled.
+ * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
+ * | | |0 = Receive FIFO overrun interrupt Disabled.
+ * | | |1 = Receive FIFO overrun interrupt Enabled.
+ * |[6] |TXUFPOL |TX Underflow Data Polarity
+ * | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode.
+ * | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode.
+ * | | |Note:
+ * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
+ * | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
+ * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
+ * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
+ * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1
+ * | | |This bit is used to enable the TX underflow interrupt.
+ * | | |0 = Slave TX underflow interrupt Disabled.
+ * | | |1 = Slave TX underflow interrupt Enabled.
+ * |[8] |RXFBCLR |Receive FIFO Buffer Clear
+ * | | |0 = No effect.
+ * | | |1 = Clear receive FIFO pointer
+ * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
+ * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+ * | | |Note: The RX shift register will not be cleared.
+ * |[9] |TXFBCLR |Transmit FIFO Buffer Clear
+ * | | |0 = No effect.
+ * | | |1 = Clear transmit FIFO pointer
+ * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
+ * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+ * | | |Note: The TX shift register will not be cleared.
+ * |[26:24] |RXTH |Receive FIFO Threshold
+ * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
+ * |[30:28] |TXTH |Transmit FIFO Threshold
+ * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
+ * @var QSPI_T::STATUS
+ * Offset: 0x14 QSPI Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSY |Busy Status (Read Only)
+ * | | |0 = QSPI controller is in idle state.
+ * | | |1 = QSPI controller is in busy state.
+ * | | |The following listing are the bus busy conditions:
+ * | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0.
+ * | | |b
+ * | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
+ * | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1.
+ * | | |d
+ * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active.
+ * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
+ * |[1] |UNITIF |Unit Transfer Interrupt Flag
+ * | | |0 = No transaction has been finished since this bit was cleared to 0.
+ * | | |1 = QSPI controller has finished one unit transfer.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[2] |SSACTIF |Slave Select Active Interrupt Flag
+ * | | |0 = Slave select active interrupt was cleared or not occurred.
+ * | | |1 = Slave select active interrupt event occurred.
+ * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+ * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
+ * | | |0 = Slave select inactive interrupt was cleared or not occurred.
+ * | | |1 = Slave select inactive interrupt event occurred.
+ * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+ * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
+ * | | |0 = The slave select line status is 0.
+ * | | |1 = The slave select line status is 1.
+ * | | |Note: This bit is only available in Slave mode
+ * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
+ * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in QSPI0)
+ * | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started
+ * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
+ * | | |0 = Slave time-out is not active.
+ * | | |1 = Slave time-out is active.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
+ * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
+ * | | |0 = No Slave mode bit count error event.
+ * | | |1 = Slave mode bit count error event occurs.
+ * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
+ * | | |This bit will be cleared by writing 1 to it.
+ * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
+ * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
+ * | | |0 = No Slave TX under run event.
+ * | | |1 = Slave TX under run event occurs.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
+ * | | |0 = Receive FIFO buffer is not empty.
+ * | | |1 = Receive FIFO buffer is empty.
+ * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
+ * | | |0 = Receive FIFO buffer is not full.
+ * | | |1 = Receive FIFO buffer is full.
+ * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
+ * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+ * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
+ * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+ * | | |0 = No FIFO is overrun.
+ * | | |1 = Receive FIFO is overrun.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[12] |RXTOIF |Receive Time-out Interrupt Flag
+ * | | |0 = No receive FIFO time-out event.
+ * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode
+ * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[15] |QSPIENSTS |QSPI Enable Status (Read Only)
+ * | | |0 = The QSPI controller is disabled.
+ * | | |1 = The QSPI controller is enabled.
+ * | | |Note: The QSPI peripheral clock is asynchronous with the system clock
+ * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
+ * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
+ * | | |0 = Transmit FIFO buffer is not empty.
+ * | | |1 = Transmit FIFO buffer is empty.
+ * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
+ * | | |0 = Transmit FIFO buffer is not full.
+ * | | |1 = Transmit FIFO buffer is full.
+ * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+ * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+ * |[19] |TXUFIF |TX Underflow Interrupt Flag
+ * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
+ * | | |0 = No effect.
+ * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
+ * | | |Note 1: This bit will be cleared by writing 1 to it.
+ * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
+ * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
+ * | | |0 = The reset function of TXRST or RXRST is done.
+ * | | |1 = Doing the reset function of TXRST or RXRST.
+ * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
+ * | | |User can check the status of this bit to monitor the reset function is doing or done.
+ * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
+ * | | |This bit field indicates the valid data count of receive FIFO buffer.
+ * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
+ * | | |This bit field indicates the valid data count of transmit FIFO buffer.
+ * @var QSPI_T::TX
+ * Offset: 0x20 QSPI Data Transmit Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TX |Data Transmit Register
+ * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
+ * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in SPI mode.
+ * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
+ * | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer.
+ * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid
+ * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
+ * @var QSPI_T::RX
+ * Offset: 0x30 QSPI Data Receive Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RX |Data Receive Register
+ * | | |There are 4-level FIFO buffers in this controller
+ * | | |The data receive register holds the data received from QSPI data input pin
+ * | | |This is a read only register.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */
+ __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */
+ __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */
+ __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */
+ __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */
+ __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */
+
+} QSPI_T;
+
+/**
+ @addtogroup QSPI_CONST QSPI Bit Field Definition
+ Constant Definitions for QSPI Controller
+@{ */
+
+#define QSPI_CTL_QSPIEN_Pos (0) /*!< QSPI_T::CTL: QSPIEN Position */
+#define QSPI_CTL_QSPIEN_Msk (0x1ul << QSPI_CTL_QSPIEN_Pos) /*!< QSPI_T::CTL: QSPIEN Mask */
+
+#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */
+#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */
+
+#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */
+#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */
+
+#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */
+#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */
+
+#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */
+#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */
+
+#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */
+#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */
+
+#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */
+#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */
+
+#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */
+#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */
+
+#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */
+#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */
+
+#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */
+#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */
+
+#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */
+#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */
+
+#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */
+#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */
+
+#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */
+#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */
+
+#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */
+#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */
+
+#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */
+#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */
+
+#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */
+#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */
+
+#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */
+#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */
+
+#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */
+#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */
+
+#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */
+#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */
+
+#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */
+#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */
+
+#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */
+#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */
+
+#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */
+#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */
+
+#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */
+#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */
+
+#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */
+#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */
+
+#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */
+#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */
+
+#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */
+#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */
+
+#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */
+#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */
+
+#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */
+#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */
+
+#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */
+#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */
+
+#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */
+#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */
+
+#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */
+#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */
+
+#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */
+#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */
+
+#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */
+#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */
+
+#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */
+#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */
+
+#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */
+#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */
+
+#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */
+#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */
+
+#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */
+#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */
+
+#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */
+#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */
+
+#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */
+#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */
+
+#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */
+#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */
+
+#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */
+#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */
+
+#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */
+#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */
+
+#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */
+#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */
+
+#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */
+#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */
+
+#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */
+#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */
+
+#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */
+#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */
+
+#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */
+#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */
+
+#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */
+#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */
+
+#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */
+#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */
+
+#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */
+#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */
+
+#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */
+#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */
+
+#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */
+#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */
+
+#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */
+#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */
+
+#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */
+#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */
+
+#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */
+#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */
+
+#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */
+#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */
+
+#define QSPI_STATUS_QSPIENSTS_Pos (15) /*!< QSPI_T::STATUS: QSPIENSTS Position */
+#define QSPI_STATUS_QSPIENSTS_Msk (0x1ul << QSPI_STATUS_QSPIENSTS_Pos) /*!< QSPI_T::STATUS: QSPIENSTS Mask */
+
+#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */
+#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */
+
+#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */
+#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */
+
+#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */
+#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */
+
+#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */
+#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */
+
+#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */
+#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */
+
+#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */
+#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */
+
+#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */
+#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */
+
+#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */
+#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */
+
+#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */
+#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */
+
+
+/**@}*/ /* QSPI_CONST */
+/**@}*/ /* end of QSPI register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __QSPI_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/rtc_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/rtc_reg.h
new file mode 100644
index 00000000000..644d8e48566
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/rtc_reg.h
@@ -0,0 +1,1274 @@
+/**************************************************************************//**
+ * @file rtc_reg.h
+ * @version V1.00
+ * @brief RTC register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __RTC_REG_H__
+#define __RTC_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup RTC Real Time Clock Controller(RTC)
+ Memory Mapped Structure for RTC Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var RTC_T::INIT
+ * Offset: 0x00 RTC Initiation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INIT_ACTIVE|RTC Active Status (Read Only)
+ * | | |0 = RTC is at reset state.
+ * | | |1 = RTC is at normal active state.
+ * |[31:1] |INIT |RTC Initiation (Write Only)
+ * | | |When RTC block is powered on, RTC is at reset state
+ * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leaving reset state
+ * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
+ * | | |The INIT is a write-only field and read value will be always 0.
+ * @var RTC_T::RWEN
+ * Offset: 0x04 RTC Access Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
+ * | | |0 = RTC register read/write Disabled.
+ * | | |1 = RTC register read/write Enabled.
+ * | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.
+ * |[24] |RTCBUSY |RTC Write Busy Flag
+ * | | |This bit indicates RTC registers are writable or not.
+ * | | |0: RTC registers are writable.
+ * | | |1: RTC registers can't write, RTC under Busy Status.
+ * | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles.
+ * @var RTC_T::FREQADJ
+ * Offset: 0x08 RTC Frequency Compensation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[21:0] |FREQADJ |Frequency Compensation Register (M480)
+ * | | |User must to get actual LXT frequency for RTC application.
+ * | | |FCR = 0x200000 * (32768 / LXT frequency).
+ * | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0.
+ * |[5:0] |FRACTION |Fraction Part (M480LD)
+ * | | |Formula: FRACTION = (fraction part of detected value) X 64.
+ * | | |Note: Digit in FCR must be expressed as hexadecimal number.
+ * |[12:8] |INTEGER |Integer Part (M480LD)
+ * | | |00000 = Integer part of detected value is 32752.
+ * | | |00001 = Integer part of detected value is 32753.
+ * | | |00010 = Integer part of detected value is 32754.
+ * | | |00011 = Integer part of detected value is 32755.
+ * | | |00100 = Integer part of detected value is 32756.
+ * | | |00101 = Integer part of detected value is 32757.
+ * | | |00110 = Integer part of detected value is 32758.
+ * | | |00111 = Integer part of detected value is 32759.
+ * | | |01000 = Integer part of detected value is 32760.
+ * | | |01001 = Integer part of detected value is 32761.
+ * | | |01010 = Integer part of detected value is 32762.
+ * | | |01011 = Integer part of detected value is 32763.
+ * | | |01100 = Integer part of detected value is 32764.
+ * | | |01101 = Integer part of detected value is 32765.
+ * | | |01110 = Integer part of detected value is 32766.
+ * | | |01111 = Integer part of detected value is 32767.
+ * | | |10000 = Integer part of detected value is 32768.
+ * | | |10001 = Integer part of detected value is 32769.
+ * | | |10010 = Integer part of detected value is 32770.
+ * | | |10011 = Integer part of detected value is 32771.
+ * | | |10100 = Integer part of detected value is 32772.
+ * | | |10101 = Integer part of detected value is 32773.
+ * | | |10110 = Integer part of detected value is 32774.
+ * | | |10111 = Integer part of detected value is 32775.
+ * | | |11000 = Integer part of detected value is 32776.
+ * | | |11001 = Integer part of detected value is 32777.
+ * | | |11010 = Integer part of detected value is 32778.
+ * | | |11011 = Integer part of detected value is 32779.
+ * | | |11100 = Integer part of detected value is 32780.
+ * | | |11101 = Integer part of detected value is 32781.
+ * | | |11110 = Integer part of detected value is 32782.
+ * | | |11111 = Integer part of detected value is 32783.
+ * |[31] |FCR_BUSY |Frequency Compensation Register Write Operation Busy (Read Only) (M480LD)
+ * | | |0 = The new register write operation is acceptable.
+ * | | |1 = The last write operation is in progress and new register write operation prohibited.
+ * | | |Note: This bit is only used when DYN_COMP_EN(RTC_CLKFMT[16]) enabled.
+ * @var RTC_T::TIME
+ * Offset: 0x0C RTC Time Loading Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SEC |1-Sec Time Digit (0~9)
+ * |[6:4] |TENSEC |10-Sec Time Digit (0~5)
+ * |[11:8] |MIN |1-Min Time Digit (0~9)
+ * |[14:12] |TENMIN |10-Min Time Digit (0~5)
+ * |[19:16] |HR |1-Hour Time Digit (0~9)
+ * |[21:20] |TENHR |10-Hour Time Digit (0~2)
+ * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication
+ * | | |(If RTC_TIME[21] is 1, it indicates PM time message).
+ * @var RTC_T::CAL
+ * Offset: 0x10 RTC Calendar Loading Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DAY |1-Day Calendar Digit (0~9)
+ * |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
+ * |[11:8] |MON |1-Month Calendar Digit (0~9)
+ * |[12] |TENMON |10-Month Calendar Digit (0~1)
+ * |[19:16] |YEAR |1-Year Calendar Digit (0~9)
+ * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
+ * @var RTC_T::CLKFMT
+ * Offset: 0x14 RTC Time Scale Selection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |24HEN |24-hour / 12-hour Time Scale Selection
+ * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
+ * | | |0 = 12-hour time scale with AM and PM indication selected.
+ * | | |1 = 24-hour time scale selected.
+ * @var RTC_T::WEEKDAY
+ * Offset: 0x18 RTC Day of the Week Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |WEEKDAY |Day of the Week Register
+ * | | |000 = Sunday.
+ * | | |001 = Monday.
+ * | | |010 = Tuesday.
+ * | | |011 = Wednesday.
+ * | | |100 = Thursday.
+ * | | |101 = Friday.
+ * | | |110 = Saturday.
+ * | | |111 = Reserved.
+ * @var RTC_T::TALM
+ * Offset: 0x1C RTC Time Alarm Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
+ * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
+ * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
+ * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
+ * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
+ * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
+ * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication
+ * | | |(If RTC_TIME[21] is 1, it indicates PM time message).
+ * @var RTC_T::CALM
+ * Offset: 0x20 RTC Calendar Alarm Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
+ * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
+ * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
+ * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
+ * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
+ * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
+ * @var RTC_T::LEAPYEAR
+ * Offset: 0x24 RTC Leap Year Indicator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
+ * | | |0 = This year is not a leap year.
+ * | | |1 = This year is leap year.
+ * @var RTC_T::INTEN
+ * Offset: 0x28 RTC Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ALMIEN |Alarm Interrupt Enable Bit
+ * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
+ * | | |0 = RTC Alarm interrupt Disabled.
+ * | | |1 = RTC Alarm interrupt Enabled.
+ * |[1] |TICKIEN |Time Tick Interrupt Enable Bit
+ * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
+ * | | |0 = RTC Time Tick interrupt Disabled.
+ * | | |1 = RTC Time Tick interrupt Enabled.
+ * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit
+ * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
+ * | | |0 = Tamper 0 interrupt Disabled.
+ * | | |1 = Tamper 0 interrupt Enabled.
+ * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit
+ * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated.
+ * | | |0 = Tamper 1 or Pair 0 interrupt Disabled.
+ * | | |1 = Tamper 1 or Pair 0 interrupt Enabled.
+ * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit
+ * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated.
+ * | | |0 = Tamper 2 interrupt Disabled.
+ * | | |1 = Tamper 2 interrupt Enabled.
+ * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit
+ * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated.
+ * | | |0 = Tamper 3 or Pair 1 interrupt Disabled.
+ * | | |1 = Tamper 3 or Pair 1 interrupt Enabled.
+ * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit
+ * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated.
+ * | | |0 = Tamper 4 interrupt Disabled.
+ * | | |1 = Tamper 4 interrupt Enabled.
+ * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit
+ * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated.
+ * | | |0 = Tamper 5 or Pair 2 interrupt Disabled.
+ * | | |1 = Tamper 5 or Pair 2 interrupt Enabled.
+ * @var RTC_T::INTSTS
+ * Offset: 0x2C RTC Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ALMIF |RTC Alarm Interrupt Flag
+ * | | |0 = Alarm condition is not matched.
+ * | | |1 = Alarm condition is matched.
+ * | | |Note: Write 1 to clear this bit.
+ * |[1] |TICKIF |RTC Time Tick Interrupt Flag
+ * | | |0 = Tick condition does not occur.
+ * | | |1 = Tick condition occur.
+ * | | |Note: Write 1 to clear this bit.
+ * |[8] |TAMP0IF |Tamper 0 Interrupt Flag
+ * | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).
+ * | | |0 = No Tamper 0 interrupt flag is generated.
+ * | | |1 = Tamper 0 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag
+ * | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13])
+ * | | |or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.
+ * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated.
+ * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * |[10] |TAMP2IF |Tamper 2 Interrupt Flag
+ * | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).
+ * | | |0 = No Tamper 2 interrupt flag is generated.
+ * | | |1 = Tamper 2 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag
+ * | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21])
+ * | | |or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated
+ * | | |or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated.
+ * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated.
+ * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * |[12] |TAMP4IF |Tamper 4 Interrupt Flag
+ * | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).
+ * | | |0 = No Tamper 4 interrupt flag is generated.
+ * | | |1 = Tamper 4 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag
+ * | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29])
+ * | | |or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated
+ * | | |or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated.
+ * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated.
+ * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * @var RTC_T::TICK
+ * Offset: 0x30 RTC Time Tick Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |TICK |Time Tick Register
+ * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
+ * | | |000 = Time tick is 1 second.
+ * | | |001 = Time tick is 1/2 second.
+ * | | |010 = Time tick is 1/4 second.
+ * | | |011 = Time tick is 1/8 second.
+ * | | |100 = Time tick is 1/16 second.
+ * | | |101 = Time tick is 1/32 second.
+ * | | |110 = Time tick is 1/64 second.
+ * | | |111 = Time tick is 1/128 second.
+ * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
+ * @var RTC_T::TAMSK
+ * Offset: 0x34 RTC Time Alarm Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
+ * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
+ * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
+ * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
+ * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
+ * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
+ * @var RTC_T::CAMSK
+ * Offset: 0x38 RTC Calendar Alarm Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
+ * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
+ * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
+ * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
+ * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
+ * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
+ * @var RTC_T::SPRCTL
+ * Offset: 0x3C RTC Spare Functional Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2] |SPRRWEN |Spare Register Enable Bit
+ * | | |0 = Spare register is Disabled.
+ * | | |1 = Spare register is Enabled.
+ * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
+ * |[5] |SPRCSTS |SPR Clear Flag
+ * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected.
+ * | | |0 = Spare register content is not cleared.
+ * | | |1 = Spare register content is cleared.
+ * | | |Writes 1 to clear this bit.
+ * | | |Note: This bit keep 1 when RTC_INTSTS[13:8] not equal zero.
+ * @var RTC_T::SPR[20]
+ * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SPARE |Spare Register
+ * | | |This field is used to store back-up information defined by user.
+ * | | |This field will be cleared by hardware automatically once a tamper pin event is detected.
+ * | | |Before storing back-up information in to RTC_SPRx register,
+ * | | |user should check REWNF (RTC_RWEN[16]) is enabled.
+ * @var RTC_T::LXTCTL
+ * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:1] |GAIN |Oscillator Gain Option
+ * | | |User can select oscillator gain according to crystal external loading and operating temperature range
+ * | | |The larger gain value corresponding to stronger driving capability and higher power consumption.
+ * | | |00 = L0 mode.
+ * | | |01 = L1 mode.
+ * | | |10 = L2 mode.
+ * | | |11 = L3 mode.
+ * @var RTC_T::GPIOCTL0
+ * Offset: 0x104 RTC GPIO Control 0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |OPMODE0 |IO Operation Mode
+ * | | |00 = PF.4 is input only mode, without pull-up resistor.
+ * | | |01 = PF.4 is output push pull mode.
+ * | | |10 = PF.4 is open drain mode.
+ * | | |11 = PF.4 is quasi-bidirectional mode with internal pull up.
+ * |[2] |DOUT0 |IO Output Data
+ * | | |0 = PF.4 output low.
+ * | | |1 = PF.4 output high.
+ * |[3] |CTLSEL0 |IO Pin State Backup Selection
+ * | | |When low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function
+ * | | |User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL0 control register.
+ * | | |0 = PF.4 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off.
+ * | | |1 = PF.4 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.
+ * | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.4 I/O pull-up or pull-down.
+ * | | |00 = PF.4 pull-up and pull-up disable.
+ * | | |01 = PF.4 pull-down enable.
+ * | | |10 = PF.4 pull-up enable.
+ * | | |11 = PF.4 pull-up and pull-up disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode.
+ * |[9:8] |OPMODE1 |IO Operation Mode
+ * | | |00 = PF.5 is input only mode, without pull-up resistor.
+ * | | |01 = PF.5 is output push pull mode.
+ * | | |10 = PF.5 is open drain mode.
+ * | | |11 = PF.5 is quasi-bidirectional mode with internal pull up.
+ * |[10] |DOUT1 |IO Output Data
+ * | | |0 = PF.5 output low.
+ * | | |1 = PF.5 output high.
+ * |[11] |CTLSEL1 |IO Pin State Backup Selection
+ * | | |When low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function
+ * | | |User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL0 control register.
+ * | | |0 = PF.5 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off.
+ * | | |1 = PF.5 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.
+ * | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.5 I/O pull-up or pull-down.
+ * | | |00 = PF.5 pull-up and pull-up disable.
+ * | | |01 = PF.5 pull-down enable.
+ * | | |10 = PF.5 pull-up enable.
+ * | | |11 = PF.5 pull-up and pull-up disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode.
+ * |[17:16] |OPMODE2 |IO Operation Mode
+ * | | |00 = PF.6 is input only mode, without pull-up resistor.
+ * | | |01 = PF.6 is output push pull mode.
+ * | | |10 = PF.6 is open drain mode.
+ * | | |11 = PF.6 is quasi-bidirectional mode with internal pull up.
+ * |[18] |DOUT2 |IO Output Data
+ * | | |0 = PF.6 output low.
+ * | | |1 = PF.6 output high.
+ * |[19] |CTLSEL2 |IO Pin State Backup Selection
+ * | | |When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function
+ * | | |User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL0 control register.
+ * | | |0 = PF.6 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off.
+ * | | |1 = PF.6 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.
+ * | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.6 I/O pull-up or pull-down.
+ * | | |00 = PF.6 pull-up and pull-up disable.
+ * | | |01 = PF.6 pull-down enable.
+ * | | |10 = PF.6 pull-up enable.
+ * | | |11 = PF.6 pull-up and pull-up disable.
+ * | | |Note1:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode.
+ * |[25:24] |OPMODE3 |IO Operation Mode
+ * | | |00 = PF.7 is input only mode, without pull-up resistor.
+ * | | |01 = PF.7 is output push pull mode.
+ * | | |10 = PF.7 is open drain mode.
+ * | | |11 = PF.7 is quasi-bidirectional mode.
+ * |[26] |DOUT3 |IO Output Data
+ * | | |0 = PF.7 output low.
+ * | | |1 = PF.7 output high.
+ * |[27] |CTLSEL3 |IO Pin State Backup Selection
+ * | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function
+ * | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL0 control register.
+ * | | |0 = PF.7 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off.
+ * | | |1 = PF.7 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1.
+ * | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
+ * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.7 I/O pull-up or pull-down.
+ * | | |00 = PF.7 pull-up and pull-down disable.
+ * | | |01 = PF.7 pull-down enable.
+ * | | |10 = PF.7 pull-up enable.
+ * | | |11 = PF.7 pull-up and pull-down disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode.
+ * @var RTC_T::GPIOCTL1
+ * Offset: 0x108 RTC GPIO Control 1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |OPMODE4 |IO Operation Mode
+ * | | |00 = PF.8 is input only mode, without pull-up resistor.
+ * | | |01 = PF.8 is output push pull mode.
+ * | | |10 = PF.8 is open drain mode.
+ * | | |11 = PF.8 is quasi-bidirectional mode.
+ * |[2] |DOUT4 |IO Output Data
+ * | | |0 = PF.8 output low.
+ * | | |1 = PF.8 output high.
+ * |[3] |CTLSEL4 |IO Pin State Backup Selection
+ * | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function
+ * | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL1 control register.
+ * | | |0 = PF.8 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off.
+ * | | |1 = PF.8 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1.
+ * | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
+ * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.8 I/O pull-up or pull-down.
+ * | | |00 = PF.8 pull-up and pull-down disable.
+ * | | |01 = PF.8 pull-down enable.
+ * | | |10 = PF.8 pull-up enable.
+ * | | |11 = PF.8 pull-up and pull-down disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode.
+ * |[9:8] |OPMODE5 |IO Operation Mode
+ * | | |00 = PF.9 is input only mode, without pull-up resistor.
+ * | | |01 = PF.9 is output push pull mode.
+ * | | |10 = PF.9 is open drain mode.
+ * | | |11 = PF.9 is quasi-bidirectional mode.
+ * |[10] |DOUT5 |IO Output Data
+ * | | |0 = PF.9 output low.
+ * | | |1 = PF.9 output high.
+ * |[11] |CTLSEL5 |IO Pin State Backup Selection
+ * | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function
+ * | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL1 control register.
+ * | | |0 = PF.9 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off.
+ * | | |1 = PF.9 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1.
+ * | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.9 I/O pull-up or pull-down.
+ * | | |00 = PF.9 pull-up and pull-down disable.
+ * | | |01 = PF.9 pull-down enable.
+ * | | |10 = PF.9 pull-up enable.
+ * | | |11 = PF.9 pull-up and pull-down disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode.
+ * |[17:16] |OPMODE6 |IO Operation Mode
+ * | | |00 = PF.10 is input only mode, without pull-up resistor.
+ * | | |01 = PF.10 is output push pull mode.
+ * | | |10 = PF.10 is open drain mode.
+ * | | |11 = PF.10 is quasi-bidirectional mode.
+ * |[18] |DOUT6 |IO Output Data
+ * | | |0 = PF.10 output low.
+ * | | |1 = PF.10 output high.
+ * |[19] |CTLSEL6 |IO Pin State Backup Selection
+ * | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function
+ * | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL1 control register.
+ * | | |0 = PF.10 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off.
+ * | | |1 = PF.10 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1.
+ * | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.10 I/O pull-up or pull-down.
+ * | | |00 = PF.10 pull-up and pull-down disable.
+ * | | |01 = PF.10 pull-down enable.
+ * | | |10 = PF.10 pull-up enable.
+ * | | |11 = PF.10 pull-up and pull-down disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode.
+ * |[25:24] |OPMODE7 |IO Operation Mode
+ * | | |00 = PF.11 is input only mode, without pull-up resistor.
+ * | | |01 = PF.11 is output push pull mode.
+ * | | |10 = PF.11 is open drain mode.
+ * | | |11 = PF.11 is quasi-bidirectional mode.
+ * |[26] |DOUT7 |IO Output Data
+ * | | |0 = PF.11 output low.
+ * | | |1 = PF.11 output high.
+ * |[27] |CTLSEL7 |IO Pin State Backup Selection
+ * | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function
+ * | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL1 control register.
+ * | | |0 = PF.11 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off.
+ * | | |1 = PF.11 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1.
+ * | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.11 I/O pull-up or pull-down.
+ * | | |00 = PF.11 pull-up and pull-down disable.
+ * | | |01 = PF.11 pull-down enable.
+ * | | |10 = PF.11 pull-up enable.
+ * | | |11 = PF.11 pull-up and pull-down disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode.
+ * @var RTC_T::DSTCTL
+ * Offset: 0x110 RTC Daylight Saving Time Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADDHR |Add 1 Hour
+ * | | |0 = No effect.
+ * | | |1 = Indicates RTC hour digit has been added one hour for summer time change.
+ * |[1] |SUBHR |Subtract 1 Hour
+ * | | |0 = No effect.
+ * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change.
+ * |[2] |DSBAK |Daylight Saving Back
+ * | | |0= Normal mode.
+ * | | |1= Daylight saving mode.
+ * @var RTC_T::TAMPCTL
+ * Offset: 0x120 RTC Tamper Pin Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select
+ * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.
+ * | | |0 = Tamper input is from Tamper 2.
+ * | | |1 = Tamper input is from Tamper 0.
+ * | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
+ * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select
+ * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.
+ * | | |0 = Tamper input is from Tamper 4.
+ * | | |1 = Tamper input is from Tamper 0.
+ * | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
+ * |[3:2] |DYNSRC |Dynamic Reference Pattern
+ * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode.
+ * | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out.
+ * | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out.
+ * | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out.
+ * | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set.
+ * |[4] |SEEDRLD |Reload New Seed for PRNG Engine
+ * | | |Setting this bit, the tamper configuration will be reload.
+ * | | |0 = Generating key based on the current seed.
+ * | | |1 = Reload new seed.
+ * | | |Note: Before set this bit, the tamper configuration should be set to complete.
+ * |[7:5] |DYNRATE |Dynamic Change Rate
+ * | | |This item is choice the dynamic tamper output change rate.
+ * | | |000 = 210 * RTC_CLK.
+ * | | |001 = 211 * RTC_CLK.
+ * | | |010 = 212 * RTC_CLK.
+ * | | |011 = 213 * RTC_CLK.
+ * | | |100 = 214 * RTC_CLK.
+ * | | |101 = 215 * RTC_CLK.
+ * | | |110 = 216 * RTC_CLK.
+ * | | |111 = 217 * RTC_CLK.
+ * | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately.
+ * |[8] |TAMP0EN |Tamper0 Detect Enable Bit
+ * | | |0 = Tamper 0 detect Disabled.
+ * | | |1 = Tamper 0 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[9] |TAMP0LV |Tamper 0 Level
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit
+ * | | |0 = Tamper 0 de-bounce Disabled.
+ * | | |1 = Tamper 0 de-bounce Enabled.
+ * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit
+ * | | |0 = Tamper 1 detect Disabled.
+ * | | |1 = Tamper 1 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[13] |TAMP1LV |Tamper 1 Level
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit
+ * | | |0 = Tamper 1 de-bounce Disabled.
+ * | | |1 = Tamper 1 de-bounce Enabled.
+ * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit
+ * | | |0 = Static detect.
+ * | | |1 = Dynamic detect.
+ * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit
+ * | | |0 = Tamper 2 detect Disabled.
+ * | | |1 = Tamper 2 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[17] |TAMP2LV |Tamper 2 Level
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit
+ * | | |0 = Tamper 2 de-bounce Disabled.
+ * | | |1 = Tamper 2 de-bounce Enabled.
+ * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit
+ * | | |0 = Tamper 3 detect Disabled.
+ * | | |1 = Tamper 3 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[21] |TAMP3LV |Tamper 3 Level
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit
+ * | | |0 = Tamper 3 de-bounce Disabled.
+ * | | |1 = Tamper 3 de-bounce Enabled.
+ * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit
+ * | | |0 = Static detect.
+ * | | |1 = Dynamic detect.
+ * |[24] |TAMP4EN |Tamper4 Detect Enable Bit
+ * | | |0 = Tamper 4 detect Disabled.
+ * | | |1 = Tamper 4 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[25] |TAMP4LV |Tamper 4 Level
+ * | | |This bit depends on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit
+ * | | |0 = Tamper 4 de-bounce Disabled.
+ * | | |1 = Tamper 4 de-bounce Enabled.
+ * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit
+ * | | |0 = Tamper 5 detect Disabled.
+ * | | |1 = Tamper 5 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[29] |TAMP5LV |Tamper 5 Level
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit
+ * | | |0 = Tamper 5 de-bounce Disabled.
+ * | | |1 = Tamper 5 de-bounce Enabled.
+ * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit
+ * | | |0 = Static detect.
+ * | | |1 = Dynamic detect.
+ * @var RTC_T::TAMPSEED
+ * Offset: 0x128 RTC Tamper Dynamic Seed Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEED |Seed Value
+ * @var RTC_T::TAMPTIME
+ * Offset: 0x130 RTC Tamper Time Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9)
+ * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5)
+ * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9)
+ * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5)
+ * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9)
+ * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2)
+ * | | |Note: 24-hour time scale only.
+ * @var RTC_T::TAMPCAL
+ * Offset: 0x134 RTC Tamper Calendar Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9)
+ * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3)
+ * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9)
+ * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1)
+ * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9)
+ * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9)
+ */
+ __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */
+ __IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */
+ __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */
+ __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */
+ __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */
+ __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */
+ __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */
+ __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */
+ __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */
+ __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */
+ __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */
+ __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */
+ __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */
+ __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */
+ __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */
+ __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */
+ __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008c] RTC Spare Register 0 ~ 19 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[28];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */
+ __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */
+ __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE4[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */
+ __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */
+
+} RTC_T;
+
+/**
+ @addtogroup RTC_CONST RTC Bit Field Definition
+ Constant Definitions for RTC Controller
+@{ */
+
+#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: INIT_ACTIVE Position */
+#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: INIT_ACTIVE Mask */
+
+#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */
+#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
+
+#define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */
+#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */
+
+#define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */
+#define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */
+
+#define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */
+#define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */
+
+#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */
+#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */
+
+#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */
+#define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */
+
+#define RTC_FREQADJ_FCR_BUSY_Pos (31) /*!< RTC_T::FREQADJ: FCR_BUSY Position */
+#define RTC_FREQADJ_FCR_BUSY_Msk (0x1ul << RTC_FREQADJ_FCR_BUSY_Pos) /*!< RTC_T::FREQADJ: FCR_BUSY Mask */
+
+#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
+#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
+
+#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
+#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
+
+#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
+#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
+
+#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
+#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
+
+#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
+#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
+
+#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
+#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
+
+#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
+#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
+
+#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
+#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
+
+#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
+#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
+
+#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
+#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
+
+#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
+#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
+
+#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
+#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
+
+#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
+#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
+
+#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
+#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
+
+#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
+#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
+
+#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
+#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
+
+#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
+#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
+
+#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
+#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
+
+#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
+#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
+
+#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
+#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
+
+#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
+#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
+
+#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
+#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
+
+#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
+#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
+
+#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
+#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
+
+#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
+#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
+
+#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
+#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
+
+#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
+#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
+
+#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
+#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
+
+#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
+#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
+
+#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */
+#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */
+
+#define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */
+#define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */
+
+#define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */
+#define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */
+
+#define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */
+#define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */
+
+#define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */
+#define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */
+
+#define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */
+#define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */
+
+#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
+#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
+
+#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
+#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
+
+#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */
+#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */
+
+#define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */
+#define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */
+
+#define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */
+#define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */
+
+#define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */
+#define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */
+
+#define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */
+#define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */
+
+#define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */
+#define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */
+
+#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
+#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
+
+#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
+#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
+
+#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
+#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
+
+#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
+#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
+
+#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
+#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
+
+#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
+#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
+
+#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
+#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
+
+#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
+#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
+
+#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
+#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
+
+#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
+#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
+
+#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
+#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
+
+#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
+#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
+
+#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
+#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
+
+#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */
+#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */
+
+#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */
+#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */
+
+#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */
+#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */
+
+#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */
+#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */
+
+#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */
+#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */
+
+#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */
+#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */
+
+#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */
+#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */
+
+#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */
+#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */
+
+#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */
+#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */
+
+#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */
+#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */
+
+#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */
+#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */
+
+#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */
+#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */
+
+#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */
+#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */
+
+#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */
+#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */
+
+#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */
+#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */
+
+#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */
+#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */
+
+#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */
+#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */
+
+#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */
+#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */
+
+#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */
+#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */
+
+#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */
+#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */
+
+#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */
+#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */
+
+#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */
+#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */
+
+#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */
+#define RTC_LXTCTL_GAIN_Msk (0x3ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */
+
+#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */
+#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */
+
+#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */
+#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */
+
+#define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */
+#define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */
+
+#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */
+#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */
+
+#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */
+#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */
+
+#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */
+#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */
+
+#define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */
+#define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */
+
+#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */
+#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */
+
+#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */
+#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */
+
+#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */
+#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */
+
+#define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */
+#define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */
+
+#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */
+#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */
+
+#define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */
+#define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */
+
+#define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */
+#define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */
+
+#define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */
+#define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */
+
+#define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */
+#define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */
+
+#define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */
+#define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */
+
+#define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */
+#define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */
+
+#define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */
+#define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */
+
+#define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */
+#define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */
+
+#define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */
+#define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */
+
+#define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */
+#define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */
+
+#define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */
+#define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */
+
+#define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */
+#define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */
+
+#define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */
+#define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */
+
+#define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */
+#define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */
+
+#define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */
+#define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */
+
+#define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */
+#define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */
+
+#define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */
+#define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */
+
+#define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */
+#define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */
+
+#define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */
+#define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */
+
+#define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */
+#define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */
+
+#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */
+#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */
+
+#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */
+#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */
+
+#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */
+#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */
+
+#define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */
+#define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */
+
+#define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */
+#define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */
+
+#define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */
+#define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */
+
+#define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */
+#define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */
+
+#define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */
+#define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */
+
+#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */
+#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */
+
+#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */
+#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */
+
+#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */
+#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */
+
+#define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */
+#define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */
+
+#define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */
+#define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */
+
+#define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */
+#define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */
+
+#define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */
+#define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */
+
+#define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */
+#define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */
+
+#define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */
+#define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */
+
+#define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */
+#define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */
+
+#define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */
+#define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */
+
+#define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */
+#define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */
+
+#define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */
+#define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */
+
+#define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */
+#define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */
+
+#define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */
+#define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */
+
+#define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */
+#define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */
+
+#define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */
+#define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */
+
+#define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */
+#define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */
+
+#define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */
+#define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */
+
+#define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */
+#define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */
+
+#define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */
+#define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */
+
+#define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */
+#define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */
+
+#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */
+#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */
+
+#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */
+#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */
+
+#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */
+#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */
+
+#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */
+#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */
+
+#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */
+#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */
+
+#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */
+#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */
+
+#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */
+#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */
+
+#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */
+#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */
+
+#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */
+#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */
+
+#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */
+#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */
+
+#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */
+#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */
+
+#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */
+#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */
+
+
+/**@}*/ /* RTC_CONST */
+/**@}*/ /* end of RTC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __RTC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sc_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sc_reg.h
new file mode 100644
index 00000000000..af930b950d1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sc_reg.h
@@ -0,0 +1,1019 @@
+/**************************************************************************//**
+ * @file sc_reg.h
+ * @version V1.00
+ * @brief SC register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SC_REG_H__
+#define __SC_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup SC Smart Card Host Interface Controller(SC)
+ Memory Mapped Structure for SC Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var SC_T::DAT
+ * Offset: 0x00 SC Receive/Transmit Holding Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DAT |Receive/Transmit Holding Buffer
+ * | | |Write Operation:
+ * | | |By writing data to DAT, the SC will send out an 8-bit data.
+ * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.
+ * | | |Read Operation:
+ * | | |By reading DAT, the SC will return an 8-bit received data.
+ * @var SC_T::CTL
+ * Offset: 0x04 SC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SCEN |SC Controller Enable Bit
+ * | | |Set this bit to 1 to enable SC operation. If this bit is cleared,
+ * | | |0 = SC will force all transition to IDLE state.
+ * | | |1 = SC controller is enabled and all function can work correctly.
+ * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.
+ * |[1] |RXOFF |RX Transition Disable Control Bit
+ * | | |This bit is used for disable Rx transition function.
+ * | | |0 = The receiver Enabled.
+ * | | |1 = The receiver Disabled.
+ * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
+ * |[2] |TXOFF |TX Transition Disable Control Bit
+ * | | |This bit is used for disable Tx transition function.
+ * | | |0 = The transceiver Enabled.
+ * | | |1 = The transceiver Disabled.
+ * |[3] |AUTOCEN |Auto Convention Enable Bit
+ * | | |This bit is used for enable auto convention function.
+ * | | |0 = Auto-convention Disabled.
+ * | | |1 = Auto-convention Enabled.
+ * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR)
+ * | | |state and the first data must be 0x3B or 0x3F.
+ * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and
+ * | | |change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F.
+ * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00
+ * | | |automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.
+ * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an
+ * | | |interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.
+ * |[5:4] |CONSEL |Convention Selection
+ * | | |00 = Direct convention.
+ * | | |01 = Reserved.
+ * | | |10 = Reserved.
+ * | | |11 = Inverse convention.
+ * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
+ * |[7:6] |RXTRGLV |Rx Buffer Trigger Level
+ * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set
+ * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.
+ * | | |00 = Rx Buffer Trigger Level with 01 bytes.
+ * | | |01 = Rx Buffer Trigger Level with 02 bytes.
+ * | | |10 = Rx Buffer Trigger Level with 03 bytes.
+ * | | |11 = Reserved.
+ * |[12:8] |BGT |Block Guard Time (BGT)
+ * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters
+ * | | |between different transfer directions
+ * | | |This field indicates the counter for the bit length of block guard time
+ * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this
+ * | | |field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it.
+ * | | |Note: The real block guard time is BGT + 1.
+ * |[14:13] |TMRSEL |Timer Channel Selection
+ * | | |00 = All internal timer function Disabled.
+ * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled
+ * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0].
+ * | | |Other configurations are reserved
+ * |[15] |NSB |Stop Bit Length
+ * | | |This field indicates the length of stop bit.
+ * | | |0 = The stop bit length is 2 ETU.
+ * | | |1= The stop bit length is 1 ETU.
+ * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length.
+ * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.
+ * |[18:16] |RXRTY |RX Error Retry Count Number
+ * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred.
+ * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
+ * | | |Note2: This field cannot be changed when RXRTYEN enabled
+ * | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
+ * |[19] |RXRTYEN |RX Error Retry Enable Bit
+ * | | |This bit enables receiver retry function when parity error has occurred.
+ * | | |0 = RX error retry function Disabled.
+ * | | |1 = RX error retry function Enabled.
+ * | | |Note: User must fill in the RXRTY value before enabling this bit.
+ * |[22:20] |TXRTY |TX Error Retry Count Number
+ * | | |This field indicates the maximum number of transmitter retries that are allowed when parity
+ * | | |error has occurred.
+ * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
+ * | | |Note2: This field cannot be changed when TXRTYEN enabled
+ * | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
+ * |[23] |TXRTYEN |TX Error Retry Enable Bit
+ * | | |This bit enables transmitter retry function when parity error has occurred.
+ * | | |0 = TX error retry function Disabled.
+ * | | |1 = TX error retry function Enabled.
+ * |[25:24] |CDDBSEL |Card Detect De-bounce Selection
+ * | | |This field indicates the card detect de-bounce selection.
+ * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce
+ * | | |sample card removal once per 128 SC module clocks.
+ * | | |Other configurations are reserved.
+ * |[26] |CDLV |Card Detect Level Selection
+ * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected.
+ * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected.
+ * | | |Note: User must select card detect level before Smart Card controller enabled.
+ * |[30] |SYNC |SYNC Flag Indicator (Read Only)
+ * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
+ * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
+ * | | |1 = Last value is synchronizing.
+ * @var SC_T::ALTCTL
+ * Offset: 0x08 SC Alternate Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TXRST |TX Software Reset
+ * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the TX internal state machine and pointers.
+ * | | |Note: This bit will be auto cleared after reset is complete.
+ * |[1] |RXRST |Rx Software Reset
+ * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the Rx internal state machine and pointers.
+ * | | |Note: This bit will be auto cleared after reset is complete.
+ * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
+ * | | |This bit enables SC controller to initiate the card by deactivation sequence.
+ * | | |0 = No effect.
+ * | | |1 = Deactivation sequence generator Enabled.
+ * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and
+ * | | |the INITIF (SCn_INTSTS[8]) will be set to 1.
+ * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
+ * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[3] |ACTEN |Activation Sequence Generator Enable Bit
+ * | | |This bit enables SC controller to initiate the card by activation sequence.
+ * | | |0 = No effect.
+ * | | |1 = Activation sequence generator Enabled.
+ * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the
+ * | | |INITIF (SCn_INTSTS[8]) will be set to 1.
+ * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
+ * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+ * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data
+ * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.
+ * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
+ * | | |This bit enables SC controller to initiate the card by warm reset sequence.
+ * | | |0 = No effect.
+ * | | |1 = Warm reset sequence generator Enabled.
+ * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the
+ * | | |INITIF (SCn_INTSTS[8]) will be set to 1.
+ * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
+ * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+ * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data
+ * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform
+ * | | |warm reset sequence.
+ * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
+ * | | |This bit enables Timer 0 to start counting
+ * | | |User can fill 0 to stop it and set 1 to reload and count
+ * | | |The counter unit is ETU base.
+ * | | |0 = Stops counting.
+ * | | |1 = Start counting.
+ * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only.
+ * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will
+ * | | |be auto-cleared by hardware.
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
+ * | | |This bit enables Timer 1 to start counting
+ * | | |User can fill 0 to stop it and set 1 to reload and count
+ * | | |The counter unit is ETU base.
+ * | | |0 = Stops counting.
+ * | | |1 = Start counting.
+ * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only
+ * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
+ * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will
+ * | | |be auto-cleared by hardware.
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
+ * | | |This bit enables Timer 2 to start counting
+ * | | |User can fill 0 to stop it and set 1 to reload and count
+ * | | |The counter unit is ETU base.
+ * | | |0 = Stops counting.
+ * | | |1 = Start counting.
+ * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only
+ * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
+ * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will
+ * | | |be auto-cleared by hardware.
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[9:8] |INITSEL |Initial Timing Selection
+ * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation.
+ * | | |The unit of initial timing is SC module clock.
+ * | | |Activation: refer to SC Activation Sequence in Figure 7.17-54.
+ * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 7.17-5.
+ * | | |Deactivation: refer to Deactivation Sequence in Figure 7.17-56.
+ * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation
+ * | | |at most 128 SC module clock cycles.
+ * |[11] |ADACEN |Auto Deactivation When Card Removal
+ * | | |This bit is used for enable hardware auto deactivation when smart card is removed.
+ * | | |0 = Auto deactivation Disabled.
+ * | | |1 = Auto deactivation Enabled.
+ * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence
+ * | | |if this bit is set
+ * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.
+ * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
+ * | | |This bit enables the receiver block guard time function.
+ * | | |0 = Receiver block guard time function Disabled.
+ * | | |1 = Receiver block guard time function Enabled.
+ * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only)
+ * | | |This bit indicates the timer counter status of timer0.
+ * | | |0 = Timer0 is not active.
+ * | | |1 = Timer0 is active.
+ * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).
+ * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only)
+ * | | |This bit indicates the timer counter status of timer1.
+ * | | |0 = Timer1 is not active.
+ * | | |1 = Timer1 is active.
+ * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).
+ * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only)
+ * | | |This bit indicates the timer counter status of timer2.
+ * | | |0 = Timer2 is not active.
+ * | | |1 = Timer2 is active.
+ * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).
+ * |[31] |SYNC |SYNC Flag Indicator (Read Only)
+ * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.
+ * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register.
+ * | | |1 = Last value is synchronizing.
+ * @var SC_T::EGT
+ * Offset: 0x0C SC Extra Guard Time Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |EGT |Extra Guard Time
+ * | | |This field indicates the extra guard time value.
+ * | | |Note: The extra guard time unit is ETU base.
+ * @var SC_T::RXTOUT
+ * Offset: 0x10 SC Receive Buffer Time-out Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter
+ * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data
+ * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by
+ * | | |reading SCn_DAT, a receiver time-out flag RBTOIF (SCn_INTSTS[9]) will be set, and hardware will
+ * | | |generate an interrupt to CPU when RBTOIEN (SCn_INTEN[9]) is enabled.
+ * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
+ * | | |Note2: Filling in all 0 to this field indicates to disable this function.
+ * @var SC_T::ETUCTL
+ * Offset: 0x14 SC Element Time Unit Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |ETURDIV |ETU Rate Divider
+ * | | |The field is used for ETU clock rate divider.
+ * | | |The real ETU is ETURDIV + 1.
+ * | | |Note: User can configure this field, but this field must be greater than 0x04.
+ * @var SC_T::INTEN
+ * Offset: 0x18 SC Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
+ * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.
+ * | | |0 = Receive data reach trigger level interrupt Disabled.
+ * | | |1 = Receive data reach trigger level interrupt Enabled.
+ * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
+ * | | |This field is used to enable transmit buffer empty interrupt.
+ * | | |0 = Transmit buffer empty interrupt Disabled.
+ * | | |1 = Transmit buffer empty interrupt Enabled.
+ * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
+ * | | |This field is used to enable transfer error interrupt
+ * | | |The transfer error states is at SCn_STATUS register which includes receiver break error
+ * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive
+ * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]),
+ * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error
+ * | | |TXOVERR (SCn_STATUS[30]).
+ * | | |0 = Transfer error interrupt Disabled.
+ * | | |1 = Transfer error interrupt Enabled.
+ * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
+ * | | |This field is used to enable Timer0 interrupt function.
+ * | | |0 = Timer0 interrupt Disabled.
+ * | | |1 = Timer0 interrupt Enabled.
+ * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
+ * | | |This field is used to enable the Timer1 interrupt function.
+ * | | |0 = Timer1 interrupt Disabled.
+ * | | |1 = Timer1 interrupt Enabled.
+ * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
+ * | | |This field is used to enable Timer2 interrupt function.
+ * | | |0 = Timer2 interrupt Disabled.
+ * | | |1 = Timer2 interrupt Enabled.
+ * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
+ * | | |This field is used to enable block guard time interrupt in receive direction.
+ * | | |0 = Block guard time interrupt Disabled.
+ * | | |1 = Block guard time interrupt Enabled.
+ * | | |Note: This bit is valid only for receive direction block guard time.
+ * |[7] |CDIEN |Card Detect Interrupt Enable Bit
+ * | | |This field is used to enable card detect interrupt
+ * | | |The card detect status is CDPINSTS (SCn_STATUS[13]).
+ * | | |0 = Card detect interrupt Disabled.
+ * | | |1 = Card detect interrupt Enabled.
+ * |[8] |INITIEN |Initial End Interrupt Enable Bit
+ * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation
+ * | | |(DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt.
+ * | | |0 = Initial end interrupt Disabled.
+ * | | |1 = Initial end interrupt Enabled.
+ * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit
+ * | | |This field is used to enable receiver buffer time-out interrupt.
+ * | | |0 = Receiver buffer time-out interrupt Disabled.
+ * | | |1 = Receiver buffer time-out interrupt Enabled.
+ * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
+ * | | |This field is used to enable auto-convention error interrupt.
+ * | | |0 = Auto-convention error interrupt Disabled.
+ * | | |1 = Auto-convention error interrupt Enabled.
+ * @var SC_T::INTSTS
+ * Offset: 0x1C SC Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
+ * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.
+ * | | |0 = Number of receive buffer is less than RXTRGLV setting.
+ * | | |1 = Number of receive buffer data equals the RXTRGLV setting.
+ * | | |Note: This bit is read only
+ * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV,
+ * | | |this bit will be cleared automatically.
+ * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
+ * | | |This field is used for transmit buffer empty interrupt status flag.
+ * | | |0 = Transmit buffer is not empty.
+ * | | |1 = Transmit buffer is empty.
+ * | | |Note: This bit is read only
+ * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit
+ * | | |will be cleared automatically.
+ * |[2] |TERRIF |Transfer Error Interrupt Status Flag
+ * | | |This field is used for transfer error interrupt status flag
+ * | | |The transfer error states is at SCn_STATUS register which includes receiver break error
+ * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive
+ * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]),
+ * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error
+ * | | |TXOVERR (SCn_STATUS[30]).
+ * | | |0 = Transfer error interrupt did not occur.
+ * | | |1 = Transfer error interrupt occurred.
+ * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.
+ * | | |Note2: This bit can be cleared by writing 1 to it.
+ * |[3] |TMR0IF |Timer0 Interrupt Status Flag
+ * | | |This field is used for Timer0 interrupt status flag.
+ * | | |0 = Timer0 interrupt did not occur.
+ * | | |1 = Timer0 interrupt occurred.
+ * | | |Note: This bit can be cleared by writing 1 to it.
+ * |[4] |TMR1IF |Timer1 Interrupt Status Flag
+ * | | |This field is used for Timer1 interrupt status flag.
+ * | | |0 = Timer1 interrupt did not occur.
+ * | | |1 = Timer1 interrupt occurred.
+ * | | |Note: This bit can be cleared by writing 1 to it.
+ * |[5] |TMR2IF |Timer2 Interrupt Status Flag
+ * | | |This field is used for Timer2 interrupt status flag.
+ * | | |0 = Timer2 interrupt did not occur.
+ * | | |1 = Timer2 interrupt occurred.
+ * | | |Note: This bit can be cleared by writing 1 to it.
+ * |[6] |BGTIF |Block Guard Time Interrupt Status Flag
+ * | | |This field is used for indicate block guard time interrupt status flag in receive direction.
+ * | | |0 = Block guard time interrupt did not occur.
+ * | | |1 = Block guard time interrupt occurred.
+ * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.
+ * | | |Note2: This bit can be cleared by writing 1 to it.
+ * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
+ * | | |This field is used for card detect interrupt status flag
+ * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).
+ * | | |0 = Card detect event did not occur.
+ * | | |1 = Card detect event occurred.
+ * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it.
+ * |[8] |INITIF |Initial End Interrupt Status Flag
+ * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2]))
+ * | | |and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.
+ * | | |0 = Initial sequence is not complete.
+ * | | |1 = Initial sequence is completed.
+ * | | |Note: This bit can be cleared by writing 1 to it.
+ * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only)
+ * | | |This field is used for indicate receive buffer time-out interrupt status flag.
+ * | | |0 = Receive buffer time-out interrupt did not occur.
+ * | | |1 = Receive buffer time-out interrupt occurred.
+ * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT
+ * | | |register to clear it.
+ * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag
+ * | | |This field indicates auto convention sequence error.
+ * | | |0 = Received TS at ATR state is 0x3B or 0x3F.
+ * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F.
+ * | | |Note: This bit can be cleared by writing 1 to it.
+ * @var SC_T::STATUS
+ * Offset: 0x20 SC Transfer Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXOV |Receive Overflow Error Status Flag
+ * | | |This bit is set when Rx buffer overflow.
+ * | | |0 = Rx buffer is not overflow.
+ * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes).
+ * | | |Note: This bit can be cleared by writing 1 to it.
+ * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only)
+ * | | |This bit indicates Rx buffer empty or not.
+ * | | |0 = Rx buffer is not empty.
+ * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU.
+ * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only)
+ * | | |This bit indicates Rx buffer full or not.
+ * | | |0 = Rx buffer count is less than 4.
+ * | | |1 = Rx buffer count equals to 4.
+ * |[4] |PEF |Receiver Parity Error Status Flag
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit.
+ * | | |0 = Receiver parity error flag did not occur.
+ * | | |1 = Receiver parity error flag occurred.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not
+ * | | |set this flag.
+ * |[5] |FEF |Receiver Frame Error Status Flag
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is,
+ * | | |the stop bit following the last data bit or parity bit is detected as logic 0).
+ * | | |0 = Receiver frame error flag did not occur.
+ * | | |1 = Receiver frame error flag occurred.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not
+ * | | |set this flag.
+ * |[6] |BEF |Receiver Break Error Status Flag
+ * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state
+ * | | |(logic 0) is longer than a full word transmission time (that is, the total time of start bit +
+ * | | |data bits + parity bit + stop bit).
+ * | | |0 = Receiver break error flag did not occur.
+ * | | |1 = Receiver break error flag occurred.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set
+ * | | |this flag.
+ * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag
+ * | | |This bit is set when Tx buffer overflow.
+ * | | |0 = Tx buffer is not overflow.
+ * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]).
+ * | | |Note: This bit can be cleared by writing 1 to it.
+ * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
+ * | | |This bit indicates TX buffer empty or not.
+ * | | |0 = Tx buffer is not empty.
+ * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter
+ * | | |Shift Register.
+ * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).
+ * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
+ * | | |This bit indicates Tx buffer full or not.
+ * | | |0 = Tx buffer count is less than 4.
+ * | | |1 = Tx buffer count equals to 4.
+ * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin
+ * | | |This bit is set whenever card has been removal.
+ * | | |0 = No effect.
+ * | | |1 = Card removed.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set.
+ * |[12] |CINSERT |Card Insert Status of SCn_CD Pin
+ * | | |This bit is set whenever card has been inserted.
+ * | | |0 = No effect.
+ * | | |1 = Card insert.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set.
+ * |[13] |CDPINSTS |Card Detect Pin Status (Read Only)
+ * | | |This bit is the pin status of SCn_CD.
+ * | | |0 = The SCn_CD pin state at low.
+ * | | |1 = The SCn_CD pin state at high.
+ * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only)
+ * | | |This field indicates the Rx buffer pointer status
+ * | | |When SC controller receives one byte from external device, RXPOINT increases one
+ * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one.
+ * |[21] |RXRERR |Receiver Retry Error
+ * | | |This bit is used for receiver error retry and set by hardware.
+ * | | |0 = No Rx retry transfer.
+ * | | |1 = Rx has any error and retries transfer.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
+ * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]),
+ * | | |hardware will not set this flag.
+ * |[22] |RXOVERR |Receiver over Retry Error
+ * | | |This bit is used for receiver retry counts over than retry number limitation.
+ * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1.
+ * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware
+ * | | |will not set this flag.
+ * |[23] |RXACT |Receiver in Active Status Flag (Read Only)
+ * | | |This bit indicates Rx transfer status.
+ * | | |0 = This bit is cleared automatically when Rx transfer is finished.
+ * | | |1 = This bit is set by hardware when Rx transfer is in active.
+ * | | |Note: This bit is read only.
+ * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only)
+ * | | |This field indicates the Tx buffer pointer status
+ * | | |When CPU writes data into SCn_DAT, TXPOINT increases one
+ * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one.
+ * |[29] |TXRERR |Transmitter Retry Error
+ * | | |This bit is used for indicate transmitter error retry and set by hardware.
+ * | | |0 = No Tx retry transfer.
+ * | | |1 = Tx has any error and retries transfer.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU.
+ * |[30] |TXOVERR |Transmitter over Retry Error
+ * | | |This bit is used for transmitter retry counts over than retry number limitation.
+ * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1.
+ * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1.
+ * | | |Note: This bit can be cleared by writing 1 to it.
+ * |[31] |TXACT |Transmit in Active Status Flag (Read Only)
+ * | | |This bit indicates Tx transmit status.
+ * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission
+ * | | |has completed.
+ * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP
+ * | | |bit of the last byte has not been transmitted.
+ * | | |Note: This bit is read only.
+ * @var SC_T::PINCTL
+ * Offset: 0x24 SC Pin Control State Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PWREN |SCn_PWR Pin Signal
+ * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.
+ * | | |Write this field to drive SCn_PWR pin
+ * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level.
+ * | | |Read this field to get SCn_PWR signal status.
+ * | | |0 = SCn_PWR signal status is low.
+ * | | |1 = SCn_PWR signal status is high.
+ * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |Thus, do not fill in this field when operating in these modes.
+ * |[1] |RSTEN |SCn_RST Pin Signal
+ * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.
+ * | | |Write this field to drive SCn_RST pin.
+ * | | |0 = Drive SCn_RST pin to low.
+ * | | |1 = Drive SCn_RST pin to high.
+ * | | |Read this field to get SCn_RST signal status.
+ * | | |0 = SCn_RST signal status is low.
+ * | | |1 = SCn_RST signal status is high.
+ * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |Thus, do not fill in this field when operating in these modes.
+ * |[6] |CLKKEEP |SC Clock Enable Bit
+ * | | |0 = SC clock generation Disabled.
+ * | | |1 = SC clock always keeps free running.
+ * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |Thus, do not fill in this field when operating in these modes.
+ * |[9] |SCDATA |SCn_DATA Pin Signal
+ * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.
+ * | | |0 = Drive SCn_DATA pin to low.
+ * | | |1 = Drive SCn_DATA pin to high.
+ * | | |Read this field to get SCn_DATA signal status.
+ * | | |0 = SCn_DATA signal status is low.
+ * | | |1 = SCn_DATA signal status is high.
+ * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |Thus, do not fill in this field when SC is in these modes.
+ * |[11] |PWRINV |SCn_PWR Pin Inverse
+ * | | |This bit is used for inverse the SCn_PWR pin.
+ * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]).
+ * | | |PWRINV is 0 and PWREN is 0, SCn_PWR pin is 0.
+ * | | |PWRINV is 0 and PWREN is 1, SCn_PWR pin is 1.
+ * | | |PWRINV is 1 and PWREN is 0, SCn_PWR pin is 1.
+ * | | |PWRINV is 1 and PWREN is 1, SCn_PWR pin is 0.
+ * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).
+ * |[16] |DATASTS |SCn_DATA Pin Status (Read Only)
+ * | | |This bit is the pin status of SCn_DATA.
+ * | | |0 = The SCn_DATA pin status is low.
+ * | | |1 = The SCn_DATA pin status is high.
+ * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only)
+ * | | |This bit is the pin status of SCn_PWR.
+ * | | |0 = SCn_PWR pin to low.
+ * | | |1 = SCn_PWR pin to high.
+ * |[18] |RSTSTS |SCn_RST Pin Status (Read Only)
+ * | | |This bit is the pin status of SCn_RST.
+ * | | |0 = SCn_RST pin is low.
+ * | | |1 = SCn_RST pin is high.
+ * |[30] |SYNC |SYNC Flag Indicator (Read Only)
+ * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.
+ * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register.
+ * | | |1 = Last value is synchronizing.
+ * @var SC_T::TMRCTL0
+ * Offset: 0x28 SC Internal Timer0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CNT |Timer0 Counter Value
+ * | | |This field indicates the internal Timer0 counter values.
+ * | | |Note: Unit of Timer0 counter is ETU base.
+ * |[27:24] |OPMODE |Timer0 Operation Mode Selection
+ * | | |This field indicates the internal 24-bit Timer0 operation selection.
+ * | | |Refer to Table 7.17-3 for programming Timer0.
+ * |[31] |SYNC |SYNC Flag Indicator (Read Only)
+ * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.
+ * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register.
+ * | | |1 = Last value is synchronizing.
+ * @var SC_T::TMRCTL1
+ * Offset: 0x2C SC Internal Timer1 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CNT |Timer 1 Counter Value
+ * | | |This field indicates the internal Timer1 counter values.
+ * | | |Note: Unit of Timer1 counter is ETU base.
+ * |[27:24] |OPMODE |Timer 1 Operation Mode Selection
+ * | | |This field indicates the internal 8-bit Timer1 operation selection.
+ * | | |Refer to Table 7.17-3 for programming Timer1.
+ * |[31] |SYNC |SYNC Flag Indicator (Read Only)
+ * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.
+ * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register.
+ * | | |1 = Last value is synchronizing.
+ * @var SC_T::TMRCTL2
+ * Offset: 0x30 SC Internal Timer2 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CNT |Timer 2 Counter Value
+ * | | |This field indicates the internal Timer2 counter values.
+ * | | |Note: Unit of Timer2 counter is ETU base.
+ * |[27:24] |OPMODE |Timer 2 Operation Mode Selection
+ * | | |This field indicates the internal 8-bit Timer2 operation selection
+ * | | |Refer to Table 7.17-3 for programming Timer2.
+ * |[31] |SYNC |SYNC Flag Indicator (Read Only)
+ * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.
+ * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register.
+ * | | |1 = Last value is synchronizing.
+ * @var SC_T::UARTCTL
+ * Offset: 0x34 SC UART Mode Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |UARTEN |UART Mode Enable Bit
+ * | | |Sets this bit to enable UART mode function.
+ * | | |0 = Smart Card mode.
+ * | | |1 = UART mode.
+ * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0.
+ * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0.
+ * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.
+ * |[5:4] |WLS |Word Length Selection
+ * | | |This field is used for select UART data length.
+ * | | |00 = Word length is 8 bits.
+ * | | |01 = Word length is 7 bits.
+ * | | |10 = Word length is 6 bits.
+ * | | |11 = Word length is 5 bits.
+ * | | |Note: In smart card mode, this WLS must be '00'.
+ * |[6] |PBOFF |Parity Bit Disable Control
+ * | | |Sets this bit is used for disable parity check function.
+ * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data.
+ * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
+ * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit).
+ * |[7] |OPE |Odd Parity Enable Bit
+ * | | |This is used for odd/even parity selection.
+ * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+ * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+ * | | |Note: This bit has effect only when PBOFF bit is '0'.
+ * @var SC_T::ACTCTL
+ * Offset: 0x4C SC Activation Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation
+ * | | |This field provide the configurable cycles to extend the activation time T1 period.
+ * | | |The cycle scaling factor is 2048.
+ * | | |Extend cycles = (filled value * 2048) cycles.
+ * | | |Refer to SC activation sequence in Figure 7.17-4.
+ * | | |For example,
+ * | | |SCLK = 4MHz, each cycle = 0.25us,.
+ * | | |Filled 20 to this field
+ * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms.
+ * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3
+ */
+ __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */
+ __IO uint32_t CTL; /*!< [0x0004] SC Control Register */
+ __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */
+ __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */
+ __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */
+ __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */
+ __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */
+ __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */
+ __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */
+ __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */
+ __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */
+ __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */
+ __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */
+ __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE0[5];
+ /** @endcond */
+ __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */
+
+} SC_T;
+
+/**
+ @addtogroup SC_CONST SC Bit Field Definition
+ Constant Definitions for SC Controller
+@{ */
+
+#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
+#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
+
+#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
+#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
+
+#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
+#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
+
+#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
+#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
+
+#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
+#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
+
+#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
+#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
+
+#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
+#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
+
+#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
+#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
+
+#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
+#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
+
+#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
+#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
+
+#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
+#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
+
+#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
+#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
+
+#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
+#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
+
+#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
+#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
+
+#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
+#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
+
+#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
+#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
+
+#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
+#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
+
+#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
+#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
+
+#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
+#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
+
+#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
+#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
+
+#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
+#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
+
+#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
+#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
+
+#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
+#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
+
+#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
+#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
+
+#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
+#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
+
+#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
+#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
+
+#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
+#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
+
+#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
+#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
+
+#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
+#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
+
+#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
+#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
+
+#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
+#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
+
+#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */
+#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */
+
+#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
+#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
+
+#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
+#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
+
+#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */
+#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */
+
+#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
+#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
+
+#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
+#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
+
+#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
+#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
+
+#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */
+#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
+
+#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
+#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
+
+#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
+#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
+
+#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
+#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
+
+#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
+#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
+
+#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
+#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
+
+#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */
+#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */
+
+#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
+#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
+
+#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
+#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
+
+#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
+#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
+
+#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
+#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
+
+#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
+#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
+
+#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
+#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
+
+#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
+#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
+
+#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
+#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
+
+#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
+#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
+
+#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
+#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
+
+#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */
+#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */
+
+#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
+#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
+
+#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */
+#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */
+
+#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
+#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
+
+#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
+#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
+
+#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
+#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
+
+#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
+#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
+
+#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
+#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
+
+#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
+#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
+
+#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
+#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
+
+#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
+#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
+
+#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
+#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
+
+#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
+#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
+
+#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
+#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
+
+#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
+#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
+
+#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
+#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
+
+#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
+#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
+
+#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
+#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */
+
+#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
+#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */
+
+#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
+#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */
+
+#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */
+#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */
+
+#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
+#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */
+
+#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
+#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */
+
+#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */
+#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */
+
+#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
+#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */
+
+#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */
+#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */
+
+#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
+#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */
+
+#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */
+#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */
+
+#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
+#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */
+
+#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
+#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */
+
+#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
+#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */
+
+#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
+#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */
+
+#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
+#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */
+
+#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */
+#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */
+
+#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
+#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */
+
+#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
+#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */
+
+#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */
+#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */
+
+#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
+#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */
+
+#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
+#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */
+
+#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */
+#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */
+
+#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
+#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */
+
+#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
+#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */
+
+#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
+#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */
+
+#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
+#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */
+
+#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */
+#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */
+
+/**@}*/ /* SC_CONST */
+/**@}*/ /* end of SC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __SC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sdh_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sdh_reg.h
new file mode 100644
index 00000000000..56f42e82005
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sdh_reg.h
@@ -0,0 +1,541 @@
+/**************************************************************************//**
+ * @file sdh_reg.h
+ * @version V1.00
+ * @brief SDH register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SDH_REG_H__
+#define __SDH_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup SDH SD Card Host Interface(SDH)
+ Memory Mapped Structure for SDH Controller
+@{ */
+
+typedef struct
+{
+
+ /**
+ * @var SDH_T::FB
+ * Offset: 0x00~0x7C Shared Buffer (FIFO)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |BUFFER |Shared Buffer
+ * | | |Buffer for DMA transfer
+ * @var SDH_T::DMACTL
+ * Offset: 0x400 DMA Control and Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DMAEN |DMA Engine Enable Bit
+ * | | |0 = DMA Disabled.
+ * | | |1 = DMA Enabled.
+ * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
+ * | | |Note: If target abort is occurred, DMAEN will be cleared.
+ * |[1] |DMARST |Software Engine Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset internal state machine and pointers
+ * | | |The contents of control register will not be cleared
+ * | | |This bit will auto be cleared after few clock cycles.
+ * | | |Note: The software reset DMA related registers.
+ * |[3] |SGEN |Scatter-gather Function Enable Bit
+ * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
+ * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table
+ * | | |The format of these Pads' will be described later).
+ * |[9] |DMABUSY |DMA Transfer Is in Progress
+ * | | |This bit indicates if SD Host is granted and doing DMA transfer or not.
+ * | | |0 = DMA transfer is not in progress.
+ * | | |1 = DMA transfer is in progress.
+ * @var SDH_T::DMASA
+ * Offset: 0x408 DMA Transfer Starting Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order
+ * | | |0 = PAD table is fetched in order.
+ * | | |1 = PAD table is fetched out of order.
+ * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
+ * |[31:1] |DMASA |DMA Transfer Starting Address
+ * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
+ * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
+ * | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.
+ * @var SDH_T::DMABCNT
+ * Offset: 0x40C DMA Transfer Byte Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[25:0] |BCNT |DMA Transfer Byte Count (Read Only)
+ * | | |This field indicates the remained byte count of DMA transfer
+ * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0.
+ * @var SDH_T::DMAINTEN
+ * Offset: 0x410 DMA Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit
+ * | | |0 = Target abort interrupt generation Disabled during DMA transfer.
+ * | | |1 = Target abort interrupt generation Enabled during DMA transfer.
+ * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit
+ * | | |0 = Interrupt generation Disabled when wrong EOT is encountered.
+ * | | |1 = Interrupt generation Enabled when wrong EOT is encountered.
+ * @var SDH_T::DMAINTSTS
+ * Offset: 0x414 DMA Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag
+ * | | |0 = No bus ERROR response received.
+ * | | |1 = Bus ERROR response received.
+ * | | |Note1: This bit is read only, but can be cleared by writing '1' to it.
+ * | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened
+ * | | |DMA will stop transfer and respond this event and then go to IDLE state
+ * | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.
+ * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag
+ * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
+ * | | |0 = No EOT encountered before DMA transfer finished.
+ * | | |1 = EOT encountered before DMA transfer finished.
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * @var SDH_T::GCTL
+ * Offset: 0x800 Global Control and Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GCTLRST |Software Engine Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset SD host
+ * | | |The contents of control register will not be cleared
+ * | | |This bit will auto cleared after reset complete.
+ * |[1] |SDEN |Secure Digital Functionality Enable Bit
+ * | | |0 = SD functionality disabled.
+ * | | |1 = SD functionality enabled.
+ * @var SDH_T::GINTEN
+ * Offset: 0x804 Global Interrupt Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit
+ * | | |0 = DMA READ/WRITE target abort interrupt generation disabled.
+ * | | |1 = DMA READ/WRITE target abort interrupt generation enabled.
+ * @var SDH_T::GINTSTS
+ * Offset: 0x808 Global Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
+ * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
+ * | | |When Target Abort is occurred, please reset all engine.
+ * | | |0 = No bus ERROR response received.
+ * | | |1 = Bus ERROR response received.
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * @var SDH_T::CTL
+ * Offset: 0x820 SD Control and Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |COEN |Command Output Enable Bit
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+ * | | |1 = Enabled, SD host will output a command to SD card.
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+ * |[1] |RIEN |Response Input Enable Bit
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+ * | | |1 = Enabled, SD host will wait to receive a response from SD card.
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+ * |[2] |DIEN |Data Input Enable Bit
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+ * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+ * |[3] |DOEN |Data Output Enable Bit
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+ * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+ * |[4] |R2EN |Response R2 Input Enable Bit
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+ * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+ * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+ * | | |1 = Enabled, SD host will output 74 clock cycles to SD card.
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+ * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+ * | | |1 = Enabled, SD host will output 8 clock cycles.
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+ * |[7] |CLKKEEP |SD Clock Enable Control
+ * | | |0 = SD host decided when to output clock and when to disable clock output automatically.
+ * | | |1 = SD clock always keeps free running.
+ * |[13:8] |CMDCODE |SD Command Code
+ * | | |This register contains the SD command code (0x00 - 0x3F).
+ * |[14] |CTLRST |Software Engine Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the internal state machine and counters
+ * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared)
+ * | | |This bit will be auto cleared after few clock cycles.
+ * |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection)
+ * | | |0 = Data bus width is 1-bit.
+ * | | |1 = Data bus width is 4-bit.
+ * |[23:16] |BLKCNT |Block Counts to Be Transferred or Received
+ * | | |This field contains the block counts for data-in and data-out transfer
+ * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance
+ * | | |Don't fill 0x0 to this field.
+ * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
+ * |[27:24] |SDNWR |NWR Parameter for Block Write Operation
+ * | | |This value indicates the NWR parameter for data block write operation in SD clock counts
+ * | | |The actual clock cycle will be SDNWR+1.
+ * @var SDH_T::CMDARG
+ * Offset: 0x824 SD Command Argument Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ARGUMENT |SD Command Argument
+ * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card
+ * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
+ * @var SDH_T::INTEN
+ * Offset: 0x828 SD Interrupt Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit
+ * | | |0 = BLKDIF (SDH_INTEN[0]) trigger interrupt Disable.
+ * | | |1 = BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled.
+ * |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit
+ * | | |0 = CRCIF (SDH_INTEN[1]) trigger interrupt Disable.
+ * | | |1 = CRCIF (SDH_INTEN[1]) trigger interrupt Enabled.
+ * |[8] |CDIEN |SD Card Detection Interrupt Enable Bit
+ * | | |Enable/Disable interrupts generation of SD controller when card is inserted or removed.
+ * | | |0 = CDIF (SDH_INTEN[8]) trigger interrupt Disable.
+ * | | |1 = CDIF (SDH_INTEN[8]) trigger interrupt Enabled.
+ * |[12] |RTOIEN |Response Time-out Interrupt Enable Bit
+ * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out
+ * | | |Time-out value is specified at TOUT register.
+ * | | |0 = RTOIF (SDH_INTEN[12]) trigger interrupt Disabled.
+ * | | |1 = RTOIF (SDH_INTEN[12]) trigger interrupt Enabled.
+ * |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit
+ * | | |Enable/Disable interrupts generation of SD controller when data input time-out
+ * | | |Time-out value is specified at TOUT register.
+ * | | |0 = DITOIF (SDH_INTEN[13]) trigger interrupt Disabled.
+ * | | |1 = DITOIF (SDH_INTEN[13]) trigger interrupt Enabled.
+ * |[14] |WKIEN |Wake-up Signal Generating Enable Bit
+ * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
+ * | | |0 = SD Card interrupt to wake-up chip Disabled.
+ * | | |1 = SD Card interrupt to wake-up chip Enabled.
+ * |[30] |CDSRC |SD Card Detect Source Selection
+ * | | |0 = From SD card's DAT3 pin.
+ * | | |Host need clock to got data on pin DAT3
+ * | | |Please make sure CLKKEEP (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
+ * | | |1 = From GPIO pin.
+ * @var SDH_T::INTSTS
+ * Offset: 0x82C SD Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only)
+ * | | |This bit indicates that SD host has finished all data-in or data-out block transfer
+ * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
+ * | | |0 = Not finished yet.
+ * | | |1 = Done.
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
+ * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
+ * | | |When CRC error is occurred, software should reset SD engine
+ * | | |Some response (ex
+ * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
+ * | | |In this condition, software should ignore CRC error and clears this bit manually.
+ * | | |0 = No CRC error is occurred.
+ * | | |1 = CRC error is occurred.
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[2] |CRC7 |CRC7 Check Status (Read Only)
+ * | | |SD host will check CRC7 correctness during each response in
+ * | | |If that response does not contain CRC7 information (ex
+ * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
+ * | | |0 = Fault.
+ * | | |1 = OK.
+ * |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only)
+ * | | |SD host will check CRC16 correctness after data-in transfer.
+ * | | |0 = Fault.
+ * | | |1 = OK.
+ * |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only)
+ * | | |SD host will record CRC status of data-out transfer
+ * | | |Software could use this value to identify what type of error is during data-out transfer.
+ * | | |010 = Positive CRC status.
+ * | | |101 = Negative CRC status.
+ * | | |111 = SD card programming error occurs.
+ * |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only)
+ * | | |This bit is the DAT0 pin status of current selected SD port.
+ * |[8] |CDIF |SD Card Detection Interrupt Flag (Read Only)
+ * | | |This bit indicates that SD card is inserted or removed
+ * | | |Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active.
+ * | | |0 = No card is inserted or removed.
+ * | | |1 = There is a card inserted in or removed from SD.
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only)
+ * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
+ * | | |0 = Not time-out.
+ * | | |1 = Response time-out.
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only)
+ * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
+ * | | |0 = Not time-out.
+ * | | |1 = Data input time-out.
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[16] |CDSTS |Card Detect Status of SD (Read Only)
+ * | | |This bit indicates the card detect pin status of SD, and is used for card detection
+ * | | |When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal.
+ * | | |If CDSRC (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
+ * | | |0 = Card removed.
+ * | | |1 = Card inserted.
+ * | | |If CDSRC (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
+ * | | |0 = Card inserted.
+ * | | |1 = Card removed.
+ * |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only)
+ * | | |This bit indicates the DAT1 pin status of SD port.
+ * @var SDH_T::RESP0
+ * Offset: 0x830 SD Receiving Response Token Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RESPTK0 |SD Receiving Response Token 0
+ * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
+ * | | |This field contains response bit 47-16 of the response token.
+ * @var SDH_T::RESP1
+ * Offset: 0x834 SD Receiving Response Token Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |RESPTK1 |SD Receiving Response Token 1
+ * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
+ * | | |This register contains the bit 15-8 of the response token.
+ * @var SDH_T::BLEN
+ * Offset: 0x838 SD Block Length Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit
+ * | | |An 11-bit value specifies the SD transfer byte count of a block
+ * | | |The actual byte count is equal to BLKLEN+1.
+ * | | |Note: The default SD block length is 512 bytes
+ * @var SDH_T::TOUT
+ * Offset: 0x83C SD Response/Data-in Time-out Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |TOUT |SD Response/Data-in Time-out Value
+ * | | |A 24-bit value specifies the time-out counts of response and data input
+ * | | |SD host controller will wait start bit of response or data-in until this value reached
+ * | | |The time period depends on SD engine clock frequency
+ * | | |Do not write a small number into this field, or you may never get response or data due to time-out.
+ * | | |Note: Filling 0x0 into this field will disable hardware time-out function.
+ */
+
+ __IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[224];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */
+ __I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */
+ __IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */
+ __IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[250];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */
+ __IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */
+ __I uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */
+ __IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */
+ __IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */
+ __IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */
+ __I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */
+ __I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */
+ __IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */
+ __IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */
+
+} SDH_T;
+
+
+/**
+ @addtogroup SDH_CONST SDH Bit Field Definition
+ Constant Definitions for SDH Controller
+@{ */
+
+#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */
+#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */
+
+#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */
+#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */
+
+#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */
+#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */
+
+#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */
+#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */
+
+#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */
+#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */
+
+#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */
+#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */
+
+#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */
+#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */
+
+#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */
+#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */
+
+#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */
+#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */
+
+#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */
+#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */
+
+#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */
+#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */
+
+#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */
+#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */
+
+#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */
+#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */
+
+#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */
+#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */
+
+#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */
+#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */
+
+#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */
+#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */
+
+#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */
+#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */
+
+#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */
+#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */
+
+#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */
+#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */
+
+#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */
+#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */
+
+#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */
+#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */
+
+#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */
+#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */
+
+#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */
+#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */
+
+#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */
+#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */
+
+#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */
+#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */
+
+#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */
+#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */
+
+#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */
+#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */
+
+#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */
+#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */
+
+#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */
+#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */
+
+#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */
+#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */
+
+#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */
+#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */
+
+#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */
+#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */
+
+#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */
+#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */
+
+#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */
+#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */
+
+#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */
+#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */
+
+#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */
+#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */
+
+#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */
+#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */
+
+#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */
+#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */
+
+#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */
+#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */
+
+#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */
+#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */
+
+#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */
+#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */
+
+#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */
+#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */
+
+#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */
+#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */
+
+#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */
+#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */
+
+#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */
+#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */
+
+#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */
+#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */
+
+#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */
+#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */
+
+#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */
+#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */
+
+#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */
+#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */
+
+#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */
+#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */
+
+#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */
+#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */
+
+/**@}*/ /* SDH_CONST */
+/**@}*/ /* end of SDH register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __SDH_REG_H__ */
+
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spi_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spi_reg.h
new file mode 100644
index 00000000000..9bb647fe144
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spi_reg.h
@@ -0,0 +1,800 @@
+/**************************************************************************//**
+ * @file spi_reg.h
+ * @version V1.00
+ * @brief SPI register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SPI_REG_H__
+#define __SPI_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup SPI Serial Peripheral Interface Controller(SPI)
+ Memory Mapped Structure for SPI Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var SPI_T::CTL
+ * Offset: 0x00 SPI Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SPIEN |SPI Transfer Control Enable Bit
+ * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
+ * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
+ * | | |0 = Transfer control Disabled.
+ * | | |1 = Transfer control Enabled.
+ * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
+ * |[1] |RXNEG |Receive on Negative Edge
+ * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
+ * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
+ * |[2] |TXNEG |Transmit on Negative Edge
+ * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
+ * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock.
+ * |[3] |CLKPOL |Clock Polarity
+ * | | |0 = SPI bus clock is idle low.
+ * | | |1 = SPI bus clock is idle high.
+ * |[7:4] |SUSPITV |Suspend Interval (Master Only)
+ * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
+ * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
+ * | | |The default value is 0x3
+ * | | |The period of the suspend interval is obtained according to the following equation.
+ * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
+ * | | |Example:
+ * | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle.
+ * | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle.
+ * | | |.....
+ * | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle.
+ * | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle.
+ * |[12:8] |DWIDTH |Data Width
+ * | | |This field specifies how many bits can be transmitted / received in one transaction
+ * | | |The minimum bit length is 8 bits and can up to 32 bits.
+ * | | |DWIDTH = 0x08 .... 8 bits.
+ * | | |DWIDTH = 0x09 .... 9 bits.
+ * | | |.....
+ * | | |DWIDTH = 0x1F .... 31 bits.
+ * | | |DWIDTH = 0x00 .... 32 bits.
+ * | | |Note: For SPI1~SPI4, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode
+ * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI1~SPI4.
+ * |[13] |LSB |Send LSB First
+ * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
+ * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
+ * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit
+ * | | |This bit is used to select full-duplex or half-duplex for SPI transfer
+ * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
+ * | | |0 = SPI operates in full-duplex transfer.
+ * | | |1 = SPI operates in half-duplex transfer.
+ * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
+ * | | |This bit field is only available in Master mode
+ * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
+ * | | |0 = Receive-only mode Disabled.
+ * | | |1 = Receive-only mode Enabled.
+ * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
+ * | | |0 = SPI unit transfer interrupt Disabled.
+ * | | |1 = SPI unit transfer interrupt Enabled.
+ * |[18] |SLAVE |Slave Mode Control
+ * | | |0 = Master mode.
+ * | | |1 = Slave mode.
+ * |[19] |REORDER |Byte Reorder Function Enable Bit
+ * | | |0 = Byte Reorder function Disabled.
+ * | | |1 = Byte Reorder function Enabled
+ * | | |A byte suspend interval will be inserted among each byte
+ * | | |The period of the byte suspend interval depends on the setting of SUSPITV.
+ * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
+ * |[20] |DATDIR |Data Port Direction Control
+ * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
+ * | | |0 = SPI data is input direction.
+ * | | |1 = SPI data is output direction.
+ * @var SPI_T::CLKDIV
+ * Offset: 0x04 SPI Clock Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |DIVIDER |Clock Divider
+ * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master
+ * | | |The frequency is obtained according to the following equation.
+ * | | |where
+ * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
+ * | | |Note: Not supported in I2S mode.
+ * @var SPI_T::SSCTL
+ * Offset: 0x08 SPI Slave Select Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SS |Slave Selection Control (Master Only)
+ * | | |If AUTOSS bit is cleared to 0,
+ * | | |0 = set the SPIx_SS line to inactive state.
+ * | | |1 = set the SPIx_SS line to active state.
+ * | | |If the AUTOSS bit is set to 1,
+ * | | |0 = Keep the SPIx_SS line at inactive state.
+ * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
+ * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]).
+ * |[2] |SSACTPOL |Slave Selection Active Polarity
+ * | | |This bit defines the active polarity of slave selection signal (SPIx_SS).
+ * | | |0 = The slave selection signal SPIx_SS is active low.
+ * | | |1 = The slave selection signal SPIx_SS is active high.
+ * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
+ * | | |0 = Automatic slave selection function Disabled
+ * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]).
+ * | | |1 = Automatic slave selection function Enabled.
+ * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
+ * | | |0 = Slave mode bit count error interrupt Disabled.
+ * | | |1 = Slave mode bit count error interrupt Enabled.
+ * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
+ * | | |0 = Slave mode TX under run interrupt Disabled.
+ * | | |1 = Slave mode TX under run interrupt Enabled.
+ * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
+ * | | |0 = Slave select active interrupt Disabled.
+ * | | |1 = Slave select active interrupt Enabled.
+ * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
+ * | | |0 = Slave select inactive interrupt Disabled.
+ * | | |1 = Slave select inactive interrupt Enabled.
+ * @var SPI_T::PDMACTL
+ * Offset: 0x0C SPI PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TXPDMAEN |Transmit PDMA Enable Bit
+ * | | |0 = Transmit PDMA function Disabled.
+ * | | |1 = Transmit PDMA function Enabled.
+ * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
+ * | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
+ * |[1] |RXPDMAEN |Receive PDMA Enable Bit
+ * | | |0 = Receive PDMA function Disabled.
+ * | | |1 = Receive PDMA function Enabled.
+ * |[2] |PDMARST |PDMA Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
+ * @var SPI_T::FIFOCTL
+ * Offset: 0x10 SPI FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXRST |Receive Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset receive FIFO pointer and receive circuit
+ * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
+ * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
+ * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
+ * |[1] |TXRST |Transmit Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset transmit FIFO pointer and transmit circuit
+ * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
+ * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
+ * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
+ * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
+ * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
+ * | | |0 = RX FIFO threshold interrupt Disabled.
+ * | | |1 = RX FIFO threshold interrupt Enabled.
+ * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
+ * | | |0 = TX FIFO threshold interrupt Disabled.
+ * | | |1 = TX FIFO threshold interrupt Enabled.
+ * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
+ * | | |0 = Receive time-out interrupt Disabled.
+ * | | |1 = Receive time-out interrupt Enabled.
+ * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
+ * | | |0 = Receive FIFO overrun interrupt Disabled.
+ * | | |1 = Receive FIFO overrun interrupt Enabled.
+ * |[6] |TXUFPOL |TX Underflow Data Polarity
+ * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
+ * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
+ * | | |Note:
+ * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
+ * | | |2. This bit should be set as 0 in I2S mode.
+ * | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
+ * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
+ * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
+ * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1
+ * | | |This bit is used to enable the TX underflow interrupt.
+ * | | |0 = Slave TX underflow interrupt Disabled.
+ * | | |1 = Slave TX underflow interrupt Enabled.
+ * |[8] |RXFBCLR |Receive FIFO Buffer Clear
+ * | | |0 = No effect.
+ * | | |1 = Clear receive FIFO pointer
+ * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
+ * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+ * | | |Note: The RX shift register will not be cleared.
+ * |[9] |TXFBCLR |Transmit FIFO Buffer Clear
+ * | | |0 = No effect.
+ * | | |1 = Clear transmit FIFO pointer
+ * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
+ * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+ * | | |Note: The TX shift register will not be cleared.
+ * |[26:24] |RXTH |Receive FIFO Threshold
+ * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
+ * | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
+ * |[30:28] |TXTH |Transmit FIFO Threshold
+ * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
+ * | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length
+ * @var SPI_T::STATUS
+ * Offset: 0x14 SPI Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSY |Busy Status (Read Only)
+ * | | |0 = SPI controller is in idle state.
+ * | | |1 = SPI controller is in busy state.
+ * | | |The following listing are the bus busy conditions:
+ * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0.
+ * | | |b
+ * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
+ * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1.
+ * | | |d
+ * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
+ * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
+ * |[1] |UNITIF |Unit Transfer Interrupt Flag
+ * | | |0 = No transaction has been finished since this bit was cleared to 0.
+ * | | |1 = SPI controller has finished one unit transfer.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[2] |SSACTIF |Slave Select Active Interrupt Flag
+ * | | |0 = Slave select active interrupt was cleared or not occurred.
+ * | | |1 = Slave select active interrupt event occurred.
+ * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+ * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
+ * | | |0 = Slave select inactive interrupt was cleared or not occurred.
+ * | | |1 = Slave select inactive interrupt event occurred.
+ * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+ * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
+ * | | |0 = The slave select line status is 0.
+ * | | |1 = The slave select line status is 1.
+ * | | |Note: This bit is only available in Slave mode
+ * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
+ * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
+ * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
+ * | | |0 = No Slave mode bit count error event.
+ * | | |1 = Slave mode bit count error event occurs.
+ * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
+ * | | |This bit will be cleared by writing 1 to it.
+ * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
+ * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
+ * | | |0 = No Slave TX under run event.
+ * | | |1 = Slave TX under run event occurs.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
+ * | | |0 = Receive FIFO buffer is not empty.
+ * | | |1 = Receive FIFO buffer is empty.
+ * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
+ * | | |0 = Receive FIFO buffer is not full.
+ * | | |1 = Receive FIFO buffer is full.
+ * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
+ * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+ * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
+ * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+ * | | |0 = No FIFO is overrun.
+ * | | |1 = Receive FIFO is overrun.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[12] |RXTOIF |Receive Time-out Interrupt Flag
+ * | | |0 = No receive FIFO time-out event.
+ * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode
+ * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[15] |SPIENSTS |SPI Enable Status (Read Only)
+ * | | |0 = The SPI controller is disabled.
+ * | | |1 = The SPI controller is enabled.
+ * | | |Note: The SPI peripheral clock is asynchronous with the system clock
+ * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
+ * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
+ * | | |0 = Transmit FIFO buffer is not empty.
+ * | | |1 = Transmit FIFO buffer is empty.
+ * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
+ * | | |0 = Transmit FIFO buffer is not full.
+ * | | |1 = Transmit FIFO buffer is full.
+ * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+ * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+ * |[19] |TXUFIF |TX Underflow Interrupt Flag
+ * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
+ * | | |0 = No effect.
+ * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
+ * | | |Note 1: This bit will be cleared by writing 1 to it.
+ * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
+ * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
+ * | | |0 = The reset function of TXRST or RXRST is done.
+ * | | |1 = Doing the reset function of TXRST or RXRST.
+ * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
+ * | | |User can check the status of this bit to monitor the reset function is doing or done.
+ * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
+ * | | |This bit field indicates the valid data count of receive FIFO buffer.
+ * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
+ * | | |This bit field indicates the valid data count of transmit FIFO buffer.
+ * @var SPI_T::TX
+ * Offset: 0x20 SPI Data Transmit Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TX |Data Transmit Register
+ * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
+ * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
+ * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
+ * | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.
+ * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]
+ * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
+ * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
+ * @var SPI_T::RX
+ * Offset: 0x30 SPI Data Receive Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RX |Data Receive Register
+ * | | |There are 4-level FIFO buffers in this controller
+ * | | |The data receive register holds the data received from SPI data input pin
+ * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register
+ * | | |This is a read only register.
+ * @var SPI_T::I2SCTL
+ * Offset: 0x60 I2S Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |I2SEN |I2S Controller Enable Bit
+ * | | |0 = Disabled I2S mode.
+ * | | |1 = Enabled I2S mode.
+ * | | |Note:
+ * | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode.
+ * | | |2
+ * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
+ * |[1] |TXEN |Transmit Enable Bit
+ * | | |0 = Data transmit Disabled.
+ * | | |1 = Data transmit Enabled.
+ * |[2] |RXEN |Receive Enable Bit
+ * | | |0 = Data receive Disabled.
+ * | | |1 = Data receive Enabled.
+ * |[3] |MUTE |Transmit Mute Enable Bit
+ * | | |0 = Transmit data is shifted from buffer.
+ * | | |1 = Transmit channel zero.
+ * |[5:4] |WDWIDTH |Word Width
+ * | | |00 = data size is 8-bit.
+ * | | |01 = data size is 16-bit.
+ * | | |10 = data size is 24-bit.
+ * | | |11 = data size is 32-bit.
+ * |[6] |MONO |Monaural Data
+ * | | |0 = Data is stereo format.
+ * | | |1 = Data is monaural format.
+ * |[7] |ORDER |Stereo Data Order in FIFO
+ * | | |0 = Left channel data at high byte.
+ * | | |1 = Left channel data at low byte.
+ * |[8] |SLAVE |Slave Mode
+ * | | |I2S can operate as master or slave
+ * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M480 series to audio CODEC chip
+ * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
+ * | | |0 = Master mode.
+ * | | |1 = Slave mode.
+ * |[15] |MCLKEN |Master Clock Enable Bit
+ * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
+ * | | |0 = Master clock Disabled.
+ * | | |1 = Master clock Enabled.
+ * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
+ * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1
+ * | | |This function is only available in transmit operation.
+ * | | |0 = Right channel zero cross detection Disabled.
+ * | | |1 = Right channel zero cross detection Enabled.
+ * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
+ * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1
+ * | | |This function is only available in transmit operation.
+ * | | |0 = Left channel zero cross detection Disabled.
+ * | | |1 = Left channel zero cross detection Enabled.
+ * |[23] |RXLCH |Receive Left Channel Enable Bit
+ * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
+ * | | |0 = Receive right channel data in Mono mode.
+ * | | |1 = Receive left channel data in Mono mode.
+ * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit
+ * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit
+ * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[29:28] |FORMAT |Data Format Selection
+ * | | |00 = I2S data format.
+ * | | |01 = MSB justified data format.
+ * | | |10 = PCM mode A.
+ * | | |11 = PCM mode B.
+ * @var SPI_T::I2SCLK
+ * Offset: 0x64 I2S Clock Divider Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |MCLKDIV |Master Clock Divider
+ * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices
+ * | | |The frequency of master clock, fMCLK, is determined by the following expressions:
+ * | | |If MCLKDIV >= 1,.
+ * | | |If MCLKDIV = 0,.
+ * | | |where
+ * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2
+ * | | |In general, the master clock rate is 256 times sampling clock rate.
+ * |[17:8] |BCLKDIV |Bit Clock Divider
+ * | | |The I2S controller will generate bit clock in Master mode
+ * | | |The clock frequency of bit clock , fBCLK, is determined by the following expression:
+ * | | |where
+ * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
+ * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
+ * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
+ * @var SPI_T::I2SSTS
+ * Offset: 0x68 I2S Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4] |RIGHT |Right Channel (Read Only)
+ * | | |This bit indicates the current transmit data is belong to which channel.
+ * | | |0 = Left channel.
+ * | | |1 = Right channel.
+ * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
+ * | | |0 = Receive FIFO buffer is not empty.
+ * | | |1 = Receive FIFO buffer is empty.
+ * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
+ * | | |0 = Receive FIFO buffer is not full.
+ * | | |1 = Receive FIFO buffer is full.
+ * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
+ * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+ * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
+ * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
+ * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[12] |RXTOIF |Receive Time-out Interrupt Flag
+ * | | |0 = No receive FIFO time-out event.
+ * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode
+ * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[15] |I2SENSTS |I2S Enable Status (Read Only)
+ * | | |0 = The SPI/I2S control logic is disabled.
+ * | | |1 = The SPI/I2S control logic is enabled.
+ * | | |Note: The SPI peripheral clock is asynchronous with the system clock
+ * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
+ * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
+ * | | |0 = Transmit FIFO buffer is not empty.
+ * | | |1 = Transmit FIFO buffer is empty.
+ * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
+ * | | |0 = Transmit FIFO buffer is not full.
+ * | | |1 = Transmit FIFO buffer is full.
+ * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+ * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+ * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
+ * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
+ * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
+ * | | |0 = No zero cross event occurred on right channel.
+ * | | |1 = Zero cross event occurred on right channel.
+ * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
+ * | | |0 = No zero cross event occurred on left channel.
+ * | | |1 = Zero cross event occurred on left channel.
+ * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
+ * | | |0 = The reset function of TXRST or RXRST is done.
+ * | | |1 = Doing the reset function of TXRST or RXRST.
+ * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
+ * | | |User can check the status of this bit to monitor the reset function is doing or done.
+ * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
+ * | | |This bit field indicates the valid data count of receive FIFO buffer.
+ * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
+ * | | |This bit field indicates the valid data count of transmit FIFO buffer.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */
+ __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */
+ __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */
+ __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */
+ __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */
+ __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[11];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */
+ __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */
+ __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */
+
+} SPI_T;
+
+/**
+ @addtogroup SPI_CONST SPI Bit Field Definition
+ Constant Definitions for SPI Controller
+@{ */
+
+#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
+#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
+
+#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
+#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
+
+#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
+#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
+
+#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
+#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
+
+#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
+#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
+
+#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
+#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
+
+#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
+#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
+
+#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */
+#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */
+
+#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */
+#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */
+
+#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
+#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
+
+#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
+#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
+
+#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
+#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
+
+#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */
+#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */
+
+#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
+#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
+
+#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
+#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
+
+#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
+#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
+
+#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
+#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
+
+#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
+#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
+
+#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
+#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
+
+#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
+#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
+
+#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
+#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
+
+#define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */
+#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */
+
+#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
+#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
+
+#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
+#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
+
+#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
+#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
+
+#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
+#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
+
+#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
+#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
+
+#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
+#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
+
+#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
+#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
+
+#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
+#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
+
+#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
+#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
+
+#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
+#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
+
+#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
+#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
+
+#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
+#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
+
+#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
+#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
+
+#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
+#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
+
+#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
+#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
+
+#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
+#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
+
+#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
+#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
+
+#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
+#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
+
+#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
+#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
+
+#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
+#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
+
+#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
+#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
+
+#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
+#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
+
+#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
+#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
+
+#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
+#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
+
+#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
+#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
+
+#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
+#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
+
+#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
+#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
+
+#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
+#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
+
+#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
+#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
+
+#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
+#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
+
+#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
+#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
+
+#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
+#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
+
+#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
+#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
+
+#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
+#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
+
+#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
+#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
+
+#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
+#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
+
+#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
+#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
+
+#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
+#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
+
+#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
+#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
+
+#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
+#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
+
+#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
+#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
+
+#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
+#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
+
+#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
+#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
+
+#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
+#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
+
+#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
+#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
+
+#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
+#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
+
+#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
+#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
+
+#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
+#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
+
+#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
+#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
+
+#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
+#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
+
+#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
+#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
+
+#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
+#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
+
+#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
+#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
+
+#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
+#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
+
+#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
+#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
+
+#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
+#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
+
+#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
+#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
+
+#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
+#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
+
+#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
+#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
+
+#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
+#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
+
+#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
+#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
+
+#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
+#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
+
+#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
+#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
+
+#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
+#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
+
+#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
+#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
+
+#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
+#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
+
+#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
+#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
+
+#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
+#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
+
+#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
+#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
+
+#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
+#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
+
+/**@}*/ /* SPI_CONST */
+/**@}*/ /* end of SPI register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __SPI_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spim_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spim_reg.h
new file mode 100644
index 00000000000..59a9a343f18
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spim_reg.h
@@ -0,0 +1,557 @@
+/**************************************************************************//**
+ * @file spim_reg.h
+ * @version V1.00
+ * @brief SPIM register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SPIM_REG_H__
+#define __SPIM_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup SPIM Serial Peripheral Interface Controller Master Mode (SPIM)
+ Memory Mapped Structure for SPIM Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var SPIM_T::CTL0
+ * Offset: 0x00 Control and Status Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CIPHOFF |Cipher Disable Control
+ * | | |0 = Cipher function Enabled.
+ * | | |1 = Cipher function Disabled.
+ * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
+ * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
+ * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
+ * | | |Note3 : When cipher encryption/decryption is enabled, please set DESELTIM (SPIM_DMMCTL[20:16]) >= 0x10.
+ * | | |When cipher encryption/decryption is disabled, please set DESELTIM(SPIM_DMMCTL[20:16]) >= 0x8.
+ * |[2] |BALEN |Balance the AHB Control Time Between Cipher Enable and Disable Control
+ * | | |When cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation
+ * | | |Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled.
+ * | | |Note: Only useful when cipher is disabled.
+ * |[5] |B4ADDREN |4-byte Address Mode Enable Control
+ * | | |0 = 4-byte address mode is disabled, and 3-byte address mode is enabled.
+ * | | |1 = 4-byte address mode is enabled.
+ * | | |Note: Used for DMA write mode, DMA read mode, and DMM mode.
+ * |[6] |IEN |Interrupt Enable Control
+ * | | |0 = SPIM Interrupt Disabled.
+ * | | |1 = SPIM Interrupt Enabled.
+ * |[7] |IF |Interrupt Flag
+ * | | |(1) Write Operation :
+ * | | |0 = No effect.
+ * | | |1 = Write 1 to clear.
+ * | | |(2) Read Operation :
+ * | | |0 = The transfer has not finished yet.
+ * | | |1 = The transfer has done.
+ * |[12:8] |DWIDTH |Transmit/Receive Bit Length
+ * | | |This specifies how many bits are transmitted/received in one transmit/receive transaction.
+ * | | |0x7 = 8 bits.
+ * | | |0xF = 16 bits.
+ * | | |0x17 = 24 bits.
+ * | | |0x1F = 32 bits.
+ * | | |Others = Incorrect transfer result.
+ * | | |Note1: Only used for normal I/O mode.
+ * | | |Note2: Only 8, 16, 24, and 32 bits are allowed. Other bit length will result in incorrect transfer.
+ * |[14:13] |BURSTNUM |Transmit/Receive Burst Number
+ * | | |This field specifies how many transmit/receive transactions should be executed continuously in one transfer.
+ * | | |0x0 = Only one transmit/receive transaction will be executed in one transfer.
+ * | | |0x1 = Two successive transmit/receive transactions will be executed in one transfer.
+ * | | |0x2 = Three successive transmit/receive transactions will be executed in one transfer.
+ * | | |0x3 = Four successive transmit/receive transactions will be executed in one transfer.
+ * | | |Note: Only used for normal I/O Mode.
+ * |[15] |QDIODIR |SPI Interface Direction Select for Quad/Dual Mode
+ * | | |0 = Interface signals are input.
+ * | | |1 = Interface signals are output.
+ * | | |Note: Only used for normal I/O mode.
+ * |[19:16] |SUSPITV |Suspend Interval
+ * | | |These four bits provide the configuration of suspend interval between two successive transmit/receive transactions in a transfer
+ * | | |The default value is 0x00
+ * | | |When BURSTNUM = 00, setting this field has no effect on transfer
+ * | | |The desired interval is obtained according to the following equation (from the last falling edge of current SPI clock to the first rising edge of next SPI clock):
+ * | | | (SUSPITV+2)*period of AHB clock
+ * | | | 0x0 = 2 AHB clock cycles.
+ * | | | 0x1 = 3 AHB clock cycles.
+ * | | | ......
+ * | | | 0xE = 16 AHB clock cycles.
+ * | | | 0xF = 17 AHB clock cycles.
+ * | | | Note: Only used for normal I/O mode.
+ * |[21:20] |BITMODE |SPI Interface Bit Mode
+ * | | |0x0 = Standard mode.
+ * | | |0x1 = Dual mode.
+ * | | |0x2 = Quad mode.
+ * | | |0x3 = Reserved.
+ * | | |Note: Only used for normal I/O mode.
+ * |[23:22] |OPMODE |SPI Function Operation Mode
+ * | | |0x0 = Normal I/O mode. (Note1) (Note3)
+ * | | |0x1 = DMA write mode. (Note2) (Note3)
+ * | | |0x2 = DMA read mode. (Note3)
+ * | | |0x3 = Direct Memory Mapping mode (DMM mode) (Default). (Note4)
+ * | | |Note1 : After user uses Normal I/O mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
+ * | | |Note2 : In DMA write mode, hardware will send just one page program command per operation
+ * | | |Users must take care of cross-page cases
+ * | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
+ * | | |Note3 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x00000000 to 0x01FFFFFF when user uses Normal I/O mode, DMA write mode, and DMA read mode to write/read external SPI flash data
+ * | | |Please user check size of used SPI flash component to know access address range of external SPI flash.
+ * | | |Note4 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x08000000 to 0x09FFFFFF when user uses Direct Memory mapping mode (DMM mode) to read external SPI flash data
+ * | | |Please user check size of used SPI flash component to know access address range of external SPI flash.
+ * |[31:24] |CMDCODE |Page Program Command Code (Note4)
+ * | | |(1) 0x02 = Page program (Used for DMA Write mode).
+ * | | |(2) 0x32 = Quad page program with TYPE_1 program flow (Used for DMA Write mode). (Note3)
+ * | | |(3) 0x38 = Quad page program with TYPE_2 program flow (Used for DMA Write mode). (Note3)
+ * | | |(4) 0x40 = Quad page program with TYPE_3 program flow (Used for DMA Write mode). (Note3)
+ * | | |The Others = Reserved.
+ * | | |Read Command Code :
+ * | | |(1) 0x03 = Standard Read (Used for DMA Read/DMM mode).
+ * | | |(2) 0x0B = Fast Read (Used for DMA Read/DMM mode).
+ * | | |The fast read command code "0x0B" is similar to command code of standard read "0x03" except it can operate at highest possible frequency
+ * | | |(Note2)
+ * | | |(3) 0x3B = Fast Read Dual Output (Used for DMA Read/DMM mode).
+ * | | |(4) 0xBB = Fast Read Dual I/O (Used for DMA Read/DMM mode).
+ * | | |The fast read dual I/O command code "0xBB" is similar to command code of fast read dual output "0x3B" but with capability to input the address bits two bits per clock
+ * | | |(Note2)
+ * | | |(5) 0xEB = Fast quad read (Used for DMA Read/DMM mode).
+ * | | |(6) 0xE7 = Word quad read (Used for DMA Read/DMM mode).
+ * | | |The command code of word quad read "0xE7" is similar to command code of fast quad read "0xEB" except that the lowest address bit must equal to 0 and the number of dummy cycles is less than fast quad read
+ * | | |(Note2)
+ * | | |(7) 0x0D = DTR/DDR Fast read (Used for DMA Read/DMM mode).
+ * | | |(8) 0xBD = DTR/DDR dual read (Used for DMA Read/DMM mode).
+ * | | |(9) 0xED = DTR/DDR quad read (Used for DMA Read/DMM mode).
+ * | | |The Others command codes are Reserved.
+ * | | |The DTR/DDR read commands "0x0D,0xBD,0xED" improves throughput by transferring address and data on both the falling and rising edge of SPI flash clock (SPIM_CLK)
+ * | | |It is similar to those commands "0x0B, 0xBB, 0xEB" but allows transfer of address and data on rising edge and falling edge of SPI flash output clock
+ * | | |(Note2)
+ * | | |Note1: Quad mode of SPI Flash must be enabled first by normal I/O mode before using quad page program/quad read commands.
+ * | | |Note2: See SPI flash specifications for support items.
+ * | | |Note3: For TYPE_1, TYPE_2, and TYPE_3 of page program command code, refer to Figure 7.19-3, Figure 7.19-4, and Figure 7.19-5.
+ * | | |Note4: Please disable "continuous read mode" and "burst wrap mode" before DMA write mode of SPI flash controller is used to program data of external SPI flash
+ * | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
+ * @var SPIM_T::CTL1
+ * Offset: 0x04 Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SPIMEN |Go and Busy Status
+ * | | |(1) Write Operation :
+ * | | |0 = No effect.
+ * | | |1 = Start the transfer
+ * | | |This bit remains set during the transfer and is automatically cleared after transfer finished.
+ * | | |(2) Read Operation :
+ * | | |0 = The transfer has done.
+ * | | |1 = The transfer has not finished yet.
+ * | | |Note: All registers should be set before writing 1 to the SPIMEN bit
+ * | | |When a transfer is in progress, you should not write to any register of this peripheral.
+ * |[1] |CACHEOFF |Cache Memory Function Disable Control
+ * | | |0 = Cache memory function enable. (Default value)
+ * | | |1 = Cache memory function disable.
+ * | | |Note: When CCM mode is enabled, the cache function will be disable by hardware automatically
+ * | | |When CCM mode is disabled, the cache function can be enable or disable by user.
+ * |[2] |CCMEN |CCM (Core Coupled Memory) Mode Enable Control
+ * | | |0 = CCM mode disable. (Default value)
+ * | | |1 = CCM mode enable.
+ * | | |Note1: When CCM mode is enabled, the cache function will be disable by hardware automatically
+ * | | |When CCM mode is disabled, the cache function can be enabled or disabled by user.
+ * | | |Note2: When CCM mode is disabled, user accesses the core coupled memory by bus master
+ * | | |In this case, the SPI flash controller will send error response via HRESP bus signal to bus master.
+ * | | |Note3: When CCM mode needs to be enabled, user sets CCMEN to 1 and needs to read this register to show the current hardware status
+ * | | |When reading data of CCMEN is 1, MCU can start to read data from CCM memory space or write data to CCM memory space.
+ * |[3] |CDINVAL |Cache Data Invalid Enable Control
+ * | | |(1) Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set all cache data to be invalid. This bit is cleared by hardware automatically.
+ * | | |(2) Read Operation : No effect
+ * | | |Note: When SPI flash memory is page erasing or whole flash erasing, please set CDINVAL to 0x1
+ * | | |After user uses normal I/O mode or DMA write mode of SPI flash controller to program or erase the content of external SPI flash, please set CDINVAL to 0x1.
+ * |[4] |SS |Slave Select Active Enable Control
+ * | | |0 = SPIM_SS is in active level.
+ * | | |1 = SPIM_SS is in inactive level (Default).
+ * | | |Note: This interface can only drive one device/slave at a given time
+ * | | |Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer
+ * | | |Functional description of SSACTPOL(SPIM_CTL1[5]) and SS is shown in Table 2.
+ * |[5] |SSACTPOL |Slave Select Active Level
+ * | | |It defines the active level of device/slave select signal (SPIM_SS), and we show in Table 2.
+ * | | |0 = The SPIM_SS slave select signal is active low.
+ * | | |1 = The SPIM_SS slave select signal is active high.
+ * |[11:8] |IDLETIME |Idle Time Interval
+ * | | |In DMM mode, IDLETIME is set to control the minimum idle time between two SPI Flash accesses.
+ * | | |Minimum idle time = (IDLETIME + 1) * AHB clock cycle time.
+ * | | |Note1: Only used for DMM mode.
+ * | | |Note2 : AHB clock cycle time = 1/AHB clock frequency.
+ * |[31:16] |DIVIDER |Clock Divider Register
+ * | | |The value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock "SCLK" on the output SPIM_CLK pin
+ * | | |The desired frequency is obtained according to the following equation:
+ * | | |Note1: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of HCLK.
+ * | | |Note2: SCLK is serial SPI output clock.
+ * | | |Note3: Please check the specification of the used SPI flash component to decide the frequency of SPI flash clock.
+ * | | |Note4: For DTR/DDR read commands "0x0D, 0xBD, 0xED", the setting values of DIVIDER are only 1,2,4,8,16,32,..., where n = 0,1,2,3,4, ...
+ * @var SPIM_T::RXCLKDLY
+ * Offset: 0x0C RX Clock Delay Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DWDELSEL |SPI flash deselect time interval of DMA write mode
+ * | | |For DMA write mode only
+ * | | |This register sets the deselect time interval of SPI flash (i.e.
+ * | | |time interval of inactive level of SPIM_SS) when SPI flash controller operates on DMA write mode
+ * | | |(Note1)
+ * | | |Deselect time interval of DMA write mode = (DWDELSEL + 1) * AHB clock cycle time (Note2).
+ * | | |Note1: Please user check the used external SPI flash component to set this register value
+ * | | |In general case, the deselect time interval of SPI flash is greater than 50 ns when SPI flash performs the program operation.
+ * | | |Note2: AHB clock cycle time = 1/AHB clock frequency.
+ * |[18:16] |RDDLYSEL |Sampling Clock Delay Selection for Received Data
+ * | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode
+ * | | |Determine the number of inserted delay cycles
+ * | | |Used to adjust the sampling clock of received data to latch the correct data.
+ * | | |0x0 : No delay. (Default Value)
+ * | | |0x1 : Delay 1 SPI flash clock.
+ * | | |0x2 : Delay 2 SPI flash clocks.
+ * | | |0x3 : Delay 3 SPI flash clocks.
+ * | | |...
+ * | | |0x7 : Delay 7 SPI flash clocks
+ * | | |Note : We can use manufacturer id or device id of external SPI flash component to determine the correct setting value of RDDLYSEL, and we give example as follows.
+ * | | |For example, manufacturer id and device id of external SPI flash for some vendor are 0xEF and 0x1234 separately
+ * | | |Firstly, we set RDDLYSEL to 0x0, and use read manufacturer id/device id command to read the manufacturer id of external SPI flash by using normal I/O mode (the manufacturer id is 0xEF (1110_1111) in this example).
+ * | | |If manufacturer id which reads from external SPI flash is 0xF7 (1111_0111), it denotes that manufacturer id is shifted the right by 1 bit and most significant bit (MSB) of manufacturer id is assigned to 1
+ * | | |According to manufacturer id reads from external SPI flash, we need to set RDDLYSEL to 0x1 to receive SPI flash data correctly.
+ * |[20] |RDEDGE |Sampling Clock Edge Selection for Received Data
+ * | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode
+ * | | |0 : Use SPI input clock rising edge to sample received data. (Default Value)
+ * | | |1 : Use SPI input clock falling edge to sample received data.
+ * @var SPIM_T::RX[4]
+ * Offset: 0x10 ~ 0x1C Data Receive Register 0 ~ 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RXDAT |Data Receive Register
+ * | | |The Data Receive Registers hold the received data of the last executed transfer.
+ * | | |Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]
+ * | | |If BURSTNUM > 0, received data are held in the most significant RXDAT register first.
+ * | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH]
+ * | | |If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RXDAT register first.
+ * | | |In a byte, received data are held in the most significant bit of RXDAT register first.
+ * | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, received data will be held in the order SPIM_RX3[23:0], SPIM_RX2[23:0], SPIM_RX1[23:0], SPIM_RX0[23:0].
+ * | | |Example 2: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, received data will be held in the order SPIM_RX0[7:0], SPIM_RX0[15:8], SPIM_RX0[23:16].
+ * | | |Example 3: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, received data will be held in the order SPIM_RX0[7], SPIM_RX0[6], ...,
+ * | | |SPIM_RX0[0].
+ * @var SPIM_T::TX[4]
+ * Offset: 0x20 ~ 0x2C Data Transmit Register 0 ~ 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TXDAT |Data Transmit Register
+ * | | |The Data Transmit Registers hold the data to be transmitted in next transfer.
+ * | | |Number of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM]
+ * | | |If BURSTNUM > 0, data are transmitted in the most significant TXDAT register first.
+ * | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH]
+ * | | |If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TXDAT register first.
+ * | | |In a byte, data are transmitted in the most significant bit of TXDAT register first.
+ * | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX3[23:0], SPIM_TX2[23:0], SPIM_TX1[23:0], SPIM_TX0[23:0] in next transfer.
+ * | | |Example 2: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX0[7:0], SPIM_TX0[15:8], SPIM_TX0[23:16] in next transfer.
+ * | | |Example 3: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, data will be transmitted in the order SPIM_TX0[7], SPIM_TX0[6], ...,
+ * | | |SPIM_TX0[0] in next transfer.
+ * @var SPIM_T::SRAMADDR
+ * Offset: 0x30 SRAM Memory Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ADDR |SRAM Memory Address
+ * | | |For DMA Read mode, this is the destination address for DMA transfer.
+ * | | |For DMA Write mode, this is the source address for DMA transfer.
+ * | | |Note: This address must be word-aligned.
+ * @var SPIM_T::DMACNT
+ * Offset: 0x34 DMA Transfer Byte Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |DMACNT |DMA Transfer Byte Count Register
+ * | | |It indicates the transfer length for DMA process.
+ * | | |Note1: The unit for counting is byte.
+ * | | |Note2: The number must be the multiple of 4.
+ * | | |Note3: Please check specification of used SPI flash to know maximum byte length of page program.
+ * @var SPIM_T::FADDR
+ * Offset: 0x38 SPI Flash Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ADDR |SPI Flash Address Register
+ * | | |For DMA Read mode, this is the source address for DMA transfer.
+ * | | |For DMA Write mode, this is the destination address for DMA transfer.
+ * | | |Note 1 : This address must be word-aligned.
+ * | | |Note 2 : For external SPI flash with 32 MB, the value of this SPI flash address register "ADDR" is from 0x00000000 to 0x01FFFFFF when user uses DMA write mode and DMA read mode to write/read external SPI flash data
+ * | | |Please user check size of used SPI flash component to know access address range of external SPI flash.
+ * @var SPIM_T::KEY1
+ * Offset: 0x3C Cipher Key1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY1 |Cipher Key1 Register
+ * | | |This is the KEY1 data for cipher function.
+ * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
+ * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
+ * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
+ * @var SPIM_T::KEY2
+ * Offset: 0x40 Cipher Key2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KEY2 |Cipher Key2 Register
+ * | | |This is the KEY2 data for cipher function.
+ * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
+ * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
+ * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
+ * @var SPIM_T::DMMCTL
+ * Offset: 0x44 Direct Memory Mapping Mode Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:8] |CRMDAT |Mode bits data for Continuous Read Mode (or performance enhance mode) (Default value = 0)
+ * | | |Only for direct memory mapping mode
+ * | | |Set the mode bits data for continuous read mode (or performance enhance mode).
+ * | | |When we set this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25]), this reduces the command phase by eight clocks and allows the read address to be immediately entered after SPIM_SS asserted to active
+ * | | |(Note1)
+ * | | |Note1 : Please check the used SPI flash specification to know the setting value of this mode bits data, and different SPI flash vendor may use different setting values.
+ * | | |Note2 : CRMDAT needs to used with CREN(SPIM_DMMCTL[25]).
+ * |[20:16] |DESELTIM |SPI Flash Deselect Time
+ * | | |Only for direct memory mapping mode
+ * | | |Set the minimum time width of SPI flash deselect time (i.e.
+ * | | |Minimum SPIM_SS deselect time), and we show in Figure 7.19-8.
+ * | | |(1) Cache function disable :
+ * | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 1) * AHB clock cycle time.
+ * | | |(2) Cache function enable :
+ * | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 4) * AHB clock cycle time.
+ * | | |Note1 : AHB clock cycle time = 1/AHB clock frequency.
+ * | | |Note2 : When cipher encryption/decryption is enabled, please set this register value >= 0x10
+ * | | |When cipher encryption/decryption is disabled, please set this register value >= 0x8.
+ * | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values.
+ * |[24] |BWEN |16 bytes Burst Wrap Mode Enable Control Register (Default value = 0)
+ * | | |Only for WINBOND SPI flash, direct memory mapping mode, Cache enable, and read command code "0xEB, and 0xE7"
+ * | | |0 = Burst Wrap Mode Disable. (Default)
+ * | | |1 = Burst Wrap Mode Enable.
+ * | | |In direct memory mapping mode, both of quad read commands "0xEB" and "0xE7" support burst wrap mode for cache application and performance enhance
+ * | | |For cache application, the burst wrap mode can be used to fill the cache line quickly (In this SPI flash controller, we use cache data line with 16 bytes size)
+ * | | |For performance enhance with direct memory mapping mode and cache enable, when cache data is miss, the burst wrap mode can let MCU get the required SPI flash data quickly.
+ * |[25] |CREN |Continuous Read Mode Enable Control
+ * | | |Only for direct memory mapping mode, read command codes 0xBB, 0xEB, 0xE7, 0x0D, 0xBD, 0xED (Note2)
+ * | | |0 = Continuous Read Mode Disable. (Default)
+ * | | |1 = Continuous Read Mode Enable.
+ * | | |For read operations of SPI flash, commands of fast read quad I/O (0xEB), word read quad I/O (0xE7 in Winbond SPI flash), fast read dual I/O (0xBB), DTR/DDR fast read (0x0D), DTR/DDR fast read dual I/O (0xBD), and DTR/DDR fast read quad I/O (0xED) can further reduce command overhead through setting the "continuous read mode" bits (8 bits) after the input address data.
+ * | | |Note: When user uses function of continuous read mode and sets USETEN (SPIM_CTL2[16]) to 1, CRMDAT(SPIM_DMMCTL[15:8]) must be set by used SPI flash specifications
+ * | | |When user uses function of continuous read mode and sets USETEN(SPIM_CTL2[16]) to 0, CRMDAT(SPIM_DMMCTL[15:8]) is set by default value of WINBOND SPI flash.
+ * |[26] |UACTSCLK |User Sets SPI Flash Active SCLK Time
+ * | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode
+ * | | |0 = According to DIVIDER(SPIM_CTL1[31:16]), ACTSCLKT(SPIM_DMMCTL[31:28]) is set by hardware automatically
+ * | | |(Default value)
+ * | | |1 = Set ACTSCLKT(SPIM_DMMCTL[31:28]) by user manually.
+ * | | |When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually, please set UACTSCLK to 1.
+ * |[31:28] |ACTSCLKT |SPI Flash Active SCLK Time
+ * | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode
+ * | | |This register sets time interval between SPIM SS active edge and the position edge of the first serial SPI output clock, and we show in Figure 7.19-8.
+ * | | |(1) ACTSCLKT = 0 (function disable) :.
+ * | | |Time interval = 1 AHB clock cycle time.
+ * | | |(2) ACTSCLKT != 0 (function enable) :
+ * | | |Time interval = (ACTSCLKT + 3) * AHB clock cycle time.
+ * | | |Note1 : AHB clock cycle time = 1/AHB clock frequency.
+ * | | |Note2 : SCLK is SPI output clock
+ * | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values.
+ * @var SPIM_T::CTL2
+ * Offset: 0x48 Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[16] |USETEN |User Set Value Enable Control
+ * | | |Only for direct memory mapping mode and DMA read mode with read commands 0x03,0x0B,0x3B,0xBB,0xEB,0xE7
+ * | | |0 = Hardware circuit of SPI flash controller will use the following default values of DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations automatically.
+ * | | |Dummy cycle number (DCNUM) :
+ * | | |Dummy cycle number for read command 0x03 : 0x0
+ * | | |Dummy cycle number for read command 0x0B : 0x8
+ * | | |Dummy cycle number for read command 0x3B : 0x8
+ * | | |Dummy cycle number for read command 0xBB : 0x0
+ * | | |Dummy cycle number for read command 0xEB : 0x4
+ * | | |Dummy cycle number for read command 0xE7 : 0x2
+ * | | |Mode bits data for continuous read mode (CRMDAT) : 0x20
+ * | | |1 = If DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) are not set as above default values, user must set USETEN to 0x1, DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations manually.
+ * | | |For DTR/DDR command codes 0x0D, 0xBD, and 0xED, please set USETEN to 0x1.
+ * |[20] |DTRMPOFF |Mode Phase OFF for DTR/DDR Command Codes 0x0D, 0xBD, and 0xED
+ * | | |Only for direct memory mapping mode and DMA read mode (Note1)
+ * | | |0 = mode cycle number (or performance enhance cycle number) does not equal to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED.
+ * | | |1 = mode cycle number (or performance enhance cycle number) equals to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED.
+ * | | |Note1 : Please check the used SPI flash specification to know the mode cycle number (or performance enhance cycle number) for DTR/DDR command codes 0x0D, 0xBD, and 0xED.
+ * |[28:24] |DCNUM |Dummy Cycle Number
+ * | | |Only for direct memory mapping mode and DMA read mode (Note1)
+ * | | |Set number of dummy cycles
+ * | | |(1) For non-DTR/non-DDR command codes 0x03, 0x0B, 0x3B, 0xBB, 0xEB, and 0xE7 :
+ * | | |When read command code do not need any dummy cycles (i.e.
+ * | | |dummy cycle number = 0x0), user must set DCNUM to 0x0.
+ * | | |For command code 0xBB, if both mode cycle number (or performance enhance cycle number) and dummy cycle number do not equal to 0x0 simultaneously, user must set DCNUM to "mode cycle number + dummy cycle number" by used SPI flash specification.
+ * | | |For command code 0xBB, if there is only dummy cycle number (i.e.
+ * | | |dummy cycle number != 0x0 and mode cycle number = 0x0 (or performance enhance cycle number = 0x0)), user set DCNUM to dummy cycle number by used SPI flash specification.
+ * | | |For command codes 0x0B, 0x3B, 0xEB, and 0xE7, user only set DCNUM to dummy cycle number by used SPI flash specification.
+ * | | |(2) For DTR/DDR command codes 0x0D, 0xBD, and 0xED :
+ * | | |user sets DCNUM to dummy cycle number and DTRMPOFF(SPIM_CTL2[20]) by used SPI flash specification.
+ * | | |Note1 : Number of dummy cycles depends on the frequency of SPI output clock, SPI flash vendor, and read command types
+ * | | |Please check the used SPI flash specification to know the setting value of this number of dummy cycles.
+ */
+ __IO uint32_t CTL0; /*!< [0x0000] Control and Status Register 0 */
+ __IO uint32_t CTL1; /*!< [0x0004] Control Register 1 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t RXCLKDLY; /*!< [0x000c] RX Clock Delay Control Register */
+ __I uint32_t RX[4]; /*!< [0x0010] ~ [0x001C] Data Receive Register 0~3 */
+ __IO uint32_t TX[4]; /*!< [0x0020] ~ [0x002C] Data Transmit Register 0~3 */
+ __IO uint32_t SRAMADDR; /*!< [0x0030] SRAM Memory Address Register */
+ __IO uint32_t DMACNT; /*!< [0x0034] DMA Transfer Byte Count Register */
+ __IO uint32_t FADDR; /*!< [0x0038] SPI Flash Address Register */
+ __O uint32_t KEY1; /*!< [0x003c] Cipher Key1 Register */
+ __O uint32_t KEY2; /*!< [0x0040] Cipher Key2 Register */
+ __IO uint32_t DMMCTL; /*!< [0x0044] Direct Memory Mapping Mode Control Register */
+ __IO uint32_t CTL2; /*!< [0x0048] Control Register 2 */
+
+} SPIM_T;
+
+/**
+ @addtogroup SPIM_CONST SPIM Bit Field Definition
+ Constant Definitions for SPIM Controller
+@{ */
+
+#define SPIM_CTL0_CIPHOFF_Pos (0) /*!< SPIM_T::CTL0: CIPHOFF Position */
+#define SPIM_CTL0_CIPHOFF_Msk (0x1ul << SPIM_CTL0_CIPHOFF_Pos) /*!< SPIM_T::CTL0: CIPHOFF Mask */
+
+#define SPIM_CTL0_BALEN_Pos (2) /*!< SPIM_T::CTL0: BALEN Position */
+#define SPIM_CTL0_BALEN_Msk (0x1ul << SPIM_CTL0_BALEN_Pos) /*!< SPIM_T::CTL0: BALEN Mask */
+
+#define SPIM_CTL0_B4ADDREN_Pos (5) /*!< SPIM_T::CTL0: B4ADDREN Position */
+#define SPIM_CTL0_B4ADDREN_Msk (0x1ul << SPIM_CTL0_B4ADDREN_Pos) /*!< SPIM_T::CTL0: B4ADDREN Mask */
+
+#define SPIM_CTL0_IEN_Pos (6) /*!< SPIM_T::CTL0: IEN Position */
+#define SPIM_CTL0_IEN_Msk (0x1ul << SPIM_CTL0_IEN_Pos) /*!< SPIM_T::CTL0: IEN Mask */
+
+#define SPIM_CTL0_IF_Pos (7) /*!< SPIM_T::CTL0: IF Position */
+#define SPIM_CTL0_IF_Msk (0x1ul << SPIM_CTL0_IF_Pos) /*!< SPIM_T::CTL0: IF Mask */
+
+#define SPIM_CTL0_DWIDTH_Pos (8) /*!< SPIM_T::CTL0: DWIDTH Position */
+#define SPIM_CTL0_DWIDTH_Msk (0x1ful << SPIM_CTL0_DWIDTH_Pos) /*!< SPIM_T::CTL0: DWIDTH Mask */
+
+#define SPIM_CTL0_BURSTNUM_Pos (13) /*!< SPIM_T::CTL0: BURSTNUM Position */
+#define SPIM_CTL0_BURSTNUM_Msk (0x3ul << SPIM_CTL0_BURSTNUM_Pos) /*!< SPIM_T::CTL0: BURSTNUM Mask */
+
+#define SPIM_CTL0_QDIODIR_Pos (15) /*!< SPIM_T::CTL0: QDIODIR Position */
+#define SPIM_CTL0_QDIODIR_Msk (0x1ul << SPIM_CTL0_QDIODIR_Pos) /*!< SPIM_T::CTL0: QDIODIR Mask */
+
+#define SPIM_CTL0_SUSPITV_Pos (16) /*!< SPIM_T::CTL0: SUSPITV Position */
+#define SPIM_CTL0_SUSPITV_Msk (0xful << SPIM_CTL0_SUSPITV_Pos) /*!< SPIM_T::CTL0: SUSPITV Mask */
+
+#define SPIM_CTL0_BITMODE_Pos (20) /*!< SPIM_T::CTL0: BITMODE Position */
+#define SPIM_CTL0_BITMODE_Msk (0x3ul << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_T::CTL0: BITMODE Mask */
+
+#define SPIM_CTL0_OPMODE_Pos (22) /*!< SPIM_T::CTL0: OPMODE Position */
+#define SPIM_CTL0_OPMODE_Msk (0x3ul << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_T::CTL0: OPMODE Mask */
+
+#define SPIM_CTL0_CMDCODE_Pos (24) /*!< SPIM_T::CTL0: CMDCODE Position */
+#define SPIM_CTL0_CMDCODE_Msk (0xfful << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_T::CTL0: CMDCODE Mask */
+
+#define SPIM_CTL1_SPIMEN_Pos (0) /*!< SPIM_T::CTL1: SPIMEN Position */
+#define SPIM_CTL1_SPIMEN_Msk (0x1ul << SPIM_CTL1_SPIMEN_Pos) /*!< SPIM_T::CTL1: SPIMEN Mask */
+
+#define SPIM_CTL1_CACHEOFF_Pos (1) /*!< SPIM_T::CTL1: CACHEOFF Position */
+#define SPIM_CTL1_CACHEOFF_Msk (0x1ul << SPIM_CTL1_CACHEOFF_Pos) /*!< SPIM_T::CTL1: CACHEOFF Mask */
+
+#define SPIM_CTL1_CCMEN_Pos (2) /*!< SPIM_T::CTL1: CCMEN Position */
+#define SPIM_CTL1_CCMEN_Msk (0x1ul << SPIM_CTL1_CCMEN_Pos) /*!< SPIM_T::CTL1: CCMEN Mask */
+
+#define SPIM_CTL1_CDINVAL_Pos (3) /*!< SPIM_T::CTL1: CDINVAL Position */
+#define SPIM_CTL1_CDINVAL_Msk (0x1ul << SPIM_CTL1_CDINVAL_Pos) /*!< SPIM_T::CTL1: CDINVAL Mask */
+
+#define SPIM_CTL1_SS_Pos (4) /*!< SPIM_T::CTL1: SS Position */
+#define SPIM_CTL1_SS_Msk (0x1ul << SPIM_CTL1_SS_Pos) /*!< SPIM_T::CTL1: SS Mask */
+
+#define SPIM_CTL1_SSACTPOL_Pos (5) /*!< SPIM_T::CTL1: SSACTPOL Position */
+#define SPIM_CTL1_SSACTPOL_Msk (0x1ul << SPIM_CTL1_SSACTPOL_Pos) /*!< SPIM_T::CTL1: SSACTPOL Mask */
+
+#define SPIM_CTL1_IDLETIME_Pos (8) /*!< SPIM_T::CTL1: IDLETIME Position */
+#define SPIM_CTL1_IDLETIME_Msk (0xful << SPIM_CTL1_IDLETIME_Pos) /*!< SPIM_T::CTL1: IDLETIME Mask */
+
+#define SPIM_CTL1_DIVIDER_Pos (16) /*!< SPIM_T::CTL1: DIVIDER Position */
+#define SPIM_CTL1_DIVIDER_Msk (0xfffful << SPIM_CTL1_DIVIDER_Pos) /*!< SPIM_T::CTL1: DIVIDER Mask */
+
+#define SPIM_RXCLKDLY_DWDELSEL_Pos (0) /*!< SPIM_T::RXCLKDLY: DWDELSEL Position */
+#define SPIM_RXCLKDLY_DWDELSEL_Msk (0xfful << SPIM_RXCLKDLY_DWDELSEL_Pos) /*!< SPIM_T::RXCLKDLY: DWDELSEL Mask */
+
+#define SPIM_RXCLKDLY_RDDLYSEL_Pos (16) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Position */
+#define SPIM_RXCLKDLY_RDDLYSEL_Msk (0x7ul << SPIM_RXCLKDLY_RDDLYSEL_Pos) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Mask */
+
+#define SPIM_RXCLKDLY_RDEDGE_Pos (20) /*!< SPIM_T::RXCLKDLY: RDEDGE Position */
+#define SPIM_RXCLKDLY_RDEDGE_Msk (0x1ul << SPIM_RXCLKDLY_RDEDGE_Pos) /*!< SPIM_T::RXCLKDLY: RDEDGE Mask */
+
+#define SPIM_RX_RXDAT_Pos (0) /*!< SPIM_T::RX[4]: RXDAT Position */
+#define SPIM_RX_RXDAT_Msk (0xfffffffful << SPIM_RX_RXDAT_Pos) /*!< SPIM_T::RX[4]: RXDAT Mask */
+
+#define SPIM_TX_TXDAT_Pos (0) /*!< SPIM_T::TX[4]: TXDAT Position */
+#define SPIM_TX_TXDAT_Msk (0xfffffffful << SPIM_TX_TXDAT_Pos) /*!< SPIM_T::TX[4]: TXDAT Mask */
+
+#define SPIM_SRAMADDR_ADDR_Pos (0) /*!< SPIM_T::SRAMADDR: ADDR Position */
+#define SPIM_SRAMADDR_ADDR_Msk (0xfffffffful << SPIM_SRAMADDR_ADDR_Pos) /*!< SPIM_T::SRAMADDR: ADDR Mask */
+
+#define SPIM_DMACNT_DMACNT_Pos (0) /*!< SPIM_T::DMACNT: DMACNT Position */
+#define SPIM_DMACNT_DMACNT_Msk (0xfffffful << SPIM_DMACNT_DMACNT_Pos) /*!< SPIM_T::DMACNT: DMACNT Mask */
+
+#define SPIM_FADDR_ADDR_Pos (0) /*!< SPIM_T::FADDR: ADDR Position */
+#define SPIM_FADDR_ADDR_Msk (0xfffffffful << SPIM_FADDR_ADDR_Pos) /*!< SPIM_T::FADDR: ADDR Mask */
+
+#define SPIM_KEY1_KEY1_Pos (0) /*!< SPIM_T::KEY1: KEY1 Position */
+#define SPIM_KEY1_KEY1_Msk (0xfffffffful << SPIM_KEY1_KEY1_Pos) /*!< SPIM_T::KEY1: KEY1 Mask */
+
+#define SPIM_KEY2_KEY2_Pos (0) /*!< SPIM_T::KEY2: KEY2 Position */
+#define SPIM_KEY2_KEY2_Msk (0xfffffffful << SPIM_KEY2_KEY2_Pos) /*!< SPIM_T::KEY2: KEY2 Mask */
+
+#define SPIM_DMMCTL_CRMDAT_Pos (8) /*!< SPIM_T::DMMCTL: CRMDAT Position */
+#define SPIM_DMMCTL_CRMDAT_Msk (0xfful << SPIM_DMMCTL_CRMDAT_Pos) /*!< SPIM_T::DMMCTL: CRMDAT Mask */
+
+#define SPIM_DMMCTL_DESELTIM_Pos (16) /*!< SPIM_T::DMMCTL: DESELTIM Position */
+#define SPIM_DMMCTL_DESELTIM_Msk (0x1ful << SPIM_DMMCTL_DESELTIM_Pos) /*!< SPIM_T::DMMCTL: DESELTIM Mask */
+
+#define SPIM_DMMCTL_BWEN_Pos (24) /*!< SPIM_T::DMMCTL: BWEN Position */
+#define SPIM_DMMCTL_BWEN_Msk (0x1ul << SPIM_DMMCTL_BWEN_Pos) /*!< SPIM_T::DMMCTL: BWEN Mask */
+
+#define SPIM_DMMCTL_CREN_Pos (25) /*!< SPIM_T::DMMCTL: CREN Position */
+#define SPIM_DMMCTL_CREN_Msk (0x1ul << SPIM_DMMCTL_CREN_Pos) /*!< SPIM_T::DMMCTL: CREN Mask */
+
+#define SPIM_DMMCTL_UACTSCLK_Pos (26) /*!< SPIM_T::DMMCTL: UACTSCLK Position */
+#define SPIM_DMMCTL_UACTSCLK_Msk (0x1ul << SPIM_DMMCTL_UACTSCLK_Pos) /*!< SPIM_T::DMMCTL: UACTSCLK Mask */
+
+#define SPIM_DMMCTL_ACTSCLKT_Pos (28) /*!< SPIM_T::DMMCTL: ACTSCLKT Position */
+#define SPIM_DMMCTL_ACTSCLKT_Msk (0xful << SPIM_DMMCTL_ACTSCLKT_Pos) /*!< SPIM_T::DMMCTL: ACTSCLKT Mask */
+
+#define SPIM_CTL2_USETEN_Pos (16) /*!< SPIM_T::CTL2: USETEN Position */
+#define SPIM_CTL2_USETEN_Msk (0x1ul << SPIM_CTL2_USETEN_Pos) /*!< SPIM_T::CTL2: USETEN Mask */
+
+#define SPIM_CTL2_DTRMPOFF_Pos (20) /*!< SPIM_T::CTL2: DTRMPOFF Position */
+#define SPIM_CTL2_DTRMPOFF_Msk (0x1ul << SPIM_CTL2_DTRMPOFF_Pos) /*!< SPIM_T::CTL2: DTRMPOFF Mask */
+
+#define SPIM_CTL2_DCNUM_Pos (24) /*!< SPIM_T::CTL2: DCNUM Position */
+#define SPIM_CTL2_DCNUM_Msk (0x1ful << SPIM_CTL2_DCNUM_Pos) /*!< SPIM_T::CTL2: DCNUM Mask */
+
+/**@}*/ /* SPIM_CONST */
+/**@}*/ /* end of SPIM register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __SPIM_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sys_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sys_reg.h
new file mode 100644
index 00000000000..2bf3288d245
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sys_reg.h
@@ -0,0 +1,3662 @@
+/**************************************************************************//**
+ * @file sys_reg.h
+ * @version V1.00
+ * @brief SYS register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SYS_REG_H__
+#define __SYS_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup SYS System Manger Controller(SYS)
+ Memory Mapped Structure for SYS Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var SYS_T::PDID
+ * Offset: 0x00 Part Device Identification Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |PDID |Part Device Identification Number (Read Only)
+ * | | |This register reflects device part number code
+ * | | |Software can read this register to identify which device is used.
+ * @var SYS_T::RSTSTS
+ * Offset: 0x04 System Reset Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PORF |POR Reset Flag
+ * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
+ * | | |0 = No reset from POR or CHIPRST.
+ * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[1] |PINRF |NRESET Pin Reset Flag
+ * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
+ * | | |0 = No reset from nRESET pin.
+ * | | |1 = Pin nRESET had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[2] |WDTRF |WDT Reset Flag
+ * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
+ * | | |0 = No reset from watchdog timer or window watchdog timer.
+ * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
+ * | | |Note1: Write 1 to clear this bit to 0.
+ * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset
+ * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
+ * |[3] |LVRF |LVR Reset Flag
+ * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source.
+ * | | |0 = No reset from LVR.
+ * | | |1 = LVR controller had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |BODRF |BOD Reset Flag
+ * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source.
+ * | | |0 = No reset from BOD.
+ * | | |1 = The BOD had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |SYSRF |System Reset Flag
+ * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
+ * | | |0 = No reset from Cortex-M4.
+ * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[7] |CPURF |CPU Reset Flag
+ * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
+ * | | |0 = No reset from CPU.
+ * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
+ * | | |Note: Write to clear this bit to 0.
+ * |[8] |CPULKRF |CPU Lock-up Reset Flag
+ * | | |0 = No reset from CPU lock-up happened.
+ * | | |1 = The Cortex-M4 lock-up happened and chip is reset.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * | | |Note2: When CPU lock-up happened under ICE is connected, This flag will set to 1 but chip will not reset.
+ * @var SYS_T::IPRST0
+ * Offset: 0x08 Peripheral Reset Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CHIPRST |Chip One-shot Reset (Write Protect)
+ * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
+ * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
+ * | | |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2
+ * | | |0 = Chip normal operation.
+ * | | |1 = Chip one-shot reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |CPURST |Processor Core One-shot Reset (Write Protect)
+ * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
+ * | | |0 = Processor core normal operation.
+ * | | |1 = Processor core one-shot reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |PDMARST |PDMA Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the PDMA
+ * | | |User needs to set this bit to 0 to release from reset state.
+ * | | |0 = PDMA controller normal operation.
+ * | | |1 = PDMA controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |EBIRST |EBI Controller Reset (Write Protect)
+ * | | |Set this bit to 1 will generate a reset signal to the EBI
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = EBI controller normal operation.
+ * | | |1 = EBI controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5] |EMACRST |EMAC Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the EMAC controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = EMAC controller normal operation.
+ * | | |1 = EMAC controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = SDHOST0 controller normal operation.
+ * | | |1 = SDHOST0 controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect)
+ * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = CRC calculation controller normal operation.
+ * | | |1 = CRC calculation controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8] |CCAPRST |CCAP Controller Reset (Write Protect)
+ * | | |Set this bit to 1 will generate a reset signal to the CCAP controller.
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = CCAP controller normal operation.
+ * | | |1 = CCAP controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10] |HSUSBDRST |HSUSBD Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the HSUSBD controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = HSUSBD controller normal operation.
+ * | | |1 = HSUSBD controller reset.
+ * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = CRYPTO controller normal operation.
+ * | | |1 = CRYPTO controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[14] |SPIMRST |SPIM Controller Reset
+ * | | |Setting this bit to 1 will generate a reset signal to the SPIM controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = SPIM controller normal operation.
+ * | | |1 = SPIM controller reset.
+ * |[16] |USBHRST |USBH Controller Reset (Write Protect)
+ * | | |Set this bit to 1 will generate a reset signal to the USBH controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = USBH controller normal operation.
+ * | | |1 = USBH controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[17] |SDH1RST |SDHOST1 Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the SDHOST1 controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = SDHOST1 controller normal operation.
+ * | | |1 = SDHOST1 controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::IPRST1
+ * Offset: 0x0C Peripheral Reset Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |GPIORST |GPIO Controller Reset
+ * | | |0 = GPIO controller normal operation.
+ * | | |1 = GPIO controller reset.
+ * |[2] |TMR0RST |Timer0 Controller Reset
+ * | | |0 = Timer0 controller normal operation.
+ * | | |1 = Timer0 controller reset.
+ * |[3] |TMR1RST |Timer1 Controller Reset
+ * | | |0 = Timer1 controller normal operation.
+ * | | |1 = Timer1 controller reset.
+ * |[4] |TMR2RST |Timer2 Controller Reset
+ * | | |0 = Timer2 controller normal operation.
+ * | | |1 = Timer2 controller reset.
+ * |[5] |TMR3RST |Timer3 Controller Reset
+ * | | |0 = Timer3 controller normal operation.
+ * | | |1 = Timer3 controller reset.
+ * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset
+ * | | |0 = Analog Comparator 0/1 controller normal operation.
+ * | | |1 = Analog Comparator 0/1 controller reset.
+ * |[8] |I2C0RST |I2C0 Controller Reset
+ * | | |0 = I2C0 controller normal operation.
+ * | | |1 = I2C0 controller reset.
+ * |[9] |I2C1RST |I2C1 Controller Reset
+ * | | |0 = I2C1 controller normal operation.
+ * | | |1 = I2C1 controller reset.
+ * |[10] |I2C2RST |I2C2 Controller Reset
+ * | | |0 = I2C2 controller normal operation.
+ * | | |1 = I2C2 controller reset.
+ * |[12] |QSPI0RST |QSPI0 Controller Reset
+ * | | |0 = QSPI0 controller normal operation.
+ * | | |1 = QSPI0 controller reset.
+ * |[13] |SPI0RST |SPI0 Controller Reset
+ * | | |0 = SPI0 controller normal operation.
+ * | | |1 = SPI0 controller reset.
+ * |[14] |SPI1RST |SPI1 Controller Reset
+ * | | |0 = SPI1 controller normal operation.
+ * | | |1 = SPI1 controller reset.
+ * |[15] |SPI2RST |SPI2 Controller Reset
+ * | | |0 = SPI2 controller normal operation.
+ * | | |1 = SPI2 controller reset.
+ * |[16] |UART0RST |UART0 Controller Reset
+ * | | |0 = UART0 controller normal operation.
+ * | | |1 = UART0 controller reset.
+ * |[17] |UART1RST |UART1 Controller Reset
+ * | | |0 = UART1 controller normal operation.
+ * | | |1 = UART1 controller reset.
+ * |[18] |UART2RST |UART2 Controller Reset
+ * | | |0 = UART2 controller normal operation.
+ * | | |1 = UART2 controller reset.
+ * |[19] |UART3RST |UART3 Controller Reset
+ * | | |0 = UART3 controller normal operation.
+ * | | |1 = UART3 controller reset.
+ * |[20] |UART4RST |UART4 Controller Reset
+ * | | |0 = UART4 controller normal operation.
+ * | | |1 = UART4 controller reset.
+ * |[21] |UART5RST |UART5 Controller Reset
+ * | | |0 = UART5 controller normal operation.
+ * | | |1 = UART5 controller reset.
+ * |[24] |CAN0RST |CAN0 Controller Reset
+ * | | |0 = CAN0 controller normal operation.
+ * | | |1 = CAN0 controller reset.
+ * |[25] |CAN1RST |CAN1 Controller Reset
+ * | | |0 = CAN1 controller normal operation.
+ * | | |1 = CAN1 controller reset.
+ * |[27] |USBDRST |USBD Controller Reset
+ * | | |0 = USBD controller normal operation.
+ * | | |1 = USBD controller reset.
+ * |[28] |EADCRST |EADC Controller Reset
+ * | | |0 = EADC controller normal operation.
+ * | | |1 = EADC controller reset.
+ * |[29] |I2S0RST |I2S0 Controller Reset
+ * | | |0 = I2S0 controller normal operation.
+ * | | |1 = I2S0 controller reset.
+ * @var SYS_T::IPRST2
+ * Offset: 0x10 Peripheral Reset Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SC0RST |SC0 Controller Reset
+ * | | |0 = SC0 controller normal operation.
+ * | | |1 = SC0 controller reset.
+ * |[1] |SC1RST |SC1 Controller Reset
+ * | | |0 = SC1 controller normal operation.
+ * | | |1 = SC1 controller reset.
+ * |[2] |SC2RST |SC2 Controller Reset
+ * | | |0 = SC2 controller normal operation.
+ * | | |1 = SC2 controller reset.
+ * |[6] |SPI3RST |SPI3 Controller Reset
+ * | | |0 = SPI3 controller normal operation.
+ * | | |1 = SPI3 controller reset.
+ * |[8] |USCI0RST |USCI0 Controller Reset
+ * | | |0 = USCI0 controller normal operation.
+ * | | |1 = USCI0 controller reset.
+ * |[9] |USCI1RST |USCI1 Controller Reset
+ * | | |0 = USCI1 controller normal operation.
+ * | | |1 = USCI1 controller reset.
+ * |[12] |DACRST |DAC Controller Reset
+ * | | |0 = DAC controller normal operation.
+ * | | |1 = DAC controller reset.
+ * |[16] |EPWM0RST |EPWM0 Controller Reset
+ * | | |0 = EPWM0 controller normal operation.
+ * | | |1 = EPWM0 controller reset.
+ * |[17] |EPWM1RST |EPWM1 Controller Reset
+ * | | |0 = EPWM1 controller normal operation.
+ * | | |1 = EPWM1 controller reset.
+ * |[18] |BPWM0RST |BPWM0 Controller Reset
+ * | | |0 = BPWM0 controller normal operation.
+ * | | |1 = BPWM0 controller reset.
+ * |[19] |BPWM1RST |BPWM1 Controller Reset
+ * | | |0 = BPWM1 controller normal operation.
+ * | | |1 = BPWM1 controller reset.
+ * |[22] |QEI0RST |QEI0 Controller Reset
+ * | | |0 = QEI0 controller normal operation.
+ * | | |1 = QEI0 controller reset.
+ * |[23] |QEI1RST |QEI1 Controller Reset
+ * | | |0 = QEI1 controller normal operation.
+ * | | |1 = QEI1 controller reset.
+ * |[26] |ECAP0RST |ECAP0 Controller Reset
+ * | | |0 = ECAP0 controller normal operation.
+ * | | |1 = ECAP0 controller reset.
+ * |[27] |ECAP1RST |ECAP1 Controller Reset
+ * | | |0 = ECAP1 controller normal operation.
+ * | | |1 = ECAP1 controller reset.
+ * |[28] |CAN2RST |CAN2 Controller Reset
+ * | | |0 = CAN2 controller normal operation.
+ * | | |1 = CAN2 controller reset.
+ * |[30] |OPARST |OP Amplifier (OPA) Controller Reset
+ * | | |0 = OPA controller normal operation.
+ * | | |1 = OPA controller reset.
+ * @var SYS_T::BODCTL
+ * Offset: 0x18 Brown-Out Detector Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect)
+ * | | |The default value is set by flash controller user configuration register CBODEN(CONFIG0 [19]).
+ * | | |0 = Brown-out Detector function Disabled.
+ * | | |1 = Brown-out Detector function Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect)
+ * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
+ * | | |0 = Brown-out INTERRUPT function Enabled.
+ * | | |1 = Brown-out RESET function Enabled.
+ * | | |Note1:
+ * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
+ * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high
+ * | | |BOD interrupt will keep till to the BODEN set to 0
+ * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |BODIF |Brown-out Detector Interrupt Flag
+ * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
+ * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect)
+ * | | |0 = BOD operate in normal mode (default).
+ * | | |1 = BOD Low Power mode Enabled.
+ * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |BODOUT |Brown-out Detector Output Status
+ * | | |0 = Brown-out Detector output status is 0.
+ * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.
+ * | | |1 = Brown-out Detector output status is 1.
+ * | | |It means the detected voltage is lower than BODVL setting
+ * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
+ * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect)
+ * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting
+ * | | |LVR function is enabled by default.
+ * | | |0 = Low Voltage Reset function Disabled.
+ * | | |1 = Low Voltage Reset function Enabled.
+ * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect)
+ * | | |000 = BOD output is sampled by RC10K clock.
+ * | | |001 = 4 system clock (HCLK).
+ * | | |010 = 8 system clock (HCLK).
+ * | | |011 = 16 system clock (HCLK).
+ * | | |100 = 32 system clock (HCLK).
+ * | | |101 = 64 system clock (HCLK).
+ * | | |110 = 128 system clock (HCLK).
+ * | | |111 = 256 system clock (HCLK).
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+ * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect)
+ * | | |000 = Without de-glitch function.
+ * | | |001 = 4 system clock (HCLK).
+ * | | |010 = 8 system clock (HCLK).
+ * | | |011 = 16 system clock (HCLK).
+ * | | |100 = 32 system clock (HCLK).
+ * | | |101 = 64 system clock (HCLK).
+ * | | |110 = 128 system clock (HCLK).
+ * | | |111 = 256 system clock (HCLK).
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+ * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect)
+ * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]).
+ * | | |000 = Brown-Out Detector threshold voltage is 1.6V.
+ * | | |001 = Brown-Out Detector threshold voltage is 1.8V.
+ * | | |010 = Brown-Out Detector threshold voltage is 2.0V.
+ * | | |011 = Brown-Out Detector threshold voltage is 2.2V.
+ * | | |100 = Brown-Out Detector threshold voltage is 2.4V.
+ * | | |101 = Brown-Out Detector threshold voltage is 2.6V.
+ * | | |110 = Brown-Out Detector threshold voltage is 2.8V.
+ * | | |111 = Brown-Out Detector threshold voltage is 3.0V.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::IVSCTL
+ * Offset: 0x1C Internal Voltage Source Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |VTEMPEN |Temperature Sensor Enable Bit
+ * | | |This bit is used to enable/disable temperature sensor function.
+ * | | |0 = Temperature sensor function Disabled (default).
+ * | | |1 = Temperature sensor function Enabled.
+ * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9.
+ * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit
+ * | | |This bit is used to enable/disable VBAT unity gain buffer function.
+ * | | |0 = VBAT unity gain buffer function Disabled (default).
+ * | | |1 = VBAT unity gain buffer function Enabled.
+ * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
+ * @var SYS_T::PORCTL
+ * Offset: 0x24 Power-On-Reset Controller Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect)
+ * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again
+ * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
+ * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
+ * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::VREFCTL
+ * Offset: 0x28 VREF Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |VREFCTL |VREF Control Bits (Write Protect)
+ * | | |00000 = VREF is from external pin.
+ * | | |00011 = VREF is internal 1.6V.
+ * | | |00111 = VREF is internal 2.0V.
+ * | | |01011 = VREF is internal 2.5V.
+ * | | |01111 = VREF is internal 3.0V.
+ * | | |Others = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7:6] |PRELOAD_SEL|Pre-load Timing Selection.
+ * | | |00 = pre-load time is 60us for 0.1uF Capacitor.
+ * | | |01 = pre-load time is 310us for 1uF Capacitor.
+ * | | |10 = pre-load time is 1270us for 4.7uF Capacitor.
+ * | | |11 = pre-load time is 2650us for 10uF Capacitor.
+ * @var SYS_T::USBPHY
+ * Offset: 0x2C USB PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |USBROLE |USB Role Option (Write Protect)
+ * | | |These two bits are used to select the role of USB.
+ * | | |00 = Standard USB Device mode.
+ * | | |01 = Standard USB Host mode.
+ * | | |10 = ID dependent mode.
+ * | | |11 = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable
+ * |[8] |USBEN |USB PHY Enable (Write Protect)
+ * | | |This bit is used to enable/disable USB PHY.
+ * | | |0 = USB PHY Disabled.
+ * | | |1 = USB PHY Enabled.
+ * |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect)
+ * | | |These two bits are used to select the role of HSUSB
+ * | | |00 = Standard HSUSB Device mode.
+ * | | |01 = Standard HSUSB Host mode.
+ * | | |10 = ID dependent mode.
+ * | | |11 = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[24] |HSUSBEN |HSUSB PHY Enable (Write Protect)
+ * | | |This bit is used to enable/disable HSUSB PHY.
+ * | | |0 = HSUSB PHY Disabled.
+ * | | |1 = HSUSB PHY Enabled.
+ * |[25] |HSUSBACT |HSUSB PHY Active Control
+ * | | |This bit is used to control HSUSB PHY at reset state or active state.
+ * | | |0 = HSUSB PHY at reset state.
+ * | | |1 = HSUSB PHY at active state.
+ * | | |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode.
+ * @var SYS_T::GPA_MFPL
+ * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection
+ * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection
+ * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection
+ * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection
+ * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection
+ * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection
+ * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection
+ * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection
+ * @var SYS_T::GPA_MFPH
+ * Offset: 0x34 GPIOA High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection
+ * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection
+ * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection
+ * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection
+ * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection
+ * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection
+ * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection
+ * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection
+ * @var SYS_T::GPB_MFPL
+ * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection
+ * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection
+ * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection
+ * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection
+ * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection
+ * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection
+ * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection
+ * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection
+ * @var SYS_T::GPB_MFPH
+ * Offset: 0x3C GPIOB High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection
+ * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection
+ * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection
+ * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection
+ * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection
+ * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection
+ * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection
+ * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection
+ * @var SYS_T::GPC_MFPL
+ * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection
+ * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection
+ * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection
+ * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection
+ * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection
+ * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection
+ * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection
+ * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection
+ * @var SYS_T::GPC_MFPH
+ * Offset: 0x44 GPIOC High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection
+ * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection
+ * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection
+ * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection
+ * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection
+ * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection
+ * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection
+ * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection
+ * @var SYS_T::GPD_MFPL
+ * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection
+ * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection
+ * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection
+ * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection
+ * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection
+ * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection
+ * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection
+ * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection
+ * @var SYS_T::GPD_MFPH
+ * Offset: 0x4C GPIOD High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection
+ * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection
+ * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection
+ * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection
+ * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection
+ * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection
+ * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection
+ * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection
+ * @var SYS_T::GPE_MFPL
+ * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection
+ * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection
+ * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection
+ * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection
+ * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection
+ * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection
+ * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection
+ * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection
+ * @var SYS_T::GPE_MFPH
+ * Offset: 0x54 GPIOE High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection
+ * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection
+ * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection
+ * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection
+ * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection
+ * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection
+ * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection
+ * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection
+ * @var SYS_T::GPF_MFPL
+ * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection
+ * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection
+ * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection
+ * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection
+ * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection
+ * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection
+ * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection
+ * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection
+ * @var SYS_T::GPF_MFPH
+ * Offset: 0x5C GPIOF High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection
+ * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection
+ * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection
+ * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection
+ * |[19:16] |PF12MFP |PF.12 Multi-function Pin Selection
+ * |[23:20] |PF13MFP |PF.13 Multi-function Pin Selection
+ * |[27:24] |PF14MFP |PF.14 Multi-function Pin Selection
+ * |[31:28] |PF15MFP |PF.15 Multi-function Pin Selection
+ * @var SYS_T::GPG_MFPL
+ * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PG0MFP |PG.0 Multi-function Pin Selection
+ * |[7:4] |PG1MFP |PG.1 Multi-function Pin Selection
+ * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection
+ * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection
+ * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection
+ * |[23:20] |PG5MFP |PG.5 Multi-function Pin Selection
+ * |[27:24] |PG6MFP |PG.6 Multi-function Pin Selection
+ * |[31:28] |PG7MFP |PG.7 Multi-function Pin Selection
+ * @var SYS_T::GPG_MFPH
+ * Offset: 0x64 GPIOG High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PG8MFP |PG.8 Multi-function Pin Selection
+ * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection
+ * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection
+ * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection
+ * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection
+ * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection
+ * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection
+ * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection
+ * @var SYS_T::GPH_MFPL
+ * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PH0MFP |PH.0 Multi-function Pin Selection
+ * |[7:4] |PH1MFP |PH.1 Multi-function Pin Selection
+ * |[11:8] |PH2MFP |PH.2 Multi-function Pin Selection
+ * |[15:12] |PH3MFP |PH.3 Multi-function Pin Selection
+ * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection
+ * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection
+ * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection
+ * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection
+ * @var SYS_T::GPH_MFPH
+ * Offset: 0x6C GPIOH High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection
+ * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection
+ * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection
+ * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection
+ * |[19:16] |PH12MFP |PH.12 Multi-function Pin Selection
+ * |[23:20] |PH13MFP |PH.13 Multi-function Pin Selection
+ * |[27:24] |PH14MFP |PH.14 Multi-function Pin Selection
+ * |[31:28] |PH15MFP |PH.15 Multi-function Pin Selection
+ * @var SYS_T::GPA_MFOS
+ * Offset: 0x80 GPIOA Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPB_MFOS
+ * Offset: 0x84 GPIOB Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPC_MFOS
+ * Offset: 0x88 GPIOC Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPD_MFOS
+ * Offset: 0x8C GPIOD Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPE_MFOS
+ * Offset: 0x90 GPIOE Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPF_MFOS
+ * Offset: 0x94 GPIOF Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPG_MFOS
+ * Offset: 0x98 GPIOG Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPH_MFOS
+ * Offset: 0x9C GPIOH Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::SRAM_INTCTL
+ * Offset: 0xC0 System SRAM Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit
+ * | | |0 = SRAM parity check error interrupt Disabled.
+ * | | |1 = SRAM parity check error interrupt Enabled.
+ * @var SYS_T::SRAM_STATUS
+ * Offset: 0xC4 System SRAM Parity Error Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PERRIF |SRAM Parity Check Error Flag
+ * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0.
+ * | | |0 = No System SRAM parity error.
+ * | | |1 = System SRAM parity error occur.
+ * @var SYS_T::SRAM_ERRADDR
+ * Offset: 0xC8 System SRAM Parity Check Error Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ERRADDR |System SRAM Parity Error Address
+ * | | |This register shows system SRAM parity error byte address.
+ * @var SYS_T::SRAM_BISTCTL
+ * Offset: 0xD0 System SRAM BIST Test Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SRBIST0 |SRAM Bank0 BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for SRAM bank0.
+ * | | |0 = system SRAM bank0 BIST Disabled.
+ * | | |1 = system SRAM bank0 BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |SRBIST1 |SRAM Bank1 BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for SRAM bank1.
+ * | | |0 = system SRAM bank1 BIST Disabled.
+ * | | |1 = system SRAM bank1 BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |CRBIST |CACHE BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for CACHE RAM
+ * | | |0 = system CACHE BIST Disabled.
+ * | | |1 = system CACHE BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |CANBIST |CAN BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for CAN RAM
+ * | | |0 = system CAN BIST Disabled.
+ * | | |1 = system CAN BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |USBBIST |USB BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for USB RAM
+ * | | |0 = system USB BIST Disabled.
+ * | | |1 = system USB BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5] |SPIMBIST |SPIM BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for SPIM RAM
+ * | | |0 = system SPIM BIST Disabled.
+ * | | |1 = system SPIM BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |EMCBIST |EMC BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for EMC RAM
+ * | | |0 = system EMC BIST Disabled.
+ * | | |1 = system EMC BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |PDMABIST |PDMA BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for PDMA RAM
+ * | | |0 = system PDMA BIST Disabled.
+ * | | |1 = system PDMA BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8] |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for HSUSBD RAM
+ * | | |0 = system HSUSBD BIST Disabled.
+ * | | |1 = system HSUSBD BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[9] |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for HSUSBH RAM
+ * | | |0 = system HSUSBH BIST Disabled.
+ * | | |1 = system HSUSBH BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[16] |SRB0S0 |SRAM Bank0 Section 0 BIST Select (Write Protect)
+ * | | |This bit define if the first 16KB section of SRAM bank0 is selected or not when doing bist test.
+ * | | |0 = SRAM bank0 section 0 is deselected when doing bist test.
+ * | | |1 = SRAM bank0 section 0 is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test.
+ * |[17] |SRB0S1 |SRAM Bank0 Section 1 BIST Select (Write Protect)
+ * | | |This bit define if the second 16KB section of SRAM bank0 is selected or not when doing bist test.
+ * | | |0 = SRAM bank0 section 1 is deselected when doing bist test.
+ * | | |1 = SRAM bank0 section 1 is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test.
+ * |[18] |SRB1S0 |SRAM Bank1 Section 0 BIST Select (Write Protect)
+ * | | |This bit define if the first 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 first 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 first 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * |[19] |SRB1S1 |SRAM Bank1 Section 1 BIST Select (Write Protect)
+ * | | |This bit define if the second 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 second 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 second 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * |[20] |SRB1S2 |SRAM Bank1 Section 0 BIST Select (Write Protect)
+ * | | |This bit define if the third 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 third 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 third 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * |[21] |SRB1S3 |SRAM Bank1 Section 1 BIST Select (Write Protect)
+ * | | |This bit define if the fourth 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 fourth 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 fourth 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * |[22] |SRB1S4 |SRAM Bank1 Section 0 BIST Select (Write Protect)
+ * | | |This bit define if the fifth 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 fifth 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 fifth 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * |[23] |SRB1S5 |SRAM Bank1 Section 1 BIST Select (Write Protect)
+ * | | |This bit define if the sixth 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 sixth 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 sixth 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * @var SYS_T::SRAM_BISTSTS
+ * Offset: 0xD4 System SRAM BIST Test Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag
+ * | | |0 = 1st system SRAM BIST test pass.
+ * | | |1 = 1st system SRAM BIST test fail.
+ * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag
+ * | | |0 = 2nd system SRAM BIST test pass.
+ * | | |1 = 2nd system SRAM BIST test fail.
+ * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag
+ * | | |0 = System CACHE RAM BIST test pass.
+ * | | |1 = System CACHE RAM BIST test fail.
+ * |[3] |CANBEF |CAN SRAM BIST Fail Flag
+ * | | |0 = CAN SRAM BIST test pass.
+ * | | |1 = CAN SRAM BIST test fail.
+ * |[4] |USBBEF |USB SRAM BIST Fail Flag
+ * | | |0 = USB SRAM BIST test pass.
+ * | | |1 = USB SRAM BIST test fail.
+ * |[16] |SRBEND0 |1st SRAM BIST Test Finish
+ * | | |0 = 1st system SRAM BIST active.
+ * | | |1 =1st system SRAM BIST finish.
+ * |[17] |SRBEND1 |2nd SRAM BIST Test Finish
+ * | | |0 = 2nd system SRAM BIST is active.
+ * | | |1 = 2nd system SRAM BIST finish.
+ * |[18] |CRBEND |CACHE SRAM BIST Test Finish
+ * | | |0 = System CACHE RAM BIST is active.
+ * | | |1 = System CACHE RAM BIST test finish.
+ * |[19] |CANBEND |CAN SRAM BIST Test Finish
+ * | | |0 = CAN SRAM BIST is active.
+ * | | |1 = CAN SRAM BIST test finish.
+ * |[20] |USBBEND |USB SRAM BIST Test Finish
+ * | | |0 = USB SRAM BIST is active.
+ * | | |1 = USB SRAM BIST test finish.
+ * @var SYS_T::HIRCTCTL
+ * Offset: 0xE4 HIRC48M Trim Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |FREQSEL |Trim Frequency Selection
+ * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.
+ * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
+ * | | |00 = Disable HIRC auto trim function.
+ * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz.
+ * | | |10 = Reserved..
+ * | | |11 = Reserved.
+ * |[5:4] |LOOPSEL |Trim Calculation Loop Selection
+ * | | |This field defines that trim value calculation is based on how many reference clocks.
+ * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock.
+ * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock.
+ * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock.
+ * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock.
+ * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
+ * |[7:6] |RETRYCNT |Trim Value Update Limitation Count
+ * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
+ * | | |Once the HIRC locked, the internal trim value update counter will be reset.
+ * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
+ * | | |00 = Trim retry count limitation is 64 loops.
+ * | | |01 = Trim retry count limitation is 128 loops.
+ * | | |10 = Trim retry count limitation is 256 loops.
+ * | | |11 = Trim retry count limitation is 512 loops.
+ * |[8] |CESTOPEN |Clock Error Stop Enable Bit
+ * | | |0 = The trim operation is keep going if clock is inaccuracy.
+ * | | |1 = The trim operation is stopped if clock is inaccuracy.
+ * |[9] |BOUNDEN |Boundary Enable Bit
+ * | | |0 = Boundary function is disable.
+ * | | |1 = Boundary function is enable.
+ * |[10] |REFCKSEL |Reference Clock Selection
+ * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator.
+ * | | |1 = HIRC trim reference from internal USB synchronous mode.
+ * | | |Note: HIRC trim reference clock is 20Khz in test mode.
+ * |[20:16 |BOUNDARY |Boundary Selection
+ * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved.
+ * | | |Note1: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable.
+ * @var SYS_T::HIRCTIEN
+ * Offset: 0xE8 HIRC48M Trim Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit
+ * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTCTL[1:0]).
+ * | | |If this bit is high and TFAILIF(SYS_HIRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+ * | | |0 = Disable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU.
+ * | | |1 = Enable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU.
+ * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit
+ * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
+ * | | |If this bit is set to1, and CLKERRIF(SYS_HIRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+ * | | |0 = Disable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU.
+ * | | |1 = Enable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU.
+ * @var SYS_T::HIRCTISTS
+ * Offset: 0xEC HIRC48M Trim Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FREQLOCK |HIRC Frequency Lock Status
+ * | | |This bit indicates the HIRC frequency is locked.
+ * | | |This is a status bit and doesn't trigger any interrupt
+ * | | |Write 1 to clear this to 0
+ * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.
+ * | | |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet.
+ * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz.
+ * |[1] |TFAILIF |Trim Failure Interrupt Status
+ * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked
+ * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
+ * | | |If this bit is set and TFAILIEN(SYS_HIRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached
+ * | | |Write 1 to clear this to 0.
+ * | | |0 = Trim value update limitation count does not reach.
+ * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked.
+ * |[2] |CLKERRIF |Clock Error Interrupt Status
+ * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy.
+ * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTCTL[8]) is set to 1.
+ * | | |If this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+ * | | |Write 1 to clear this to 0.
+ * | | |0 = Clock frequency is accurate.
+ * | | |1 = Clock frequency is inaccurate.
+ * |[3] |OVBDIF |Over Boundary Status
+ * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set.
+ * | | |Note1: Write 1 to clear this flag.
+ * | | |Note2: This function is only supported in M48xGC/M48xG8.
+ * | | |0 = Over boundary condition did not occur.
+ * | | |1 = Over boundary condition occurred.
+ * @var SYS_T::IRCTCTL
+ * Offset: 0xF0 HIRC Trim Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |FREQSEL |Trim Frequency Selection
+ * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.
+ * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
+ * | | |00 = Disable HIRC auto trim function.
+ * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz.
+ * | | |10 = Reserved..
+ * | | |11 = Reserved.
+ * |[5:4] |LOOPSEL |Trim Calculation Loop Selection
+ * | | |This field defines that trim value calculation is based on how many reference clocks.
+ * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock.
+ * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock.
+ * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock.
+ * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock.
+ * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
+ * |[7:6] |RETRYCNT |Trim Value Update Limitation Count
+ * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
+ * | | |Once the HIRC locked, the internal trim value update counter will be reset.
+ * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
+ * | | |00 = Trim retry count limitation is 64 loops.
+ * | | |01 = Trim retry count limitation is 128 loops.
+ * | | |10 = Trim retry count limitation is 256 loops.
+ * | | |11 = Trim retry count limitation is 512 loops.
+ * |[8] |CESTOPEN |Clock Error Stop Enable Bit
+ * | | |0 = The trim operation is keep going if clock is inaccuracy.
+ * | | |1 = The trim operation is stopped if clock is inaccuracy.
+ * |[10] |REFCKSEL |Reference Clock Selection
+ * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator.
+ * | | |1 = HIRC trim reference from internal USB synchronous mode.
+ * | | |Note: HIRC trim reference clock is 20Khz in test mode.
+ * @var SYS_T::IRCTIEN
+ * Offset: 0xF4 HIRC Trim Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit
+ * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
+ * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+ * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
+ * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
+ * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit
+ * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
+ * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+ * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
+ * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
+ * @var SYS_T::IRCTISTS
+ * Offset: 0xF8 HIRC Trim Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FREQLOCK |HIRC Frequency Lock Status
+ * | | |This bit indicates the HIRC frequency is locked.
+ * | | |This is a status bit and doesn't trigger any interrupt
+ * | | |Write 1 to clear this to 0
+ * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.
+ * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet.
+ * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz.
+ * |[1] |TFAILIF |Trim Failure Interrupt Status
+ * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked
+ * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
+ * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached
+ * | | |Write 1 to clear this to 0.
+ * | | |0 = Trim value update limitation count does not reach.
+ * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked.
+ * |[2] |CLKERRIF |Clock Error Interrupt Status
+ * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy.
+ * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
+ * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+ * | | |Write 1 to clear this to 0.
+ * | | |0 = Clock frequency is accurate.
+ * | | |1 = Clock frequency is inaccurate.
+ * @var SYS_T::REGLCTL
+ * Offset: 0x100 Register Lock Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |REGLCTL |Register Lock Control Code
+ * | | |Some registers have write-protection function
+ * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
+ * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
+ * | | |Register Lock Control Code
+ * | | |0 = Write-protection Enabled for writing protected registers
+ * | | |Any write to the protected register is ignored.
+ * | | |1 = Write-protection Disabled for writing protected registers.
+ * @var SYS_T::PORDISAN
+ * Offset: 0x1EC Analog POR Disable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |POROFFAN |Power-on Reset Enable Bit (Write Protect)
+ * | | |After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.
+ * | | |The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including:
+ * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::PLCTL
+ * Offset: 0x1F8 Power Level Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |PLSEL |Power Level Select(Write Protect)
+ * | | |00 = Power level is PL0.
+ * | | |01 = Power level is PL1.
+ * | | |Others = Reserved.
+ * |[21:16] |LVSSTEP |LDO Voltage Scaling Step(Write Protect)
+ * | | |The LVSSTEP value is LDO voltage rising step.
+ * | | |Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV.
+ * |[31:24] |LVSPRD |LDO Voltage Scaling Period(Write Protect)
+ * | | |The LVSPRD value is the period of each LDO voltage rising step.
+ * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us.
+ * @var SYS_T::PLSTS
+ * Offset: 0x1FC Power Level Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only)
+ * | | |This bit is set by hardware when core voltage is changing
+ * | | |After core voltage change is completed, this bit will be cleared automatically by hardware.
+ * | | |0 = Core voltage change is completed.
+ * | | |1 = Core voltage change is ongoing.
+ * |[9:8] |PLSTATUS |Power Level Status (Read Only)
+ * | | |00 = Power level is PL0.
+ * | | |01 = Power level is PL1.
+ * | | |Others = Reserved.
+ * @var SYS_T::AHBMCTL
+ * Offset: 0x400 AHB Bus Matrix Priority Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect)
+ * | | |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix
+ * | | |0 = Run robin mode.
+ * | | |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ */
+ __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */
+ __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */
+ __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */
+ __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */
+ __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE0[1];
+ /** @endcond */
+ __IO uint32_t BODCTL; /*!< [0x0018] Brown-Out Detector Control Register */
+ __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE1[1];
+ /** @endcond */
+ __IO uint32_t PORCTL; /*!< [0x0024] Power-On-Reset Controller Register */
+ __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */
+ __IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */
+ __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */
+ __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */
+ __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */
+ __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */
+ __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */
+ __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */
+ __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */
+ __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */
+ __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */
+ __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */
+ __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */
+ __IO uint32_t GPF_MFPH; /*!< [0x005c] GPIOF High Byte Multiple Function Control Register */
+ __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */
+ __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */
+ __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */
+ __IO uint32_t GPH_MFPH; /*!< [0x006c] GPIOH High Byte Multiple Function Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE2[4];
+ /** @endcond */
+ __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */
+ __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */
+ __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */
+ __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */
+ __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */
+ __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */
+ __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */
+ __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE3[8];
+ /** @endcond */
+ __IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */
+ __IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */
+ __I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE4[1];
+ /** @endcond */
+ __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */
+ __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE5[3];
+ /** @endcond */
+ __IO uint32_t HIRCTCTL; /*!< [0x00e4] HIRC48M Trim Control Register */
+ __IO uint32_t HIRCTIEN; /*!< [0x00e8] HIRC48M Trim Interrupt Enable Register */
+ __IO uint32_t HIRCTISTS; /*!< [0x00ec] HIRC48M Trim Interrupt Status Register */
+ __IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */
+ __IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */
+ __IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE6[1];
+ /** @endcond */
+ __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE7[58];
+ /** @endcond */
+ __IO uint32_t PORDISAN; /*!< [0x01ec] Analog POR Disable Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE8;
+ /** @endcond */
+ __I uint32_t CSERVER; /*!< [0x01f4] Chip Series Version Register */
+ __IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */
+ __I uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE9[128];
+ /** @endcond */
+ __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */
+
+} SYS_T;
+
+/**
+ @addtogroup SYS_CONST SYS Bit Field Definition
+ Constant Definitions for SYS Controller
+@{ */
+
+#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */
+#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */
+
+#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */
+#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */
+
+#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */
+#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */
+
+#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */
+#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */
+
+#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */
+#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */
+
+#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */
+#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */
+
+#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */
+#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */
+
+#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */
+#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */
+
+#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */
+#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */
+
+#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */
+#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */
+
+#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */
+#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */
+
+#define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */
+#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */
+
+#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */
+#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */
+
+#define SYS_IPRST0_EMACRST_Pos (5) /*!< SYS_T::IPRST0: EMACRST Position */
+#define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) /*!< SYS_T::IPRST0: EMACRST Mask */
+
+#define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */
+#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */
+
+#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */
+#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */
+
+#define SYS_IPRST0_CCAPRST_Pos (8) /*!< SYS_T::IPRST0: CCAPRST Position */
+#define SYS_IPRST0_CCAPRST_Msk (0x1ul << SYS_IPRST0_CCAPRST_Pos) /*!< SYS_T::IPRST0: CCAPRST Mask */
+
+#define SYS_IPRST0_HSUSBDRST_Pos (10) /*!< SYS_T::IPRST0: HSUSBDRST Position */
+#define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */
+
+#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */
+#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */
+
+#define SYS_IPRST0_SPIMRST_Pos (14) /*!< SYS_T::IPRST0: SPIMRST Position */
+#define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) /*!< SYS_T::IPRST0: SPIMRST Mask */
+
+#define SYS_IPRST0_USBHRST_Pos (16) /*!< SYS_T::IPRST0: USBHRST Position */
+#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */
+
+#define SYS_IPRST0_SDH1RST_Pos (17) /*!< SYS_T::IPRST0: SDH1RST Position */
+#define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */
+
+#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */
+#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */
+
+#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */
+#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */
+
+#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */
+#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */
+
+#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */
+#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */
+
+#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */
+#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */
+
+#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */
+#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */
+
+#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */
+#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */
+
+#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */
+#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */
+
+#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */
+#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */
+
+#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */
+#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */
+
+#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */
+#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */
+
+#define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */
+#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */
+
+#define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */
+#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */
+
+#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */
+#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */
+
+#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */
+#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */
+
+#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */
+#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */
+
+#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */
+#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */
+
+#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */
+#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */
+
+#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */
+#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */
+
+#define SYS_IPRST1_UART6RST_Pos (22) /*!< SYS_T::IPRST1: UART6RST Position */
+#define SYS_IPRST1_UART6RST_Msk (0x1ul << SYS_IPRST1_UART6RST_Pos) /*!< SYS_T::IPRST1: UART6RST Mask */
+
+#define SYS_IPRST1_UART7RST_Pos (23) /*!< SYS_T::IPRST1: UART7RST Position */
+#define SYS_IPRST1_UART7RST_Msk (0x1ul << SYS_IPRST1_UART7RST_Pos) /*!< SYS_T::IPRST1: UART7RST Mask */
+
+#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */
+#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */
+
+#define SYS_IPRST1_CAN1RST_Pos (25) /*!< SYS_T::IPRST1: CAN1RST Position */
+#define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /*!< SYS_T::IPRST1: CAN1RST Mask */
+
+#define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */
+#define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */
+
+#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */
+#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */
+
+#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */
+#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */
+
+#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */
+#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */
+
+#define SYS_IPRST1_HSOTGRST_Pos (30) /*!< SYS_T::IPRST1: HSOTGRST Position */
+#define SYS_IPRST1_HSOTGRST_Msk (0x1ul << SYS_IPRST1_HSOTGRST_Pos) /*!< SYS_T::IPRST1: HSOTGRST Mask */
+
+#define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */
+#define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */
+
+#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */
+#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */
+
+#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */
+#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */
+
+#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */
+#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */
+
+#define SYS_IPRST2_QSPI1RST_Pos (4) /*!< SYS_T::IPRST2: QSPI1RST Position */
+#define SYS_IPRST2_QSPI1RST_Msk (0x1ul << SYS_IPRST2_QSPI1RST_Pos) /*!< SYS_T::IPRST2: QSPI1RST Mask */
+
+#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */
+#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */
+
+#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */
+#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */
+
+#define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */
+#define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */
+
+#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */
+#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */
+
+#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */
+#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */
+
+#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */
+#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */
+
+#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */
+#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */
+
+#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */
+#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */
+
+#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */
+#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */
+
+#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */
+#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */
+
+#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */
+#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */
+
+#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */
+#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */
+
+#define SYS_IPRST2_CAN2RST_Pos (28) /*!< SYS_T::IPRST2: CAN2RST Position */
+#define SYS_IPRST2_CAN2RST_Msk (0x1ul << SYS_IPRST2_CAN2RST_Pos) /*!< SYS_T::IPRST2: CAN2RST Mask */
+
+#define SYS_IPRST2_OPARST_Pos (30) /*!< SYS_T::IPRST2: OPARST Position */
+#define SYS_IPRST2_OPARST_Msk (0x1ul << SYS_IPRST2_OPARST_Pos) /*!< SYS_T::IPRST2: OPARST Mask */
+
+#define SYS_IPRST2_EADC1RST_Pos (31) /*!< SYS_T::IPRST2: EADC1RST Position */
+#define SYS_IPRST2_EADC1RST_Msk (0x1ul << SYS_IPRST2_EADC1RST_Pos) /*!< SYS_T::IPRST2: EADC1RST Mask */
+
+#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */
+#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */
+
+#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */
+#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */
+
+#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */
+#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */
+
+#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */
+#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */
+
+#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */
+#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */
+
+#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */
+#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */
+
+#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */
+#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */
+
+#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */
+#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */
+
+#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */
+#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */
+
+#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */
+#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */
+
+#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */
+#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */
+
+#define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */
+#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */
+
+#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */
+#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */
+
+#define SYS_VREFCTL_PRELOAD_SEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOAD_SEL Position */
+#define SYS_VREFCTL_PRELOAD_SEL_Msk (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos) /*!< SYS_T::VREFCTL: PRELOAD_SEL Mask */
+
+#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */
+#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */
+
+#define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */
+#define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */
+
+#define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */
+#define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */
+
+#define SYS_USBPHY_HSUSBROLE_Pos (16) /*!< SYS_T::USBPHY: HSUSBROLE Position */
+#define SYS_USBPHY_HSUSBROLE_Msk (0x3ul << SYS_USBPHY_HSUSBROLE_Pos) /*!< SYS_T::USBPHY: HSUSBROLE Mask */
+
+#define SYS_USBPHY_HSUSBEN_Pos (24) /*!< SYS_T::USBPHY: HSUSBEN Position */
+#define SYS_USBPHY_HSUSBEN_Msk (0x1ul << SYS_USBPHY_HSUSBEN_Pos) /*!< SYS_T::USBPHY: HSUSBEN Mask */
+
+#define SYS_USBPHY_HSUSBACT_Pos (25) /*!< SYS_T::USBPHY: HSUSBACT Position */
+#define SYS_USBPHY_HSUSBACT_Msk (0x1ul << SYS_USBPHY_HSUSBACT_Pos) /*!< SYS_T::USBPHY: HSUSBACT Mask */
+
+#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */
+#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */
+
+#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */
+#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */
+
+#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */
+#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */
+
+#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */
+#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */
+
+#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */
+#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */
+
+#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */
+#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */
+
+#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */
+#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */
+
+#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */
+#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */
+
+#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */
+#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */
+
+#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */
+#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */
+
+#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */
+#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */
+
+#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */
+#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */
+
+#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */
+#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */
+
+#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */
+#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */
+
+#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */
+#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */
+
+#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */
+#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */
+
+#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */
+#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */
+
+#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */
+#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */
+
+#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */
+#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */
+
+#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */
+#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */
+
+#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */
+#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */
+
+#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */
+#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */
+
+#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */
+#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */
+
+#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */
+#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */
+
+#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */
+#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */
+
+#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */
+#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */
+
+#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */
+#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */
+
+#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */
+#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */
+
+#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */
+#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */
+
+#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */
+#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */
+
+#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */
+#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */
+
+#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */
+#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */
+
+#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */
+#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */
+
+#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */
+#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */
+
+#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */
+#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */
+
+#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */
+#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */
+
+#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */
+#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */
+
+#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */
+#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */
+
+#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */
+#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */
+
+#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */
+#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */
+
+#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */
+#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */
+
+#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */
+#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */
+
+#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */
+#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */
+
+#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */
+#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */
+
+#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */
+#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */
+
+#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */
+#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */
+
+#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */
+#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */
+
+#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */
+#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */
+
+#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */
+#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */
+
+#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */
+#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */
+
+#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */
+#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */
+
+#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */
+#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */
+
+#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */
+#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */
+
+#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */
+#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */
+
+#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */
+#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */
+
+#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */
+#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */
+
+#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */
+#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */
+
+#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */
+#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */
+
+#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */
+#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */
+
+#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */
+#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */
+
+#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */
+#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */
+
+#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */
+#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */
+
+#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */
+#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */
+
+#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */
+#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */
+
+#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */
+#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */
+
+#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */
+#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */
+
+#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */
+#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */
+
+#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */
+#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */
+
+#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */
+#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */
+
+#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */
+#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */
+
+#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */
+#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */
+
+#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */
+#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */
+
+#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */
+#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */
+
+#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */
+#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */
+
+#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */
+#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */
+
+#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */
+#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */
+
+#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */
+#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */
+
+#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */
+#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */
+
+#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */
+#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */
+
+#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */
+#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */
+
+#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */
+#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */
+
+#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */
+#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */
+
+#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */
+#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */
+
+#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */
+#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */
+
+#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */
+#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */
+
+#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */
+#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */
+
+#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */
+#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */
+
+#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */
+#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */
+
+#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */
+#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */
+
+#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */
+#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */
+
+#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */
+#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */
+
+#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */
+#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */
+
+#define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS_T::GPF_MFPH: PF12MFP Position */
+#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS_T::GPF_MFPH: PF12MFP Mask */
+
+#define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS_T::GPF_MFPH: PF13MFP Position */
+#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS_T::GPF_MFPH: PF13MFP Mask */
+
+#define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS_T::GPF_MFPH: PF14MFP Position */
+#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS_T::GPF_MFPH: PF14MFP Mask */
+
+#define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS_T::GPF_MFPH: PF15MFP Position */
+#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS_T::GPF_MFPH: PF15MFP Mask */
+
+#define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFPL: PG0MFP Position */
+#define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS_T::GPG_MFPL: PG0MFP Mask */
+
+#define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS_T::GPG_MFPL: PG1MFP Position */
+#define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS_T::GPG_MFPL: PG1MFP Mask */
+
+#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */
+#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */
+
+#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */
+#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */
+
+#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */
+#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */
+
+#define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS_T::GPG_MFPL: PG5MFP Position */
+#define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS_T::GPG_MFPL: PG5MFP Mask */
+
+#define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS_T::GPG_MFPL: PG6MFP Position */
+#define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS_T::GPG_MFPL: PG6MFP Mask */
+
+#define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS_T::GPG_MFPL: PG7MFP Position */
+#define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS_T::GPG_MFPL: PG7MFP Mask */
+
+#define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFPH: PG8MFP Position */
+#define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS_T::GPG_MFPH: PG8MFP Mask */
+
+#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */
+#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */
+
+#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */
+#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */
+
+#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */
+#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */
+
+#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */
+#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */
+
+#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */
+#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */
+
+#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */
+#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */
+
+#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */
+#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */
+
+#define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFPL: PH0MFP Position */
+#define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS_T::GPH_MFPL: PH0MFP Mask */
+
+#define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS_T::GPH_MFPL: PH1MFP Position */
+#define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS_T::GPH_MFPL: PH1MFP Mask */
+
+#define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS_T::GPH_MFPL: PH2MFP Position */
+#define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS_T::GPH_MFPL: PH2MFP Mask */
+
+#define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS_T::GPH_MFPL: PH3MFP Position */
+#define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS_T::GPH_MFPL: PH3MFP Mask */
+
+#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */
+#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */
+
+#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */
+#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */
+
+#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */
+#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */
+
+#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */
+#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */
+
+#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */
+#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */
+
+#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */
+#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */
+
+#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */
+#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */
+
+#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */
+#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */
+
+#define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS_T::GPH_MFPH: PH12MFP Position */
+#define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS_T::GPH_MFPH: PH12MFP Mask */
+
+#define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS_T::GPH_MFPH: PH13MFP Position */
+#define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS_T::GPH_MFPH: PH13MFP Mask */
+
+#define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS_T::GPH_MFPH: PH14MFP Position */
+#define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS_T::GPH_MFPH: PH14MFP Mask */
+
+#define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS_T::GPH_MFPH: PH15MFP Position */
+#define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS_T::GPH_MFPH: PH15MFP Mask */
+
+#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */
+#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */
+
+#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */
+#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */
+
+#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */
+#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */
+
+#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */
+#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */
+
+#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */
+#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */
+
+#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */
+#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */
+
+#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */
+#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */
+
+#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */
+#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */
+
+#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */
+#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */
+
+#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */
+#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */
+
+#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */
+#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */
+
+#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */
+#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */
+
+#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */
+#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */
+
+#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */
+#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */
+
+#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */
+#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */
+
+#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */
+#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */
+
+#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */
+#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */
+
+#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */
+#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */
+
+#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */
+#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */
+
+#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */
+#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */
+
+#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */
+#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */
+
+#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */
+#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */
+
+#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */
+#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */
+
+#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */
+#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */
+
+#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */
+#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */
+
+#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */
+#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */
+
+#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */
+#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */
+
+#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */
+#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */
+
+#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */
+#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */
+
+#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */
+#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */
+
+#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */
+#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */
+
+#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */
+#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */
+
+#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */
+#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */
+
+#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */
+#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */
+
+#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */
+#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */
+
+#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */
+#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */
+
+#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */
+#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */
+
+#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */
+#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */
+
+#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */
+#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */
+
+#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */
+#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */
+
+#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */
+#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */
+
+#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */
+#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */
+
+#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */
+#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */
+
+#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */
+#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */
+
+#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */
+#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */
+
+#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */
+#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */
+
+#define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */
+#define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */
+
+#define SYS_GPC_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPC_MFOS: MFOS15 Position */
+#define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) /*!< SYS_T::GPC_MFOS: MFOS15 Mask */
+
+#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */
+#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */
+
+#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */
+#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */
+
+#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */
+#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */
+
+#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */
+#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */
+
+#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */
+#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */
+
+#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */
+#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */
+
+#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */
+#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */
+
+#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */
+#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */
+
+#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */
+#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */
+
+#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */
+#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */
+
+#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */
+#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */
+
+#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */
+#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */
+
+#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */
+#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */
+
+#define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */
+#define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */
+
+#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */
+#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */
+
+#define SYS_GPD_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPD_MFOS: MFOS15 Position */
+#define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) /*!< SYS_T::GPD_MFOS: MFOS15 Mask */
+
+#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */
+#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */
+
+#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */
+#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */
+
+#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */
+#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */
+
+#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */
+#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */
+
+#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */
+#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */
+
+#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */
+#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */
+
+#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */
+#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */
+
+#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */
+#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */
+
+#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */
+#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */
+
+#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */
+#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */
+
+#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */
+#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */
+
+#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */
+#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */
+
+#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */
+#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */
+
+#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */
+#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */
+
+#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */
+#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */
+
+#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */
+#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */
+
+#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */
+#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */
+
+#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */
+#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */
+
+#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */
+#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */
+
+#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */
+#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */
+
+#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */
+#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */
+
+#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */
+#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */
+
+#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */
+#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */
+
+#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */
+#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */
+
+#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */
+#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */
+
+#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */
+#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */
+
+#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */
+#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */
+
+#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */
+#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */
+
+#define SYS_GPF_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPF_MFOS: MFOS12 Position */
+#define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) /*!< SYS_T::GPF_MFOS: MFOS12 Mask */
+
+#define SYS_GPF_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPF_MFOS: MFOS13 Position */
+#define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) /*!< SYS_T::GPF_MFOS: MFOS13 Mask */
+
+#define SYS_GPF_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPF_MFOS: MFOS14 Position */
+#define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) /*!< SYS_T::GPF_MFOS: MFOS14 Mask */
+
+#define SYS_GPF_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPF_MFOS: MFOS15 Position */
+#define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) /*!< SYS_T::GPF_MFOS: MFOS15 Mask */
+
+#define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */
+#define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */
+
+#define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */
+#define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */
+
+#define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */
+#define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */
+
+#define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */
+#define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */
+
+#define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */
+#define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */
+
+#define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */
+#define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */
+
+#define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */
+#define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */
+
+#define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */
+#define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */
+
+#define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */
+#define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */
+
+#define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */
+#define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */
+
+#define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */
+#define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */
+
+#define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */
+#define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */
+
+#define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */
+#define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */
+
+#define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */
+#define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */
+
+#define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */
+#define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */
+
+#define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */
+#define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */
+
+#define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */
+#define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */
+
+#define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */
+#define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */
+
+#define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */
+#define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */
+
+#define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */
+#define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */
+
+#define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */
+#define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */
+
+#define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */
+#define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */
+
+#define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */
+#define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */
+
+#define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */
+#define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */
+
+#define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */
+#define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */
+
+#define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */
+#define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */
+
+#define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */
+#define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */
+
+#define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */
+#define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */
+
+#define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */
+#define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */
+
+#define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */
+#define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */
+
+#define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */
+#define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */
+
+#define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */
+#define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */
+
+#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */
+#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */
+
+#define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */
+#define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */
+
+#define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */
+#define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */
+
+#define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */
+#define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */
+
+#define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */
+#define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */
+
+#define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */
+#define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */
+
+#define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */
+#define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */
+
+#define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */
+#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */
+
+#define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */
+#define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask */
+
+#define SYS_SRAM_BISTCTL_EMCBIST_Pos (6) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Position */
+#define SYS_SRAM_BISTCTL_EMCBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMCBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Mask */
+
+#define SYS_SRAM_BISTCTL_PDMABIST_Pos (7) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Position */
+#define SYS_SRAM_BISTCTL_PDMABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Mask */
+
+#define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos (8) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/
+#define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask */
+
+#define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos (9) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/
+#define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask */
+
+#define SYS_SRAM_BISTCTL_SRB0S0_Pos (16) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Position */
+#define SYS_SRAM_BISTCTL_SRB0S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB0S1_Pos (17) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Position */
+#define SYS_SRAM_BISTCTL_SRB0S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S0_Pos (18) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Position */
+#define SYS_SRAM_BISTCTL_SRB1S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S1_Pos (19) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Position */
+#define SYS_SRAM_BISTCTL_SRB1S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S2_Pos (20) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Position */
+#define SYS_SRAM_BISTCTL_SRB1S2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S2_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S3_Pos (21) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Position */
+#define SYS_SRAM_BISTCTL_SRB1S3_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S3_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S4_Pos (22) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Position */
+#define SYS_SRAM_BISTCTL_SRB1S4_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S4_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S5_Pos (23) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Position */
+#define SYS_SRAM_BISTCTL_SRB1S5_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S5_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Mask */
+
+#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/
+#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */
+
+#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/
+#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */
+
+#define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */
+#define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */
+
+#define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */
+#define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */
+
+#define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */
+#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */
+
+#define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */
+#define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */
+
+#define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */
+#define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */
+
+#define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */
+#define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */
+
+#define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */
+#define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */
+
+#define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */
+#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */
+
+#define SYS_HIRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::HIRCTCTL: FREQSEL Position */
+#define SYS_HIRCTCTL_FREQSEL_Msk (0x3ul << SYS_HIRCTCTL_FREQSEL_Pos) /*!< SYS_T::HIRCTCTL: FREQSEL Mask */
+
+#define SYS_HIRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::HIRCTCTL: LOOPSEL Position */
+#define SYS_HIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_HIRCTCTL_LOOPSEL_Pos) /*!< SYS_T::HIRCTCTL: LOOPSEL Mask */
+
+#define SYS_HIRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::HIRCTCTL: RETRYCNT Position */
+#define SYS_HIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_HIRCTCTL_RETRYCNT_Pos) /*!< SYS_T::HIRCTCTL: RETRYCNT Mask */
+
+#define SYS_HIRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::HIRCTCTL: CESTOPEN Position */
+#define SYS_HIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_HIRCTCTL_CESTOPEN_Pos) /*!< SYS_T::HIRCTCTL: CESTOPEN Mask */
+
+#define SYS_HIRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::HIRCTCTL: BOUNDEN Position */
+#define SYS_HIRCTCTL_BOUNDEN_Msk (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos) /*!< SYS_T::HIRCTCTL: BOUNDEN Mask */
+
+#define SYS_HIRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::HIRCTCTL: REFCKSEL Position */
+#define SYS_HIRCTCTL_REFCKSEL_Msk (0x1ul << SYS_HIRCTCTL_REFCKSEL_Pos) /*!< SYS_T::HIRCTCTL: REFCKSEL Mask */
+
+#define SYS_HIRCTCTL_BOUNDARY_Pos (16) /*!< SYS_T::HIRCTCTL: BOUNDARY Position */
+#define SYS_HIRCTCTL_BOUNDARY_Msk (0x1ful << SYS_HIRCTCTL_BOUNDARY_Pos) /*!< SYS_T::HIRCTCTL: BOUNDARY Mask */
+
+#define SYS_HIRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::HIRCTIEN: TFAILIEN Position */
+#define SYS_HIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_HIRCTIEN_TFAILIEN_Pos) /*!< SYS_T::HIRCTIEN: TFAILIEN Mask */
+
+#define SYS_HIRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::HIRCTIEN: CLKEIEN Position */
+#define SYS_HIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_HIRCTIEN_CLKEIEN_Pos) /*!< SYS_T::HIRCTIEN: CLKEIEN Mask */
+
+#define SYS_HIRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::HIRCTISTS: FREQLOCK Position */
+#define SYS_HIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_HIRCTISTS_FREQLOCK_Pos) /*!< SYS_T::HIRCTISTS: FREQLOCK Mask */
+
+#define SYS_HIRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::HIRCTISTS: TFAILIF Position */
+#define SYS_HIRCTISTS_TFAILIF_Msk (0x1ul << SYS_HIRCTISTS_TFAILIF_Pos) /*!< SYS_T::HIRCTISTS: TFAILIF Mask */
+
+#define SYS_HIRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::HIRCTISTS: CLKERRIF Position */
+#define SYS_HIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_HIRCTISTS_CLKERRIF_Pos) /*!< SYS_T::HIRCTISTS: CLKERRIF Mask */
+
+#define SYS_HIRCTISTS_OVBDIF_Pos (3) /*!< SYS_T::HIRCTISTS: OVBDIF Position */
+#define SYS_HIRCTISTS_OVBDIF_Msk (0x1ul << SYS_HIRCTISTS_OVBDIF_Pos) /*!< SYS_T::HIRCTISTS: OVBDIF Mask */
+
+#define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */
+#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */
+
+#define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */
+#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */
+
+#define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */
+#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */
+
+#define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */
+#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */
+
+#define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */
+#define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */
+
+#define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */
+#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */
+
+#define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */
+#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */
+
+#define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */
+#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */
+
+#define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */
+#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */
+
+#define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */
+#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */
+
+#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */
+#define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */
+
+#define SYS_PORDISAN_POROFFAN_Pos (0) /*!< SYS_T::PORDISAN: POROFFAN Position */
+#define SYS_PORDISAN_POROFFAN_Msk (0xfffful << SYS_PORDISAN_POROFFAN_Pos) /*!< SYS_T::PORDISAN: POROFFAN Mask */
+
+#define SYS_CSERVER_VERSION_Pos (0) /*!< SYS_T::CSERVER: VERSION Position */
+#define SYS_CSERVER_VERSION_Msk (0xfful << SYS_CSERVER_VERSION_Pos) /*!< SYS_T::CSERVER: VERSION Mask */
+
+#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */
+#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */
+
+#define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */
+#define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */
+
+#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */
+#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */
+
+#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */
+#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */
+
+#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */
+#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */
+
+#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */
+#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */
+
+/**@}*/ /* SYS_CONST */
+/**@}*/ /* end of SYS register group */
+
+/**
+ @addtogroup NMI NMI Controller (NMI)
+ Memory Mapped Structure for NMI Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var NMI_T::NMIEN
+ * Offset: 0x00 NMI Source Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BODOUT |BOD NMI Source Enable (Write Protect)
+ * | | |0 = BOD NMI source Disabled.
+ * | | |1 = BOD NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect)
+ * | | |0 = IRC TRIM NMI source Disabled.
+ * | | |1 = IRC TRIM NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |PWRWU_INT |Power-down Mode Wake-up NMI Source Enable (Write Protect)
+ * | | |0 = Power-down mode wake-up NMI source Disabled.
+ * | | |1 = Power-down mode wake-up NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |SRAM_PERR |SRAM Parity Check NMI Source Enable (Write Protect)
+ * | | |0 = SRAM parity check error NMI source Disabled.
+ * | | |1 = SRAM parity check error NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |CLKFAIL |Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect)
+ * | | |0 = Clock fail detected and IRC Auto Trim interrupt NMI source Disabled.
+ * | | |1 = Clock fail detected and IRC Auto Trim interrupt NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect)
+ * | | |0 = RTC NMI source Disabled.
+ * | | |1 = RTC NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect)
+ * | | |0 = Backup register tamper detected NMI source Disabled.
+ * | | |1 = Backup register tamper detected NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PA.6 or PB.5 pin NMI source Disabled.
+ * | | |1 = External interrupt from PA.6 or PB.5 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled.
+ * | | |1 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled.
+ * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PB.2 or PC.7 pin NMI source Disabled.
+ * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled.
+ * | | |1 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PB.7 or PF.14 pin NMI source Disabled.
+ * | | |1 = External interrupt from PB.7 or PF.14 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect)
+ * | | |0 = UART0 NMI source Disabled.
+ * | | |1 = UART0 NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect)
+ * | | |0 = UART1 NMI source Disabled.
+ * | | |1 = UART1 NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var NMI_T::NMISTS
+ * Offset: 0x04 NMI Source Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BODOUT |BOD Interrupt Flag (Read Only)
+ * | | |0 = BOD interrupt is deasserted.
+ * | | |1 = BOD interrupt is asserted.
+ * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only)
+ * | | |0 = HIRC TRIM interrupt is deasserted.
+ * | | |1 = HIRC TRIM interrupt is asserted.
+ * |[2] |PWRWU_INT |Power-down Mode Wake-up Interrupt Flag (Read Only)
+ * | | |0 = Power-down mode wake-up interrupt is deasserted.
+ * | | |1 = Power-down mode wake-up interrupt is asserted.
+ * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only)
+ * | | |0 = SRAM parity check error interrupt is deasserted.
+ * | | |1 = SRAM parity check error interrupt is asserted.
+ * |[4] |CLKFAIL |Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only)
+ * | | |0 = Clock fail detected or IRC Auto Trim interrupt is deasserted.
+ * | | |1 = Clock fail detected or IRC Auto Trim interrupt is asserted.
+ * |[6] |RTC_INT |RTC Interrupt Flag (Read Only)
+ * | | |0 = RTC interrupt is deasserted.
+ * | | |1 = RTC interrupt is asserted.
+ * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only)
+ * | | |0 = Backup register tamper detected interrupt is deasserted.
+ * | | |1 = Backup register tamper detected interrupt is asserted.
+ * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PA.6 or PB.5 interrupt is deasserted.
+ * | | |1 = External Interrupt from PA.6 or PB.5 interrupt is asserted.
+ * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted.
+ * | | |1 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted.
+ * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted.
+ * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted.
+ * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted.
+ * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted.
+ * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted.
+ * | | |1 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted.
+ * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PB.7 or PF.14 interrupt is deasserted.
+ * | | |1 = External Interrupt from PB.7 or PF.14 interrupt is asserted.
+ * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only)
+ * | | |0 = UART1 interrupt is deasserted.
+ * | | |1 = UART1 interrupt is asserted.
+ * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only)
+ * | | |0 = UART1 interrupt is deasserted.
+ * | | |1 = UART1 interrupt is asserted.
+ */
+ __IO uint32_t NMIEN; /*!< [0x0000] NMI Source Interrupt Enable Register */
+ __I uint32_t NMISTS; /*!< [0x0004] NMI Source Interrupt Status Register */
+
+} NMI_T;
+
+/**
+ @addtogroup NMI_CONST NMI Bit Field Definition
+ Constant Definitions for NMI Controller
+@{ */
+
+#define NMI_NMIEN_BODOUT_Pos (0) /*!< NMI_T::NMIEN: BODOUT Position */
+#define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) /*!< NMI_T::NMIEN: BODOUT Mask */
+
+#define NMI_NMIEN_IRC_INT_Pos (1) /*!< NMI_T::NMIEN: IRC_INT Position */
+#define NMI_NMIEN_IRC_INT_Msk (0x1ul << NMI_NMIEN_IRC_INT_Pos) /*!< NMI_T::NMIEN: IRC_INT Mask */
+
+#define NMI_NMIEN_PWRWU_INT_Pos (2) /*!< NMI_T::NMIEN: PWRWU_INT Position */
+#define NMI_NMIEN_PWRWU_INT_Msk (0x1ul << NMI_NMIEN_PWRWU_INT_Pos) /*!< NMI_T::NMIEN: PWRWU_INT Mask */
+
+#define NMI_NMIEN_SRAM_PERR_Pos (3) /*!< NMI_T::NMIEN: SRAM_PERR Position */
+#define NMI_NMIEN_SRAM_PERR_Msk (0x1ul << NMI_NMIEN_SRAM_PERR_Pos) /*!< NMI_T::NMIEN: SRAM_PERR Mask */
+
+#define NMI_NMIEN_CLKFAIL_Pos (4) /*!< NMI_T::NMIEN: CLKFAIL Position */
+#define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) /*!< NMI_T::NMIEN: CLKFAIL Mask */
+
+#define NMI_NMIEN_RTC_INT_Pos (6) /*!< NMI_T::NMIEN: RTC_INT Position */
+#define NMI_NMIEN_RTC_INT_Msk (0x1ul << NMI_NMIEN_RTC_INT_Pos) /*!< NMI_T::NMIEN: RTC_INT Mask */
+
+#define NMI_NMIEN_TAMPER_INT_Pos (7) /*!< NMI_T::NMIEN: TAMPER_INT Position */
+#define NMI_NMIEN_TAMPER_INT_Msk (0x1ul << NMI_NMIEN_TAMPER_INT_Pos) /*!< NMI_T::NMIEN: TAMPER_INT Mask */
+
+#define NMI_NMIEN_EINT0_Pos (8) /*!< NMI_T::NMIEN: EINT0 Position */
+#define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) /*!< NMI_T::NMIEN: EINT0 Mask */
+
+#define NMI_NMIEN_EINT1_Pos (9) /*!< NMI_T::NMIEN: EINT1 Position */
+#define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) /*!< NMI_T::NMIEN: EINT1 Mask */
+
+#define NMI_NMIEN_EINT2_Pos (10) /*!< NMI_T::NMIEN: EINT2 Position */
+#define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) /*!< NMI_T::NMIEN: EINT2 Mask */
+
+#define NMI_NMIEN_EINT3_Pos (11) /*!< NMI_T::NMIEN: EINT3 Position */
+#define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) /*!< NMI_T::NMIEN: EINT3 Mask */
+
+#define NMI_NMIEN_EINT4_Pos (12) /*!< NMI_T::NMIEN: EINT4 Position */
+#define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) /*!< NMI_T::NMIEN: EINT4 Mask */
+
+#define NMI_NMIEN_EINT5_Pos (13) /*!< NMI_T::NMIEN: EINT5 Position */
+#define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) /*!< NMI_T::NMIEN: EINT5 Mask */
+
+#define NMI_NMIEN_UART0_INT_Pos (14) /*!< NMI_T::NMIEN: UART0_INT Position */
+#define NMI_NMIEN_UART0_INT_Msk (0x1ul << NMI_NMIEN_UART0_INT_Pos) /*!< NMI_T::NMIEN: UART0_INT Mask */
+
+#define NMI_NMIEN_UART1_INT_Pos (15) /*!< NMI_T::NMIEN: UART1_INT Position */
+#define NMI_NMIEN_UART1_INT_Msk (0x1ul << NMI_NMIEN_UART1_INT_Pos) /*!< NMI_T::NMIEN: UART1_INT Mask */
+
+#define NMI_NMISTS_BODOUT_Pos (0) /*!< NMI_T::NMISTS: BODOUT Position */
+#define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) /*!< NMI_T::NMISTS: BODOUT Mask */
+
+#define NMI_NMISTS_IRC_INT_Pos (1) /*!< NMI_T::NMISTS: IRC_INT Position */
+#define NMI_NMISTS_IRC_INT_Msk (0x1ul << NMI_NMISTS_IRC_INT_Pos) /*!< NMI_T::NMISTS: IRC_INT Mask */
+
+#define NMI_NMISTS_PWRWU_INT_Pos (2) /*!< NMI_T::NMISTS: PWRWU_INT Position */
+#define NMI_NMISTS_PWRWU_INT_Msk (0x1ul << NMI_NMISTS_PWRWU_INT_Pos) /*!< NMI_T::NMISTS: PWRWU_INT Mask */
+
+#define NMI_NMISTS_SRAM_PERR_Pos (3) /*!< NMI_T::NMISTS: SRAM_PERR Position */
+#define NMI_NMISTS_SRAM_PERR_Msk (0x1ul << NMI_NMISTS_SRAM_PERR_Pos) /*!< NMI_T::NMISTS: SRAM_PERR Mask */
+
+#define NMI_NMISTS_CLKFAIL_Pos (4) /*!< NMI_T::NMISTS: CLKFAIL Position */
+#define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) /*!< NMI_T::NMISTS: CLKFAIL Mask */
+
+#define NMI_NMISTS_RTC_INT_Pos (6) /*!< NMI_T::NMISTS: RTC_INT Position */
+#define NMI_NMISTS_RTC_INT_Msk (0x1ul << NMI_NMISTS_RTC_INT_Pos) /*!< NMI_T::NMISTS: RTC_INT Mask */
+
+#define NMI_NMISTS_TAMPER_INT_Pos (7) /*!< NMI_T::NMISTS: TAMPER_INT Position */
+#define NMI_NMISTS_TAMPER_INT_Msk (0x1ul << NMI_NMISTS_TAMPER_INT_Pos) /*!< NMI_T::NMISTS: TAMPER_INT Mask */
+
+#define NMI_NMISTS_EINT0_Pos (8) /*!< NMI_T::NMISTS: EINT0 Position */
+#define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) /*!< NMI_T::NMISTS: EINT0 Mask */
+
+#define NMI_NMISTS_EINT1_Pos (9) /*!< NMI_T::NMISTS: EINT1 Position */
+#define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) /*!< NMI_T::NMISTS: EINT1 Mask */
+
+#define NMI_NMISTS_EINT2_Pos (10) /*!< NMI_T::NMISTS: EINT2 Position */
+#define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) /*!< NMI_T::NMISTS: EINT2 Mask */
+
+#define NMI_NMISTS_EINT3_Pos (11) /*!< NMI_T::NMISTS: EINT3 Position */
+#define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) /*!< NMI_T::NMISTS: EINT3 Mask */
+
+#define NMI_NMISTS_EINT4_Pos (12) /*!< NMI_T::NMISTS: EINT4 Position */
+#define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) /*!< NMI_T::NMISTS: EINT4 Mask */
+
+#define NMI_NMISTS_EINT5_Pos (13) /*!< NMI_T::NMISTS: EINT5 Position */
+#define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) /*!< NMI_T::NMISTS: EINT5 Mask */
+
+#define NMI_NMISTS_UART0_INT_Pos (14) /*!< NMI_T::NMISTS: UART0_INT Position */
+#define NMI_NMISTS_UART0_INT_Msk (0x1ul << NMI_NMISTS_UART0_INT_Pos) /*!< NMI_T::NMISTS: UART0_INT Mask */
+
+#define NMI_NMISTS_UART1_INT_Pos (15) /*!< NMI_T::NMISTS: UART1_INT Position */
+#define NMI_NMISTS_UART1_INT_Msk (0x1ul << NMI_NMISTS_UART1_INT_Pos) /*!< NMI_T::NMISTS: UART1_INT Mask */
+
+/**@}*/ /* NMI_CONST */
+/**@}*/ /* end of NMI register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __SYS_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/system_M480.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/system_M480.h
new file mode 100644
index 00000000000..fe12ac2f5fe
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/system_M480.h
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file system_M480.h
+ * @version V1.00
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M480
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __SYSTEM_M480_H__
+#define __SYSTEM_M480_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+
+#ifndef __HSI
+#define __HSI (12000000UL) /*!< PLL default output is 50MHz */
+#endif
+
+#ifndef __HXT
+#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
+#endif
+
+#ifndef __LXT
+#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
+#endif
+
+#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */
+#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
+#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */
+
+
+#define __SYSTEM_CLOCK (1UL*__HXT)
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
+extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the micro controller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_M480_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/timer_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/timer_reg.h
new file mode 100644
index 00000000000..7c3b4acdac6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/timer_reg.h
@@ -0,0 +1,1094 @@
+/**************************************************************************//**
+ * @file timer_reg.h
+ * @version V1.00
+ * @brief TIMER register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TIMER_REG_H__
+#define __TIMER_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup TIMER Timer Controller(TIMER)
+ Memory Mapped Structure for TIMER Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var TIMER_T::CTL
+ * Offset: 0x00 Timer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |PSC |Prescale Counter
+ * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter
+ * | | |If this field is 0 (PSC = 0), then there is no scaling.
+ * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
+ * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control
+ * | | |Setting this bit will enable the inter-timer trigger capture function.
+ * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event
+ * | | |Also, Timer1/3 will be in trigger-counting mode of capture function.
+ * | | |0 = Inter-Timer Trigger Capture mode Disabled.
+ * | | |1 = Inter-Timer Trigger Capture mode Enabled.
+ * | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0.
+ * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit
+ * | | |0 = The behavior selection in periodic mode is Disabled.
+ * | | |When user updates CMPDAT while timer is running in periodic mode,
+ * | | |CNT will be reset to default value.
+ * | | |1 = The behavior selection in periodic mode is Enabled.
+ * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list,
+ * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually.
+ * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately.
+ * | | |If updated CMPDAT value < CNT, CNT will be reset to default value.
+ * |[21] |TGLPINSEL |Toggle-output Pin Select
+ * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin).
+ * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin).
+ * |[22] |CAPSRC |Capture Pin Source Selection
+ * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin.
+ * | | |1 = Capture Function source is from internal ACMP output signal
+ * | | |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source.
+ * |[23] |WKEN |Wake-up Function Enable Bit
+ * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
+ * | | |0 = Wake-up function Disabled if timer interrupt signal generated.
+ * | | |1 = Wake-up function Enabled if timer interrupt signal generated.
+ * |[24] |EXTCNTEN |Event Counter Mode Enable Bit
+ * | | |This bit is for external counting pin function enabled.
+ * | | |0 = Event counter mode Disabled.
+ * | | |1 = Event counter mode Enabled.
+ * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
+ * |[25] |ACTSTS |Timer Active Status Bit (Read Only)
+ * | | |This bit indicates the 24-bit up counter status.
+ * | | |0 = 24-bit up counter is not active.
+ * | | |1 = 24-bit up counter is active.
+ * | | |Note: This bit may active when CNT 0 transition to CNT 1.
+ * |[28:27] |OPMODE |Timer Counting Mode Select
+ * | | |00 = The Timer controller is operated in One-shot mode.
+ * | | |01 = The Timer controller is operated in Periodic mode.
+ * | | |10 = The Timer controller is operated in Toggle-output mode.
+ * | | |11 = The Timer controller is operated in Continuous Counting mode.
+ * |[29] |INTEN |Timer Interrupt Enable Bit
+ * | | |0 = Timer time-out interrupt Disabled.
+ * | | |1 = Timer time-out interrupt Enabled.
+ * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
+ * |[30] |CNTEN |Timer Counting Enable Bit
+ * | | |0 = Stops/Suspends counting.
+ * | | |1 = Starts counting.
+ * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
+ * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
+ * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
+ * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
+ * | | |0 = ICE debug mode acknowledgement effects TIMER counting.
+ * | | |TIMER counter will be held while CPU is held by ICE.
+ * | | |1 = ICE debug mode acknowledgement Disabled.
+ * | | |TIMER counter will keep going no matter CPU is held by ICE or not.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var TIMER_T::CMP
+ * Offset: 0x04 Timer Comparator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CMPDAT |Timer Comparator Value
+ * | | |CMPDAT is a 24-bit compared value register
+ * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
+ * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
+ * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
+ * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field
+ * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
+ * @var TIMER_T::INTSTS
+ * Offset: 0x08 Timer Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TIF |Timer Interrupt Flag
+ * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
+ * | | |0 = No effect.
+ * | | |1 = CNT value matches the CMPDAT value.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[1] |TWKF |Timer Wake-up Flag
+ * | | |This bit indicates the interrupt wake-up flag status of timer.
+ * | | |0 = Timer does not cause CPU wake-up.
+ * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * @var TIMER_T::CNT
+ * Offset: 0x0C Timer Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CNT |Timer Data Register
+ * | | |Read operation.
+ * | | |Read this register to get CNT value. For example:
+ * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.
+ * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.
+ * | | |Write operation.
+ * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
+ * |[31] |RSTACT |Timer Data Register Reset Active (Read Only)
+ * | | |This bit indicates if the counter reset operation active.
+ * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter
+ * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress
+ * | | |Once the counter reset operation done, timer clear this bit to 0 automatically.
+ * | | |0 = Reset operation is done.
+ * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress.
+ * | | |Note: This bit is read only.
+ * @var TIMER_T::CAP
+ * Offset: 0x10 Timer Capture Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CAPDAT |Timer Capture Data Register
+ * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
+ * @var TIMER_T::EXTCTL
+ * Offset: 0x14 Timer External Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTPHASE |Timer External Count Phase
+ * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3).
+ * | | |0 = A falling edge of external counting pin will be counted.
+ * | | |1 = A rising edge of external counting pin will be counted.
+ * |[3] |CAPEN |Timer External Capture Pin Enable Bit
+ * | | |This bit enables the TMx_EXT capture pin input function.
+ * | | |0 =TMx_EXT (x= 0~3) pin Disabled.
+ * | | |1 =TMx_EXT (x= 0~3) pin Enabled.
+ * |[4] |CAPFUNCS |Capture Function Selection
+ * | | |0 = External Capture Mode Enabled.
+ * | | |1 = External Reset Mode Enabled.
+ * | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field.
+ * | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately.
+ * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit
+ * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled.
+ * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled.
+ * | | |Note: CAPIEN is used to enable timer external interrupt
+ * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
+ * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
+ * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit
+ * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled.
+ * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled.
+ * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
+ * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit
+ * | | |0 = TMx (x= 0~3) pin de-bounce Disabled.
+ * | | |1 = TMx (x= 0~3) pin de-bounce Enabled.
+ * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
+ * |[8:10] |ICAPSEL |Internal Capture Source Select
+ * | | |000 = Capture Function source is from internal ACMP0 output signal.
+ * | | |001 = Capture Function source is from internal ACMP1 output signal.
+ * | | |010 = Capture Function source is from HXT.
+ * | | |011 = Capture Function source is from LXT.
+ * | | |100 = Capture Function source is from HIRC.
+ * | | |101 = Capture Function source is from LIRC.
+ * | | |110 = Reserved.
+ * | | |111 = Reserved.
+ * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
+ * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect
+ * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
+ * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin.
+ * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin.
+ * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer.
+ * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer..
+ * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin.
+ * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin.
+ * | | |100, 101 = Reserved.
+ * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function
+ * | | |0 = Event Counter input source is from TMx (x= 0~3) pin.
+ * | | |1 = Event Counter input source is from USB internal SOF output signal.
+ * |[31:28] |CAPDIVSCL |Timer Capture Source Divider
+ * | | |This bits indicate the divide scale for capture source divider
+ * | | |0000 = Capture source/1.
+ * | | |0001 = Capture source/2.
+ * | | |0010 = Capture source/4.
+ * | | |0011 = Capture source/8.
+ * | | |0100 = Capture source/16.
+ * | | |0101 = Capture source/32.
+ * | | |0110 = Capture source/64.
+ * | | |0111 = Capture source/128.
+ * | | |1000 = Capture source/256.
+ * | | |1001~1111 = Reserved.
+ * | | |Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. * @var TIMER_T::EINTSTS
+ * Offset: 0x18 Timer External Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAPIF |Timer External Capture Interrupt Flag
+ * | | |This bit indicates the timer external capture interrupt flag status.
+ * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur.
+ * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
+ * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status
+ * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
+ * @var TIMER_T::TRGCTL
+ * Offset: 0x1C Timer Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TRGSSEL |Trigger Source Select Bit
+ * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or
+ * | | |capture interrupt signal.
+ * | | |0 = Time-out interrupt signal is used to internal trigger EPWM, BPWM, PDMA, DAC, and EADC.
+ * | | |1 = Capture interrupt signal is used to internal trigger EPWM, BPWM, PDMA, DAC, and EADC.
+ * |[1] |TRGEPWM |Trigger EPWM and BPWM Enable Bit
+ * | | |If this bit is set to 1, each timer time-out event or capture event can be as EPWM and BPWM counter clock source.
+ * | | |0 = Timer interrupt trigger EPWM and BPWM Disabled.
+ * | | |1 = Timer interrupt trigger EPWM and BPWM Enabled.
+ * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM and BPWM counter clock source.
+ * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM counter clock source.
+ * |[2] |TRGEADC |Trigger EADC Enable Bit
+ * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
+ * | | |0 = Timer interrupt trigger EADC Disabled.
+ * | | |1 = Timer interrupt trigger EADC Enabled.
+ * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion.
+ * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion.
+ * |[3] |TRGDAC |Trigger DAC Enable Bit
+ * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
+ * | | |0 = Timer interrupt trigger DAC Disabled.
+ * | | |1 = Timer interrupt trigger DAC Enabled.
+ * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC.
+ * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC.
+ * |[4] |TRGPDMA |Trigger PDMA Enable Bit
+ * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
+ * | | |0 = Timer interrupt trigger PDMA Disabled.
+ * | | |1 = Timer interrupt trigger PDMA Enabled.
+ * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer.
+ * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer.
+ * @var TIMER_T::ALTCTL
+ * Offset: 0x20 Timer Alternative Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FUNCSEL |Function Selection
+ * | | |0 = Timer controller is used as timer function.
+ * | | |1 = Timer controller is used as PWM function.
+ * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
+ * @var TIMER_T::PWMCTL
+ * Offset: 0x40 Timer PWM Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTEN |PWM Counter Enable Bit
+ * | | |0 = PWM counter and clock prescale Stop Running.
+ * | | |1 = PWM counter and clock prescale Start Running.
+ * |[2:1] |CNTTYPE |PWM Counter Behavior Type
+ * | | |00 = Up count type.
+ * | | |01 = Down count type.
+ * | | |10 = Up-down count type.
+ * | | |11 = Reserved.
+ * |[3] |CNTMODE |PWM Counter Mode
+ * | | |0 = Auto-reload mode.
+ * | | |1 = One-shot mode.
+ * |[8] |CTRLD |Center Re-load
+ * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.
+ * |[9] |IMMLDEN |Immediately Load Enable Bit
+ * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled
+ * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period.
+ * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP.
+ * | | |Note: If IMMLDEN is enabled, CTRLD will be invalid.
+ * |[16] |OUTMODE |PWM Output Mode
+ * | | |This bit controls the output mode of corresponding PWM channel.
+ * | | |0 = PWM independent mode.
+ * | | |1 = PWM complementary mode.
+ * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
+ * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode.
+ * | | |0 = ICE debug mode counter halt disable.
+ * | | |1 = ICE debug mode counter halt enable.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
+ * | | |0 = ICE debug mode acknowledgement effects PWM output.
+ * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged.
+ * | | |1 = ICE debug mode acknowledgement disabled.
+ * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * @var TIMER_T::PWMCLKSRC
+ * Offset: 0x44 Timer PWM Counter Clock Source Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |CLKSRC |PWM Counter Clock Source Select
+ * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.
+ * | | |000 = TMRx_CLK.
+ * | | |001 = Internal TIMER0 time-out or capture event.
+ * | | |010 = Internal TIMER1 time-out or capture event.
+ * | | |011 = Internal TIMER2 time-out or capture event.
+ * | | |100 = Internal TIMER3 time-out or capture event.
+ * | | |Others = Reserved.
+ * | | |Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
+ * @var TIMER_T::PWMCLKPSC
+ * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale
+ * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)
+ * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source.
+ * @var TIMER_T::PWMCNTCLR
+ * Offset: 0x4C Timer PWM Clear Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTCLR |Clear PWM Counter Control Bit
+ * | | |It is automatically cleared by hardware.
+ * | | |0 = No effect.
+ * | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type.
+ * @var TIMER_T::PWMPERIOD
+ * Offset: 0x50 Timer PWM Period Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PERIOD |PWM Period Register
+ * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.
+ * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.
+ * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+ * | | |In up and down count type:
+ * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK.
+ * | | |In up-down count type:
+ * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK.
+ * | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type.
+ * @var TIMER_T::PWMCMPDAT
+ * Offset: 0x54 Timer PWM Comparator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMP |PWM Comparator Register
+ * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert.
+ * @var TIMER_T::PWMDTCTL
+ * Offset: 0x58 Timer PWM Dead-Time Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |DTCNT |Dead-time Counter (Write Protect)
+ * | | |The dead-time can be calculated from the following two formulas:
+ * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0.
+ * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)
+ * | | |Dead-time insertion function is only active when PWM complementary mode is enabled
+ * | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.
+ * | | |0 = Dead-time insertion Disabled on the pin pair.
+ * | | |1 = Dead-time insertion Enabled on the pin pair.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect)
+ * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale.
+ * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * @var TIMER_T::PWMCNT
+ * Offset: 0x5C Timer PWM Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CNT |PWM Counter Value Register (Read Only)
+ * | | |User can monitor CNT to know the current counter value in 16-bit period counter.
+ * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only)
+ * | | |0 = Counter is active in down count.
+ * | | |1 = Counter is active up count.
+ * @var TIMER_T::PWMMSKEN
+ * Offset: 0x60 Timer PWM Output Mask Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit
+ * | | |The PWMx_CH0 output signal will be masked when this bit is enabled
+ * | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data.
+ * | | |0 = PWMx_CH0 output signal is non-masked.
+ * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data.
+ * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit
+ * | | |The PWMx_CH1 output signal will be masked when this bit is enabled
+ * | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data.
+ * | | |0 = PWMx_CH1 output signal is non-masked.
+ * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data.
+ * @var TIMER_T::PWMMSK
+ * Offset: 0x64 Timer PWM Output Mask Data Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit
+ * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1).
+ * | | |0 = Output logic Low to PWMx_CH0.
+ * | | |1 = Output logic High to PWMx_CH0.
+ * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit
+ * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1).
+ * | | |0 = Output logic Low to PWMx_CH1.
+ * | | |1 = Output logic High to PWMx_CH1.
+ * @var TIMER_T::PWMBNF
+ * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit
+ * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled.
+ * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled.
+ * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection
+ * | | |000 = Noise filter clock is PCLKx.
+ * | | |001 = Noise filter clock is PCLKx/2.
+ * | | |010 = Noise filter clock is PCLKx/4.
+ * | | |011 = Noise filter clock is PCLKx/8.
+ * | | |100 = Noise filter clock is PCLKx/16.
+ * | | |101 = Noise filter clock is PCLKx/32.
+ * | | |110 = Noise filter clock is PCLKx/64.
+ * | | |111 = Noise filter clock is PCLKx/128.
+ * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count
+ * | | |The fields is used to control the active noise filter sample time.
+ * | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT.
+ * |[7] |BRKPINV |Brake Pin Detection Control Bit
+ * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect.
+ * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect .
+ * |[17:16] |BKPINSRC |Brake Pin Source Select
+ * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin.
+ * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin.
+ * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin.
+ * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin.
+ * @var TIMER_T::PWMFAILBRK
+ * Offset: 0x6C Timer PWM System Fail Brake Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit
+ * | | |0 = Brake Function triggered by clock fail detection Disabled.
+ * | | |1 = Brake Function triggered by clock fail detection Enabled.
+ * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit
+ * | | |0 = Brake Function triggered by BOD event Disabled.
+ * | | |1 = Brake Function triggered by BOD event Enabled.
+ * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit
+ * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
+ * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
+ * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit
+ * | | |0 = Brake Function triggered by core lockup event Disabled.
+ * | | |1 = Brake Function triggered by core lockup event Enabled.
+ * @var TIMER_T::PWMBRKCTL
+ * Offset: 0x70 Timer PWM Brake Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
+ * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled.
+ * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled.
+ * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
+ * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled.
+ * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled.
+ * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)
+ * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled.
+ * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect)
+ * | | |0 = System fail condition as edge-detect brake source Disabled.
+ * | | |1 = System fail condition as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
+ * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled.
+ * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled.
+ * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
+ * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled.
+ * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled.
+ * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)
+ * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled.
+ * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect)
+ * | | |0 = System fail condition as level-detect brake source Disabled.
+ * | | |1 = System fail condition as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect)
+ * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output.
+ * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened.
+ * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened.
+ * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect)
+ * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output.
+ * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened.
+ * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened.
+ * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * @var TIMER_T::PWMPOLCTL
+ * Offset: 0x74 Timer PWM Pin Output Polar Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit
+ * | | |The bit is used to control polarity state of PWMx_CH0 output pin.
+ * | | |0 = PWMx_CH0 output pin polar inverse Disabled.
+ * | | |1 = PWMx_CH0 output pin polar inverse Enabled.
+ * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit
+ * | | |The bit is used to control polarity state of PWMx_CH1 output pin.
+ * | | |0 = PWMx_CH1 output pin polar inverse Disabled.
+ * | | |1 = PWMx_CH1 output pin polar inverse Enabled.
+ * @var TIMER_T::PWMPOEN
+ * Offset: 0x78 Timer PWM Pin Output Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit
+ * | | |0 = PWMx_CH0 pin at tri-state mode.
+ * | | |1 = PWMx_CH0 pin in output mode.
+ * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit
+ * | | |0 = PWMx_CH1 pin at tri-state mode.
+ * | | |1 = PWMx_CH1 pin in output mode.
+ * @var TIMER_T::PWMSWBRK
+ * Offset: 0x7C Timer PWM Software Trigger Brake Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)
+ * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect)
+ * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * @var TIMER_T::PWMINTEN0
+ * Offset: 0x80 Timer PWM Interrupt Enable Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit
+ * | | |0 = Zero point interrupt Disabled.
+ * | | |1 = Zero point interrupt Enabled.
+ * |[1] |PIEN |PWM Period Point Interrupt Enable Bit
+ * | | |0 = Period point interrupt Disabled.
+ * | | |1 = Period point interrupt Enabled.
+ * | | |Note: When in up-down count type, period point means the center point of current PWM period.
+ * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * @var TIMER_T::PWMINTEN1
+ * Offset: 0x84 Timer PWM Interrupt Enable Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect)
+ * | | |0 = PWM edge-detect brake interrupt Disabled.
+ * | | |1 = PWM edge-detect brake interrupt Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect)
+ * | | |0 = PWM level-detect brake interrupt Disabled.
+ * | | |1 = PWM level-detect brake interrupt Enabled.
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
+ * @var TIMER_T::PWMINTSTS0
+ * Offset: 0x88 Timer PWM Interrupt Status Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ZIF |PWM Zero Point Interrupt Flag
+ * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[1] |PIF |PWM Period Point Interrupt Flag
+ * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD.
+ * | | |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period.
+ * | | |Note2: This bit is cleared by writing 1 to it.
+ * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag
+ * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.
+ * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type.
+ * | | |Note2: This bit is cleared by writing 1 to it.
+ * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag
+ * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.
+ * | | |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.
+ * | | |Note2: This bit is cleared by writing 1 to it.
+ * @var TIMER_T::PWMINTSTS1
+ * Offset: 0x8C Timer PWM Interrupt Status Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
+ * | | |0 = PWMx_CH0 edge-detect brake event do not happened.
+ * | | |1 = PWMx_CH0 edge-detect brake event happened.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)
+ * | | |0 = PWMx_CH1 edge-detect brake event do not happened.
+ * | | |1 = PWMx_CH1 edge-detect brake event happened.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
+ * | | |0 = PWMx_CH0 level-detect brake event do not happened.
+ * | | |1 = PWMx_CH0 level-detect brake event happened.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)
+ * | | |0 = PWMx_CH1 level-detect brake event do not happened.
+ * | | |1 = PWMx_CH1 level-detect brake event happened.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+ * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only)
+ * | | |0 = PWMx_CH0 edge-detect brake state is released.
+ * | | |1 = PWMx_CH0 at edge-detect brake state.
+ * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period.
+ * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only)
+ * | | |0 = PWMx_CH1 edge-detect brake state is released.
+ * | | |1 = PWMx_CH1 at edge-detect brake state.
+ * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period.
+ * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only)
+ * | | |0 = PWMx_CH0 level-detect brake state is released.
+ * | | |1 = PWMx_CH0 at level-detect brake state.
+ * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
+ * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only)
+ * | | |0 = PWMx_CH1 level-detect brake state is released.
+ * | | |1 = PWMx_CH1 at level-detect brake state.
+ * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
+ * @var TIMER_T::PWMEADCTS
+ * Offset: 0x90 Timer PWM ADC Trigger Source Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger EADC Conversion
+ * | | |000 = Trigger EADC conversion at zero point (ZIF).
+ * | | |001 = Trigger EADC conversion at period point (PIF).
+ * | | |010 = Trigger EADC conversion at zero or period point (ZIF or PIF).
+ * | | |011 = Trigger EADC conversion at compare up count point (CMPUIF).
+ * | | |100 = Trigger EADC conversion at compare down count point (CMPDIF).
+ * | | |Others = Reserved.
+ * |[7] |TRGEN |PWM Counter Event Trigger EADC Conversion Enable Bit
+ * | | |0 = PWM counter event trigger EADC conversion Disabled.
+ * | | |1 = PWM counter event trigger EADC conversion Enabled.
+ * @var TIMER_T::PWMSCTL
+ * Offset: 0x94 Timer PWM Synchronous Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select
+ * | | |00 = PWM synchronous function Disabled.
+ * | | |01 = PWM synchronous counter start function Enabled.
+ * | | |10 = Reserved.
+ * | | |11 = PWM synchronous counter clear function Enabled.
+ * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select
+ * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN.
+ * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN.
+ * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.
+ * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1.
+ * @var TIMER_T::PWMSTRG
+ * Offset: 0x98 Timer PWM Synchronous Trigger Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only)
+ * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.
+ * | | |Note: This bit is only available in TIMER0 and TIMER2.
+ * @var TIMER_T::PWMSTATUS
+ * Offset: 0x9C Timer PWM Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag
+ * | | |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF.
+ * | | |1 = Indicates the PWM counter value has reached its maximum value.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag
+ * | | |0 = PWM counter event trigger EADC start conversion is not occurred.
+ * | | |1 = PWM counter event trigger EADC start conversion has occurred.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * @var TIMER_T::PWMPBUF
+ * Offset: 0xA0 Timer PWM Period Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PBUF |PWM Period Buffer Register (Read Only)
+ * | | |Used as PERIOD active register.
+ * @var TIMER_T::PWMCMPBUF
+ * Offset: 0xA4 Timer PWM Comparator Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only)
+ * | | |Used as CMP active register.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */
+ __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */
+ __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */
+ __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */
+ __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */
+ __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */
+ __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */
+ __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */
+ __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE0[7];
+ /** @endcond */
+ __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */
+ __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */
+ __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */
+ __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */
+ __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */
+ __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */
+ __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */
+ __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */
+ __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */
+ __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */
+ __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */
+ __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */
+ __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */
+ __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */
+ __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */
+ __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */
+ __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */
+ __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */
+ __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */
+ __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */
+ __IO uint32_t PWMEADCTS; /*!< [0x0090] Timer PWM EADC Trigger Source Select Register */
+ __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */
+ __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */
+ __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */
+ __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */
+ __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */
+
+} TIMER_T;
+
+/**
+ @addtogroup TIMER_CONST TIMER Bit Field Definition
+ Constant Definitions for TIMER Controller
+@{ */
+
+#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
+#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
+
+#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */
+#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */
+
+#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */
+#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */
+
+#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */
+#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
+
+#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */
+#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */
+
+#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
+#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
+
+#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
+#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
+
+#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
+#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
+
+#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
+#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
+
+#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
+#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
+
+#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
+#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
+
+#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
+#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
+
+#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
+#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
+
+#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
+#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
+
+#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
+#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
+
+#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
+#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
+
+#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */
+#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */
+
+#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
+#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
+
+#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
+#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
+
+#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
+#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
+
+#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
+#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
+
+#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
+#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
+
+#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
+#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
+
+#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
+#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
+
+#define TIMER_EXTCTL_ICAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: ICAPSEL Position */
+#define TIMER_EXTCTL_ICAPSEL_Msk (0x7ul << TIMER_EXTCTL_ICAPSEL_Pos) /*!< TIMER_T::EXTCTL: ICAPSEL Mask */
+
+#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
+#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
+
+#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */
+#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */
+
+#define TIMER_EXTCTL_CAPDIVSCL_Pos (28) /*!< TIMER_T::EXTCTL: CAPDIVSCL Position */
+#define TIMER_EXTCTL_CAPDIVSCL_Msk (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< TIMER_T::EXTCTL: CAPDIVSCL Mask */
+
+#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
+#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
+
+#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */
+#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */
+
+#define TIMER_TRGCTL_TRGEPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGEPWM Position */
+#define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) /*!< TIMER_T::TRGCTL: TRGEPWM Mask */
+
+#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */
+#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */
+
+#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */
+#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */
+
+#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */
+#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */
+
+#define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */
+#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */
+
+#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */
+#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */
+
+#define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */
+#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */
+
+#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */
+#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */
+
+#define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */
+#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */
+
+#define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */
+#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */
+
+#define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */
+#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */
+
+#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */
+#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */
+
+#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */
+#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */
+
+#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */
+#define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */
+
+#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */
+#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */
+
+#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */
+#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */
+
+#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */
+#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */
+
+#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */
+#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */
+
+#define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */
+#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */
+
+#define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */
+#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */
+
+#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */
+#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */
+
+#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */
+#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */
+
+#define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */
+#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */
+
+#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */
+#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */
+
+#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */
+#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */
+
+#define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */
+#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */
+
+#define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */
+#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */
+
+#define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */
+#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */
+
+#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */
+#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */
+
+#define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */
+#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */
+
+#define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */
+#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */
+
+#define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */
+#define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */
+
+#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */
+#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */
+
+#define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */
+#define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */
+
+#define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */
+#define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */
+
+#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */
+#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */
+
+#define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */
+#define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */
+
+#define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */
+#define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */
+
+#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */
+#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */
+
+#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */
+#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */
+
+#define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */
+#define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */
+
+#define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */
+#define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */
+
+#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */
+#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */
+
+#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */
+#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */
+
+#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */
+#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */
+
+#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */
+#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */
+
+#define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */
+#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */
+
+#define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */
+#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */
+
+#define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */
+#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */
+
+#define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */
+#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */
+
+#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */
+#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */
+
+#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */
+#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */
+
+#define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */
+#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */
+
+#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */
+#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */
+
+#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */
+#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */
+
+#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */
+#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */
+
+#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */
+#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */
+
+#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */
+#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */
+
+#define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */
+#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */
+
+#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */
+#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */
+
+#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */
+#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */
+
+#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */
+#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */
+
+#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */
+#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */
+
+#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */
+#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */
+
+#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */
+#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */
+
+#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */
+#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */
+
+#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */
+#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */
+
+#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */
+#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */
+
+#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */
+#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */
+
+#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */
+#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */
+
+#define TIMER_PWMEADCTS_TRGSEL_Pos (0) /*!< TIMER_T::PWMEADCTS: TRGSEL Position */
+#define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< TIMER_T::PWMEADCTS: TRGSEL Mask */
+
+#define TIMER_PWMEADCTS_TRGEN_Pos (7) /*!< TIMER_T::PWMEADCTS: TRGEN Position */
+#define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /*!< TIMER_T::PWMEADCTS: TRGEN Mask */
+
+#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */
+#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */
+
+#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */
+#define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */
+
+#define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */
+#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */
+
+#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */
+#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */
+
+#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */
+#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */
+
+#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */
+#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */
+
+#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */
+#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */
+
+/**@}*/ /* TIMER_CONST */
+/**@}*/ /* end of TIMER register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __TIMER_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/trng_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/trng_reg.h
new file mode 100644
index 00000000000..ede3dfa65ba
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/trng_reg.h
@@ -0,0 +1,138 @@
+/**************************************************************************//**
+ * @file trng_reg.h
+ * @version V1.00
+ * @brief TRNG register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TRNG_REG_H__
+#define __TRNG_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+ @{
+
+*/
+
+/*---------------------- True Random Number Generator -------------------------*/
+/**
+ @addtogroup TRNG True Random Number Generator(TRNG)
+ Memory Mapped Structure for TRNG Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var TRNG_T::CTL
+ * Offset: 0x00 TRNG Control Register and Status
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TRNGEN |Random Number Generator Enable Bit
+ * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1.
+ * | | |0 = TRNG disabled.
+ * | | |1 = TRNG enabled.
+ * | | |Note: TRNGEN is an enable bit of digital part
+ * | | |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption.
+ * |[1] |DVIF |Data Valid (Read Only)
+ * | | |0 = Data is not valid. Reading from RNGD returns 0x00000000.
+ * | | |1 = Data is valid. A valid random number can be read form RNGD.
+ * | | |This bit is cleared to u20180u2019 by read TRNG_DATA.
+ * |[5:2] |CLKP |Clock Prescaler
+ * | | |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation)
+ * | | |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module.
+ * | | |0000 = 80 ~ 100 MHz.
+ * | | |0001 = 60 ~ 80 MHz.
+ * | | |0010 = 50 ~60 MHz.
+ * | | |0011 = 40 ~50 MHz.
+ * | | |0100 = 30 ~40 MHz.
+ * | | |0101 = 25 ~30 MHz.
+ * | | |0110 = 20 ~25 MHz.
+ * | | |0111 = 15 ~20 MHz.
+ * | | |1000 = 12 ~15 MHz.
+ * | | |1001 = 9 ~12 MHz.
+ * | | |1010 = 7 ~9 MHz.
+ * | | |1011 = 6 ~7 MHz.
+ * | | |1100 = 5 ~6 MHz.
+ * | | |1101 = 4 ~5 MHz.
+ * | | |1111 = Reserved.
+ * |[6] |DVIEN |Data Valid Interrupt Enable Bit
+ * | | |0 = Interrupt disabled..
+ * | | |1 = Interrupt enabled.
+ * |[7] |READY |Random Number Generator Ready (Read Only)
+ * | | |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us.
+ * | | |0 = RNG is not ready or was not activated.
+ * | | |1 = RNG is ready to be enabled..
+ * |[31:8] |Reversed |Reversed
+ * @var TRNG_T::DATA
+ * Offset: 0x04 TRNG Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DATA |Random Number Generator Data (Read Only)
+ * | | |The DATA store the random number generated by TRNG and can be read only once.
+ * @var TRNG_T::ACT
+ * Offset: 0x0C TRNG Activation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |VER |TRNG Version
+ * | | |TRNG version number is dependent on TRNG module.
+ * | | |0x02:(Current Version Number)
+ * |[7] |ACT |Random Number Generator Activation
+ * | | |After enable the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.
+ * | | |0 = TRNG inactive.
+ * | | |1 = TRNG active.
+ * | | |Note: ACT is an enable bit of analog part
+ * | | |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] TRNG Control Register and Status */
+ __I uint32_t DATA; /*!< [0x0004] TRNG Data Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t ACT; /*!< [0x000c] TRNG Activation Register */
+
+} TRNG_T;
+
+/**
+ @addtogroup TRNG_CONST TRNG Bit Field Definition
+ Constant Definitions for TRNG Controller
+@{ */
+
+#define TRNG_CTL_TRNGEN_Pos (0) /*!< TRNG_T::CTL: TRNGEN Position */
+#define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */
+
+#define TRNG_CTL_DVIF_Pos (1) /*!< TRNG_T::CTL: DVIF Position */
+#define TRNG_CTL_DVIF_Msk (0x1ul << TRNG_CTL_DVIF_Pos) /*!< TRNG_T::CTL: DVIF Mask */
+
+#define TRNG_CTL_CLKP_Pos (2) /*!< TRNG_T::CTL: CLKP Position */
+#define TRNG_CTL_CLKP_Msk (0xful << TRNG_CTL_CLKP_Pos) /*!< TRNG_T::CTL: CLKP Mask */
+
+#define TRNG_CTL_DVIEN_Pos (6) /*!< TRNG_T::CTL: DVIEN Position */
+#define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */
+
+#define TRNG_CTL_READY_Pos (7) /*!< TRNG_T::CTL: READY Position */
+#define TRNG_CTL_READY_Msk (0x1ul << TRNG_CTL_READY_Pos) /*!< TRNG_T::CTL: READY Mask */
+
+#define TRNG_CTL_Reversed_Pos (8) /*!< TRNG_T::CTL: Reversed Position */
+#define TRNG_CTL_Reversed_Msk (0xfffffful << TRNG_CTL_Reversed_Pos) /*!< TRNG_T::CTL: Reversed Mask */
+
+#define TRNG_DATA_DATA_Pos (0) /*!< TRNG_T::DATA: DATA Position */
+#define TRNG_DATA_DATA_Msk (0xfful << TRNG_DATA_DATA_Pos) /*!< TRNG_T::DATA: DATA Mask */
+
+#define TRNG_ACT_VER_Pos (0) /*!< TRNG_T::ACT: VER Position */
+#define TRNG_ACT_VER_Msk (0x7ful << TRNG_ACT_VER_Pos) /*!< TRNG_T::ACT: VER Mask */
+
+#define TRNG_ACT_ACT_Pos (7) /*!< TRNG_T::ACT: ACT Position */
+#define TRNG_ACT_ACT_Msk (0x1ul << TRNG_ACT_ACT_Pos) /*!< TRNG_T::ACT: ACT Mask */
+
+/**@}*/ /* TRNG_CONST */
+/**@}*/ /* end of TRNG register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __TRNG_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uart_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uart_reg.h
new file mode 100644
index 00000000000..3524551a7a1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uart_reg.h
@@ -0,0 +1,1273 @@
+/**************************************************************************//**
+ * @file uart_reg.h
+ * @version V1.00
+ * @brief UART register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __UART_REG_H__
+#define __UART_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
+ Memory Mapped Structure for UART Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var UART_T::DAT
+ * Offset: 0x00 UART Receive/Transmit Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DAT |Data Receive/Transmit Buffer
+ * | | |Write Operation:
+ * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO
+ * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
+ * | | |Read Operation:
+ * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
+ * |[8] |PARITY |Parity Bit Receive/Transmit Buffer
+ * | | |Write Operation:
+ * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO
+ * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set,
+ * | | |the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
+ * | | |Read Operation:
+ * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.
+ * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
+ * @var UART_T::INTEN
+ * Offset: 0x04 UART Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit
+ * | | |0 = Receive data available interrupt Disabled.
+ * | | |1 = Receive data available interrupt Enabled.
+ * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit
+ * | | |0 = Transmit holding register empty interrupt Disabled.
+ * | | |1 = Transmit holding register empty interrupt Enabled.
+ * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
+ * | | |0 = Receive Line Status interrupt Disabled.
+ * | | |1 = Receive Line Status interrupt Enabled.
+ * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit
+ * | | |0 = Modem status interrupt Disabled.
+ * | | |1 = Modem status interrupt Enabled.
+ * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit
+ * | | |0 = RX time-out interrupt Disabled.
+ * | | |1 = RX time-out interrupt Enabled.
+ * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit
+ * | | |0 = Buffer error interrupt Disabled.
+ * | | |1 = Buffer error interrupt Enabled.
+ * |[6] |WKIEN |Wake-up Interrupt Enable Bit
+ * | | |0 = Wake-up Interrupt Disabled.
+ * | | |1 = Wake-up Interrupt Enabled.
+ * |[8] |LINIEN |LIN Bus Interrupt Enable Bit
+ * | | |0 = LIN bus interrupt Disabled.
+ * | | |1 = LIN bus interrupt Enabled.
+ * | | |Note: This bit is used for LIN function mode.
+ * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit
+ * | | |0 = Receive Buffer Time-out counter Disabled.
+ * | | |1 = Receive Buffer Time-out counter Enabled.
+ * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit
+ * | | |0 = nRTS auto-flow control Disabled.
+ * | | |1 = nRTS auto-flow control Enabled.
+ * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
+ * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit
+ * | | |0 = nCTS auto-flow control Disabled.
+ * | | |1 = nCTS auto-flow control Enabled.
+ * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
+ * |[14] |TXPDMAEN |TX PDMA Enable Bit
+ * | | |This bit can enable or disable TX PDMA service.
+ * | | |0 = TX PDMA Disabled.
+ * | | |1 = TX PDMA Enabled.
+ * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused
+ * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop
+ * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
+ * |[15] |RXPDMAEN |RX PDMA Enable Bit
+ * | | |This bit can enable or disable RX PDMA service.
+ * | | |0 = RX PDMA Disabled.
+ * | | |1 = RX PDMA Enabled.
+ * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused
+ * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop
+ * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
+ * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit
+ * | | |0 = Auto-baud rate interrupt Disabled.
+ * | | |1 = Auto-baud rate interrupt Enabled.
+ * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit
+ * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
+ * | | |0 = Transmitter empty interrupt Disabled.
+ * | | |1 = Transmitter empty interrupt Enabled.
+ * @var UART_T::FIFO
+ * Offset: 0x08 UART FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |RXRST |RX Field Software Reset
+ * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the RX internal state machine and pointers.
+ * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
+ * | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
+ * |[2] |TXRST |TX Field Software Reset
+ * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the TX internal state machine and pointers.
+ * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
+ * | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
+ * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level
+ * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
+ * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
+ * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
+ * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
+ * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
+ * | | |Others = Reserved.
+ * |[8] |RXOFF |Receiver Disable Bit
+ * | | |The receiver is disabled or not (set 1 to disable receiver).
+ * | | |0 = Receiver Enabled.
+ * | | |1 = Receiver Disabled.
+ * | | |Note: This bit is used for RS-485 Normal Multi-drop mode
+ * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
+ * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control Use
+ * | | |0000 = nRTS Trigger Level is 1 byte.
+ * | | |0001 = nRTS Trigger Level is 4 bytes.
+ * | | |0010 = nRTS Trigger Level is 8 bytes.
+ * | | |0011 = nRTS Trigger Level is 14 bytes.
+ * | | |Others = Reserved.
+ * | | |Note: This field is used for auto nRTS flow control.
+ * @var UART_T::LINE
+ * Offset: 0x0C UART Line Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |WLS |Word Length Selection
+ * | | |This field sets UART word length.
+ * | | |00 = 5 bits.
+ * | | |01 = 6 bits.
+ * | | |10 = 7 bits.
+ * | | |11 = 8 bits.
+ * |[2] |NSB |Number of 'STOP Bit'
+ * | | |0 = One 'STOP bit' is generated in the transmitted data.
+ * | | |1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data
+ * | | |When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data.
+ * |[3] |PBE |Parity Bit Enable Bit
+ * | | |0 = Parity bit generated Disabled.
+ * | | |1 = Parity bit generated Enabled.
+ * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
+ * |[4] |EPE |Even Parity Enable Bit
+ * | | |0 = Odd number of logic '1's is transmitted and checked in each word.
+ * | | |1 = Even number of logic '1's is transmitted and checked in each word.
+ * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set.
+ * |[5] |SPE |Stick Parity Enable Bit
+ * | | |0 = Stick parity Disabled.
+ * | | |1 = Stick parity Enabled.
+ * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0
+ * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
+ * |[6] |BCB |Break Control Bit
+ * | | |0 = Break Control Disabled.
+ * | | |1 = Break Control Enabled.
+ * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0)
+ * | | |This bit acts only on TX line and has no effect on the transmitter logic.
+ * |[7] |PSS |Parity Bit Source Selection
+ * | | |The parity bit can be selected to be generated and checked automatically or by software.
+ * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically.
+ * | | |1 = Parity bit generated and checked by software.
+ * | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set.
+ * | | |Note2: If PSS is 0, the parity bit is transmitted and checked automatically
+ * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
+ * |[8] |TXDINV |TX Data Inverted
+ * | | |0 = Transmitted data signal inverted Disabled.
+ * | | |1 = Transmitted data signal inverted Enabled.
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
+ * |[9] |RXDINV |RX Data Inverted
+ * | | |0 = Received data signal inverted Disabled.
+ * | | |1 = Received data signal inverted Enabled.
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
+ * @var UART_T::MODEM
+ * Offset: 0x10 UART Modem Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |RTS |nRTS (Request-to-send) Signal Control
+ * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
+ * | | |0 = nRTS signal is active.
+ * | | |1 = nRTS signal is inactive.
+ * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
+ * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
+ * |[9] |RTSACTLV |nRTS Pin Active Level
+ * | | |This bit defines the active level state of nRTS pin output.
+ * | | |0 = nRTS pin output is high level active.
+ * | | |1 = nRTS pin output is low level active. (Default)
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * |[13] |RTSSTS |nRTS Pin Status (Read Only)
+ * | | |This bit mirror from nRTS pin output of voltage logic status.
+ * | | |0 = nRTS pin output is low level voltage logic state.
+ * | | |1 = nRTS pin output is high level voltage logic state.
+ * @var UART_T::MODEMSTS
+ * Offset: 0x14 UART Modem Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CTSDETF |Detect nCTS State Change Flag
+ * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
+ * | | |0 = nCTS input has not change state.
+ * | | |1 = nCTS input has change state.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[4] |CTSSTS |nCTS Pin Status (Read Only)
+ * | | |This bit mirror from nCTS pin input of voltage logic status.
+ * | | |0 = nCTS pin input is low level voltage logic state.
+ * | | |1 = nCTS pin input is high level voltage logic state.
+ * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
+ * |[8] |CTSACTLV |nCTS Pin Active Level
+ * | | |This bit defines the active level state of nCTS pin input.
+ * | | |0 = nCTS pin input is high level active.
+ * | | |1 = nCTS pin input is low level active. (Default)
+ * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * @var UART_T::FIFOSTS
+ * Offset: 0x18 UART FIFO Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXOVIF |RX Overflow Error Interrupt Flag
+ * | | |This bit is set when RX FIFO overflow.
+ * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
+ * | | |0 = RX FIFO is not overflow.
+ * | | |1 = RX FIFO is overflow.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag
+ * | | |This bit is set to logic '1' when auto-baud rate detect function is finished.
+ * | | |0 = Auto-baud rate detect function is not finished.
+ * | | |1 = Auto-baud rate detect function is finished.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag
+ * | | |This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
+ * | | |0 = Auto-baud rate counter is underflow.
+ * | | |1 = Auto-baud rate counter is overflow.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag
+ * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
+ * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1').
+ * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * |[4] |PEF |Parity Error Flag
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
+ * | | |0 = No parity error is generated.
+ * | | |1 = Parity error is generated.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[5] |FEF |Framing Error Flag
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit'
+ * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+ * | | |0 = No framing error is generated.
+ * | | |1 = Framing error is generated.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[6] |BIF |Break Interrupt Flag
+ * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0)
+ * | | |for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
+ * | | |0 = No Break interrupt is generated.
+ * | | |1 = Break interrupt is generated.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[13:8] |RXPTR |RX FIFO Pointer (Read Only)
+ * | | |This field indicates the RX FIFO Buffer Pointer
+ * | | |When UART receives one byte from external device, RXPTR increases one
+ * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
+ * | | |The Maximum value shown in RXPTR is 15
+ * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0
+ * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15
+ * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)
+ * | | |This bit initiate RX FIFO empty or not.
+ * | | |0 = RX FIFO is not empty.
+ * | | |1 = RX FIFO is empty.
+ * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high
+ * | | |It will be cleared when UART receives any new data.
+ * |[15] |RXFULL |Receiver FIFO Full (Read Only)
+ * | | |This bit initiates RX FIFO full or not.
+ * | | |0 = RX FIFO is not full.
+ * | | |1 = RX FIFO is full.
+ * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
+ * |[21:16] |TXPTR |TX FIFO Pointer (Read Only)
+ * | | |This field indicates the TX FIFO Buffer Pointer
+ * | | |When CPU writes one byte into UART_DAT, TXPTR increases one
+ * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
+ * | | |The Maximum value shown in TXPTR is 15
+ * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0
+ * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15
+ * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)
+ * | | |This bit indicates TX FIFO empty or not.
+ * | | |0 = TX FIFO is not empty.
+ * | | |1 = TX FIFO is empty.
+ * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high
+ * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty).
+ * |[23] |TXFULL |Transmitter FIFO Full (Read Only)
+ * | | |This bit indicates TX FIFO full or not.
+ * | | |0 = TX FIFO is not full.
+ * | | |1 = TX FIFO is full.
+ * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
+ * |[24] |TXOVIF |TX Overflow Error Interrupt Flag
+ * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
+ * | | |0 = TX FIFO is not overflow.
+ * | | |1 = TX FIFO is overflow.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)
+ * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
+ * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted.
+ * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted.
+ * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
+ * |[29] |RXIDLE |RX Idle Status (Read Only)
+ * | | |This bit is set by hardware when RX is idle.
+ * | | |0 = RX is busy.
+ * | | |1 = RX is idle. (Default)
+ * |[31] |TXRXACT |TX and RX Active Status (Read Only)
+ * | | |This bit indicates TX and RX are active or inactive.
+ * | | |0 = TX and RX are inactive.
+ * | | |1 = TX and RX are active. (Default)
+ * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared
+ * | | |The UART controller can not transmit or receive data at this moment
+ * | | |Otherwise this bit is set.
+ * @var UART_T::INTSTS
+ * Offset: 0x1C UART Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDAIF |Receive Data Available Interrupt Flag
+ * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set
+ * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
+ * | | |0 = No RDA interrupt flag is generated.
+ * | | |1 = RDA interrupt flag is generated.
+ * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
+ * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag
+ * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register
+ * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
+ * | | |0 = No THRE interrupt flag is generated.
+ * | | |1 = THRE interrupt flag is generated.
+ * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
+ * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)
+ * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set)
+ * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+ * | | |0 = No RLS interrupt flag is generated.
+ * | | |1 = RLS interrupt flag is generated.
+ * | | |Note1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = '1') bit"
+ * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
+ * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+ * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
+ * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only)
+ * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1)
+ * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+ * | | |0 = No Modem interrupt flag is generated.
+ * | | |1 = Modem interrupt flag is generated.
+ * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
+ * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only)
+ * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])
+ * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
+ * | | |0 = No RX time-out interrupt flag is generated.
+ * | | |1 = RX time-out interrupt flag is generated.
+ * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+ * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)
+ * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)
+ * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct
+ * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
+ * | | |0 = No buffer error interrupt flag is generated.
+ * | | |1 = Buffer error interrupt flag is generated.
+ * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
+ * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only)
+ * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
+ * | | |0 = No UART wake-up interrupt flag is generated.
+ * | | |1 = UART wake-up interrupt flag is generated.
+ * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
+ * |[7] |LINIF |LIN Bus Interrupt Flag
+ * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] = 1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1]))
+ * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
+ * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+ * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+ * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]).
+ * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
+ * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
+ * | | |0 = No RDA interrupt is generated.
+ * | | |1 = RDA interrupt is generated.
+ * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only)
+ * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
+ * | | |0 = No THRE interrupt is generated.
+ * | | |1 = THRE interrupt is generated.
+ * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
+ * | | |0 = No RLS interrupt is generated.
+ * | | |1 = RLS interrupt is generated.
+ * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
+ * | | |0 = No Modem interrupt is generated.
+ * | | |1 = Modem interrupt is generated.
+ * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only)
+ * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
+ * | | |0 = No RX time-out interrupt is generated.
+ * | | |1 = RX time-out interrupt is generated.
+ * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
+ * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
+ * | | |0 = No buffer error interrupt is generated.
+ * | | |1 = Buffer error interrupt is generated.
+ * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only)
+ * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
+ * | | |0 = No UART wake-up interrupt is generated.
+ * | | |1 = UART wake-up interrupt is generated.
+ * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)
+ * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1.
+ * | | |0 = No LIN Bus interrupt is generated.
+ * | | |1 = The LIN Bus interrupt is generated.
+ * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only)
+ * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)
+ * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+ * | | |0 = No RLS interrupt flag is generated in PDMA mode.
+ * | | |1 = RLS interrupt flag is generated in PDMA mode.
+ * | | |Note1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = '1') bit".
+ * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+ * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
+ * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only)
+ * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1))
+ * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+ * | | |0 = No Modem interrupt flag is generated in PDMA mode.
+ * | | |1 = Modem interrupt flag is generated in PDMA mode.
+ * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
+ * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only)
+ * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])
+ * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated .
+ * | | |0 = No RX time-out interrupt flag is generated in PDMA mode.
+ * | | |1 = RX time-out interrupt flag is generated in PDMA mode.
+ * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+ * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only)
+ * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)
+ * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct
+ * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
+ * | | |0 = No buffer error interrupt flag is generated in PDMA mode.
+ * | | |1 = Buffer error interrupt flag is generated in PDMA mode.
+ * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
+ * |[22] |TXENDIF |Transmitter Empty Interrupt Flag
+ * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)
+ * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
+ * | | |0 = No transmitter empty interrupt flag is generated.
+ * | | |1 = Transmitter empty interrupt flag is generated.
+ * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
+ * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
+ * | | |0 = No RLS interrupt is generated in PDMA mode.
+ * | | |1 = RLS interrupt is generated in PDMA mode.
+ * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
+ * | | |0 = No Modem interrupt is generated in PDMA mode.
+ * | | |1 = Modem interrupt is generated in PDMA mode.
+ * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only)
+ * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
+ * | | |0 = No RX time-out interrupt is generated in PDMA mode.
+ * | | |1 = RX time-out interrupt is generated in PDMA mode.
+ * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only)
+ * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
+ * | | |0 = No buffer error interrupt is generated in PDMA mode.
+ * | | |1 = Buffer error interrupt is generated in PDMA mode.
+ * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only)
+ * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
+ * | | |0 = No Transmitter Empty interrupt is generated.
+ * | | |1 = Transmitter Empty interrupt is generated.
+ * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only)
+ * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
+ * | | |0 = No Auto-baud Rate interrupt is generated.
+ * | | |1 = The Auto-baud Rate interrupt is generated.
+ * @var UART_T::TOUT
+ * Offset: 0x20 UART Time-out Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TOIC |Time-out Interrupt Comparator
+ * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11])
+ * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled
+ * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4])
+ * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255
+ * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
+ * |[15:8] |DLY |TX Delay Time Value
+ * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit
+ * | | |The unit is bit time.
+ * @var UART_T::BAUD
+ * Offset: 0x24 UART Baud Rate Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |BRD |Baud Rate Divider
+ * | | |The field indicates the baud rate divider
+ * | | |This filed is used in baud rate calculation
+ * | | |The detail description is shown in Table 7.15-4.
+ * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1
+ * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2
+ * | | |The detail description is shown in Table 7.15-4
+ * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0
+ * | | |This bit is baud rate mode selection bit 0
+ * | | |UART provides three baud rate calculation modes
+ * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode
+ * | | |The detail description is shown in Table 7.15-4.
+ * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1
+ * | | |This bit is baud rate mode selection bit 1
+ * | | |UART provides three baud rate calculation modes
+ * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode
+ * | | |The detail description is shown in Table 7.15-4.
+ * | | |Note: In IrDA mode must be operated in mode 0.
+ * @var UART_T::IRDA
+ * Offset: 0x28 UART IrDA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit
+ * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
+ * | | |1 = IrDA Transmitter Enabled and Receiver Disabled.
+ * |[5] |TXINV |IrDA Inverse Transmitting Output Signal
+ * | | |0 = None inverse transmitting signal. (Default).
+ * | | |1 = Inverse transmitting output signal.
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
+ * |[6] |RXINV |IrDA Inverse Receive Input Signal
+ * | | |0 = None inverse receiving input signal.
+ * | | |1 = Inverse receiving input signal. (Default)
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
+ * @var UART_T::ALTCTL
+ * Offset: 0x2C UART Alternate Control/Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |BRKFL |UART LIN Break Field Length
+ * | | |This field indicates a 4-bit LIN TX break field count.
+ * | | |Note1: This break field length is BRKFL + 1.
+ * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
+ * |[6] |LINRXEN |LIN RX Enable Bit
+ * | | |0 = LIN RX mode Disabled.
+ * | | |1 = LIN RX mode Enabled.
+ * |[7] |LINTXEN |LIN TX Break Mode Enable Bit
+ * | | |0 = LIN TX Break mode Disabled.
+ * | | |1 = LIN TX Break mode Enabled.
+ * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
+ * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM)
+ * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
+ * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
+ * | | |Note: It cannot be active with RS-485_AAD operation mode.
+ * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)
+ * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
+ * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
+ * | | |Note: It cannot be active with RS-485_NMM operation mode.
+ * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD)
+ * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
+ * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
+ * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
+ * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit
+ * | | |This bit is used to enable RS-485 Address Detection mode.
+ * | | |0 = Address detection mode Disabled.
+ * | | |1 = Address detection mode Enabled.
+ * | | |Note: This bit is used for RS-485 any operation mode.
+ * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only)
+ * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
+ * | | |0 = No auto-baud rate interrupt flag is generated.
+ * | | |1 = Auto-baud rate interrupt flag is generated.
+ * | | |Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
+ * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit
+ * | | |0 = Auto-baud rate detect function Disabled.
+ * | | |1 = Auto-baud rate detect function Enabled.
+ * | | |Note : This bit is cleared automatically after auto-baud detection is finished.
+ * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length
+ * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
+ * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
+ * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
+ * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
+ * | | |Note : The calculation of bit number includes the START bit.
+ * |[31:24] |ADDRMV |Address Match Value
+ * | | |This field contains the RS-485 address match values.
+ * | | |Note: This field is used for RS-485 auto address detection mode.
+ * @var UART_T::FUNCSEL
+ * Offset: 0x30 UART Function Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |FUNCSEL |Function Select
+ * | | |00 = UART function.
+ * | | |01 = LIN function.
+ * | | |10 = IrDA function.
+ * | | |11 = RS-485 function.
+ * |[3] |TXRXDIS |TX and RX Disable Bit
+ * | | |Setting this bit can disable TX and RX.
+ * | | |0 = TX and RX Enabled.
+ * | | |1 = TX and RX Disabled.
+ * | | |Note: The TX and RX will not disable immediately when this bit is set
+ * | | |The TX and RX complete current task before disable TX and RX
+ * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
+ * @var UART_T::LINCTL
+ * Offset: 0x34 UART LIN Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SLVEN |LIN Slave Mode Enable Bit
+ * | | |0 = LIN slave mode Disabled.
+ * | | |1 = LIN slave mode Enabled.
+ * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit
+ * | | |0 = LIN slave header detection Disabled.
+ * | | |1 = LIN slave header detection Enabled.
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted
+ * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit
+ * | | |0 = LIN automatic resynchronization Disabled.
+ * | | |1 = LIN automatic resynchronization Enabled.
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
+ * | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization).
+ * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit
+ * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
+ * | | |1 = UART_BAUD is updated at the next received character
+ * | | |User must set the bit before checksum reception.
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode
+ * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared)
+ * | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization).
+ * |[4] |MUTE |LIN Mute Mode Enable Bit
+ * | | |0 = LIN mute mode Disabled.
+ * | | |1 = LIN mute mode Enabled.
+ * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 7.15.5.9 (LIN slave mode).
+ * |[8] |SENDH |LIN TX Send Header Enable Bit
+ * | | |The LIN TX header can be break field or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]).
+ * | | |0 = Send LIN TX header Disabled.
+ * | | |1 = Send LIN TX header Enabled.
+ * | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
+ * | | |Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
+ * |[9] |IDPEN |LIN ID Parity Enable Bit
+ * | | |0 = LIN frame ID parity Disabled.
+ * | | |1 = LIN frame ID parity Enabled.
+ * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked.
+ * | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10
+ * |[10] |BRKDETEN |LIN Break Detection Enable Bit
+ * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field
+ * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
+ * | | |0 = LIN break detection Disabled .
+ * | | |1 = LIN break detection Enabled.
+ * |[11] |LINRXOFF |LIN Receiver Disable Bit
+ * | | |If the receiver is enabled (LINRXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore.
+ * | | |0 = LIN receiver Enabled.
+ * | | |1 = LIN receiver Disabled.
+ * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
+ * |[12] |BITERREN |Bit Error Detect Enable Bit
+ * | | |0 = Bit error detection function Disabled.
+ * | | |1 = Bit error detection function Enabled.
+ * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted
+ * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * |[19:16] |BRKFL |LIN Break Field Length
+ * | | |This field indicates a 4-bit LIN TX break field count.
+ * | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
+ * | | |Note2: This break field length is BRKFL + 1.
+ * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
+ * |[21:20] |BSL |LIN Break/Sync Delimiter Length
+ * | | |00 = The LIN break/sync delimiter length is 1-bit time.
+ * | | |01 = The LIN break/sync delimiter length is 2-bit time.
+ * | | |10 = The LIN break/sync delimiter length is 3-bit time.
+ * | | |11 = The LIN break/sync delimiter length is 4-bit time.
+ * | | |Note: This bit used for LIN master to sending header field.
+ * |[23:22] |HSEL |LIN Header Select
+ * | | |00 = The LIN header includes 'break field'.
+ * | | |01 = The LIN header includes 'break field' and 'sync field'.
+ * | | |10 = The LIN header includes 'break field', 'sync field' and 'frame ID field'.
+ * | | |11 = Reserved.
+ * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1).
+ * |[31:24] |PID |LIN PID Bits
+ * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
+ * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
+ * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
+ * | | |Note2: This field can be used for LIN master mode or slave mode.
+ * @var UART_T::LINSTS
+ * Offset: 0x38 UART LIN Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SLVHDETF |LIN Slave Header Detection Flag
+ * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
+ * | | |0 = LIN header not detected.
+ * | | |1 = LIN header detected (break + sync + frame ID).
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+ * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not.
+ * |[1] |SLVHEF |LIN Slave Header Error Flag
+ * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it
+ * | | |The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field',
+ * | | |'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode',
+ * | | |'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'.
+ * | | |0 = LIN header error not detected.
+ * | | |1 = LIN header error detected.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and
+ * | | |enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+ * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag
+ * | | |This bit is set by hardware when receipted frame ID parity is not correct.
+ * | | |0 = No active.
+ * | | |1 = Receipted frame ID parity is not correct.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
+ * |[3] |SLVSYNCF |LIN Slave Sync Field
+ * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode
+ * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
+ * | | |0 = The current character is not at LIN sync state.
+ * | | |1 = The current character is at LIN sync state.
+ * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
+ * | | |Note2: This bit can be cleared by writing 1 to it.
+ * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
+ * |[8] |BRKDETF |LIN Break Detection Flag
+ * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
+ * | | |0 = LIN break not detected.
+ * | | |1 = LIN break detected.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1).
+ * |[9] |BITEF |Bit Error Detect Status Flag
+ * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.
+ * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * | | |0 = Bit error not detected.
+ * | | |1 = Bit error detected.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
+ * @var UART_T::BRCOMP
+ * Offset: 0x3C UART Baud Rate Compensation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |BRCOMP |Baud Rate Compensation Patten
+ * | | |These 9-bits are used to define the relative bit is compensated or not.
+ * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit.
+ * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease
+ * | | |0 = Positive (increase one module clock) compensation for each compensated bit.
+ * | | |1 = Negative (decrease one module clock) compensation for each compensated bit.
+ * @var UART_T::WKCTL
+ * Offset: 0x40 UART Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKCTSEN |nCTS Wake-up Enable Bit
+ * | | |0 = nCTS Wake-up system function Disabled.
+ * | | |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external.
+ * | | |nCTS change will wake-up system from Power-down mode.
+ * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit
+ * | | |0 = Incoming data wake-up system function Disabled.
+ * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,.
+ * | | |incoming data will wake-up system from Power-down mode.
+ * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit
+ * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled.
+ * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is.
+ * | | |in Power-down mode, Received Data FIFO reached threshold will wake-up system from
+ * | | |Power-down mode.
+ * |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit
+ * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled.
+ * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in.
+ * | | |Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.
+ * | | |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode
+ * | | |and ADDRDEN (UART_ALTCTL[15]) is set to 1.
+ * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
+ * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled.
+ * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the.
+ * | | |system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up
+ * | | |system from Power-down mode.
+ * | | |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
+ * @var UART_T::WKSTS
+ * Offset: 0x44 UART Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CTSWKF |nCTS Wake-up Flag
+ * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up.
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by nCTS wake-up.
+ * | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * |[1] |DATWKF |Incoming Data Wake-up Flag
+ * | | |This bit is set if chip wake-up from power-down state by data wake-up.
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up.
+ * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag
+ * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold
+ * | | |wake-up .
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up.
+ * | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag
+ * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up.
+ * | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag
+ * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out
+ * | | |wake-up.
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out.
+ * | | |wake-up.
+ * | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * @var UART_T::DWKCOMP
+ * Offset: 0x48 UART Incoming Data Wake-up Compensation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |STCOMP |Start Bit Compensation Value
+ * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.
+ * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
+ */
+ __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */
+ __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */
+ __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */
+ __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */
+ __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */
+ __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */
+ __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */
+ __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */
+ __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */
+ __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */
+ __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */
+ __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */
+ __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */
+ __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */
+ __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */
+ __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */
+ __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */
+ __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */
+ __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */
+
+} UART_T;
+
+/**
+ @addtogroup UART_CONST UART Bit Field Definition
+ Constant Definitions for UART Controller
+@{ */
+
+#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */
+#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */
+
+#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */
+#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */
+
+#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */
+#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */
+
+#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */
+#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */
+
+#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */
+#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */
+
+#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */
+#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */
+
+#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */
+#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */
+
+#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */
+#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */
+
+#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */
+#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */
+
+#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */
+#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */
+
+#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */
+#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */
+
+#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */
+#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */
+
+#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */
+#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */
+
+#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */
+#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */
+
+#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */
+#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */
+
+#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */
+#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */
+
+#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */
+#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */
+
+#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */
+#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */
+
+#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */
+#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */
+
+#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */
+#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */
+
+#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */
+#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */
+
+#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */
+#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */
+
+#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */
+#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */
+
+#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */
+#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */
+
+#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */
+#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */
+
+#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */
+#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */
+
+#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */
+#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */
+
+#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */
+#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */
+
+#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */
+#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */
+
+#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */
+#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */
+
+#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */
+#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */
+
+#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */
+#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */
+
+#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */
+#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */
+
+#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */
+#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */
+
+#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */
+#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */
+
+#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */
+#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */
+
+#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */
+#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */
+
+#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */
+#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */
+
+#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */
+#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */
+
+#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */
+#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */
+
+#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */
+#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */
+
+#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */
+#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */
+
+#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */
+#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */
+
+#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */
+#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */
+
+#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */
+#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */
+
+#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */
+#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */
+
+#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */
+#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */
+
+#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */
+#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */
+
+#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */
+#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */
+
+#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */
+#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */
+
+#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */
+#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */
+
+#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */
+#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */
+
+#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */
+#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */
+
+#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */
+#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */
+
+#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */
+#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */
+
+#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */
+#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */
+
+#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */
+#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */
+
+#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */
+#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */
+
+#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */
+#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */
+
+#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */
+#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */
+
+#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */
+#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */
+
+#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */
+#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */
+
+#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */
+#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */
+
+#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */
+#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */
+
+#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */
+#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */
+
+#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */
+#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */
+
+#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */
+#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */
+
+#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */
+#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */
+
+#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */
+#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */
+
+#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */
+#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */
+
+#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */
+#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */
+
+#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */
+#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */
+
+#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */
+#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */
+
+#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */
+#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */
+
+#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */
+#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */
+
+#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */
+#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */
+
+#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */
+#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */
+
+#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */
+#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */
+
+#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */
+#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */
+
+#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */
+#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */
+
+#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */
+#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */
+
+#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */
+#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */
+
+#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */
+#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */
+
+#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */
+#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */
+
+#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */
+#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */
+
+#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */
+#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */
+
+#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */
+#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */
+
+#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */
+#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */
+
+#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */
+#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */
+
+#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */
+#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */
+
+#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */
+#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */
+
+#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */
+#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */
+
+#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */
+#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */
+
+#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */
+#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */
+
+#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */
+#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */
+
+#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */
+#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */
+
+#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */
+#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */
+
+#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */
+#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */
+
+#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */
+#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */
+
+#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */
+#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */
+
+#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */
+#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */
+
+#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */
+#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */
+
+#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */
+#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */
+
+#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */
+#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */
+
+#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */
+#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */
+
+#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */
+#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */
+
+#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */
+#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */
+
+#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */
+#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */
+
+#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */
+#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */
+
+#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */
+#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */
+
+#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */
+#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */
+
+#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */
+#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */
+
+#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */
+#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */
+
+#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */
+#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */
+
+#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */
+#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */
+
+#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */
+#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */
+
+#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */
+#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */
+
+#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */
+#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */
+
+#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */
+#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */
+
+#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */
+#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */
+
+#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */
+#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */
+
+#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */
+#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */
+
+#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */
+#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */
+
+#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */
+#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */
+
+#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */
+#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */
+
+#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */
+#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */
+
+#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */
+#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */
+
+#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */
+#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */
+
+#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */
+#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */
+
+#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */
+#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */
+
+#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */
+#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */
+
+#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */
+#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */
+
+#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */
+#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */
+
+#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */
+#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */
+
+#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */
+#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */
+
+#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */
+#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */
+
+/**@}*/ /* UART_CONST */
+/**@}*/ /* end of UART register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __UART_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ui2c_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ui2c_reg.h
new file mode 100644
index 00000000000..04222bcf978
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ui2c_reg.h
@@ -0,0 +1,583 @@
+/**************************************************************************//**
+ * @file ui2c_reg.h
+ * @version V1.00
+ * @brief UI2C register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __UI2C_REG_H__
+#define __UI2C_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup UI2C I2C Mode of USCI Controller(UI2C)
+ Memory Mapped Structure for UI2C Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var UI2C_T::CTL
+ * Offset: 0x00 USCI Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |FUNMODE |Function Mode
+ * | | |This bit field selects the protocol for this USCI controller
+ * | | |Selecting a protocol that is not available or a reserved combination disables the USCI
+ * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
+ * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
+ * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
+ * | | |001 = The SPI protocol is selected.
+ * | | |010 = The UART protocol is selected.
+ * | | |100 = The I2C protocol is selected.
+ * | | |Note: Other bit combinations are reserved.
+ * @var UI2C_T::BRGEN
+ * Offset: 0x08 USCI Baud Rate Generator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RCLKSEL |Reference Clock Source Selection
+ * | | |This bit selects the source signal of reference clock (fREF_CLK).
+ * | | |0 = Peripheral device clock fPCLK.
+ * | | |1 = Reserved.
+ * |[1] |PTCLKSEL |Protocol Clock Source Selection
+ * | | |This bit selects the source signal of protocol clock (fPROT_CLK).
+ * | | |0 = Reference clock fREF_CLK.
+ * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
+ * |[3:2] |SPCLKSEL |Sample Clock Source Selection
+ * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
+ * | | |00 = fSAMP_CLK = fDIV_CLK.
+ * | | |01 = fSAMP_CLK = fPROT_CLK.
+ * | | |10 = fSAMP_CLK = fSCLK.
+ * | | |11 = fSAMP_CLK = fREF_CLK.
+ * |[4] |TMCNTEN |Time Measurement Counter Enable Bit
+ * | | |This bit enables the 10-bit timing measurement counter.
+ * | | |0 = Time measurement counter is Disabled.
+ * | | |1 = Time measurement counter is Enabled.
+ * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
+ * | | |0 = Time measurement counter with fPROT_CLK.
+ * | | |1 = Time measurement counter with fDIV_CLK.
+ * |[9:8] |PDSCNT |Pre-divider for Sample Counter
+ * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
+ * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
+ * |[14:10] |DSCNT |Denominator for Sample Counter
+ * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
+ * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
+ * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
+ * |[25:16] |CLKDIV |Clock Divider
+ * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
+ * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled
+ * | | |The revised value is the average bit time between bit 5 and bit 6
+ * | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate.
+ * @var UI2C_T::LINECTL
+ * Offset: 0x2C USCI Line Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LSB |LSB First Transmission Selection
+ * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
+ * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
+ * |[11:8] |DWIDTH |Word Length of Transmission
+ * | | |This bit field defines the data word length (amount of bits) for reception and transmission
+ * | | |The data word is always right-aligned in the data buffer
+ * | | |USCI support word length from 4 to 16 bits.
+ * | | |0x0: The data word contains 16 bits located at bit positions [15:0].
+ * | | |0x1: Reserved.
+ * | | |0x2: Reserved.
+ * | | |0x3: Reserved.
+ * | | |0x4: The data word contains 4 bits located at bit positions [3:0].
+ * | | |0x5: The data word contains 5 bits located at bit positions [4:0].
+ * | | |...
+ * | | |0xF: The data word contains 15 bits located at bit positions [14:0].
+ * | | |Note: In UART protocol, the length can be configured as 6~13 bits
+ * | | |And in I2C protocol, the length fixed as 8 bits.
+ * @var UI2C_T::TXDAT
+ * Offset: 0x30 USCI Transmit Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |TXDAT |Transmit Data
+ * | | |Software can use this bit field to write 16-bit transmit data for transmission.
+ * @var UI2C_T::RXDAT
+ * Offset: 0x34 USCI Receive Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RXDAT |Received Data
+ * | | |This bit field monitors the received data which stored in receive data buffer.
+ * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
+ * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]).
+ * @var UI2C_T::DEVADDR0
+ * Offset: 0x44 USCI Device Address Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |DEVADDR |Device Address
+ * | | |In I2C protocol, this bit field contains the programmed slave address
+ * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
+ * | | |Then the second address byte is also compared to DEVADDR[7:0].
+ * | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
+ * | | |Note 2: When software set 10'h000, the address can not be used.
+ * @var UI2C_T::DEVADDR1
+ * Offset: 0x48 USCI Device Address Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |DEVADDR |Device Address
+ * | | |In I2C protocol, this bit field contains the programmed slave address
+ * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
+ * | | |Then the second address byte is also compared to DEVADDR[7:0].
+ * | | |Note 1: The DEVADDR [9:7] must be set 3'000 when I2C operating in 7-bit address mode.
+ * | | |Note 2: When software set 10'h000, the address can not be used.
+ * @var UI2C_T::ADDRMSK0
+ * Offset: 0x4C USCI Device Address Mask Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |ADDRMSK |USCI Device Address Mask
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * | | |USCI support multiple address recognition with two address mask register
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * | | |Note: The wake-up function can not use address mask.
+ * @var UI2C_T::ADDRMSK1
+ * Offset: 0x50 USCI Device Address Mask Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |ADDRMSK |USCI Device Address Mask
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * | | |USCI support multiple address recognition with two address mask register
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * | | |Note: The wake-up function can not use address mask.
+ * @var UI2C_T::WKCTL
+ * Offset: 0x54 USCI Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Wake-up Enable Bit
+ * | | |0 = Wake-up function Disabled.
+ * | | |1 = Wake-up function Enabled.
+ * |[1] |WKADDREN |Wake-up Address Match Enable Bit
+ * | | |0 = The chip is woken up according data toggle.
+ * | | |1 = The chip is woken up according address match.
+ * @var UI2C_T::WKSTS
+ * Offset: 0x58 USCI Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKF |Wake-up Flag
+ * | | |When chip is woken up from Power-down mode, this bit is set to 1
+ * | | |Software can write 1 to clear this bit.
+ * @var UI2C_T::PROTCTL
+ * Offset: 0x5C USCI Protocol Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GCFUNC |General Call Function
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[1] |AA |Assert Acknowledge Control
+ * | | |When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
+ * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
+ * |[2] |STO |I2C STOP Control
+ * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically
+ * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (USCI_PROTSTS.ERRIF = 1).
+ * |[3] |STA |I2C START Control
+ * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
+ * |[4] |ADDR10EN |Address 10-bit Function Enable Bit
+ * | | |0 = Address match 10 bit function is disabled.
+ * | | |1 = Address match 10 bit function is enabled.
+ * |[5] |PTRG |I2C Protocol Trigger (Write Only)
+ * | | |When a new state is present in the USCI_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested
+ * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
+ * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead.
+ * | | |1 = I2C's stretch active.
+ * |[8] |SCLOUTEN |SCL Output Enable Bit
+ * | | |This bit enables monitor pulling SCL to low
+ * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
+ * | | |0 = SCL output will be forced high due to open drain mechanism.
+ * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt.
+ * |[9] |MONEN |Monitor Mode Enable Bit
+ * | | |This bit enables monitor mode
+ * | | |In monitor mode the SDA output will be put in high impedance mode
+ * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
+ * | | |0 = The monitor mode is disabled.
+ * | | |1 = The monitor mode is enabled.
+ * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
+ * |[25:16] |TOCNT |Time-out Clock Cycle
+ * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) when each interrupt flags are clear
+ * | | |The time-out is enable when TOCNT bigger than 0.
+ * | | |Note: The TMCNTSRC (USCI_BRGEN [5]) must be set zero on I2C mode.
+ * |[31] |PROTEN |I2C Protocol Enable Bit
+ * | | |0 = I2C Protocol disable.
+ * | | |1 = I2C Protocol enable.
+ * @var UI2C_T::PROTIEN
+ * Offset: 0x60 USCI Protocol Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TOIEN |Time-out Interrupt Enable Control
+ * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
+ * | | |0 = The time-out interrupt is disabled.
+ * | | |1 = The time-out interrupt is enabled.
+ * |[1] |STARIEN |Start Condition Received Interrupt Enable Control
+ * | | |This bit enables the generation of a protocol interrupt if a start condition is detected.
+ * | | |0 = The start condition interrupt is disabled.
+ * | | |1 = The start condition interrupt is enabled.
+ * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control
+ * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected.
+ * | | |0 = The stop condition interrupt is disabled.
+ * | | |1 = The stop condition interrupt is enabled.
+ * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control
+ * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.
+ * | | |0 = The non - acknowledge interrupt is disabled.
+ * | | |1 = The non - acknowledge interrupt is enabled.
+ * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control
+ * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
+ * | | |0 = The arbitration lost interrupt is disabled.
+ * | | |1 = The arbitration lost interrupt is enabled.
+ * |[5] |ERRIEN |Error Interrupt Enable Control
+ * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (USCI_PROTSTS [16])).
+ * | | |0 = The error interrupt is disabled.
+ * | | |1 = The error interrupt is enabled.
+ * |[6] |ACKIEN |Acknowledge Interrupt Enable Control
+ * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
+ * | | |0 = The acknowledge interrupt is disabled.
+ * | | |1 = The acknowledge interrupt is enabled.
+ * @var UI2C_T::PROTSTS
+ * Offset: 0x64 USCI Protocol Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5] |TOIF |Time-out Interrupt Flag
+ * | | |0 = A time-out interrupt status has not occurred.
+ * | | |1 = A time-out interrupt status has occurred.
+ * | | |Note: It is cleared by software writing one into this bit
+ * |[6] |ONBUSY |On Bus Busy
+ * | | |Indicates that a communication is in progress on the bus
+ * | | |It is set by hardware when a START condition is detected
+ * | | |It is cleared by hardware when a STOP condition is detected
+ * | | |0 = The bus is IDLE (both SCLK and SDA High).
+ * | | |1 = The bus is busy.
+ * |[8] |STARIF |Start Condition Received Interrupt Flag
+ * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode
+ * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode.
+ * | | |A protocol interrupt can be generated if USCI_PROTCTL.STARIEN = 1.
+ * | | |0 = A start condition has not yet been detected.
+ * | | |1 = A start condition has been detected.
+ * | | |It is cleared by software writing one into this bit
+ * |[9] |STORIF |Stop Condition Received Interrupt Flag
+ * | | |This bit indicates that a stop condition has been detected on the I2C bus lines
+ * | | |A protocol interrupt can be generated if USCI_PROTCTL.STORIEN = 1.
+ * | | |0 = A stop condition has not yet been detected.
+ * | | |1 = A stop condition has been detected.
+ * | | |It is cleared by software writing one into this bit
+ * | | |Note: This bit is set when slave RX mode.
+ * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag
+ * | | |This bit indicates that a non - acknowledge has been received in master mode
+ * | | |A protocol interrupt can be generated if USCI_PROTCTL.NACKIEN = 1.
+ * | | |0 = A non - acknowledge has not been received.
+ * | | |1 = A non - acknowledge has been received.
+ * | | |It is cleared by software writing one into this bit
+ * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag
+ * | | |This bit indicates that an arbitration has been lost
+ * | | |A protocol interrupt can be generated if USCI_PROTCTL.ARBLOIEN = 1.
+ * | | |0 = An arbitration has not been lost.
+ * | | |1 = An arbitration has been lost.
+ * | | |It is cleared by software writing one into this bit
+ * |[12] |ERRIF |Error Interrupt Flag
+ * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
+ * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit
+ * | | |A protocol interrupt can be generated if USCI_PROTCTL.ERRIEN = 1.
+ * | | |0 = An I2C error has not been detected.
+ * | | |1 = An I2C error has been detected.
+ * | | |It is cleared by software writing one into this bit
+ * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode.
+ * |[13] |ACKIF |Acknowledge Received Interrupt Flag
+ * | | |This bit indicates that an acknowledge has been received in master mode
+ * | | |A protocol interrupt can be generated if USCI_PROTCTL.ACKIEN = 1.
+ * | | |0 = An acknowledge has not been received.
+ * | | |1 = An acknowledge has been received.
+ * | | |It is cleared by software writing one into this bit
+ * |[14] |SLASEL |Slave Select Status
+ * | | |This bit indicates that this device has been selected as slave.
+ * | | |0 = The device is not selected as slave.
+ * | | |1 = The device is selected as slave.
+ * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
+ * |[15] |SLAREAD |Slave Read Request Status
+ * | | |This bit indicates that a slave read request has been detected.
+ * | | |0 = A slave R/W bit is 1 has not been detected.
+ * | | |1 = A slave R/W bit is 1 has been detected.
+ * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
+ * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
+ * | | |0 = The ACK bit cycle of address match frame isn't done.
+ * | | |1 = The ACK bit cycle of address match frame is done in power-down.
+ * | | |Note: This bit can't release when WKUPIF is set.
+ * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
+ * | | |0 = Write command be record on the address match wakeup frame.
+ * | | |1 = Read command be record on the address match wakeup frame.
+ * |[18] |BUSHANG |Bus Hang-up
+ * | | |This bit indicates bus hang-up status
+ * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK
+ * | | |The hang-up counter will count to overflow and set this bit when SDA is low
+ * | | |The counter will be reset by falling edge of SCL signal.
+ * | | |0 = The bus is normal status for transmission.
+ * | | |1 = The bus is hang-up status for transmission.
+ * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
+ * |[19] |ERRARBLO |Error Arbitration Lost
+ * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor
+ * | | |The I2C can send start condition when ERRARBLO is set
+ * | | |Thus this bit doesn't be cared on slave mode.
+ * | | |0 = The bus is normal status for transmission.
+ * | | |1 = The bus is error arbitration lost status for transmission.
+ * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
+ * @var UI2C_T::ADMAT
+ * Offset: 0x88 I2C Slave Match Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADMAT0 |USCI Address 0 Match Status Register
+ * | | |When address 0 is matched, hardware will inform which address used
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.
+ * |[1] |ADMAT1 |USCI Address 1 Match Status Register
+ * | | |When address 1 is matched, hardware will inform which address used
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.
+ * @var UI2C_T::TMCTL
+ * Offset: 0x8C I2C Timing Configure Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |STCTL |Setup Time Configure Control Register
+ * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.
+ * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK.
+ * |[24:16] |HTCTL |Hold Time Configure Control Register
+ * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in
+ * | | |transmission mode.
+ * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[8];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
+ __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
+ __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */
+ __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */
+ __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */
+ __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */
+ __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
+ __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
+ __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
+ __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
+ __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[8];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */
+ __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */
+
+} UI2C_T;
+
+/**
+ @addtogroup UI2C_CONST UI2C Bit Field Definition
+ Constant Definitions for UI2C Controller
+@{ */
+
+#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */
+#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */
+
+#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */
+#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */
+
+#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */
+#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */
+
+#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */
+#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */
+
+#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */
+#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */
+
+#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */
+#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */
+
+#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */
+#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */
+
+#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */
+#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */
+
+#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */
+#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */
+
+#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */
+#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */
+
+#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */
+#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */
+
+#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */
+#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */
+
+#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */
+#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */
+
+#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */
+#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */
+
+#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */
+#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */
+
+#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */
+#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */
+
+#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */
+#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */
+
+#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */
+#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */
+
+#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */
+#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */
+
+#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */
+#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */
+
+#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */
+#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */
+
+#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */
+#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */
+
+#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */
+#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */
+
+#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */
+#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */
+
+#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */
+#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */
+
+#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */
+#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */
+
+#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */
+#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */
+
+#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */
+#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */
+
+#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */
+#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */
+
+#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */
+#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */
+
+#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */
+#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */
+
+#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */
+#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */
+
+#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */
+#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */
+
+#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */
+#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */
+
+#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */
+#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */
+
+#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */
+#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */
+
+#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */
+#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */
+
+#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */
+#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */
+
+#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */
+#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */
+
+#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */
+#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */
+
+#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */
+#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */
+
+#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */
+#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */
+
+#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */
+#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */
+
+#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */
+#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */
+
+#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */
+#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */
+
+#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */
+#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */
+
+#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */
+#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */
+
+#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */
+#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */
+
+#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */
+#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */
+
+#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */
+#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */
+
+#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */
+#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */
+
+#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */
+#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */
+
+#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */
+#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */
+
+#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */
+#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */
+
+#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */
+#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */
+
+/**@}*/ /* UI2C_CONST */
+/**@}*/ /* end of UI2C register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __UI2C_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbd_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbd_reg.h
new file mode 100644
index 00000000000..5638db70e6e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbd_reg.h
@@ -0,0 +1,649 @@
+/**************************************************************************//**
+ * @file usbd_reg.h
+ * @version V1.00
+ * @brief USBD register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __USBD_REG_H__
+#define __USBD_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup USBD USB Device Controller(USBD)
+ Memory Mapped Structure for USBD Controller
+@{ */
+
+typedef struct
+{
+
+ /**
+ * @var USBD_EP_T::BUFSEG
+ * Offset: 0x000 Endpoint n Buffer Segmentation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:3] |BUFSEG |Endpoint Buffer Segmentation
+ * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
+ * | | |USBD_SRAM address + { BUFSEG, 3'b000}
+ * | | |Where the USBD_SRAM address = USBD_BA+0x100h.
+ * | | |Refer to the section 7.29.5.7 for the endpoint SRAM structure and its description.
+ * @var USBD_EP_T::MXPLD
+ * Offset: 0x004 Endpoint n Maximal Payload Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |MXPLD |Maximal Payload
+ * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)
+ * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
+ * | | |(1) When the register is written by CPU,
+ * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
+ * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
+ * | | |(2) When the register is read by CPU,
+ * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
+ * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
+ * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
+ * @var USBD_EP_T::CFG
+ * Offset: 0x008 Endpoint n Configuration Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |EPNUM |Endpoint Number
+ * | | |These bits are used to define the endpoint number of the current endpoint
+ * |[4] |ISOCH |Isochronous Endpoint
+ * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
+ * | | |0 = No Isochronous endpoint.
+ * | | |1 = Isochronous endpoint.
+ * |[6:5] |STATE |Endpoint STATE
+ * | | |00 = Endpoint is Disabled.
+ * | | |01 = Out endpoint.
+ * | | |10 = IN endpoint.
+ * | | |11 = Undefined.
+ * |[7] |DSQSYNC |Data Sequence Synchronization
+ * | | |0 = DATA0 PID.
+ * | | |1 = DATA1 PID.
+ * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction
+ * | | |hardware will toggle automatically in IN token base on the bit.
+ * |[9] |CSTALL |Clear STALL Response
+ * | | |0 = Disable the device to clear the STALL handshake in setup stage.
+ * | | |1 = Clear the device to response STALL handshake in setup stage.
+ * @var USBD_EP_T::CFGP
+ * Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CLRRDY |Clear Ready
+ * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data
+ * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
+ * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
+ * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
+ * | | |This bit is write 1 only and is always 0 when it is read back.
+ * |[1] |SSTALL |Set STALL
+ * | | |0 = Disable the device to response STALL.
+ * | | |1 = Set the device to respond STALL automatically.
+ */
+ __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint n Buffer Segmentation Register */
+ __IO uint32_t MXPLD; /*!< [0x0004] Endpoint n Maximal Payload Register */
+ __IO uint32_t CFG; /*!< [0x0008] Endpoint n Configuration Register */
+ __IO uint32_t CFGP; /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register */
+
+} USBD_EP_T;
+
+typedef struct
+{
+
+
+ /**
+ * @var USBD_T::INTEN
+ * Offset: 0x00 USB Device Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSIEN |Bus Event Interrupt Enable Bit
+ * | | |0 = BUS event interrupt Disabled.
+ * | | |1 = BUS event interrupt Enabled.
+ * |[1] |USBIEN |USB Event Interrupt Enable Bit
+ * | | |0 = USB event interrupt Disabled.
+ * | | |1 = USB event interrupt Enabled.
+ * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit
+ * | | |0 = VBUS detection Interrupt Disabled.
+ * | | |1 = VBUS detection Interrupt Enabled.
+ * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit
+ * | | |0 = No-event-wake-up Interrupt Disabled.
+ * | | |1 = No-event-wake-up Interrupt Enabled.
+ * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit
+ * | | |0 = SOF Interrupt Disabled.
+ * | | |1 = SOF Interrupt Enabled.
+ * |[8] |WKEN |Wake-up Function Enable Bit
+ * | | |0 = USB wake-up function Disabled.
+ * | | |1 = USB wake-up function Enabled.
+ * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token
+ * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted.
+ * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token.
+ * @var USBD_T::INTSTS
+ * Offset: 0x04 USB Device Interrupt Event Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSIF |BUS Interrupt Status
+ * | | |The BUS event means that there is one of the suspense or the resume function in the bus.
+ * | | |0 = No BUS event occurred.
+ * | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0].
+ * |[1] |USBIF |USB Event Interrupt Status
+ * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
+ * | | |0 = No USB event occurred.
+ * | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]).
+ * |[2] |VBDETIF |VBUS Detection Interrupt Status
+ * | | |0 = There is not attached/detached event in the USB.
+ * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2].
+ * |[3] |NEVWKIF |No-event-wake-up Interrupt Status
+ * | | |0 = NEVWK event does not occur.
+ * | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3].
+ * |[4] |SOFIF |Start of Frame Interrupt Status
+ * | | |0 = SOF event does not occur.
+ * | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4].
+ * |[16] |EPEVT0 |Endpoint 0's USB Event Status
+ * | | |0 = No event occurred in endpoint 0.
+ * | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1].
+ * |[17] |EPEVT1 |Endpoint 1's USB Event Status
+ * | | |0 = No event occurred in endpoint 1.
+ * | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1].
+ * |[18] |EPEVT2 |Endpoint 2's USB Event Status
+ * | | |0 = No event occurred in endpoint 2.
+ * | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
+ * |[19] |EPEVT3 |Endpoint 3's USB Event Status
+ * | | |0 = No event occurred in endpoint 3.
+ * | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1].
+ * |[20] |EPEVT4 |Endpoint 4's USB Event Status
+ * | | |0 = No event occurred in endpoint 4.
+ * | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1].
+ * |[21] |EPEVT5 |Endpoint 5's USB Event Status
+ * | | |0 = No event occurred in endpoint 5.
+ * | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1].
+ * |[22] |EPEVT6 |Endpoint 6's USB Event Status
+ * | | |0 = No event occurred in endpoint 6.
+ * | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
+ * |[23] |EPEVT7 |Endpoint 7's USB Event Status
+ * | | |0 = No event occurred in endpoint 7.
+ * | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1].
+ * |[24] |EPEVT8 |Endpoint 8's USB Event Status
+ * | | |0 = No event occurred in endpoint 8.
+ * | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1].
+ * |[25] |EPEVT9 |Endpoint 9's USB Event Status
+ * | | |0 = No event occurred in endpoint 9.
+ * | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1].
+ * |[26] |EPEVT10 |Endpoint 10's USB Event Status
+ * | | |0 = No event occurred in endpoint 10.
+ * | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1].
+ * |[27] |EPEVT11 |Endpoint 11's USB Event Status
+ * | | |0 = No event occurred in endpoint 11.
+ * | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1].
+ * |[31] |SETUP |Setup Event Status
+ * | | |0 = No Setup event.
+ * | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31].
+ * @var USBD_T::FADDR
+ * Offset: 0x08 USB Device Function Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |FADDR |USB Device Function Address
+ * @var USBD_T::EPSTS
+ * Offset: 0x0C USB Device Endpoint Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7] |OV |Overrun
+ * | | |It indicates that the received data is over the maximum payload number or not.
+ * | | |0 = No overrun.
+ * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
+ * @var USBD_T::ATTR
+ * Offset: 0x10 USB Device Bus Status and Attribution Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |USBRST |USB Reset Status
+ * | | |0 = Bus no reset.
+ * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us.
+ * | | |Note: This bit is read only.
+ * |[1] |SUSPEND |Suspend Status
+ * | | |0 = Bus no suspend.
+ * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
+ * | | |Note: This bit is read only.
+ * |[2] |RESUME |Resume Status
+ * | | |0 = No bus resume.
+ * | | |1 = Resume from suspend.
+ * | | |Note: This bit is read only.
+ * |[3] |TOUT |Time-out Status
+ * | | |0 = No time-out.
+ * | | |1 = No Bus response more than 18 bits time.
+ * | | |Note: This bit is read only.
+ * |[4] |PHYEN |PHY Transceiver Function Enable Bit
+ * | | |0 = PHY transceiver function Disabled.
+ * | | |1 = PHY transceiver function Enabled.
+ * |[5] |RWAKEUP |Remote Wake-up
+ * | | |0 = Release the USB bus from K state.
+ * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up.
+ * |[7] |USBEN |USB Controller Enable Bit
+ * | | |0 = USB Controller Disabled.
+ * | | |1 = USB Controller Enabled.
+ * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit
+ * | | |0 = Pull-up resistor in USB_D+ bus Disabled.
+ * | | |1 = Pull-up resistor in USB_D+ bus Active.
+ * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
+ * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
+ * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
+ * |[11] |LPMACK |LPM Token Acknowledge Enable Bit
+ * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively.
+ * | | |0= the valid LPM Token will be NYET.
+ * | | |1= the valid LPM Token will be ACK.
+ * |[12] |L1SUSPEND |LPM L1 Suspend
+ * | | |0 = Bus no L1 state suspend.
+ * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged.
+ * | | |Note: This bit is read only.
+ * |[13] |L1RESUME |LPM L1 Resume
+ * | | |0 = Bus no LPM L1 state resume.
+ * | | |1 = LPM L1 state Resume from LPM L1 state suspend.
+ * | | |Note: This bit is read only.
+ * @var USBD_T::VBUSDET
+ * Offset: 0x14 USB Device VBUS Detection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |VBUSDET |Device VBUS Detection
+ * | | |0 = Controller is not attached to the USB host.
+ * | | |1 = Controller is attached to the USB host.
+ * @var USBD_T::STBUFSEG
+ * Offset: 0x18 SETUP Token Buffer Segmentation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation
+ * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
+ * | | |USBD_SRAM address + {STBUFSEG, 3'b000}
+ * | | |Where the USBD_SRAM address = USBD_BA+0x100h.
+ * | | |Note: It is used for SETUP token only.
+ * @var USBD_T::EPSTS0
+ * Offset: 0x20 USB Device Endpoint Status Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[03:00] |EPSTS0 |Endpoint 0 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * |[07:04] |EPSTS1 |Endpoint 1 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * |[11:08] |EPSTS2 |Endpoint 2 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * |[15:12] |EPSTS3 |Endpoint 3 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * |[19:16] |EPSTS4 |Endpoint 4 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * |[23:20] |EPSTS5 |Endpoint 5 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * |[27:24] |EPSTS6 |Endpoint 6 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * |[31:28] |EPSTS7 |Endpoint 7 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * @var USBD_T::EPSTS1
+ * Offset: 0x24 USB Device Endpoint Status Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |EPSTS8 |Endpoint 8 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * |[7:4] |EPSTS9 |Endpoint 9 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * |[11:8] |EPSTS10 |Endpoint 10 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * |[15:12] |EPSTS11 |Endpoint 11 Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |0000 = In ACK.
+ * | | |0001 = In NAK.
+ * | | |0010 = Out Packet Data0 ACK.
+ * | | |0011 = Setup ACK.
+ * | | |0110 = Out Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ * @var USBD_T::LPMATTR
+ * Offset: 0x88 USB LPM Attribution Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |LPMLINKSTS|LPM Link State
+ * | | |These bits contain the bLinkState received with last ACK LPM Token
+ * |[7:4] |LPMBESL |LPM Best Effort Service Latency
+ * | | |These bits contain the BESL value received with last ACK LPM Token
+ * |[8] |LPMRWAKUP |LPM Remote Wakeup
+ * | | |This bit contains the bRemoteWake value received with last ACK LPM Token
+ * @var USBD_T::FN
+ * Offset: 0x8C USB Frame number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[10:0] |FN |Frame Number
+ * | | |These bits contain the 11-bits frame number in the last received SOF packet.
+ * @var USBD_T::SE0
+ * Offset: 0x90 USB Device Drive SE0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SE0 |Drive Single Ended Zero in USB Bus
+ * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
+ * | | |0 = Normal operation.
+ * | | |1 = Force USB PHY transceiver to drive SE0.
+ */
+
+ __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */
+ __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */
+ __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */
+ __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */
+ __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */
+ __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */
+ __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */
+ __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[24];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */
+ __I uint32_t FN; /*!< [0x008c] USB Frame number Register */
+ __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[283];
+ /// @endcond //HIDDEN_SYMBOLS
+ USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */
+
+} USBD_T;
+
+
+/**
+ @addtogroup USBD_CONST USBD Bit Field Definition
+ Constant Definitions for USBD Controller
+@{ */
+
+#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
+#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
+
+#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
+#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
+
+#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
+#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
+
+#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
+#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
+
+#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */
+#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */
+
+#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
+#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
+
+#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
+#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
+
+#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
+#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
+
+#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
+#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
+
+#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
+#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
+
+#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
+#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
+
+#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */
+#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */
+
+#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
+#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
+
+#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
+#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
+
+#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
+#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
+
+#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
+#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
+
+#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
+#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
+
+#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
+#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
+
+#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
+#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
+
+#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
+#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
+
+#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */
+#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */
+
+#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */
+#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */
+
+#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */
+#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */
+
+#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */
+#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */
+
+#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
+#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
+
+#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
+#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
+
+#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
+#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
+
+#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
+#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
+
+#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
+#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
+
+#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
+#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
+
+#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
+#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
+
+#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
+#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
+
+#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
+#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
+
+#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
+#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
+
+#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
+#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
+
+#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
+#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
+
+#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */
+#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */
+
+#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */
+#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */
+
+#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */
+#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */
+
+#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
+#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
+
+#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
+#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
+
+#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */
+#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */
+
+#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */
+#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */
+
+#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */
+#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */
+
+#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */
+#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */
+
+#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */
+#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */
+
+#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */
+#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */
+
+#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */
+#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */
+
+#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */
+#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */
+
+#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */
+#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */
+
+#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */
+#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */
+
+#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */
+#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */
+
+#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */
+#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */
+
+#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */
+#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */
+
+#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */
+#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */
+
+#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */
+#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */
+
+#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */
+#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */
+
+#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
+#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
+
+#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
+#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
+
+#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
+#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
+
+#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
+#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
+
+#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
+#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
+
+#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
+#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
+
+#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
+#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
+
+#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
+#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
+
+#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
+#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
+
+#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
+#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
+
+/**@}*/ /* USBD_CONST */
+/**@}*/ /* end of USBD register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __USBD_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbh_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbh_reg.h
new file mode 100644
index 00000000000..01dcffeaf70
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbh_reg.h
@@ -0,0 +1,797 @@
+/**************************************************************************//**
+ * @file usbh_reg.h
+ * @version V1.00
+ * @brief USBH register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __USBH_REG_H__
+#define __USBH_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup USBH USB Host Controller(USBH)
+ Memory Mapped Structure for USBH Controller
+@{ */
+
+typedef struct
+{
+
+ /**
+ * @var USBH_T::HcRevision
+ * Offset: 0x00 Host Controller Revision Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |REV |Revision Number
+ * | | |Indicates the Open HCI Specification revision number implemented by the Hardware
+ * | | |Host Controller supports 1.1 specification.
+ * | | |(X.Y = XYh).
+ * @var USBH_T::HcControl
+ * Offset: 0x04 Host Controller Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |CBSR |Control Bulk Service Ratio
+ * | | |This specifies the service ratio between Control and Bulk EDs
+ * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs
+ * | | |The internal count will be retained when crossing the frame boundary
+ * | | |In case of reset, HCD is responsible for restoring this
+ * | | |Value.
+ * | | |00 = Number of Control EDs over Bulk EDs served is 1:1.
+ * | | |01 = Number of Control EDs over Bulk EDs served is 2:1.
+ * | | |10 = Number of Control EDs over Bulk EDs served is 3:1.
+ * | | |11 = Number of Control EDs over Bulk EDs served is 4:1.
+ * |[2] |PLE |Periodic List Enable Bit
+ * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list
+ * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
+ * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled.
+ * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled.
+ * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
+ * |[3] |IE |Isochronous List Enable Bit
+ * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list
+ * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
+ * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled.
+ * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too.
+ * |[4] |CLE |Control List Enable Bit
+ * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled.
+ * | | |1 = Processing of the Control list in the next frame Enabled.
+ * |[5] |BLE |Bulk List Enable Bit
+ * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled.
+ * | | |1 = Processing of the Bulk list in the next frame Enabled.
+ * |[7:6] |HCFS |Host Controller Functional State
+ * | | |This field sets the Host Controller state
+ * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port
+ * | | |States are:
+ * | | |00 = USBSUSPEND.
+ * | | |01 = USBOPERATIONAL.
+ * | | |10 = USBRESUME.
+ * | | |11 = USBRESET.
+ * @var USBH_T::HcCommandStatus
+ * Offset: 0x08 Host Controller Command Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HCR |Host Controller Reset
+ * | | |This bit is set to initiate the software reset of Host Controller
+ * | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
+ * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
+ * | | |0 = Host Controller is not in software reset state.
+ * | | |1 = Host Controller is in software reset state.
+ * |[1] |CLF |Control List Filled
+ * | | |Set high to indicate there is an active TD on the Control List
+ * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
+ * | | |0 = No active TD found or Host Controller begins to process the head of the Control list.
+ * | | |1 = An active TD added or found on the Control list.
+ * |[2] |BLF |Bulk List Filled
+ * | | |Set high to indicate there is an active TD on the Bulk list
+ * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
+ * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
+ * | | |1 = An active TD added or found on the Bulk list.
+ * |[17:16] |SOC |Schedule Overrun Count
+ * | | |These bits are incremented on each scheduling overrun error
+ * | | |It is initialized to 00b and wraps around at 11b
+ * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
+ * @var USBH_T::HcInterruptStatus
+ * Offset: 0x0C Host Controller Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SO |Scheduling Overrun
+ * | | |Set when the List Processor determines a Schedule Overrun has occurred.
+ * | | |0 = Schedule Overrun didn't occur.
+ * | | |1 = Schedule Overrun has occurred.
+ * |[1] |WDH |Write Back Done Head
+ * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead
+ * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
+ * | | |0 =.Host Controller didn't update HccaDoneHead.
+ * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
+ * |[2] |SF |Start of Frame
+ * | | |Set when the Frame Management functional block signals a 'Start of Frame' event
+ * | | |Host Control generates a SOF token at the same time.
+ * | | |0 =.Not the start of a frame.
+ * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
+ * |[3] |RD |Resume Detected
+ * | | |Set when Host Controller detects resume signaling on a downstream port.
+ * | | |0 = No resume signaling detected on a downstream port.
+ * | | |1 = Resume signaling detected on a downstream port.
+ * |[5] |FNO |Frame Number Overflow
+ * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+ * | | |0 = The bit 15 of Frame Number didn't change.
+ * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+ * |[6] |RHSC |Root Hub Status Change
+ * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed.
+ * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change.
+ * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed.
+ * @var USBH_T::HcInterruptEnable
+ * Offset: 0x10 Host Controller Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SO |Scheduling Overrun Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+ * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+ * |[1] |WDH |Write Back Done Head Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+ * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+ * |[2] |SF |Start of Frame Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+ * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+ * |[3] |RD |Resume Detected Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+ * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+ * |[5] |FNO |Frame Number Overflow Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+ * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+ * |[6] |RHSC |Root Hub Status Change Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+ * |[31] |MIE |Master Interrupt Enable Bit
+ * | | |This bit is a global interrupt enable
+ * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+ * @var USBH_T::HcInterruptDisable
+ * Offset: 0x14 Host Controller Interrupt Disable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SO |Scheduling Overrun Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+ * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+ * |[1] |WDH |Write Back Done Head Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+ * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+ * |[2] |SF |Start of Frame Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+ * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+ * |[3] |RD |Resume Detected Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+ * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+ * |[5] |FNO |Frame Number Overflow Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+ * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+ * |[6] |RHSC |Root Hub Status Change Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+ * |[31] |MIE |Master Interrupt Disable Bit
+ * | | |Global interrupt disable. Writing '1' to disable all interrupts.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+ * @var USBH_T::HcHCCA
+ * Offset: 0x18 Host Controller Communication Area Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:8] |HCCA |Host Controller Communication Area
+ * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
+ * @var USBH_T::HcPeriodCurrentED
+ * Offset: 0x1C Host Controller Period Current ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |PCED |Periodic Current ED
+ * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
+ * @var USBH_T::HcControlHeadED
+ * Offset: 0x20 Host Controller Control Head ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |CHED |Control Head ED
+ * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
+ * @var USBH_T::HcControlCurrentED
+ * Offset: 0x24 Host Controller Control Current ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |CCED |Control Current Head ED
+ * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
+ * @var USBH_T::HcBulkHeadED
+ * Offset: 0x28 Host Controller Bulk Head ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |BHED |Bulk Head ED
+ * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
+ * @var USBH_T::HcBulkCurrentED
+ * Offset: 0x2C Host Controller Bulk Current ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |BCED |Bulk Current Head ED
+ * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.
+ * @var USBH_T::HcDoneHead
+ * Offset: 0x30 Host Controller Done Head Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |DH |Done Head
+ * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
+ * @var USBH_T::HcFmInterval
+ * Offset: 0x34 Host Controller Frame Interval Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[13:0] |FI |Frame Interval
+ * | | |This field specifies the length of a frame as (bit times - 1)
+ * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
+ * |[30:16] |FSMPS |FS Largest Data Packet
+ * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
+ * |[31] |FIT |Frame Interval Toggle
+ * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
+ * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]).
+ * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]).
+ * @var USBH_T::HcFmRemaining
+ * Offset: 0x38 Host Controller Frame Remaining Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[13:0] |FR |Frame Remaining
+ * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period
+ * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval
+ * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
+ * |[31] |FRT |Frame Remaining Toggle
+ * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
+ * @var USBH_T::HcFmNumber
+ * Offset: 0x3C Host Controller Frame Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FN |Frame Number
+ * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])
+ * | | |The count rolls over from 'FFFFh' to '0h.'
+ * @var USBH_T::HcPeriodicStart
+ * Offset: 0x40 Host Controller Periodic Start Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[13:0] |PS |Periodic Start
+ * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
+ * @var USBH_T::HcLSThreshold
+ * Offset: 0x44 Host Controller Low-speed Threshold Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |LST |Low-speed Threshold
+ * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction
+ * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field
+ * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
+ * @var USBH_T::HcRhDescriptorA
+ * Offset: 0x48 Host Controller Root Hub Descriptor A Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |NDP |Number Downstream Ports
+ * | | |USB host control supports two downstream ports and only one port is available in this series of chip.
+ * |[8] |PSM |Power Switching Mode
+ * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.
+ * | | |0 = Global Switching.
+ * | | |1 = Individual Switching.
+ * |[11] |OCPM |over Current Protection Mode
+ * | | |This bit describes how the over current status for the Root Hub ports reported
+ * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.
+ * | | |0 = Global Over current.
+ * | | |1 = Individual Over current.
+ * |[12] |NOCP |No over Current Protection
+ * | | |This bit describes how the over current status for the Root Hub ports reported.
+ * | | |0 = Over current status is reported.
+ * | | |1 = Over current status is not reported.
+ * @var USBH_T::HcRhDescriptorB
+ * Offset: 0x4C Host Controller Root Hub Descriptor B Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:16] |PPCM |Port Power Control Mask
+ * | | |Global power switching
+ * | | |This field is only valid if PowerSwitchingMode is set (individual port switching)
+ * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower)
+ * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
+ * | | |0 = Port power controlled by global power switching.
+ * | | |1 = Port power controlled by port power switching.
+ * | | |Note: PPCM[15:2] and PPCM[0] are reserved.
+ * @var USBH_T::HcRhStatus
+ * Offset: 0x50 Host Controller Root Hub Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LPS |Clear Global Power
+ * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power.
+ * | | |This bit always read as zero.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Clear global power.
+ * |[1] |OCI |over Current Indicator
+ * | | |This bit reflects the state of the over current status pin
+ * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
+ * | | |0 = No over current condition.
+ * | | |1 = Over current condition.
+ * |[15] |DRWE |Device Remote Wakeup Enable Bit
+ * | | |This bit controls if port's Connect Status Change as a remote wake-up event.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Connect Status Change as a remote wake-up event Enabled.
+ * | | |Read Operation:
+ * | | |0 = Connect Status Change as a remote wake-up event Disabled.
+ * | | |1 = Connect Status Change as a remote wake-up event Enabled.
+ * |[16] |LPSC |Set Global Power
+ * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports.
+ * | | |This bit always read as zero.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set global power.
+ * |[17] |OCIC |over Current Indicator Change
+ * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = OCI (HcRhStatus[1]) didn't change.
+ * | | |1 = OCI (HcRhStatus[1]) change.
+ * |[31] |CRWE |Clear Remote Wake-up Enable Bit
+ * | | |This bit is use to clear DRWE (HcRhStatus[15]).
+ * | | |This bit always read as zero.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Clear DRWE (HcRhStatus[15]).
+ * @var USBH_T::HcRhPortStatus[2]
+ * Offset: 0x54 Host Controller Root Hub Port Status
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CCS |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Clear port enable.
+ * | | |Read Operation:
+ * | | |0 = No device connected.
+ * | | |1 = Device connected.
+ * |[1] |PES |Port Enable Status
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set port enable.
+ * | | |Read Operation:
+ * | | |0 = Port Disabled.
+ * | | |1 = Port Enabled.
+ * |[2] |PSS |Port Suspend Status
+ * | | |This bit indicates the port is suspended
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set port suspend.
+ * | | |Read Operation:
+ * | | |0 = Port is not suspended.
+ * | | |1 = Port is selectively suspended.
+ * |[3] |POCI |Port over Current Indicator (Read) or Clear Port Suspend (Write)
+ * | | |This bit reflects the state of the over current status pin dedicated to this port
+ * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.
+ * | | |This bit is also used to initiate the selective result sequence for the port.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Clear port suspend.
+ * | | |Read Operation:
+ * | | |0 = No over current condition.
+ * | | |1 = Over current condition.
+ * |[4] |PRS |Port Reset Status
+ * | | |This bit reflects the reset state of the port.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set port reset.
+ * | | |Read Operation
+ * | | |0 = Port reset signal is not active.
+ * | | |1 = Port reset signal is active.
+ * |[8] |PPS |Port Power Status
+ * | | |This bit reflects the power state of the port regardless of the power switching mode.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Port Power Enabled.
+ * | | |Read Operation:
+ * | | |0 = Port power is Disabled.
+ * | | |1 = Port power is Enabled.
+ * |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write)
+ * | | |This bit defines the speed (and bud idle) of the attached device
+ * | | |It is only valid when CCS (HcRhPortStatus1[0]) is set.
+ * | | |This bit is also used to clear port power.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Clear PPS (HcRhPortStatus1[8]).
+ * | | |Read Operation:
+ * | | |0 = Full Speed device.
+ * | | |1 = Low-speed device.
+ * |[16] |CSC |Connect Status Change
+ * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change).
+ * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed).
+ * |[17] |PESC |Port Enable Status Change
+ * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = PES (HcRhPortStatus1[1]) didn't change.
+ * | | |1 = PES (HcRhPortStatus1[1]) changed.
+ * |[18] |PSSC |Port Suspend Status Change
+ * | | |This bit indicates the completion of the selective resume sequence for the port.
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = Port resume is not completed.
+ * | | |1 = Port resume completed.
+ * |[19] |OCIC |Port over Current Indicator Change
+ * | | |This bit is set when POCI (HcRhPortStatus1[3]) changes.
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = POCI (HcRhPortStatus1[3]) didn't change.
+ * | | |1 = POCI (HcRhPortStatus1[3]) changes.
+ * |[20] |PRSC |Port Reset Status Change
+ * | | |This bit indicates that the port reset signal has completed.
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = Port reset is not complete.
+ * | | |1 = Port reset is complete.
+ * @var USBH_T::HcPhyControl
+ * Offset: 0x200 Host Controller PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[27] |STBYEN |USB Transceiver Standby Enable Bit
+ * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
+ * | | |0 = The USB transceiver would never enter the standby mode.
+ * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
+ * @var USBH_T::HcMiscControl
+ * Offset: 0x204 Host Controller Miscellaneous Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |ABORT |AHB Bus ERROR Response
+ * | | |This bit indicates there is an ERROR response received in AHB bus.
+ * | | |0 = No ERROR response received.
+ * | | |1 = ERROR response received.
+ * |[3] |OCAL |over Current Active Low
+ * | | |This bit controls the polarity of over current flag from external power IC.
+ * | | |0 = Over current flag is high active.
+ * | | |1 = Over current flag is low active.
+ * |[16] |DPRT1 |Disable Port 1
+ * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled
+ * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
+ * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
+ * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled.
+ * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode.
+ */
+ __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */
+ __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */
+ __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */
+ __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */
+ __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */
+ __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */
+ __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */
+ __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */
+ __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */
+ __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */
+ __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */
+ __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */
+ __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */
+ __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */
+ __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */
+ __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */
+ __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */
+ __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */
+ __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */
+ __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */
+ __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */
+ __IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status [1] */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[105];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */
+ __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */
+
+} USBH_T;
+
+/**
+ @addtogroup USBH_CONST USBH Bit Field Definition
+ Constant Definitions for USBH Controller
+@{ */
+
+#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */
+#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */
+
+#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */
+#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */
+
+#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */
+#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */
+
+#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */
+#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */
+
+#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */
+#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */
+
+#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */
+#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */
+
+#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */
+#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */
+
+#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */
+#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */
+
+#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */
+#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */
+
+#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */
+#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */
+
+#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */
+#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */
+
+#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */
+#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */
+
+#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/
+#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */
+
+#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */
+#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */
+
+#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */
+#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */
+
+#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/
+#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */
+
+#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/
+#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */
+
+#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */
+#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */
+
+#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/
+#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */
+
+#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */
+#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */
+
+#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */
+#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */
+
+#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/
+#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */
+
+#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/
+#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */
+
+#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/
+#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */
+
+#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/
+#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */
+
+#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/
+#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */
+
+#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/
+#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */
+
+#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/
+#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */
+
+#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/
+#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */
+
+#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/
+#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */
+
+#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/
+#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */
+
+#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */
+#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */
+
+#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/
+#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */
+
+#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */
+#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */
+
+#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/
+#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */
+
+#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */
+#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */
+
+#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */
+#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */
+
+#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */
+#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */
+
+#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */
+#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */
+
+#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */
+#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */
+
+#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */
+#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */
+
+#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */
+#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */
+
+#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */
+#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */
+
+#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */
+#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */
+
+#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */
+#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */
+
+#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */
+#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */
+
+#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */
+#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */
+
+#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */
+#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */
+
+#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */
+#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */
+
+#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */
+#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */
+
+#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */
+#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */
+
+#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */
+#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */
+
+#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */
+#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */
+
+#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */
+#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */
+
+#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */
+#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */
+
+#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */
+#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */
+
+#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
+#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
+
+#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus1: CCS Position */
+#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus1: CCS Mask */
+
+#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus1: PES Position */
+#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus1: PES Mask */
+
+#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus1: PSS Position */
+#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus1: PSS Mask */
+
+#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus1: POCI Position */
+#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus1: POCI Mask */
+
+#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus1: PRS Position */
+#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus1: PRS Mask */
+
+#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus1: PPS Position */
+#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus1: PPS Mask */
+
+#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus1: LSDA Position */
+#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus1: LSDA Mask */
+
+#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus1: CSC Position */
+#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus1: CSC Mask */
+
+#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus1: PESC Position */
+#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus1: PESC Mask */
+
+#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus1: PSSC Position */
+#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus1: PSSC Mask */
+
+#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus1: OCIC Position */
+#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus1: OCIC Mask */
+
+#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus1: PRSC Position */
+#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus1: PRSC Mask */
+
+#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */
+#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */
+
+#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */
+#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */
+
+#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */
+#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */
+
+#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */
+#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */
+
+/**@}*/ /* USBH_CONST */
+/**@}*/ /* end of USBH register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __USBH_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uspi_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uspi_reg.h
new file mode 100644
index 00000000000..d9a2d3077a3
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uspi_reg.h
@@ -0,0 +1,677 @@
+/**************************************************************************//**
+ * @file uspi_reg.h
+ * @version V1.00
+ * @brief USPI register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __USPI_REG_H__
+#define __USPI_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup USPI SPI Mode of USCI Controller(USPI)
+ Memory Mapped Structure for USPI Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var USPI_T::CTL
+ * Offset: 0x00 USCI Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |FUNMODE |Function Mode
+ * | | |This bit field selects the protocol for this USCI controller
+ * | | |Selecting a protocol that is not available or a reserved combination disables the USCI
+ * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
+ * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
+ * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
+ * | | |001 = The SPI protocol is selected.
+ * | | |010 = The UART protocol is selected.
+ * | | |100 = The I2C protocol is selected.
+ * | | |Note: Other bit combinations are reserved.
+ * @var USPI_T::INTEN
+ * Offset: 0x04 USCI Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
+ * | | |This bit enables the interrupt generation in case of a transmit start event.
+ * | | |0 = The transmit start interrupt is disabled.
+ * | | |1 = The transmit start interrupt is enabled.
+ * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
+ * | | |This bit enables the interrupt generation in case of a transmit finish event.
+ * | | |0 = The transmit finish interrupt is disabled.
+ * | | |1 = The transmit finish interrupt is enabled.
+ * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit
+ * | | |This bit enables the interrupt generation in case of a receive start event.
+ * | | |0 = The receive start interrupt is disabled.
+ * | | |1 = The receive start interrupt is enabled.
+ * |[4] |RXENDIEN |Receive End Interrupt Enable Bit
+ * | | |This bit enables the interrupt generation in case of a receive finish event.
+ * | | |0 = The receive end interrupt is disabled.
+ * | | |1 = The receive end interrupt is enabled.
+ * @var USPI_T::BRGEN
+ * Offset: 0x08 USCI Baud Rate Generator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RCLKSEL |Reference Clock Source Selection
+ * | | |This bit selects the source of reference clock (fREF_CLK).
+ * | | |0 = Peripheral device clock fPCLK.
+ * | | |1 = Reserved.
+ * |[1] |PTCLKSEL |Protocol Clock Source Selection
+ * | | |This bit selects the source of protocol clock (fPROT_CLK).
+ * | | |0 = Reference clock fREF_CLK.
+ * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
+ * |[3:2] |SPCLKSEL |Sample Clock Source Selection
+ * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
+ * | | |00 = fDIV_CLK.
+ * | | |01 = fPROT_CLK.
+ * | | |10 = fSCLK.
+ * | | |11 = fREF_CLK.
+ * |[4] |TMCNTEN |Time Measurement Counter Enable Bit
+ * | | |This bit enables the 10-bit timing measurement counter.
+ * | | |0 = Time measurement counter is Disabled.
+ * | | |1 = Time measurement counter is Enabled.
+ * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
+ * | | |0 = Time measurement counter with fPROT_CLK.
+ * | | |1 = Time measurement counter with fDIV_CLK.
+ * |[25:16] |CLKDIV |Clock Divider
+ * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
+ * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled
+ * | | |The revised value is the average bit time between bit 5 and bit 6
+ * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate.
+ * @var USPI_T::DATIN0
+ * Offset: 0x10 USCI Input Data Signal Configuration Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SYNCSEL |Input Signal Synchronization Selection
+ * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.
+ * |[2] |ININV |Input Signal Inverse Selection
+ * | | |This bit defines the inverter enable of the input asynchronous signal.
+ * | | |0 = The un-synchronized input signal will not be inverted.
+ * | | |1 = The un-synchronized input signal will be inverted.
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.
+ * @var USPI_T::CTLIN0
+ * Offset: 0x20 USCI Input Control Signal Configuration Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SYNCSEL |Input Synchronization Signal Selection
+ * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.
+ * |[2] |ININV |Input Signal Inverse Selection
+ * | | |This bit defines the inverter enable of the input asynchronous signal.
+ * | | |0 = The un-synchronized input signal will not be inverted.
+ * | | |1 = The un-synchronized input signal will be inverted.
+ * @var USPI_T::CLKIN
+ * Offset: 0x28 USCI Input Clock Signal Configuration Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SYNCSEL |Input Synchronization Signal Selection
+ * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.
+ * @var USPI_T::LINECTL
+ * Offset: 0x2C USCI Line Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LSB |LSB First Transmission Selection
+ * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
+ * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
+ * |[5] |DATOINV |Data Output Inverse Selection
+ * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
+ * | | |0 = Data output level is not inverted.
+ * | | |1 = Data output level is inverted.
+ * |[7] |CTLOINV |Control Signal Output Inverse Selection
+ * | | |This bit defines the relation between the internal control signal and the output control signal.
+ * | | |0 = No effect.
+ * | | |1 = The control signal will be inverted before its output.
+ * | | |Note: The control signal has different definitions in different protocol
+ * | | |In SPI protocol, the control signal means slave select signal
+ * |[11:8] |DWIDTH |Word Length of Transmission
+ * | | |This bit field defines the data word length (amount of bits) for reception and transmission
+ * | | |The data word is always right-aligned in the data buffer
+ * | | |USCI support word length from 4 to 16 bits.
+ * | | |0x0: The data word contains 16 bits located at bit positions [15:0].
+ * | | |0x1: Reserved.
+ * | | |0x2: Reserved.
+ * | | |0x3: Reserved.
+ * | | |0x4: The data word contains 4 bits located at bit positions [3:0].
+ * | | |0x5: The data word contains 5 bits located at bit positions [4:0].
+ * | | |...
+ * | | |0xF: The data word contains 15 bits located at bit positions [14:0].
+ * @var USPI_T::TXDAT
+ * Offset: 0x30 USCI Transmit Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |TXDAT |Transmit Data
+ * | | |Software can use this bit field to write 16-bit transmit data for transmission
+ * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
+ * |[16] |PORTDIR |Port Direction Control
+ * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer
+ * | | |It is used to define the direction of the data port pin
+ * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously.
+ * | | |0 = The data pin is configured as output mode.
+ * | | |1 = The data pin is configured as input mode.
+ * @var USPI_T::RXDAT
+ * Offset: 0x34 USCI Receive Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RXDAT |Received Data
+ * | | |This bit field monitors the received data which stored in receive data buffer.
+ * @var USPI_T::BUFCTL
+ * Offset: 0x38 USCI Transmit/Receive Buffer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6] |TXUDRIEN |Slave Transmit Under Run Interrupt Enable Bit
+ * | | |0 = Transmit under-run interrupt Disabled.
+ * | | |1 = Transmit under-run interrupt Enabled.
+ * |[7] |TXCLR |Clear Transmit Buffer
+ * | | |0 = No effect.
+ * | | |1 = The transmit buffer is cleared
+ * | | |Should only be used while the buffer is not taking part in data traffic.
+ * | | |Note: It is cleared automatically after one PCLK cycle.
+ * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit
+ * | | |0 = Receive overrun interrupt Disabled.
+ * | | |1 = Receive overrun interrupt Enabled.
+ * |[15] |RXCLR |Clear Receive Buffer
+ * | | |0 = No effect.
+ * | | |1 = The receive buffer is cleared
+ * | | |Should only be used while the buffer is not taking part in data traffic.
+ * | | |Note: It is cleared automatically after one PCLK cycle.
+ * |[16] |TXRST |Transmit Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
+ * | | |Note: It is cleared automatically after one PCLK cycle.
+ * |[17] |RXRST |Receive Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
+ * | | |Note: It is cleared automatically after one PCLK cycle.
+ * @var USPI_T::BUFSTS
+ * Offset: 0x3C USCI Transmit/Receive Buffer Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXEMPTY |Receive Buffer Empty Indicator
+ * | | |0 = Receive buffer is not empty.
+ * | | |1 = Receive buffer is empty.
+ * |[1] |RXFULL |Receive Buffer Full Indicator
+ * | | |0 = Receive buffer is not full.
+ * | | |1 = Receive buffer is full.
+ * |[3] |RXOVIF |Receive Buffer Over-run Interrupt Status
+ * | | |This bit indicates that a receive buffer overrun event has been detected
+ * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
+ * | | |It is cleared by software writes 1 to this bit.
+ * | | |0 = A receive buffer overrun event has not been detected.
+ * | | |1 = A receive buffer overrun event has been detected.
+ * |[8] |TXEMPTY |Transmit Buffer Empty Indicator
+ * | | |0 = Transmit buffer is not empty.
+ * | | |1 = Transmit buffer is empty and available for the next transmission datum.
+ * |[9] |TXFULL |Transmit Buffer Full Indicator
+ * | | |0 = Transmit buffer is not full.
+ * | | |1 = Transmit buffer is full.
+ * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status
+ * | | |This bit indicates that a transmit buffer under-run event has been detected
+ * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated
+ * | | |It is cleared by software writes 1 to this bit
+ * | | |0 = A transmit buffer under-run event has not been detected.
+ * | | |1 = A transmit buffer under-run event has been detected.
+ * @var USPI_T::PDMACTL
+ * Offset: 0x40 USCI PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PDMARST |PDMA Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
+ * |[1] |TXPDMAEN |PDMA Transmit Channel Available
+ * | | |0 = Transmit PDMA function Disabled.
+ * | | |1 = Transmit PDMA function Enabled.
+ * |[2] |RXPDMAEN |PDMA Receive Channel Available
+ * | | |0 = Receive PDMA function Disabled.
+ * | | |1 = Receive PDMA function Enabled.
+ * |[3] |PDMAEN |PDMA Mode Enable Bit
+ * | | |0 = PDMA function Disabled.
+ * | | |1 = PDMA function Enabled.
+ * | | |Notice: The I2C is not supporting PDMA function.
+ * @var USPI_T::WKCTL
+ * Offset: 0x54 USCI Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Wake-up Enable Bit
+ * | | |0 = Wake-up function Disabled.
+ * | | |1 = Wake-up function Enabled.
+ * |[1] |WKADDREN |Wake-up Address Match Enable Bit
+ * | | |0 = The chip is woken up according data toggle.
+ * | | |1 = The chip is woken up according address match.
+ * |[2] |PDBOPT |Power Down Blocking Option
+ * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
+ * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
+ * @var USPI_T::WKSTS
+ * Offset: 0x58 USCI Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKF |Wake-up Flag
+ * | | |When chip is woken up from Power-down mode, this bit is set to 1
+ * | | |Software can write 1 to clear this bit.
+ * @var USPI_T::PROTCTL
+ * Offset: 0x5C USCI Protocol Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SLAVE |Slave Mode Selection
+ * | | |0 = Master mode.
+ * | | |1 = Slave mode.
+ * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only)
+ * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
+ * | | |0 = 4-wire bi-direction interface.
+ * | | |1 = 3-wire bi-direction interface.
+ * |[2] |SS |Slave Select Control (Master Only)
+ * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.
+ * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal.
+ * | | |Note: In SPI protocol, the internal slave select signal is active high.
+ * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only)
+ * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit.
+ * | | |1 = Slave select signal will be generated automatically
+ * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
+ * |[7:6] |SCLKMODE |Serial Bus Clock Mode
+ * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge.
+ * | | |MODE0 = The idle state of SPI clock is low level
+ * | | |Data is transmitted with falling edge and received with rising edge.
+ * | | |MODE1 = The idle state of SPI clock is low level
+ * | | |Data is transmitted with rising edge and received with falling edge.
+ * | | |MODE2 = The idle state of SPI clock is high level
+ * | | |Data is transmitted with rising edge and received with falling edge.
+ * | | |MODE3 = The idle state of SPI clock is high level
+ * | | |Data is transmitted with falling edge and received with rising edge.
+ * |[11:8] |SUSPITV |Suspend Interval (Master Only)
+ * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer
+ * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
+ * | | |The default value is 0x3
+ * | | |The period of the suspend interval is obtained according to the following equation.
+ * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
+ * | | |Example:
+ * | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle.
+ * | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle.
+ * | | |.....
+ * | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle.
+ * | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle.
+ * |[14:12] |TSMSEL |Transmit Data Mode Selection
+ * | | |This bit field describes how receive and transmit data is shifted in and out.
+ * | | |TSMSEL = 000b: Full-duplex SPI.
+ * | | |TSMSEL = 100b: Half-duplex SPI.
+ * | | |Other values are reserved.
+ * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
+ * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only)
+ * | | |In Slave mode, this bit field is used for Slave time-out period
+ * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event
+ * | | |Writing 0x0 into this bit field will disable the Slave time-out function.
+ * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
+ * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave)
+ * | | |This bit defines the transmitting data level when no data is available for transferring.
+ * | | |0 = The output data level is 0 if TX under run event occurs.
+ * | | |1 = The output data level is 1 if TX under run event occurs.
+ * |[31] |PROTEN |SPI Protocol Enable Bit
+ * | | |0 = SPI Protocol Disabled.
+ * | | |1 = SPI Protocol Enabled.
+ * @var USPI_T::PROTIEN
+ * Offset: 0x60 USCI Protocol Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control
+ * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
+ * | | |0 = Slave select inactive interrupt generation Disabled.
+ * | | |1 = Slave select inactive interrupt generation Enabled.
+ * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control
+ * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
+ * | | |0 = Slave select active interrupt generation Disabled.
+ * | | |1 = Slave select active interrupt generation Enabled.
+ * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control
+ * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
+ * | | |0 = The Slave time-out interrupt Disabled.
+ * | | |1 = The Slave time-out interrupt Enabled.
+ * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control
+ * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])
+ * | | |Bit count error event occurs.
+ * | | |0 = The Slave mode bit count error interrupt Disabled.
+ * | | |1 = The Slave mode bit count error interrupt Enabled.
+ * @var USPI_T::PROTSTS
+ * Offset: 0x64 USCI Protocol Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TXSTIF |Transmit Start Interrupt Flag
+ * | | |0 = Transmit start event does not occur.
+ * | | |1 = Transmit start event occurs.
+ * | | |Note: It is cleared by software writes 1 to this bit
+ * |[2] |TXENDIF |Transmit End Interrupt Flag
+ * | | |0 = Transmit end event does not occur.
+ * | | |1 = Transmit end event occurs.
+ * | | |Note: It is cleared by software writes 1 to this bit
+ * |[3] |RXSTIF |Receive Start Interrupt Flag
+ * | | |0 = Receive start event does not occur.
+ * | | |1 = Receive start event occurs.
+ * | | |Note: It is cleared by software writes 1 to this bit
+ * |[4] |RXENDIF |Receive End Interrupt Flag
+ * | | |0 = Receive end event does not occur.
+ * | | |1 = Receive end event occurs.
+ * | | |Note: It is cleared by software writes 1 to this bit
+ * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only)
+ * | | |0 = Slave time-out event does not occur.
+ * | | |1 = Slave time-out event occurs.
+ * | | |Note: It is cleared by software writes 1 to this bit
+ * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only)
+ * | | |0 = Slave bit count error event does not occur.
+ * | | |1 = Slave bit count error event occurs.
+ * | | |Note: It is cleared by software writes 1 to this bit.
+ * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only)
+ * | | |This bit indicates that the internal slave select signal has changed to inactive
+ * | | |It is cleared by software writes 1 to this bit
+ * | | |0 = The slave select signal has not changed to inactive.
+ * | | |1 = The slave select signal has changed to inactive.
+ * | | |Note: The internal slave select signal is active high.
+ * |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only)
+ * | | |This bit indicates that the internal slave select signal has changed to active
+ * | | |It is cleared by software writes one to this bit
+ * | | |0 = The slave select signal has not changed to active.
+ * | | |1 = The slave select signal has changed to active.
+ * | | |Note: The internal slave select signal is active high.
+ * |[16] |SSLINE |Slave Select Line Bus Status (Read Only)
+ * | | |This bit is only available in Slave mode
+ * | | |It used to monitor the current status of the input slave select signal on the bus.
+ * | | |0 = The slave select line status is 0.
+ * | | |1 = The slave select line status is 1.
+ * |[17] |BUSY |Busy Status (Read Only)
+ * | | |0 = SPI is in idle state.
+ * | | |1 = SPI is in busy state.
+ * | | |The following listing are the bus busy conditions:
+ * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0.
+ * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
+ * | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active.
+ * | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
+ * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only)
+ * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1
+ * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
+ * | | |0 = Slave transmit under-run event does not occur.
+ * | | |1 = Slave transmit under-run event occurs.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
+ __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
+ __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
+ __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
+ __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
+ __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
+ __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
+ __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
+ __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[4];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
+ __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
+ __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
+ __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
+ __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
+
+} USPI_T;
+
+/**
+ @addtogroup USPI_CONST USPI Bit Field Definition
+ Constant Definitions for USPI Controller
+@{ */
+
+#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */
+#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */
+
+#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */
+#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */
+
+#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */
+#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */
+
+#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */
+#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */
+
+#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */
+#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */
+
+#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */
+#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */
+
+#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */
+#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */
+
+#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */
+#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */
+
+#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */
+#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */
+
+#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */
+#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */
+
+#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */
+#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */
+
+#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */
+#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */
+
+#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */
+#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */
+
+#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */
+#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */
+
+#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */
+#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */
+
+#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */
+#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */
+
+#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */
+#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */
+
+#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */
+#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */
+
+#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */
+#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */
+
+#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */
+#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */
+
+#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */
+#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */
+
+#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */
+#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */
+
+#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */
+#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */
+
+#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */
+#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */
+
+#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */
+#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */
+
+#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */
+#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */
+
+#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */
+#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */
+
+#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */
+#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */
+
+#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */
+#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */
+
+#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */
+#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */
+
+#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */
+#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */
+
+#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */
+#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */
+
+#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */
+#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */
+
+#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */
+#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */
+
+#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */
+#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */
+
+#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */
+#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */
+
+#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */
+#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */
+
+#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */
+#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */
+
+#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */
+#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */
+
+#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */
+#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */
+
+#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */
+#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */
+
+#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */
+#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */
+
+#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */
+#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */
+
+#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */
+#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */
+
+#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */
+#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */
+
+#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */
+#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */
+
+#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */
+#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */
+
+#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */
+#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */
+
+#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */
+#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */
+
+#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */
+#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */
+
+#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */
+#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */
+
+#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */
+#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */
+
+#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */
+#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */
+
+#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */
+#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */
+
+#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */
+#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */
+
+#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */
+#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */
+
+#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */
+#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */
+
+#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */
+#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */
+
+#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */
+#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */
+
+#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */
+#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */
+
+#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */
+#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */
+
+#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */
+#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */
+
+#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */
+#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */
+
+#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */
+#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */
+
+#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */
+#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */
+
+#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */
+#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */
+
+#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */
+#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */
+
+#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */
+#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */
+
+/**@}*/ /* USPI_CONST */
+/**@}*/ /* end of USPI register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __USPI_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uuart_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uuart_reg.h
new file mode 100644
index 00000000000..3ebce1d6f31
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uuart_reg.h
@@ -0,0 +1,679 @@
+/**************************************************************************//**
+ * @file uuart_reg.h
+ * @version V1.00
+ * @brief UUART register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __UUART_REG_H__
+#define __UUART_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup UUART UART Mode of USCI Controller(UUART)
+ Memory Mapped Structure for UUART Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var UUART_T::CTL
+ * Offset: 0x00 USCI Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |FUNMODE |Function Mode
+ * | | |This bit field selects the protocol for this USCI controller
+ * | | |Selecting a protocol that is not available or a reserved combination disables the USCI
+ * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
+ * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
+ * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
+ * | | |001 = The SPI protocol is selected.
+ * | | |010 = The UART protocol is selected.
+ * | | |100 = The I2C protocol is selected.
+ * | | |Note: Other bit combinations are reserved.
+ * @var UUART_T::INTEN
+ * Offset: 0x04 USCI Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
+ * | | |This bit enables the interrupt generation in case of a transmit start event.
+ * | | |0 = The transmit start interrupt is disabled.
+ * | | |1 = The transmit start interrupt is enabled.
+ * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
+ * | | |This bit enables the interrupt generation in case of a transmit finish event.
+ * | | |0 = The transmit finish interrupt is disabled.
+ * | | |1 = The transmit finish interrupt is enabled.
+ * |[3] |RXSTIEN |Receive Start Interrupt Enable BIt
+ * | | |This bit enables the interrupt generation in case of a receive start event.
+ * | | |0 = The receive start interrupt is disabled.
+ * | | |1 = The receive start interrupt is enabled.
+ * |[4] |RXENDIEN |Receive End Interrupt Enable Bit
+ * | | |This bit enables the interrupt generation in case of a receive finish event.
+ * | | |0 = The receive end interrupt is disabled.
+ * | | |1 = The receive end interrupt is enabled.
+ * @var UUART_T::BRGEN
+ * Offset: 0x08 USCI Baud Rate Generator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RCLKSEL |Reference Clock Source Selection
+ * | | |This bit selects the source signal of reference clock (fREF_CLK).
+ * | | |0 = Peripheral device clock fPCLK.
+ * | | |1 = Reserved.
+ * |[1] |PTCLKSEL |Protocol Clock Source Selection
+ * | | |This bit selects the source signal of protocol clock (fPROT_CLK).
+ * | | |0 = Reference clock fREF_CLK.
+ * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
+ * |[3:2] |SPCLKSEL |Sample Clock Source Selection
+ * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
+ * | | |00 = fSAMP_CLK = fDIV_CLK.
+ * | | |01 = fSAMP_CLK = fPROT_CLK.
+ * | | |10 = fSAMP_CLK = fSCLK.
+ * | | |11 = fSAMP_CLK = fREF_CLK.
+ * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit
+ * | | |This bit enables the 10-bit timing measurement counter.
+ * | | |0 = Timing measurement counter is Disabled.
+ * | | |1 = Timing measurement counter is Enabled.
+ * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection
+ * | | |0 = Timing measurement counter with fPROT_CLK.
+ * | | |1 = Timing measurement counter with fDIV_CLK.
+ * |[9:8] |PDSCNT |Pre-divider for Sample Counter
+ * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
+ * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
+ * |[14:10] |DSCNT |Denominator for Sample Counter
+ * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
+ * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
+ * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
+ * |[25:16] |CLKDIV |Clock Divider
+ * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and
+ * | | |the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
+ * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55
+ * | | |when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled
+ * | | |The revised value is the average bit time between bit 5 and bit 6
+ * | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate.
+ * @var UUART_T::DATIN0
+ * Offset: 0x10 USCI Input Data Signal Configuration Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SYNCSEL |Input Signal Synchronization Selection
+ * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or
+ * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.
+ * |[2] |ININV |Input Signal Inverse Selection
+ * | | |This bit defines the inverter enable of the input asynchronous signal.
+ * | | |0 = The un-synchronized input signal will not be inverted.
+ * | | |1 = The un-synchronized input signal will be inverted.
+ * |[4:3] |EDGEDET |Input Signal Edge Detection Mode
+ * | | |This bit field selects which edge actives the trigger event of input data signal.
+ * | | |00 = The trigger event activation is disabled.
+ * | | |01 = A rising edge activates the trigger event of input data signal.
+ * | | |10 = A falling edge activates the trigger event of input data signal.
+ * | | |11 = Both edges activate the trigger event of input data signal.
+ * | | |Note: In UART function mode, it is suggested to set this bit field as 10.
+ * @var UUART_T::CTLIN0
+ * Offset: 0x20 USCI Input Control Signal Configuration Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SYNCSEL |Input Synchronization Signal Selection
+ * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or
+ * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.
+ * |[2] |ININV |Input Signal Inverse Selection
+ * | | |This bit defines the inverter enable of the input asynchronous signal.
+ * | | |0 = The un-synchronized input signal will not be inverted.
+ * | | |1 = The un-synchronized input signal will be inverted.
+ * @var UUART_T::CLKIN
+ * Offset: 0x28 USCI Input Clock Signal Configuration Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SYNCSEL |Input Synchronization Signal Selection
+ * | | |This bit selects if the un-synchronized input signal or
+ * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.
+ * @var UUART_T::LINECTL
+ * Offset: 0x2C USCI Line Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LSB |LSB First Transmission Selection
+ * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
+ * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
+ * |[5] |DATOINV |Data Output Inverse Selection
+ * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
+ * | | |0 = The value of USCIx_DAT1 is equal to the data shift register.
+ * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register.
+ * |[7] |CTLOINV |Control Signal Output Inverse Selection
+ * | | |This bit defines the relation between the internal control signal and the output control signal.
+ * | | |0 = No effect.
+ * | | |1 = The control signal will be inverted before its output.
+ * | | |Note: In UART protocol, the control signal means nRTS signal.
+ * |[11:8] |DWIDTH |Word Length of Transmission
+ * | | |This bit field defines the data word length (amount of bits) for reception and transmission
+ * | | |The data word is always right-aligned in the data buffer
+ * | | |USCI support word length from 4 to 16 bits.
+ * | | |0x0: The data word contains 16 bits located at bit positions [15:0].
+ * | | |0x1: Reserved.
+ * | | |0x2: Reserved.
+ * | | |0x3: Reserved.
+ * | | |0x4: The data word contains 4 bits located at bit positions [3:0].
+ * | | |0x5: The data word contains 5 bits located at bit positions [4:0].
+ * | | |..
+ * | | |0xF: The data word contains 15 bits located at bit positions [14:0].
+ * | | |Note: In UART protocol, the length can be configured as 6~13 bits.
+ * @var UUART_T::TXDAT
+ * Offset: 0x30 USCI Transmit Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |TXDAT |Transmit Data
+ * | | |Software can use this bit field to write 16-bit transmit data for transmission.
+ * @var UUART_T::RXDAT
+ * Offset: 0x34 USCI Receive Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RXDAT |Received Data
+ * | | |This bit field monitors the received data which stored in receive data buffer.
+ * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]).
+ * @var UUART_T::BUFCTL
+ * Offset: 0x38 USCI Transmit/Receive Buffer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7] |TXCLR |Clear Transmit Buffer
+ * | | |0 = No effect.
+ * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value)
+ * | | |Should only be used while the buffer is not taking part in data traffic.
+ * | | |Note: It is cleared automatically after one PCLK cycle.
+ * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control
+ * | | |0 = Receive overrun interrupt Disabled.
+ * | | |1 = Receive overrun interrupt Enabled.
+ * |[15] |RXCLR |Clear Receive Buffer
+ * | | |0 = No effect.
+ * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value)
+ * | | |Should only be used while the buffer is not taking part in data traffic.
+ * | | |Note: It is cleared automatically after one PCLK cycle.
+ * |[16] |TXRST |Transmit Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
+ * | | |Note: It is cleared automatically after one PCLK cycle.
+ * |[17] |RXRST |Receive Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
+ * | | |Note 1: It is cleared automatically after one PCLK cycle.
+ * | | |Note 2: It is suggest to check the RXBUSY (USCI_PROTSTS[10]) before this bit will be set to 1.
+ * @var UUART_T::BUFSTS
+ * Offset: 0x3C USCI Transmit/Receive Buffer Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXEMPTY |Receive Buffer Empty Indicator
+ * | | |0 = Receive buffer is not empty.
+ * | | |1 = Receive buffer is empty.
+ * |[1] |RXFULL |Receive Buffer Full Indicator
+ * | | |0 = Receive buffer is not full.
+ * | | |1 = Receive buffer is full.
+ * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status
+ * | | |This bit indicates that a receive buffer overrun error event has been detected
+ * | | |If RXOVIEN (USCI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
+ * | | |It is cleared by software writes 1 to this bit.
+ * | | |0 = A receive buffer overrun error event has not been detected.
+ * | | |1 = A receive buffer overrun error event has been detected.
+ * |[8] |TXEMPTY |Transmit Buffer Empty Indicator
+ * | | |0 = Transmit buffer is not empty.
+ * | | |1 = Transmit buffer is empty.
+ * |[9] |TXFULL |Transmit Buffer Full Indicator
+ * | | |0 = Transmit buffer is not full.
+ * | | |1 = Transmit buffer is full.
+ * @var UUART_T::PDMACTL
+ * Offset: 0x40 USCI PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PDMARST |PDMA Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
+ * |[1] |TXPDMAEN |PDMA Transmit Channel Available
+ * | | |0 = Transmit PDMA function Disabled.
+ * | | |1 = Transmit PDMA function Enabled.
+ * |[2] |RXPDMAEN |PDMA Receive Channel Available
+ * | | |0 = Receive PDMA function Disabled.
+ * | | |1 = Receive PDMA function Enabled.
+ * |[3] |PDMAEN |PDMA Mode Enable Bit
+ * | | |0 = PDMA function Disabled.
+ * | | |1 = PDMA function Enabled.
+ * @var UUART_T::WKCTL
+ * Offset: 0x54 USCI Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Wake-up Enable Bit
+ * | | |0 = Wake-up function Disabled.
+ * | | |1 = Wake-up function Enabled.
+ * |[2] |PDBOPT |Power Down Blocking Option
+ * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
+ * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
+ * @var UUART_T::WKSTS
+ * Offset: 0x58 USCI Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKF |Wake-up Flag
+ * | | |When chip is woken up from Power-down mode, this bit is set to 1
+ * | | |Software can write 1 to clear this bit.
+ * @var UUART_T::PROTCTL
+ * Offset: 0x5C USCI Protocol Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |STOPB |Stop Bits
+ * | | |This bit defines the number of stop bits in an UART frame.
+ * | | |0 = The number of stop bits is 1.
+ * | | |1 = The number of stop bits is 2.
+ * |[1] |PARITYEN |Parity Enable Bit
+ * | | |This bit defines the parity bit is enabled in an UART frame.
+ * | | |0 = The parity bit Disabled.
+ * | | |1 = The parity bit Enabled.
+ * |[2] |EVENPARITY|Even Parity Enable Bit
+ * | | |0 = Odd number of logic 1's is transmitted and checked in each word.
+ * | | |1 = Even number of logic 1's is transmitted and checked in each word.
+ * | | |Note: This bit has effect only when PARITYEN is set.
+ * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit
+ * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (USCI_BUFSTS[1] = 1'b1)), the UART will de-assert nRTS signal.
+ * | | |0 = nRTS auto-flow control Disabled.
+ * | | |1 = nRTS auto-flow control Enabled.
+ * | | |Note: This bit has effect only when the RTSAUDIREN is not set.
+ * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit
+ * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
+ * | | |0 = nCTS auto-flow control Disabled.
+ * | | |1 = nCTS auto-flow control Enabled.
+ * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit
+ * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.
+ * | | |0 = nRTS auto direction control Disabled.
+ * | | |1 = nRTS auto direction control Enabled.
+ * | | |Note 1: This bit is used for nRTS auto direction control for RS485.
+ * | | |Note 2: This bit has effect only when the RTSAUTOEN is not set.
+ * |[6] |ABREN |Auto-baud Rate Detect Enable Bit
+ * | | |0 = Auto-baud rate detect function Disabled.
+ * | | |1 = Auto-baud rate detect function Enabled.
+ * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit
+ * | | |The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (USCI_PROTIEN [1]) is enabled).
+ * |[9] |DATWKEN |Data Wake-up Mode Enable Bit
+ * | | |0 = Data wake-up mode Disabled.
+ * | | |1 = Data wake-up mode Enabled.
+ * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit
+ * | | |0 = nCTS wake-up mode Disabled.
+ * | | |1 = nCTS wake-up mode Enabled.
+ * |[14:11] |WAKECNT |Wake-up Counter
+ * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
+ * |[24:16] |BRDETITV |Baud Rate Detection Interval
+ * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) does the slave calculates the baud rate in one bits
+ * | | |The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55)
+ * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (USCI_PROTCTL[9]) is set.
+ * | | |Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
+ * |[26] |STICKEN |Stick Parity Enable Bit
+ * | | |0 = Stick parity Disabled.
+ * | | |1 = Stick parity Enabled.
+ * | | |Note: Refer to RS-485 Support section for detail information.
+ * |[29] |BCEN |Transmit Break Control Enable Bit
+ * | | |0 = Transmit Break Control Disabled.
+ * | | |1 = Transmit Break Control Enabled.
+ * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0)
+ * | | |This bit acts only on TX line and has no effect on the transmitter logic.
+ * |[31] |PROTEN |UART Protocol Enable Bit
+ * | | |0 = UART Protocol Disabled.
+ * | | |1 = UART Protocol Enabled.
+ * @var UUART_T::PROTIEN
+ * Offset: 0x60 USCI Protocol Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit
+ * | | |0 = Auto-baud rate interrupt Disabled.
+ * | | |1 = Auto-baud rate interrupt Enabled.
+ * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
+ * | | |0 = Receive line status interrupt Disabled.
+ * | | |1 = Receive line status interrupt Enabled.
+ * | | |Note: USCI_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
+ * @var UUART_T::PROTSTS
+ * Offset: 0x64 USCI Protocol Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TXSTIF |Transmit Start Interrupt Flag
+ * | | |0 = A transmit start interrupt status has not occurred.
+ * | | |1 = A transmit start interrupt status has occurred.
+ * | | |Note 1: It is cleared by software writing one into this bit.
+ * | | |Note 2: Used for user to load next transmit data when there is no data in transmit buffer.
+ * |[2] |TXENDIF |Transmit End Interrupt Flag
+ * | | |0 = A transmit end interrupt status has not occurred.
+ * | | |1 = A transmit end interrupt status has occurred.
+ * | | |Note: It is cleared by software writing one into this bit.
+ * |[3] |RXSTIF |Receive Start Interrupt Flag
+ * | | |0 = A receive start interrupt status has not occurred.
+ * | | |1 = A receive start interrupt status has occurred.
+ * | | |Note: It is cleared by software writing one into this bit.
+ * |[4] |RXENDIF |Receive End Interrupt Flag
+ * | | |0 = A receive finish interrupt status has not occurred.
+ * | | |1 = A receive finish interrupt status has occurred.
+ * | | |Note: It is cleared by software writing one into this bit.
+ * |[5] |PARITYERR |Parity Error Flag
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
+ * | | |0 = No parity error is generated.
+ * | | |1 = Parity error is generated.
+ * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
+ * |[6] |FRMERR |Framing Error Flag
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit'
+ * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+ * | | |0 = No framing error is generated.
+ * | | |1 = Framing error is generated.
+ * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
+ * |[7] |BREAK |Break Flag
+ * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state'
+ * | | |(logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
+ * | | |0 = No Break is generated.
+ * | | |1 = Break is generated in the receiver bus.
+ * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
+ * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag
+ * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data
+ * | | |If the ABRIEN (USCI_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated
+ * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
+ * | | |0 = Auto-baud rate detect function is not done.
+ * | | |1 = One Bit auto-baud rate detect function is done.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[10] |RXBUSY |RX Bus Status Flag (Read Only)
+ * | | |This bit indicates the busy status of the receiver.
+ * | | |0 = The receiver is Idle.
+ * | | |1 = The receiver is BUSY.
+ * |[11] |ABERRSTS |Auto-baud Rate Error Status
+ * | | |This bit is set when auto-baud rate detection counter overrun
+ * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (USCI_BRGEN[25:16]) value and
+ * | | |enable ABREN (USCI_PROTCTL[6]) to detect the correct baud rate again.
+ * | | |0 = Auto-baud rate detect counter is not overrun.
+ * | | |1 = Auto-baud rate detect counter is overrun.
+ * | | |Note 1: This bit is set at the same time of ABRDETIF.
+ * | | |Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
+ * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only)
+ * | | |This bit used to indicate the current status of the internal synchronized nCTS signal.
+ * | | |0 = The internal synchronized nCTS is low.
+ * | | |1 = The internal synchronized nCTS is high.
+ * |[17] |CTSLV |nCTS Pin Status (Read Only)
+ * | | |This bit used to monitor the current status of nCTS pin input.
+ * | | |0 = nCTS pin input is low level voltage logic state.
+ * | | |1 = nCTS pin input is high level voltage logic state.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
+ __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
+ __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
+ __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
+ __IO uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
+ __IO uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
+ __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
+ __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
+ __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[4];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
+ __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
+ __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
+ __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
+ __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
+
+} UUART_T;
+
+/**
+ @addtogroup UUART_CONST UUART Bit Field Definition
+ Constant Definitions for UUART Controller
+@{ */
+
+#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */
+#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */
+
+#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */
+#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */
+
+#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */
+#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */
+
+#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */
+#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */
+
+#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */
+#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */
+
+#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */
+#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */
+
+#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */
+#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */
+
+#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */
+#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */
+
+#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */
+#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */
+
+#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */
+#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */
+
+#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */
+#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */
+
+#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */
+#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */
+
+#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */
+#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */
+
+#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */
+#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */
+
+#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */
+#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */
+
+#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */
+#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */
+
+#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */
+#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */
+
+#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */
+#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */
+
+#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */
+#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */
+
+#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */
+#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */
+
+#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */
+#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */
+
+#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */
+#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */
+
+#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */
+#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */
+
+#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */
+#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */
+
+#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */
+#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */
+
+#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */
+#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */
+
+#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */
+#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */
+
+#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */
+#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */
+
+#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */
+#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */
+
+#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */
+#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */
+
+#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */
+#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */
+
+#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */
+#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */
+
+#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */
+#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */
+
+#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */
+#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */
+
+#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */
+#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */
+
+#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */
+#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */
+
+#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */
+#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */
+
+#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */
+#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */
+
+#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */
+#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */
+
+#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */
+#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */
+
+#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */
+#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */
+
+#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */
+#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */
+
+#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */
+#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */
+
+#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */
+#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */
+
+#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */
+#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */
+
+#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */
+#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */
+
+#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */
+#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */
+
+#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */
+#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */
+
+#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */
+#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */
+
+#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */
+#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */
+
+#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */
+#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */
+
+#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */
+#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */
+
+#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */
+#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */
+
+#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */
+#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */
+
+#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */
+#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */
+
+#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */
+#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */
+
+#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */
+#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */
+
+#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */
+#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */
+
+#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */
+#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */
+
+#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */
+#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */
+
+#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */
+#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */
+
+#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */
+#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */
+
+#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */
+#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */
+
+#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */
+#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */
+
+#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */
+#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */
+
+#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */
+#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */
+
+#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */
+#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */
+
+#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */
+#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */
+
+#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */
+#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */
+
+#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */
+#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */
+
+/**@}*/ /* UUART_CONST */
+/**@}*/ /* end of UUART register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __UUART_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wdt_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wdt_reg.h
new file mode 100644
index 00000000000..2bead168677
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wdt_reg.h
@@ -0,0 +1,183 @@
+/**************************************************************************//**
+ * @file wdt_reg.h
+ * @version V1.00
+ * @brief WDT register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WDT_REG_H__
+#define __WDT_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup WDT Watch Dog Timer Controller(WDT)
+ Memory Mapped Structure for WDT Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var WDT_T::CTL
+ * Offset: 0x00 WDT Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RSTCNT |Reset WDT Up Counter (Write Protect)
+ * | | |0 = No effect.
+ * | | |1 = Reset the internal 18-bit WDT up counter value.
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note2: This bit will be automatically cleared by hardware.
+ * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect)
+ * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
+ * | | |0 = WDT time-out reset function Disabled.
+ * | | |1 = WDT time-out reset function Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |RSTF |WDT Time-out Reset Flag
+ * | | |This bit indicates the system has been reset by WDT time-out reset or not.
+ * | | |0 = WDT time-out reset did not occur.
+ * | | |1 = WDT time-out reset occurred.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[3] |IF |WDT Time-out Interrupt Flag
+ * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
+ * | | |0 = WDT time-out interrupt did not occur.
+ * | | |1 = WDT time-out interrupt occurred.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)
+ * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
+ * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
+ * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
+ * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect)
+ * | | |This bit indicates the interrupt wake-up flag status of WDT
+ * | | |0 = WDT does not cause chip wake-up.
+ * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note2: This bit is cleared by writing 1 to it.
+ * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect)
+ * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
+ * | | |0 = WDT time-out interrupt Disabled.
+ * | | |1 = WDT time-out interrupt Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |WDTEN |WDT Enable Control (Write Protect)
+ * | | |0 = WDT Disabled (This action will reset the internal up counter value).
+ * | | |1 = WDT Enabled.
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
+ * |[10:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
+ * | | |These three bits select the time-out interval period for the WDT.
+ * | | |000 = 24 * WDT_CLK.
+ * | | |001 = 26 * WDT_CLK.
+ * | | |010 = 28 * WDT_CLK.
+ * | | |011 = 210 * WDT_CLK.
+ * | | |100 = 212 * WDT_CLK.
+ * | | |101 = 214 * WDT_CLK.
+ * | | |110 = 216 * WDT_CLK.
+ * | | |111 = 218 * WDT_CLK.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only)
+ * | | |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
+ * | | |0 = Set WDTEN bit is completed.
+ * | | |1 = Set WDTEN bit is synchronizing and not become active yet..
+ * | | |Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
+ * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
+ * | | |0 = ICE debug mode acknowledgement affects WDT counting.
+ * | | |WDT up counter will be held while CPU is held by ICE.
+ * | | |1 = ICE debug mode acknowledgement Disabled.
+ * | | |WDT up counter will keep going no matter CPU is held by ICE or not.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var WDT_T::ALTCTL
+ * Offset: 0x04 WDT Alternative Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
+ * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened
+ * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
+ * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
+ * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
+ * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
+ * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
+ * @var WDT_T::RSTCNT
+ * Offset: 0x08 WDT Reset Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RSTCNT |WDT Reset Counter Register
+ * | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
+ * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
+ * | | |Note: RSTCNT (WDT_CTL[0]) bit is a write protected bit
+ * | | |RSTCNT (WDT_RSTCNT[31:0]) bits are not write protected.
+ */
+ __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */
+ __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */
+ __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */
+
+} WDT_T;
+
+/**
+ @addtogroup WDT_CONST WDT Bit Field Definition
+ Constant Definitions for WDT Controller
+@{ */
+
+#define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */
+#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */
+
+#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
+#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
+
+#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
+#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
+
+#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
+#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
+
+#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
+#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
+
+#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
+#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
+
+#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
+#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
+
+#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
+#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
+
+#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
+#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
+
+#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */
+#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */
+
+#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
+#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
+
+#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
+#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
+
+#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */
+#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */
+
+/**@}*/ /* WDT_CONST */
+/**@}*/ /* end of WDT register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __WDT_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wwdt_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wwdt_reg.h
new file mode 100644
index 00000000000..67f5748826a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wwdt_reg.h
@@ -0,0 +1,149 @@
+/**************************************************************************//**
+ * @file wwdt_reg.h
+ * @version V1.00
+ * @brief WWDT register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WWDT_REG_H__
+#define __WWDT_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup WWDT Window Watchdog Timer(WWDT)
+ Memory Mapped Structure for WWDT Controller
+@{ */
+
+typedef struct
+{
+
+
+ /**
+ * @var WWDT_T::RLDCNT
+ * Offset: 0x00 WWDT Reload Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RLDCNT |WWDT Reload Counter Register
+ * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
+ * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16])
+ * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
+ * @var WWDT_T::CTL
+ * Offset: 0x04 WWDT Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WWDTEN |WWDT Enable Control Bit
+ * | | |Set this bit to enable WWDT counter counting.
+ * | | |0 = WWDT counter is stopped.
+ * | | |1 = WWDT counter is starting counting.
+ * |[1] |INTEN |WWDT Interrupt Enable Control Bit
+ * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
+ * | | |0 = WWDT counter compare match interrupt Disabled.
+ * | | |1 = WWDT counter compare match interrupt Enabled.
+ * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
+ * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
+ * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
+ * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
+ * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
+ * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
+ * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
+ * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
+ * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
+ * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
+ * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
+ * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
+ * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
+ * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
+ * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
+ * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
+ * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
+ * |[21:16] |CMPDAT |WWDT Window Compare Register
+ * | | |Set this register to adjust the valid reload window.
+ * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT
+ * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
+ * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
+ * | | |0 = ICE debug mode acknowledgement effects WWDT counting.
+ * | | |WWDT down counter will be held while CPU is held by ICE.
+ * | | |1 = ICE debug mode acknowledgement Disabled.
+ * | | |WWDT down counter will keep going no matter CPU is held by ICE or not.
+ * @var WWDT_T::STATUS
+ * Offset: 0x08 WWDT Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
+ * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
+ * | | |0 = No effect.
+ * | | |1 = WWDT counter value matches CMPDAT.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[1] |WWDTRF |WWDT Timer-out Reset Flag
+ * | | |This bit indicates the system has been reset by WWDT time-out reset or not.
+ * | | |0 = WWDT time-out reset did not occur.
+ * | | |1 = WWDT time-out reset occurred.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * @var WWDT_T::CNT
+ * Offset: 0x0C WWDT Counter Value Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CNTDAT |WWDT Counter Value
+ * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
+ */
+ __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */
+ __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */
+ __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */
+ __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */
+
+} WWDT_T;
+
+/**
+ @addtogroup WWDT_CONST WWDT Bit Field Definition
+ Constant Definitions for WWDT Controller
+@{ */
+
+#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */
+#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */
+
+#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
+#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
+
+#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
+#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
+
+#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
+#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
+
+#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
+#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
+
+#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
+#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
+
+#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
+#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
+
+#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
+#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
+
+#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
+#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
+
+/**@}*/ /* WWDT_CONST */
+/**@}*/ /* end of WWDT register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __WWDT_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/ARM/startup_M480.s b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/ARM/startup_M480.s
new file mode 100644
index 00000000000..3e31df75cb5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/ARM/startup_M480.s
@@ -0,0 +1,514 @@
+;/******************************************************************************
+; * @file startup_M480.s
+; * @version V1.00
+; * @brief CMSIS Cortex-M4 Core Device Startup File for M480
+; *
+; * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+;*****************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+ IF :LNOT: :DEF: Stack_Size
+Stack_Size EQU 0x00000800
+ ENDIF
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+ IF :LNOT: :DEF: Heap_Size
+Heap_Size EQU 0x00000100
+ ENDIF
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD BOD_IRQHandler ; 0: Brown Out detection
+ DCD IRC_IRQHandler ; 1: Internal RC
+ DCD PWRWU_IRQHandler ; 2: Power down wake up
+ DCD RAMPE_IRQHandler ; 3: RAM parity error
+ DCD CKFAIL_IRQHandler ; 4: Clock detection fail
+ DCD Default_Handler ; 5: Reserved
+ DCD RTC_IRQHandler ; 6: Real Time Clock
+ DCD TAMPER_IRQHandler ; 7: Tamper detection
+ DCD WDT_IRQHandler ; 8: Watchdog timer
+ DCD WWDT_IRQHandler ; 9: Window watchdog timer
+ DCD EINT0_IRQHandler ; 10: External Input 0
+ DCD EINT1_IRQHandler ; 11: External Input 1
+ DCD EINT2_IRQHandler ; 12: External Input 2
+ DCD EINT3_IRQHandler ; 13: External Input 3
+ DCD EINT4_IRQHandler ; 14: External Input 4
+ DCD EINT5_IRQHandler ; 15: External Input 5
+ DCD GPA_IRQHandler ; 16: GPIO Port A
+ DCD GPB_IRQHandler ; 17: GPIO Port B
+ DCD GPC_IRQHandler ; 18: GPIO Port C
+ DCD GPD_IRQHandler ; 19: GPIO Port D
+ DCD GPE_IRQHandler ; 20: GPIO Port E
+ DCD GPF_IRQHandler ; 21: GPIO Port F
+ DCD QSPI0_IRQHandler ; 22: QSPI0
+ DCD SPI0_IRQHandler ; 23: SPI0
+ DCD BRAKE0_IRQHandler ; 24:
+ DCD EPWM0P0_IRQHandler ; 25:
+ DCD EPWM0P1_IRQHandler ; 26:
+ DCD EPWM0P2_IRQHandler ; 27:
+ DCD BRAKE1_IRQHandler ; 28:
+ DCD EPWM1P0_IRQHandler ; 29:
+ DCD EPWM1P1_IRQHandler ; 30:
+ DCD EPWM1P2_IRQHandler ; 31:
+ DCD TMR0_IRQHandler ; 32: Timer 0
+ DCD TMR1_IRQHandler ; 33: Timer 1
+ DCD TMR2_IRQHandler ; 34: Timer 2
+ DCD TMR3_IRQHandler ; 35: Timer 3
+ DCD UART0_IRQHandler ; 36: UART0
+ DCD UART1_IRQHandler ; 37: UART1
+ DCD I2C0_IRQHandler ; 38: I2C0
+ DCD I2C1_IRQHandler ; 39: I2C1
+ DCD PDMA_IRQHandler ; 40: Peripheral DMA
+ DCD DAC_IRQHandler ; 41: DAC
+ DCD EADC00_IRQHandler ; 42: EADC0 interrupt source 0
+ DCD EADC01_IRQHandler ; 43: EADC0 interrupt source 1
+ DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
+ DCD Default_Handler ; 45: Reserved
+ DCD EADC02_IRQHandler ; 46: EADC0 interrupt source 2
+ DCD EADC03_IRQHandler ; 47: EADC0 interrupt source 3
+ DCD UART2_IRQHandler ; 48: UART2
+ DCD UART3_IRQHandler ; 49: UART3
+ DCD QSPI1_IRQHandler ; 50: QSPI1
+ DCD SPI1_IRQHandler ; 51: SPI1
+ DCD SPI2_IRQHandler ; 52: SPI2
+ DCD USBD_IRQHandler ; 53: USB device
+ DCD OHCI_IRQHandler ; 54: OHCI
+ DCD USBOTG_IRQHandler ; 55: USB OTG
+ DCD CAN0_IRQHandler ; 56: CAN0
+ DCD CAN1_IRQHandler ; 57: CAN1
+ DCD SC0_IRQHandler ; 58:
+ DCD SC1_IRQHandler ; 59:
+ DCD SC2_IRQHandler ; 60:
+ DCD Default_Handler ; 61:
+ DCD SPI3_IRQHandler ; 62: SPI3
+ DCD Default_Handler ; 63:
+ DCD SDH0_IRQHandler ; 64: SDH0
+ DCD USBD20_IRQHandler ; 65: USBD20
+ DCD EMAC_TX_IRQHandler ; 66: EMAC_TX
+ DCD EMAC_RX_IRQHandler ; 67: EMAX_RX
+ DCD I2S0_IRQHandler ; 68: I2S0
+ DCD Default_Handler ; 69: ToDo: Add description to this Interrupt
+ DCD OPA0_IRQHandler ; 70: OPA0
+ DCD CRYPTO_IRQHandler ; 71: CRYPTO
+ DCD GPG_IRQHandler ; 72:
+ DCD EINT6_IRQHandler ; 73:
+ DCD UART4_IRQHandler ; 74: UART4
+ DCD UART5_IRQHandler ; 75: UART5
+ DCD USCI0_IRQHandler ; 76: USCI0
+ DCD USCI1_IRQHandler ; 77: USCI1
+ DCD BPWM0_IRQHandler ; 78: BPWM0
+ DCD BPWM1_IRQHandler ; 79: BPWM1
+ DCD SPIM_IRQHandler ; 80: SPIM
+ DCD CCAP_IRQHandler ; 81: CCAP
+ DCD I2C2_IRQHandler ; 82: I2C2
+ DCD Default_Handler ; 83:
+ DCD QEI0_IRQHandler ; 84: QEI0
+ DCD QEI1_IRQHandler ; 85: QEI1
+ DCD ECAP0_IRQHandler ; 86: ECAP0
+ DCD ECAP1_IRQHandler ; 87: ECAP1
+ DCD GPH_IRQHandler ; 88:
+ DCD EINT7_IRQHandler ; 89:
+ DCD SDH1_IRQHandler ; 90: SDH1
+ DCD Default_Handler ; 91:
+ DCD EHCI_IRQHandler ; 92: EHCI
+ DCD USBOTG20_IRQHandler ; 93:
+ DCD Default_Handler ; 94:
+ DCD Default_Handler ; 95:
+ DCD Default_Handler ; 96:
+ DCD Default_Handler ; 97:
+ DCD Default_Handler ; 98:
+ DCD Default_Handler ; 99:
+ DCD Default_Handler ; 100:
+ DCD TRNG_IRQHandler ; 101: TRNG
+ DCD UART6_IRQHandler ; 102: UART6
+ DCD UART7_IRQHandler ; 103: UART7
+ DCD EADC10_IRQHandler ; 104: EADC1 interrupt source 0
+ DCD EADC11_IRQHandler ; 105: EADC1 interrupt source 1
+ DCD EADC12_IRQHandler ; 106: EADC1 interrupt source 2
+ DCD EADC13_IRQHandler ; 107: EADC1 interrupt source 3
+ DCD CAN2_IRQHandler ; 108: CAN2
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ ; Unlock Register
+ LDR R0, =0x40000100
+ LDR R1, =0x59
+ STR R1, [R0]
+ LDR R1, =0x16
+ STR R1, [R0]
+ LDR R1, =0x88
+ STR R1, [R0]
+
+ IF :LNOT: :DEF: ENABLE_SPIM_CACHE
+ LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
+ LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
+ ORR R1, R1, #0x4000
+ STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
+
+ LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
+ LDR R1, [R0,#4] ; R1 = SPIM->CTL1
+ ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk
+ STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
+ LDR R1, [R0,#4] ; R1 = SPIM->CTL1
+ ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk
+ STR R1, [R0,#4] ; _SPIM_ENABLE_CCM()
+ ENDIF
+
+ LDR R0, =SystemInit
+ BLX R0
+
+ ; Init POR
+ ; LDR R2, =0x40000024
+ ; LDR R1, =0x00005AA5
+ ; STR R1, [R2]
+
+ ; Lock
+ LDR R0, =0x40000100
+ LDR R1, =0
+ STR R1, [R0]
+
+ LDR R0, =__main
+ BX R0
+
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT IRC_IRQHandler [WEAK]
+ EXPORT PWRWU_IRQHandler [WEAK]
+ EXPORT RAMPE_IRQHandler [WEAK]
+ EXPORT CKFAIL_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT WWDT_IRQHandler [WEAK]
+ EXPORT EINT0_IRQHandler [WEAK]
+ EXPORT EINT1_IRQHandler [WEAK]
+ EXPORT EINT2_IRQHandler [WEAK]
+ EXPORT EINT3_IRQHandler [WEAK]
+ EXPORT EINT4_IRQHandler [WEAK]
+ EXPORT EINT5_IRQHandler [WEAK]
+ EXPORT GPA_IRQHandler [WEAK]
+ EXPORT GPB_IRQHandler [WEAK]
+ EXPORT GPC_IRQHandler [WEAK]
+ EXPORT GPD_IRQHandler [WEAK]
+ EXPORT GPE_IRQHandler [WEAK]
+ EXPORT GPF_IRQHandler [WEAK]
+ EXPORT QSPI0_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT BRAKE0_IRQHandler [WEAK]
+ EXPORT EPWM0P0_IRQHandler [WEAK]
+ EXPORT EPWM0P1_IRQHandler [WEAK]
+ EXPORT EPWM0P2_IRQHandler [WEAK]
+ EXPORT BRAKE1_IRQHandler [WEAK]
+ EXPORT EPWM1P0_IRQHandler [WEAK]
+ EXPORT EPWM1P1_IRQHandler [WEAK]
+ EXPORT EPWM1P2_IRQHandler [WEAK]
+ EXPORT TMR0_IRQHandler [WEAK]
+ EXPORT TMR1_IRQHandler [WEAK]
+ EXPORT TMR2_IRQHandler [WEAK]
+ EXPORT TMR3_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT PDMA_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT EADC00_IRQHandler [WEAK]
+ EXPORT EADC01_IRQHandler [WEAK]
+ EXPORT ACMP01_IRQHandler [WEAK]
+ EXPORT EADC02_IRQHandler [WEAK]
+ EXPORT EADC03_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT QSPI1_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USBD_IRQHandler [WEAK]
+ EXPORT OHCI_IRQHandler [WEAK]
+ EXPORT USBOTG_IRQHandler [WEAK]
+ EXPORT CAN0_IRQHandler [WEAK]
+ EXPORT CAN1_IRQHandler [WEAK]
+ EXPORT SC0_IRQHandler [WEAK]
+ EXPORT SC1_IRQHandler [WEAK]
+ EXPORT SC2_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT SDH0_IRQHandler [WEAK]
+ EXPORT USBD20_IRQHandler [WEAK]
+ EXPORT EMAC_TX_IRQHandler [WEAK]
+ EXPORT EMAC_RX_IRQHandler [WEAK]
+ EXPORT I2S0_IRQHandler [WEAK]
+ EXPORT OPA0_IRQHandler [WEAK]
+ EXPORT CRYPTO_IRQHandler [WEAK]
+ EXPORT GPG_IRQHandler [WEAK]
+ EXPORT EINT6_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT USCI0_IRQHandler [WEAK]
+ EXPORT USCI1_IRQHandler [WEAK]
+ EXPORT BPWM0_IRQHandler [WEAK]
+ EXPORT BPWM1_IRQHandler [WEAK]
+ EXPORT SPIM_IRQHandler [WEAK]
+ EXPORT CCAP_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT QEI0_IRQHandler [WEAK]
+ EXPORT QEI1_IRQHandler [WEAK]
+ EXPORT ECAP0_IRQHandler [WEAK]
+ EXPORT ECAP1_IRQHandler [WEAK]
+ EXPORT GPH_IRQHandler [WEAK]
+ EXPORT EINT7_IRQHandler [WEAK]
+ EXPORT SDH1_IRQHandler [WEAK]
+ EXPORT EHCI_IRQHandler [WEAK]
+ EXPORT USBOTG20_IRQHandler [WEAK]
+ EXPORT TRNG_IRQHandler [WEAK]
+ EXPORT UART6_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT EADC10_IRQHandler [WEAK]
+ EXPORT EADC11_IRQHandler [WEAK]
+ EXPORT EADC12_IRQHandler [WEAK]
+ EXPORT EADC13_IRQHandler [WEAK]
+ EXPORT CAN2_IRQHandler [WEAK]
+
+Default__IRQHandler
+BOD_IRQHandler
+IRC_IRQHandler
+PWRWU_IRQHandler
+RAMPE_IRQHandler
+CKFAIL_IRQHandler
+RTC_IRQHandler
+TAMPER_IRQHandler
+WDT_IRQHandler
+WWDT_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+EINT4_IRQHandler
+EINT5_IRQHandler
+GPA_IRQHandler
+GPB_IRQHandler
+GPC_IRQHandler
+GPD_IRQHandler
+GPE_IRQHandler
+GPF_IRQHandler
+QSPI0_IRQHandler
+SPI0_IRQHandler
+BRAKE0_IRQHandler
+EPWM0P0_IRQHandler
+EPWM0P1_IRQHandler
+EPWM0P2_IRQHandler
+BRAKE1_IRQHandler
+EPWM1P0_IRQHandler
+EPWM1P1_IRQHandler
+EPWM1P2_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+PDMA_IRQHandler
+DAC_IRQHandler
+EADC00_IRQHandler
+EADC01_IRQHandler
+ACMP01_IRQHandler
+EADC02_IRQHandler
+EADC03_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+QSPI1_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USBD_IRQHandler
+OHCI_IRQHandler
+USBOTG_IRQHandler
+CAN0_IRQHandler
+CAN1_IRQHandler
+SC0_IRQHandler
+SC1_IRQHandler
+SC2_IRQHandler
+SPI3_IRQHandler
+SDH0_IRQHandler
+USBD20_IRQHandler
+EMAC_TX_IRQHandler
+EMAC_RX_IRQHandler
+I2S0_IRQHandler
+OPA0_IRQHandler
+CRYPTO_IRQHandler
+GPG_IRQHandler
+EINT6_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+USCI0_IRQHandler
+USCI1_IRQHandler
+BPWM0_IRQHandler
+BPWM1_IRQHandler
+SPIM_IRQHandler
+CCAP_IRQHandler
+I2C2_IRQHandler
+QEI0_IRQHandler
+QEI1_IRQHandler
+ECAP0_IRQHandler
+ECAP1_IRQHandler
+GPH_IRQHandler
+EINT7_IRQHandler
+SDH1_IRQHandler
+EHCI_IRQHandler
+USBOTG20_IRQHandler
+TRNG_IRQHandler
+UART6_IRQHandler
+UART7_IRQHandler
+EADC10_IRQHandler
+EADC11_IRQHandler
+EADC12_IRQHandler
+EADC13_IRQHandler
+CAN2_IRQHandler
+
+
+
+ B .
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
+;/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/GCC/startup_M480.S b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/GCC/startup_M480.S
new file mode 100644
index 00000000000..a4eb650ee2c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/GCC/startup_M480.S
@@ -0,0 +1,375 @@
+/****************************************************************************//**
+ * @file startup_M480.S
+ * @version V1.00
+ * @brief CMSIS Cortex-M4 Core Device Startup File for M480
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+ // Unlock Register
+ ldr r0, =0x40000100
+ ldr r1, =0x59
+ str r1, [r0]
+ ldr r1, =0x16
+ str r1, [r0]
+ ldr r1, =0x88
+ str r1, [r0]
+
+#ifndef ENABLE_SPIM_CACHE
+ ldr r0, =0x40000200 // R0 = Clock Controller Register Base Address
+ ldr r1, [r0,#0x4] // R1 = 0x40000204 (AHBCLK)
+ orr r1, r1, #0x4000
+ str r1, [r0,#0x4] // CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk//
+
+ ldr r0, =0x40007000 // R0 = SPIM Register Base Address
+ ldr r1, [r0,#4] // R1 = SPIM->CTL1
+ orr r1, r1,#2 // R1 |= SPIM_CTL1_CACHEOFF_Msk
+ str r1, [r0,#4] // _SPIM_DISABLE_CACHE()
+ ldr r1, [r0,#4] // R1 = SPIM->CTL1
+ orr r1, r1, #4 // R1 |= SPIM_CTL1_CCMEN_Msk
+ str r1, [r0,#4] // _SPIM_ENABLE_CCM()
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ // Lock
+ ldr r0, =0x40000100
+ ldr r1, =0
+ str r1, [r0]
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the application's entry point.*/
+ bl entry
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack // Top of Stack
+ .word Reset_Handler // Reset Handler
+ .word NMI_Handler // NMI Handler
+ .word HardFault_Handler // Hard Fault Handler
+ .word MemManage_Handler // MPU Fault Handler
+ .word BusFault_Handler // Bus Fault Handler
+ .word UsageFault_Handler // Usage Fault Handler
+ .word 0 // Reserved
+ .word 0 // DCDReserved
+ .word 0 // Reserved
+ .word 0 // Reserved
+ .word SVC_Handler // SVCall Handler
+ .word DebugMon_Handler // Debug Monitor Handler
+ .word 0 // Reserved
+ .word PendSV_Handler // PendSV Handler
+ .word SysTick_Handler // SysTick Handler
+
+ // External Interrupts
+ .word BOD_IRQHandler /* 0: BOD */
+ .word IRC_IRQHandler /* 1: IRC */
+ .word PWRWU_IRQHandler /* 2: PWRWU */
+ .word RAMPE_IRQHandler /* 3: RAMPE */
+ .word CKFAIL_IRQHandler /* 4: CKFAIL */
+ .word 0 /* 5: Reserved */
+ .word RTC_IRQHandler /* 6: RTC */
+ .word TAMPER_IRQHandler /* 7: TAMPER */
+ .word WDT_IRQHandler /* 8: WDT */
+ .word WWDT_IRQHandler /* 9: WWDT */
+ .word EINT0_IRQHandler /* 10: EINT0 */
+ .word EINT1_IRQHandler /* 11: EINT1 */
+ .word EINT2_IRQHandler /* 12: EINT2 */
+ .word EINT3_IRQHandler /* 13: EINT3 */
+ .word EINT4_IRQHandler /* 14: EINT4 */
+ .word EINT5_IRQHandler /* 15: EINT5 */
+ .word GPA_IRQHandler /* 16: GPA */
+ .word GPB_IRQHandler /* 17: GPB */
+ .word GPC_IRQHandler /* 18: GPC */
+ .word GPD_IRQHandler /* 19: GPD */
+ .word GPE_IRQHandler /* 20: GPE */
+ .word GPF_IRQHandler /* 21: GPF */
+ .word QSPI0_IRQHandler /* 22: QSPI0 */
+ .word SPI0_IRQHandler /* 23: SPI0 */
+ .word BRAKE0_IRQHandler /* 24: BRAKE0 */
+ .word EPWM0P0_IRQHandler /* 25: EPWM0P0 */
+ .word EPWM0P1_IRQHandler /* 26: EPWM0P1 */
+ .word EPWM0P2_IRQHandler /* 27: EPWM0P2 */
+ .word BRAKE1_IRQHandler /* 28: BRAKE1 */
+ .word EPWM1P0_IRQHandler /* 29: EPWM1P0 */
+ .word EPWM1P1_IRQHandler /* 30: EPWM1P1 */
+ .word EPWM1P2_IRQHandler /* 31: EPWM1P2 */
+ .word TMR0_IRQHandler /* 32: TIMER0 */
+ .word TMR1_IRQHandler /* 33: TIMER1 */
+ .word TMR2_IRQHandler /* 34: TIMER2 */
+ .word TMR3_IRQHandler /* 35: TIMER3 */
+ .word UART0_IRQHandler /* 36: UART0 */
+ .word UART1_IRQHandler /* 37: UART1 */
+ .word I2C0_IRQHandler /* 38: I2C0 */
+ .word I2C1_IRQHandler /* 39: I2C1 */
+ .word PDMA_IRQHandler /* 40: PDMA */
+ .word DAC_IRQHandler /* 41: DAC */
+ .word EADC00_IRQHandler /* 42: EADC00 */
+ .word EADC01_IRQHandler /* 43: EADC01 */
+ .word ACMP01_IRQHandler /* 44: ACMP */
+ .word 0 /* 45: Reserved */
+ .word EADC02_IRQHandler /* 46: EADC02 */
+ .word EADC03_IRQHandler /* 47: EADC03 */
+ .word UART2_IRQHandler /* 48: UART2 */
+ .word UART3_IRQHandler /* 49: UART3 */
+ .word QSPI1_IRQHandler /* 50: QSPI1 */
+ .word SPI1_IRQHandler /* 51: SPI1 */
+ .word SPI2_IRQHandler /* 52: SPI2 */
+ .word USBD_IRQHandler /* 53: USBD */
+ .word OHCI_IRQHandler /* 54: OHCI */
+ .word USBOTG_IRQHandler /* 55: OTG */
+ .word CAN0_IRQHandler /* 56: CAN0 */
+ .word CAN1_IRQHandler /* 57: CAN1 */
+ .word SC0_IRQHandler /* 58: SC0 */
+ .word SC1_IRQHandler /* 59: SC1 */
+ .word SC2_IRQHandler /* 60: SC2 */
+ .word 0 /* 61: Reserved */
+ .word SPI3_IRQHandler /* 62: SPI3 */
+ .word 0 /* 63: Reserved */
+ .word SDH0_IRQHandler /* 64: SDH0 */
+ .word USBD20_IRQHandler /* 65: HSUSBD */
+ .word EMAC_TX_IRQHandler /* 66: EMAC_TX */
+ .word EMAC_RX_IRQHandler /* 67: EMAC_RX */
+ .word I2S0_IRQHandler /* 68: I2S */
+ .word 0 /* 69: Reserved */
+ .word OPA0_IRQHandler /* 70: OPA */
+ .word CRYPTO_IRQHandler /* 71: CRYPTO */
+ .word GPG_IRQHandler /* 72: GPG */
+ .word EINT6_IRQHandler /* 73: EINT6 */
+ .word UART4_IRQHandler /* 74: UART4 */
+ .word UART5_IRQHandler /* 75: UART5 */
+ .word USCI0_IRQHandler /* 76: USCI0 */
+ .word USCI1_IRQHandler /* 77: USCI1 */
+ .word BPWM0_IRQHandler /* 78: BPWM0 */
+ .word BPWM1_IRQHandler /* 79: BPWM1 */
+ .word SPIM_IRQHandler /* 80: SPIM */
+ .word CCAP_IRQHandler /* 81: CCAP */
+ .word I2C2_IRQHandler /* 82: I2C2 */
+ .word 0 /* 83: Reserved */
+ .word QEI0_IRQHandler /* 84: QEI0 */
+ .word QEI1_IRQHandler /* 85: QEI1 */
+ .word ECAP0_IRQHandler /* 86: ECAP0 */
+ .word ECAP1_IRQHandler /* 87: ECAP1 */
+ .word GPH_IRQHandler /* 88: GPH */
+ .word EINT7_IRQHandler /* 89: EINT7 */
+ .word SDH1_IRQHandler /* 90: SDH1 */
+ .word 0 /* 91: Reserved */
+ .word EHCI_IRQHandler /* 92: EHCI */
+ .word USBOTG20_IRQHandler /* 93: HSOTG */
+ .word 0 /* 94: Reserved */
+ .word 0 /* 95: Reserved */
+ .word 0 /* 96: Reserved */
+ .word 0 /* 97: Reserved */
+ .word 0 /* 98: Reserved */
+ .word 0 /* 99: Reserved */
+ .word 0 /* 100: Reserved */
+ .word TRNG_IRQHandler /* 101: TRNG */
+ .word UART6_IRQHandler /* 102: UART6 */
+ .word UART7_IRQHandler /* 103: UART7 */
+ .word EADC10_IRQHandler /* 104: EADC10 */
+ .word EADC11_IRQHandler /* 105: EADC11 */
+ .word EADC12_IRQHandler /* 106: EADC12 */
+ .word EADC13_IRQHandler /* 107: EADC13 */
+ .word CAN2_IRQHandler /* 108: CAN2 */
+
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler BOD_IRQHandler
+ def_irq_handler IRC_IRQHandler
+ def_irq_handler PWRWU_IRQHandler
+ def_irq_handler RAMPE_IRQHandler
+ def_irq_handler CKFAIL_IRQHandler
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler TAMPER_IRQHandler
+ def_irq_handler WDT_IRQHandler
+ def_irq_handler WWDT_IRQHandler
+ def_irq_handler EINT0_IRQHandler
+ def_irq_handler EINT1_IRQHandler
+ def_irq_handler EINT2_IRQHandler
+ def_irq_handler EINT3_IRQHandler
+ def_irq_handler EINT4_IRQHandler
+ def_irq_handler EINT5_IRQHandler
+ def_irq_handler GPA_IRQHandler
+ def_irq_handler GPB_IRQHandler
+ def_irq_handler GPC_IRQHandler
+ def_irq_handler GPD_IRQHandler
+ def_irq_handler GPE_IRQHandler
+ def_irq_handler GPF_IRQHandler
+ def_irq_handler QSPI0_IRQHandler
+ def_irq_handler SPI0_IRQHandler
+ def_irq_handler BRAKE0_IRQHandler
+ def_irq_handler EPWM0P0_IRQHandler
+ def_irq_handler EPWM0P1_IRQHandler
+ def_irq_handler EPWM0P2_IRQHandler
+ def_irq_handler BRAKE1_IRQHandler
+ def_irq_handler EPWM1P0_IRQHandler
+ def_irq_handler EPWM1P1_IRQHandler
+ def_irq_handler EPWM1P2_IRQHandler
+ def_irq_handler TMR0_IRQHandler
+ def_irq_handler TMR1_IRQHandler
+ def_irq_handler TMR2_IRQHandler
+ def_irq_handler TMR3_IRQHandler
+ def_irq_handler UART0_IRQHandler
+ def_irq_handler UART1_IRQHandler
+ def_irq_handler I2C0_IRQHandler
+ def_irq_handler I2C1_IRQHandler
+ def_irq_handler PDMA_IRQHandler
+ def_irq_handler DAC_IRQHandler
+ def_irq_handler EADC00_IRQHandler
+ def_irq_handler EADC01_IRQHandler
+ def_irq_handler ACMP01_IRQHandler
+ def_irq_handler EADC02_IRQHandler
+ def_irq_handler EADC03_IRQHandler
+ def_irq_handler UART2_IRQHandler
+ def_irq_handler UART3_IRQHandler
+ def_irq_handler QSPI1_IRQHandler
+ def_irq_handler SPI1_IRQHandler
+ def_irq_handler SPI2_IRQHandler
+ def_irq_handler USBD_IRQHandler
+ def_irq_handler OHCI_IRQHandler
+ def_irq_handler USBOTG_IRQHandler
+ def_irq_handler CAN0_IRQHandler
+ def_irq_handler CAN1_IRQHandler
+ def_irq_handler SC0_IRQHandler
+ def_irq_handler SC1_IRQHandler
+ def_irq_handler SC2_IRQHandler
+ def_irq_handler SPI3_IRQHandler
+ def_irq_handler SDH0_IRQHandler
+ def_irq_handler USBD20_IRQHandler
+ def_irq_handler EMAC_TX_IRQHandler
+ def_irq_handler EMAC_RX_IRQHandler
+ def_irq_handler I2S0_IRQHandler
+ def_irq_handler OPA0_IRQHandler
+ def_irq_handler CRYPTO_IRQHandler
+ def_irq_handler GPG_IRQHandler
+ def_irq_handler EINT6_IRQHandler
+ def_irq_handler UART4_IRQHandler
+ def_irq_handler UART5_IRQHandler
+ def_irq_handler USCI0_IRQHandler
+ def_irq_handler USCI1_IRQHandler
+ def_irq_handler BPWM0_IRQHandler
+ def_irq_handler BPWM1_IRQHandler
+ def_irq_handler SPIM_IRQHandler
+ def_irq_handler CCAP_IRQHandler
+ def_irq_handler I2C2_IRQHandler
+ def_irq_handler QEI0_IRQHandler
+ def_irq_handler QEI1_IRQHandler
+ def_irq_handler ECAP0_IRQHandler
+ def_irq_handler ECAP1_IRQHandler
+ def_irq_handler GPH_IRQHandler
+ def_irq_handler EINT7_IRQHandler
+ def_irq_handler SDH1_IRQHandler
+ def_irq_handler EHCI_IRQHandler
+ def_irq_handler USBOTG20_IRQHandler
+ def_irq_handler TRNG_IRQHandler
+ def_irq_handler UART6_IRQHandler
+ def_irq_handler UART7_IRQHandler
+ def_irq_handler EADC10_IRQHandler
+ def_irq_handler EADC11_IRQHandler
+ def_irq_handler EADC12_IRQHandler
+ def_irq_handler EADC13_IRQHandler
+ def_irq_handler CAN2_IRQHandler
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/IAR/startup_M480.s b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/IAR/startup_M480.s
new file mode 100644
index 00000000000..9aa379a7584
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/IAR/startup_M480.s
@@ -0,0 +1,451 @@
+;/******************************************************************************
+; * @file startup_M480.s
+; * @version V1.00
+; * @brief CMSIS Cortex-M4 Core Device Startup File for M480
+; *
+; * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+;*****************************************************************************/
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN HardFault_Handler
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD BOD_IRQHandler ; 0: Brown Out detection
+ DCD IRC_IRQHandler ; 1: Internal RC
+ DCD PWRWU_IRQHandler ; 2: Power down wake up
+ DCD RAMPE_IRQHandler ; 3: RAM parity error
+ DCD CKFAIL_IRQHandler ; 4: Clock detection fail
+ DCD Default_Handler ; 5: Reserved
+ DCD RTC_IRQHandler ; 6: Real Time Clock
+ DCD TAMPER_IRQHandler ; 7: Tamper detection
+ DCD WDT_IRQHandler ; 8: Watchdog timer
+ DCD WWDT_IRQHandler ; 9: Window watchdog timer
+ DCD EINT0_IRQHandler ; 10: External Input 0
+ DCD EINT1_IRQHandler ; 11: External Input 1
+ DCD EINT2_IRQHandler ; 12: External Input 2
+ DCD EINT3_IRQHandler ; 13: External Input 3
+ DCD EINT4_IRQHandler ; 14: External Input 4
+ DCD EINT5_IRQHandler ; 15: External Input 5
+ DCD GPA_IRQHandler ; 16: GPIO Port A
+ DCD GPB_IRQHandler ; 17: GPIO Port B
+ DCD GPC_IRQHandler ; 18: GPIO Port C
+ DCD GPD_IRQHandler ; 19: GPIO Port D
+ DCD GPE_IRQHandler ; 20: GPIO Port E
+ DCD GPF_IRQHandler ; 21: GPIO Port F
+ DCD QSPI0_IRQHandler ; 22: QSPI0
+ DCD SPI0_IRQHandler ; 23: SPI0
+ DCD BRAKE0_IRQHandler ; 24:
+ DCD PWM0P0_IRQHandler ; 25:
+ DCD PWM0P1_IRQHandler ; 26:
+ DCD PWM0P2_IRQHandler ; 27:
+ DCD BRAKE1_IRQHandler ; 28:
+ DCD PWM1P0_IRQHandler ; 29:
+ DCD PWM1P1_IRQHandler ; 30:
+ DCD PWM1P2_IRQHandler ; 31:
+ DCD TMR0_IRQHandler ; 32: Timer 0
+ DCD TMR1_IRQHandler ; 33: Timer 1
+ DCD TMR2_IRQHandler ; 34: Timer 2
+ DCD TMR3_IRQHandler ; 35: Timer 3
+ DCD UART0_IRQHandler ; 36: UART0
+ DCD UART1_IRQHandler ; 37: UART1
+ DCD I2C0_IRQHandler ; 38: I2C0
+ DCD I2C1_IRQHandler ; 39: I2C1
+ DCD PDMA_IRQHandler ; 40: Peripheral DMA
+ DCD DAC_IRQHandler ; 41: DAC
+ DCD EADC00_IRQHandler ; 42: EADC0 interrupt source 0
+ DCD EADC01_IRQHandler ; 43: EADC0 interrupt source 1
+ DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
+ DCD Default_Handler ; 45: Reserved
+ DCD EADC02_IRQHandler ; 46: EADC0 interrupt source 2
+ DCD EADC03_IRQHandler ; 47: EADC0 interrupt source 3
+ DCD UART2_IRQHandler ; 48: UART2
+ DCD UART3_IRQHandler ; 49: UART3
+ DCD QSPI1_IRQHandler ; 50: QSPI1
+ DCD SPI1_IRQHandler ; 51: SPI1
+ DCD SPI2_IRQHandler ; 52: SPI2
+ DCD USBD_IRQHandler ; 53: USB device
+ DCD OHCI_IRQHandler ; 54: OHCI
+ DCD USBOTG_IRQHandler ; 55: USB OTG
+ DCD CAN0_IRQHandler ; 56: CAN0
+ DCD CAN1_IRQHandler ; 57: CAN1
+ DCD SC0_IRQHandler ; 58:
+ DCD SC1_IRQHandler ; 59:
+ DCD SC2_IRQHandler ; 60:
+ DCD Default_Handler ; 61:
+ DCD SPI3_IRQHandler ; 62: SPI3
+ DCD Default_Handler ; 63:
+ DCD SDH0_IRQHandler ; 64: SDH0
+ DCD USBD20_IRQHandler ; 65: USBD20
+ DCD EMAC_TX_IRQHandler ; 66: EMAC_TX
+ DCD EMAC_RX_IRQHandler ; 67: EMAX_RX
+ DCD I2S0_IRQHandler ; 68: I2S0
+ DCD Default_Handler ; 69: ToDo: Add description to this Interrupt
+ DCD OPA0_IRQHandler ; 70: OPA0
+ DCD CRYPTO_IRQHandler ; 71: CRYPTO
+ DCD GPG_IRQHandler ; 72:
+ DCD EINT6_IRQHandler ; 73:
+ DCD UART4_IRQHandler ; 74: UART4
+ DCD UART5_IRQHandler ; 75: UART5
+ DCD USCI0_IRQHandler ; 76: USCI0
+ DCD USCI1_IRQHandler ; 77: USCI1
+ DCD BPWM0_IRQHandler ; 78: BPWM0
+ DCD BPWM1_IRQHandler ; 79: BPWM1
+ DCD SPIM_IRQHandler ; 80: SPIM
+ DCD CCAP_IRQHandler ; 81: CCAP
+ DCD I2C2_IRQHandler ; 82: I2C2
+ DCD Default_Handler ; 83:
+ DCD QEI0_IRQHandler ; 84: QEI0
+ DCD QEI1_IRQHandler ; 85: QEI1
+ DCD ECAP0_IRQHandler ; 86: ECAP0
+ DCD ECAP1_IRQHandler ; 87: ECAP1
+ DCD GPH_IRQHandler ; 88:
+ DCD EINT7_IRQHandler ; 89:
+ DCD SDH1_IRQHandler ; 90: SDH1
+ DCD Default_Handler ; 91:
+ DCD EHCI_IRQHandler ; 92: EHCI
+ DCD USBOTG20_IRQHandler ; 93:
+ DCD Default_Handler ; 94:
+ DCD Default_Handler ; 95:
+ DCD Default_Handler ; 96:
+ DCD Default_Handler ; 97:
+ DCD Default_Handler ; 98:
+ DCD Default_Handler ; 99:
+ DCD Default_Handler ; 100:
+ DCD TRNG_IRQHandler ; 101: TRNG
+ DCD UART6_IRQHandler ; 102: UART6
+ DCD UART7_IRQHandler ; 103: UART7
+ DCD EADC10_IRQHandler ; 104: EADC1 interrupt source 0
+ DCD EADC11_IRQHandler ; 105: EADC1 interrupt source 1
+ DCD EADC12_IRQHandler ; 106: EADC1 interrupt source 2
+ DCD EADC13_IRQHandler ; 107: EADC1 interrupt source 3
+ DCD CAN2_IRQHandler ; 108: CAN2
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ ; Unlock Register
+ LDR R0, =0x40000100
+ LDR R1, =0x59
+ STR R1, [R0]
+ LDR R1, =0x16
+ STR R1, [R0]
+ LDR R1, =0x88
+ STR R1, [R0]
+
+ #ifndef ENABLE_SPIM_CACHE
+ LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
+ LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
+ ORR R1, R1, #0x4000
+ STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
+
+ LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
+ LDR R1, [R0,#4] ; R1 = SPIM->CTL1
+ ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk
+ STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
+ LDR R1, [R0,#4] ; R1 = SPIM->CTL1
+ ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk
+ STR R1, [R0,#4] ; _SPIM_ENABLE_CCM()
+ #endif
+
+ LDR R0, =SystemInit
+ BLX R0
+
+ ; Init POR
+ ; LDR R2, =0x40000024
+ ; LDR R1, =0x00005AA5
+ ; STR R1, [R2]
+
+ ; Lock register
+ LDR R0, =0x40000100
+ MOVS R1, #0
+ STR R1, [R0]
+
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK IRC_IRQHandler
+ PUBWEAK PWRWU_IRQHandler
+ PUBWEAK RAMPE_IRQHandler
+ PUBWEAK CKFAIL_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK TAMPER_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK WWDT_IRQHandler
+ PUBWEAK EINT0_IRQHandler
+ PUBWEAK EINT1_IRQHandler
+ PUBWEAK EINT2_IRQHandler
+ PUBWEAK EINT3_IRQHandler
+ PUBWEAK EINT4_IRQHandler
+ PUBWEAK EINT5_IRQHandler
+ PUBWEAK GPA_IRQHandler
+ PUBWEAK GPB_IRQHandler
+ PUBWEAK GPC_IRQHandler
+ PUBWEAK GPD_IRQHandler
+ PUBWEAK GPE_IRQHandler
+ PUBWEAK GPF_IRQHandler
+ PUBWEAK QSPI0_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK BRAKE0_IRQHandler
+ PUBWEAK PWM0P0_IRQHandler
+ PUBWEAK PWM0P1_IRQHandler
+ PUBWEAK PWM0P2_IRQHandler
+ PUBWEAK BRAKE1_IRQHandler
+ PUBWEAK PWM1P0_IRQHandler
+ PUBWEAK PWM1P1_IRQHandler
+ PUBWEAK PWM1P2_IRQHandler
+ PUBWEAK TMR0_IRQHandler
+ PUBWEAK TMR1_IRQHandler
+ PUBWEAK TMR2_IRQHandler
+ PUBWEAK TMR3_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK PDMA_IRQHandler
+ PUBWEAK DAC_IRQHandler
+ PUBWEAK EADC00_IRQHandler
+ PUBWEAK EADC01_IRQHandler
+ PUBWEAK ACMP01_IRQHandler
+ PUBWEAK EADC02_IRQHandler
+ PUBWEAK EADC03_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK UART3_IRQHandler
+ PUBWEAK QSPI1_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK SPI2_IRQHandler
+ PUBWEAK USBD_IRQHandler
+ PUBWEAK OHCI_IRQHandler
+ PUBWEAK USBOTG_IRQHandler
+ PUBWEAK CAN0_IRQHandler
+ PUBWEAK CAN1_IRQHandler
+ PUBWEAK SC0_IRQHandler
+ PUBWEAK SC1_IRQHandler
+ PUBWEAK SC2_IRQHandler
+ PUBWEAK SPI3_IRQHandler
+ PUBWEAK SDH0_IRQHandler
+ PUBWEAK USBD20_IRQHandler
+ PUBWEAK EMAC_TX_IRQHandler
+ PUBWEAK EMAC_RX_IRQHandler
+ PUBWEAK I2S0_IRQHandler
+ PUBWEAK OPA0_IRQHandler
+ PUBWEAK CRYPTO_IRQHandler
+ PUBWEAK GPG_IRQHandler
+ PUBWEAK EINT6_IRQHandler
+ PUBWEAK UART4_IRQHandler
+ PUBWEAK UART5_IRQHandler
+ PUBWEAK USCI0_IRQHandler
+ PUBWEAK USCI1_IRQHandler
+ PUBWEAK BPWM0_IRQHandler
+ PUBWEAK BPWM1_IRQHandler
+ PUBWEAK SPIM_IRQHandler
+ PUBWEAK CCAP_IRQHandler
+ PUBWEAK I2C2_IRQHandler
+ PUBWEAK QEI0_IRQHandler
+ PUBWEAK QEI1_IRQHandler
+ PUBWEAK ECAP0_IRQHandler
+ PUBWEAK ECAP1_IRQHandler
+ PUBWEAK GPH_IRQHandler
+ PUBWEAK EINT7_IRQHandler
+ PUBWEAK SDH1_IRQHandler
+ PUBWEAK EHCI_IRQHandler
+ PUBWEAK USBOTG20_IRQHandler
+ PUBWEAK TRNG_IRQHandler
+ PUBWEAK UART6_IRQHandler
+ PUBWEAK UART7_IRQHandler
+ PUBWEAK EADC10_IRQHandler
+ PUBWEAK EADC11_IRQHandler
+ PUBWEAK EADC12_IRQHandler
+ PUBWEAK EADC13_IRQHandler
+ PUBWEAK CAN2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+
+BOD_IRQHandler
+IRC_IRQHandler
+PWRWU_IRQHandler
+RAMPE_IRQHandler
+CKFAIL_IRQHandler
+RTC_IRQHandler
+TAMPER_IRQHandler
+WDT_IRQHandler
+WWDT_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+EINT4_IRQHandler
+EINT5_IRQHandler
+GPA_IRQHandler
+GPB_IRQHandler
+GPC_IRQHandler
+GPD_IRQHandler
+GPE_IRQHandler
+GPF_IRQHandler
+QSPI0_IRQHandler
+SPI0_IRQHandler
+BRAKE0_IRQHandler
+PWM0P0_IRQHandler
+PWM0P1_IRQHandler
+PWM0P2_IRQHandler
+BRAKE1_IRQHandler
+PWM1P0_IRQHandler
+PWM1P1_IRQHandler
+PWM1P2_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+PDMA_IRQHandler
+DAC_IRQHandler
+EADC00_IRQHandler
+EADC01_IRQHandler
+ACMP01_IRQHandler
+EADC02_IRQHandler
+EADC03_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+QSPI1_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USBD_IRQHandler
+OHCI_IRQHandler
+USBOTG_IRQHandler
+CAN0_IRQHandler
+CAN1_IRQHandler
+SC0_IRQHandler
+SC1_IRQHandler
+SC2_IRQHandler
+SPI3_IRQHandler
+SDH0_IRQHandler
+USBD20_IRQHandler
+EMAC_TX_IRQHandler
+EMAC_RX_IRQHandler
+I2S0_IRQHandler
+OPA0_IRQHandler
+CRYPTO_IRQHandler
+GPG_IRQHandler
+EINT6_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+USCI0_IRQHandler
+USCI1_IRQHandler
+BPWM0_IRQHandler
+BPWM1_IRQHandler
+SPIM_IRQHandler
+CCAP_IRQHandler
+I2C2_IRQHandler
+QEI0_IRQHandler
+QEI1_IRQHandler
+ECAP0_IRQHandler
+ECAP1_IRQHandler
+GPH_IRQHandler
+EINT7_IRQHandler
+SDH1_IRQHandler
+EHCI_IRQHandler
+USBOTG20_IRQHandler
+TRNG_IRQHandler
+UART6_IRQHandler
+UART7_IRQHandler
+EADC10_IRQHandler
+EADC11_IRQHandler
+EADC12_IRQHandler
+EADC13_IRQHandler
+CAN2_IRQHandler
+Default_Handler
+ B Default_Handler
+
+
+
+
+ END
+;/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/system_M480.c b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/system_M480.c
new file mode 100644
index 00000000000..76573a4a3e4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/system_M480.c
@@ -0,0 +1,110 @@
+/**************************************************************************//**
+ * @file system_M480.c
+ * @version V1.000
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include "NuMicro.h"
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */
+uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
+uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC};
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t u32Freq, u32ClkSrc;
+ uint32_t u32HclkDiv;
+
+ /* Update PLL Clock */
+ PllClock = CLK_GetPLLClockFreq();
+
+ u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
+
+ if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
+ {
+ /* Use PLL clock */
+ u32Freq = PllClock;
+ }
+ else
+ {
+ /* Use the clock sources directly */
+ u32Freq = gau32ClkSrcTbl[u32ClkSrc];
+ }
+
+ u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
+
+ /* Update System Core Clock */
+ SystemCoreClock = u32Freq / u32HclkDiv;
+
+
+ //if(SystemCoreClock == 0)
+ // __BKPT(0);
+
+ CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
+}
+
+/**
+ * @brief Set PF.2 and PF.3 to input mode
+ * @param None
+ * @return None
+ * @details GPIO default state could be configured as input or quasi through user config.
+ * To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes
+ * PF.2 and PF.3 to input mode no matter which mode they are working at.
+ */
+static __INLINE void HXTInit(void)
+{
+ PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
+
+}
+
+/**
+ * @brief Initialize the System
+ *
+ * @param none
+ * @return none
+ */
+void SystemInit (void)
+{
+ /* Add your system initialize code here.
+ Do not use global variables because this function is called before
+ reaching pre-main. RW section maybe overwritten afterwards. */
+
+
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
+ (3UL << 11*2) ); /* set CP11 Full Access */
+#endif
+
+ /* Set access cycle for CPU @ 192MHz */
+ FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos);
+ /* Configure power down bias, must set 1 before entering power down mode.
+ So set it at the very beginning */
+ CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk;
+ /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */
+ CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
+ RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk |
+ RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk);
+ RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk |
+ RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk);
+ CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
+ HXTInit();
+
+}
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/Device/SConscript b/bsp/nuvoton/libraries/m480/Device/SConscript
new file mode 100644
index 00000000000..26e69fb8240
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/Device/SConscript
@@ -0,0 +1,25 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+Nuvoton/M480/Source/system_M480.c
+""")
+
+# add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+ src = src + ['Nuvoton/M480/Source/GCC/startup_M480.S']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src = src + ['Nuvoton/M480/Source/ARM/startup_M480.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src = src + ['Nuvoton/M480/Source/IAR/startup_M480.s']
+
+path = [cwd + '/Nuvoton/M480/Include',]
+
+group = DefineGroup('m480_device', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/nuvoton/libraries/m480/README.md b/bsp/nuvoton/libraries/m480/README.md
new file mode 100644
index 00000000000..e64b8733212
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/README.md
@@ -0,0 +1,49 @@
+# M480 Series
+
+## Supported drivers
+
+| Peripheral | rt_device_class_type | Device name |
+| ------ | ---- | :------: |
+| BPWM | RT_Device_Class_Miscellaneous (PWM) | ***bpwm[0-1]*** |
+| BPWM (Capture function)| RT_Device_Class_Miscellaneous (Input capture) | ***bpwm[0-1]i[0-5]*** |
+| CAN | RT_Device_Class_CAN | ***can[0-1]*** |
+| CLK | RT_Device_Class_PM | ***pm*** |
+| CRC | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** |
+| CRYPTO | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** |
+| EADC | RT_Device_Class_Miscellaneous (ADC) | ***eadc[0-1]*** |
+| EBI | N/A | ***N/A*** |
+| ECAP | RT_Device_Class_Miscellaneous (Input capture) | ***ecap[0-1]i[0-2]*** |
+| EMAC | RT_Device_Class_NetIf | ***e0*** |
+| EPWM | RT_Device_Class_Miscellaneous (PWM) | ***epwm[0-1]*** |
+| EPWM (Capture function) | RT_Device_Class_Miscellaneous (Input capture) | ***epwm[0-1]i[0-5]*** |
+| FMC | FAL | ***N/A*** |
+| GPIO | RT_Device_Class_Miscellaneous (Pin) | ***gpio*** |
+| GPIO | RT_Device_Class_I2CBUS | ***softi2c0[0-1]*** |
+| HSOTG | RT_Device_Class_USBHost/RT_Device_Class_USBDevice | ***N/A*** |
+| HSUSBD | RT_Device_Class_USBDevice | ***usbd*** |
+| I2C | RT_Device_Class_I2CBUS | ***i2c[0-2]*** |
+| I2S | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***sound0*** |
+| PDMA | N/A | ***N/A*** |
+| QEI | RT_Device_Class_Miscellaneous (Pulse encoder) | ***qei[0-1]*** |
+| QSPI | RT_Device_Class_SPIBUS | ***qspi[0-1]*** |
+| RTC | RT_Device_Class_RTC | ***rtc*** |
+| SC (UART function) | RT_Device_Class_Char | ***scuart[0-2]*** |
+| SDH | RT_Device_Class_Block | ***sdh[0-1]*** |
+| SPI | RT_Device_Class_SPIBUS | ***spi[0-3]*** |
+| SPI (I2S function) | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***spii2s[0-3]*** |
+| TIMER | RT_Device_Class_Timer | ***timer[0-3]*** |
+| TIMER (Capture function) | RT_Device_Class_Miscellaneous (Input capture) | ***timer[0-3]i0*** |
+| TIMER (PWM function) | RT_Device_Class_Miscellaneous (PWM) | ***tpwm[0-3]*** |
+| TRNG | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** |
+| UART | RT_Device_Class_Char | ***uart[0-7]*** |
+| USBD | RT_Device_Class_USBDevice | ***usbd*** |
+| USBH, HSUSBH | RT_Device_Class_USBHost | ***usbh*** |
+| USCI (I2C function) | RT_Device_Class_I2CBUS | ***ui2c[0-1]*** |
+| USCI (SPI function) | RT_Device_Class_SPIBUS | ***uspi[0-1]*** |
+| USCI (UART function) | RT_Device_Class_Char | ***uuart[0-1]*** |
+| WDT | RT_Device_Class_Miscellaneous (Watchdog) | ***wdt*** |
+
+## Resources
+* [Download M480 TRM][1]
+
+ [1]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=DA05-M480
diff --git a/bsp/nuvoton/libraries/m480/SConscript b/bsp/nuvoton/libraries/m480/SConscript
new file mode 100644
index 00000000000..4c815c49b83
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/SConscript b/bsp/nuvoton/libraries/m480/StdDriver/SConscript
new file mode 100644
index 00000000000..6a932cff584
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/SConscript
@@ -0,0 +1,28 @@
+# RT-Thread building script for component
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+libs = []
+src = Glob('*src/*.c') + Glob('src/*.cpp')
+cpppath = [cwd + '/inc']
+libpath = [cwd + '/lib']
+
+if not GetDepend('BSP_USE_STDDRIVER_SOURCE'):
+ if rtconfig.CROSS_TOOL == 'keil':
+ if GetOption('target') == 'mdk5' and os.path.isfile('./lib/libstddriver_keil.lib'):
+ libs += ['libstddriver_keil']
+ elif GetOption('target') == 'mdk4' and os.path.isfile('./lib/libstddriver_keil4.lib'):
+ libs += ['libstddriver_keil4']
+ elif rtconfig.CROSS_TOOL == 'gcc' and os.path.isfile('./lib/libstddriver_gcc.a'):
+ libs += ['libstddriver_gcc']
+ elif os.path.isfile('./lib/libstddriver_iar.a'):
+ libs += ['libstddriver_iar']
+
+if not libs:
+ group = DefineGroup('m480_stddriver', src, depend = [''], CPPPATH = cpppath)
+else:
+ src = []
+ group = DefineGroup('m480_stddriver', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath)
+
+Return('group')
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_acmp.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_acmp.h
new file mode 100644
index 00000000000..23db060037d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_acmp.h
@@ -0,0 +1,415 @@
+/**************************************************************************//**
+ * @file ACMP.h
+ * @version V1.00
+ * @brief M480 Series ACMP Driver Header File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_ACMP_H__
+#define __NU_ACMP_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+
+/** @addtogroup ACMP_Driver ACMP Driver
+ @{
+*/
+
+
+/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
+ @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_CTL constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_CTL_FILTSEL_OFF (0UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for filter function disabled. \hideinitializer */
+#define ACMP_CTL_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 1 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 2 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 4 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 8 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 16 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 32 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 64 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_INTPOL_RF (0UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. \hideinitializer */
+#define ACMP_CTL_INTPOL_R (1UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. \hideinitializer */
+#define ACMP_CTL_INTPOL_F (2UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. \hideinitializer */
+#define ACMP_CTL_POSSEL_P0 (0UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. \hideinitializer */
+#define ACMP_CTL_POSSEL_P1 (1UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. \hideinitializer */
+#define ACMP_CTL_POSSEL_P2 (2UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. \hideinitializer */
+#define ACMP_CTL_POSSEL_P3 (3UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. \hideinitializer */
+#define ACMP_CTL_NEGSEL_PIN (0UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. \hideinitializer */
+#define ACMP_CTL_NEGSEL_CRV (1UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. \hideinitializer */
+#define ACMP_CTL_NEGSEL_VBG (2UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. \hideinitializer */
+#define ACMP_CTL_NEGSEL_DAC (3UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. \hideinitializer */
+#define ACMP_CTL_HYSTERESIS_30MV (3UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. \hideinitializer */
+#define ACMP_CTL_HYSTERESIS_20MV (2UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. \hideinitializer */
+#define ACMP_CTL_HYSTERESIS_10MV (1UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. \hideinitializer */
+#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for disabling the hysteresis function. \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_VREF constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_VREF_CRVSSEL_VDDA (0UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage \hideinitializer */
+#define ACMP_VREF_CRVSSEL_INTVREF (1UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage \hideinitializer */
+
+
+/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Macros and functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+ * @brief This macro is used to enable output inverse function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.
+ * \hideinitializer
+ */
+#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk)
+
+/**
+ * @brief This macro is used to disable output inverse function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.
+ * \hideinitializer
+ */
+#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk)
+
+/**
+ * @brief This macro is used to select ACMP negative input source
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @param[in] u32Src is comparator negative input selection. Including:
+ * - \ref ACMP_CTL_NEGSEL_PIN
+ * - \ref ACMP_CTL_NEGSEL_CRV
+ * - \ref ACMP_CTL_NEGSEL_VBG
+ * - \ref ACMP_CTL_NEGSEL_DAC
+ * @return None
+ * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.
+ * \hideinitializer
+ */
+#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))
+
+/**
+ * @brief This macro is used to enable hysteresis function and set hysteresis to 30mV
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * \hideinitializer
+ */
+#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV)
+
+/**
+ * @brief This macro is used to disable hysteresis function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear HYSEL bits of ACMP_CTL register to disable hysteresis function.
+ * \hideinitializer
+ */
+#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk)
+
+/**
+ * @brief This macro is used to select hysteresis level
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @param[in] u32HysSel The hysteresis function option. Including:
+ * - \ref ACMP_CTL_HYSTERESIS_30MV
+ * - \ref ACMP_CTL_HYSTERESIS_20MV
+ * - \ref ACMP_CTL_HYSTERESIS_10MV
+ * - \ref ACMP_CTL_HYSTERESIS_DISABLE
+ * \hideinitializer
+ * @return None
+ */
+#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel))
+
+/**
+ * @brief This macro is used to enable interrupt
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.
+ * If wake-up function is enabled, the wake-up interrupt will be enabled as well.
+ * \hideinitializer
+ */
+#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)
+
+/**
+ * @brief This macro is used to disable interrupt
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.
+ * \hideinitializer
+ */
+#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)
+
+/**
+ * @brief This macro is used to enable ACMP
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.
+ * \hideinitializer
+ */
+#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)
+
+/**
+ * @brief This macro is used to disable ACMP
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
+ * \hideinitializer
+ */
+#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)
+
+/**
+ * @brief This macro is used to get ACMP output value
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return ACMP output value
+ * @details This macro will return the ACMP output value.
+ * \hideinitializer
+ */
+#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0)
+
+/**
+ * @brief This macro is used to get ACMP interrupt flag
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return ACMP interrupt occurred (1) or not (0)
+ * @details This macro will return the ACMP interrupt flag.
+ * \hideinitializer
+ */
+#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0)
+
+/**
+ * @brief This macro is used to clear ACMP interrupt flag
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.
+ * \hideinitializer
+ */
+#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))
+
+/**
+ * @brief This macro is used to clear ACMP wake-up interrupt flag
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.
+ * \hideinitializer
+ */
+#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum))))
+
+/**
+ * @brief This macro is used to enable ACMP wake-up function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.
+ * \hideinitializer
+ */
+#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk)
+
+/**
+ * @brief This macro is used to disable ACMP wake-up function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.
+ * \hideinitializer
+ */
+#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk)
+
+/**
+ * @brief This macro is used to select ACMP positive input pin
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @param[in] u32Pin Comparator positive pin selection. Including:
+ * - \ref ACMP_CTL_POSSEL_P0
+ * - \ref ACMP_CTL_POSSEL_P1
+ * - \ref ACMP_CTL_POSSEL_P2
+ * - \ref ACMP_CTL_POSSEL_P3
+ * @return None
+ * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.
+ * \hideinitializer
+ */
+#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
+
+/**
+ * @brief This macro is used to enable ACMP filter function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.
+ * \hideinitializer
+ */
+#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk)
+
+/**
+ * @brief This macro is used to disable ACMP filter function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.
+ * \hideinitializer
+ */
+#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk)
+
+/**
+ * @brief This macro is used to set ACMP filter function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @param[in] u32Cnt is comparator filter count setting.
+ * - \ref ACMP_CTL_FILTSEL_OFF
+ * - \ref ACMP_CTL_FILTSEL_1PCLK
+ * - \ref ACMP_CTL_FILTSEL_2PCLK
+ * - \ref ACMP_CTL_FILTSEL_4PCLK
+ * - \ref ACMP_CTL_FILTSEL_8PCLK
+ * - \ref ACMP_CTL_FILTSEL_16PCLK
+ * - \ref ACMP_CTL_FILTSEL_32PCLK
+ * - \ref ACMP_CTL_FILTSEL_64PCLK
+ * @return None
+ * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).
+ * \hideinitializer
+ */
+#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
+
+/**
+ * @brief This macro is used to select comparator reference voltage
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32Level The comparator reference voltage setting.
+ * The formula is:
+ * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)
+ * The range of u32Level is 0 ~ 15.
+ * @return None
+ * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).
+ * \hideinitializer
+ */
+#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src))
+
+/**
+ * @brief This macro is used to select ACMP interrupt condition
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @param[in] u32Cond Comparator interrupt condition selection. Including:
+ * - \ref ACMP_CTL_INTPOL_RF
+ * - \ref ACMP_CTL_INTPOL_R
+ * - \ref ACMP_CTL_INTPOL_F
+ * @return None
+ * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.
+ * \hideinitializer
+ */
+#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))
+
+/**
+ * @brief This macro is used to enable ACMP window latch mode
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode.
+ * When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch
+ * block; when ACMP0/1_WLAT pin is at low level, the output of window latch block,
+ * WLATOUT, is frozen.
+ * \hideinitializer
+ */
+#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk)
+
+/**
+ * @brief This macro is used to disable ACMP window latch mode
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode.
+ * \hideinitializer
+ */
+#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk)
+
+/**
+ * @brief This macro is used to enable ACMP window compare mode
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode.
+ * When window compare mode is enabled, user can connect the specific analog voltage
+ * source to either the positive inputs of both comparators or the negative inputs of
+ * both comparators. The upper bound and lower bound of the designated range are
+ * determined by the voltages applied to the other inputs of both comparators. If the
+ * output of a comparator is low and the other comparator outputs high, which means two
+ * comparators implies the upper and lower bound. User can directly monitor a specific
+ * analog voltage source via ACMPWO (ACMP_STATUS[16]).
+ * \hideinitializer
+ */
+#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk)
+
+/**
+ * @brief This macro is used to disable ACMP window compare mode
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode.
+ * \hideinitializer
+ */
+#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk)
+
+
+
+
+/* Function prototype declaration */
+void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel);
+void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);
+
+
+
+/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group ACMP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __NU_ACMP_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_bpwm.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_bpwm.h
new file mode 100644
index 00000000000..04e65f601a5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_bpwm.h
@@ -0,0 +1,361 @@
+/**************************************************************************//**
+ * @file nu_bpwm.h
+ * @version V1.00
+ * @brief M480 series PWM driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_BPWM_H__
+#define __NU_BPWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup BPWM_Driver BPWM Driver
+ @{
+*/
+
+/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants
+ @{
+*/
+#define BPWM_CHANNEL_NUM (6) /*!< BPWM channel number \hideinitializer */
+#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */
+#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */
+#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */
+#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */
+#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */
+#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Counter Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_UP_COUNTER (0UL) /*!< Up counter type \hideinitializer */
+#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type \hideinitializer */
+#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Aligned Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) \hideinitializer */
+#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Output Level Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing \hideinitializer */
+#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low \hideinitializer */
+#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high \hideinitializer */
+#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Synchronous Start Function Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_SSCTL_SSRC_PWM0 (0UL<SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk)
+
+/**
+ * @brief Disable timer synchronous start counting function of specified channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This macro is used to disable timer synchronous start counting function of specified channel(s).
+ * @note All channels share channel 0's setting.
+ * \hideinitializer
+ */
+#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk)
+
+/**
+ * @brief This macro enable BPWM counter synchronous start counting function.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @return None
+ * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time.
+ * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC().
+ * \hideinitializer
+ */
+#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk)
+
+/**
+ * @brief This macro enable output inverter of specified channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask))
+
+/**
+ * @brief This macro get captured rising data
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
+
+/**
+ * @brief This macro get captured falling data
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
+
+/**
+ * @brief This macro mask output logic to high or low
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32LevelMask Output logic to high or low
+ * @return None
+ * @details This macro is used to mask output logic to high or low of specified channel(s).
+ * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
+ * \hideinitializer
+ */
+#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \
+ { \
+ (bpwm)->MSKEN = (u32ChannelMask); \
+ (bpwm)->MSK = (u32LevelMask); \
+ }
+
+/**
+ * @brief This macro set the prescaler of all channels
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler))
+
+/**
+ * @brief This macro set the duty of the selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @note This new setting will take effect on next BPWM period
+ * \hideinitializer
+ */
+#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
+
+/**
+ * @brief This macro get the duty of the selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)])
+
+/**
+ * @brief This macro set the period of all channels
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @note This new setting will take effect on next BPWM period
+ * @note BPWM counter will stop if period length set to 0
+ * \hideinitializer
+ */
+#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR))
+
+/**
+ * @brief This macro get the period of all channels
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD)
+
+/**
+ * @brief This macro set the BPWM aligned type
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @param[in] u32AlignedType BPWM aligned type, valid values are:
+ * - \ref BPWM_EDGE_ALIGNED
+ * - \ref BPWM_CENTER_ALIGNED
+ * @return None
+ * @note All channels share channel 0's setting.
+ * \hideinitializer
+ */
+#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType))
+
+/**
+ * @brief Clear counter of channel 0
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This macro is used to clear counter of channel 0
+ * \hideinitializer
+ */
+#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk))
+
+/**
+ * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32ZeroLevel output level at zero point, valid values are:
+ * - \ref BPWM_OUTPUT_NOTHING
+ * - \ref BPWM_OUTPUT_LOW
+ * - \ref BPWM_OUTPUT_HIGH
+ * - \ref BPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
+ * - \ref BPWM_OUTPUT_NOTHING
+ * - \ref BPWM_OUTPUT_LOW
+ * - \ref BPWM_OUTPUT_HIGH
+ * - \ref BPWM_OUTPUT_TOGGLE
+ * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
+ * - \ref BPWM_OUTPUT_NOTHING
+ * - \ref BPWM_OUTPUT_LOW
+ * - \ref BPWM_OUTPUT_HIGH
+ * - \ref BPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
+ * - \ref BPWM_OUTPUT_NOTHING
+ * - \ref BPWM_OUTPUT_LOW
+ * - \ref BPWM_OUTPUT_HIGH
+ * - \ref BPWM_OUTPUT_TOGGLE
+ * @return None
+ * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * \hideinitializer
+ */
+#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
+ do{ \
+ int i; \
+ for(i = 0; i < 6; i++) { \
+ if((u32ChannelMask) & (1 << i)) { \
+ (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \
+ (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \
+ (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \
+ (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \
+ } \
+ } \
+ }while(0)
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define BPWM functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
+uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
+void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
+void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
+void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
+uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+
+
+/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group BPWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_BPWM_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_can.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_can.h
new file mode 100644
index 00000000000..cfc1c1fd163
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_can.h
@@ -0,0 +1,192 @@
+/**************************************************************************//**
+ * @file nu_can.h
+ * @version V2.00
+ * @brief M480 Series CAN Driver Header File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_CAN_H__
+#define __NU_CAN_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+ @{
+*/
+
+/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAN Test Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CAN_NORMAL_MODE 0ul /*!< CAN select normal mode \hideinitializer */
+#define CAN_BASIC_MODE 1ul /*!< CAN select basic mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message ID Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CAN_STD_ID 0ul /*!< CAN select standard ID \hideinitializer */
+#define CAN_EXT_ID 1ul /*!< CAN select extended ID \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message Frame Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CAN_REMOTE_FRAME 0ul /*!< CAN frame select remote frame \hideinitializer */
+#define CAN_DATA_FRAME 1ul /*!< CAN frame select data frame \hideinitializer */
+
+/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs
+ @{
+*/
+/**
+ * @details CAN message structure
+ */
+typedef struct
+{
+ uint32_t IdType; /*!< ID type */
+ uint32_t FrameType; /*!< Frame type */
+ uint32_t Id; /*!< Message ID */
+ uint8_t DLC; /*!< Data length */
+ uint8_t Data[8]; /*!< Data */
+} STR_CANMSG_T;
+
+/**
+ * @details CAN mask message structure
+ */
+typedef struct
+{
+ uint8_t u8Xtd; /*!< Extended ID */
+ uint8_t u8Dir; /*!< Direction */
+ uint32_t u32Id; /*!< Message ID */
+ uint8_t u8IdType; /*!< ID type*/
+} STR_CANMASK_T;
+
+/*@}*/ /* end of group CAN_EXPORTED_STRUCTS */
+
+/** @cond HIDDEN_SYMBOLS */
+#define MSG(id) (id)
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+ @{
+*/
+
+/**
+ * @brief Get interrupt status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return CAN module status register value.
+ *
+ * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
+ * EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
+ * \hideinitializer
+ */
+#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
+
+/**
+ * @brief Get specified interrupt pending status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return The source of the interrupt.
+ *
+ * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
+ * with the highest priority, disregarding their chronological order.
+ * \hideinitializer
+ */
+#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
+
+/**
+ * @brief Disable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details The macro is used to disable wake-up function.
+ * \hideinitializer
+ */
+#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0ul)
+
+/**
+ * @brief Enable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
+ * \hideinitializer
+ */
+#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk)
+
+/**
+ * @brief Get specified Message Object new data into bit value.
+ *
+ * @param[in] can The base address of can module.
+ * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
+ *
+ * @return Specified Message Object new data into bit value.
+ *
+ * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
+ * or by the Message Handler after reception of a Data Frame or after a successful transmission.
+ * \hideinitializer
+ */
+#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define CAN functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
+void CAN_Close(CAN_T *tCAN);
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);
+int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum);
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg);
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg);
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
+void CAN_LeaveTestMode(CAN_T *tCAN);
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN);
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj);
+void CAN_LeaveInitMode(CAN_T *tCAN);
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast);
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast);
+void CAN_WaitMsg(CAN_T *tCAN);
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg);
+
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CAN_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__NU_CAN_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ccap.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ccap.h
new file mode 100644
index 00000000000..a7927f36b71
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ccap.h
@@ -0,0 +1,165 @@
+/**************************************************************************//**
+ * @file nu_ccap.h
+ * @version V1.00
+ * @brief M480 Series CCAP Driver Header File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_CCAP_H__
+#define __NU_CCAP_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CCAP_Driver CCAP Driver
+ @{
+*/
+
+/** @addtogroup CCAP_EXPORTED_CONSTANTS CCAP Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CTL constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CCAP_CTL_CCAPEN (1ul<CTL & CCAP_CTL_CCAPEN_Msk)?0:1)
+
+/**
+ * @brief Clear CCAP flag
+ *
+ * @param[in] u32IntMask interrupt flags settings. It could be
+ * - \ref CCAP_INT_VINTF_Msk
+ * - \ref CCAP_INT_MEINTF_Msk
+ * - \ref CCAP_INT_ADDRMINTF_Msk
+ * - \ref CCAP_INT_MDINTF_Msk
+ *
+ * @return TRUE(Enable) or FALSE(Disable)
+ *
+ * @details Clear Image Capture Interface interrupt flag
+ * \hideinitializer
+ */
+#define CCAP_CLR_INT_FLAG(u32IntMask) (CCAP->INT |=u32IntMask)
+
+/**
+ * @brief Get CCAP Interrupt status
+ *
+ * @return TRUE(Enable) or FALSE(Disable)
+ *
+ * @details Get Image Capture Interface interrupt status.
+ * \hideinitializer
+ */
+#define CCAP_GET_INT_STS() (CCAP->INT)
+
+void CCAP_Open(uint32_t u32InFormat, uint32_t u32OutFormet);
+void CCAP_SetCroppingWindow(uint32_t u32VStart,uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width);
+void CCAP_SetPacketBuf(uint32_t u32Address );
+void CCAP_Close(void);
+void CCAP_EnableInt(uint32_t u32IntMask);
+void CCAP_DisableInt(uint32_t u32IntMask);
+void CCAP_Start(void);
+void CCAP_Stop(uint32_t u32FrameComplete);
+void CCAP_SetPacketScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator);
+void CCAP_SetPacketStride(uint32_t u32Stride );
+void CCAP_EnableMono(uint32_t u32Interface);
+void CCAP_DisableMono(void);
+void CCAP_EnableLumaYOne(uint32_t u32th);
+void CCAP_DisableLumaYOne(void);
+
+/*@}*/ /* end of group CCAP_EXPORTED_FUNCTIONS */
+
+
+
+/*@}*/ /* end of group CCAP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_CCAP_H__
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_clk.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_clk.h
new file mode 100644
index 00000000000..9dc88b552d8
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_clk.h
@@ -0,0 +1,714 @@
+/**************************************************************************//**
+ * @file CLK.h
+ * @version V1.0
+ * @brief M480 Series CLK Driver Header File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_CLK_H__
+#define __NU_CLK_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CLK_Driver CLK Driver
+ @{
+*/
+
+/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
+ @{
+*/
+
+
+#define FREQ_25MHZ 25000000UL /*!< 25 MHz \hideinitializer */
+#define FREQ_50MHZ 50000000UL /*!< 50 MHz \hideinitializer */
+#define FREQ_72MHZ 72000000UL /*!< 72 MHz \hideinitializer */
+#define FREQ_80MHZ 80000000UL /*!< 80 MHz \hideinitializer */
+#define FREQ_100MHZ 100000000UL /*!< 100 MHz \hideinitializer */
+#define FREQ_125MHZ 125000000UL /*!< 125 MHz \hideinitializer */
+#define FREQ_160MHZ 160000000UL /*!< 160 MHz \hideinitializer */
+#define FREQ_192MHZ 192000000UL /*!< 192 MHz \hideinitializer */
+#define FREQ_200MHZ 200000000UL /*!< 200 MHz \hideinitializer */
+#define FREQ_250MHZ 250000000UL /*!< 250 MHz \hideinitializer */
+#define FREQ_500MHZ 500000000UL /*!< 500 MHz \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKSEL0 constant definitions. (Write-protection) */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HXT/2 \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HCLK/2 \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HIRC/2 \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK \hideinitializer */
+
+#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HXT \hideinitializer */
+#define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HCLK \hideinitializer */
+#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HIRC \hideinitializer */
+
+
+#if(0)
+#define CLK_CLKSEL0_PCLK0DIV1 (0x0UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from HCLK \hideinitializer */
+#define CLK_CLKSEL0_PCLK0DIV2 (0x1UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from 1/2 HCLK \hideinitializer */
+
+#define CLK_CLKSEL0_PCLK1DIV1 (0x0UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from HCLK \hideinitializer */
+#define CLK_CLKSEL0_PCLK1DIV2 (0x1UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from 1/2 HCLK \hideinitializer */
+#endif
+
+#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HCLK \hideinitializer */
+
+#define CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_SDH0SEL_PLL (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from HCLK \hideinitializer */
+
+#define CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_SDH1SEL_PLL (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from HCLK \hideinitializer */
+
+#define CLK_CLKSEL0_USBSEL_RC48M (0x0UL << CLK_CLKSEL0_USBSEL_Pos) /*!< Select USB clock source from RC48M \hideinitializer */
+#define CLK_CLKSEL0_USBSEL_PLL (0x1UL << CLK_CLKSEL0_USBSEL_Pos) /*!< Select USB clock source from PLL \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKSEL1 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from HCLK/2048 \hideinitializer */
+
+#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART0SEL_PLL (0x1UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART1SEL_PLL (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK \hideinitializer */
+
+#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKSEL2 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_EPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_EPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_BPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_BPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI2SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK0 \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKSEL3 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL3_RTCSEL_LXT (0x0UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_QSPI1SEL_HXT (0x0UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_QSPI1SEL_PLL (0x1UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_QSPI1SEL_HIRC (0x3UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_QSPI1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART2SEL_PLL (0x1UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART3SEL_PLL (0x1UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART4SEL_PLL (0x1UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART5SEL_PLL (0x1UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART6SEL_HXT (0x0UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART6SEL_LXT (0x2UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART6SEL_PLL (0x1UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART6SEL_HIRC (0x3UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART7SEL_HXT (0x0UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART7SEL_LXT (0x2UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART7SEL_PLL (0x1UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART7SEL_HIRC (0x3UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from high speed oscillator \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKDIV0 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_USB(x) (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_SDH0(x) (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV0_UART0(x) (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_UART1(x) (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_EADC(x) (((x) - 1UL) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKDIV1 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV1_SC0(x) (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV1_SC1(x) (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV1_SC2(x) (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKDIV2 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV2_I2S0(x) (((x) - 1UL) << CLK_CLKDIV2_I2SDIV_Pos) /*!< CLKDIV2 Setting for I2S0 clock divider. It could be 1~16 */
+#define CLK_CLKDIV2_EADC1(x) (((x) - 1UL) << CLK_CLKDIV2_EADC1DIV_Pos) /*!< CLKDIV2 Setting for EADC1 clock divider. It could be 1~256 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKDIV3 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV3_CCAP(x) (((x) - 1UL) << CLK_CLKDIV3_CCAPDIV_Pos) /*!< CLKDIV3 Setting for CCAP clock divider. It could be 1~256 */
+#define CLK_CLKDIV3_VSENSE(x) (((x) - 1UL) << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLKDIV3 Setting for VSENSE clock divider. It could be 1~256 */
+#define CLK_CLKDIV3_EMAC(x) (((x) - 1UL) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV3 Setting for EMAC clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV3_SDH1(x) (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLKDIV3 Setting for SDH1 clock divider. It could be 1~256 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKDIV4 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV4_UART2(x) (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV4_UART3(x) (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV4_UART4(x) (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV4_UART5(x) (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV4_UART6(x) (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLKDIV4 Setting for UART6 clock divider. It could be 1~16 */
+#define CLK_CLKDIV4_UART7(x) (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLKDIV4 Setting for UART7 clock divider. It could be 1~16 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* PCLKDIV constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PCLKDIV_PCLK0DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
+//
+#define CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
+#define CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
+#define CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
+#define CLK_PCLKDIV_APB0DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
+#define CLK_PCLKDIV_APB0DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
+#define CLK_PCLKDIV_APB1DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
+#define CLK_PCLKDIV_APB1DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
+#define CLK_PCLKDIV_APB1DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
+#define CLK_PCLKDIV_APB1DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
+#define CLK_PCLKDIV_APB1DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 4MHz < FIN/NR < 8MHz \hideinitializer */
+#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz \hideinitializer */
+
+#define CLK_PLLCTL_NF(x) (((x)-2UL)) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */
+#define CLK_PLLCTL_NR(x) (((x)-1UL)<<9) /*!< x must be constant and 1 <= x <= 32. 4MHz < FIN/NR < 8MHz \hideinitializer */
+
+#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 \hideinitializer */
+#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 \hideinitializer */
+#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 \hideinitializer */
+
+#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_80MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_160MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+
+#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_80MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_144MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_160MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_192MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* MODULE constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
+
+#define MODULE_APBCLK(x) (((x) >>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
+#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
+#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
+#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
+#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
+#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */
+#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */
+
+#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
+#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
+#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
+#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */
+#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */
+
+#define PDMA_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA Module \hideinitializer */
+#define ISP_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< ISP Module \hideinitializer */
+#define EBI_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< EBI Module \hideinitializer */
+#define USBH_MODULE ((0UL<<30)|(0UL<<28) |(0x1UL<<25) |(8UL<<20) |(0UL<<18) |(0xFUL<<10) |(4UL<<5) |(16UL<<0)) /*!< USBH Module \hideinitializer */
+#define EMAC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(16UL<<5) |(5UL<<0)) /*!< EMAC Module \hideinitializer */
+#define SDH0_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(20UL<<20) |(0UL<<18) |(0xFFUL<<10) |(24UL<<5) |(6UL<<0)) /*!< SDH0 Module \hideinitializer */
+#define CRC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< CRC Module \hideinitializer */
+#define CCAP_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(16UL<<20) |(2UL<<18) |(0xFFUL<<10) |(0UL<<5) |(8UL<<0)) /*!< CCAP Module \hideinitializer */
+#define SEN_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< SEN Module \hideinitializer */
+#define HSUSBD_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< HSUSBD Module \hideinitializer */
+#define CRPT_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< CRPT Module \hideinitializer */
+#define SPIM_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPIM Module \hideinitializer */
+#define FMCIDLE_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< FMCIDLE Module \hideinitializer */
+#define SDH1_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(22UL<<20) |(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(17UL<<0)) /*!< SDH1 Module \hideinitializer */
+#define WDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WDT Module \hideinitializer */
+#define RTC_MODULE ((1UL<<30)|(3UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< RTC Module \hideinitializer */
+#define TMR0_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TMR0 Module \hideinitializer */
+#define TMR1_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< TMR1 Module \hideinitializer */
+#define TMR2_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< TMR2 Module \hideinitializer */
+#define TMR3_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(20UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< TMR3 Module \hideinitializer */
+#define CLKO_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(28UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< CLKO Module \hideinitializer */
+#define WWDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(30UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WWDT Module \hideinitializer */
+#define ACMP01_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< ACMP01 Module \hideinitializer */
+#define I2C0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< I2C0 Module \hideinitializer */
+#define I2C1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< I2C1 Module \hideinitializer */
+#define I2C2_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< I2C2 Module \hideinitializer */
+#define QSPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(2UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< QSPI0 Module \hideinitializer */
+#define SPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(4UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< SPI0 Module \hideinitializer */
+#define SPI1_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(6UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPI1 Module \hideinitializer */
+#define SPI2_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(10UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< SPI2 Module \hideinitializer */
+#define UART0_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(24UL<<20) |(0UL<<18) |(0xFUL<<10) |(8UL<<5) |(16UL<<0)) /*!< UART0 Module \hideinitializer */
+#define UART1_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(26UL<<20) |(0UL<<18) |(0xFUL<<10) |(12UL<<5) |(17UL<<0)) /*!< UART1 Module \hideinitializer */
+#define UART2_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(24UL<<20) |(3UL<<18) |(0xFUL<<10) |(0UL<<5) |(18UL<<0)) /*!< UART2 Module \hideinitializer */
+#define UART3_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(26UL<<20) |(3UL<<18) |(0xFUL<<10) |(4UL<<5) |(19UL<<0)) /*!< UART3 Module \hideinitializer */
+#define UART4_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(28UL<<20) |(3UL<<18) |(0xFUL<<10) |(8UL<<5) |(20UL<<0)) /*!< UART4 Module \hideinitializer */
+#define UART5_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(30UL<<20) |(3UL<<18) |(0xFUL<<10) |(12UL<<5) |(21UL<<0)) /*!< UART5 Module \hideinitializer */
+#define UART6_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(20UL<<20) |(3UL<<18) |(0xFUL<<10) |(16UL<<5) |(22UL<<0)) /*!< UART6 Module \hideinitializer */
+#define UART7_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(22UL<<20) |(3UL<<18) |(0xFUL<<10) |(20UL<<5) |(23UL<<0)) /*!< UART7 Module \hideinitializer */
+#define CAN0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< CAN0 Module \hideinitializer */
+#define CAN1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< CAN1 Module \hideinitializer */
+#define OTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< OTG Module \hideinitializer */
+#define USBD_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(0xFUL<<10) |(4UL<<5) |(27UL<<0)) /*!< USBD Module \hideinitializer */
+#define EADC_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(0UL<<18) |(0xFFUL<<10) |(16UL<<5) |(28UL<<0)) /*!< EADC Module \hideinitializer */
+#define I2S0_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(16UL<<20) |(2UL<<18) |(0xFUL<<10) |(0UL<<5) |(29UL<<0)) /*!< I2S0 Module \hideinitializer */
+#define HSOTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< HSOTG Module \hideinitializer */
+#define SC0_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(0UL<<20) |(1UL<<18) |(0xFFUL<<10) |(0UL<<5) |(0UL<<0)) /*!< SC0 Module \hideinitializer */
+#define SC1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(2UL<<20) |(1UL<<18) |(0xFFUL<<10) |(8UL<<5) |(1UL<<0)) /*!< SC1 Module \hideinitializer */
+#define SC2_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(4UL<<20) |(1UL<<18) |(0xFFUL<<10) |(16UL<<5) |(2UL<<0)) /*!< SC2 Module \hideinitializer */
+#define QSPI1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< QSPI1 Module \hideinitializer */
+#define SPI3_MODULE ((2UL<<30)|(2UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< SPI3 Module \hideinitializer */
+#define USCI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< USCI0 Module \hideinitializer */
+#define USCI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< USCI1 Module \hideinitializer */
+#define DAC_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< DAC Module \hideinitializer */
+#define CAN2_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(28UL<<0)) /*!< CAN2 Module \hideinitializer */
+#define EPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< EPWM0 Module \hideinitializer */
+#define EPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(1UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< EPWM1 Module \hideinitializer */
+#define BPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< BPWM0 Module \hideinitializer */
+#define BPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(9UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< BPWM1 Module \hideinitializer */
+#define QEI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< QEI0 Module \hideinitializer */
+#define QEI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< QEI1 Module \hideinitializer */
+#define TRNG_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< TRNG Module \hideinitializer */
+#define ECAP0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< ECAP0 Module \hideinitializer */
+#define ECAP1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< ECAP1 Module \hideinitializer */
+#define OPA_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< OPA Module \hideinitializer */
+#define EADC1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(31UL<<0)) /*!< EADC1 Module \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* PDMSEL constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Power-down mode \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Low leakage Power-down mode \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Fast wake-up Power-down mode \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_SPD0 (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 0 \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_SPD1 (0x5UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 1 \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Deep Power-down mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* WKTMRIS constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_131072 (0x8UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 131072 OSC10K clocks (13107.2 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_262144 (0x9UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 262144 OSC10K clocks (26214.4 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_524288 (0xaUL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 524288 OSC10K clocks (52428.8ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_1048576 (0xbUL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1048576 OSC10K clocks (104857.6ms) \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* SWKDBCLKSEL constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin both edge at Deep Power-down mode \hideinitializer */
+
+#define CLK_DPDWKPIN0_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN0_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN0_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN0_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode \hideinitializer */
+
+#define CLK_DPDWKPIN1_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN1_RISING (0x1UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN1_FALLING (0x2UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN1_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode \hideinitializer */
+
+#define CLK_DPDWKPIN2_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN2_RISING (0x1UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN2_FALLING (0x2UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN2_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode \hideinitializer */
+
+#define CLK_DPDWKPIN3_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN3_RISING (0x1UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN3_FALLING (0x2UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN3_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode \hideinitializer */
+
+#define CLK_DPDWKPIN4_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN4_RISING (0x1UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN4_FALLING (0x2UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN4_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */
+#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */
+#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */
+#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function \hideinitializer */
+#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function \hideinitializer */
+
+#define CLK_SPDSRETSEL_NO (0x0UL << CLK_PMUCTL_SRETSEL_Pos) /*!< No SRAM retention when chip enter SPD mode \hideinitializer */
+#define CLK_SPDSRETSEL_16K (0x1UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 16K SRAM retention when chip enter SPD mode \hideinitializer */
+#define CLK_SPDSRETSEL_32K (0x2UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 32K SRAM retention when chip enter SPD mode \hideinitializer */
+#define CLK_SPDSRETSEL_64K (0x3UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 64K SRAM retention when chip enter SPD mode \hideinitializer */
+#define CLK_SPDSRETSEL_128K (0x4UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 128K SRAM retention when chip enter SPD mode \hideinitializer */
+
+#define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
+#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_DPDWKPIN0(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_DPDWKPIN1(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN1_Msk) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_DPDWKPIN2(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN2_Msk) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_DPDWKPIN3(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN3_Msk) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_DPDWKPIN4(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN4_Msk) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */
+#define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */
+#define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
+#define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
+
+/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
+
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set Wake-up Timer Time-out Interval
+ *
+ * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be
+ * - \ref CLK_PMUCTL_WKTMRIS_128
+ * - \ref CLK_PMUCTL_WKTMRIS_256
+ * - \ref CLK_PMUCTL_WKTMRIS_512
+ * - \ref CLK_PMUCTL_WKTMRIS_1024
+ * - \ref CLK_PMUCTL_WKTMRIS_4096
+ * - \ref CLK_PMUCTL_WKTMRIS_8192
+ * - \ref CLK_PMUCTL_WKTMRIS_16384
+ * - \ref CLK_PMUCTL_WKTMRIS_65536
+ * - \ref CLK_PMUCTL_WKTMRIS_131072
+ * - \ref CLK_PMUCTL_WKTMRIS_262144
+ * - \ref CLK_PMUCTL_WKTMRIS_524288
+ * - \ref CLK_PMUCTL_WKTMRIS_1048576
+ *
+ * @return None
+ *
+ * @details This function set Wake-up Timer Time-out Interval.
+ *
+ * \hideinitializer
+ */
+#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval))
+
+/**
+ * @brief Set De-bounce Sampling Cycle Time
+ *
+ * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256
+ *
+ * @return None
+ *
+ * @details This function set Set De-bounce Sampling Cycle Time.
+ *
+ * \hideinitializer
+ */
+#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us);
+__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us);
+
+/**
+ * @brief This function execute delay function.
+ * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
+ * 72MHz => 233016us, 50MHz => 335544us,
+ * 48MHz => 349525us, 28MHz => 699050us ...
+ * @return None
+ * @details Use the SysTick to generate the delay time and the unit is in us.
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.
+ */
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
+{
+ SysTick->LOAD = us * CyclesPerUs;
+ SysTick->VAL = 0x0UL;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+ /* Waiting for down-count to zero */
+ while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
+ {
+ }
+
+ /* Disable SysTick counter */
+ SysTick->CTRL = 0UL;
+}
+
+/**
+ * @brief This function execute long delay function.
+ * @param[in] us Delay time.
+ * @return None
+ * @details Use the SysTick to generate the long delay time and the UNIT is in us.
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.
+ * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
+ */
+__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
+{
+ uint32_t delay;
+
+ /* It should <= 349525us for each delay loop */
+ delay = 349525UL;
+
+ do
+ {
+ if(us > delay)
+ {
+ us -= delay;
+ }
+ else
+ {
+ delay = us;
+ us = 0UL;
+ }
+
+ SysTick->LOAD = delay * CyclesPerUs;
+ SysTick->VAL = (0x0UL);
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+ /* Waiting for down-count to zero */
+ while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
+
+ /* Disable SysTick counter */
+ SysTick->CTRL = 0UL;
+
+ }
+ while(us > 0UL);
+
+}
+
+
+void CLK_DisableCKO(void);
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
+void CLK_PowerDown(void);
+void CLK_Idle(void);
+uint32_t CLK_GetHXTFreq(void);
+uint32_t CLK_GetLXTFreq(void);
+uint32_t CLK_GetHCLKFreq(void);
+uint32_t CLK_GetPCLK0Freq(void);
+uint32_t CLK_GetPCLK1Freq(void);
+uint32_t CLK_GetCPUFreq(void);
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
+void CLK_EnableXtalRC(uint32_t u32ClkMask);
+void CLK_DisableXtalRC(uint32_t u32ClkMask);
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
+void CLK_DisablePLL(void);
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
+void CLK_DisableSysTick(void);
+void CLK_SetPowerDownMode(uint32_t u32PDMode);
+void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
+uint32_t CLK_GetPMUWKSrc(void);
+void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
+uint32_t CLK_GetPLLClockFreq(void);
+uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
+uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
+
+/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CLK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_CLK_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crc.h
new file mode 100644
index 00000000000..2dc6afca049
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crc.h
@@ -0,0 +1,113 @@
+/**************************************************************************//**
+ * @file nu_crc.h
+ * @version V1.00
+ * @brief M480 series CRC driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_CRC_H__
+#define __NU_CRC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CRC_Driver CRC Driver
+ @{
+*/
+
+/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* CRC Polynomial Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0)
+
+/**
+ * @brief Get CRC Seed Value
+ *
+ * @param None
+ *
+ * @return CRC seed value
+ *
+ * @details This macro gets the current CRC seed value.
+ * \hideinitializer
+ */
+#define CRC_GET_SEED() (CRC->SEED)
+
+/**
+ * @brief CRC Write Data
+ *
+ * @param[in] u32Data Write data
+ *
+ * @return None
+ *
+ * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
+ * \hideinitializer
+ */
+#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data))
+
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
+uint32_t CRC_GetChecksum(void);
+
+/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CRC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crypto.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crypto.h
new file mode 100644
index 00000000000..6b0ccb27d0a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crypto.h
@@ -0,0 +1,378 @@
+/**************************************************************************//**
+ * @file nu_crypto.h
+ * @version V1.10
+ * @brief Cryptographic Accelerator driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_CRYPTO_H__
+#define __NU_CRYPTO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CRYPTO_Driver CRYPTO Driver
+ @{
+*/
+
+
+/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants
+ @{
+*/
+
+#define PRNG_KEY_SIZE_64 0UL /*!< Select to generate 64-bit random key \hideinitializer */
+#define PRNG_KEY_SIZE_128 1UL /*!< Select to generate 128-bit random key \hideinitializer */
+#define PRNG_KEY_SIZE_192 2UL /*!< Select to generate 192-bit random key \hideinitializer */
+#define PRNG_KEY_SIZE_256 3UL /*!< Select to generate 256-bit random key \hideinitializer */
+
+#define PRNG_SEED_CONT 0UL /*!< PRNG using current seed \hideinitializer */
+#define PRNG_SEED_RELOAD 1UL /*!< PRNG reload new seed \hideinitializer */
+
+#define AES_KEY_SIZE_128 0UL /*!< AES select 128-bit key length \hideinitializer */
+#define AES_KEY_SIZE_192 1UL /*!< AES select 192-bit key length \hideinitializer */
+#define AES_KEY_SIZE_256 2UL /*!< AES select 256-bit key length \hideinitializer */
+
+#define AES_MODE_ECB 0UL /*!< AES select ECB mode \hideinitializer */
+#define AES_MODE_CBC 1UL /*!< AES select CBC mode \hideinitializer */
+#define AES_MODE_CFB 2UL /*!< AES select CFB mode \hideinitializer */
+#define AES_MODE_OFB 3UL /*!< AES select OFB mode \hideinitializer */
+#define AES_MODE_CTR 4UL /*!< AES select CTR mode \hideinitializer */
+#define AES_MODE_CBC_CS1 0x10UL /*!< AES select CBC CS1 mode \hideinitializer */
+#define AES_MODE_CBC_CS2 0x11UL /*!< AES select CBC CS2 mode \hideinitializer */
+#define AES_MODE_CBC_CS3 0x12UL /*!< AES select CBC CS3 mode \hideinitializer */
+
+#define AES_NO_SWAP 0UL /*!< AES do not swap input and output data \hideinitializer */
+#define AES_OUT_SWAP 1UL /*!< AES swap output data \hideinitializer */
+#define AES_IN_SWAP 2UL /*!< AES swap input data \hideinitializer */
+#define AES_IN_OUT_SWAP 3UL /*!< AES swap both input and output data \hideinitializer */
+
+#define DES_MODE_ECB 0x000UL /*!< DES select ECB mode \hideinitializer */
+#define DES_MODE_CBC 0x100UL /*!< DES select CBC mode \hideinitializer */
+#define DES_MODE_CFB 0x200UL /*!< DES select CFB mode \hideinitializer */
+#define DES_MODE_OFB 0x300UL /*!< DES select OFB mode \hideinitializer */
+#define DES_MODE_CTR 0x400UL /*!< DES select CTR mode \hideinitializer */
+#define TDES_MODE_ECB 0x004UL /*!< TDES select ECB mode \hideinitializer */
+#define TDES_MODE_CBC 0x104UL /*!< TDES select CBC mode \hideinitializer */
+#define TDES_MODE_CFB 0x204UL /*!< TDES select CFB mode \hideinitializer */
+#define TDES_MODE_OFB 0x304UL /*!< TDES select OFB mode \hideinitializer */
+#define TDES_MODE_CTR 0x404UL /*!< TDES select CTR mode \hideinitializer */
+
+#define TDES_NO_SWAP 0UL /*!< TDES do not swap data \hideinitializer */
+#define TDES_WHL_SWAP 1UL /*!< TDES swap high-low word \hideinitializer */
+#define TDES_OUT_SWAP 2UL /*!< TDES swap output data \hideinitializer */
+#define TDES_OUT_WHL_SWAP 3UL /*!< TDES swap output data and high-low word \hideinitializer */
+#define TDES_IN_SWAP 4UL /*!< TDES swap input data \hideinitializer */
+#define TDES_IN_WHL_SWAP 5UL /*!< TDES swap input data and high-low word \hideinitializer */
+#define TDES_IN_OUT_SWAP 6UL /*!< TDES swap both input and output data \hideinitializer */
+#define TDES_IN_OUT_WHL_SWAP 7UL /*!< TDES swap input, output and high-low word \hideinitializer */
+
+#define SHA_MODE_SHA1 0UL /*!< SHA select SHA-1 160-bit \hideinitializer */
+#define SHA_MODE_SHA224 5UL /*!< SHA select SHA-224 224-bit \hideinitializer */
+#define SHA_MODE_SHA256 4UL /*!< SHA select SHA-256 256-bit \hideinitializer */
+#define SHA_MODE_SHA384 7UL /*!< SHA select SHA-384 384-bit \hideinitializer */
+#define SHA_MODE_SHA512 6UL /*!< SHA select SHA-512 512-bit \hideinitializer */
+
+#define SHA_NO_SWAP 0UL /*!< SHA do not swap input and output data \hideinitializer */
+#define SHA_OUT_SWAP 1UL /*!< SHA swap output data \hideinitializer */
+#define SHA_IN_SWAP 2UL /*!< SHA swap input data \hideinitializer */
+#define SHA_IN_OUT_SWAP 3UL /*!< SHA swap both input and output data \hideinitializer */
+
+#define CRYPTO_DMA_FIRST 0x4UL /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */
+#define CRYPTO_DMA_ONE_SHOT 0x5UL /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */
+#define CRYPTO_DMA_CONTINUE 0x6UL /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */
+#define CRYPTO_DMA_LAST 0x7UL /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */
+
+typedef enum
+{
+ /*!< ECC curve \hideinitializer */
+ CURVE_P_192, /*!< ECC curve P-192 \hideinitializer */
+ CURVE_P_224, /*!< ECC curve P-224 \hideinitializer */
+ CURVE_P_256, /*!< ECC curve P-256 \hideinitializer */
+ CURVE_P_384, /*!< ECC curve P-384 \hideinitializer */
+ CURVE_P_521, /*!< ECC curve P-521 \hideinitializer */
+ CURVE_K_163, /*!< ECC curve K-163 \hideinitializer */
+ CURVE_K_233, /*!< ECC curve K-233 \hideinitializer */
+ CURVE_K_283, /*!< ECC curve K-283 \hideinitializer */
+ CURVE_K_409, /*!< ECC curve K-409 \hideinitializer */
+ CURVE_K_571, /*!< ECC curve K-571 \hideinitializer */
+ CURVE_B_163, /*!< ECC curve B-163 \hideinitializer */
+ CURVE_B_233, /*!< ECC curve B-233 \hideinitializer */
+ CURVE_B_283, /*!< ECC curve B-283 \hideinitializer */
+ CURVE_B_409, /*!< ECC curve B-409 \hideinitializer */
+ CURVE_B_571, /*!< ECC curve K-571 \hideinitializer */
+ CURVE_KO_192, /*!< ECC 192-bits "Koblitz" curve \hideinitializer */
+ CURVE_KO_224, /*!< ECC 224-bits "Koblitz" curve \hideinitializer */
+ CURVE_KO_256, /*!< ECC 256-bits "Koblitz" curve \hideinitializer */
+ CURVE_BP_256, /*!< ECC Brainpool 256-bits curve \hideinitializer */
+ CURVE_BP_384, /*!< ECC Brainpool 256-bits curve \hideinitializer */
+ CURVE_BP_512, /*!< ECC Brainpool 256-bits curve \hideinitializer */
+ CURVE_UNDEF, /*!< Invalid curve \hideinitializer */
+}
+E_ECC_CURVE; /*!< ECC curve \hideinitializer */
+
+
+/*@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros
+ @{
+*/
+
+/*----------------------------------------------------------------------------------------------*/
+/* Macros */
+/*----------------------------------------------------------------------------------------------*/
+
+/**
+ * @brief This macro enables PRNG interrupt.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk)
+
+/**
+ * @brief This macro disables PRNG interrupt.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk)
+
+/**
+ * @brief This macro gets PRNG interrupt flag.
+ * @param crpt Specified cripto module
+ * @return PRNG interrupt flag.
+ * \hideinitializer
+ */
+#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk)
+
+/**
+ * @brief This macro clears PRNG interrupt flag.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk)
+
+/**
+ * @brief This macro enables AES interrupt.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
+
+/**
+ * @brief This macro disables AES interrupt.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
+
+/**
+ * @brief This macro gets AES interrupt flag.
+ * @param crpt Specified cripto module
+ * @return AES interrupt flag.
+ * \hideinitializer
+ */
+#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
+
+/**
+ * @brief This macro clears AES interrupt flag.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
+
+/**
+ * @brief This macro enables AES key protection.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk)
+
+/**
+ * @brief This macro disables AES key protection.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk)
+
+/**
+ * @brief This macro enables TDES interrupt.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))
+
+/**
+ * @brief This macro disables TDES interrupt.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))
+
+/**
+ * @brief This macro gets TDES interrupt flag.
+ * @param crpt Specified cripto module
+ * @return TDES interrupt flag.
+ * \hideinitializer
+ */
+#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))
+
+/**
+ * @brief This macro clears TDES interrupt flag.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))
+
+/**
+ * @brief This macro enables TDES key protection.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk)
+
+/**
+ * @brief This macro disables TDES key protection.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk)
+
+/**
+ * @brief This macro enables SHA interrupt.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))
+
+/**
+ * @brief This macro disables SHA interrupt.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))
+
+/**
+ * @brief This macro gets SHA interrupt flag.
+ * @param crpt Specified cripto module
+ * @return SHA interrupt flag.
+ * \hideinitializer
+ */
+#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))
+
+/**
+ * @brief This macro clears SHA interrupt flag.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))
+
+/**
+ * @brief This macro enables ECC interrupt.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))
+
+/**
+ * @brief This macro disables ECC interrupt.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))
+
+/**
+ * @brief This macro gets ECC interrupt flag.
+ * @param crpt Specified cripto module
+ * @return ECC interrupt flag.
+ * \hideinitializer
+ */
+#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))
+
+/**
+ * @brief This macro clears ECC interrupt flag.
+ * @param crpt Specified cripto module
+ * @return None
+ * \hideinitializer
+ */
+#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))
+
+
+/*@}*/ /* end of group M480_CRYPTO_EXPORTED_MACROS */
+
+
+/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed);
+void PRNG_Start(CRPT_T *crpt);
+void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]);
+void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);
+void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode);
+void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
+void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]);
+void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
+void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType);
+void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode);
+void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]);
+void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL);
+void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
+void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len);
+void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode);
+void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt);
+void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]);
+void ECC_Complete(CRPT_T *crpt);
+int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]);
+int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]);
+int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]);
+int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]);
+int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S);
+int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S);
+
+
+/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CRYPTO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_CRYPTO_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_dac.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_dac.h
new file mode 100644
index 00000000000..71c22f4e4a0
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_dac.h
@@ -0,0 +1,269 @@
+/**************************************************************************//**
+ * @file nu_dac.h
+ * @version V1.00
+ * @brief M480 series DAC driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_DAC_H__
+#define __NU_DAC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup DAC_Driver DAC Driver
+ @{
+*/
+
+
+/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* DAC_CTL Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk)
+
+/**
+ * @brief Enable DAC data left-aligned.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
+ * \hideinitializer
+ */
+#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
+
+/**
+ * @brief Enable DAC data right-aligned.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
+ * \hideinitializer
+ */
+#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
+
+/**
+ * @brief Enable output voltage buffer.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
+ * drive external loads directly without having to add an external operational amplifier.
+ * \hideinitializer
+ */
+#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
+
+/**
+ * @brief Disable output voltage buffer.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details This macro is used to disable output voltage buffer.
+ * \hideinitializer
+ */
+#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
+
+/**
+ * @brief Enable the interrupt.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M480 DAC.
+ * @return None
+ * @details This macro is used to enable DAC interrupt.
+ * \hideinitializer
+ */
+#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
+
+/**
+ * @brief Disable the interrupt.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M480 DAC.
+ * @return None
+ * @details This macro is used to disable DAC interrupt.
+ * \hideinitializer
+ */
+#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
+
+/**
+ * @brief Enable DMA under-run interrupt.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details This macro is used to enable DMA under-run interrupt.
+ * \hideinitializer
+ */
+#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
+
+/**
+ * @brief Disable DMA under-run interrupt.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details This macro is used to disable DMA under-run interrupt.
+ * \hideinitializer
+ */
+#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
+
+/**
+ * @brief Enable PDMA mode.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
+ * \hideinitializer
+ */
+#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
+
+/**
+ * @brief Disable PDMA mode.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details This macro is used to disable DMA mode.
+ * \hideinitializer
+ */
+#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
+
+/**
+ * @brief Write data for conversion.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M480 DAC.
+ * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
+ * @return None
+ * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
+ * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
+ * \hideinitializer
+ */
+#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
+
+/**
+ * @brief Read DAC 12-bit holding data.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M480 DAC.
+ * @return Return DAC 12-bit holding data.
+ * @details This macro is used to read DAC_DAT register.
+ * \hideinitializer
+ */
+#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
+
+/**
+ * @brief Get the busy state of DAC.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M480 DAC.
+ * @retval 0 Idle state.
+ * @retval 1 Busy state.
+ * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
+ * \hideinitializer
+ */
+#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
+
+/**
+ * @brief Get the interrupt flag.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M480 DAC.
+ * @retval 0 DAC is in conversion state.
+ * @retval 1 DAC conversion finish.
+ * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
+ * \hideinitializer
+ */
+#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
+
+/**
+ * @brief Get the DMA under-run flag.
+ * @param[in] dac Base address of DAC module.
+ * @retval 0 No DMA under-run error condition occurred.
+ * @retval 1 DMA under-run error condition occurred.
+ * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
+ * \hideinitializer
+ */
+#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
+
+/**
+ * @brief This macro clear the interrupt status bit.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M480 DAC.
+ * @return None
+ * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
+ * \hideinitializer
+ */
+#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
+
+/**
+ * @brief This macro clear the DMA under-run flag.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
+ * \hideinitializer
+ */
+#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
+
+
+/**
+ * @brief Enable DAC group mode
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * \hideinitializer
+ */
+#define DAC_ENABLE_GROUP_MODE(dac) (DAC0->CTL |= DAC_CTL_GRPEN_Msk)
+
+/**
+ * @brief Disable DAC group mode
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * \hideinitializer
+ */
+#define DAC_DISABLE_GROUP_MODE(dac) (DAC0->CTL &= ~DAC_CTL_GRPEN_Msk)
+
+void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
+void DAC_Close(DAC_T *dac, uint32_t u32Ch);
+uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay);
+
+/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group DAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_DAC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h
new file mode 100644
index 00000000000..c9bd0ef39bc
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h
@@ -0,0 +1,616 @@
+/**************************************************************************//**
+ * @file nu_eadc.h
+ * @version V0.10
+ * @brief M480 series EADC driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_EADC_H__
+#define __NU_EADC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EADC_Driver EADC Driver
+ @{
+*/
+
+/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* EADC_CTL Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EADC_CTL_DIFFEN_SINGLE_END (0UL<CTL |= EADC_CTL_ADCRST_Msk)
+
+/**
+ * @brief Enable PDMA transfer.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
+ * user can enable this bit to generate a PDMA data transfer request.
+ * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
+
+/**
+ * @brief Disable PDMA transfer.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details This macro is used to disable PDMA transfer.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
+
+/**
+ * @brief Enable Sample Module PDMA transfer.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+ * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
+ * @return None
+ * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
+ * user can enable this bit to generate a PDMA data transfer request.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask)
+
+/**
+ * @brief Disable Sample Module PDMA transfer.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+ * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
+ * @return None
+ * @details This macro is used to disable sample module PDMA transfer.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask))
+
+/**
+ * @brief Enable double buffer mode.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
+ * @return None
+ * @details The ADC controller supports a double buffer mode in sample module 0~3.
+ * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
+
+/**
+ * @brief Disable double buffer mode.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
+ * @return None
+ * @details Sample has one sample result register.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
+
+/**
+ * @brief Set ADIFn at A/D end of conversion.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+ * @return None
+ * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
+
+/**
+ * @brief Set ADIFn at A/D start of conversion.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+ * @return None
+ * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
+
+/**
+ * @brief Enable the interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
+ * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
+ * @return None
+ * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.
+ * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
+ * \hideinitializer
+ */
+#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
+
+/**
+ * @brief Disable the interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
+ * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
+ * @return None
+ * @details Specific sample module A/D ADINT0 interrupt function Disabled.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
+
+/**
+ * @brief Enable the sample module interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
+ * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+ * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
+ * @return None
+ * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
+
+/**
+ * @brief Disable the sample module interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
+ * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+ * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
+ * @return None
+ * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
+
+/**
+ * @brief Set the input mode output format.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32Format Decides the output format. Valid values are:
+ * - EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result.
+ * - EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.
+ * @return None
+ * @details The macro is used to set A/D input mode output format.
+ * \hideinitializer
+ */
+#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
+
+/**
+ * @brief Start the A/D conversion.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
+ * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
+ * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
+ * @return None
+ * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
+ * \hideinitializer
+ */
+#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
+
+/**
+ * @brief Cancel the conversion for sample module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
+ * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
+ * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
+ * @return None
+ * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
+ * \hideinitializer
+ */
+#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
+
+/**
+ * @brief Get the conversion pending flag.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return Return the conversion pending sample module.
+ * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
+ * the STPFn (n=0~18) bit is automatically cleared to 0.
+ * \hideinitializer
+ */
+#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
+
+/**
+ * @brief Get the conversion data of the user-specified sample module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+ * @return Return the conversion data of the user-specified sample module.
+ * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
+ * \hideinitializer
+ */
+#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
+
+/**
+ * @brief Get the data overrun flag of the user-specified sample module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
+ * @return Return the data overrun flag of the user-specified sample module.
+ * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
+ * \hideinitializer
+ */
+#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
+
+/**
+ * @brief Get the data valid flag of the user-specified sample module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
+ * @return Return the data valid flag of the user-specified sample module.
+ * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status.
+ * \hideinitializer
+ */
+#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
+
+/**
+ * @brief Get the double data of the user-specified sample module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+ * @return Return the double data of the user-specified sample module.
+ * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
+ * \hideinitializer
+ */
+#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk)
+
+/**
+ * @brief Get the user-specified interrupt flags.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
+ * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
+ * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
+ * @return Return the user-specified interrupt flags.
+ * @details This macro is used to get the user-specified interrupt flags.
+ * \hideinitializer
+ */
+#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
+
+/**
+ * @brief Get the user-specified sample module overrun flags.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
+ * @return Return the user-specified sample module overrun flags.
+ * @details This macro is used to get the user-specified sample module overrun flags.
+ * \hideinitializer
+ */
+#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
+
+/**
+ * @brief Clear the selected interrupt status bits.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
+ * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
+ * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
+ * @return None
+ * @details This macro is used to clear clear the selected interrupt status bits.
+ * \hideinitializer
+ */
+#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
+
+/**
+ * @brief Clear the selected sample module overrun status bits.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
+ * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
+ * @return None
+ * @details This macro is used to clear the selected sample module overrun status bits.
+ * \hideinitializer
+ */
+#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
+
+/**
+ * @brief Check all sample module A/D result data register overrun flags.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @retval 0 None of sample module data register overrun flag is set to 1.
+ * @retval 1 Any one of sample module data register overrun flag is set to 1.
+ * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+ * \hideinitializer
+ */
+#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
+
+/**
+ * @brief Check all sample module A/D result data register valid flags.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @retval 0 None of sample module data register valid flag is set to 1.
+ * @retval 1 Any one of sample module data register valid flag is set to 1.
+ * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+ * \hideinitializer
+ */
+#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
+
+/**
+ * @brief Check all A/D sample module start of conversion overrun flags.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @retval 0 None of sample module event overrun flag is set to 1.
+ * @retval 1 Any one of sample module event overrun flag is set to 1.
+ * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+ * \hideinitializer
+ */
+#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
+
+/**
+ * @brief Check all A/D interrupt flag overrun bits.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @retval 0 None of ADINT interrupt flag is overwritten to 1.
+ * @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
+ * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+ * \hideinitializer
+ */
+#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
+
+/**
+ * @brief Get the busy state of EADC.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @retval 0 Idle state.
+ * @retval 1 Busy state.
+ * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
+ * \hideinitializer
+ */
+#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
+
+/**
+ * @brief Configure the comparator 0 and enable it.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+ * @param[in] u32Condition specifies the compare condition. Valid values are:
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+ * @return None
+ * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
+ * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_CMP0(eadc,\
+ u32ModuleNum,\
+ u32Condition,\
+ u16CMPData,\
+ u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+ (u32Condition) |\
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+ EADC_CMP_ADCMPEN_Msk))
+
+/**
+ * @brief Configure the comparator 1 and enable it.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+ * @param[in] u32Condition specifies the compare condition. Valid values are:
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+ * @return None
+ * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
+ * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_CMP1(eadc,\
+ u32ModuleNum,\
+ u32Condition,\
+ u16CMPData,\
+ u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+ (u32Condition) |\
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+ EADC_CMP_ADCMPEN_Msk))
+
+/**
+ * @brief Configure the comparator 2 and enable it.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+ * @param[in] u32Condition specifies the compare condition. Valid values are:
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+ * @return None
+ * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
+ * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_CMP2(eadc,\
+ u32ModuleNum,\
+ u32Condition,\
+ u16CMPData,\
+ u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+ (u32Condition) |\
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+ EADC_CMP_ADCMPEN_Msk))
+
+/**
+ * @brief Configure the comparator 3 and enable it.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+ * @param[in] u32Condition specifies the compare condition. Valid values are:
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
+ * @return None
+ * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
+ * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_CMP3(eadc,\
+ u32ModuleNum,\
+ u32Condition,\
+ u16CMPData,\
+ u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+ (u32Condition) |\
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+ EADC_CMP_ADCMPEN_Msk))
+
+/**
+ * @brief Enable the compare window mode.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
+ * @return None
+ * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
+
+/**
+ * @brief Disable the compare window mode.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
+ * @return None
+ * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
+
+/**
+ * @brief Enable the compare interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
+ * @return None
+ * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
+ * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,
+ * if ADCMPIE is set to 1, a compare interrupt request is generated.
+ * \hideinitializer
+ */
+#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
+
+/**
+ * @brief Disable the compare interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
+ * @return None
+ * @details This macro is used to disable the compare interrupt.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
+
+/**
+ * @brief Disable comparator 0.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details This macro is used to disable comparator 0.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
+
+/**
+ * @brief Disable comparator 1.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details This macro is used to disable comparator 1.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
+
+/**
+ * @brief Disable comparator 2.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details This macro is used to disable comparator 2.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0)
+
+/**
+ * @brief Disable comparator 3.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details This macro is used to disable comparator 3.
+ * \hideinitializer
+ */
+#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define EADC functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
+void EADC_Close(EADC_T *eadc);
+void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel);
+void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
+
+/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EADC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_EADC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ebi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ebi.h
new file mode 100644
index 00000000000..cd9c4998122
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ebi.h
@@ -0,0 +1,352 @@
+/**************************************************************************//**
+ * @file nu_ebi.h
+ * @version V3.00
+ * @brief M480 series External Bus Interface(EBI) driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_EBI_H__
+#define __NU_EBI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EBI_Driver EBI Driver
+ @{
+*/
+
+/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* Miscellaneous Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */
+#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */
+#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */
+#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Constants for EBI bank number */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */
+#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */
+#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Constants for EBI data bus width */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */
+#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Constants for EBI CS Active Level */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */
+#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Constants for EBI MCLK divider and Timing */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */
+#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */
+#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */
+#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */
+#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */
+#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */
+#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */
+#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */
+
+#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */
+#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */
+#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */
+#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */
+#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */
+#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */
+#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */
+
+#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */
+#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */
+#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */
+
+/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Read 8-bit data on EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ *
+ * @return 8-bit Data
+ *
+ * @details This macro is used to read 8-bit data from specify address on EBI bank0.
+ * \hideinitializer
+ */
+#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 8-bit data to EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 8-bit data to specify address on EBI bank0.
+ * \hideinitializer
+ */
+#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 16-bit data on EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ *
+ * @return 16-bit Data
+ *
+ * @details This macro is used to read 16-bit data from specify address on EBI bank0.
+ * \hideinitializer
+ */
+#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 16-bit data to EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 16-bit data to specify address on EBI bank0.
+ * \hideinitializer
+ */
+#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 32-bit data on EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ *
+ * @return 32-bit Data
+ *
+ * @details This macro is used to read 32-bit data from specify address on EBI bank0.
+ * \hideinitializer
+ */
+#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 32-bit data to EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 32-bit data to specify address on EBI bank0.
+ * \hideinitializer
+ */
+#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 8-bit data on EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ *
+ * @return 8-bit Data
+ *
+ * @details This macro is used to read 8-bit data from specify address on EBI bank1.
+ * \hideinitializer
+ */
+#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 8-bit data to EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 8-bit data to specify address on EBI bank1.
+ * \hideinitializer
+ */
+#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 16-bit data on EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ *
+ * @return 16-bit Data
+ *
+ * @details This macro is used to read 16-bit data from specify address on EBI bank1.
+ * \hideinitializer
+ */
+#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 16-bit data to EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 16-bit data to specify address on EBI bank1.
+ * \hideinitializer
+ */
+#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 32-bit data on EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ *
+ * @return 32-bit Data
+ *
+ * @details This macro is used to read 32-bit data from specify address on EBI bank1.
+ * \hideinitializer
+ */
+#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 32-bit data to EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 32-bit data to specify address on EBI bank1.
+ * \hideinitializer
+ */
+#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 8-bit data on EBI bank2
+ *
+ * @param[in] u32Addr The data address on EBI bank2.
+ *
+ * @return 8-bit Data
+ *
+ * @details This macro is used to read 8-bit data from specify address on EBI bank2.
+ * \hideinitializer
+ */
+#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 8-bit data to EBI bank2
+ *
+ * @param[in] u32Addr The data address on EBI bank2.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 8-bit data to specify address on EBI bank2.
+ * \hideinitializer
+ */
+#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 16-bit data on EBI bank2
+ *
+ * @param[in] u32Addr The data address on EBI bank2.
+ *
+ * @return 16-bit Data
+ *
+ * @details This macro is used to read 16-bit data from specify address on EBI bank2.
+ * \hideinitializer
+ */
+#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 16-bit data to EBI bank2
+ *
+ * @param[in] u32Addr The data address on EBI bank2.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 16-bit data to specify address on EBI bank2.
+ * \hideinitializer
+ */
+#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 32-bit data on EBI bank2
+ *
+ * @param[in] u32Addr The data address on EBI bank2.
+ *
+ * @return 32-bit Data
+ *
+ * @details This macro is used to read 32-bit data from specify address on EBI bank2.
+ * \hideinitializer
+ */
+#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 32-bit data to EBI bank2
+ *
+ * @param[in] u32Addr The data address on EBI bank2.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 32-bit data to specify address on EBI bank2.
+ * \hideinitializer
+ */
+#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Enable EBI Write Buffer
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to improve EBI write operation for all EBI banks.
+ * \hideinitializer
+ */
+#define EBI_ENABLE_WRITE_BUFFER() (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk);
+
+/**
+ * @brief Disable EBI Write Buffer
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to disable EBI write buffer function.
+ * \hideinitializer
+ */
+#define EBI_DISABLE_WRITE_BUFFER() (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk);
+
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
+void EBI_Close(uint32_t u32Bank);
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
+
+/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EBI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ecap.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ecap.h
new file mode 100644
index 00000000000..ebcf061ac06
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ecap.h
@@ -0,0 +1,458 @@
+/**************************************************************************//**
+ * @file nu_ecap.h
+ * @version V3.00
+ * @brief EnHanced Input Capture Timer(ECAP) driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_ECAP_H__
+#define __NU_ECAP_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup ECAP_Driver ECAP Driver
+ @{
+*/
+
+/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants
+ @{
+*/
+
+#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */
+#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */
+#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ECAP CTL0 constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel))
+
+/**
+ * @brief This macro is used to disable noise filter
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will disable the noise filter of input capture.
+ * \hideinitializer
+ */
+#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk)
+
+/**
+ * @brief This macro is used to enable noise filter
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32ClkSel Select noise filter clock divide number
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_1
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_2
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_4
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_16
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_32
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_64
+ * @return None
+ * @details This macro will enable the noise filter of input capture and set noise filter clock divide.
+ * \hideinitializer
+ */
+#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel))
+
+/**
+ * @brief This macro is used to enable input channel unit
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Mask The input channel mask
+ * - \ref ECAP_CTL0_IC0EN_Msk
+ * - \ref ECAP_CTL0_IC1EN_Msk
+ * - \ref ECAP_CTL0_IC2EN_Msk
+ * @return None
+ * @details This macro will enable the input channel_n to input capture.
+ * \hideinitializer
+ */
+#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask))
+
+/**
+ * @brief This macro is used to disable input channel unit
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Mask The input channel mask
+ * - \ref ECAP_CTL0_IC0EN_Msk
+ * - \ref ECAP_CTL0_IC1EN_Msk
+ * - \ref ECAP_CTL0_IC2EN_Msk
+ * @return None
+ * @details This macro will disable the input channel_n to input capture.
+ * \hideinitializer
+ */
+#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))
+
+/**
+ * @brief This macro is used to select input channel source
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Index The input channel number
+ * - \ref ECAP_IC0
+ * - \ref ECAP_IC1
+ * - \ref ECAP_IC2
+ * @param[in] u32Src The input source
+ * - \ref ECAP_CAP_INPUT_SRC_FROM_IC
+ * - \ref ECAP_CAP_INPUT_SRC_FROM_CH
+ * @return None
+ * @details This macro will select the input source from ICx, CHx.
+ * \hideinitializer
+ */
+#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<CTL0 |= (u32Mask))
+
+/**
+ * @brief This macro is used to disable input channel interrupt
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Mask The input channel mask
+ * - \ref ECAP_IC0
+ * - \ref ECAP_IC1
+ * - \ref ECAP_IC2
+ * @return None
+ * @details This macro will disable the input channel_n interrupt.
+ * \hideinitializer
+ */
+#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))
+
+/**
+ * @brief This macro is used to enable input channel overflow interrupt
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will enable the input channel overflow interrupt.
+ * \hideinitializer
+ */
+#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk)
+
+/**
+ * @brief This macro is used to disable input channel overflow interrupt
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will disable the input channel overflow interrupt.
+ * \hideinitializer
+ */
+#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk)
+
+/**
+ * @brief This macro is used to enable input channel compare-match interrupt
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will enable the input channel compare-match interrupt.
+ * \hideinitializer
+ */
+#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk)
+
+/**
+ * @brief This macro is used to disable input channel compare-match interrupt
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will disable the input channel compare-match interrupt.
+ * \hideinitializer
+ */
+#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk)
+
+/**
+ * @brief This macro is used to start capture counter
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will start capture counter up-counting.
+ * \hideinitializer
+ */
+#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk)
+
+/**
+ * @brief This macro is used to stop capture counter
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will stop capture counter up-counting.
+ * \hideinitializer
+ */
+#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk)
+
+/**
+ * @brief This macro is used to set event to clear capture counter
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Event The input channel number
+ * - \ref ECAP_CTL0_CMPCLREN_Msk
+ * - \ref ECAP_CTL1_CAP0RLDEN_Msk
+ * - \ref ECAP_CTL1_CAP1RLDEN_Msk
+ * - \ref ECAP_CTL1_CAP2RLDEN_Msk
+ * - \ref ECAP_CTL1_OVRLDEN_Msk
+
+ * @return None
+ * @details This macro will enable and select compare or capture event that can clear capture counter.
+ * \hideinitializer
+ */
+#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \
+ if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \
+ (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \
+ else \
+ (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \
+ (ecap)->CTL1 = ((ecap)->CTL1 &~0xF00) | ((u32Event) & 0xF00); \
+ }while(0);
+
+/**
+ * @brief This macro is used to enable compare function
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will enable the compare function.
+ * \hideinitializer
+ */
+#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk)
+
+/**
+ * @brief This macro is used to disable compare function
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will disable the compare function.
+ * \hideinitializer
+ */
+#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk)
+
+/**
+ * @brief This macro is used to enable input capture function.
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will enable input capture timer/counter.
+ * \hideinitializer
+ */
+#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk)
+
+/**
+ * @brief This macro is used to disable input capture function.
+ * @param[in] ecap Specify ECAP port
+ * @return None
+ * @details This macro will disable input capture timer/counter.
+ * \hideinitializer
+ */
+#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk)
+
+/**
+ * @brief This macro is used to select input channel edge detection
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Index The input channel number
+ * - \ref ECAP_IC0
+ * - \ref ECAP_IC1
+ * - \ref ECAP_IC2
+ * @param[in] u32Edge The input source
+ * - \ref ECAP_RISING_EDGE
+ * - \ref ECAP_FALLING_EDGE
+ * - \ref ECAP_RISING_FALLING_EDGE
+ * @return None
+ * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change.
+ * \hideinitializer
+ */
+#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1)))
+
+/**
+ * @brief This macro is used to select ECAP counter reload trigger source
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32TrigSrc The input source
+ * - \ref ECAP_CTL1_CAP0RLDEN_Msk
+ * - \ref ECAP_CTL1_CAP1RLDEN_Msk
+ * - \ref ECAP_CTL1_CAP2RLDEN_Msk
+ * - \ref ECAP_CTL1_OVRLDEN_Msk
+ * @return None
+ * @details This macro will select capture counter reload trigger source.
+ * \hideinitializer
+ */
+#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc))
+
+/**
+ * @brief This macro is used to select capture timer clock divide.
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Clkdiv The input source
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_1
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_4
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_16
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_32
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_64
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_96
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_112
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_128
+ * @return None
+ * @details This macro will select capture timer clock has a pre-divider with eight divided option.
+ * \hideinitializer
+ */
+#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv))
+
+/**
+ * @brief This macro is used to select capture timer/counter clock source
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32ClkSrc The input source
+ * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK
+ * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0
+ * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1
+ * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2
+ * @return None
+ * @details This macro will select capture timer/clock clock source.
+ * \hideinitializer
+ */
+#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc))
+
+/**
+ * @brief This macro is used to read input capture status
+ * @param[in] ecap Specify ECAP port
+ * @return Input capture status flags
+ * @details This macro will get the input capture interrupt status.
+ * \hideinitializer
+ */
+#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS)
+
+/**
+ * @brief This macro is used to get input channel interrupt flag
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Mask The input channel mask
+ * - \ref ECAP_STATUS_CAPTF0_Msk
+ * - \ref ECAP_STATUS_CAPTF1_Msk
+ * - \ref ECAP_STATUS_CAPTF2_Msk
+ * - \ref ECAP_STATUS_CAPOVF_Msk
+ * - \ref ECAP_STATUS_CAPCMPF_Msk
+ * @return None
+ * @details This macro will write 1 to get the input channel_n interrupt flag.
+ * \hideinitializer
+ */
+#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0)
+
+/**
+ * @brief This macro is used to clear input channel interrupt flag
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Mask The input channel mask
+ * - \ref ECAP_STATUS_CAPTF0_Msk
+ * - \ref ECAP_STATUS_CAPTF1_Msk
+ * - \ref ECAP_STATUS_CAPTF2_Msk
+ * - \ref ECAP_STATUS_CAPOVF_Msk
+ * - \ref ECAP_STATUS_CAPCMPF_Msk
+ * @return None
+ * @details This macro will write 1 to clear the input channel_n interrupt flag.
+ * \hideinitializer
+ */
+#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask))
+
+/**
+ * @brief This macro is used to set input capture counter value
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Val Counter value
+ * @return None
+ * @details This macro will set a counter value of input capture.
+ * \hideinitializer
+ */
+#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val))
+
+/**
+ * @brief This macro is used to get input capture counter value
+ * @param[in] ecap Specify ECAP port
+ * @return Capture counter value
+ * @details This macro will get a counter value of input capture.
+ * \hideinitializer
+ */
+#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT)
+
+/**
+ * @brief This macro is used to get input capture counter hold value
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Index The input channel number
+ * - \ref ECAP_IC0
+ * - \ref ECAP_IC1
+ * - \ref ECAP_IC2
+ * @return Capture counter hold value
+ * @details This macro will get a hold value of input capture channel_n.
+ * \hideinitializer
+ */
+#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index)))
+
+/**
+ * @brief This macro is used to set input capture counter compare value
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Val Input capture compare value
+ * @return None
+ * @details This macro will set a compare value of input capture counter.
+ * \hideinitializer
+ */
+#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val))
+
+void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask);
+void ECAP_Close(ECAP_T* ecap);
+void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask);
+void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask);
+/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group ECAP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_ECAP_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_emac.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_emac.h
new file mode 100644
index 00000000000..152873d76ac
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_emac.h
@@ -0,0 +1,357 @@
+/**************************************************************************//**
+ * @file nu_emac.h
+ * @version V1.00
+ * @brief M480 EMAC driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_EMAC_H__
+#define __NU_EMAC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EMAC_Driver EMAC Driver
+ @{
+*/
+
+/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
+ @{
+*/
+
+#define EMAC_PHY_ADDR 1UL /*!< PHY address, this address is board dependent \hideinitializer */
+#define EMAC_RX_DESC_SIZE 4UL /*!< Number of Rx Descriptors, should be 2 at least \hideinitializer */
+#define EMAC_TX_DESC_SIZE 4UL /*!< Number of Tx Descriptors, should be 2 at least \hideinitializer */
+#define EMAC_CAMENTRY_NB 16UL /*!< Number of CAM \hideinitializer */
+#define EMAC_MAX_PKT_SIZE 1524UL /*!< Number of HDR + EXTRA + VLAN_TAG + PAYLOAD + CRC \hideinitializer */
+
+#define EMAC_LINK_DOWN 0UL /*!< Ethernet link is down \hideinitializer */
+#define EMAC_LINK_100F 1UL /*!< Ethernet link is 100Mbps full duplex \hideinitializer */
+#define EMAC_LINK_100H 2UL /*!< Ethernet link is 100Mbps half duplex \hideinitializer */
+#define EMAC_LINK_10F 3UL /*!< Ethernet link is 10Mbps full duplex \hideinitializer */
+#define EMAC_LINK_10H 4UL /*!< Ethernet link is 10Mbps half duplex \hideinitializer */
+
+/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Enable EMAC Tx function
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_ENABLE_TX() (EMAC->CTL |= EMAC_CTL_TXON_Msk)
+
+
+/**
+ * @brief Enable EMAC Rx function
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0)
+
+/**
+ * @brief Disable EMAC Tx function
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_DISABLE_TX() (EMAC->CTL &= ~EMAC_CTL_TXON_Msk)
+
+
+/**
+ * @brief Disable EMAC Rx function
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_DISABLE_RX() (EMAC->CTL &= ~EMAC_CTL_RXON_Msk)
+
+/**
+ * @brief Enable EMAC Magic Packet Wakeup function
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_ENABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL |= EMAC_CTL_WOLEN_Msk)
+
+/**
+ * @brief Disable EMAC Magic Packet Wakeup function
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_DISABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk)
+
+/**
+ * @brief Enable EMAC to receive broadcast packets
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_ENABLE_RECV_BCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk)
+
+/**
+ * @brief Disable EMAC to receive broadcast packets
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_DISABLE_RECV_BCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk)
+
+/**
+ * @brief Enable EMAC to receive multicast packets
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_ENABLE_RECV_MCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk)
+
+/**
+ * @brief Disable EMAC Magic Packet Wakeup function
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_DISABLE_RECV_MCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk)
+
+/**
+ * @brief Check if EMAC time stamp alarm interrupt occurred or not
+ * @param None
+ * @return If time stamp alarm interrupt occurred or not
+ * @retval 0 Alarm interrupt does not occur
+ * @retval 1 Alarm interrupt occurred
+ * \hideinitializer
+ */
+#define EMAC_GET_ALARM_FLAG() (EMAC->INTSTS & EMAC_INTSTS_TSALMIF_Msk ? 1 : 0)
+
+/**
+ * @brief Clear EMAC time stamp alarm interrupt flag
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define EMAC_CLR_ALARM_FLAG() (EMAC->INTSTS = EMAC_INTSTS_TSALMIF_Msk)
+
+/**
+ * @brief Trigger EMAC Rx function
+ * @param None
+ * @return None
+ */
+#define EMAC_TRIGGER_RX() do{EMAC->RXST = 0UL;}while(0)
+
+/**
+ * @brief Trigger EMAC Tx function
+ * @param None
+ * @return None
+ */
+#define EMAC_TRIGGER_TX() do{EMAC->TXST = 0UL;}while(0)
+
+/**
+ * @brief Enable specified EMAC interrupt
+ *
+ * @param[in] emac The pointer of the specified EMAC module
+ * @param[in] u32eIntSel Interrupt type select
+ * - \ref EMAC_INTEN_RXIEN_Msk : Receive
+ * - \ref EMAC_INTEN_CRCEIEN_Msk : CRC Error
+ * - \ref EMAC_INTEN_RXOVIEN_Msk : Receive FIFO Overflow
+ * - \ref EMAC_INTEN_LPIEN_Msk : Long Packet
+ * - \ref EMAC_INTEN_RXGDIEN_Msk : Receive Good
+ * - \ref EMAC_INTEN_ALIEIEN_Msk : Alignment Error
+ * - \ref EMAC_INTEN_RPIEN_Msk : Runt Packet
+ * - \ref EMAC_INTEN_MPCOVIEN_Msk : Miss Packet Counter Overrun
+ * - \ref EMAC_INTEN_MFLEIEN_Msk : Maximum Frame Length Exceed
+ * - \ref EMAC_INTEN_DENIEN_Msk : DMA Early Notification
+ * - \ref EMAC_INTEN_RDUIEN_Msk : Receive Descriptor Unavailable
+ * - \ref EMAC_INTEN_RXBEIEN_Msk : Receive Bus Error
+ * - \ref EMAC_INTEN_CFRIEN_Msk : Control Frame Receive
+ * - \ref EMAC_INTEN_WOLIEN_Msk : Wake on LAN Interrupt
+ * - \ref EMAC_INTEN_TXIEN_Msk : Transmit
+ * - \ref EMAC_INTEN_TXUDIEN_Msk : Transmit FIFO Underflow
+ * - \ref EMAC_INTEN_TXCPIEN_Msk : Transmit Completion
+ * - \ref EMAC_INTEN_EXDEFIEN_Msk : Defer Exceed
+ * - \ref EMAC_INTEN_NCSIEN_Msk : No Carrier Sense
+ * - \ref EMAC_INTEN_TXABTIEN_Msk : Transmit Abort
+ * - \ref EMAC_INTEN_LCIEN_Msk : Late Collision
+ * - \ref EMAC_INTEN_TDUIEN_Msk : Transmit Descriptor Unavailable
+ * - \ref EMAC_INTEN_TXBEIEN_Msk : Transmit Bus Error
+ * - \ref EMAC_INTEN_TSALMIEN_Msk : Time Stamp Alarm
+ *
+ * @return None
+ *
+ * @details This macro enable specified EMAC interrupt.
+ * \hideinitializer
+ */
+#define EMAC_ENABLE_INT(emac, u32eIntSel) ((emac)->INTEN |= (u32eIntSel))
+
+/**
+ * @brief Disable specified EMAC interrupt
+ *
+ * @param[in] emac The pointer of the specified EMAC module
+ * @param[in] u32eIntSel Interrupt type select
+ * - \ref EMAC_INTEN_RXIEN_Msk : Receive
+ * - \ref EMAC_INTEN_CRCEIEN_Msk : CRC Error
+ * - \ref EMAC_INTEN_RXOVIEN_Msk : Receive FIFO Overflow
+ * - \ref EMAC_INTEN_LPIEN_Msk : Long Packet
+ * - \ref EMAC_INTEN_RXGDIEN_Msk : Receive Good
+ * - \ref EMAC_INTEN_ALIEIEN_Msk : Alignment Error
+ * - \ref EMAC_INTEN_RPIEN_Msk : Runt Packet
+ * - \ref EMAC_INTEN_MPCOVIEN_Msk : Miss Packet Counter Overrun
+ * - \ref EMAC_INTEN_MFLEIEN_Msk : Maximum Frame Length Exceed
+ * - \ref EMAC_INTEN_DENIEN_Msk : DMA Early Notification
+ * - \ref EMAC_INTEN_RDUIEN_Msk : Receive Descriptor Unavailable
+ * - \ref EMAC_INTEN_RXBEIEN_Msk : Receive Bus Error
+ * - \ref EMAC_INTEN_CFRIEN_Msk : Control Frame Receive
+ * - \ref EMAC_INTEN_WOLIEN_Msk : Wake on LAN Interrupt
+ * - \ref EMAC_INTEN_TXIEN_Msk : Transmit
+ * - \ref EMAC_INTEN_TXUDIEN_Msk : Transmit FIFO Underflow
+ * - \ref EMAC_INTEN_TXCPIEN_Msk : Transmit Completion
+ * - \ref EMAC_INTEN_EXDEFIEN_Msk : Defer Exceed
+ * - \ref EMAC_INTEN_NCSIEN_Msk : No Carrier Sense
+ * - \ref EMAC_INTEN_TXABTIEN_Msk : Transmit Abort
+ * - \ref EMAC_INTEN_LCIEN_Msk : Late Collision
+ * - \ref EMAC_INTEN_TDUIEN_Msk : Transmit Descriptor Unavailable
+ * - \ref EMAC_INTEN_TXBEIEN_Msk : Transmit Bus Error
+ * - \ref EMAC_INTEN_TSALMIEN_Msk : Time Stamp Alarm
+ *
+ * @return None
+ *
+ * @details This macro disable specified EMAC interrupt.
+ * \hideinitializer
+ */
+#define EMAC_DISABLE_INT(emac, u32eIntSel) ((emac)->INTEN &= ~ (u32eIntSel))
+
+/**
+ * @brief Get specified interrupt flag/status
+ *
+ * @param[in] emac The pointer of the specified EMAC module
+ * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
+ * - \ref EMAC_INTSTS_RXIF_Msk : Receive
+ * - \ref EMAC_INTSTS_CRCEIF_Msk : CRC Error
+ * - \ref EMAC_INTSTS_RXOVIF_Msk : Receive FIFO Overflow
+ * - \ref EMAC_INTSTS_LPIF_Msk : Long Packet
+ * - \ref EMAC_INTSTS_RXGDIF_Msk : Receive Good
+ * - \ref EMAC_INTSTS_ALIEIF_Msk : Alignment Error
+ * - \ref EMAC_INTSTS_RPIF_Msk : Runt Packet
+ * - \ref EMAC_INTSTS_MPCOVIF_Msk : Missed Packet Counter
+ * - \ref EMAC_INTSTS_MFLEIF_Msk : Maximum Frame Length Exceed
+ * - \ref EMAC_INTSTS_DENIF_Msk : DMA Early Notification
+ * - \ref EMAC_INTSTS_RDUIF_Msk : Receive Descriptor Unavailable
+ * - \ref EMAC_INTSTS_RXBEIF_Msk : Receive Bus Error
+ * - \ref EMAC_INTSTS_CFRIF_Msk : Control Frame Receive
+ * - \ref EMAC_INTSTS_WOLIF_Msk : Wake on LAN
+ * - \ref EMAC_INTSTS_TXIF_Msk : Transmit
+ * - \ref EMAC_INTSTS_TXUDIF_Msk : Transmit FIFO Underflow
+ * - \ref EMAC_INTSTS_TXCPIF_Msk : Transmit Completion
+ * - \ref EMAC_INTSTS_EXDEFIF_Msk : Defer Exceed
+ * - \ref EMAC_INTSTS_NCSIF_Msk : No Carrier Sense
+ * - \ref EMAC_INTSTS_TXABTIF_Msk : Transmit Abort
+ * - \ref EMAC_INTSTS_LCIF_Msk : Late Collision
+ * - \ref EMAC_INTSTS_TDUIF_Msk : Transmit Descriptor Unavailable
+ * - \ref EMAC_INTSTS_TXBEIF_Msk : Transmit Bus Error
+ * - \ref EMAC_INTSTS_TSALMIF_Msk : Time Stamp Alarm
+ *
+ * @return None
+ *
+ * @details This macro get specified interrupt flag or interrupt indicator status.
+ * \hideinitializer
+ */
+#define EMAC_GET_INT_FLAG(emac, u32eIntTypeFlag) (((emac)->INTSTS & (u32eIntTypeFlag))?1:0)
+
+/**
+ * @brief Clear specified interrupt flag/status
+ *
+ * @param[in] emac The pointer of the specified EMAC module
+ * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
+ * - \ref EMAC_INTSTS_RXIF_Msk : Receive
+ * - \ref EMAC_INTSTS_CRCEIF_Msk : CRC Error
+ * - \ref EMAC_INTSTS_RXOVIF_Msk : Receive FIFO Overflow
+ * - \ref EMAC_INTSTS_LPIF_Msk : Long Packet
+ * - \ref EMAC_INTSTS_RXGDIF_Msk : Receive Good
+ * - \ref EMAC_INTSTS_ALIEIF_Msk : Alignment Error
+ * - \ref EMAC_INTSTS_RPIF_Msk : Runt Packet
+ * - \ref EMAC_INTSTS_MPCOVIF_Msk : Missed Packet Counter
+ * - \ref EMAC_INTSTS_MFLEIF_Msk : Maximum Frame Length Exceed
+ * - \ref EMAC_INTSTS_DENIF_Msk : DMA Early Notification
+ * - \ref EMAC_INTSTS_RDUIF_Msk : Receive Descriptor Unavailable
+ * - \ref EMAC_INTSTS_RXBEIF_Msk : Receive Bus Error
+ * - \ref EMAC_INTSTS_CFRIF_Msk : Control Frame Receive
+ * - \ref EMAC_INTSTS_WOLIF_Msk : Wake on LAN
+ * - \ref EMAC_INTSTS_TXIF_Msk : Transmit
+ * - \ref EMAC_INTSTS_TXUDIF_Msk : Transmit FIFO Underflow
+ * - \ref EMAC_INTSTS_TXCPIF_Msk : Transmit Completion
+ * - \ref EMAC_INTSTS_EXDEFIF_Msk : Defer Exceed
+ * - \ref EMAC_INTSTS_NCSIF_Msk : No Carrier Sense
+ * - \ref EMAC_INTSTS_TXABTIF_Msk : Transmit Abort
+ * - \ref EMAC_INTSTS_LCIF_Msk : Late Collision
+ * - \ref EMAC_INTSTS_TDUIF_Msk : Transmit Descriptor Unavailable
+ * - \ref EMAC_INTSTS_TXBEIF_Msk : Transmit Bus Error
+ * - \ref EMAC_INTSTS_TSALMIF_Msk : Time Stamp Alarm
+ *
+ * @retval 0 The specified interrupt is not happened.
+ * 1 The specified interrupt is happened.
+ *
+ * @details This macro clear specified interrupt flag or interrupt indicator status.
+ * \hideinitializer
+ */
+#define EMAC_CLEAR_INT_FLAG(emac, u32eIntTypeFlag) ((emac)->INTSTS |= (u32eIntTypeFlag))
+
+void EMAC_Open(uint8_t *pu8MacAddr);
+void EMAC_Close(void);
+void EMAC_SetMacAddr(uint8_t *pu8MacAddr);
+void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[]);
+void EMAC_DisableCamEntry(uint32_t u32Entry);
+
+uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size);
+uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec);
+void EMAC_RecvPktDone(void);
+
+uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size);
+uint32_t EMAC_SendPktDone(void);
+uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec);
+
+void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_DisableTS(void);
+void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec);
+void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_DisableAlarm(void);
+
+uint32_t EMAC_CheckLinkStatus(void);
+
+void EMAC_PhyInit(void);
+int32_t EMAC_FillCamEntry(uint8_t pu8MacAddr[]);
+uint8_t *EMAC_ClaimFreeTXBuf(void);
+uint32_t EMAC_GetAvailRXBufSize(uint8_t** ppuDataBuf);
+uint32_t EMAC_SendPktWoCopy(uint32_t u32Size);
+void EMAC_RecvPktDoneWoRxTrigger(void);
+
+/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EMAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_EMAC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_epwm.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_epwm.h
new file mode 100644
index 00000000000..01557f8054e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_epwm.h
@@ -0,0 +1,645 @@
+/**************************************************************************//**
+ * @file nu_epwm.h
+ * @version V3.00
+ * @brief M480 series EPWM driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_EPWM_H__
+#define __NU_EPWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EPWM_Driver EPWM Driver
+ @{
+*/
+
+/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants
+ @{
+*/
+#define EPWM_CHANNEL_NUM (6U) /*!< EPWM channel number \hideinitializer */
+#define EPWM_CH_0_MASK (0x1U) /*!< EPWM channel 0 mask \hideinitializer */
+#define EPWM_CH_1_MASK (0x2U) /*!< EPWM channel 1 mask \hideinitializer */
+#define EPWM_CH_2_MASK (0x4U) /*!< EPWM channel 2 mask \hideinitializer */
+#define EPWM_CH_3_MASK (0x8U) /*!< EPWM channel 3 mask \hideinitializer */
+#define EPWM_CH_4_MASK (0x10U) /*!< EPWM channel 4 mask \hideinitializer */
+#define EPWM_CH_5_MASK (0x20U) /*!< EPWM channel 5 mask \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Counter Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_UP_COUNTER (0U) /*!< Up counter type \hideinitializer */
+#define EPWM_DOWN_COUNTER (1U) /*!< Down counter type \hideinitializer */
+#define EPWM_UP_DOWN_COUNTER (2U) /*!< Up-Down counter type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Aligned Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_EDGE_ALIGNED (1U) /*!< EPWM working in edge aligned type(down count) \hideinitializer */
+#define EPWM_CENTER_ALIGNED (2U) /*!< EPWM working in center aligned type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Output Level Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_OUTPUT_NOTHING (0U) /*!< EPWM output nothing \hideinitializer */
+#define EPWM_OUTPUT_LOW (1U) /*!< EPWM output low \hideinitializer */
+#define EPWM_OUTPUT_HIGH (2U) /*!< EPWM output high \hideinitializer */
+#define EPWM_OUTPUT_TOGGLE (3U) /*!< EPWM output toggle \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Synchronous Start Function Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_SSCTL_SSRC_EPWM0 (0U<CTL1 = (epwm)->CTL1 | (0x7ul<CTL1 = (epwm)->CTL1 & ~(0x7ul<CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief This macro disable group mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to disable group mode of EPWM module.
+ * \hideinitializer
+ */
+#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief Enable timer synchronous start counting function of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32SyncSrc Synchronous start source selection, valid values are:
+ * - \ref EPWM_SSCTL_SSRC_EPWM0
+ * - \ref EPWM_SSCTL_SSRC_EPWM1
+ * - \ref EPWM_SSCTL_SSRC_BPWM0
+ * - \ref EPWM_SSCTL_SSRC_BPWM1
+ * @return None
+ * @details This macro is used to enable timer synchronous start counting function of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask))
+
+/**
+ * @brief Disable timer synchronous start counting function of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to disable timer synchronous start counting function of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \
+ do{ \
+ int i;\
+ for(i = 0; i < 6; i++) { \
+ if((u32ChannelMask) & (1 << i)) \
+ (epwm)->SSCTL &= ~(1UL << i); \
+ } \
+ }while(0)
+
+/**
+ * @brief This macro enable EPWM counter synchronous start counting function.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time.
+ * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC().
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk)
+
+/**
+ * @brief This macro enable output inverter of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to enable output inverter of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask))
+
+/**
+ * @brief This macro get captured rising data
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured rising data of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
+
+/**
+ * @brief This macro get captured falling data
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured falling data of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
+
+/**
+ * @brief This macro mask output logic to high or low
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32LevelMask Output logic to high or low
+ * @return None
+ * @details This macro is used to mask output logic to high or low of specified channel(s).
+ * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
+ * \hideinitializer
+ */
+#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \
+ { \
+ (epwm)->MSKEN = (u32ChannelMask); \
+ (epwm)->MSK = (u32LevelMask); \
+ }
+
+/**
+ * @brief This macro set the prescaler of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
+ * @return None
+ * @details This macro is used to set the prescaler of specified channel.
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
+ * The clock of EPWM counter is divided by (u32Prescaler + 1).
+ * \hideinitializer
+ */
+#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler))
+
+/**
+ * @brief This macro get the prescaler of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
+ * @details This macro is used to get the prescaler of specified channel.
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
+ * The clock of EPWM counter is divided by (u32Prescaler + 1).
+ * \hideinitializer
+ */
+#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U])
+
+/**
+ * @brief This macro set the comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the comparator of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * \hideinitializer
+ */
+#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
+
+/**
+ * @brief This macro get the comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF
+ * @details This macro is used to get the comparator of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)])
+
+/**
+ * @brief This macro set the free trigger comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the free trigger comparator of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * \hideinitializer
+ */
+#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR))
+
+/**
+ * @brief This macro set the period of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the period of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * @note EPWM counter will stop if period length set to 0.
+ * \hideinitializer
+ */
+#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
+
+/**
+ * @brief This macro get the period of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return the period of specified channel. Valid values are between 0~0xFFFF
+ * @details This macro is used to get the period of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)])
+
+/**
+ * @brief This macro set the EPWM aligned type
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32AlignedType EPWM aligned type, valid values are:
+ * - \ref EPWM_EDGE_ALIGNED
+ * - \ref EPWM_CENTER_ALIGNED
+ * @return None
+ * @details This macro is used to set the EPWM aligned type of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \
+ do{ \
+ int i; \
+ for(i = 0; i < 6; i++) { \
+ if((u32ChannelMask) & (1 << i)) \
+ (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \
+ } \
+ }while(0)
+
+/**
+ * @brief Set load window of window loading mode for specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to set load window of window loading mode for specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask))
+
+/**
+ * @brief Trigger synchronous event from specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4
+ * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @return None
+ * @details This macro is used to trigger synchronous event from specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1)))
+
+/**
+ * @brief Clear counter of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to clear counter of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask))
+
+/**
+ * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32ZeroLevel output level at zero point, valid values are:
+ * - \ref EPWM_OUTPUT_NOTHING
+ * - \ref EPWM_OUTPUT_LOW
+ * - \ref EPWM_OUTPUT_HIGH
+ * - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
+ * - \ref EPWM_OUTPUT_NOTHING
+ * - \ref EPWM_OUTPUT_LOW
+ * - \ref EPWM_OUTPUT_HIGH
+ * - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
+ * - \ref EPWM_OUTPUT_NOTHING
+ * - \ref EPWM_OUTPUT_LOW
+ * - \ref EPWM_OUTPUT_HIGH
+ * - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
+ * - \ref EPWM_OUTPUT_NOTHING
+ * - \ref EPWM_OUTPUT_LOW
+ * - \ref EPWM_OUTPUT_HIGH
+ * - \ref EPWM_OUTPUT_TOGGLE
+ * @return None
+ * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
+ do{ \
+ int i; \
+ for(i = 0; i < 6; i++) { \
+ if((u32ChannelMask) & (1 << i)) { \
+ (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \
+ (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \
+ (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \
+ (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \
+ } \
+ } \
+ }while(0)
+
+/**
+ * @brief Trigger brake event from specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @param[in] u32BrakeType Type of brake trigger.
+ * - \ref EPWM_FB_EDGE
+ * - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This macro is used to trigger brake event from specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
+
+/**
+ * @brief Set Dead zone clock source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
+ * @return None
+ * @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
+ * @note The write-protection function should be disabled before using this function.
+ * \hideinitializer
+ */
+#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \
+ ((epwm)->DTCTL[(u32ChannelNum) >> 1] = (((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \
+ ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos)))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define EPWM functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
+uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
+void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum);
+int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt);
+void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
+void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
+void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration);
+void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
+void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource);
+uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
+void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
+void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
+void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm);
+void EPWM_EnableSyncPinInverse(EPWM_T *epwm);
+void EPWM_DisableSyncPinInverse(EPWM_T *epwm);
+void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
+void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
+void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable);
+uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel);
+void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle);
+void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt);
+void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+
+/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EPWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_EPWM_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_fmc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_fmc.h
new file mode 100644
index 00000000000..d2aa0e96bdc
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_fmc.h
@@ -0,0 +1,302 @@
+/**************************************************************************//**
+ * @file nu_fmc.h
+ * @version V1.00
+ * @brief M480 Series Flash Memory Controller Driver Header File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_FMC_H__
+#define __NU_FMC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+ @{
+*/
+
+
+/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Base Address */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_APROM_BASE 0x00000000UL /*!< APROM base address \hideinitializer */
+#define FMC_APROM_END 0x00080000UL /*!< APROM end address \hideinitializer */
+#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address \hideinitializer */
+#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM base address \hideinitializer */
+#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address \hideinitializer */
+#define FMC_SPROM_BASE 0x00200000UL /*!< SPROM base address \hideinitializer */
+#define FMC_SPROM_END 0x00201000UL /*!< SPROM end address \hideinitializer */
+#define FMC_XOM_BASE 0x00200000UL /*!< XOM Base Address \hideinitializer */
+#define FMC_XOMR0_BASE 0x00200000UL /*!< XOMR 0 Base Address \hideinitializer */
+#define FMC_XOMR1_BASE 0x00200010UL /*!< XOMR 1 Base Address \hideinitializer */
+#define FMC_XOMR2_BASE 0x00200020UL /*!< XOMR 2 Base Address \hideinitializer */
+#define FMC_XOMR3_BASE 0x00200030UL /*!< XOMR 3 Base Address \hideinitializer */
+#define FMC_CONFIG_BASE 0x00300000UL /*!< User Configuration address \hideinitializer */
+#define FMC_USER_CONFIG_0 0x00300000UL /*!< User Config 0 address \hideinitializer */
+#define FMC_USER_CONFIG_1 0x00300004UL /*!< User Config 1 address \hideinitializer */
+#define FMC_USER_CONFIG_2 0x00300008UL /*!< User Config 2 address \hideinitializer */
+#define FMC_KPROM_BASE 0x00301000UL /*!< Security ROM base address \hideinitializer */
+#define FMC_OTP_BASE 0x00310000UL /*!< OTP flash base address \hideinitializer */
+
+#define FMC_FLASH_PAGE_SIZE 0x1000UL /*!< Flash Page Size (4K bytes) \hideinitializer */
+#define FMC_PAGE_ADDR_MASK 0xFFFFF000UL /*!< Flash page address mask \hideinitializer */
+#define FMC_MULTI_WORD_PROG_LEN 512 /*!< The maximum length of a multi-word program. */
+
+#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size \hideinitializer */
+#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size \hideinitializer */
+#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) \hideinitializer */
+#define FMC_SPROM_SIZE 0x1000UL /*!< SPROM Size (4 Kbytes) \hideinitializer */
+#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* XOM region number constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define XOMR0 0UL /*!< XOM region 0 */
+#define XOMR1 1UL /*!< XOM region 1 */
+#define XOMR2 2UL /*!< XOM region 2 */
+#define XOMR3 3UL /*!< XOM region 3 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ISPCTL constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define IS_BOOT_FROM_LDROM 0x1UL /*!< ISPCTL setting to select to boot from LDROM */
+#define IS_BOOT_FROM_APROM 0x0UL /*!< ISPCTL setting to select to boot from APROM */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ISPCMD constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read flash word \hideinitializer */
+#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID \hideinitializer */
+#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result \hideinitializer */
+#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID \hideinitializer */
+#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID \hideinitializer */
+#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read checksum \hideinitializer */
+#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: Write flash word \hideinitializer */
+#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash \hideinitializer */
+#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Erase Flash bank 0 or 1 \hideinitializer */
+#define FMC_ISPCMD_BLOCK_ERASE 0x25UL /*!< ISP Command: Erase 4 pages alignment of APROM in bank 0 or 1 \hideinitializer */
+#define FMC_ISPCMD_PROGRAM_MUL 0x27UL /*!< ISP Command: Multuple word program \hideinitializer */
+#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification \hideinitializer */
+#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run checksum calculation \hideinitializer */
+#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Vector Page Remap \hideinitializer */
+#define FMC_ISPCMD_READ_64 0x40UL /*!< ISP Command: Read double flash word \hideinitializer */
+#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: Write double flash word \hideinitializer */
+
+#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. \hideinitializer */
+#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. \hideinitializer */
+#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. \hideinitializer */
+
+
+/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup FMC_EXPORTED_MACROS FMC Exported Macros
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macros */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM \hideinitializer */
+#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM \hideinitializer */
+#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM update \hideinitializer */
+#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM update \hideinitializer */
+#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable User Config update \hideinitializer */
+#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable User Config update \hideinitializer */
+#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM update \hideinitializer */
+#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM update \hideinitializer */
+#define FMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk) /*!< Enable SPROM update \hideinitializer */
+#define FMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk) /*!< Disable SPROM update \hideinitializer */
+#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP function \hideinitializer */
+#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP function \hideinitializer */
+#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag \hideinitializer */
+#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag \hideinitializer */
+
+/*@}*/ /* end of group FMC_EXPORTED_MACROS */
+
+
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+__STATIC_INLINE uint32_t FMC_ReadCID(void);
+__STATIC_INLINE uint32_t FMC_ReadPID(void);
+__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index);
+__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index);
+__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
+__STATIC_INLINE uint32_t FMC_GetVECMAP(void);
+
+/**
+ * @brief Get current vector mapping address.
+ * @param None
+ * @return The current vector mapping address.
+ * @details To get VECMAP value which is the page address for remapping to vector page (0x0).
+ * @note
+ * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
+ */
+__STATIC_INLINE uint32_t FMC_GetVECMAP(void)
+{
+ return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);
+}
+
+/**
+ * @brief Read company ID
+ * @param None
+ * @return The company ID (32-bit)
+ * @details The company ID of Nuvoton is fixed to be 0xDA
+ */
+__STATIC_INLINE uint32_t FMC_ReadCID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */
+ FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Read product ID
+ * @param None
+ * @return The product ID (32-bit)
+ * @details This function is used to read product ID.
+ */
+__STATIC_INLINE uint32_t FMC_ReadPID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */
+ FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Read Unique ID
+ * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
+ * @return The 32-bit unique ID data of specified UID index.
+ * @details To read out 96-bit Unique ID.
+ */
+__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID;
+ FMC->ISPADDR = ((uint32_t)u8Index << 2u);
+ FMC->ISPDAT = 0u;
+ FMC->ISPTRG = 0x1u;
+#if ISBEN
+ __ISB();
+#endif
+ while(FMC->ISPTRG) {}
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief To read UCID
+ * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
+ * @return The UCID of specified index
+ * @details This function is used to read unique chip ID (UCID).
+ */
+__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
+ FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Set vector mapping address
+ * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment.
+ * @return To set VECMAP to remap specified page address to 0x0.
+ * @details This function is used to set VECMAP to map specified page to vector page (0x0).
+ * @note
+ * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
+ */
+__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
+ FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */
+ FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG) {} /* Waiting for ISP Done */
+}
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+extern void FMC_Close(void);
+extern int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page);
+extern int32_t FMC_Erase(uint32_t u32PageAddr);
+extern int32_t FMC_Erase_SPROM(void);
+extern int32_t FMC_Erase_Block(uint32_t u32BlockAddr);
+extern int32_t FMC_Erase_Bank(uint32_t u32BankAddr);
+extern int32_t FMC_EraseXOM(uint32_t xom_num);
+extern int32_t FMC_GetXOMState(uint32_t xom_num);
+extern int32_t FMC_GetBootSource(void);
+extern void FMC_Open(void);
+extern uint32_t FMC_Read(uint32_t u32Addr);
+extern int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1);
+extern uint32_t FMC_ReadDataFlashBaseAddr(void);
+extern void FMC_SetBootSource(int32_t i32BootSrc);
+extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
+extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1);
+extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len);
+extern int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word);
+extern int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word);
+extern int32_t FMC_Lock_OTP(uint32_t otp_num);
+extern int32_t FMC_Is_OTP_Locked(uint32_t otp_num);
+extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count);
+extern int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count);
+extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count);
+extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count);
+extern int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM);
+extern int32_t FMC_CompareSPKey(uint32_t key[3]);
+
+
+/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group FMC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_FMC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_gpio.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_gpio.h
new file mode 100644
index 00000000000..08ce10ce59e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_gpio.h
@@ -0,0 +1,497 @@
+/**************************************************************************//**
+ * @file GPIO.h
+ * @version V3.00
+ * @brief M480 series GPIO driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_GPIO_H__
+#define __NU_GPIO_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+ @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
+ @{
+*/
+
+
+#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO_MODE Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode \hideinitializer */
+#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode \hideinitializer */
+#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode \hideinitializer */
+#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO Interrupt Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge \hideinitializer */
+#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge \hideinitializer */
+#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge \hideinitializer */
+#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High \hideinitializer */
+#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO_INTTYPE Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode \hideinitializer */
+#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO Slew Rate Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode \hideinitializer */
+#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode \hideinitializer */
+#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO Pull-up And Pull-down Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode \hideinitializer */
+#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode \hideinitializer */
+#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO_DBCTL Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset \hideinitializer */
+#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 \hideinitializer */
+
+#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz \hideinitializer */
+#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK \hideinitializer */
+
+#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks \hideinitializer */
+
+
+/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
+ Example 1:
+
+ PA0 = 1;
+
+ It is used to set GPIO PA.0 to high;
+
+ Example 2:
+
+ if (PA0)
+ PA0 = 0;
+
+ If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.
+ */
+#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) /*!< Pin Data Input/Output \hideinitializer */
+#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output \hideinitializer */
+#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output \hideinitializer */
+#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output \hideinitializer */
+#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output \hideinitializer */
+#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output \hideinitializer */
+#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output \hideinitializer */
+#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output \hideinitializer */
+#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output \hideinitializer */
+#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output \hideinitializer */
+#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output \hideinitializer */
+#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output \hideinitializer */
+#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output \hideinitializer */
+#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output \hideinitializer */
+#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output \hideinitializer */
+#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output \hideinitializer */
+#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output \hideinitializer */
+#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output \hideinitializer */
+#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output \hideinitializer */
+#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output \hideinitializer */
+#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output \hideinitializer */
+#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output \hideinitializer */
+#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output \hideinitializer */
+#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output \hideinitializer */
+#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output \hideinitializer */
+#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output \hideinitializer */
+#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output \hideinitializer */
+#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output \hideinitializer */
+#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output \hideinitializer */
+#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output \hideinitializer */
+#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output \hideinitializer */
+#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output \hideinitializer */
+#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output \hideinitializer */
+#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output \hideinitializer */
+#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output \hideinitializer */
+#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output \hideinitializer */
+#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output \hideinitializer */
+#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output \hideinitializer */
+#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output \hideinitializer */
+#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output \hideinitializer */
+#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output \hideinitializer */
+#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output \hideinitializer */
+#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output \hideinitializer */
+#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output \hideinitializer */
+#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output \hideinitializer */
+#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output \hideinitializer */
+#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output \hideinitializer */
+#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output \hideinitializer */
+#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output \hideinitializer */
+#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output \hideinitializer */
+#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output \hideinitializer */
+#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output \hideinitializer */
+#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output \hideinitializer */
+#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output \hideinitializer */
+#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output \hideinitializer */
+#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output \hideinitializer */
+#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output \hideinitializer */
+#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output \hideinitializer */
+#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output \hideinitializer */
+#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output \hideinitializer */
+#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output \hideinitializer */
+#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output \hideinitializer */
+#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output \hideinitializer */
+#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output \hideinitializer */
+#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output \hideinitializer */
+#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output \hideinitializer */
+#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output \hideinitializer */
+#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output \hideinitializer */
+#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output \hideinitializer */
+#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output \hideinitializer */
+#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output \hideinitializer */
+#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output \hideinitializer */
+#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output \hideinitializer */
+#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output \hideinitializer */
+#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output \hideinitializer */
+#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output \hideinitializer */
+#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output \hideinitializer */
+#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output \hideinitializer */
+#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output \hideinitializer */
+#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output \hideinitializer */
+#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output \hideinitializer */
+#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output \hideinitializer */
+#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output \hideinitializer */
+#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output \hideinitializer */
+#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output \hideinitializer */
+#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output \hideinitializer */
+#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output \hideinitializer */
+#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output \hideinitializer */
+#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output \hideinitializer */
+#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output \hideinitializer */
+#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output \hideinitializer */
+#define PG0 GPIO_PIN_DATA(6, 0 ) /*!< Specify PG.0 Pin Data Input/Output \hideinitializer */
+#define PG1 GPIO_PIN_DATA(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output \hideinitializer */
+#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output \hideinitializer */
+#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output \hideinitializer */
+#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output \hideinitializer */
+#define PG5 GPIO_PIN_DATA(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output \hideinitializer */
+#define PG6 GPIO_PIN_DATA(6, 6 ) /*!< Specify PG.6 Pin Data Input/Output \hideinitializer */
+#define PG7 GPIO_PIN_DATA(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output \hideinitializer */
+#define PG8 GPIO_PIN_DATA(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output \hideinitializer */
+#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output \hideinitializer */
+#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output \hideinitializer */
+#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output \hideinitializer */
+#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output \hideinitializer */
+#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output \hideinitializer */
+#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output \hideinitializer */
+#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output \hideinitializer */
+#define PH0 GPIO_PIN_DATA(7, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */
+#define PH1 GPIO_PIN_DATA(7, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */
+#define PH2 GPIO_PIN_DATA(7, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */
+#define PH3 GPIO_PIN_DATA(7, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */
+#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */
+#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */
+#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */
+#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */
+#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */
+#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */
+#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */
+#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear GPIO Pin Interrupt Flag
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Clear the interrupt status of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))
+
+/**
+ * @brief Disable Pin De-bounce Function
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Disable the interrupt de-bounce function of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))
+
+/**
+ * @brief Enable Pin De-bounce Function
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ * @return None
+ *
+ * @details Enable the interrupt de-bounce function of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))
+
+/**
+ * @brief Disable I/O Digital Input Path
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Disable I/O digital input path of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
+
+/**
+ * @brief Enable I/O Digital Input Path
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Enable I/O digital input path of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))
+
+/**
+ * @brief Disable I/O DOUT mask
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Disable I/O DOUT mask of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))
+
+/**
+ * @brief Enable I/O DOUT mask
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Enable I/O DOUT mask of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
+
+/**
+ * @brief Get GPIO Pin Interrupt Flag
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @retval 0 No interrupt at specified GPIO pin
+ * @retval 1 The specified GPIO pin generate an interrupt
+ *
+ * @details Get the interrupt status of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))
+
+/**
+ * @brief Set De-bounce Sampling Cycle Time
+ *
+ * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.
+ * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be
+ * - \ref GPIO_DBCTL_DBCLKSEL_1
+ * - \ref GPIO_DBCTL_DBCLKSEL_2
+ * - \ref GPIO_DBCTL_DBCLKSEL_4
+ * - \ref GPIO_DBCTL_DBCLKSEL_8
+ * - \ref GPIO_DBCTL_DBCLKSEL_16
+ * - \ref GPIO_DBCTL_DBCLKSEL_32
+ * - \ref GPIO_DBCTL_DBCLKSEL_64
+ * - \ref GPIO_DBCTL_DBCLKSEL_128
+ * - \ref GPIO_DBCTL_DBCLKSEL_256
+ * - \ref GPIO_DBCTL_DBCLKSEL_512
+ * - \ref GPIO_DBCTL_DBCLKSEL_1024
+ * - \ref GPIO_DBCTL_DBCLKSEL_2048
+ * - \ref GPIO_DBCTL_DBCLKSEL_4096
+ * - \ref GPIO_DBCTL_DBCLKSEL_8192
+ * - \ref GPIO_DBCTL_DBCLKSEL_16384
+ * - \ref GPIO_DBCTL_DBCLKSEL_32768
+ *
+ * @return None
+ *
+ * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
+ * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
+ * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
+ * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,
+ * and system will sampling interrupt input once per 00 us.
+ * \hideinitializer
+ */
+#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
+
+/**
+ * @brief Get GPIO Port IN Data
+ *
+* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ *
+ * @return The specified port data
+ *
+ * @details Get the PIN register of specified GPIO port.
+ * \hideinitializer
+ */
+#define GPIO_GET_IN_DATA(port) ((port)->PIN)
+
+/**
+ * @brief Set GPIO Port OUT Data
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Data GPIO port data.
+ *
+ * @return None
+ *
+ * @details Set the Data into specified GPIO port.
+ * \hideinitializer
+ */
+#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
+
+/**
+ * @brief Toggle Specified GPIO pin
+ *
+ * @param[in] u32Pin Pxy
+ *
+ * @return None
+ *
+ * @details Toggle the specified GPIO pint.
+ * \hideinitializer
+ */
+#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
+
+
+/**
+ * @brief Enable External GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Pin The pin of specified GPIO port.
+ * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be 0 ~ 13 for PE GPIO port.
+ * It could be 0 ~ 11 for PG GPIO port.
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ * \hideinitializer
+ */
+#define GPIO_EnableEINT GPIO_EnableInt
+
+/**
+ * @brief Disable External GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Pin The pin of specified GPIO port.
+ * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be 0 ~ 13 for PE GPIO port.
+ * It could be 0 ~ 11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ * \hideinitializer
+ */
+#define GPIO_DisableEINT GPIO_DisableInt
+
+
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_GPIO_H__ */
+
+/*** (C) COPYRIGHT 2013~2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsotg.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsotg.h
new file mode 100644
index 00000000000..b561f226748
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsotg.h
@@ -0,0 +1,268 @@
+/**************************************************************************//**
+ * @file nu_hsotg.h
+ * @version V0.10
+ * @brief M480 Series HSOTG Driver Header File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_HSOTG_H__
+#define __NU_HSOTG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup HSOTG_Driver HSOTG Driver
+ @{
+*/
+
+
+/** @addtogroup HSOTG_EXPORTED_CONSTANTS HSOTG Exported Constants
+ @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* HSOTG constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define HSOTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */
+#define HSOTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */
+#define HSOTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */
+#define HSOTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */
+
+
+/*@}*/ /* end of group HSOTG_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup HSOTG_EXPORTED_FUNCTIONS HSOTG Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Macros and functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+ * @brief This macro is used to enable HSOTG function
+ * @param None
+ * @return None
+ * @details This macro will set OTGEN bit of HSOTG_CTL register to enable HSOTG function.
+ * \hideinitializer
+ */
+#define HSOTG_ENABLE() (HSOTG->CTL |= HSOTG_CTL_OTGEN_Msk)
+
+/**
+ * @brief This macro is used to disable HSOTG function
+ * @param None
+ * @return None
+ * @details This macro will clear OTGEN bit of HSOTG_CTL register to disable HSOTG function.
+ * \hideinitializer
+ */
+#define HSOTG_DISABLE() (HSOTG->CTL &= ~HSOTG_CTL_OTGEN_Msk)
+
+/**
+ * @brief This macro is used to enable USB PHY
+ * @param None
+ * @return None
+ * @details When the USB role is selected as HSOTG device, use this macro to enable USB PHY.
+ * This macro will set OTGPHYEN bit of HSOTG_PHYCTL register to enable USB PHY.
+ * \hideinitializer
+ */
+#define HSOTG_ENABLE_PHY() (HSOTG->PHYCTL |= HSOTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+ * @brief This macro is used to disable USB PHY
+ * @param None
+ * @return None
+ * @details This macro will clear OTGPHYEN bit of HSOTG_PHYCTL register to disable USB PHY.
+ * \hideinitializer
+ */
+#define HSOTG_DISABLE_PHY() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+ * @brief This macro is used to enable ID detection function
+ * @param None
+ * @return None
+ * @details This macro will set IDDETEN bit of HSOTG_PHYCTL register to enable ID detection function.
+ * \hideinitializer
+ */
+#define HSOTG_ENABLE_ID_DETECT() (HSOTG->PHYCTL |= HSOTG_PHYCTL_IDDETEN_Msk)
+
+/**
+ * @brief This macro is used to disable ID detection function
+ * @param None
+ * @return None
+ * @details This macro will clear IDDETEN bit of HSOTG_PHYCTL register to disable ID detection function.
+ * \hideinitializer
+ */
+#define HSOTG_DISABLE_ID_DETECT() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_IDDETEN_Msk)
+
+/**
+ * @brief This macro is used to enable HSOTG wake-up function
+ * @param None
+ * @return None
+ * @details This macro will set WKEN bit of HSOTG_CTL register to enable HSOTG wake-up function.
+ * \hideinitializer
+ */
+#define HSOTG_ENABLE_WAKEUP() (HSOTG->CTL |= HSOTG_CTL_WKEN_Msk)
+
+/**
+ * @brief This macro is used to disable HSOTG wake-up function
+ * @param None
+ * @return None
+ * @details This macro will clear WKEN bit of HSOTG_CTL register to disable HSOTG wake-up function.
+ * \hideinitializer
+ */
+#define HSOTG_DISABLE_WAKEUP() (HSOTG->CTL &= ~HSOTG_CTL_WKEN_Msk)
+
+/**
+ * @brief This macro is used to set the polarity of USB_VBUS_EN pin
+ * @param[in] u32Pol The polarity selection. Valid values are listed below.
+ * - \ref HSOTG_VBUS_EN_ACTIVE_HIGH
+ * - \ref HSOTG_VBUS_EN_ACTIVE_LOW
+ * @return None
+ * @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
+ * \hideinitializer
+ */
+#define HSOTG_SET_VBUS_EN_POL(u32Pol) (HSOTG->PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask))
+
+/**
+ * @brief This macro is used to disable HSOTG related interrupts
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref HSOTG_INTEN_ROLECHGIEN_Msk
+ * - \ref HSOTG_INTEN_VBEIEN_Msk
+ * - \ref HSOTG_INTEN_SRPFIEN_Msk
+ * - \ref HSOTG_INTEN_HNPFIEN_Msk
+ * - \ref HSOTG_INTEN_GOIDLEIEN_Msk
+ * - \ref HSOTG_INTEN_IDCHGIEN_Msk
+ * - \ref HSOTG_INTEN_PDEVIEN_Msk
+ * - \ref HSOTG_INTEN_HOSTIEN_Msk
+ * - \ref HSOTG_INTEN_BVLDCHGIEN_Msk
+ * - \ref HSOTG_INTEN_AVLDCHGIEN_Msk
+ * - \ref HSOTG_INTEN_VBCHGIEN_Msk
+ * - \ref HSOTG_INTEN_SECHGIEN_Msk
+ * - \ref HSOTG_INTEN_SRPDETIEN_Msk
+ * @return None
+ * @details This macro will disable HSOTG related interrupts specified by u32Mask parameter.
+ * \hideinitializer
+ */
+#define HSOTG_DISABLE_INT(u32Mask) (HSOTG->INTEN &= ~(u32Mask))
+
+/**
+ * @brief This macro is used to get HSOTG related interrupt flags
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref HSOTG_INTSTS_ROLECHGIF_Msk
+ * - \ref HSOTG_INTSTS_VBEIF_Msk
+ * - \ref HSOTG_INTSTS_SRPFIF_Msk
+ * - \ref HSOTG_INTSTS_HNPFIF_Msk
+ * - \ref HSOTG_INTSTS_GOIDLEIF_Msk
+ * - \ref HSOTG_INTSTS_IDCHGIF_Msk
+ * - \ref HSOTG_INTSTS_PDEVIF_Msk
+ * - \ref HSOTG_INTSTS_HOSTIF_Msk
+ * - \ref HSOTG_INTSTS_BVLDCHGIF_Msk
+ * - \ref HSOTG_INTSTS_AVLDCHGIF_Msk
+ * - \ref HSOTG_INTSTS_VBCHGIF_Msk
+ * - \ref HSOTG_INTSTS_SECHGIF_Msk
+ * - \ref HSOTG_INTSTS_SRPDETIF_Msk
+ * @return Interrupt flags of selected sources.
+ * @details This macro will return HSOTG related interrupt flags specified by u32Mask parameter.
+ * \hideinitializer
+ */
+#define HSOTG_GET_INT_FLAG(u32Mask) (HSOTG->INTSTS & (u32Mask))
+
+/**
+ * @brief This macro is used to clear HSOTG related interrupt flags
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref HSOTG_INTSTS_ROLECHGIF_Msk
+ * - \ref HSOTG_INTSTS_VBEIF_Msk
+ * - \ref HSOTG_INTSTS_SRPFIF_Msk
+ * - \ref HSOTG_INTSTS_HNPFIF_Msk
+ * - \ref HSOTG_INTSTS_GOIDLEIF_Msk
+ * - \ref HSOTG_INTSTS_IDCHGIF_Msk
+ * - \ref HSOTG_INTSTS_PDEVIF_Msk
+ * - \ref HSOTG_INTSTS_HOSTIF_Msk
+ * - \ref HSOTG_INTSTS_BVLDCHGIF_Msk
+ * - \ref HSOTG_INTSTS_AVLDCHGIF_Msk
+ * - \ref HSOTG_INTSTS_VBCHGIF_Msk
+ * - \ref HSOTG_INTSTS_SECHGIF_Msk
+ * - \ref HSOTG_INTSTS_SRPDETIF_Msk
+ * @return None
+ * @details This macro will clear HSOTG related interrupt flags specified by u32Mask parameter.
+ * \hideinitializer
+ */
+#define HSOTG_CLR_INT_FLAG(u32Mask) (HSOTG->INTSTS = (u32Mask))
+
+/**
+ * @brief This macro is used to get HSOTG related status
+ * @param[in] u32Mask The combination of user specified source. Valid values are listed below.
+ * - \ref HSOTG_STATUS_OVERCUR_Msk
+ * - \ref HSOTG_STATUS_IDSTS_Msk
+ * - \ref HSOTG_STATUS_SESSEND_Msk
+ * - \ref HSOTG_STATUS_BVLD_Msk
+ * - \ref HSOTG_STATUS_AVLD_Msk
+ * - \ref HSOTG_STATUS_VBUSVLD_Msk
+ * @return The user specified status.
+ * @details This macro will return HSOTG related status specified by u32Mask parameter.
+ * \hideinitializer
+ */
+#define HSOTG_GET_STATUS(u32Mask) (HSOTG->STATUS & (u32Mask))
+
+
+
+/*@}*/ /* end of group HSOTG_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group HSOTG_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __NU_HSOTG_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsusbd.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsusbd.h
new file mode 100644
index 00000000000..3fcebb1b2da
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsusbd.h
@@ -0,0 +1,382 @@
+/**************************************************************************//**
+ * @file nu_hsusbd.h
+ * @version V1.00
+ * @brief M480 HSUSBD driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_HSUSBD_H__
+#define __NU_HSUSBD_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup HSUSBD_Driver HSUSBD Driver
+ @{
+*/
+
+/** @addtogroup HSUSBD_EXPORTED_CONSTANTS HSUSBD Exported Constants
+ @{
+*/
+/** @cond HIDDEN_SYMBOLS */
+#define HSUSBD_MAX_EP 12ul
+
+#define Maximum(a,b) (a)>(b) ? (a) : (b)
+#define Minimum(a,b) (((a)<(b)) ? (a) : (b))
+
+
+#define CEP 0xfful /*!< Control Endpoint \hideinitializer */
+#define EPA 0ul /*!< Endpoint A \hideinitializer */
+#define EPB 1ul /*!< Endpoint B \hideinitializer */
+#define EPC 2ul /*!< Endpoint C \hideinitializer */
+#define EPD 3ul /*!< Endpoint D \hideinitializer */
+#define EPE 4ul /*!< Endpoint E \hideinitializer */
+#define EPF 5ul /*!< Endpoint F \hideinitializer */
+#define EPG 6ul /*!< Endpoint G \hideinitializer */
+#define EPH 7ul /*!< Endpoint H \hideinitializer */
+#define EPI 8ul /*!< Endpoint I \hideinitializer */
+#define EPJ 9ul /*!< Endpoint J \hideinitializer */
+#define EPK 10ul /*!< Endpoint K \hideinitializer */
+#define EPL 11ul /*!< Endpoint L \hideinitializer */
+
+/** @endcond HIDDEN_SYMBOLS */
+/********************* Bit definition of CEPCTL register **********************/
+#define HSUSBD_CEPCTL_NAKCLR ((uint32_t)0x00000000ul) /*!PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk|HSUSBD_PHYCTL_DPPUEN_Msk))) /*!PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!PHYCTL |= HSUSBD_PHYCTL_PHYEN_Msk)) /*!PHYCTL &= ~HSUSBD_PHYCTL_PHYEN_Msk)) /*!PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!PHYCTL |= HSUSBD_PHYCTL_DPPUEN_Msk)) /*!FADDR = (addr)) /*!FADDR)) /*!GINTEN = (intr)) /*!BUSINTEN = (intr)) /*!BUSINTSTS) /*!BUSINTSTS = (flag)) /*!CEPINTEN = (intr)) /*!CEPINTSTS = (flag)) /*!CEPCTL = (flag)) /*!CEPTXCNT = (size)) /*!EP[(ep)].EPMPS = (size)) /*!EP[(ep)].EPINTEN = (intr)) /*!EP[(ep)].EPINTSTS) /*!EP[(ep)].EPINTSTS = (flag)) /*!DMACNT = (len)) /*!DMAADDR = (addr)) /*!DMACTL = (HSUSBD->DMACTL & ~HSUSBD_DMACTL_EPNUM_Msk) | HSUSBD_DMACTL_DMARD_Msk | (epnum) | 0x100) /*!DMACTL = (HSUSBD->DMACTL & ~(HSUSBD_DMACTL_EPNUM_Msk | HSUSBD_DMACTL_DMARD_Msk | 0x100)) | (epnum)) /*!DMACTL |= HSUSBD_DMACTL_DMAEN_Msk) /*!PHYCTL & HSUSBD_PHYCTL_VBUSDET_Msk)) /*!DMACNT = 0ul;
+ HSUSBD->DMACTL = 0x80ul;
+ HSUSBD->DMACTL = 0x00ul;
+}
+/**
+ * @brief HSUSBD_SetEpBufAddr, Set Endpoint buffer address
+ * @param[in] u32Ep Endpoint Number
+ * @param[in] u32Base Buffer Start Address
+ * @param[in] u32Len Buffer length
+ * @retval None.
+ */
+__STATIC_INLINE void HSUSBD_SetEpBufAddr(uint32_t u32Ep, uint32_t u32Base, uint32_t u32Len)
+{
+ if (u32Ep == CEP)
+ {
+ HSUSBD->CEPBUFST = u32Base;
+ HSUSBD->CEPBUFEND = u32Base + u32Len - 1ul;
+ }
+ else
+ {
+ HSUSBD->EP[u32Ep].EPBUFST = u32Base;
+ HSUSBD->EP[u32Ep].EPBUFEND = u32Base + u32Len - 1ul;
+ }
+}
+
+/**
+ * @brief HSUSBD_ConfigEp, Config Endpoint
+ * @param[in] u32Ep USB endpoint
+ * @param[in] u32EpNum Endpoint number
+ * @param[in] u32EpType Endpoint type
+ * @param[in] u32EpDir Endpoint direction
+ * @retval None.
+ */
+__STATIC_INLINE void HSUSBD_ConfigEp(uint32_t u32Ep, uint32_t u32EpNum, uint32_t u32EpType, uint32_t u32EpDir)
+{
+ if (u32EpType == HSUSBD_EP_CFG_TYPE_BULK)
+ {
+ HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_AUTO);
+ }
+ else if (u32EpType == HSUSBD_EP_CFG_TYPE_INT)
+ {
+ HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_MANUAL);
+ }
+ else if (u32EpType == HSUSBD_EP_CFG_TYPE_ISO)
+ {
+ HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_FLY);
+ }
+
+ HSUSBD->EP[u32Ep].EPCFG = (u32EpType|u32EpDir|HSUSBD_EP_CFG_VALID|(u32EpNum << 4));
+}
+
+/**
+ * @brief Set USB endpoint stall state
+ * @param[in] u32Ep The USB endpoint ID.
+ * @return None
+ * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
+ */
+__STATIC_INLINE void HSUSBD_SetEpStall(uint32_t u32Ep)
+{
+ if (u32Ep == CEP)
+ {
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL);
+ }
+ else
+ {
+ HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT;
+ }
+}
+
+/**
+ * @brief Set USB endpoint stall state
+ *
+ * @param[in] u32EpNum USB endpoint
+ * @return None
+ *
+ * @details Set USB endpoint stall state, endpoint will return STALL token.
+ */
+__STATIC_INLINE void HSUSBD_SetStall(uint32_t u32EpNum)
+{
+ uint32_t i;
+
+ if (u32EpNum == 0ul)
+ {
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL);
+ }
+ else
+ {
+ for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum)
+ {
+ HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT;
+ }
+ }
+ }
+}
+
+/**
+ * @brief Clear USB endpoint stall state
+ * @param[in] u32Ep The USB endpoint ID.
+ * @return None
+ * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
+ */
+__STATIC_INLINE void HSUSBD_ClearEpStall(uint32_t u32Ep)
+{
+ HSUSBD->EP[u32Ep].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE;
+}
+
+/**
+ * @brief Clear USB endpoint stall state
+ *
+ * @param[in] u32EpNum USB endpoint
+ * @return None
+ *
+ * @details Clear USB endpoint stall state, endpoint will return ACK/NAK token.
+ */
+__STATIC_INLINE void HSUSBD_ClearStall(uint32_t u32EpNum)
+{
+ uint32_t i;
+
+ for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum)
+ {
+ HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE;
+ }
+ }
+}
+
+/**
+ * @brief Get USB endpoint stall state
+ * @param[in] u32Ep The USB endpoint ID.
+ * @retval 0 USB endpoint is not stalled.
+ * @retval Others USB endpoint is stalled.
+ * @details Get USB endpoint stall state of the specified endpoint ID.
+ */
+__STATIC_INLINE uint32_t HSUSBD_GetEpStall(uint32_t u32Ep)
+{
+ return (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT);
+}
+
+/**
+ * @brief Get USB endpoint stall state
+ *
+ * @param[in] u32EpNum USB endpoint
+ * @retval 0: USB endpoint is not stalled.
+ * @retval non-0: USB endpoint is stalled.
+ *
+ * @details Get USB endpoint stall state.
+ */
+__STATIC_INLINE uint32_t HSUSBD_GetStall(uint32_t u32EpNum)
+{
+ uint32_t i;
+ uint32_t val = 0ul;
+
+ for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum)
+ {
+ val = (HSUSBD->EP[i].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT);
+ break;
+ }
+ }
+ return val;
+}
+
+
+/*-------------------------------------------------------------------------------------------*/
+typedef void (*HSUSBD_VENDOR_REQ)(void); /*!CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl))
+
+/**
+ * @brief The macro is used to set START condition of I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Set the I2C bus START condition in I2C_CTL register.
+ * \hideinitializer
+ */
+#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
+
+/**
+ * @brief The macro is used to wait I2C bus status get ready
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
+ * \hideinitializer
+ */
+#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
+
+/**
+ * @brief The macro is used to Read I2C Bus Data Register
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return A byte of I2C data register
+ *
+ * @details I2C controller read data from bus and save it in I2CDAT register.
+ * \hideinitializer
+ */
+#define I2C_GET_DATA(i2c) ((i2c)->DAT)
+
+/**
+ * @brief Write a Data to I2C Data Register
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8Data A byte that writes to data register
+ *
+ * @return None
+ *
+ * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
+ * \hideinitializer
+ */
+#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
+
+/**
+ * @brief Get I2C Bus status code
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C status code
+ *
+ * @details To get this status code to monitor I2C bus event.
+ * \hideinitializer
+ */
+#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
+
+/**
+ * @brief Get Time-out flag from I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @retval 0 I2C Bus time-out is not happened
+ * @retval 1 I2C Bus time-out is happened
+ *
+ * @details When I2C bus occurs time-out event, the time-out flag will be set.
+ * \hideinitializer
+ */
+#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
+
+/**
+ * @brief To get wake-up flag from I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @retval 0 Chip is not woken-up from power-down mode
+ * @retval 1 Chip is woken-up from power-down mode
+ *
+ * @details I2C bus occurs wake-up event, wake-up flag will be set.
+ * \hideinitializer
+ */
+#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
+
+/**
+ * @brief To clear wake-up flag
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details If wake-up flag is set, use this macro to clear it.
+ * \hideinitializer
+ */
+#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
+
+/**
+ * @brief To get SMBus Status
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return SMBus status
+ *
+ * @details To get the Bus Management status of I2C_BUSSTS register
+ * \hideinitializer
+ *
+ */
+#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
+
+/**
+ * @brief Get SMBus CRC value
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return Packet error check byte value
+ *
+ * @details The CRC check value after a transmission or a reception by count by using CRC8
+ * \hideinitializer
+ */
+#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
+
+/**
+ * @brief Set SMBus Bytes number of Transmission or reception
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u32PktSize Transmit / Receive bytes
+ *
+ * @return None
+ *
+ * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
+
+/**
+ * @brief Enable SMBus Alert function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
+ * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
+ * \hideinitializer
+ */
+#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
+
+/**
+ * @brief Disable SMBus Alert pin function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
+ * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
+ * \hideinitializer
+ */
+#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
+
+/**
+ * @brief Set SMBus SUSCON pin is output mode
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
+ *
+ * \hideinitializer
+ */
+#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
+
+/**
+ * @brief Set SMBus SUSCON pin is input mode
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
+ *
+ * \hideinitializer
+ */
+#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
+
+/**
+ * @brief Set SMBus SUSCON pin output high state
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
+
+
+/**
+ * @brief Set SMBus SUSCON pin output low state
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
+
+/**
+ * @brief Enable SMBus Acknowledge control by manual
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
+
+/**
+ * @brief Disable SMBus Acknowledge control by manual
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Disable acknowledge response control by user.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
+
+/**
+ * @brief Enable SMBus Acknowledge manual interrupt
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
+ * \hideinitializer
+ */
+#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
+
+/**
+ * @brief Disable SMBus Acknowledge manual interrupt
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
+ * \hideinitializer
+ */
+#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
+
+/**
+ * @brief Enable SMBus PEC clear at REPEAT START
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
+
+/**
+ * @brief Disable SMBus PEC clear at Repeat START
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function is used to disable the condition of Repeat START can clear the PEC calculation.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
+
+/**
+ * @brief Enable RX PDMA function.
+ * @param[in] i2c The pointer of the specified I2C module.
+ * @return None.
+ * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
+ * \hideinitializer
+ */
+#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
+
+/**
+ * @brief Enable TX PDMA function.
+ * @param[in] i2c The pointer of the specified I2C module.
+ * @return None.
+ * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
+ * \hideinitializer
+ */
+#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
+
+/**
+ * @brief Disable RX PDMA transfer.
+ * @param[in] i2c The pointer of the specified I2C module.
+ * @return None.
+ * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
+ * \hideinitializer
+ */
+#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
+
+/**
+ * @brief Disable TX PDMA transfer.
+ * @param[in] i2c The pointer of the specified I2C module.
+ * @return None.
+ * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
+ * \hideinitializer
+ */
+#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
+
+/**
+ * @brief Enable PDMA stretch function.
+ * @param[in] i2c The pointer of the specified I2C module.
+ * @return None.
+ * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
+ * \hideinitializer
+ */
+#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
+
+/**
+ * @brief Disable PDMA stretch function.
+ * @param[in] i2c The pointer of the specified I2C module.
+ * @return None.
+ * @details I2C will send STOP after PDMA transfers done automatically.
+ * \hideinitializer
+ */
+#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
+
+/**
+ * @brief Reset PDMA function.
+ * @param[in] i2c The pointer of the specified I2C module.
+ * @return None.
+ * @details I2C PDMA engine will be reset after this function is called.
+ * \hideinitializer
+ */
+#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void I2C_STOP(I2C_T *i2c);
+
+/**
+ * @brief The macro is used to set STOP condition of I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Set the I2C bus STOP condition in I2C_CTL register.
+ */
+__STATIC_INLINE void I2C_STOP(I2C_T *i2c)
+{
+
+ (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);
+ while(i2c->CTL0 & I2C_CTL0_STO_Msk)
+ {
+ }
+}
+
+void I2C_ClearTimeoutFlag(I2C_T *i2c);
+void I2C_Close(I2C_T *i2c);
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
+void I2C_DisableInt(I2C_T *i2c);
+void I2C_EnableInt(I2C_T *i2c);
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
+uint32_t I2C_GetIntFlag(I2C_T *i2c);
+uint32_t I2C_GetStatus(I2C_T *i2c);
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
+uint8_t I2C_GetData(I2C_T *i2c);
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
+void I2C_DisableTimeout(I2C_T *i2c);
+void I2C_EnableWakeup(I2C_T *i2c);
+void I2C_DisableWakeup(I2C_T *i2c);
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag);
+uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data);
+uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);
+uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
+uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);
+uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
+uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);
+uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
+uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);
+uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
+uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);
+uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
+uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
+void I2C_SMBusClose(I2C_T *i2c);
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
+
+/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group I2C_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_i2s.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_i2s.h
new file mode 100644
index 00000000000..096c6c0d1ae
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_i2s.h
@@ -0,0 +1,353 @@
+/****************************************************************************//**
+ * @file nu_i2s.h
+ * @version V0.10
+ * @brief M480 I2S driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_I2S_H__
+#define __NU_I2S_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup I2S_Driver I2S Driver
+ @{
+*/
+
+/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants
+ @{
+*/
+#define I2S_DATABIT_8 (0U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
+#define I2S_DATABIT_16 (1U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
+#define I2S_DATABIT_24 (2U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
+#define I2S_DATABIT_32 (3U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
+
+/* Audio Format */
+#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */
+#define I2S_DISABLE_MONO (0U) /*!< Stereo channel \hideinitializer */
+
+/* I2S Data Format */
+#define I2S_FORMAT_I2S (0U << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */
+#define I2S_FORMAT_I2S_MSB (1U << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */
+#define I2S_FORMAT_I2S_LSB (2U << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */
+#define I2S_FORMAT_PCM (4U << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */
+#define I2S_FORMAT_PCM_MSB (5U << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */
+#define I2S_FORMAT_PCM_LSB (6U << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */
+
+/* I2S Data Format */
+#define I2S_ORDER_AT_MSB (0U) /*!< Channel data is at MSB \hideinitializer */
+#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */
+
+/* I2S TDM Channel Number */
+#define I2S_TDM_2CH 0U /*!< Use TDM 2 channel \hideinitializer */
+#define I2S_TDM_4CH 1U /*!< Use TDM 4 channel \hideinitializer */
+#define I2S_TDM_6CH 2U /*!< Use TDM 6 channel \hideinitializer */
+#define I2S_TDM_8CH 3U /*!< Use TDM 8 channel \hideinitializer */
+
+/* I2S TDM Channel Width */
+#define I2S_TDM_WIDTH_8BIT 0U /*!< TDM channel witch is 8-bit \hideinitializer */
+#define I2S_TDM_WIDTH_16BIT 1U /*!< TDM channel witch is 16-bit \hideinitializer */
+#define I2S_TDM_WIDTH_24BIT 2U /*!< TDM channel witch is 24-bit \hideinitializer */
+#define I2S_TDM_WIDTH_32BIT 3U /*!< TDM channel witch is 32-bit \hideinitializer */
+
+/* I2S TDM Sync Width */
+#define I2S_TDM_SYNC_ONE_BCLK 0U /*!< TDM sync widht is one BLCK period \hideinitializer */
+#define I2S_TDM_SYNC_ONE_CHANNEL 1U /*!< TDM sync widht is one channel period \hideinitializer */
+
+/* I2S Operation mode */
+#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */
+#define I2S_MODE_MASTER (0u) /*!< As master mode \hideinitializer */
+
+/* I2S FIFO Threshold */
+#define I2S_FIFO_TX_LEVEL_WORD_0 (0U) /*!< TX threshold is 0 word \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_1 (1U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_2 (2U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_3 (3U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_4 (4U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_5 (5U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_6 (6U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_7 (7U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_8 (8U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_9 (9U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_10 (10U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_11 (11U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_12 (12U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_13 (13U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_14 (14U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_15 (15U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */
+
+#define I2S_FIFO_RX_LEVEL_WORD_1 (0U) /*!< RX threshold is 1 word \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_2 (1U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_3 (2U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_4 (3U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_5 (4U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_6 (5U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_7 (6U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_8 (7U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_9 (8U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_10 (9U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_11 (10U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_12 (11U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_13 (12U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_14 (13U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_15 (14U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_16 (15U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */
+
+/* I2S Record Channel */
+#define I2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */
+#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
+
+/* I2S Channel */
+#define I2S_RIGHT (0U) /*!< Select right channel \hideinitializer */
+#define I2S_LEFT (1U) /*!< Select left channel \hideinitializer */
+
+/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */
+
+/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+/**
+ * @brief Enable zero cross detect function.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
+ * @return none
+ * \hideinitializer
+ */
+__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
+{
+ if((u32ChMask > 0U) && (u32ChMask < 9U))
+ {
+ i2s->CTL1 |= ((uint32_t)1U << (u32ChMask-1U));
+ }
+}
+
+/**
+ * @brief Disable zero cross detect function.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
+ * @return none
+ * \hideinitializer
+ */
+__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
+{
+ if((u32ChMask > 0U) && (u32ChMask < 9U))
+ {
+ i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask-1U));
+ }
+}
+
+/**
+ * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )
+
+/**
+ * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )
+
+/**
+ * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )
+
+/**
+ * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )
+
+/**
+ * @brief Enable I2S Tx function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )
+
+/**
+ * @brief Disable I2S Tx function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )
+
+/**
+ * @brief Enable I2S Rx function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )
+
+/**
+ * @brief Disable I2S Rx function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )
+
+/**
+ * @brief Enable Tx Mute function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )
+
+/**
+ * @brief Disable Tx Mute function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )
+
+/**
+ * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )
+
+/**
+ * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )
+
+/**
+ * @brief This function sets the recording source channel when mono mode is used.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Ch left or right channel. Valid values are:
+ * - \ref I2S_MONO_LEFT
+ * - \ref I2S_MONO_RIGHT
+ * @return none
+ * \hideinitializer
+ */
+__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
+{
+ u32Ch == I2S_MONO_LEFT ?
+ (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :
+ (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);
+}
+
+/**
+ * @brief Write data to I2S Tx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Data: The data written to FIFO.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) )
+
+/**
+ * @brief Read Rx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @return Data in Rx FIFO.
+ * \hideinitializer
+ */
+#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
+
+/**
+ * @brief This function gets the interrupt flag according to the mask parameter.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Mask is the mask for the all interrupt flags.
+ * @return The masked bit value of interrupt flag.
+ * \hideinitializer
+ */
+#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )
+
+/**
+ * @brief This function clears the interrupt flag according to the mask parameter.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Mask is the mask for the all interrupt flags.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )
+
+/**
+ * @brief This function gets the zero crossing interrupt flag according to the mask parameter.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Mask is the mask for the all interrupt flags.
+ * @return The masked bit value of interrupt flag.
+ * \hideinitializer
+ */
+#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )
+
+/**
+ * @brief This function clears the zero crossing interrupt flag according to the mask parameter.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Mask is the mask for the all interrupt flags.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )
+
+/**
+ * @brief Get transmit FIFO level
+ * @param[in] i2s is the base address of I2S module.
+ * @return FIFO level
+ * \hideinitializer
+ */
+#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )
+
+/**
+ * @brief Get receive FIFO level
+ * @param[in] i2s is the base address of I2S module.
+ * @return FIFO level
+ * \hideinitializer
+ */
+#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )
+
+void I2S_Close(I2S_T *i2s);
+void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
+void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
+uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
+void I2S_DisableMCLK(I2S_T *i2s);
+void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);
+uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat);
+
+/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
+
+
+/*@}*/ /* end of group I2S_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_opa.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_opa.h
new file mode 100644
index 00000000000..8d2baa9d180
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_opa.h
@@ -0,0 +1,209 @@
+/**************************************************************************//**
+ * @file nu_opa.h
+ * @version V3.00
+ * @brief M480 series OPA driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_OPA_H__
+#define __NU_OPA_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup OPA_Driver OPA Driver
+ @{
+*/
+
+/** @addtogroup OPA_EXPORTED_CONSTANTS OPA Exported Constants
+ @{
+*/
+#define OPA_CALIBRATION_CLK_1K (0UL) /*!< OPA calibration clock select 1 KHz \hideinitializer */
+#define OPA_CALIBRATION_RV_1_2_AVDD (0UL) /*!< OPA calibration reference voltage select 1/2 AVDD \hideinitializer */
+#define OPA_CALIBRATION_RV_H_L_VCM (1UL) /*!< OPA calibration reference voltage select from high vcm to low vcm \hideinitializer */
+
+/*@}*/ /* end of group OPA_EXPORTED_CONSTANTS */
+
+/** @addtogroup OPA_EXPORTED_FUNCTIONS OPA Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define OPA functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, uint32_t u32OpaNum, uint32_t u32ClockSel, uint32_t u32LevelSel);
+
+/**
+ * @brief This macro is used to power on the OPA circuit
+ * @param[in] opa The pointer of the specified OPA module
+ * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+ * @return None
+ * @details This macro will set OPx_EN (x=0, 1) bit of OPACR register to power on the OPA circuit.
+ * @note Remember to enable HIRC clock while power on the OPA circuit.
+ * \hideinitializer
+ */
+#define OPA_POWER_ON(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum))))
+
+/**
+ * @brief This macro is used to power down the OPA circuit
+ * @param[in] opa The pointer of the specified OPA module
+ * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+ * @return None
+ * @details This macro will clear OPx_EN (x=0, 1) bit of OPACR register to power down the OPA circuit.
+ * \hideinitializer
+ */
+#define OPA_POWER_DOWN(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum))))
+
+/**
+ * @brief This macro is used to enable the OPA Schmitt trigger buffer
+ * @param[in] opa The pointer of the specified OPA module
+ * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+ * @return None
+ * @details This macro will set OPSCHx_EN (x=0, 1) bit of OPACR register to enable the OPA Schmitt trigger buffer.
+ * \hideinitializer
+ */
+#define OPA_ENABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum))))
+
+/**
+ * @brief This macro is used to disable the OPA Schmitt trigger buffer
+ * @param[in] opa The pointer of the specified OPA module
+ * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+ * @return None
+ * @details This macro will clear OPSCHx_EN (x=0, 1) bit of OPACR register to disable the OPA Schmitt trigger buffer.
+ * \hideinitializer
+ */
+#define OPA_DISABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum))))
+
+/**
+ * @brief This macro is used to enable OPA Schmitt trigger digital output interrupt
+ * @param[in] opa The pointer of the specified OPA module
+ * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+ * @return None
+ * @details This macro will set OPDIEx (x=0, 1) bit of OPACR register to enable the OPA Schmitt trigger digital output interrupt.
+ * \hideinitializer
+ */
+#define OPA_ENABLE_INT(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum))))
+
+/**
+ * @brief This macro is used to disable OPA Schmitt trigger digital output interrupt
+ * @param[in] opa The pointer of the specified OPA module
+ * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+ * @return None
+ * @details This macro will clear OPDIEx (x=0, 1) bit of OPACR register to disable the OPA Schmitt trigger digital output interrupt.
+ * \hideinitializer
+ */
+#define OPA_DISABLE_INT(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum))))
+
+/**
+ * @brief This macro is used to get OPA digital output state
+ * @param[in] opa The pointer of the specified OPA module
+ * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+ * @return OPA digital output state
+ * @details This macro will return the OPA digital output value.
+ * \hideinitializer
+ */
+#define OPA_GET_DIGITAL_OUTPUT(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDO0_Msk<<(u32OpaNum)))?1UL:0UL)
+
+/**
+ * @brief This macro is used to get OPA interrupt flag
+ * @param[in] opa The pointer of the specified OPA module
+ * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+ * @retval 0 OPA interrupt does not occur.
+ * @retval 1 OPA interrupt occurs.
+ * @details This macro will return the ACMP interrupt flag.
+ * \hideinitializer
+ */
+#define OPA_GET_INT_FLAG(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum)))?1UL:0UL)
+
+/**
+ * @brief This macro is used to clear OPA interrupt flag
+ * @param[in] opa The pointer of the specified OPA module
+ * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+ * @return None
+ * @details This macro will write 1 to OPDFx (x=0,1) bit of OPASR register to clear interrupt flag.
+ * \hideinitializer
+ */
+#define OPA_CLR_INT_FLAG(opa, u32OpaNum) ((opa)->STATUS = (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum)))
+
+
+/**
+ * @brief This function is used to configure and start OPA calibration
+ * @param[in] opa The pointer of the specified OPA module
+ * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+ * @param[in] u32ClockSel Select OPA calibration clock
+ * - \ref OPA_CALIBRATION_CLK_1K
+ * @param[in] u32RefVol Select OPA reference voltage
+ * - \ref OPA_CALIBRATION_RV_1_2_AVDD
+ * - \ref OPA_CALIBRATION_RV_H_L_VCM
+ * @retval 0 PMOS and NMOS calibration successfully.
+ * @retval -1 only PMOS calibration failed.
+ * @retval -2 only NMOS calibration failed.
+ * @retval -3 PMOS and NMOS calibration failed.
+ */
+__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa,
+ uint32_t u32OpaNum,
+ uint32_t u32ClockSel,
+ uint32_t u32RefVol)
+{
+ uint32_t u32CALResult;
+ int32_t i32Ret = 0L;
+
+ (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALCLK0_Msk << (u32OpaNum << 1)));
+ (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALRVS0_Msk << (u32OpaNum))) | (((u32RefVol) << OPA_CALCTL_CALRVS0_Pos) << (u32OpaNum));
+ (opa)->CALCTL |= (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum));
+ while((opa)->CALCTL & (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum))) {}
+
+ u32CALResult = ((opa)->CALST >> ((u32OpaNum)*4U)) & (OPA_CALST_CALNS0_Msk|OPA_CALST_CALPS0_Msk);
+ if (u32CALResult == 0U)
+ {
+ i32Ret = 0L;
+ }
+ else if (u32CALResult == OPA_CALST_CALNS0_Msk)
+ {
+ i32Ret = -2L;
+ }
+ else if (u32CALResult == OPA_CALST_CALPS0_Msk)
+ {
+ i32Ret = -1L;
+ }
+ else if (u32CALResult == (OPA_CALST_CALNS0_Msk|OPA_CALST_CALPS0_Msk))
+ {
+ i32Ret = -3L;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief This macro is used to generate asynchronous reset signals to OPA controller
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define OPA_Reset() \
+do { \
+ SYS->IPRST2 |= SYS_IPRST2_OPARST_Msk; \
+ SYS->IPRST2 &= ~SYS_IPRST2_OPARST_Msk; \
+} while(0)
+
+/*@}*/ /* end of group OPA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group OPA_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_OPA_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_otg.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_otg.h
new file mode 100644
index 00000000000..21c4b8be240
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_otg.h
@@ -0,0 +1,268 @@
+/**************************************************************************//**
+ * @file nu_otg.h
+ * @version V0.10
+ * @brief M480 Series OTG Driver Header File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_OTG_H__
+#define __NU_OTG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup OTG_Driver OTG Driver
+ @{
+*/
+
+
+/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants
+ @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* OTG constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */
+#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */
+#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */
+#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */
+
+
+/*@}*/ /* end of group OTG_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Macros and functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+ * @brief This macro is used to enable OTG function
+ * @param None
+ * @return None
+ * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function.
+ * \hideinitializer
+ */
+#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
+
+/**
+ * @brief This macro is used to disable OTG function
+ * @param None
+ * @return None
+ * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function.
+ * \hideinitializer
+ */
+#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
+
+/**
+ * @brief This macro is used to enable USB PHY
+ * @param None
+ * @return None
+ * @details When the USB role is selected as OTG device, use this macro to enable USB PHY.
+ * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY.
+ * \hideinitializer
+ */
+#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+ * @brief This macro is used to disable USB PHY
+ * @param None
+ * @return None
+ * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY.
+ * \hideinitializer
+ */
+#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+ * @brief This macro is used to enable ID detection function
+ * @param None
+ * @return None
+ * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function.
+ * \hideinitializer
+ */
+#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
+
+/**
+ * @brief This macro is used to disable ID detection function
+ * @param None
+ * @return None
+ * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function.
+ * \hideinitializer
+ */
+#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
+
+/**
+ * @brief This macro is used to enable OTG wake-up function
+ * @param None
+ * @return None
+ * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function.
+ * \hideinitializer
+ */
+#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
+
+/**
+ * @brief This macro is used to disable OTG wake-up function
+ * @param None
+ * @return None
+ * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function.
+ * \hideinitializer
+ */
+#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
+
+/**
+ * @brief This macro is used to set the polarity of USB_VBUS_EN pin
+ * @param[in] u32Pol The polarity selection. Valid values are listed below.
+ * - \ref OTG_VBUS_EN_ACTIVE_HIGH
+ * - \ref OTG_VBUS_EN_ACTIVE_LOW
+ * @return None
+ * @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
+ * \hideinitializer
+ */
+#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask))
+
+/**
+ * @brief This macro is used to disable OTG related interrupts
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref OTG_INTEN_ROLECHGIEN_Msk
+ * - \ref OTG_INTEN_VBEIEN_Msk
+ * - \ref OTG_INTEN_SRPFIEN_Msk
+ * - \ref OTG_INTEN_HNPFIEN_Msk
+ * - \ref OTG_INTEN_GOIDLEIEN_Msk
+ * - \ref OTG_INTEN_IDCHGIEN_Msk
+ * - \ref OTG_INTEN_PDEVIEN_Msk
+ * - \ref OTG_INTEN_HOSTIEN_Msk
+ * - \ref OTG_INTEN_BVLDCHGIEN_Msk
+ * - \ref OTG_INTEN_AVLDCHGIEN_Msk
+ * - \ref OTG_INTEN_VBCHGIEN_Msk
+ * - \ref OTG_INTEN_SECHGIEN_Msk
+ * - \ref OTG_INTEN_SRPDETIEN_Msk
+ * @return None
+ * @details This macro will disable OTG related interrupts specified by u32Mask parameter.
+ * \hideinitializer
+ */
+#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask))
+
+/**
+ * @brief This macro is used to get OTG related interrupt flags
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref OTG_INTSTS_ROLECHGIF_Msk
+ * - \ref OTG_INTSTS_VBEIF_Msk
+ * - \ref OTG_INTSTS_SRPFIF_Msk
+ * - \ref OTG_INTSTS_HNPFIF_Msk
+ * - \ref OTG_INTSTS_GOIDLEIF_Msk
+ * - \ref OTG_INTSTS_IDCHGIF_Msk
+ * - \ref OTG_INTSTS_PDEVIF_Msk
+ * - \ref OTG_INTSTS_HOSTIF_Msk
+ * - \ref OTG_INTSTS_BVLDCHGIF_Msk
+ * - \ref OTG_INTSTS_AVLDCHGIF_Msk
+ * - \ref OTG_INTSTS_VBCHGIF_Msk
+ * - \ref OTG_INTSTS_SECHGIF_Msk
+ * - \ref OTG_INTSTS_SRPDETIF_Msk
+ * @return Interrupt flags of selected sources.
+ * @details This macro will return OTG related interrupt flags specified by u32Mask parameter.
+ * \hideinitializer
+ */
+#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask))
+
+/**
+ * @brief This macro is used to clear OTG related interrupt flags
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref OTG_INTSTS_ROLECHGIF_Msk
+ * - \ref OTG_INTSTS_VBEIF_Msk
+ * - \ref OTG_INTSTS_SRPFIF_Msk
+ * - \ref OTG_INTSTS_HNPFIF_Msk
+ * - \ref OTG_INTSTS_GOIDLEIF_Msk
+ * - \ref OTG_INTSTS_IDCHGIF_Msk
+ * - \ref OTG_INTSTS_PDEVIF_Msk
+ * - \ref OTG_INTSTS_HOSTIF_Msk
+ * - \ref OTG_INTSTS_BVLDCHGIF_Msk
+ * - \ref OTG_INTSTS_AVLDCHGIF_Msk
+ * - \ref OTG_INTSTS_VBCHGIF_Msk
+ * - \ref OTG_INTSTS_SECHGIF_Msk
+ * - \ref OTG_INTSTS_SRPDETIF_Msk
+ * @return None
+ * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter.
+ * \hideinitializer
+ */
+#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask))
+
+/**
+ * @brief This macro is used to get OTG related status
+ * @param[in] u32Mask The combination of user specified source. Valid values are listed below.
+ * - \ref OTG_STATUS_OVERCUR_Msk
+ * - \ref OTG_STATUS_IDSTS_Msk
+ * - \ref OTG_STATUS_SESSEND_Msk
+ * - \ref OTG_STATUS_BVLD_Msk
+ * - \ref OTG_STATUS_AVLD_Msk
+ * - \ref OTG_STATUS_VBUSVLD_Msk
+ * @return The user specified status.
+ * @details This macro will return OTG related status specified by u32Mask parameter.
+ * \hideinitializer
+ */
+#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask))
+
+
+
+/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group OTG_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*__NU_OTG_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_pdma.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_pdma.h
new file mode 100644
index 00000000000..8579994db78
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_pdma.h
@@ -0,0 +1,391 @@
+/**************************************************************************//**
+ * @file nu_pdma.h
+ * @version V1.00
+ * @brief M480 series PDMA driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_PDMA_H__
+#define __NU_PDMA_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup PDMA_Driver PDMA Driver
+ @{
+*/
+
+/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
+ @{
+*/
+#define PDMA_CH_MAX 16UL /*!< Specify Maximum Channels of PDMA \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Operation Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_OP_STOP 0x00000000UL /*!INTSTS))
+
+/**
+ * @brief Get Transfer Done Interrupt Status
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @return None
+ *
+ * @details Get the transfer done Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_GET_TD_STS(pdma) ((uint32_t)(pdma->TDSTS))
+
+/**
+ * @brief Clear Transfer Done Interrupt Status
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @param[in] u32Mask The channel mask
+ *
+ * @return None
+ *
+ * @details Clear the transfer done Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_CLR_TD_FLAG(pdma,u32Mask) ((uint32_t)(pdma->TDSTS = (u32Mask)))
+
+/**
+ * @brief Get Target Abort Interrupt Status
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @return None
+ *
+ * @details Get the target abort Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)(pdma->ABTSTS))
+
+/**
+ * @brief Clear Target Abort Interrupt Status
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @param[in] u32Mask The channel mask
+ *
+ * @return None
+ *
+ * @details Clear the target abort Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_CLR_ABORT_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ABTSTS = (u32Mask)))
+
+/**
+ * @brief Get Alignment Interrupt Status
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @return None
+ *
+ * @details Get Alignment Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)(PDMA->ALIGN))
+
+/**
+ * @brief Clear Alignment Interrupt Status
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Mask The channel mask
+ *
+ * @return None
+ *
+ * @details Clear the Alignment Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ALIGN = (u32Mask)))
+
+/**
+ * @brief Clear Timeout Interrupt Status
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ *
+ * @return None
+ *
+ * @details Clear the selected channel timeout interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_CLR_TMOUT_FLAG(pdma,u32Ch) ((uint32_t)(pdma->INTSTS = (1 << ((u32Ch) + 8))))
+
+/**
+ * @brief Check Channel Status
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ *
+ * @retval 0 Idle state
+ * @retval 1 Busy state
+ *
+ * @details Check the selected channel is busy or not.
+ * \hideinitializer
+ */
+#define PDMA_IS_CH_BUSY(pdma,u32Ch) ((uint32_t)(pdma->TRGSTS & (1 << (u32Ch)))? 1 : 0)
+
+/**
+ * @brief Set Source Address
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Addr The selected address
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel source address.
+ * \hideinitializer
+ */
+#define PDMA_SET_SRC_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].SA = (u32Addr)))
+
+/**
+ * @brief Set Destination Address
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Addr The selected address
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel destination address.
+ * \hideinitializer
+ */
+#define PDMA_SET_DST_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].DA = (u32Addr)))
+
+/**
+ * @brief Set Transfer Count
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32TransCount Transfer Count
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel transfer count.
+ * \hideinitializer
+ */
+#define PDMA_SET_TRANS_CNT(pdma,u32Ch, u32TransCount) ((uint32_t)(pdma->DSCT[(u32Ch)].CTL=(pdma->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1) << PDMA_DSCT_CTL_TXCNT_Pos)))
+
+/**
+ * @brief Set Scatter-gather descriptor Address
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Addr The descriptor address
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel scatter-gather descriptor address.
+ * \hideinitializer
+ */
+#define PDMA_SET_SCATTER_DESC(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].NEXT = (u32Addr) - (pdma->SCATBA)))
+
+/**
+ * @brief Stop the channel
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @param[in] u32Ch The selected channel
+ *
+ * @return None
+ *
+ * @details This macro stop the selected channel.
+ * \hideinitializer
+ */
+#define PDMA_STOP(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch))))
+
+/**
+ * @brief Pause the channel
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @param[in] u32Ch The selected channel
+ *
+ * @return None
+ *
+ * @details This macro pause the selected channel.
+ * \hideinitializer
+ */
+#define PDMA_PAUSE(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch))))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define PDMA functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask);
+void PDMA_Close(PDMA_T * pdma);
+void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
+void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
+void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
+void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
+void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask);
+void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask);
+void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
+void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch);
+void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask);
+void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask);
+void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount);
+void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount);
+
+
+/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PDMA_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_PDMA_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qei.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qei.h
new file mode 100644
index 00000000000..217d506fd2a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qei.h
@@ -0,0 +1,390 @@
+/**************************************************************************//**
+ * @file nu_qei.h
+ * @version V3.00
+ * @brief Quadrature Encoder Interface (QEI) driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_QEI_H__
+#define __NU_QEI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup QEI_Driver QEI Driver
+ @{
+*/
+
+/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* QEI counting mode selection constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<CTL &= (~QEI_CTL_CMPEN_Msk))
+
+/**
+ * @brief Enable QEI compare function
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return None
+ * @details This macro enable QEI counter compare function.
+ * \hideinitializer
+ */
+#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk)
+
+/**
+ * @brief Disable QEI index latch function
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return None
+ * @details This macro disable QEI index trigger counter latch function.
+ * \hideinitializer
+ */
+#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk))
+
+/**
+ * @brief Enable QEI index latch function
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return None
+ * @details This macro enable QEI index trigger counter latch function.
+ * \hideinitializer
+ */
+#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk)
+
+/**
+ * @brief Disable QEI index reload function
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return None
+ * @details This macro disable QEI index trigger counter reload function.
+ * \hideinitializer
+ */
+#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk))
+
+/**
+ * @brief Enable QEI index reload function
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return None
+ * @details This macro enable QEI index trigger counter reload function.
+ * \hideinitializer
+ */
+#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk)
+
+/**
+ * @brief Disable QEI input
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32InputType Input signal type.
+ * - \ref QEI_CTL_CHAEN_Msk : QEA input
+ * - \ref QEI_CTL_CHAEN_Msk : QEB input
+ * - \ref QEI_CTL_IDXEN_Msk : IDX input
+ * @return None
+ * @details This macro disable specified QEI signal input.
+ * \hideinitializer
+ */
+#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))
+
+/**
+ * @brief Enable QEI input
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32InputType Input signal type .
+ * - \ref QEI_CTL_CHAEN_Msk : QEA input
+ * - \ref QEI_CTL_CHBEN_Msk : QEB input
+ * - \ref QEI_CTL_IDXEN_Msk : IDX input
+ * @return None
+ * @details This macro enable specified QEI signal input.
+ * \hideinitializer
+ */
+#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType))
+
+/**
+ * @brief Disable inverted input polarity
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32InputType Input signal type .
+ * - \ref QEI_CTL_CHAINV_Msk : QEA Input
+ * - \ref QEI_CTL_CHBINV_Msk : QEB Input
+ * - \ref QEI_CTL_IDXINV_Msk : IDX Input
+ * @return None
+ * @details This macro disable specified QEI signal inverted input polarity.
+ * \hideinitializer
+ */
+#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))
+
+/**
+ * @brief Enable inverted input polarity
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32InputType Input signal type.
+ * - \ref QEI_CTL_CHAINV_Msk : QEA Input
+ * - \ref QEI_CTL_CHBINV_Msk : QEB Input
+ * - \ref QEI_CTL_IDXINV_Msk : IDX Input
+ * @return None
+ * @details This macro inverse specified QEI signal input polarity.
+ * \hideinitializer
+ */
+#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType))
+
+/**
+ * @brief Disable QEI interrupt
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32IntSel Interrupt type selection.
+ * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt
+ * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt
+ * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt
+ * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt
+ * @return None
+ * @details This macro disable specified QEI interrupt.
+ * \hideinitializer
+ */
+#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel))
+
+/**
+ * @brief Enable QEI interrupt
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32IntSel Interrupt type selection.
+ * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt
+ * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt
+ * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt
+ * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt
+ * @return None
+ * @details This macro enable specified QEI interrupt.
+ * \hideinitializer
+ */
+#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel))
+
+/**
+ * @brief Disable QEI noise filter
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return None
+ * @details This macro disable QEI noise filter function.
+ * \hideinitializer
+ */
+#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk)
+
+/**
+ * @brief Enable QEI noise filter
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32ClkSel The sampling frequency of the noise filter clock.
+ * - \ref QEI_CTL_NFCLKSEL_DIV1
+ * - \ref QEI_CTL_NFCLKSEL_DIV2
+ * - \ref QEI_CTL_NFCLKSEL_DIV4
+ * - \ref QEI_CTL_NFCLKSEL_DIV16
+ * - \ref QEI_CTL_NFCLKSEL_DIV32
+ * - \ref QEI_CTL_NFCLKSEL_DIV64
+ * @return None
+ * @details This macro enable QEI noise filter function and select noise filter clock.
+ * \hideinitializer
+ */
+#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel))
+
+/**
+ * @brief Get QEI counter value
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return QEI pulse counter register value.
+ * @details This macro get QEI pulse counter value.
+ * \hideinitializer
+ */
+#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT)
+
+/**
+ * @brief Get QEI counting direction
+ * @param[in] qei The pointer of the specified QEI module.
+ * @retval 0 QEI counter is in down-counting.
+ * @retval 1 QEI counter is in up-counting.
+ * @details This macro get QEI counting direction.
+ * \hideinitializer
+ */
+#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0)
+
+/**
+ * @brief Get QEI counter hold value
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return QEI pulse counter hold register value.
+ * @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control.
+ * \hideinitializer
+ */
+#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD)
+
+/**
+ * @brief Get QEI counter index latch value
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return QEI pulse counter index latch value
+ * @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected.
+ * \hideinitializer
+ */
+#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH)
+
+/**
+ * @brief Set QEI counter index latch value
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32Val The latch value.
+ * @return QEI pulse counter index latch value
+ * @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected.
+ * \hideinitializer
+ */
+#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH = (u32Val))
+
+/**
+ * @brief Get QEI interrupt flag status
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32IntSel Interrupt type selection.
+* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag
+ * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag
+ * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag
+ * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag
+ * - \ref QEI_STATUS_IDXF_Msk : Index detected flag
+ * @retval 0 QEI specified interrupt flag is not set.
+ * @retval 1 QEI specified interrupt flag is set.
+ * @details This macro get QEI specified interrupt flag status.
+ * \hideinitializer
+ */
+#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0)
+
+
+/**
+ * @brief Clear QEI interrupt flag
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32IntSel Interrupt type selection.
+ * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag
+ * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag
+ * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag
+ * - \ref QEI_STATUS_IDXF_Msk : Index detected flag
+ * @return None
+ * @details This macro clear QEI specified interrupt flag.
+ * \hideinitializer
+ */
+#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel))
+
+/**
+ * @brief Set QEI counter compare value
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32Value The counter compare value.
+ * @return None
+ * @details This macro set QEI pulse counter compare value.
+ * \hideinitializer
+ */
+#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value))
+
+/**
+ * @brief Set QEI counter value
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32Value The counter compare value.
+ * @return None
+ * @details This macro set QEI pulse counter value.
+ * \hideinitializer
+ */
+#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value))
+
+/**
+ * @brief Enable QEI counter hold mode
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32Type The triggered type.
+ * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control
+ * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0
+ * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1
+ * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2
+ * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3
+ * @return None
+ * @details This macro enable QEI counter hold mode.
+ * \hideinitializer
+ */
+#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type))
+
+/**
+ * @brief Disable QEI counter hold mode
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32Type The triggered type.
+ * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control
+ * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0
+ * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1
+ * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2
+ * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3
+ * @return None
+ * @details This macro disable QEI counter hold mode.
+ * \hideinitializer
+ */
+#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type))
+
+/**
+ * @brief Set QEI maximum count value
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32Value The counter maximum value.
+ * @return QEI maximum count value
+ * @details This macro set QEI maximum count value.
+ * \hideinitializer
+ */
+#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value))
+
+/**
+ * @brief Set QEI counting mode
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32Mode QEI counting mode.
+ * - \ref QEI_CTL_X4_FREE_COUNTING_MODE
+ * - \ref QEI_CTL_X2_FREE_COUNTING_MODE
+ * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE
+ * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE
+ * @return None
+ * @details This macro set QEI counting mode.
+ * \hideinitializer
+ */
+#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode))
+
+
+void QEI_Close(QEI_T* qei);
+void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel);
+void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel);
+void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value);
+void QEI_Start(QEI_T* qei);
+void QEI_Stop(QEI_T* qei);
+
+
+/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group QEI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_QEI_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h
new file mode 100644
index 00000000000..64114525e1e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h
@@ -0,0 +1,357 @@
+/**************************************************************************//**
+ * @file nu_qspi.h
+ * @version V3.00
+ * @brief M480 series QSPI driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_QSPI_H__
+#define __NU_QSPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup QSPI_Driver QSPI Driver
+ @{
+*/
+
+/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants
+ @{
+*/
+
+#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
+#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
+#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
+#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
+
+#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
+#define QSPI_MASTER (0x0U) /*!< Set as master \hideinitializer */
+
+#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
+#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
+#define QSPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */
+
+/* QSPI Interrupt Mask */
+#define QSPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */
+#define QSPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */
+#define QSPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
+#define QSPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */
+#define QSPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */
+#define QSPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */
+#define QSPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */
+#define QSPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */
+#define QSPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */
+#define QSPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */
+
+/* QSPI Status Mask */
+#define QSPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */
+#define QSPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */
+#define QSPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */
+#define QSPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */
+#define QSPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */
+#define QSPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */
+#define QSPI_QSPIEN_STS_MASK (0x40U) /*!< QSPIEN status mask \hideinitializer */
+#define QSPI_SSLINE_STS_MASK (0x80U) /*!< QSPIx_SS line status mask \hideinitializer */
+
+/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear the unit transfer interrupt flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag.
+ * \hideinitializer
+ */
+#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk)
+
+/**
+ * @brief Trigger RX PDMA function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function.
+ * \hideinitializer
+ */
+#define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk)
+
+/**
+ * @brief Trigger TX PDMA function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function.
+ * \hideinitializer
+ */
+#define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk)
+
+/**
+ * @brief Disable RX PDMA transfer.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function.
+ * \hideinitializer
+ */
+#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Disable TX PDMA transfer.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function.
+ * \hideinitializer
+ */
+#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+ * @brief Get the count of available data in RX FIFO.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return The count of available data in RX FIFO.
+ * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO.
+ * \hideinitializer
+ */
+#define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos)
+
+/**
+ * @brief Get the RX FIFO empty flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @retval 0 RX FIFO is not empty.
+ * @retval 1 RX FIFO is empty.
+ * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag.
+ * \hideinitializer
+ */
+#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos)
+
+/**
+ * @brief Get the TX FIFO empty flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @retval 0 TX FIFO is not empty.
+ * @retval 1 TX FIFO is empty.
+ * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag.
+ * \hideinitializer
+ */
+#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos)
+
+/**
+ * @brief Get the TX FIFO full flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @retval 0 TX FIFO is not full.
+ * @retval 1 TX FIFO is full.
+ * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag.
+ * \hideinitializer
+ */
+#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos)
+
+/**
+ * @brief Get the datum read from RX register.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return Data in RX register.
+ * @details Read QSPI_RX register to get the received datum.
+ * \hideinitializer
+ */
+#define QSPI_READ_RX(qspi) ((qspi)->RX)
+
+/**
+ * @brief Write datum to TX register.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus.
+ * @return None.
+ * @details Write u32TxData to QSPI_TX register.
+ * \hideinitializer
+ */
+#define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData))
+
+/**
+ * @brief Set QSPIx_SS pin to high state.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set QSPIx_SS pin to high state.
+ * \hideinitializer
+ */
+#define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))
+
+/**
+ * @brief Set QSPIx_SS pin to low state.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set QSPIx_SS pin to low state.
+ * \hideinitializer
+ */
+#define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk)
+
+/**
+ * @brief Enable Byte Reorder function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]).
+ * \hideinitializer
+ */
+#define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk)
+
+/**
+ * @brief Disable Byte Reorder function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function.
+ * \hideinitializer
+ */
+#define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk)
+
+/**
+ * @brief Set the length of suspend interval.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
+ * @return None.
+ * @details Set the length of suspend interval according to u32SuspCycle.
+ * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle).
+ * \hideinitializer
+ */
+#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos))
+
+/**
+ * @brief Set the QSPI transfer sequence with LSB first.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first.
+ * \hideinitializer
+ */
+#define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk)
+
+/**
+ * @brief Set the QSPI transfer sequence with MSB first.
+ * @param[in] qspi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first.
+ * \hideinitializer
+ */
+#define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk)
+
+/**
+ * @brief Set the data width of a QSPI transaction.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Width The bit width of one transaction.
+ * @return None.
+ * @details The data width can be 8 ~ 32 bits.
+ * \hideinitializer
+ */
+#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos))
+
+/**
+ * @brief Get the QSPI busy state.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @retval 0 QSPI controller is not busy.
+ * @retval 1 QSPI controller is busy.
+ * @details This macro will return the busy state of QSPI controller.
+ * \hideinitializer
+ */
+#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos )
+
+/**
+ * @brief Enable QSPI controller.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set QSPIEN (QSPI_CTL[0]) to enable QSPI controller.
+ * \hideinitializer
+ */
+#define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk)
+
+/**
+ * @brief Disable QSPI controller.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear QSPIEN (QSPI_CTL[0]) to disable QSPI controller.
+ * \hideinitializer
+ */
+#define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk)
+
+/**
+ * @brief Disable QSPI Dual IO function.
+ * @param[in] qspi is the base address of QSPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
+
+/**
+ * @brief Enable Dual IO function and set QSPI Dual IO direction to input.
+ * @param[in] qspi is the base address of QSPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk )
+
+/**
+ * @brief Enable Dual IO function and set QSPI Dual IO direction to output.
+ * @param[in] qspi is the base address of QSPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk )
+
+/**
+ * @brief Disable QSPI Dual IO function.
+ * @param[in] qspi is the base address of QSPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk )
+
+/**
+ * @brief Set QSPI Quad IO direction to input.
+ * @param[in] qspi is the base address of QSPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk )
+
+/**
+ * @brief Set QSPI Quad IO direction to output.
+ * @param[in] qspi is the base address of QSPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk )
+
+
+
+
+/* Function prototype declaration */
+uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void QSPI_Close(QSPI_T *qspi);
+void QSPI_ClearRxFIFO(QSPI_T *qspi);
+void QSPI_ClearTxFIFO(QSPI_T *qspi);
+void QSPI_DisableAutoSS(QSPI_T *qspi);
+void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock);
+void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+uint32_t QSPI_GetBusClock(QSPI_T *qspi);
+void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask);
+void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask);
+uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask);
+void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask);
+uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask);
+
+
+/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group QSPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_rtc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_rtc.h
new file mode 100644
index 00000000000..f416519b67d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_rtc.h
@@ -0,0 +1,342 @@
+/**************************************************************************//**
+ * @file nu_rtc.h
+ * @version V3.00
+ * @brief M480 series RTC driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_RTC_H__
+#define __NU_RTC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+ @{
+*/
+
+/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Initial Keyword Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */
+#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Time Attribute Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */
+#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */
+#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */
+#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Tick Period Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */
+#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */
+#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */
+#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */
+#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */
+#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */
+#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */
+#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Day of Week Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */
+#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */
+#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */
+#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */
+#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */
+#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */
+#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Miscellaneous Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_WAIT_COUNT 0xFFFFFFFFUL /*!< Initial Time-out Value \hideinitializer */
+#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */
+#define RTC_FCR_REFERENCE 32761UL /*!< RTC Reference for frequency compensation \hideinitializer */
+
+
+#define RTC_TAMPER0_SELECT (0x1ul << 0) /*!< Select Tamper 0 \hideinitializer */
+#define RTC_TAMPER1_SELECT (0x1ul << 1) /*!< Select Tamper 1 \hideinitializer */
+#define RTC_TAMPER2_SELECT (0x1ul << 2) /*!< Select Tamper 2 \hideinitializer */
+#define RTC_TAMPER3_SELECT (0x1ul << 3) /*!< Select Tamper 3 \hideinitializer */
+#define RTC_TAMPER4_SELECT (0x1ul << 4) /*!< Select Tamper 4 \hideinitializer */
+#define RTC_TAMPER5_SELECT (0x1ul << 5) /*!< Select Tamper 5 \hideinitializer */
+#define MAX_TAMPER_PIN_NUM 6ul /*!< Tamper Pin number \hideinitializer */
+
+#define RTC_TAMPER_HIGH_LEVEL_DETECT 1ul /*!< Tamper pin detect voltage level is high \hideinitializer */
+#define RTC_TAMPER_LOW_LEVEL_DETECT 0ul /*!< Tamper pin detect voltage level is low \hideinitializer */
+
+#define RTC_TAMPER_DEBOUNCE_ENABLE 1ul /*!< Enable RTC tamper pin de-bounce function \hideinitializer */
+#define RTC_TAMPER_DEBOUNCE_DISABLE 0ul /*!< Disable RTC tamper pin de-bounce function \hideinitializer */
+
+#define RTC_PAIR0_SELECT (0x1ul << 0) /*!< Select Pair 0 \hideinitializer */
+#define RTC_PAIR1_SELECT (0x1ul << 1) /*!< Select Pair 1 \hideinitializer */
+#define RTC_PAIR2_SELECT (0x1ul << 2) /*!< Select Pair 2 \hideinitializer */
+#define MAX_PAIR_NUM 3ul /*!< Pair number \hideinitializer */
+
+#define RTC_2POW10_CLK (0x0 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */
+#define RTC_2POW11_CLK (0x1 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */
+#define RTC_2POW12_CLK (0x2 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */
+#define RTC_2POW13_CLK (0x3 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */
+#define RTC_2POW14_CLK (0x4 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */
+#define RTC_2POW15_CLK (0x5 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */
+#define RTC_2POW16_CLK (0x6 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */
+#define RTC_2POW17_CLK (0x7 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */
+
+#define REF_RANDOM_PATTERN 0x0 /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */
+#define REF_PREVIOUS_PATTERN 0x1 /*!< The new reference pattern is repeated previous random value when the reference pattern run out \hideinitializer */
+#define REF_SEED 0x3 /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */
+
+/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs
+ @{
+*/
+/**
+ * @details RTC define Time Data Struct
+ */
+typedef struct
+{
+ uint32_t u32Year; /*!< Year value */
+ uint32_t u32Month; /*!< Month value */
+ uint32_t u32Day; /*!< Day value */
+ uint32_t u32DayOfWeek; /*!< Day of week value */
+ uint32_t u32Hour; /*!< Hour value */
+ uint32_t u32Minute; /*!< Minute value */
+ uint32_t u32Second; /*!< Second value */
+ uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
+ uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
+} S_RTC_TIME_DATA_T;
+
+/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */
+
+
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+ @{
+*/
+
+/**
+ * @brief Indicate is Leap Year or not
+ *
+ * @param None
+ *
+ * @retval 0 This year is not a leap year
+ * @retval 1 This year is a leap year
+ *
+ * @details According to current date, return this year is leap year or not.
+ * \hideinitializer
+ */
+#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
+
+/**
+ * @brief Clear RTC Alarm Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear RTC alarm interrupt flag.
+ * \hideinitializer
+ */
+#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk)
+
+/**
+ * @brief Clear RTC Tick Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear RTC tick interrupt flag.
+ * \hideinitializer
+ */
+#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk)
+
+/**
+ * @brief Clear RTC Tamper Interrupt Flag
+ *
+ * @param u32TamperFlag Tamper interrupt flag. It consists of: \n
+ * - \ref RTC_INTSTS_TAMP0IF_Msk \n
+ * - \ref RTC_INTSTS_TAMP1IF_Msk \n
+ * - \ref RTC_INTSTS_TAMP2IF_Msk \n
+ * - \ref RTC_INTSTS_TAMP3IF_Msk \n
+ * - \ref RTC_INTSTS_TAMP4IF_Msk \n
+ * - \ref RTC_INTSTS_TAMP5IF_Msk
+ *
+ * @return None
+ *
+ * @details This macro is used to clear RTC snooper pin interrupt flag.
+ * \hideinitializer
+ */
+#define RTC_CLEAR_TAMPER_INT_FLAG(u32TamperFlag) (RTC->INTSTS = (u32TamperFlag))
+
+/**
+ * @brief Get RTC Alarm Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 RTC alarm interrupt did not occur
+ * @retval 1 RTC alarm interrupt occurred
+ *
+ * @details This macro indicates RTC alarm interrupt occurred or not.
+ * \hideinitializer
+ */
+#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
+
+/**
+ * @brief Get RTC Time Tick Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 RTC time tick interrupt did not occur
+ * @retval 1 RTC time tick interrupt occurred
+ *
+ * @details This macro indicates RTC time tick interrupt occurred or not.
+ * \hideinitializer
+ */
+#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
+
+/**
+ * @brief Get RTC Tamper Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 RTC snooper pin interrupt did not occur
+ * @retval 1 RTC snooper pin interrupt occurred
+ *
+ * @details This macro indicates RTC snooper pin interrupt occurred or not.
+ * \hideinitializer
+ */
+#define RTC_GET_TAMPER_INT_FLAG() ((RTC->INTSTS & (0x3F00))? 1:0)
+
+/**
+ * @brief Get RTC TAMPER Interrupt Status
+ *
+ * @param None
+ *
+ * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated
+ * @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated
+ * @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated
+ * @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated
+ * @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated
+ * @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated
+ *
+ * @details This macro indicates RTC snooper pin interrupt occurred or not.
+ * \hideinitializer
+ */
+#define RTC_GET_TAMPER_INT_STATUS() ((RTC->INTSTS & (0x3F00)))
+
+/**
+ * @brief Read Spare Register
+ *
+ * @param[in] u32RegNum The spare register number, 0~19.
+ *
+ * @return Spare register content
+ *
+ * @details Read the specify spare register content.
+ * @note The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
+ * And its controlled by RTC Access Enable Register.
+ * \hideinitializer
+ */
+#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)])
+
+/**
+ * @brief Write Spare Register
+ *
+ * @param[in] u32RegNum The spare register number, 0~19.
+ * @param[in] u32RegValue The spare register value.
+ *
+ * @return None
+ *
+ * @details Write specify data to spare register.
+ * @note This macro is effect only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
+ * And its controlled by RTC Access Enable Register(RTC_RWEN).
+ * \hideinitializer
+ */
+#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue))
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void RTC_WaitAccessEnable(void);
+
+/**
+ * @brief Wait RTC Access Enable
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to enable the maximum RTC read/write accessible time.
+ */
+__STATIC_INLINE void RTC_WaitAccessEnable(void)
+{
+ while((RTC->RWEN & RTC_RWEN_RTCBUSY_Msk) == RTC_RWEN_RTCBUSY_Msk)
+ {
+ }
+
+ if(!(SYS->CSERVER & 0x1))
+ {
+ /* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */
+ RTC->RWEN = RTC_WRITE_KEY;
+ }
+
+ /* To wait RWENF bit is set and user can access the protected-register of RTC from now on */
+ while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == (uint32_t)0x0)
+ {
+ }
+}
+
+void RTC_Open(S_RTC_TIME_DATA_T *sPt);
+void RTC_Close(void);
+void RTC_32KCalibration(int32_t i32FrequencyX10000);
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk);
+void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk);
+uint32_t RTC_GetDayOfWeek(void);
+void RTC_SetTickPeriod(uint32_t u32TickSelection);
+void RTC_EnableInt(uint32_t u32IntFlagMask);
+void RTC_DisableInt(uint32_t u32IntFlagMask);
+void RTC_EnableSpareAccess(void);
+void RTC_DisableSpareRegister(void);
+void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn);
+void RTC_StaticTamperDisable(uint32_t u32TamperSelect);
+void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source);
+void RTC_DynamicTamperDisable(uint32_t u32PairSel);
+void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed);
+
+/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group RTC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_RTC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sc.h
new file mode 100644
index 00000000000..ac778b66442
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sc.h
@@ -0,0 +1,268 @@
+/**************************************************************************//**
+ * @file nu_sc.h
+ * @version V1.00
+ * @brief M480 Smartcard (SC) driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_SC_H__
+#define __NU_SC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SC_Driver SC Driver
+ @{
+*/
+
+/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants
+ @{
+*/
+#define SC_INTERFACE_NUM 3 /*!< Smartcard interface numbers \hideinitializer */
+#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high \hideinitializer */
+#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low \hideinitializer */
+#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status \hideinitializer */
+#define SC_CLK_ON 1 /*!< Smartcard clock on \hideinitializer */
+#define SC_CLK_OFF 0 /*!< Smartcard clock off \hideinitializer */
+
+#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask))
+
+/**
+ * @brief This macro disable smartcard interrupt
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32Mask Interrupt mask to be disabled. A combination of
+ * - \ref SC_INTEN_ACERRIEN_Msk
+ * - \ref SC_INTEN_RXTOIEN_Msk
+ * - \ref SC_INTEN_INITIEN_Msk
+ * - \ref SC_INTEN_CDIEN_Msk
+ * - \ref SC_INTEN_BGTIEN_Msk
+ * - \ref SC_INTEN_TMR2IEN_Msk
+ * - \ref SC_INTEN_TMR1IEN_Msk
+ * - \ref SC_INTEN_TMR0IEN_Msk
+ * - \ref SC_INTEN_TERRIEN_Msk
+ * - \ref SC_INTEN_TBEIEN_Msk
+ * - \ref SC_INTEN_RDAIEN_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
+
+/**
+ * @brief This macro set VCC pin state of smartcard interface
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
+ * @return None
+ * \hideinitializer
+ */
+#define SC_SET_VCC_PIN(sc, u32State) \
+ do {\
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+ if(u32State)\
+ (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\
+ else\
+ (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\
+ }while(0)
+
+
+/**
+ * @brief This macro turns CLK output on or off
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF
+ * @return None
+ * \hideinitializer
+ */
+#define SC_SET_CLK_PIN(sc, u32OnOff)\
+ do {\
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+ if(u32OnOff)\
+ (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\
+ else\
+ (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\
+ }while(0)
+
+/**
+ * @brief This macro set I/O pin state of smartcard interface
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
+ * @return None
+ * \hideinitializer
+ */
+#define SC_SET_IO_PIN(sc, u32State)\
+ do {\
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+ if(u32State)\
+ (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\
+ else\
+ (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\
+ }while(0)
+
+/**
+ * @brief This macro set RST pin state of smartcard interface
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
+ * @return None
+ * \hideinitializer
+ */
+#define SC_SET_RST_PIN(sc, u32State)\
+ do {\
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+ if(u32State)\
+ (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\
+ else\
+ (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\
+ }while(0)
+
+/**
+ * @brief This macro read one byte from smartcard module receive FIFO
+ * @param[in] sc Base address of smartcard module
+ * @return One byte read from receive FIFO
+ * \hideinitializer
+ */
+#define SC_READ(sc) ((char)((sc)->DAT))
+
+/**
+ * @brief This macro write one byte to smartcard module transmit FIFO
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u8Data Data to write to transmit FIFO
+ * @return None
+ * \hideinitializer
+ */
+#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
+
+/**
+ * @brief This macro set smartcard stop bit length
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32Len Stop bit length, ether 1 or 2.
+ * @return None
+ * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
+ * \hideinitializer
+ */
+#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1 ? SC_CTL_NSB_Msk : 0))
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count);
+__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count);
+
+/**
+ * @brief Enable/Disable Tx error retry, and set Tx error retry count
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry
+ * @return None
+ */
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
+{
+ while((sc)->CTL & SC_CTL_SYNC_Msk)
+ {
+ ;
+ }
+ /* Retry count must set while enable bit disabled, so disable it first */
+ (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);
+
+ if((u32Count) != 0UL)
+ {
+ while((sc)->CTL & SC_CTL_SYNC_Msk)
+ {
+ ;
+ }
+ (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;
+ }
+}
+
+/**
+ * @brief Enable/Disable Rx error retry, and set Rx error retry count
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry
+ * @return None
+ */
+__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
+{
+ while((sc)->CTL & SC_CTL_SYNC_Msk)
+ {
+ ;
+ }
+ /* Retry count must set while enable bit disabled, so disable it first */
+ (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);
+
+ if((u32Count) != 0UL)
+ {
+ while((sc)->CTL & SC_CTL_SYNC_Msk)
+ {
+ ;
+ }
+ (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;
+ }
+
+}
+
+
+uint32_t SC_IsCardInserted(SC_T *sc);
+void SC_ClearFIFO(SC_T *sc);
+void SC_Close(SC_T *sc);
+void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);
+void SC_ResetReader(SC_T *sc);
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
+void SC_StopAllTimer(SC_T *sc);
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
+uint32_t SC_GetInterfaceClock(SC_T *sc);
+
+
+/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_SC_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_scuart.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_scuart.h
new file mode 100644
index 00000000000..e5e9e7831ae
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_scuart.h
@@ -0,0 +1,267 @@
+/**************************************************************************//**
+ * @file nu_scuart.h
+ * @version V1.00
+ * @brief M480 Smartcard UART mode (SCUART) driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_SCUART_H__
+#define __NU_SCUART_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SCUART_Driver SCUART Driver
+ @{
+*/
+
+/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
+ @{
+*/
+#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */
+#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */
+#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */
+#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */
+
+#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */
+#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */
+#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */
+
+#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */
+#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */
+
+
+/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+ @{
+*/
+
+/* TX Macros */
+/**
+ * @brief Write Data to Tx data register
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] u8Data Data byte to transmit
+ * @return None
+ * \hideinitializer
+ */
+#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
+
+/**
+ * @brief Get TX FIFO empty flag status from register
+ * @param[in] sc The base address of smartcard module
+ * @return Transmit FIFO empty status
+ * @retval 0 Transmit FIFO is not empty
+ * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty
+ * \hideinitializer
+ */
+#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
+
+/**
+ * @brief Get TX FIFO full flag status from register
+ * @param[in] sc The base address of smartcard module
+ * @return Transmit FIFO full status
+ * @retval 0 Transmit FIFO is not full
+ * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full
+ * \hideinitializer
+ */
+#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
+
+/**
+ * @brief Wait specified smartcard port transmission complete
+ * @param[in] sc The base address of smartcard module
+ * @return None
+ * @note This Macro blocks until transmit complete.
+ * \hideinitializer
+ */
+#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)
+
+/**
+ * @brief Check specified smartcard port transmit FIFO is full or not
+ * @param[in] sc The base address of smartcard module
+ * @return Transmit FIFO full status
+ * @retval 0 Transmit FIFO is not full
+ * @retval 1 Transmit FIFO is full
+ * \hideinitializer
+ */
+#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0)
+
+/**
+ * @brief Check specified smartcard port transmission is over
+ * @param[in] sc The base address of smartcard module
+ * @return Transmit complete status
+ * @retval 0 Transmit is not complete
+ * @retval 1 Transmit complete
+ * \hideinitializer
+ */
+#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1)
+
+/**
+ * @brief Check specified Smartcard port Transmission Status
+ * @param[in] sc The pointer of smartcard module.
+ * @retval 0 Transmit is completed
+ * @retval 1 Transmit is active
+ * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted.
+ * \hideinitializer
+ */
+#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0)
+
+/* RX Macros */
+
+/**
+ * @brief Read Rx data register
+ * @param[in] sc The base address of smartcard module
+ * @return The oldest data byte in RX FIFO
+ * \hideinitializer
+ */
+#define SCUART_READ(sc) ((sc)->DAT)
+
+/**
+ * @brief Get RX FIFO empty flag status from register
+ * @param[in] sc The base address of smartcard module
+ * @return Receive FIFO empty status
+ * @retval 0 Receive FIFO is not empty
+ * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty
+ * \hideinitializer
+ */
+#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
+
+
+/**
+ * @brief Get RX FIFO full flag status from register
+ * @param[in] sc The base address of smartcard module
+ * @return Receive FIFO full status
+ * @retval 0 Receive FIFO is not full
+ * @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full
+ * \hideinitializer
+ */
+#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
+
+/**
+ * @brief Check if receive data number in FIFO reach FIFO trigger level or not
+ * @param[in] sc The base address of smartcard module
+ * @return Receive FIFO data status
+ * @retval 0 The number of bytes in receive FIFO is less than trigger level
+ * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level
+ * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO
+ * \hideinitializer
+ */
+#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0)
+
+/**
+ * @brief Check specified smartcard port receive FIFO is full or not
+ * @param[in] sc The base address of smartcard module
+ * @return Receive FIFO full status
+ * @retval 0 Receive FIFO is not full
+ * @retval 1 Receive FIFO is full
+ * \hideinitializer
+ */
+#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0)
+
+/* Interrupt Macros */
+
+/**
+ * @brief Enable specified interrupts
+ * @param[in] sc The base address of smartcard module
+ * @param[in] u32Mask Interrupt masks to enable, a combination of following bits
+ * - \ref SC_INTEN_RXTOIEN_Msk
+ * - \ref SC_INTEN_TERRIEN_Msk
+ * - \ref SC_INTEN_TBEIEN_Msk
+ * - \ref SC_INTEN_RDAIEN_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
+
+/**
+ * @brief Disable specified interrupts
+ * @param[in] sc The base address of smartcard module
+ * @param[in] u32Mask Interrupt masks to disable, a combination of following bits
+ * - \ref SC_INTEN_RXTOIEN_Msk
+ * - \ref SC_INTEN_TERRIEN_Msk
+ * - \ref SC_INTEN_TBEIEN_Msk
+ * - \ref SC_INTEN_RDAIEN_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
+
+/**
+ * @brief Get specified interrupt flag/status
+ * @param[in] sc The base address of smartcard module
+ * @param[in] u32Type Interrupt flag/status to check, could be one of following value
+ * - \ref SC_INTSTS_RXTOIF_Msk
+ * - \ref SC_INTSTS_TERRIF_Msk
+ * - \ref SC_INTSTS_TBEIF_Msk
+ * - \ref SC_INTSTS_RDAIF_Msk
+ * @return The status of specified interrupt
+ * @retval 0 Specified interrupt does not happened
+ * @retval 1 Specified interrupt happened
+ * \hideinitializer
+ */
+#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & (u32Type) ? 1 : 0)
+
+/**
+ * @brief Clear specified interrupt flag/status
+ * @param[in] sc The base address of smartcard module
+ * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values
+ * - \ref SC_INTSTS_RXTOIF_Msk
+ * - \ref SC_INTSTS_TERRIF_Msk
+ * - \ref SC_INTSTS_TBEIF_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type))
+
+/**
+ * @brief Get receive error flag/status
+ * @param[in] sc The base address of smartcard module
+ * @return Current receive error status, could one of following errors:
+ * @retval SC_STATUS_PEF_Msk Parity error
+ * @retval SC_STATUS_FEF_Msk Frame error
+ * @retval SC_STATUS_BEF_Msk Break error
+ * \hideinitializer
+ */
+#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
+
+/**
+ * @brief Clear specified receive error flag/status
+ * @param[in] sc The base address of smartcard module
+ * @param[in] u32Mask Receive error flag/status to clear, combination following values
+ * - \ref SC_STATUS_PEF_Msk
+ * - \ref SC_STATUS_FEF_Msk
+ * - \ref SC_STATUS_BEF_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask))
+
+void SCUART_Close(SC_T* sc);
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate);
+uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
+void SCUART_Write(SC_T* sc,uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
+
+/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SCUART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_SCUART_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sdh.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sdh.h
new file mode 100644
index 00000000000..41d1d199f59
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sdh.h
@@ -0,0 +1,203 @@
+/**************************************************************************//**
+ * @file nu_sdh.h
+ * @version V1.00
+ * @brief M480 SDH driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include
+
+#ifndef __NU_SDH_H__
+#define __NU_SDH_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SDH_Driver SDH Driver
+ @{
+*/
+
+
+/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants
+ @{
+*/
+
+#define SDH_ERR_ID 0xFFFF0100ul /*!< SDH error ID \hideinitializer */
+
+#define SDH_TIMEOUT (SDH_ERR_ID|0x01ul) /*!< Timeout \hideinitializer */
+#define SDH_NO_MEMORY (SDH_ERR_ID|0x02ul) /*!< OOM \hideinitializer */
+
+/*-- function return value */
+#define Successful 0ul /*!< Success \hideinitializer */
+#define Fail 1ul /*!< Failed \hideinitializer */
+
+/*--- define type of SD card or MMC */
+#define SDH_TYPE_UNKNOWN 0ul /*!< Unknown card type \hideinitializer */
+#define SDH_TYPE_SD_HIGH 1ul /*!< SDHC card \hideinitializer */
+#define SDH_TYPE_SD_LOW 2ul /*!< SD card \hideinitializer */
+#define SDH_TYPE_MMC 3ul /*!< MMC card \hideinitializer */
+#define SDH_TYPE_EMMC 4ul /*!< eMMC card \hideinitializer */
+
+/* SD error */
+#define SDH_NO_SD_CARD (SDH_ERR_ID|0x10ul) /*!< Card removed \hideinitializer */
+#define SDH_ERR_DEVICE (SDH_ERR_ID|0x11ul) /*!< Device error \hideinitializer */
+#define SDH_INIT_TIMEOUT (SDH_ERR_ID|0x12ul) /*!< Card init timeout \hideinitializer */
+#define SDH_SELECT_ERROR (SDH_ERR_ID|0x13ul) /*!< Card select error \hideinitializer */
+#define SDH_WRITE_PROTECT (SDH_ERR_ID|0x14ul) /*!< Card write protect \hideinitializer */
+#define SDH_INIT_ERROR (SDH_ERR_ID|0x15ul) /*!< Card init error \hideinitializer */
+#define SDH_CRC7_ERROR (SDH_ERR_ID|0x16ul) /*!< CRC 7 error \hideinitializer */
+#define SDH_CRC16_ERROR (SDH_ERR_ID|0x17ul) /*!< CRC 16 error \hideinitializer */
+#define SDH_CRC_ERROR (SDH_ERR_ID|0x18ul) /*!< CRC error \hideinitializer */
+#define SDH_CMD8_ERROR (SDH_ERR_ID|0x19ul) /*!< Command 8 error \hideinitializer */
+
+#define MMC_FREQ 20000ul /*!< output 20MHz to MMC \hideinitializer */
+#define SD_FREQ 25000ul /*!< output 25MHz to SD \hideinitializer */
+#define SDHC_FREQ 50000ul /*!< output 50MHz to SDH \hideinitializer */
+
+#define SD_PORT0 (1 << 0) /*!< Card select SD0 \hideinitializer */
+#define SD_PORT1 (1 << 2) /*!< Card select SD1 \hideinitializer */
+#define CardDetect_From_GPIO (1ul << 8) /*!< Card detection pin is GPIO \hideinitializer */
+#define CardDetect_From_DAT3 (1ul << 9) /*!< Card detection pin is DAT3 \hideinitializer */
+
+/*@}*/ /* end of group SDH_EXPORTED_CONSTANTS */
+
+/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines
+ @{
+*/
+typedef struct SDH_info_t
+{
+ unsigned char IsCardInsert; /*!< Card insert state */
+ unsigned char R3Flag;
+ unsigned char R7Flag;
+ unsigned char volatile DataReadyFlag;
+ unsigned int CardType; /*!< SDHC, SD, or MMC */
+ unsigned int RCA; /*!< Relative card address */
+ unsigned int totalSectorN; /*!< Total sector number */
+ unsigned int diskSize; /*!< Disk size in K bytes */
+ int sectorSize; /*!< Sector size in bytes */
+ unsigned char *dmabuf;
+} SDH_INFO_T; /*!< Structure holds SD card info */
+
+/*@}*/ /* end of group SDH_EXPORTED_TYPEDEF */
+
+/** @cond HIDDEN_SYMBOLS */
+extern SDH_INFO_T SD0, SD1;
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions
+ @{
+*/
+
+/**
+ * @brief Enable specified interrupt.
+ *
+ * @param[in] sdh Select SDH0 or SDH1.
+ * @param[in] u32IntMask Interrupt type mask:
+ * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /
+ * \ref SDH_INTEN_CDSRC_Msk \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
+ * \ref SDH_INTEN_WKIEN_Msk
+ *
+ * @return None.
+ * \hideinitializer
+ */
+#define SDH_ENABLE_INT(sdh, u32IntMask) ((sdh)->INTEN |= (u32IntMask))
+
+/**
+ * @brief Disable specified interrupt.
+ *
+ * @param[in] sdh Select SDH0 or SDH1.
+ * @param[in] u32IntMask Interrupt type mask:
+ * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /
+ * \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk /
+ *
+ * @return None.
+ * \hideinitializer
+ */
+#define SDH_DISABLE_INT(sdh, u32IntMask) ((sdh)->INTEN &= ~(u32IntMask))
+
+/**
+ * @brief Get specified interrupt flag/status.
+ *
+ * @param[in] sdh Select SDH0 or SDH1.
+ * @param[in] u32IntMask Interrupt type mask:
+ * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk /
+ * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk /
+ * \ref SDH_INTSTS_CDIF_Msk \ref SDH_INTSTS_RTOIF_Msk /
+ * \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk /
+ * \ref SDH_INTSTS_DAT1STS_Msk
+ *
+ *
+ * @return 0 = The specified interrupt is not happened.
+ * 1 = The specified interrupt is happened.
+ * \hideinitializer
+ */
+#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0)
+
+
+/**
+ * @brief Clear specified interrupt flag/status.
+ *
+ * @param[in] sdh Select SDH0 or SDH1.
+ * @param[in] u32IntMask Interrupt type mask:
+ * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk /
+ * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk
+ *
+ *
+ * @return None.
+ * \hideinitializer
+ */
+#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask))
+
+
+/**
+ * @brief Check SD Card inserted or removed.
+ *
+ * @param[in] sdh Select SDH0 or SDH1.
+ *
+ * @return 1: Card inserted.
+ * 0: Card removed.
+ * \hideinitializer
+ */
+#define SDH_IS_CARD_PRESENT(sdh) (((sdh) == SDH0)? SD0.IsCardInsert : SD1.IsCardInsert)
+
+/**
+ * @brief Get SD Card capacity.
+ *
+ * @param[in] sdh Select SDH0 or SDH1.
+ *
+ * @return SD Card capacity. (unit: KByte)
+ * \hideinitializer
+ */
+#define SDH_GET_CARD_CAPACITY(sdh) (((sdh) == SDH0)? SD0.diskSize : SD1.diskSize)
+
+
+void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc);
+uint32_t SDH_Probe(SDH_T *sdh);
+uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
+uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
+
+uint32_t SDH_CardDetection(SDH_T *sdh);
+void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc);
+void SDH_Close_Disk(SDH_T *sdh);
+
+
+/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SDH_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_SDH_H__ */
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h
new file mode 100644
index 00000000000..77eeda3b96c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h
@@ -0,0 +1,584 @@
+/**************************************************************************//**
+ * @file nu_spi.h
+ * @version V3.00
+ * @brief M480 series SPI driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_SPI_H__
+#define __NU_SPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SPI_Driver SPI Driver
+ @{
+*/
+
+/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
+ @{
+*/
+
+#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
+#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
+#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
+#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
+
+#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
+#define SPI_MASTER (0x0U) /*!< Set as master \hideinitializer */
+
+#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
+#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
+#define SPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */
+
+/* SPI Interrupt Mask */
+#define SPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */
+#define SPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */
+#define SPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
+#define SPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */
+#define SPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */
+#define SPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */
+#define SPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */
+#define SPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */
+#define SPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */
+#define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */
+
+/* SPI Status Mask */
+#define SPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */
+#define SPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */
+#define SPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */
+#define SPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */
+#define SPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */
+#define SPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */
+#define SPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */
+#define SPI_SSLINE_STS_MASK (0x80U) /*!< SPIx_SS line status mask \hideinitializer */
+
+
+/* I2S Data Width */
+#define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
+#define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
+#define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
+#define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
+
+/* I2S Audio Format */
+#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */
+#define SPII2S_STEREO (0U) /*!< Stereo channel \hideinitializer */
+
+/* I2S Data Format */
+#define SPII2S_FORMAT_I2S (0U<STATUS = SPI_STATUS_UNITIF_Msk)
+
+/**
+ * @brief Trigger RX PDMA function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
+ * \hideinitializer
+ */
+#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
+
+/**
+ * @brief Trigger TX PDMA function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
+ * \hideinitializer
+ */
+#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
+
+/**
+ * @brief Disable RX PDMA transfer.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
+ * \hideinitializer
+ */
+#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Disable TX PDMA transfer.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
+ * \hideinitializer
+ */
+#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+ * @brief Get the count of available data in RX FIFO.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return The count of available data in RX FIFO.
+ * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
+ * \hideinitializer
+ */
+#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
+
+/**
+ * @brief Get the RX FIFO empty flag.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @retval 0 RX FIFO is not empty.
+ * @retval 1 RX FIFO is empty.
+ * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
+ * \hideinitializer
+ */
+#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
+
+/**
+ * @brief Get the TX FIFO empty flag.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @retval 0 TX FIFO is not empty.
+ * @retval 1 TX FIFO is empty.
+ * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
+ * \hideinitializer
+ */
+#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
+
+/**
+ * @brief Get the TX FIFO full flag.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @retval 0 TX FIFO is not full.
+ * @retval 1 TX FIFO is full.
+ * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
+ * \hideinitializer
+ */
+#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
+
+/**
+ * @brief Get the datum read from RX register.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return Data in RX register.
+ * @details Read SPI_RX register to get the received datum.
+ * \hideinitializer
+ */
+#define SPI_READ_RX(spi) ((spi)->RX)
+
+/**
+ * @brief Write datum to TX register.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
+ * @return None.
+ * @details Write u32TxData to SPI_TX register.
+ * \hideinitializer
+ */
+#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
+
+/**
+ * @brief Set SPIx_SS pin to high state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set SPIx_SS pin to high state.
+ * \hideinitializer
+ */
+#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
+
+/**
+ * @brief Set SPIx_SS pin to low state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set SPIx_SS pin to low state.
+ * \hideinitializer
+ */
+#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
+
+/**
+ * @brief Enable Byte Reorder function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
+ * \hideinitializer
+ */
+#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
+
+/**
+ * @brief Disable Byte Reorder function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
+ * \hideinitializer
+ */
+#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
+
+/**
+ * @brief Set the length of suspend interval.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
+ * @return None.
+ * @details Set the length of suspend interval according to u32SuspCycle.
+ * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
+ * \hideinitializer
+ */
+#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
+
+/**
+ * @brief Set the SPI transfer sequence with LSB first.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
+ * \hideinitializer
+ */
+#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
+
+/**
+ * @brief Set the SPI transfer sequence with MSB first.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
+ * \hideinitializer
+ */
+#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
+
+/**
+ * @brief Set the data width of a SPI transaction.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Width The bit width of one transaction.
+ * @return None.
+ * @details The data width can be 8 ~ 32 bits.
+ * \hideinitializer
+ */
+#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
+
+/**
+ * @brief Get the SPI busy state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @retval 0 SPI controller is not busy.
+ * @retval 1 SPI controller is busy.
+ * @details This macro will return the busy state of SPI controller.
+ * \hideinitializer
+ */
+#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
+
+/**
+ * @brief Enable SPI controller.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
+ * \hideinitializer
+ */
+#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
+
+/**
+ * @brief Disable SPI controller.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
+ * \hideinitializer
+ */
+#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
+__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
+__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);
+
+/**
+ * @brief Enable zero cross detection function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32ChMask The mask for left or right channel. Valid values are:
+ * - \ref SPII2S_RIGHT
+ * - \ref SPII2S_LEFT
+ * @return None
+ * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
+ */
+__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
+{
+ if(u32ChMask == SPII2S_RIGHT)
+ {
+ i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
+ }
+ else
+ {
+ i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
+ }
+}
+
+/**
+ * @brief Disable zero cross detection function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32ChMask The mask for left or right channel. Valid values are:
+ * - \ref SPII2S_RIGHT
+ * - \ref SPII2S_LEFT
+ * @return None
+ * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
+ */
+__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
+{
+ if(u32ChMask == SPII2S_RIGHT)
+ {
+ i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
+ }
+ else
+ {
+ i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
+ }
+}
+
+/**
+ * @brief Enable I2S TX DMA function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
+ * \hideinitializer
+ */
+#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+ * @brief Disable I2S TX DMA function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
+ * \hideinitializer
+ */
+#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+ * @brief Enable I2S RX DMA function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
+ * \hideinitializer
+ */
+#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Disable I2S RX DMA function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
+ * \hideinitializer
+ */
+#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Enable I2S TX function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
+ * \hideinitializer
+ */
+#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
+
+/**
+ * @brief Disable I2S TX function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
+ * \hideinitializer
+ */
+#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
+
+/**
+ * @brief Enable I2S RX function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
+ * \hideinitializer
+ */
+#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
+
+/**
+ * @brief Disable I2S RX function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
+ * \hideinitializer
+ */
+#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
+
+/**
+ * @brief Enable TX Mute function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
+ * \hideinitializer
+ */
+#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
+
+/**
+ * @brief Disable TX Mute function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
+ * \hideinitializer
+ */
+#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
+
+/**
+ * @brief Clear TX FIFO.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
+ * \hideinitializer
+ */
+#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
+
+/**
+ * @brief Clear RX FIFO.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
+ * \hideinitializer
+ */
+#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
+
+/**
+ * @brief This function sets the recording source channel when mono mode is used.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Ch left or right channel. Valid values are:
+ * - \ref SPII2S_MONO_LEFT
+ * - \ref SPII2S_MONO_RIGHT
+ * @return None
+ * @details This function selects the recording source channel of monaural mode.
+ * \hideinitializer
+ */
+__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
+{
+ u32Ch == SPII2S_MONO_LEFT ?
+ (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
+ (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
+}
+
+/**
+ * @brief Write data to I2S TX FIFO.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Data The value written to TX FIFO.
+ * @return None
+ * @details This macro will write a value to TX FIFO.
+ * \hideinitializer
+ */
+#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
+
+/**
+ * @brief Read RX FIFO.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return The value read from RX FIFO.
+ * @details This function will return a value read from RX FIFO.
+ * \hideinitializer
+ */
+#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
+
+/**
+ * @brief Get the interrupt flag.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Mask The mask value for all interrupt flags.
+ * @return The interrupt flags specified by the u32mask parameter.
+ * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
+ * \hideinitializer
+ */
+#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
+
+/**
+ * @brief Clear the interrupt flag.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Mask The mask value for all interrupt flags.
+ * @return None
+ * @details This macro will clear the interrupt flags specified by the u32mask parameter.
+ * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
+ * \hideinitializer
+ */
+#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
+
+/**
+ * @brief Get transmit FIFO level
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return TX FIFO level
+ * @details This macro will return the number of available words in TX FIFO.
+ * \hideinitializer
+ */
+#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
+
+/**
+ * @brief Get receive FIFO level
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return RX FIFO level
+ * @details This macro will return the number of available words in RX FIFO.
+ * \hideinitializer
+ */
+#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
+
+
+
+/* Function prototype declaration */
+uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void SPI_Close(SPI_T *spi);
+void SPI_ClearRxFIFO(SPI_T *spi);
+void SPI_ClearTxFIFO(SPI_T *spi);
+void SPI_DisableAutoSS(SPI_T *spi);
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+uint32_t SPI_GetBusClock(SPI_T *spi);
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
+
+uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
+void SPII2S_Close(SPI_T *i2s);
+void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
+void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
+uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
+void SPII2S_DisableMCLK(SPI_T *i2s);
+void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+
+
+/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spim.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spim.h
new file mode 100644
index 00000000000..84a0d98ffba
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spim.h
@@ -0,0 +1,634 @@
+/**************************************************************************//**
+ * @file nu_spim.h
+ * @version V1.00
+ * @brief M480 series SPIM driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_SPIM_H__
+#define __NU_SPIM_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SPIM_Driver SPIM Driver
+ @{
+*/
+
+
+/** @addtogroup SPIM_EXPORTED_CONSTANTS SPIM Exported Constants
+ @{
+*/
+
+#define SPIM_DMM_MAP_ADDR 0x8000000UL /*!< DMM mode memory map base address \hideinitializer */
+#define SPIM_DMM_SIZE 0x2000000UL /*!< DMM mode memory mapping size \hideinitializer */
+#define SPIM_CCM_ADDR 0x20020000UL /*!< CCM mode memory map base address \hideinitializer */
+#define SPIM_CCM_SIZE 0x8000UL /*!< CCM mode memory size \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* SPIM_CTL0 constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SPIM_CTL0_RW_IN(x) ((x) ? 0UL : (0x1UL << SPIM_CTL0_QDIODIR_Pos)) /*!< SPIM_CTL0: SPI Interface Direction Select \hideinitializer */
+#define SPIM_CTL0_BITMODE_SING (0UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: One bit mode (SPI Interface including DO, DI, HOLD, WP) \hideinitializer */
+#define SPIM_CTL0_BITMODE_DUAL (1UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Two bits mode (SPI Interface including D0, D1, HOLD, WP) \hideinitializer */
+#define SPIM_CTL0_BITMODE_QUAD (2UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Four bits mode (SPI Interface including D0, D1, D2, D3) \hideinitializer */
+#define SPIM_CTL0_OPMODE_IO (0UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: I/O Mode \hideinitializer */
+#define SPIM_CTL0_OPMODE_PAGEWRITE (1UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Write Mode \hideinitializer */
+#define SPIM_CTL0_OPMODE_PAGEREAD (2UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Read Mode \hideinitializer */
+#define SPIM_CTL0_OPMODE_DIRECTMAP (3UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Direct Map Mode \hideinitializer */
+
+#define CMD_NORMAL_PAGE_PROGRAM (0x02UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */
+#define CMD_NORMAL_PAGE_PROGRAM_4B (0x12UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */
+#define CMD_QUAD_PAGE_PROGRAM_WINBOND (0x32UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for Winbond) (Page Write Mode Use) \hideinitializer */
+#define CMD_QUAD_PAGE_PROGRAM_MXIC (0x38UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for MXIC) (Page Write Mode Use) \hideinitializer */
+#define CMD_QUAD_PAGE_PROGRAM_EON (0x40UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page Program (for EON) (Page Write Mode Use) \hideinitializer */
+
+#define CMD_DMA_NORMAL_READ (0x03UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Read Data (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_FAST_READ (0x0BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_NORMAL_DUAL_READ (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_FAST_READ_DUAL_OUTPUT (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_FAST_READ_QUAD_OUTPUT (0x6BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_FAST_DUAL_READ (0xBBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_NORMAL_QUAD_READ (0xE7UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_FAST_QUAD_READ (0xEBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */
+
+/** @cond HIDDEN_SYMBOLS */
+
+typedef enum
+{
+ MFGID_UNKNOW = 0x00U,
+ MFGID_SPANSION = 0x01U,
+ MFGID_EON = 0x1CU,
+ MFGID_ISSI = 0x7FU,
+ MFGID_MXIC = 0xC2U,
+ MFGID_WINBOND = 0xEFU
+}
+E_MFGID;
+
+/* Flash opcodes. */
+#define OPCODE_WREN 0x06U /* Write enable */
+#define OPCODE_RDSR 0x05U /* Read status register #1*/
+#define OPCODE_WRSR 0x01U /* Write status register #1 */
+#define OPCODE_RDSR2 0x35U /* Read status register #2*/
+#define OPCODE_WRSR2 0x31U /* Write status register #2 */
+#define OPCODE_RDSR3 0x15U /* Read status register #3*/
+#define OPCODE_WRSR3 0x11U /* Write status register #3 */
+#define OPCODE_PP 0x02U /* Page program (up to 256 bytes) */
+#define OPCODE_SE_4K 0x20U /* Erase 4KB sector */
+#define OPCODE_BE_32K 0x52U /* Erase 32KB block */
+#define OPCODE_CHIP_ERASE 0xc7U /* Erase whole flash chip */
+#define OPCODE_BE_64K 0xd8U /* Erase 64KB block */
+#define OPCODE_READ_ID 0x90U /* Read ID */
+#define OPCODE_RDID 0x9fU /* Read JEDEC ID */
+#define OPCODE_BRRD 0x16U /* SPANSION flash - Bank Register Read command */
+#define OPCODE_BRWR 0x17U /* SPANSION flash - Bank Register write command */
+#define OPCODE_NORM_READ 0x03U /* Read data bytes */
+#define OPCODE_FAST_READ 0x0bU /* Read data bytes */
+#define OPCODE_FAST_DUAL_READ 0x3bU /* Read data bytes */
+#define OPCODE_FAST_QUAD_READ 0x6bU /* Read data bytes */
+
+/* Used for SST flashes only. */
+#define OPCODE_BP 0x02U /* Byte program */
+#define OPCODE_WRDI 0x04U /* Write disable */
+#define OPCODE_AAI_WP 0xadU /* Auto u32Address increment word program */
+
+/* Used for Macronix flashes only. */
+#define OPCODE_EN4B 0xb7U /* Enter 4-byte mode */
+#define OPCODE_EX4B 0xe9U /* Exit 4-byte mode */
+
+#define OPCODE_RDSCUR 0x2bU
+#define OPCODE_WRSCUR 0x2fU
+
+#define OPCODE_RSTEN 0x66U
+#define OPCODE_RST 0x99U
+
+#define OPCODE_ENQPI 0x38U
+#define OPCODE_EXQPI 0xFFU
+
+/* Status Register bits. */
+#define SR_WIP 0x1U /* Write in progress */
+#define SR_WEL 0x2U /* Write enable latch */
+#define SR_QE 0x40U /* Quad Enable for MXIC */
+/* Status Register #2 bits. */
+#define SR2_QE 0x2U /* Quad Enable for Winbond */
+/* meaning of other SR_* bits may differ between vendors */
+#define SR_BP0 0x4U /* Block protect 0 */
+#define SR_BP1 0x8U /* Block protect 1 */
+#define SR_BP2 0x10U /* Block protect 2 */
+#define SR_SRWD 0x80U /* SR write protect */
+#define SR3_ADR 0x01U /* 4-byte u32Address mode */
+
+#define SCUR_4BYTE 0x04U /* 4-byte u32Address mode */
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/*@}*/ /* end of group SPIM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Macros and functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/**
+ * @details Enable cipher.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk)
+
+/**
+ * @details Disable cipher.
+ * \hideinitializer
+ */
+#define SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk)
+
+/**
+ * @details Enable cipher balance
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk)
+
+/**
+ * @details Disable cipher balance
+ * \hideinitializer
+ */
+#define SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk)
+
+/**
+ * @details Set 4-byte address to be enabled/disabled.
+ * \hideinitializer
+ */
+#define SPIM_SET_4BYTE_ADDR_EN(x) \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \
+ } while (0)
+
+/**
+ * @details Enable SPIM interrupt
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk)
+
+/**
+ * @details Disable SPIM interrupt
+ * \hideinitializer
+ */
+#define SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk)
+
+/**
+ * @details Is interrupt flag on.
+ * \hideinitializer
+ */
+#define SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL)
+
+/**
+ * @details Clear interrupt flag.
+ * \hideinitializer
+ */
+#define SPIM_CLR_INT() \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos); \
+ } while (0)
+
+/**
+ * @details Set transmit/receive bit length
+ * \hideinitializer
+ */
+#define SPIM_SET_DATA_WIDTH(x) \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos); \
+ } while (0)
+
+/**
+ * @details Get data transmit/receive bit length setting
+ * \hideinitializer
+ */
+#define SPIM_GET_DATA_WIDTH() \
+ (((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U)
+
+/**
+ * @details Set data transmit/receive burst number
+ * \hideinitializer
+ */
+#define SPIM_SET_DATA_NUM(x) \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos); \
+ } while (0)
+
+/**
+ * @details Get data transmit/receive burst number
+ * \hideinitializer
+ */
+#define SPIM_GET_DATA_NUM() \
+ (((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U)
+
+/**
+ * @details Enable Single Input mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_SING_INPUT_MODE() \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1)); \
+ } while (0)
+
+/**
+ * @details Enable Single Output mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_SING_OUTPUT_MODE() \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0)); \
+ } while (0)
+
+/**
+ * @details Enable Dual Input mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_DUAL_INPUT_MODE() \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U)); \
+ } while (0)
+
+/**
+ * @details Enable Dual Output mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_DUAL_OUTPUT_MODE() \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U)); \
+ } while (0)
+
+/**
+ * @details Enable Quad Input mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_QUAD_INPUT_MODE() \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U)); \
+ } while (0)
+
+/**
+ * @details Enable Quad Output mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_QUAD_OUTPUT_MODE() \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U)); \
+ } while (0)
+
+/**
+ * @details Set suspend interval which ranges between 0 and 15.
+ * \hideinitializer
+ */
+#define SPIM_SET_SUSP_INTVL(x) \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos); \
+ } while (0)
+
+/**
+ * @details Get suspend interval setting
+ * \hideinitializer
+ */
+#define SPIM_GET_SUSP_INTVL() \
+ ((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos)
+
+/**
+ * @details Set operation mode.
+ * \hideinitializer
+ */
+#define SPIM_SET_OPMODE(x) \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \
+ } while (0)
+
+/**
+ * @details Get operation mode.
+ * \hideinitializer
+ */
+#define SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk)
+
+/**
+ * @details Set SPIM mode.
+ * \hideinitializer
+ */
+#define SPIM_SET_SPIM_MODE(x) \
+ do { \
+ SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x); \
+ } while (0)
+
+/**
+ * @details Get SPIM mode.
+ * \hideinitializer
+ */
+#define SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk)
+
+/**
+ * @details Start operation.
+ * \hideinitializer
+ */
+#define SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk)
+
+/**
+ * @details Is engine busy.
+ * \hideinitializer
+ */
+#define SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk)
+
+/**
+ * @details Wait for free.
+ * \hideinitializer
+ */
+#define SPIM_WAIT_FREE() \
+ do { \
+ while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) { } \
+ } while (0)
+
+/**
+ * @details Enable cache.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk)
+
+/**
+ * @details Disable cache.
+ * \hideinitializer
+ */
+#define SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk)
+
+/**
+ * @details Is cache enabled.
+ * \hideinitializer
+ */
+#define SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1)
+
+/**
+ * @details Enable CCM
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk)
+
+/**
+ * @details Disable CCM.
+ * \hideinitializer
+ */
+#define SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk)
+
+/**
+ * @details Is CCM enabled.
+ * \hideinitializer
+ */
+#define SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos)
+
+/**
+ * @details Invalidate cache.
+ * \hideinitializer
+ */
+#define SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk)
+
+/**
+ * @details Set SS(Select Active) to active level.
+ * \hideinitializer
+ */
+#define SPIM_SET_SS_EN(x) \
+ do { \
+ (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \
+ } while (0)
+
+/**
+ * @details Is SS(Select Active) in active level.
+ * \hideinitializer
+ */
+#define SPIM_GET_SS_EN() \
+ (!(SPIM->CTL1 & SPIM_CTL1_SS_Msk))
+
+/**
+ * @details Set active level of slave select to be high/low.
+ * \hideinitializer
+ */
+#define SPIM_SET_SS_ACTLVL(x) \
+ do { \
+ (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos)); \
+ } while (0)
+
+/**
+ * @details Set idle time interval
+ * \hideinitializer
+ */
+#define SPIM_SET_IDL_INTVL(x) \
+ do { \
+ SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos); \
+ } while (0)
+
+/**
+ * @details Get idle time interval setting
+ * \hideinitializer
+ */
+#define SPIM_GET_IDL_INTVL() \
+ ((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos)
+
+/**
+ * @details Set SPIM clock divider
+ * \hideinitializer
+ */
+#define SPIM_SET_CLOCK_DIVIDER(x) \
+ do { \
+ SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos); \
+ } while (0)
+
+/**
+ * @details Get SPIM current clock divider setting
+ * \hideinitializer
+ */
+#define SPIM_GET_CLOCK_DIVIDER() \
+ ((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos)
+
+/**
+ * @details Set SPI flash deselect time interval of DMA write mode
+ * \hideinitializer
+ */
+#define SPIM_SET_RXCLKDLY_DWDELSEL(x) \
+ do { \
+ (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) | ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \
+ } while (0)
+
+/**
+ * @details Get SPI flash deselect time interval of DMA write mode
+ * \hideinitializer
+ */
+#define SPIM_GET_RXCLKDLY_DWDELSEL() \
+ ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos)
+
+/**
+ * @details Set sampling clock delay selection for received data
+ * \hideinitializer
+ */
+#define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \
+ do { \
+ (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) | ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \
+ } while (0)
+
+/**
+ * @details Get sampling clock delay selection for received data
+ * \hideinitializer
+ */
+#define SPIM_GET_RXCLKDLY_RDDLYSEL() \
+ ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos)
+
+/**
+ * @details Set sampling clock edge selection for received data
+ * \hideinitializer
+ */
+#define SPIM_SET_RXCLKDLY_RDEDGE() \
+ (SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \
+
+/**
+ * @details Get sampling clock edge selection for received data
+ * \hideinitializer
+ */
+#define SPIM_CLR_RXCLKDLY_RDEDGE() \
+ (SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk)
+
+/**
+ * @details Set mode bits data for continuous read mode
+ * \hideinitializer
+ */
+#define SPIM_SET_DMMCTL_CRMDAT(x) \
+ do { \
+ (SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) | ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \
+ } while (0)
+
+/**
+ * @details Get mode bits data for continuous read mode
+ * \hideinitializer
+ */
+#define SPIM_GET_DMMCTL_CRMDAT() \
+ ((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos)
+
+/**
+ * @details Set DMM mode SPI flash deselect time
+ * \hideinitializer
+ */
+#define SPIM_DMM_SET_DESELTIM(x) \
+ do { \
+ SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos); \
+ } while (0)
+
+/**
+ * @details Get current DMM mode SPI flash deselect time setting
+ * \hideinitializer
+ */
+#define SPIM_DMM_GET_DESELTIM() \
+ ((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos)
+
+/**
+ * @details Enable DMM mode burst wrap mode
+ * \hideinitializer
+ */
+#define SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk)
+
+/**
+ * @details Disable DMM mode burst wrap mode
+ * \hideinitializer
+ */
+#define SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk)
+
+/**
+ * @details Enable DMM mode continuous read mode
+ * \hideinitializer
+ */
+#define SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk)
+
+/**
+ * @details Disable DMM mode continuous read mode
+ * \hideinitializer
+ */
+#define SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk)
+
+/**
+ * @details Set DMM mode SPI flash active SCLK time
+ * \hideinitializer
+ */
+#define SPIM_DMM_SET_ACTSCLKT(x) \
+ do { \
+ SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk; \
+ } while (0)
+
+/**
+ * @details Set SPI flash active SCLK time as SPIM default
+ * \hideinitializer
+ */
+#define SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk)
+
+/**
+ * @details Set dummy cycle number (Only for DMM mode and DMA mode)
+ * \hideinitializer
+ */
+#define SPIM_SET_DCNUM(x) \
+ do { \
+ SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk; \
+ } while (0)
+
+/**
+ * @details Set dummy cycle number (Only for DMM mode and DMA mode) as SPIM default
+ * \hideinitializer
+ */
+#define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk)
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Function Prototypes */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+int SPIM_InitFlash(int clrWP);
+uint32_t SPIM_GetSClkFreq(void);
+void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit);
+int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit);
+int SPIM_Is4ByteModeEnable(uint32_t u32NBit);
+
+void SPIM_ChipErase(uint32_t u32NBit, int isSync);
+void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync);
+
+void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat);
+void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy);
+
+void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd);
+void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync);
+
+void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl);
+void SPIM_ExitDirectMapMode(void);
+
+void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit);
+
+void SPIM_WinbondUnlock(uint32_t u32NBit);
+
+/*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SPIM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_SPIM_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sys.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sys.h
new file mode 100644
index 00000000000..a476699c2af
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sys.h
@@ -0,0 +1,1636 @@
+/**************************************************************************//**
+ * @file SYS.h
+ * @version V3.0
+ * @brief M480 Series SYS Driver Header File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+
+#ifndef __NU_SYS_H__
+#define __NU_SYS_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+ @{
+*/
+
+/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Module Reset Control Resister constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_RST ((0UL<<24) | SYS_IPRST0_PDMARST_Pos) /*!< Reset PDMA \hideinitializer*/
+#define EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) /*!< Reset EBI \hideinitializer*/
+#define EMAC_RST ((0UL<<24) | SYS_IPRST0_EMACRST_Pos) /*!< Reset EMAC \hideinitializer */
+#define SDH0_RST ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos) /*!< Reset SDH0 \hideinitializer */
+#define CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) /*!< Reset CRC \hideinitializer */
+#define CCAP_RST ((0UL<<24) | SYS_IPRST0_CCAPRST_Pos) /*!< Reset ICAP \hideinitializer */
+#define HSUSBD_RST ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos) /*!< Reset HSUSBD \hideinitializer */
+#define CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) /*!< Reset CRPT \hideinitializer */
+#define SPIM_RST ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos) /*!< Reset SPIM \hideinitializer */
+#define USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos) /*!< Reset USBH \hideinitializer */
+#define SDH1_RST ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos) /*!< Reset SDH1 \hideinitializer */
+
+#define GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) /*!< Reset GPIO \hideinitializer */
+#define TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) /*!< Reset TMR0 \hideinitializer */
+#define TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) /*!< Reset TMR1 \hideinitializer */
+#define TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) /*!< Reset TMR2 \hideinitializer */
+#define TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) /*!< Reset TMR3 \hideinitializer */
+#define ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) /*!< Reset ACMP01 \hideinitializer */
+#define I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) /*!< Reset I2C0 \hideinitializer */
+#define I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) /*!< Reset I2C1 \hideinitializer */
+#define I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) /*!< Reset I2C2 \hideinitializer */
+#define QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos) /*!< Reset QSPI0 \hideinitializer */
+#define SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) /*!< Reset SPI0 \hideinitializer */
+#define SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) /*!< Reset SPI1 \hideinitializer */
+#define SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) /*!< Reset SPI2 \hideinitializer */
+#define UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) /*!< Reset UART0 \hideinitializer */
+#define UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) /*!< Reset UART1 \hideinitializer */
+#define UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) /*!< Reset UART2 \hideinitializer */
+#define UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) /*!< Reset UART3 \hideinitializer */
+#define UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) /*!< Reset UART4 \hideinitializer */
+#define UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) /*!< Reset UART5 \hideinitializer */
+#define UART6_RST ((4UL<<24) | SYS_IPRST1_UART6RST_Pos) /*!< Reset UART6 \hideinitializer */
+#define UART7_RST ((4UL<<24) | SYS_IPRST1_UART7RST_Pos) /*!< Reset UART7 \hideinitializer */
+#define CAN0_RST ((4UL<<24) | SYS_IPRST1_CAN0RST_Pos) /*!< Reset CAN0 \hideinitializer */
+#define CAN1_RST ((4UL<<24) | SYS_IPRST1_CAN1RST_Pos) /*!< Reset CAN1 \hideinitializer */
+#define OTG_RST ((4UL<<24) | SYS_IPRST1_OTGRST_Pos) /*!< Reset OTG \hideinitializer */
+#define USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) /*!< Reset USBD \hideinitializer */
+#define EADC_RST ((4UL<<24) | SYS_IPRST1_EADCRST_Pos) /*!< Reset EADC \hideinitializer */
+#define I2S0_RST ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos) /*!< Reset I2S0 \hideinitializer */
+#define HSOTG_RST ((4UL<<24) | SYS_IPRST1_HSOTGRST_Pos) /*!< Reset HSOTG \hideinitializer */
+#define TRNG_RST ((4UL<<24) | SYS_IPRST1_TRNGRST_Pos) /*!< Reset TRNG \hideinitializer */
+
+#define SC0_RST ((8UL<<24) | SYS_IPRST2_SC0RST_Pos) /*!< Reset SC0 \hideinitializer */
+#define SC1_RST ((8UL<<24) | SYS_IPRST2_SC1RST_Pos) /*!< Reset SC1 \hideinitializer */
+#define SC2_RST ((8UL<<24) | SYS_IPRST2_SC2RST_Pos) /*!< Reset SC2 \hideinitializer */
+#define QSPI1_RST ((8UL<<24) | SYS_IPRST2_QSPI1RST_Pos) /*!< Reset QSPI1 \hideinitializer */
+#define SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos) /*!< Reset SPI3 \hideinitializer */
+#define USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) /*!< Reset USCI0 \hideinitializer */
+#define USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos) /*!< Reset USCI1 \hideinitializer */
+#define DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) /*!< Reset DAC \hideinitializer */
+#define EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) /*!< Reset EPWM0 \hideinitializer */
+#define EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) /*!< Reset EPWM1 \hideinitializer */
+#define BPWM0_RST ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos) /*!< Reset BPWM0 \hideinitializer */
+#define BPWM1_RST ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos) /*!< Reset BPWM1 \hideinitializer */
+#define QEI0_RST ((8UL<<24) | SYS_IPRST2_QEI0RST_Pos) /*!< Reset QEI0 \hideinitializer */
+#define QEI1_RST ((8UL<<24) | SYS_IPRST2_QEI1RST_Pos) /*!< Reset QEI1 \hideinitializer */
+#define ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) /*!< Reset ECAP0 \hideinitializer */
+#define ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) /*!< Reset ECAP1 \hideinitializer */
+#define CAN2_RST ((8UL<<24) | SYS_IPRST2_CAN2RST_Pos) /*!< Reset CAN2 \hideinitializer */
+#define OPA_RST ((8UL<<24) | SYS_IPRST2_OPARST_Pos) /*!< Reset OPA \hideinitializer */
+#define EADC1_RST ((8UL<<24) | SYS_IPRST2_EADC1RST_Pos) /*!< Reset EADC1 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Brown Out Detector Threshold Voltage Selection constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_BODCTL_BOD_RST_EN (1UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable \hideinitializer */
+#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable \hideinitializer */
+#define SYS_BODCTL_BODVL_3_0V (7UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_8V (6UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_6V (5UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_4V (4UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_2V (3UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_0V (2UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V \hideinitializer */
+#define SYS_BODCTL_BODVL_1_8V (1UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V \hideinitializer */
+#define SYS_BODCTL_BODVL_1_6V (0UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* VREFCTL constant definitions. (Write-Protection Register) */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_VREFCTL_VREF_PIN (0x0UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin \hideinitializer */
+#define SYS_VREFCTL_VREF_1_6V (0x3UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V \hideinitializer */
+#define SYS_VREFCTL_VREF_2_0V (0x7UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V \hideinitializer */
+#define SYS_VREFCTL_VREF_2_5V (0xBUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V \hideinitializer */
+#define SYS_VREFCTL_VREF_3_0V (0xFUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V \hideinitializer */
+#define SYS_VREFCTL_VREF_AVDD (0x10UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = AVDD \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USBPHY constant definitions. (Write-Protection Register) */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device \hideinitializer */
+#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */
+#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL << SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */
+#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */
+#define SYS_USBPHY_HSUSBROLE_STD_USBD (0x0UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB device \hideinitializer */
+#define SYS_USBPHY_HSUSBROLE_STD_USBH (0x1UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB host \hideinitializer */
+#define SYS_USBPHY_HSUSBROLE_ID_DEPH (0x2UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< ID dependent device \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* PLCTL constant definitions. (Write-Protection Register) */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_PLCTL_PLSEL_PL0 (0x0UL<GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ;
+
+*/
+/********************* Bit definition of GPA_MFPL register **********************/
+#define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<BODCTL |= SYS_BODCTL_BODIF_Msk)
+
+/**
+ * @brief Set Brown-out detector function to normal mode
+ * @param None
+ * @return None
+ * @details This macro set Brown-out detector to normal mode.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
+
+/**
+ * @brief Disable Brown-out detector function
+ * @param None
+ * @return None
+ * @details This macro disable Brown-out detector function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
+
+/**
+ * @brief Enable Brown-out detector function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detector function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
+
+/**
+ * @brief Get Brown-out detector interrupt flag
+ * @param None
+ * @retval 0 Brown-out detect interrupt flag is not set.
+ * @retval >=1 Brown-out detect interrupt flag is set.
+ * @details This macro get Brown-out detector interrupt flag.
+ * \hideinitializer
+ */
+#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
+
+/**
+ * @brief Get Brown-out detector status
+ * @param None
+ * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
+ * @retval >=1 System voltage is lower than BOD threshold voltage setting.
+ * @details This macro get Brown-out detector output status.
+ * If the BOD function is disabled, this function always return 0.
+ * \hideinitializer
+ */
+#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
+
+/**
+ * @brief Enable Brown-out detector interrupt function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detector interrupt function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
+
+/**
+ * @brief Enable Brown-out detector reset function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detect reset function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
+
+/**
+ * @brief Set Brown-out detector function low power mode
+ * @param None
+ * @return None
+ * @details This macro set Brown-out detector to low power mode.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
+
+/**
+ * @brief Set Brown-out detector voltage level
+ * @param[in] u32Level is Brown-out voltage level. Including :
+ * - \ref SYS_BODCTL_BODVL_3_0V
+ * - \ref SYS_BODCTL_BODVL_2_8V
+ * - \ref SYS_BODCTL_BODVL_2_6V
+ * - \ref SYS_BODCTL_BODVL_2_4V
+ * - \ref SYS_BODCTL_BODVL_2_2V
+ * - \ref SYS_BODCTL_BODVL_2_0V
+ * - \ref SYS_BODCTL_BODVL_1_8V
+ * - \ref SYS_BODCTL_BODVL_1_6V
+ * @return None
+ * @details This macro set Brown-out detector voltage level.
+ * The write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
+
+/**
+ * @brief Get reset source is from Brown-out detector reset
+ * @param None
+ * @retval 0 Previous reset source is not from Brown-out detector reset
+ * @retval >=1 Previous reset source is from Brown-out detector reset
+ * @details This macro get previous reset source is from Brown-out detect reset or not.
+ * \hideinitializer
+ */
+#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
+
+/**
+ * @brief Get reset source is from CPU reset
+ * @param None
+ * @retval 0 Previous reset source is not from CPU reset
+ * @retval >=1 Previous reset source is from CPU reset
+ * @details This macro get previous reset source is from CPU reset.
+ * \hideinitializer
+ */
+#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
+
+/**
+ * @brief Get reset source is from LVR Reset
+ * @param None
+ * @retval 0 Previous reset source is not from Low-Voltage-Reset
+ * @retval >=1 Previous reset source is from Low-Voltage-Reset
+ * @details This macro get previous reset source is from Low-Voltage-Reset.
+ * \hideinitializer
+ */
+#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
+
+/**
+ * @brief Get reset source is from Power-on Reset
+ * @param None
+ * @retval 0 Previous reset source is not from Power-on Reset
+ * @retval >=1 Previous reset source is from Power-on Reset
+ * @details This macro get previous reset source is from Power-on Reset.
+ * \hideinitializer
+ */
+#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
+
+/**
+ * @brief Get reset source is from reset pin reset
+ * @param None
+ * @retval 0 Previous reset source is not from reset pin reset
+ * @retval >=1 Previous reset source is from reset pin reset
+ * @details This macro get previous reset source is from reset pin reset.
+ * \hideinitializer
+ */
+#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
+
+/**
+ * @brief Get reset source is from system reset
+ * @param None
+ * @retval 0 Previous reset source is not from system reset
+ * @retval >=1 Previous reset source is from system reset
+ * @details This macro get previous reset source is from system reset.
+ * \hideinitializer
+ */
+#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
+
+/**
+ * @brief Get reset source is from window watch dog reset
+ * @param None
+ * @retval 0 Previous reset source is not from window watch dog reset
+ * @retval >=1 Previous reset source is from window watch dog reset
+ * @details This macro get previous reset source is from window watch dog reset.
+ * \hideinitializer
+ */
+#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
+
+/**
+ * @brief Disable Low-Voltage-Reset function
+ * @param None
+ * @return None
+ * @details This macro disable Low-Voltage-Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
+
+/**
+ * @brief Enable Low-Voltage-Reset function
+ * @param None
+ * @return None
+ * @details This macro enable Low-Voltage-Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
+
+/**
+ * @brief Disable Power-on Reset function
+ * @param None
+ * @return None
+ * @details This macro disable Power-on Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_DISABLE_POR() (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0) ? (SYS->PORCTL = 0x5AA5):(SYS->PORDISAN = 0x5AA5))
+
+/**
+ * @brief Enable Power-on Reset function
+ * @param None
+ * @return None
+ * @details This macro enable Power-on Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_ENABLE_POR() (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0) ? (SYS->PORCTL = 0):(SYS->PORDISAN = 0))
+
+/**
+ * @brief Clear reset source flag
+ * @param[in] u32RstSrc is reset source. Including :
+ * - \ref SYS_RSTSTS_PORF_Msk
+ * - \ref SYS_RSTSTS_PINRF_Msk
+ * - \ref SYS_RSTSTS_WDTRF_Msk
+ * - \ref SYS_RSTSTS_LVRF_Msk
+ * - \ref SYS_RSTSTS_BODRF_Msk
+ * - \ref SYS_RSTSTS_SYSRF_Msk
+ * - \ref SYS_RSTSTS_CPURF_Msk
+ * - \ref SYS_RSTSTS_CPULKRF_Msk
+ * @return None
+ * @details This macro clear reset source flag.
+ * \hideinitializer
+ */
+#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void SYS_UnlockReg(void);
+__STATIC_INLINE void SYS_LockReg(void);
+
+/**
+ * @brief Disable register write-protection function
+ * @param None
+ * @return None
+ * @details This function disable register write-protection function.
+ * To unlock the protected register to allow write access.
+ */
+__STATIC_INLINE void SYS_UnlockReg(void)
+{
+ do
+ {
+ SYS->REGLCTL = 0x59UL;
+ SYS->REGLCTL = 0x16UL;
+ SYS->REGLCTL = 0x88UL;
+ }
+ while(SYS->REGLCTL == 0UL);
+}
+
+/**
+ * @brief Enable register write-protection function
+ * @param None
+ * @return None
+ * @details This function is used to enable register write-protection function.
+ * To lock the protected register to forbid write access.
+ */
+__STATIC_INLINE void SYS_LockReg(void)
+{
+ SYS->REGLCTL = 0UL;
+}
+
+
+void SYS_ClearResetSrc(uint32_t u32Src);
+uint32_t SYS_GetBODStatus(void);
+uint32_t SYS_GetResetSrc(void);
+uint32_t SYS_IsRegLocked(void);
+uint32_t SYS_ReadPDID(void);
+void SYS_ResetChip(void);
+void SYS_ResetCPU(void);
+void SYS_ResetModule(uint32_t u32ModuleIndex);
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
+void SYS_DisableBOD(void);
+void SYS_SetPowerLevel(uint32_t u32PowerLevel);
+void SYS_SetVRef(uint32_t u32VRefCTL);
+
+/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SYS_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_SYS_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer.h
new file mode 100644
index 00000000000..f889abf09f0
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer.h
@@ -0,0 +1,523 @@
+/**************************************************************************//**
+ * @file nu_timer.h
+ * @version V1.00
+ * @brief M480 series Timer Controller(Timer) driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_TIMER_H__
+#define __NU_TIMER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup TIMER_Driver TIMER Driver
+ @{
+*/
+
+/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */
+#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */
+#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */
+#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */
+#define TIMER_TOUT_PIN_FROM_TMX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx pin \hideinitializer */
+#define TIMER_TOUT_PIN_FROM_TMX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */
+
+#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */
+#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */
+#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */
+#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */
+
+#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event \hideinitializer */
+#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event \hideinitializer */
+#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */
+#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */
+#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */
+#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */
+
+#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */
+#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */
+#define TIMER_TRG_TO_EPWM (TIMER_TRGCTL_TRGEPWM_Msk) /*!< Each timer event as EPWM counter clock source \hideinitializer */
+#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion \hideinitializer */
+#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion \hideinitializer */
+#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer \hideinitializer */
+
+/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set Timer Compared Value
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF.
+ *
+ * @return None
+ *
+ * @details This macro is used to set timer compared value to adjust timer time-out interval.
+ * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n
+ * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n
+ * But if timer is operating at other modes, the timer up counter will restart counting and start from 0.
+ * \hideinitializer
+ */
+#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value))
+
+/**
+ * @brief Set Timer Prescale Value
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF.
+ *
+ * @return None
+ *
+ * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n
+ * before it is fed into timer.
+ * \hideinitializer
+ */
+#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
+
+/**
+ * @brief Check specify Timer Status
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Timer 24-bit up counter is inactive
+ * @retval 1 Timer 24-bit up counter is active
+ *
+ * @details This macro is used to check if specify Timer counter is inactive or active.
+ * \hideinitializer
+ */
+#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0)
+
+/**
+ * @brief Select Toggle-output Pin
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32ToutSel Toggle-output pin selection, valid values are:
+ * - \ref TIMER_TOUT_PIN_FROM_TMX
+ * - \ref TIMER_TOUT_PIN_FROM_TMX_EXT
+ *
+ * @return None
+ *
+ * @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin.
+ * \hideinitializer
+ */
+#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
+
+/**
+ * @brief Select Timer operating mode
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32OpMode Operation mode. Possible options are
+ * - \ref TIMER_ONESHOT_MODE
+ * - \ref TIMER_PERIODIC_MODE
+ * - \ref TIMER_TOGGLE_MODE
+ * - \ref TIMER_CONTINUOUS_MODE
+ *
+ * @return None
+ * \hideinitializer
+ */
+#define TIMER_SET_OPMODE(timer, u32OpMode) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_OPMODE_Msk) | (u32OpMode))
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void TIMER_Start(TIMER_T *timer);
+__STATIC_INLINE void TIMER_Stop(TIMER_T *timer);
+__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer);
+__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer);
+__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer);
+__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer);
+__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer);
+__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer);
+__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer);
+__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer);
+__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer);
+__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer);
+__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer);
+__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer);
+__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer);
+__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer);
+__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer);
+__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer);
+__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer);
+__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer);
+__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer);
+__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer);
+__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer);
+
+/**
+ * @brief Start Timer Counting
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to start Timer counting.
+ */
+__STATIC_INLINE void TIMER_Start(TIMER_T *timer)
+{
+ timer->CTL |= TIMER_CTL_CNTEN_Msk;
+}
+
+/**
+ * @brief Stop Timer Counting
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to stop/suspend Timer counting.
+ */
+__STATIC_INLINE void TIMER_Stop(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
+}
+
+/**
+ * @brief Enable Timer Interrupt Wake-up Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n
+ * counter event interrupt or capture trigger interrupt.
+ * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
+ */
+__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer)
+{
+ timer->CTL |= TIMER_CTL_WKEN_Msk;
+}
+
+/**
+ * @brief Disable Timer Wake-up Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable the timer interrupt wake-up function.
+ */
+__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_WKEN_Msk;
+}
+
+/**
+ * @brief Start Timer Capture Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to start Timer capture function.
+ */
+__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer)
+{
+ timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+ * @brief Stop Timer Capture Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to stop Timer capture function.
+ */
+__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer)
+{
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+ * @brief Enable Capture Pin De-bounce
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable the detect de-bounce function of capture pin.
+ */
+__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
+{
+ timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
+}
+
+/**
+ * @brief Disable Capture Pin De-bounce
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable the detect de-bounce function of capture pin.
+ */
+__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
+{
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
+}
+
+/**
+ * @brief Enable Counter Pin De-bounce
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable the detect de-bounce function of counter pin.
+ */
+__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
+{
+ timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
+}
+
+/**
+ * @brief Disable Counter Pin De-bounce
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable the detect de-bounce function of counter pin.
+ */
+__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
+{
+ timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
+}
+
+/**
+ * @brief Enable Timer Time-out Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable the timer time-out interrupt function.
+ */
+__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer)
+{
+ timer->CTL |= TIMER_CTL_INTEN_Msk;
+}
+
+/**
+ * @brief Disable Timer Time-out Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable the timer time-out interrupt function.
+ */
+__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_INTEN_Msk;
+}
+
+/**
+ * @brief Enable Capture Trigger Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable the timer capture trigger interrupt function.
+ */
+__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
+{
+ timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
+}
+
+/**
+ * @brief Disable Capture Trigger Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable the timer capture trigger interrupt function.
+ */
+__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
+{
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
+}
+
+/**
+ * @brief Get Timer Time-out Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Timer time-out interrupt did not occur
+ * @retval 1 Timer time-out interrupt occurred
+ *
+ * @details This function indicates timer time-out interrupt occurred or not.
+ */
+__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
+{
+ return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Timer Time-out Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function clears timer time-out interrupt flag to 0.
+ */
+__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
+{
+ timer->INTSTS = TIMER_INTSTS_TIF_Msk;
+}
+
+/**
+ * @brief Get Timer Capture Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Timer capture interrupt did not occur
+ * @retval 1 Timer capture interrupt occurred
+ *
+ * @details This function indicates timer capture trigger interrupt occurred or not.
+ */
+__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
+{
+ return timer->EINTSTS;
+}
+
+/**
+ * @brief Clear Timer Capture Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function clears timer capture trigger interrupt flag to 0.
+ */
+__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
+{
+ timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
+}
+
+/**
+ * @brief Get Timer Wake-up Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Timer does not cause CPU wake-up
+ * @retval 1 Timer interrupt event cause CPU wake-up
+ *
+ * @details This function indicates timer interrupt event has waked up system or not.
+ */
+__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
+{
+ return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Timer Wake-up Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function clears the timer wake-up system flag to 0.
+ */
+__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
+{
+ timer->INTSTS = TIMER_INTSTS_TWKF_Msk;
+}
+
+/**
+ * @brief Get Capture value
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return 24-bit Capture Value
+ *
+ * @details This function reports the current 24-bit timer capture value.
+ */
+__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
+{
+ return timer->CAP;
+}
+
+/**
+ * @brief Get Counter value
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return 24-bit Counter Value
+ *
+ * @details This function reports the current 24-bit timer counter value.
+ */
+__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
+{
+ return timer->CNT;
+}
+
+/**
+ * @brief Reset Counter
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to reset current counter value and internal prescale counter value.
+ */
+__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer)
+{
+ timer->CNT = 0UL;
+ while((timer->CNT&TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk)
+ {
+ ;
+ }
+}
+
+
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
+void TIMER_Close(TIMER_T *timer);
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
+void TIMER_DisableCapture(TIMER_T *timer);
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
+void TIMER_DisableEventCounter(TIMER_T *timer);
+uint32_t TIMER_GetModuleClock(TIMER_T *timer);
+void TIMER_EnableFreqCounter(TIMER_T *timer,
+ uint32_t u32DropCount,
+ uint32_t u32Timeout,
+ uint32_t u32EnableInt);
+void TIMER_DisableFreqCounter(TIMER_T *timer);
+void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src);
+void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask);
+
+/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TIMER_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_TIMER_H__ */
+
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer_pwm.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer_pwm.h
new file mode 100644
index 00000000000..c7b122ff911
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer_pwm.h
@@ -0,0 +1,746 @@
+/**************************************************************************//**
+ * @file nu_timer_pwm.h
+ * @version V1.00
+ * @brief M480 series Timer PWM Controller(Timer PWM) driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_TIMER_PWM_H__
+#define __NU_TIMER_PWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver
+ @{
+*/
+
+/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* Output Channel Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */
+#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Counter Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_UP_COUNT (0UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up count type \hideinitializer */
+#define TPWM_DOWN_COUNT (1UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Down count type \hideinitializer */
+#define TPWM_UP_DOWN_COUNT (2UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up-Down count type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Counter Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */
+#define TPWM_ONE_SHOT_MODE (TIMER_PWMCTL_CNTMODE_Msk) /*!< One-shot mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Output Level Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */
+#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */
+#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */
+#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Trigger ADC Source Select Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_TRIGGER_ADC_AT_ZERO_POINT (0UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero point event occurred \hideinitializer */
+#define TPWM_TRIGGER_ADC_AT_PERIOD_POINT (1UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter period point event occurred \hideinitializer */
+#define TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT (2UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero or period point event occurred \hideinitializer */
+#define TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT (3UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter up count compare point event occurred \hideinitializer */
+#define TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT (4UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter down count compare point event occurred \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Brake Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */
+
+
+#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */
+
+#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake \hideinitializer */
+#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Load Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */
+#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */
+#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Brake Pin De-bounce Clock Source Select Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Brake Pin Source Select Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */
+#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */
+#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */
+#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Counter Clock Source Select Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Counter Synchronous Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */
+#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<ALTCTL = (1 << TIMER_ALTCTL_FUNCSEL_Pos))
+
+/**
+ * @brief Disable PWM Counter Mode
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available.
+ * @note All registers about PWM counter function will be cleared to 0 after executing this macro.
+ * \hideinitializer
+ */
+#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->ALTCTL = (0 << TIMER_ALTCTL_FUNCSEL_Pos))
+
+/**
+ * @brief Enable Independent Mode
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled.
+ * \hideinitializer
+ */
+#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1 << TIMER_PWMCTL_OUTMODE_Pos))
+
+/**
+ * @brief Enable Complementary Mode
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled.
+ * \hideinitializer
+ */
+#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos))
+
+/**
+ * @brief Set Counter Type
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] type Timer PWM count type, could be one of the following type
+ * - \ref TPWM_UP_COUNT
+ * - \ref TPWM_DOWN_COUNT
+ * - \ref TPWM_UP_DOWN_COUNT
+ *
+ * @return None
+ *
+ * @details This macro is used to set Timer PWM counter type.
+ * \hideinitializer
+ */
+#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type))
+
+/**
+ * @brief Start PWM Counter
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to enable PWM generator and start counter counting.
+ * \hideinitializer
+ */
+#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk)
+
+/**
+ * @brief Stop PWM Counter
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to stop PWM counter after current period is completed.
+ * \hideinitializer
+ */
+#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0)
+
+/**
+ * @brief Set Counter Clock Prescaler
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @param[in] prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFFF.
+ *
+ * @return None
+ *
+ * @details This macro is used to set the prescaler of specified TIMER PWM.
+ * @note If prescaler is 0, then there is no scaling in counter clock source.
+ * \hideinitializer
+ */
+#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler))
+
+/**
+ * @brief Get Counter Clock Prescaler
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0])
+ *
+ * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1).
+ * \hideinitializer
+ */
+#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC)
+
+/**
+ * @brief Set Counter Period
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF.
+ *
+ * @return None
+ *
+ * @details This macro is used to set the period of specified TIMER PWM.
+ * \hideinitializer
+ */
+#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period))
+
+/**
+ * @brief Get Counter Period
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0])
+ *
+ * @details This macro is used to get the period of specified TIMER PWM.
+ * \hideinitializer
+ */
+#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD)
+
+/**
+ * @brief Set Comparator Value
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF.
+ *
+ * @return None
+ *
+ * @details This macro is used to set the comparator value of specified TIMER PWM.
+ * \hideinitializer
+ */
+#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp))
+
+/**
+ * @brief Get Comparator Value
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0])
+ *
+ * @details This macro is used to get the comparator value of specified TIMER PWM.
+ * \hideinitializer
+ */
+#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT)
+
+/**
+ * @brief Clear Counter
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to clear counter of specified TIMER PWM.
+ * \hideinitializer
+ */
+#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk)
+
+/**
+ * @brief Software Trigger Brake Event
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @param[in] type Type of brake trigger. Valid values are:
+ * - \ref TPWM_BRAKE_EDGE
+ * - \ref TPWM_BRAKE_LEVEL
+ *
+ * @return None
+ *
+ * @details This macro is used to trigger brake event by writing PWMSWBRK register.
+ * \hideinitializer
+ */
+#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type))
+
+/**
+ * @brief Enable Output Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @param[in] ch Enable specified channel output function. Valid values are the combination of:
+ * - \ref TPWM_CH0
+ * - \ref TPWM_CH1
+ *
+ * @return None
+ *
+ * @details This macro is used to enable output function of specified output pins.
+ * @note If the corresponding bit in ch parameter is 0, then output function will be disabled in this channel.
+ * \hideinitializer
+ */
+#define TPWM_ENABLE_OUTPUT(timer, ch) ((timer)->PWMPOEN = (ch))
+
+/**
+ * @brief Set Output Inverse
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @param[in] ch Set specified channel output is inversed or not. Valid values are the combination of:
+ * - \ref TPWM_CH0
+ * - \ref TPWM_CH1
+ *
+ * @return None
+ *
+ * @details This macro is used to enable output inverse of specified output pins.
+ * @note If ch parameter is 0, then output inverse function will be disabled.
+ * \hideinitializer
+ */
+#define TPWM_SET_OUTPUT_INVERSE(timer, ch) ((timer)->PWMPOLCTL = (ch))
+
+/**
+ * @brief Enable Output Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @param[in] ch Enable specified channel output mask function. Valid values are the combination of:
+ * - \ref TPWM_CH0
+ * - \ref TPWM_CH1
+ *
+ * @param[in] level Output to high or low on specified mask channel.
+ *
+ * @return None
+ *
+ * @details This macro is used to enable output function of specified output pins.
+ * @note If ch parameter is 0, then output mask function will be disabled.
+ * \hideinitializer
+ */
+#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0)
+
+/**
+ * @brief Set Counter Synchronous Mode
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @param[in] mode Synchronous mode. Possible options are:
+ * - \ref TPWM_CNTR_SYNC_DISABLE
+ * - \ref TPWM_CNTR_SYNC_START_BY_TIMER0
+ * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0
+ * - \ref TPWM_CNTR_SYNC_START_BY_TIMER2
+ * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2
+ *
+ * @return None
+ *
+ * @details This macro is used to set counter synchronous mode of specified Timer PWM module.
+ * @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and
+ * TIMER2~3 PWM counter synchronous by TIMER2 PWM.
+ * \hideinitializer
+ */
+#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode))
+
+/**
+ * @brief Trigger Counter Synchronous
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to trigger synchronous event by specified TIMER PWM.
+ * @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n
+ * 2. STRGEN (PWMSTRG[0]) is write only and always read as 0.
+ * \hideinitializer
+ */
+#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk)
+
+/**
+ * @brief Enable Zero Event Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to enable the zero event interrupt function.
+ * \hideinitializer
+ */
+#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk)
+
+/**
+ * @brief Disable Zero Event Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to disable the zero event interrupt function.
+ * \hideinitializer
+ */
+#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk)
+
+/**
+ * @brief Get Zero Event Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Zero event interrupt did not occur
+ * @retval 1 Zero event interrupt occurred
+ *
+ * @details This macro indicates zero event occurred or not.
+ * \hideinitializer
+ */
+#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0)
+
+/**
+ * @brief Clear Zero Event Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro clears zero event interrupt flag.
+ * \hideinitializer
+ */
+#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk)
+
+/**
+ * @brief Enable Period Event Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to enable the period event interrupt function.
+ * \hideinitializer
+ */
+#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk)
+
+/**
+ * @brief Disable Period Event Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to disable the period event interrupt function.
+ * \hideinitializer
+ */
+#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk)
+
+/**
+ * @brief Get Period Event Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Period event interrupt did not occur
+ * @retval 1 Period event interrupt occurred
+ *
+ * @details This macro indicates period event occurred or not.
+ * \hideinitializer
+ */
+#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0)
+
+/**
+ * @brief Clear Period Event Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro clears period event interrupt flag.
+ * \hideinitializer
+ */
+#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk)
+
+/**
+ * @brief Enable Compare Up Event Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to enable the compare up event interrupt function.
+ * \hideinitializer
+ */
+#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk)
+
+/**
+ * @brief Disable Compare Up Event Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to disable the compare up event interrupt function.
+ * \hideinitializer
+ */
+#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk)
+
+/**
+ * @brief Get Compare Up Event Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Compare up event interrupt did not occur
+ * @retval 1 Compare up event interrupt occurred
+ *
+ * @details This macro indicates compare up event occurred or not.
+ * \hideinitializer
+ */
+#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0)
+
+/**
+ * @brief Clear Compare Up Event Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro clears compare up event interrupt flag.
+ * \hideinitializer
+ */
+#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk)
+
+/**
+ * @brief Enable Compare Down Event Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to enable the compare down event interrupt function.
+ * \hideinitializer
+ */
+#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk)
+
+/**
+ * @brief Disable Compare Down Event Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to disable the compare down event interrupt function.
+ * \hideinitializer
+ */
+#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk)
+
+/**
+ * @brief Get Compare Down Event Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Compare down event interrupt did not occur
+ * @retval 1 Compare down event interrupt occurred
+ *
+ * @details This macro indicates compare down event occurred or not.
+ * \hideinitializer
+ */
+#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0)
+
+/**
+ * @brief Clear Compare Down Event Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro clears compare down event interrupt flag.
+ * \hideinitializer
+ */
+#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk)
+
+/**
+ * @brief Get Counter Reach Maximum Count Status
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Timer PWM counter never counts to maximum value
+ * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF
+ *
+ * @details This macro indicates Timer PWM counter has count to 0xFFFF or not.
+ * \hideinitializer
+ */
+#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0)
+
+/**
+ * @brief Clear Counter Reach Maximum Count Status
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro clears reach maximum count status.
+ * \hideinitializer
+ */
+#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk)
+
+/**
+ * @brief Get Trigger ADC Status
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Trigger ADC start conversion is not occur
+ * @retval 1 Specified counter compare event has trigger ADC start conversion
+ *
+ * @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion.
+ * \hideinitializer
+ */
+#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0)
+
+/**
+ * @brief Clear Trigger ADC Status
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to clear PWM counter compare event trigger ADC status.
+ * \hideinitializer
+ */
+#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk)
+
+/**
+ * @brief Set Brake Event at Brake Pin High or Low-to-High
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high.
+ * @note The default brake pin detection is high level or from low to high.
+ * \hideinitializer
+ */
+#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk)
+
+/**
+ * @brief Set Brake Event at Brake Pin Low or High-to-Low
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low.
+ * \hideinitializer
+ */
+#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk)
+
+/**
+ * @brief Set External Brake Pin Source
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] pin The external brake pin source, could be one of following source
+ * - \ref TPWM_TM_BRAKE0
+ * - \ref TPWM_TM_BRAKE1
+ * - \ref TPWM_TM_BRAKE2
+ * - \ref TPWM_TM_BRAKE3
+ *
+ * @return None
+ *
+ * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high.
+ * \hideinitializer
+ */
+#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<CTL = (TRNG->CTL&~TRNG_CTL_CLKP_Msk)|((clkpsc & 0xf)<> 4ul)-2ul)
+
+
+/**
+ * @brief Calculate UART baudrate mode2 divider
+ *
+ * @param[in] u32SrcFreq UART clock frequency
+ * @param[in] u32BaudRate Baudrate of UART module
+ *
+ * @return UART baudrate mode2 divider
+ *
+ * @details This macro calculate UART baudrate mode2 divider.
+ * \hideinitializer
+ */
+#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul)
+
+
+/**
+ * @brief Write UART data
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u8Data Data byte to transmit.
+ *
+ * @return None
+ *
+ * @details This macro write Data to Tx data register.
+ * \hideinitializer
+ */
+#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data))
+
+
+/**
+ * @brief Read UART data
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return The oldest data byte in RX FIFO.
+ *
+ * @details This macro read Rx data register.
+ * \hideinitializer
+ */
+#define UART_READ(uart) ((uart)->DAT)
+
+
+/**
+ * @brief Get Tx empty
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Tx FIFO is not empty
+ * @retval >=1 Tx FIFO is empty
+ *
+ * @details This macro get Transmitter FIFO empty register value.
+ * \hideinitializer
+ */
+#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
+
+
+/**
+ * @brief Get Rx empty
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Rx FIFO is not empty
+ * @retval >=1 Rx FIFO is empty
+ *
+ * @details This macro get Receiver FIFO empty register value.
+ * \hideinitializer
+ */
+#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
+
+
+/**
+ * @brief Check specified UART port transmission is over.
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Tx transmission is not over
+ * @retval 1 Tx transmission is over
+ *
+ * @details This macro return Transmitter Empty Flag register bit value.
+ * It indicates if specified UART port transmission is over nor not.
+ * \hideinitializer
+ */
+#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
+
+
+/**
+ * @brief Wait specified UART port transmission is over
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro wait specified UART port transmission is over.
+ * \hideinitializer
+ */
+#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
+
+
+/**
+ * @brief Check RX is ready or not
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 The number of bytes in the RX FIFO is less than the RFITL
+ * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL
+ *
+ * @details This macro check receive data available interrupt flag is set or not.
+ * \hideinitializer
+ */
+#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
+
+
+/**
+ * @brief Check TX FIFO is full or not
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 1 TX FIFO is full
+ * @retval 0 TX FIFO is not full
+ *
+ * @details This macro check TX FIFO is full or not.
+ * \hideinitializer
+ */
+#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
+
+
+/**
+ * @brief Check RX FIFO is full or not
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 1 RX FIFO is full
+ * @retval 0 RX FIFO is not full
+ *
+ * @details This macro check RX FIFO is full or not.
+ * \hideinitializer
+ */
+#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
+
+
+/**
+ * @brief Get Tx full register value
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Tx FIFO is not full.
+ * @retval >=1 Tx FIFO is full.
+ *
+ * @details This macro get Tx full register value.
+ * \hideinitializer
+ */
+#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
+
+
+/**
+ * @brief Get Rx full register value
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Rx FIFO is not full.
+ * @retval >=1 Rx FIFO is full.
+ *
+ * @details This macro get Rx full register value.
+ * \hideinitializer
+ */
+#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
+
+
+/**
+ * @brief Enable specified UART interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32eIntSel Interrupt type select
+ * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
+ * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
+ *
+ * @return None
+ *
+ * @details This macro enable specified UART interrupt.
+ * \hideinitializer
+ */
+#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel))
+
+
+/**
+ * @brief Disable specified UART interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32eIntSel Interrupt type select
+ * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
+ * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
+ *
+ * @return None
+ *
+ * @details This macro enable specified UART interrupt.
+ * \hideinitializer
+ */
+#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel))
+
+
+/**
+ * @brief Get specified interrupt flag/status
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
+ * - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator
+ * - \ref UART_INTSTS_HWTOINT_Msk : In DMA Mode, Time-out Interrupt Indicator
+ * - \ref UART_INTSTS_HWMODINT_Msk : In DMA Mode, MODEM Status Interrupt Indicator
+ * - \ref UART_INTSTS_HWRLSINT_Msk : In DMA Mode, Receive Line Status Interrupt Indicator
+ * - \ref UART_INTSTS_HWBUFEIF_Msk : In DMA Mode, Buffer Error Interrupt Flag
+ * - \ref UART_INTSTS_HWTOIF_Msk : In DMA Mode, Time-out Interrupt Flag
+ * - \ref UART_INTSTS_HWMODIF_Msk : In DMA Mode, MODEM Interrupt Flag
+ * - \ref UART_INTSTS_HWRLSIF_Msk : In DMA Mode, Receive Line Status Flag
+ * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator
+ * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
+ * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator
+ * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator
+ * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator
+ * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator
+ * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator
+ * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag
+ * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
+ * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag
+ * - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag
+ * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag
+ * - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag
+ * - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag
+ *
+ * @retval 0 The specified interrupt is not happened.
+ * 1 The specified interrupt is happened.
+ *
+ * @details This macro get specified interrupt flag or interrupt indicator status.
+ * \hideinitializer
+ */
+#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)
+
+
+/**
+ * @brief Clear RS-485 Address Byte Detection Flag
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro clear RS-485 address byte detection flag.
+ * \hideinitializer
+ */
+#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
+
+
+/**
+ * @brief Get RS-485 Address Byte Detection Flag
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Receiver detects a data that is not an address bit.
+ * @retval 1 Receiver detects a data that is an address bit.
+ *
+ * @details This macro get RS-485 address byte detection flag.
+ * \hideinitializer
+ */
+#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart);
+__STATIC_INLINE void UART_SET_RTS(UART_T* uart);
+
+
+/**
+ * @brief Set RTS pin to low
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro set RTS pin to low.
+ */
+__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart)
+{
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+ uart->MODEM &= ~UART_MODEM_RTS_Msk;
+}
+
+
+/**
+ * @brief Set RTS pin to high
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro set RTS pin to high.
+ */
+__STATIC_INLINE void UART_SET_RTS(UART_T* uart)
+{
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
+}
+
+/**
+ * @brief Enable specified UART PDMA function
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32FuncSel Combination of following functions
+ * - \ref UART_INTEN_TXPDMAEN_Msk
+ * - \ref UART_INTEN_RXPDMAEN_Msk
+ *
+ * @return None
+ *
+ * \hideinitializer
+ */
+#define UART_PDMA_ENABLE(uart, u32FuncSel) ((uart)->INTEN |= (u32FuncSel))
+/**
+ * @brief Disable specified UART PDMA function
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32FuncSel Combination of following functions
+ * - \ref UART_INTEN_TXPDMAEN_Msk
+ * - \ref UART_INTEN_RXPDMAEN_Msk
+ *
+ * @return None
+ *
+ * \hideinitializer
+ */
+#define UART_PDMA_DISABLE(uart, u32FuncSel) ((uart)->INTEN &= ~(u32FuncSel))
+
+
+void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag);
+void UART_Close(UART_T* uart);
+void UART_DisableFlowCtrl(UART_T* uart);
+void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag);
+void UART_EnableFlowCtrl(UART_T* uart);
+void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag);
+void UART_Open(UART_T* uart, uint32_t u32baudrate);
+uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
+void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
+uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
+
+
+
+
+/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group UART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__NU_UART_H__*/
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usbd.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usbd.h
new file mode 100644
index 00000000000..cc03314b85e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usbd.h
@@ -0,0 +1,693 @@
+/**************************************************************************//**
+ * @file nu_usbd.h
+ * @version V1.00
+ * @brief M480 series USB driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_USBD_H__
+#define __NU_USBD_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup USBD_Driver USBD Driver
+ @{
+*/
+
+/** @addtogroup USBD_EXPORTED_STRUCT USBD Exported Struct
+ @{
+*/
+typedef struct s_usbd_info
+{
+ uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */
+ uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */
+ uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */
+ uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */
+ uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */
+ uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */
+ uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */
+
+} S_USBD_INFO_T; /*!< Device description structure */
+
+extern const S_USBD_INFO_T gsInfo;
+
+/*@}*/ /* end of group USBD_EXPORTED_STRUCT */
+
+
+
+
+/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants
+ @{
+*/
+#define USBD_BUF_BASE (USBD_BASE+0x100ul) /*!< USBD buffer base address \hideinitializer */
+#define USBD_MAX_EP 12ul /*!< Total EP number \hideinitializer */
+
+#define EP0 0ul /*!< Endpoint 0 \hideinitializer */
+#define EP1 1ul /*!< Endpoint 1 \hideinitializer */
+#define EP2 2ul /*!< Endpoint 2 \hideinitializer */
+#define EP3 3ul /*!< Endpoint 3 \hideinitializer */
+#define EP4 4ul /*!< Endpoint 4 \hideinitializer */
+#define EP5 5ul /*!< Endpoint 5 \hideinitializer */
+#define EP6 6ul /*!< Endpoint 6 \hideinitializer */
+#define EP7 7ul /*!< Endpoint 7 \hideinitializer */
+#define EP8 8ul /*!< Endpoint 8 \hideinitializer */
+#define EP9 9ul /*!< Endpoint 9 \hideinitializer */
+#define EP10 10ul /*!< Endpoint 10 \hideinitializer */
+#define EP11 11ul /*!< Endpoint 11 \hideinitializer */
+
+/** @cond HIDDEN_SYMBOLS */
+/* USB Request Type */
+#define REQ_STANDARD 0x00ul
+#define REQ_CLASS 0x20ul
+#define REQ_VENDOR 0x40ul
+
+/* USB Standard Request */
+#define GET_STATUS 0x00ul
+#define CLEAR_FEATURE 0x01ul
+#define SET_FEATURE 0x03ul
+#define SET_ADDRESS 0x05ul
+#define GET_DESCRIPTOR 0x06ul
+#define SET_DESCRIPTOR 0x07ul
+#define GET_CONFIGURATION 0x08ul
+#define SET_CONFIGURATION 0x09ul
+#define GET_INTERFACE 0x0Aul
+#define SET_INTERFACE 0x0Bul
+#define SYNC_FRAME 0x0Cul
+
+/* USB Descriptor Type */
+#define DESC_DEVICE 0x01ul
+#define DESC_CONFIG 0x02ul
+#define DESC_STRING 0x03ul
+#define DESC_INTERFACE 0x04ul
+#define DESC_ENDPOINT 0x05ul
+#define DESC_QUALIFIER 0x06ul
+#define DESC_OTHERSPEED 0x07ul
+#define DESC_IFPOWER 0x08ul
+#define DESC_OTG 0x09ul
+#define DESC_BOS 0x0Ful
+#define DESC_CAPABILITY 0x10ul
+
+/* USB Device Capability Type */
+#define CAP_WIRELESS 0x01ul
+#define CAP_USB20_EXT 0x02ul
+
+/* USB HID Descriptor Type */
+#define DESC_HID 0x21ul
+#define DESC_HID_RPT 0x22ul
+
+/* USB Descriptor Length */
+#define LEN_DEVICE 18ul
+#define LEN_QUALIFIER 10ul
+#define LEN_CONFIG 9ul
+#define LEN_INTERFACE 9ul
+#define LEN_ENDPOINT 7ul
+#define LEN_OTG 5ul
+#define LEN_BOS 5ul
+#define LEN_HID 9ul
+#define LEN_CCID 0x36ul
+#define LEN_BOSCAP 7ul
+
+/* USB Endpoint Type */
+#define EP_ISO 0x01
+#define EP_BULK 0x02
+#define EP_INT 0x03
+
+#define EP_INPUT 0x80
+#define EP_OUTPUT 0x00
+
+/* USB Feature Selector */
+#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01ul
+#define FEATURE_ENDPOINT_HALT 0x00ul
+/** @endcond HIDDEN_SYMBOLS */
+
+/******************************************************************************/
+/* USB Specific Macros */
+/******************************************************************************/
+
+#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable \hideinitializer */
+#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 \hideinitializer */
+
+#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable \hideinitializer */
+#define USBD_PWRDN USBD_ATTR_PWRDN_Msk /*!< PHY Turn-On \hideinitializer */
+#define USBD_PHY_EN USBD_ATTR_PHYEN_Msk /*!< PHY Enable \hideinitializer */
+#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable \hideinitializer */
+
+#define USBD_INT_BUS USBD_INTEN_BUSIEN_Msk /*!< USB Bus Event Interrupt \hideinitializer */
+#define USBD_INT_USB USBD_INTEN_USBIEN_Msk /*!< USB Event Interrupt \hideinitializer */
+#define USBD_INT_FLDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt \hideinitializer */
+#define USBD_INT_WAKEUP (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk) /*!< USB No-Event-Wake-Up Interrupt \hideinitializer */
+
+#define USBD_INTSTS_WAKEUP USBD_INTSTS_NEVWKIF_Msk /*!< USB No-Event-Wake-Up Interrupt Status \hideinitializer */
+#define USBD_INTSTS_FLDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status \hideinitializer */
+#define USBD_INTSTS_BUS USBD_INTSTS_BUSIF_Msk /*!< USB Bus Event Interrupt Status \hideinitializer */
+#define USBD_INTSTS_USB USBD_INTSTS_USBIF_Msk /*!< USB Event Interrupt Status \hideinitializer */
+#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event \hideinitializer */
+#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event \hideinitializer */
+#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event \hideinitializer */
+#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event \hideinitializer */
+#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event \hideinitializer */
+#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event \hideinitializer */
+#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event \hideinitializer */
+#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event \hideinitializer */
+#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event \hideinitializer */
+#define USBD_INTSTS_EP8 USBD_INTSTS_EPEVT8_Msk /*!< USB Endpoint 8 Event \hideinitializer */
+#define USBD_INTSTS_EP9 USBD_INTSTS_EPEVT9_Msk /*!< USB Endpoint 9 Event \hideinitializer */
+#define USBD_INTSTS_EP10 USBD_INTSTS_EPEVT10_Msk /*!< USB Endpoint 10 Event \hideinitializer */
+#define USBD_INTSTS_EP11 USBD_INTSTS_EPEVT11_Msk /*!< USB Endpoint 11 Event \hideinitializer */
+
+#define USBD_STATE_USBRST USBD_ATTR_USBRST_Msk /*!< USB Bus Reset \hideinitializer */
+#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend \hideinitializer */
+#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume \hideinitializer */
+#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout \hideinitializer */
+
+#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall \hideinitializer */
+#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall \hideinitializer */
+
+#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos)/*!< Endpoint Disable \hideinitializer */
+#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_STATE_Pos)/*!< Out Endpoint \hideinitializer */
+#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_STATE_Pos)/*!< In Endpoint \hideinitializer */
+#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous \hideinitializer */
+
+
+
+/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+ @{
+*/
+/**
+ * @brief Compare two input numbers and return maximum one.
+ *
+ * @param[in] a First number to be compared.
+ * @param[in] b Second number to be compared.
+ *
+ * @return Maximum value between a and b.
+ *
+ * @details If a > b, then return a. Otherwise, return b.
+ * \hideinitializer
+ */
+#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b))
+
+
+/**
+ * @brief Compare two input numbers and return minimum one
+ *
+ * @param[in] a First number to be compared
+ * @param[in] b Second number to be compared
+ *
+ * @return Minimum value between a and b
+ *
+ * @details If a < b, then return a. Otherwise, return b.
+ * \hideinitializer
+ */
+#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b))
+
+
+/**
+ * @brief Enable USB
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details To set USB ATTR control register to enable USB and PHY.
+ * \hideinitializer
+ */
+#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= 0x7D0))
+
+/**
+ * @brief Disable USB
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details To set USB ATTR control register to disable USB.
+ * \hideinitializer
+ */
+#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))
+
+/**
+ * @brief Enable USB PHY
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details To set USB ATTR control register to enable USB PHY.
+ * \hideinitializer
+ */
+#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN))
+
+/**
+ * @brief Disable USB PHY
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details To set USB ATTR control register to disable USB PHY.
+ * \hideinitializer
+ */
+#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))
+
+/**
+ * @brief Enable SE0. Force USB PHY transceiver to drive SE0.
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus.
+ * \hideinitializer
+ */
+#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0))
+
+/**
+ * @brief Disable SE0
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function.
+ * \hideinitializer
+ */
+#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))
+
+/**
+ * @brief Set USB device address
+ *
+ * @param[in] addr The USB device address.
+ *
+ * @return None
+ *
+ * @details Write USB device address to USB_FADDR register.
+ * \hideinitializer
+ */
+#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr))
+
+/**
+ * @brief Get USB device address
+ *
+ * @param None
+ *
+ * @return USB device address
+ *
+ * @details Read USB_FADDR register to get USB device address.
+ * \hideinitializer
+ */
+#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR))
+
+/**
+ * @brief Enable USB interrupt function
+ *
+ * @param[in] intr The combination of the specified interrupt enable bits.
+ * Each bit corresponds to a interrupt enable bit.
+ * This parameter decides which interrupts will be enabled.
+ * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS)
+ *
+ * @return None
+ *
+ * @details Enable USB related interrupt functions specified by intr parameter.
+ * \hideinitializer
+ */
+#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr))
+
+/**
+ * @brief Get interrupt status
+ *
+ * @param None
+ *
+ * @return The value of USB_INTSTS register
+ *
+ * @details Return all interrupt flags of USB_INTSTS register.
+ * \hideinitializer
+ */
+#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS))
+
+/**
+ * @brief Clear USB interrupt flag
+ *
+ * @param[in] flag The combination of the specified interrupt flags.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be cleared.
+ * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB)
+ *
+ * @return None
+ *
+ * @details Clear USB related interrupt flags specified by flag parameter.
+ * \hideinitializer
+ */
+#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag))
+
+/**
+ * @brief Get endpoint status
+ *
+ * @param None
+ *
+ * @return The value of USB_EPSTS register.
+ *
+ * @details Return all endpoint status.
+ * \hideinitializer
+ */
+#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS))
+
+/**
+ * @brief Get USB bus state
+ *
+ * @param None
+ *
+ * @return The value of USB_ATTR[3:0].
+ * Bit 0 indicates USB bus reset status.
+ * Bit 1 indicates USB bus suspend status.
+ * Bit 2 indicates USB bus resume status.
+ * Bit 3 indicates USB bus time-out status.
+ *
+ * @details Return USB_ATTR[3:0] for USB bus events.
+ * \hideinitializer
+ */
+#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0xf))
+
+/**
+ * @brief Check cable connection state
+ *
+ * @param None
+ *
+ * @retval 0 USB cable is not attached.
+ * @retval 1 USB cable is attached.
+ *
+ * @details Check the connection state by FLDET bit of USB_FLDET register.
+ * \hideinitializer
+ */
+#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))
+
+/**
+ * @brief Stop USB transaction of the specified endpoint ID
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @return None
+ *
+ * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID.
+ * \hideinitializer
+ */
+#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)
+
+/**
+ * @brief Set USB DATA1 PID for the specified endpoint ID
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @return None
+ *
+ * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction.
+ * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
+ * \hideinitializer
+ */
+#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)
+
+/**
+ * @brief Set USB DATA0 PID for the specified endpoint ID
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @return None
+ *
+ * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction.
+ * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
+ * \hideinitializer
+ */
+#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))
+
+/**
+ * @brief Set USB payload size (IN data)
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @param[in] size The transfer length.
+ *
+ * @return None
+ *
+ * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction.
+ * \hideinitializer
+ */
+#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
+
+/**
+ * @brief Get USB payload size (OUT data)
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @return The value of USB_MXPLDx register.
+ *
+ * @details Get the data length of OUT data transaction by reading USB_MXPLDx register.
+ * \hideinitializer
+ */
+#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))
+
+/**
+ * @brief Configure endpoint
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @param[in] config The USB configuration.
+ *
+ * @return None
+ *
+ * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID.
+ * \hideinitializer
+ */
+#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
+
+/**
+ * @brief Set USB endpoint buffer
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @param[in] offset The SRAM offset.
+ *
+ * @return None
+ *
+ * @details This macro will set the SRAM offset for the specified endpoint ID.
+ * \hideinitializer
+ */
+#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
+
+/**
+ * @brief Get the offset of the specified USB endpoint buffer
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @return The offset of the specified endpoint buffer.
+ *
+ * @details This macro will return the SRAM offset of the specified endpoint ID.
+ * \hideinitializer
+ */
+#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
+
+/**
+ * @brief Set USB endpoint stall state
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @return None
+ *
+ * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
+ * \hideinitializer
+ */
+#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0ul].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)
+
+/**
+ * @brief Clear USB endpoint stall state
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @return None
+ *
+ * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
+ * \hideinitializer
+ */
+#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)
+
+/**
+ * @brief Get USB endpoint stall state
+ *
+ * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+ *
+ * @retval 0 USB endpoint is not stalled.
+ * @retval Others USB endpoint is stalled.
+ *
+ * @details Get USB endpoint stall state of the specified endpoint ID.
+ * \hideinitializer
+ */
+#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)
+
+/**
+ * @brief To support byte access between USB SRAM and system SRAM
+ *
+ * @param[in] dest Destination pointer.
+ *
+ * @param[in] src Source pointer.
+ *
+ * @param[in] size Byte count.
+ *
+ * @return None
+ *
+ * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
+ *
+ */
+__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size)
+{
+ uint32_t volatile i=0ul;
+
+ while(size--)
+ {
+ dest[i] = src[i];
+ i++;
+ }
+}
+
+/**
+ * @brief Set USB endpoint stall state
+ *
+ * @param[in] epnum USB endpoint number
+ *
+ * @return None
+ *
+ * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically.
+ *
+ */
+__STATIC_INLINE void USBD_SetStall(uint8_t epnum)
+{
+ uint32_t u32CfgAddr;
+ uint32_t u32Cfg;
+ uint32_t i;
+
+ for(i = 0ul; i < USBD_MAX_EP; i++)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+ if((u32Cfg & 0xful) == epnum)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+ *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Clear USB endpoint stall state
+ *
+ * @param[in] epnum USB endpoint number
+ *
+ * @return None
+ *
+ * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token.
+ */
+__STATIC_INLINE void USBD_ClearStall(uint8_t epnum)
+{
+ uint32_t u32CfgAddr;
+ uint32_t u32Cfg;
+ uint32_t i;
+
+ for(i = 0ul; i < USBD_MAX_EP; i++)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+ if((u32Cfg & 0xful) == epnum)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+ *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Get USB endpoint stall state
+ *
+ * @param[in] epnum USB endpoint number
+ *
+ * @retval 0 USB endpoint is not stalled.
+ * @retval Others USB endpoint is stalled.
+ *
+ * @details Get USB endpoint stall state.
+ *
+ */
+__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum)
+{
+ uint32_t u32CfgAddr;
+ uint32_t u32Cfg;
+ uint32_t i;
+
+ for(i = 0ul; i < USBD_MAX_EP; i++)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+ if((u32Cfg & 0xful) == epnum)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+ break;
+ }
+ }
+
+ return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
+}
+
+
+extern volatile uint8_t g_usbd_RemoteWakeupEn;
+
+
+typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */
+typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */
+typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */
+typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */
+
+
+/*--------------------------------------------------------------------*/
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
+void USBD_Start(void);
+void USBD_GetSetupPacket(uint8_t *buf);
+void USBD_ProcessSetupPacket(void);
+void USBD_StandardRequest(void);
+void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size);
+void USBD_CtrlIn(void);
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_CtrlOut(void);
+void USBD_SwReset(void);
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);
+void USBD_LockEpStall(uint32_t u32EpBitmap);
+
+/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USBD_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__NU_USBD_H__*/
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_i2c.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_i2c.h
new file mode 100644
index 00000000000..55508d5e77e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_i2c.h
@@ -0,0 +1,332 @@
+/**************************************************************************//**
+ * @file USCI_I2C.h
+ * @version V3.0
+ * @brief M480 series USCI I2C(UI2C) driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_USCI_I2C_H__
+#define __NU_USCI_I2C_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup USCI_I2C_Driver USCI_I2C Driver
+ @{
+*/
+
+/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C master event definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+enum UI2C_MASTER_EVENT
+{
+ MASTER_SEND_ADDRESS = 10, /*!< Master send address to Slave */
+ MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */
+ MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */
+ MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */
+ MASTER_SEND_DATA, /*!< Master Send Data to Slave */
+ MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */
+ MASTER_READ_DATA, /*!< Master Get Data from Slave */
+ MASTER_STOP, /*!< Master send stop to Slave */
+ MASTER_SEND_START /*!< Master send start to Slave */
+};
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C slave event definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+enum UI2C_SLAVE_EVENT
+{
+ SLAVE_ADDRESS_ACK = 100, /*!< Slave send address ACK */
+ SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */
+ SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */
+ SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */
+ SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */
+ SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */
+ SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */
+};
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_CTL constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_CTL_PTRG 0x20UL /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit \hideinitializer */
+#define UI2C_CTL_STA 0x08UL /*!< USCI_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
+#define UI2C_CTL_STO 0x04UL /*!< USCI_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
+#define UI2C_CTL_AA 0x02UL /*!< USCI_CTL setting for I2C control bits. It would set AA bit \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C GCMode constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode \hideinitializer */
+#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C Wakeup Mode constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle \hideinitializer */
+#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C interrupt mask definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask \hideinitializer */
+#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask \hideinitializer */
+#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask \hideinitializer */
+#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask \hideinitializer */
+#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask \hideinitializer */
+#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask \hideinitializer */
+#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask \hideinitializer */
+
+/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions
+ @{
+*/
+
+/**
+ * @brief This macro sets the USCI_I2C protocol control register at one time
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8Ctrl Set the register value of USCI_I2C control register.
+ *
+ * @return None
+ *
+ * @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, SI, ACK.
+ * \hideinitializer
+ */
+#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl))
+
+/**
+ * @brief This macro only set START bit to protocol control register of USCI_I2C module.
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register.
+ * \hideinitializer
+ */
+#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk)
+
+/**
+ * @brief This macro only set STOP bit to the control register of USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register.
+ * \hideinitializer
+ */
+#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk))
+
+/**
+ * @brief This macro returns the data stored in data register of USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return Data
+ *
+ * @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus
+ * \hideinitializer
+ */
+#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT)
+
+/**
+ * @brief This macro writes the data to data register of USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8Data The data which will be written to data register of USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus
+ * \hideinitializer
+ */
+#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data))
+
+/**
+ * @brief This macro returns time-out flag
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @retval 0 USCI_I2C bus time-out is not happened
+ * @retval 1 USCI_I2C bus time-out is happened
+ *
+ * @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared.
+ * \hideinitializer
+ */
+#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0)
+
+/**
+ * @brief This macro returns wake-up flag
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @retval 0 Chip is not woken-up from power-down mode
+ * @retval 1 Chip is woken-up from power-down mode
+ *
+ * @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep.
+ * \hideinitializer
+ */
+#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0)
+
+/**
+ * @brief This macro is used to clear USCI_I2C wake-up flag
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details If USCI_I2C wake-up flag is set, use this macro to clear it.
+ * \hideinitializer
+ */
+#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk)
+
+/**
+ * @brief This macro disables the USCI_I2C 10-bit address mode
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function.
+ * \hideinitializer
+ */
+#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk))
+
+/**
+ * @brief This macro enables the 10-bit address mode
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details To enable USCI_I2C 10-bit address match function.
+ * \hideinitializer
+ */
+#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk)
+
+/**
+ * @brief This macro gets USCI_I2C protocol interrupt flag or bus status
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return A word data of USCI_I2C_PROTSTS register
+ *
+ * @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status.
+ * \hideinitializer
+ */
+#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS)
+
+/**
+ * @brief This macro clears specified protocol interrupt flag
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u32IntTypeFlag Interrupt Type Flag, should be
+ * - \ref UI2C_PROTSTS_ACKIF_Msk
+ * - \ref UI2C_PROTSTS_ERRIF_Msk
+ * - \ref UI2C_PROTSTS_ARBLOIF_Msk
+ * - \ref UI2C_PROTSTS_NACKIF_Msk
+ * - \ref UI2C_PROTSTS_STORIF_Msk
+ * - \ref UI2C_PROTSTS_STARIF_Msk
+ * - \ref UI2C_PROTSTS_TOIF_Msk
+ * @return None
+ *
+ * @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag.
+ * \hideinitializer
+ */
+#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag))
+
+/**
+ * @brief This macro enables specified protocol interrupt
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u32IntSel Interrupt Type, should be
+ * - \ref UI2C_PROTIEN_ACKIEN_Msk
+ * - \ref UI2C_PROTIEN_ERRIEN_Msk
+ * - \ref UI2C_PROTIEN_ARBLOIEN_Msk
+ * - \ref UI2C_PROTIEN_NACKIEN_Msk
+ * - \ref UI2C_PROTIEN_STORIEN_Msk
+ * - \ref UI2C_PROTIEN_STARIEN_Msk
+ * - \ref UI2C_PROTIEN_TOIEN_Msk
+ * @return None
+ *
+ * @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function.
+ * \hideinitializer
+ */
+#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel))
+
+/**
+ * @brief This macro disables specified protocol interrupt
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u32IntSel Interrupt Type, should be
+ * - \ref UI2C_PROTIEN_ACKIEN_Msk
+ * - \ref UI2C_PROTIEN_ERRIEN_Msk
+ * - \ref UI2C_PROTIEN_ARBLOIEN_Msk
+ * - \ref UI2C_PROTIEN_NACKIEN_Msk
+ * - \ref UI2C_PROTIEN_STORIEN_Msk
+ * - \ref UI2C_PROTIEN_STARIEN_Msk
+ * - \ref UI2C_PROTIEN_TOIEN_Msk
+ * @return None
+ *
+ * @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt function.
+ * \hideinitializer
+ */
+#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel))
+
+
+uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock);
+void UI2C_Close(UI2C_T *ui2c);
+void UI2C_ClearTimeoutFlag(UI2C_T *ui2c);
+void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack);
+void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask);
+void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask);
+uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c);
+uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock);
+uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask);
+void UI2C_ClearIntFlag(UI2C_T* ui2c, uint32_t u32Mask);
+uint32_t UI2C_GetData(UI2C_T *ui2c);
+void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data);
+void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode);
+void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask);
+void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt);
+void UI2C_DisableTimeout(UI2C_T *ui2c);
+void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode);
+void UI2C_DisableWakeup(UI2C_T *ui2c);
+uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data);
+uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen);
+uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
+uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen);
+uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
+uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen);
+uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr);
+uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen);
+uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
+uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen);
+uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
+uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen);
+
+/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USCI_I2C_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h
new file mode 100644
index 00000000000..68d4e02a897
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h
@@ -0,0 +1,411 @@
+/****************************************************************************//**
+ * @file nu_usci_spi.h
+ * @version V3.00
+ * @brief M480 series USCI_SPI driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_USCI_SPI_H__
+#define __NU_USCI_SPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup USCI_SPI_Driver USCI_SPI Driver
+ @{
+*/
+
+/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants
+ @{
+*/
+
+#define USPI_MODE_0 (0x0 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge \hideinitializer */
+#define USPI_MODE_1 (0x1 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge \hideinitializer */
+#define USPI_MODE_2 (0x2 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge \hideinitializer */
+#define USPI_MODE_3 (0x3 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge \hideinitializer */
+
+#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
+#define USPI_MASTER (0x0ul) /*!< Set as master \hideinitializer */
+
+#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS \hideinitializer */
+#define USPI_SS_ACTIVE_HIGH (0x0ul) /*!< SS active high \hideinitializer */
+#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low \hideinitializer */
+
+/* USCI_SPI Interrupt Mask */
+#define USPI_SSINACT_INT_MASK (0x001ul) /*!< Slave Slave Inactive interrupt mask \hideinitializer */
+#define USPI_SSACT_INT_MASK (0x002ul) /*!< Slave Slave Active interrupt mask \hideinitializer */
+#define USPI_SLVTO_INT_MASK (0x004ul) /*!< Slave Mode Time-out interrupt mask \hideinitializer */
+#define USPI_SLVBE_INT_MASK (0x008ul) /*!< Slave Mode Bit Count Error interrupt mask \hideinitializer */
+#define USPI_TXUDR_INT_MASK (0x010ul) /*!< Slave Transmit Under Run interrupt mask \hideinitializer */
+#define USPI_RXOV_INT_MASK (0x020ul) /*!< Receive Buffer Overrun interrupt mask \hideinitializer */
+#define USPI_TXST_INT_MASK (0x040ul) /*!< Transmit Start interrupt mask \hideinitializer */
+#define USPI_TXEND_INT_MASK (0x080ul) /*!< Transmit End interrupt mask \hideinitializer */
+#define USPI_RXST_INT_MASK (0x100ul) /*!< Receive Start interrupt mask \hideinitializer */
+#define USPI_RXEND_INT_MASK (0x200ul) /*!< Receive End interrupt mask \hideinitializer */
+
+/* USCI_SPI Status Mask */
+#define USPI_BUSY_MASK (0x01ul) /*!< Busy status mask \hideinitializer */
+#define USPI_RX_EMPTY_MASK (0x02ul) /*!< RX empty status mask \hideinitializer */
+#define USPI_RX_FULL_MASK (0x04ul) /*!< RX full status mask \hideinitializer */
+#define USPI_TX_EMPTY_MASK (0x08ul) /*!< TX empty status mask \hideinitializer */
+#define USPI_TX_FULL_MASK (0x10ul) /*!< TX full status mask \hideinitializer */
+#define USPI_SSLINE_STS_MASK (0x20ul) /*!< USCI_SPI_SS line status mask \hideinitializer */
+
+/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Disable slave 3-wire mode.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk )
+
+/**
+ * @brief Enable slave 3-wire mode.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk )
+
+/**
+ * @brief Get the Rx buffer empty flag.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return Rx buffer flag
+ * @retval 0: Rx buffer is not empty
+ * @retval 1: Rx buffer is empty
+ * \hideinitializer
+ */
+#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 )
+
+/**
+ * @brief Get the Tx buffer empty flag.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return Tx buffer flag
+ * @retval 0: Tx buffer is not empty
+ * @retval 1: Tx buffer is empty
+ * \hideinitializer
+ */
+#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 )
+
+/**
+ * @brief Get the Tx buffer full flag.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return Tx buffer flag
+ * @retval 0: Tx buffer is not full
+ * @retval 1: Tx buffer is full
+ * \hideinitializer
+ */
+#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 )
+
+/**
+ * @brief Get the datum read from RX register.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return data in Rx register
+ * \hideinitializer
+ */
+#define USPI_READ_RX(uspi) ((uspi)->RXDAT)
+
+/**
+ * @brief Write datum to TX register.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus.
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) )
+
+/**
+ * @brief Set USCI_SPI_SS pin to high state.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode.
+ * \hideinitializer
+ */
+#define USPI_SET_SS_HIGH(uspi) \
+ do{ \
+ (uspi)->LINECTL &= ~(USPI_LINECTL_CTLOINV_Msk); \
+ (uspi)->PROTCTL = ((uspi)->PROTCTL & ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk)); \
+ }while(0)
+
+/**
+ * @brief Set USCI_SPI_SS pin to low state.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode.
+ * \hideinitializer
+ */
+#define USPI_SET_SS_LOW(uspi) \
+ do{ \
+ (uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \
+ (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \
+ }while(0)
+
+/**
+ * @brief Set the length of suspend interval.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32SuspCycle Decide the length of suspend interval.
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) )
+
+/**
+ * @brief Set the USCI_SPI transfer sequence with LSB first.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk )
+
+/**
+ * @brief Set the USCI_SPI transfer sequence with MSB first.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk )
+
+/**
+ * @brief Set the data width of a USCI_SPI transaction.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32Width The data width
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_SET_DATA_WIDTH(uspi,u32Width) \
+ do{ \
+ if((u32Width) == 16ul){ \
+ (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \
+ }else { \
+ (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \
+ } \
+ }while(0)
+
+/**
+ * @brief Get the USCI_SPI busy state.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return USCI_SPI busy status
+ * @retval 0: USCI_SPI module is not busy
+ * @retval 1: USCI_SPI module is busy
+ * \hideinitializer
+ */
+#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 )
+
+/**
+ * @brief Get the USCI_SPI wakeup flag.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return Wakeup status.
+ * @retval 0 Flag is not set.
+ * @retval 1 Flag is set.
+ * \hideinitializer
+ */
+#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0)
+
+/**
+ * @brief Clear the USCI_SPI wakeup flag.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk)
+
+/**
+ * @brief Get protocol interrupt flag/status.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return The interrupt flag/status of protocol status register.
+ * \hideinitializer
+ */
+#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS)
+
+/**
+ * @brief Clear specified protocol interrupt flag.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32IntTypeFlag Interrupt Type Flag, should be
+ * - \ref USPI_PROTSTS_SSACTIF_Msk
+ * - \ref USPI_PROTSTS_SSINAIF_Msk
+ * - \ref USPI_PROTSTS_SLVBEIF_Msk
+ * - \ref USPI_PROTSTS_SLVTOIF_Msk
+ * - \ref USPI_PROTSTS_RXENDIF_Msk
+ * - \ref USPI_PROTSTS_RXSTIF_Msk
+ * - \ref USPI_PROTSTS_TXENDIF_Msk
+ * - \ref USPI_PROTSTS_TXSTIF_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_CLR_PROT_INT_FLAG(uspi,u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag))
+
+/**
+ * @brief Get buffer interrupt flag/status.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return The interrupt flag/status of buffer status register.
+ * \hideinitializer
+ */
+#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS)
+
+/**
+ * @brief Clear specified buffer interrupt flag.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32IntTypeFlag Interrupt Type Flag, should be
+ * - \ref USPI_BUFSTS_TXUDRIF_Msk
+ * - \ref USPI_BUFSTS_RXOVIF_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_CLR_BUF_INT_FLAG(uspi,u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag))
+
+/**
+ * @brief Enable specified protocol interrupt.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32IntSel Interrupt Type, should be
+ * - \ref USPI_PROTIEN_SLVBEIEN_Msk
+ * - \ref USPI_PROTIEN_SLVTOIEN_Msk
+ * - \ref USPI_PROTIEN_SSACTIEN_Msk
+ * - \ref USPI_PROTIEN_SSINAIEN_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ((uspi)->PROTIEN |= (u32IntSel))
+
+/**
+ * @brief Disable specified protocol interrupt.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32IntSel Interrupt Type, should be
+ * - \ref USPI_PROTIEN_SLVBEIEN_Msk
+ * - \ref USPI_PROTIEN_SLVTOIEN_Msk
+ * - \ref USPI_PROTIEN_SSACTIEN_Msk
+ * - \ref USPI_PROTIEN_SSINAIEN_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ((uspi)->PROTIEN &= ~ (u32IntSel))
+
+/**
+ * @brief Enable specified buffer interrupt.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32IntSel Interrupt Type, should be
+ * - \ref USPI_BUFCTL_RXOVIEN_Msk
+ * - \ref USPI_BUFCTL_TXUDRIEN_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ((uspi)->BUFCTL |= (u32IntSel))
+
+/**
+ * @brief Disable specified buffer interrupt.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32IntSel Interrupt Type, should be
+ * - \ref USPI_BUFCTL_RXOVIEN_Msk
+ * - \ref USPI_BUFCTL_TXUDRIEN_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ((uspi)->BUFCTL &= ~ (u32IntSel))
+
+/**
+ * @brief Enable specified transfer interrupt.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32IntSel Interrupt Type, should be
+ * - \ref USPI_INTEN_RXENDIEN_Msk
+ * - \ref USPI_INTEN_RXSTIEN_Msk
+ * - \ref USPI_INTEN_TXENDIEN_Msk
+ * - \ref USPI_INTEN_TXSTIEN_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ((uspi)->INTEN |= (u32IntSel))
+
+/**
+ * @brief Disable specified transfer interrupt.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32IntSel Interrupt Type, should be
+ * - \ref USPI_INTEN_RXENDIEN_Msk
+ * - \ref USPI_INTEN_RXSTIEN_Msk
+ * - \ref USPI_INTEN_TXENDIEN_Msk
+ * - \ref USPI_INTEN_TXSTIEN_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ((uspi)->INTEN &= ~ (u32IntSel))
+
+
+/**
+ * @brief Trigger RX PDMA function.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None.
+ * @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function.
+ * \hideinitializer
+ */
+#define USPI_TRIGGER_RX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
+
+/**
+ * @brief Trigger TX PDMA function.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None.
+ * @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function.
+ * \hideinitializer
+ */
+#define USPI_TRIGGER_TX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
+
+/**
+ * @brief Disable RX PDMA transfer.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None.
+ * @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function.
+ * \hideinitializer
+ */
+#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Disable TX PDMA transfer.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None.
+ * @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function.
+ * \hideinitializer
+ */
+#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk )
+
+uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void USPI_Close(USPI_T *uspi);
+void USPI_ClearRxBuf(USPI_T *uspi);
+void USPI_ClearTxBuf(USPI_T *uspi);
+void USPI_DisableAutoSS(USPI_T *uspi);
+void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock);
+uint32_t USPI_GetBusClock(USPI_T *uspi);
+void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask);
+void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask);
+uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask);
+void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask);
+uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask);
+void USPI_EnableWakeup(USPI_T *uspi);
+void USPI_DisableWakeup(USPI_T *uspi);
+
+
+/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USCI_SPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_USCI_SPI_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_uart.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_uart.h
new file mode 100644
index 00000000000..e1402a19115
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_uart.h
@@ -0,0 +1,520 @@
+/**************************************************************************//**
+ * @file nu_usci_uart.h
+ * @version V3.00
+ * @brief M480 series USCI UART (UUART) driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_USCI_UART_H__
+#define __NU_USCI_UART_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup USCI_UART_Driver USCI_UART Driver
+ @{
+*/
+
+/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UUART_LINECTL constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UUART_WORD_LEN_6 (6ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits \hideinitializer */
+#define UUART_WORD_LEN_7 (7ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits \hideinitializer */
+#define UUART_WORD_LEN_8 (8ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits \hideinitializer */
+#define UUART_WORD_LEN_9 (9ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UUART_PROTCTL constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UUART_PARITY_NONE (0x0ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity \hideinitializer */
+#define UUART_PARITY_ODD (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity \hideinitializer */
+#define UUART_PARITY_EVEN (0x3ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity \hideinitializer */
+
+#define UUART_STOP_BIT_1 (0x0ul) /*!< UUART_PROTCTL setting for one stop bit \hideinitializer */
+#define UUART_STOP_BIT_2 (0x1ul) /*!< UUART_PROTCTL setting for two stop bit \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI UART interrupt mask definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UUART_ABR_INT_MASK (0x002ul) /*!< Auto-baud rate interrupt mask \hideinitializer */
+#define UUART_RLS_INT_MASK (0x004ul) /*!< Receive line status interrupt mask \hideinitializer */
+#define UUART_BUF_RXOV_INT_MASK (0x008ul) /*!< Buffer RX overrun interrupt mask \hideinitializer */
+#define UUART_TXST_INT_MASK (0x010ul) /*!< TX start interrupt mask \hideinitializer */
+#define UUART_TXEND_INT_MASK (0x020ul) /*!< Tx end interrupt mask \hideinitializer */
+#define UUART_RXST_INT_MASK (0x040ul) /*!< RX start interrupt mask \hideinitializer */
+#define UUART_RXEND_INT_MASK (0x080ul) /*!< RX end interrupt mask \hideinitializer */
+
+
+/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Write USCI_UART data
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u8Data Data byte to transmit.
+ *
+ * @return None
+ *
+ * @details This macro write Data to Tx data register.
+ * \hideinitializer
+ */
+#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data))
+
+
+/**
+ * @brief Read USCI_UART data
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @return The oldest data byte in RX buffer.
+ *
+ * @details This macro read Rx data register.
+ * \hideinitializer
+ */
+#define UUART_READ(uuart) ((uuart)->RXDAT)
+
+
+/**
+ * @brief Get Tx empty
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @retval 0 Tx buffer is not empty
+ * @retval >=1 Tx buffer is empty
+ *
+ * @details This macro get Transmitter buffer empty register value.
+ * \hideinitializer
+ */
+#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk)
+
+
+/**
+ * @brief Get Rx empty
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @retval 0 Rx buffer is not empty
+ * @retval >=1 Rx buffer is empty
+ *
+ * @details This macro get Receiver buffer empty register value.
+ * \hideinitializer
+ */
+#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk)
+
+
+/**
+ * @brief Check specified usci_uart port transmission is over.
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @retval 0 Tx transmission is not over
+ * @retval 1 Tx transmission is over
+ *
+ * @details This macro return Transmitter Empty Flag register bit value. \n
+ * It indicates if specified usci_uart port transmission is over nor not.
+ * \hideinitializer
+ */
+#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)
+
+
+/**
+ * @brief Check specified usci_uart port receiver is empty.
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @retval 0 Rx receiver is not empty
+ * @retval 1 Rx receiver is empty
+ *
+ * @details This macro return Receive Empty Flag register bit value. \n
+ * It indicates if specified usci_uart port receiver is empty nor not.
+ * \hideinitializer
+ */
+#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos)
+
+
+/**
+ * @brief Wait specified usci_uart port transmission is over
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @return None
+ *
+ * @details This macro wait specified usci_uart port transmission is over.
+ * \hideinitializer
+ */
+#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos))
+
+
+/**
+ * @brief Check TX buffer is full or not
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @retval 1 TX buffer is full
+ * @retval 0 TX buffer is not full
+ *
+ * @details This macro check TX buffer is full or not.
+ * \hideinitializer
+ */
+#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos)
+
+
+/**
+ * @brief Check RX buffer is full or not
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @retval 1 RX buffer is full
+ * @retval 0 RX buffer is not full
+ *
+ * @details This macro check RX buffer is full or not.
+ * \hideinitializer
+ */
+#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos)
+
+
+/**
+ * @brief Get Tx full register value
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @retval 0 Tx buffer is not full.
+ * @retval >=1 Tx buffer is full.
+ *
+ * @details This macro get Tx full register value.
+ * \hideinitializer
+ */
+#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)
+
+
+/**
+ * @brief Get Rx full register value
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @retval 0 Rx buffer is not full.
+ * @retval >=1 Rx buffer is full.
+ *
+ * @details This macro get Rx full register value.
+ * \hideinitializer
+ */
+#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)
+
+
+/**
+ * @brief Enable specified USCI_UART protocol interrupt
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u32IntSel Interrupt type select
+ * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt
+ * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt
+ *
+ * @return None
+ *
+ * @details This macro enable specified USCI_UART protocol interrupt.
+ * \hideinitializer
+ */
+#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel))
+
+
+/**
+ * @brief Disable specified USCI_UART protocol interrupt
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u32IntSel Interrupt type select
+ * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt
+ * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt
+ *
+ * @return None
+ *
+ * @details This macro disable specified USCI_UART protocol interrupt.
+ * \hideinitializer
+ */
+#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel))
+
+
+/**
+ * @brief Enable specified USCI_UART buffer interrupt
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u32IntSel Interrupt type select
+ * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt
+ *
+ * @return None
+ *
+ * @details This macro enable specified USCI_UART buffer interrupt.
+ * \hideinitializer
+ */
+#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel))
+
+
+/**
+ * @brief Disable specified USCI_UART buffer interrupt
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u32IntSel Interrupt type select
+ * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt
+ *
+ * @return None
+ *
+ * @details This macro disable specified USCI_UART buffer interrupt.
+ * \hideinitializer
+ */
+#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel))
+
+
+/**
+ * @brief Enable specified USCI_UART transfer interrupt
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u32IntSel Interrupt type select
+ * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt
+ * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt
+ * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt
+ * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt
+ *
+ * @return None
+ *
+ * @details This macro enable specified USCI_UART transfer interrupt.
+ * \hideinitializer
+ */
+#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel))
+
+
+/**
+ * @brief Disable specified USCI_UART transfer interrupt
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u32IntSel Interrupt type select
+ * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt
+ * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt
+ * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt
+ * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt
+ *
+ * @return None
+ *
+ * @details This macro disable specified USCI_UART transfer interrupt.
+ * \hideinitializer
+ */
+#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel))
+
+
+/**
+ * @brief Get protocol interrupt flag/status
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @return The interrupt flag/status of protocol status register.
+ *
+ * @details This macro get protocol status register value.
+ * \hideinitializer
+ */
+#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS)
+
+
+/**
+ * @brief Clear specified protocol interrupt flag
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u32IntTypeFlag Interrupt Type Flag, should be
+ * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator
+ * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag
+ * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag
+ * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag
+ * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag
+ * - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag
+ * - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag
+ * - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag
+ * - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag
+ *
+ * @return None
+ *
+ * @details This macro clear specified protocol interrupt flag.
+ * \hideinitializer
+ */
+#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag))
+
+
+/**
+ * @brief Get transmit/receive buffer interrupt flag/status
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @return The interrupt flag/status of buffer status register.
+ *
+ * @details This macro get buffer status register value.
+ * \hideinitializer
+ */
+#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS)
+
+
+/**
+ * @brief Clear specified buffer interrupt flag
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u32IntTypeFlag Interrupt Type Flag, should be
+ * - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator
+ *
+ * @return None
+ *
+ * @details This macro clear specified buffer interrupt flag.
+ * \hideinitializer
+ */
+#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag))
+
+
+/**
+ * @brief Get wakeup flag
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @retval 0 Chip did not wake up from power-down mode.
+ * @retval 1 Chip waked up from power-down mode.
+ *
+ * @details This macro get wakeup flag.
+ * \hideinitializer
+ */
+#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 )
+
+
+/**
+ * @brief Clear wakeup flag
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ *
+ * @return None
+ *
+ * @details This macro clear wakeup flag.
+ * \hideinitializer
+ */
+#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk)
+
+/**
+ * @brief Trigger RX PDMA function.
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ *
+ * @return None.
+ *
+ * @details Set RXPDMAEN bit of UUART_PDMACTL register to enable RX PDMA transfer function.
+ * \hideinitializer
+ */
+#define UUART_TRIGGER_RX_PDMA(uuart) ((uuart)->PDMACTL |= UUART_PDMACTL_RXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk)
+
+/**
+ * @brief Trigger TX PDMA function.
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ *
+ * @return None.
+ *
+ * @details Set TXPDMAEN bit of UUART_PDMACTL register to enable TX PDMA transfer function.
+ * \hideinitializer
+ */
+#define UUART_TRIGGER_TX_PDMA(uuart) ((uuart)->PDMACTL |= UUART_PDMACTL_TXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk)
+
+/**
+ * @brief Disable RX PDMA transfer.
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ *
+ * @return None.
+ *
+ * @details Clear RXPDMAEN bit of UUART_PDMACTL register to disable RX PDMA transfer function.
+ * \hideinitializer
+ */
+#define UUART_DISABLE_RX_PDMA(uuart) ( (uuart)->PDMACTL &= ~UUART_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Disable TX PDMA transfer.
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ *
+ * @return None.
+ *
+ * @details Clear TXPDMAEN bit of UUART_PDMACTL register to disable TX PDMA transfer function.
+ * \hideinitializer
+ */
+#define UUART_DISABLE_TX_PDMA(uuart) ( (uuart)->PDMACTL &= ~UUART_PDMACTL_TXPDMAEN_Msk )
+
+
+/**
+ * @brief Enable specified USCI_UART PDMA function
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u32FuncSel Combination of following functions
+ * - \ref UUART_PDMACTL_TXPDMAEN_Msk
+ * - \ref UUART_PDMACTL_RXPDMAEN_Msk
+ * - \ref UUART_PDMACTL_PDMAEN_Msk
+ *
+ * @return None
+ *
+ * \hideinitializer
+ */
+#define UUART_PDMA_ENABLE(uuart, u32FuncSel) ((uuart)->PDMACTL |= (u32FuncSel))
+
+/**
+ * @brief Disable specified USCI_UART PDMA function
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module
+ * @param[in] u32FuncSel Combination of following functions
+ * - \ref UUART_PDMACTL_TXPDMAEN_Msk
+ * - \ref UUART_PDMACTL_RXPDMAEN_Msk
+ * - \ref UUART_PDMACTL_PDMAEN_Msk
+ *
+ * @return None
+ *
+ * \hideinitializer
+ */
+#define UUART_PDMA_DISABLE(uuart, u32FuncSel) ((uuart)->PDMACTL &= ~(u32FuncSel))
+
+
+
+
+void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask);
+uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask);
+void UUART_Close(UUART_T* uuart);
+void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask);
+void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask);
+uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate);
+uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
+uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
+uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
+void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode);
+void UUART_DisableWakeup(UUART_T* uuart);
+void UUART_EnableFlowCtrl(UUART_T* uuart);
+void UUART_DisableFlowCtrl(UUART_T* uuart);
+
+
+/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USCI_UART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_USCI_UART_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wdt.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wdt.h
new file mode 100644
index 00000000000..634d73f8028
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wdt.h
@@ -0,0 +1,216 @@
+/**************************************************************************//**
+ * @file nu_wdt.h
+ * @version V3.00
+ * @brief M480 series WDT driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_WDT_H__
+#define __NU_WDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+ @{
+*/
+
+/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* WDT Time-out Interval Period Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* WDT Reset Delay Period Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */
+#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */
+#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */
+#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* WDT Free Reset Counter Keyword Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */
+
+/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear WDT Reset System Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro clears WDT time-out reset system flag.
+ * \hideinitializer
+ */
+#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
+
+/**
+ * @brief Clear WDT Time-out Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro clears WDT time-out interrupt flag.
+ * \hideinitializer
+ */
+#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
+
+/**
+ * @brief Clear WDT Wake-up Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro clears WDT time-out wake-up system flag.
+ * \hideinitializer
+ */
+#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
+
+/**
+ * @brief Get WDT Time-out Reset Flag
+ *
+ * @param None
+ *
+ * @retval 0 WDT time-out reset system did not occur
+ * @retval 1 WDT time-out reset system occurred
+ *
+ * @details This macro indicates system has been reset by WDT time-out reset or not.
+ * \hideinitializer
+ */
+#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL)
+
+/**
+ * @brief Get WDT Time-out Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 WDT time-out interrupt did not occur
+ * @retval 1 WDT time-out interrupt occurred
+ *
+ * @details This macro indicates WDT time-out interrupt occurred or not.
+ * \hideinitializer
+ */
+#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL)
+
+/**
+ * @brief Get WDT Time-out Wake-up Flag
+ *
+ * @param None
+ *
+ * @retval 0 WDT time-out interrupt does not cause CPU wake-up
+ * @retval 1 WDT time-out interrupt event cause CPU wake-up
+ *
+ * @details This macro indicates WDT time-out interrupt event has waked up system or not.
+ * \hideinitializer
+ */
+#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL)
+
+/**
+ * @brief Reset WDT Counter
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to reset the internal 18-bit WDT up counter value.
+ * @note If WDT is activated and time-out reset system function is enabled also, user should \n
+ * reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n
+ * reset system before the WDT time-out reset delay period expires.
+ * \hideinitializer
+ */
+#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD)
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void WDT_Close(void);
+__STATIC_INLINE void WDT_EnableInt(void);
+__STATIC_INLINE void WDT_DisableInt(void);
+
+/**
+ * @brief Stop WDT Counting
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will stop WDT counting and disable WDT module.
+ */
+__STATIC_INLINE void WDT_Close(void)
+{
+ WDT->CTL = 0UL;
+ return;
+}
+
+/**
+ * @brief Enable WDT Time-out Interrupt
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will enable the WDT time-out interrupt function.
+ */
+__STATIC_INLINE void WDT_EnableInt(void)
+{
+ WDT->CTL |= WDT_CTL_INTEN_Msk;
+ return;
+}
+
+/**
+ * @brief Disable WDT Time-out Interrupt
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will disable the WDT time-out interrupt function.
+ */
+__STATIC_INLINE void WDT_DisableInt(void)
+{
+ /* Do not touch another write 1 clear bits */
+ WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk);
+ return;
+}
+
+void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
+
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_WDT_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wwdt.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wwdt.h
new file mode 100644
index 00000000000..a15ae1446b2
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wwdt.h
@@ -0,0 +1,152 @@
+/**************************************************************************//**
+ * @file nu_wwdt.h
+ * @version V3.00
+ * @brief M480 series WWDT driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_WWDT_H__
+#define __NU_WWDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup WWDT_Driver WWDT Driver
+ @{
+*/
+
+/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* WWDT Prescale Period Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* WWDT Reload Counter Keyword Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */
+
+/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear WWDT Reset System Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear WWDT time-out reset system flag.
+ * \hideinitializer
+ */
+#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
+
+/**
+ * @brief Clear WWDT Compared Match Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear WWDT compared match interrupt flag.
+ * \hideinitializer
+ */
+#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
+
+/**
+ * @brief Get WWDT Reset System Flag
+ *
+ * @param None
+ *
+ * @retval 0 WWDT time-out reset system did not occur
+ * @retval 1 WWDT time-out reset system occurred
+ *
+ * @details This macro is used to indicate system has been reset by WWDT time-out reset or not.
+ * \hideinitializer
+ */
+#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)
+
+/**
+ * @brief Get WWDT Compared Match Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 WWDT compare match interrupt did not occur
+ * @retval 1 WWDT compare match interrupt occurred
+ *
+ * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not.
+ * \hideinitializer
+ */
+#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)
+
+/**
+ * @brief Get WWDT Counter
+ *
+ * @param None
+ *
+ * @return WWDT Counter Value
+ *
+ * @details This macro reflects the current WWDT counter value.
+ * \hideinitializer
+ */
+#define WWDT_GET_COUNTER() (WWDT->CNT)
+
+/**
+ * @brief Reload WWDT Counter
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to reload the WWDT counter value to 0x3F.
+ * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n
+ * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n
+ * WWDT reset signal will generate immediately to reset system.
+ * \hideinitializer
+ */
+#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)
+
+void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
+
+/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WWDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_WWDT_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.ewd b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.ewd
new file mode 100644
index 00000000000..4990af44b47
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.ewd
@@ -0,0 +1,3285 @@
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+ OCImagesPath2
+
+
+ OCImagesSuppressCheck3
+ 0
+
+
+ OCImagesPath3
+
+
+ OverrideDefFlashBoard
+ 0
+
+
+ OCImagesOffset1
+
+
+ OCImagesOffset2
+
+
+ OCImagesOffset3
+
+
+ OCImagesUse1
+ 0
+
+
+ OCImagesUse2
+ 0
+
+
+ OCImagesUse3
+ 0
+
+
+ OCDeviceConfigMacroFile
+ 1
+
+
+ OCDebuggerExtraOption
+ 1
+
+
+ OCAllMTBOptions
+ 1
+
+
+ OCMulticoreNrOfCores
+ 1
+
+
+ OCMulticoreMaster
+ 0
+
+
+ OCMulticorePort
+ 53461
+
+
+ OCMulticoreWorkspace
+
+
+ OCMulticoreSlaveProject
+
+
+ OCMulticoreSlaveConfiguration
+
+
+ OCDownloadExtraImage
+ 1
+
+
+ OCAttachSlave
+ 0
+
+
+
+
+ ARMSIM_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ OCSimDriverInfo
+ 1
+
+
+ OCSimEnablePSP
+ 0
+
+
+ OCSimPspOverrideConfig
+ 0
+
+
+ OCSimPspConfigFile
+
+
+
+
+ ANGEL_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CCAngelHeartbeat
+ 1
+
+
+ CAngelCommunication
+ 1
+
+
+ CAngelCommBaud
+ 0
+ 3
+
+
+ CAngelCommPort
+ 0
+ 0
+
+
+ ANGELTCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoAngelLogfile
+ 0
+
+
+ AngelLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ CADI_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CCadiMemory
+ 1
+
+
+ Fast Model
+
+
+ CCADILogFileCheck
+ 0
+
+
+ CCADILogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ CMSISDAP_ID
+ 2
+
+ 4
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ CMSISDAPResetList
+ 1
+ 10
+
+
+ CMSISDAPHWResetDuration
+ 300
+
+
+ CMSISDAPHWResetDelay
+ 200
+
+
+ CMSISDAPDoLogfile
+ 0
+
+
+ CMSISDAPLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CMSISDAPInterfaceRadio
+ 0
+
+
+ CMSISDAPInterfaceCmdLine
+ 0
+
+
+ CMSISDAPMultiTargetEnable
+ 0
+
+
+ CMSISDAPMultiTarget
+ 0
+
+
+ CMSISDAPJtagSpeedList
+ 0
+ 0
+
+
+ CMSISDAPBreakpointRadio
+ 0
+
+
+ CMSISDAPRestoreBreakpointsCheck
+ 0
+
+
+ CMSISDAPUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ CMSISDAPMultiCPUEnable
+ 0
+
+
+ CMSISDAPMultiCPUNumber
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+ CMSISDAPProbeConfigRadio
+ 0
+
+
+ CMSISDAPSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+ OCJetEmuParams
+ 1
+
+
+ CCCMSISDAPUsbSerialNo
+
+
+ CCCMSISDAPUsbSerialNoSelect
+ 0
+
+
+
+
+ GDBSERVER_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ TCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJTagBreakpointRadio
+ 0
+
+
+ CCJTagDoUpdateBreakpoints
+ 0
+
+
+ CCJTagUpdateBreakpoints
+ _call_main
+
+
+
+
+ IARROM_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ CRomLogFileCheck
+ 0
+
+
+ CRomLogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ CRomCommPort
+ 0
+ 0
+
+
+ CRomCommBaud
+ 0
+ 7
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ IJET_ID
+ 2
+
+ 8
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ IjetResetList
+ 1
+ 10
+
+
+ IjetHWResetDuration
+ 300
+
+
+ IjetHWResetDelay
+ 200
+
+
+ IjetPowerFromProbe
+ 1
+
+
+ IjetPowerRadio
+ 0
+
+
+ IjetDoLogfile
+ 0
+
+
+ IjetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ IjetInterfaceRadio
+ 0
+
+
+ IjetInterfaceCmdLine
+ 0
+
+
+ IjetMultiTargetEnable
+ 0
+
+
+ IjetMultiTarget
+ 0
+
+
+ IjetScanChainNonARMDevices
+ 0
+
+
+ IjetIRLength
+ 0
+
+
+ IjetJtagSpeedList
+ 0
+ 0
+
+
+ IjetProtocolRadio
+ 0
+
+
+ IjetSwoPin
+ 0
+
+
+ IjetCpuClockEdit
+
+
+ IjetSwoPrescalerList
+ 1
+ 0
+
+
+ IjetBreakpointRadio
+ 0
+
+
+ IjetRestoreBreakpointsCheck
+ 0
+
+
+ IjetUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+ IjetProbeConfigRadio
+ 0
+
+
+ IjetMultiCPUEnable
+ 0
+
+
+ IjetMultiCPUNumber
+ 0
+
+
+ IjetSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+ OCJetEmuParams
+ 1
+
+
+ IjetPreferETB
+ 1
+
+
+ IjetTraceSettingsList
+ 0
+ 0
+
+
+ IjetTraceSizeList
+ 0
+ 4
+
+
+ FlashBoardPathSlave
+ 0
+
+
+ CCIjetUsbSerialNo
+
+
+ CCIjetUsbSerialNoSelect
+ 0
+
+
+
+
+ JLINK_ID
+ 2
+
+ 16
+ 1
+ 1
+
+ JLinkSpeed
+ 1000
+
+
+ CCJLinkDoLogfile
+ 0
+
+
+ CCJLinkLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJLinkHWResetDelay
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+ JLinkInitialSpeed
+ 1000
+
+
+ CCDoJlinkMultiTarget
+ 0
+
+
+ CCScanChainNonARMDevices
+ 0
+
+
+ CCJLinkMultiTarget
+ 0
+
+
+ CCJLinkIRLength
+ 0
+
+
+ CCJLinkCommRadio
+ 0
+
+
+ CCJLinkTCPIP
+ aaa.bbb.ccc.ddd
+
+
+ CCJLinkSpeedRadioV2
+ 0
+
+
+ CCUSBDevice
+ 1
+ 1
+
+
+ CCRDICatchReset
+ 0
+
+
+ CCRDICatchUndef
+ 0
+
+
+ CCRDICatchSWI
+ 0
+
+
+ CCRDICatchData
+ 0
+
+
+ CCRDICatchPrefetch
+ 0
+
+
+ CCRDICatchIRQ
+ 0
+
+
+ CCRDICatchFIQ
+ 0
+
+
+ CCJLinkBreakpointRadio
+ 0
+
+
+ CCJLinkDoUpdateBreakpoints
+ 0
+
+
+ CCJLinkUpdateBreakpoints
+ _call_main
+
+
+ CCJLinkInterfaceRadio
+ 0
+
+
+ CCJLinkResetList
+ 6
+ 5
+
+
+ CCJLinkInterfaceCmdLine
+ 0
+
+
+ CCCatchCORERESET
+ 0
+
+
+ CCCatchMMERR
+ 0
+
+
+ CCCatchNOCPERR
+ 0
+
+
+ CCCatchCHRERR
+ 0
+
+
+ CCCatchSTATERR
+ 0
+
+
+ CCCatchBUSERR
+ 0
+
+
+ CCCatchINTERR
+ 0
+
+
+ CCCatchSFERR
+ 0
+
+
+ CCCatchHARDERR
+ 0
+
+
+ CCCatchDummy
+ 0
+
+
+ OCJLinkScriptFile
+ 1
+
+
+ CCJLinkUsbSerialNo
+
+
+ CCTcpIpAlt
+ 0
+ 0
+
+
+ CCJLinkTcpIpSerialNo
+
+
+ CCCpuClockEdit
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ OCJLinkTraceSource
+ 0
+
+
+ OCJLinkTraceSourceDummy
+ 0
+
+
+ OCJLinkDeviceName
+ 1
+
+
+
+
+ LMIFTDI_ID
+ 2
+
+ 2
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ LmiftdiSpeed
+ 500
+
+
+ CCLmiftdiDoLogfile
+ 0
+
+
+ CCLmiftdiLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCLmiFtdiInterfaceRadio
+ 0
+
+
+ CCLmiFtdiInterfaceCmdLine
+ 0
+
+
+
+
+ MACRAIGOR_ID
+ 2
+
+ 3
+ 1
+ 1
+
+ jtag
+ 0
+ 0
+
+
+ EmuSpeed
+ 1
+
+
+ TCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ DoEmuMultiTarget
+ 0
+
+
+ EmuMultiTarget
+ 0@ARM7TDMI
+
+
+ EmuHWReset
+ 0
+
+
+ CEmuCommBaud
+ 0
+ 4
+
+
+ CEmuCommPort
+ 0
+ 0
+
+
+ jtago
+ 0
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+ UnusedAddr
+ 0x00800000
+
+
+ CCMacraigorHWResetDelay
+
+
+ CCJTagBreakpointRadio
+ 0
+
+
+ CCJTagDoUpdateBreakpoints
+ 0
+
+
+ CCJTagUpdateBreakpoints
+ _call_main
+
+
+ CCMacraigorInterfaceRadio
+ 0
+
+
+ CCMacraigorInterfaceCmdLine
+ 0
+
+
+
+
+ PEMICRO_ID
+ 2
+
+ 3
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCJPEMicroShowSettings
+ 0
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ RDI_ID
+ 2
+
+ 2
+ 1
+ 1
+
+ CRDIDriverDll
+ ###Uninitialized###
+
+
+ CRDILogFileCheck
+ 0
+
+
+ CRDILogFileEdit
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCRDIHWReset
+ 0
+
+
+ CCRDICatchReset
+ 0
+
+
+ CCRDICatchUndef
+ 0
+
+
+ CCRDICatchSWI
+ 0
+
+
+ CCRDICatchData
+ 0
+
+
+ CCRDICatchPrefetch
+ 0
+
+
+ CCRDICatchIRQ
+ 0
+
+
+ CCRDICatchFIQ
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ STLINK_ID
+ 2
+
+ 3
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCSTLinkInterfaceRadio
+ 0
+
+
+ CCSTLinkInterfaceCmdLine
+ 0
+
+
+ CCSTLinkResetList
+ 2
+ 0
+
+
+ CCCpuClockEdit
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCSTLinkDoUpdateBreakpoints
+ 0
+
+
+ CCSTLinkUpdateBreakpoints
+ _call_main
+
+
+ CCSTLinkCatchCORERESET
+ 0
+
+
+ CCSTLinkCatchMMERR
+ 0
+
+
+ CCSTLinkCatchNOCPERR
+ 0
+
+
+ CCSTLinkCatchCHRERR
+ 0
+
+
+ CCSTLinkCatchSTATERR
+ 0
+
+
+ CCSTLinkCatchBUSERR
+ 0
+
+
+ CCSTLinkCatchINTERR
+ 0
+
+
+ CCSTLinkCatchSFERR
+ 0
+
+
+ CCSTLinkCatchHARDERR
+ 0
+
+
+ CCSTLinkCatchDummy
+ 0
+
+
+ CCSTLinkUsbSerialNo
+
+
+ CCSTLinkUsbSerialNoSelect
+ 0
+
+
+ CCSTLinkJtagSpeedList
+ 0
+ 0
+
+
+ CCSTLinkDAPNumber
+
+
+
+
+ THIRDPARTY_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CThirdPartyDriverDll
+ $TOOLKIT_DIR$\..\..\..\Nuvoton Tools\Nu-Link_IAR\Nu-Link_IAR.dll
+
+
+ CThirdPartyLogFileCheck
+ 0
+
+
+ CThirdPartyLogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ TIFET_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCMSPFetResetList
+ 0
+ 0
+
+
+ CCMSPFetInterfaceRadio
+ 0
+
+
+ CCMSPFetInterfaceCmdLine
+ 0
+
+
+ CCMSPFetTargetVccTypeDefault
+ 0
+
+
+ CCMSPFetTargetVoltage
+ ###Uninitialized###
+
+
+ CCMSPFetVCCDefault
+ 1
+
+
+ CCMSPFetTargetSettlingtime
+ 0
+
+
+ CCMSPFetRadioJtagSpeedType
+ 1
+
+
+ CCMSPFetConnection
+ 0
+ 0
+
+
+ CCMSPFetUsbComPort
+ Automatic
+
+
+ CCMSPFetAllowAccessToBSL
+ 0
+
+
+ CCMSPFetDoLogfile
+ 0
+
+
+ CCMSPFetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCMSPFetRadioEraseFlash
+ 1
+
+
+
+
+ XDS100_ID
+ 2
+
+ 6
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ TIPackageOverride
+ 0
+
+
+ TIPackage
+
+
+ BoardFile
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCXds100BreakpointRadio
+ 0
+
+
+ CCXds100DoUpdateBreakpoints
+ 0
+
+
+ CCXds100UpdateBreakpoints
+ _call_main
+
+
+ CCXds100CatchReset
+ 0
+
+
+ CCXds100CatchUndef
+ 0
+
+
+ CCXds100CatchSWI
+ 0
+
+
+ CCXds100CatchData
+ 0
+
+
+ CCXds100CatchPrefetch
+ 0
+
+
+ CCXds100CatchIRQ
+ 0
+
+
+ CCXds100CatchFIQ
+ 0
+
+
+ CCXds100CatchCORERESET
+ 0
+
+
+ CCXds100CatchMMERR
+ 0
+
+
+ CCXds100CatchNOCPERR
+ 0
+
+
+ CCXds100CatchCHRERR
+ 0
+
+
+ CCXds100CatchSTATERR
+ 0
+
+
+ CCXds100CatchBUSERR
+ 0
+
+
+ CCXds100CatchINTERR
+ 0
+
+
+ CCXds100CatchSFERR
+ 0
+
+
+ CCXds100CatchHARDERR
+ 0
+
+
+ CCXds100CatchDummy
+ 0
+
+
+ CCXds100CpuClockEdit
+
+
+ CCXds100SwoClockAuto
+ 0
+
+
+ CCXds100SwoClockEdit
+ 1000
+
+
+ CCXds100HWResetDelay
+ 0
+
+
+ CCXds100ResetList
+ 0
+ 0
+
+
+ CCXds100UsbSerialNo
+
+
+ CCXds100UsbSerialNoSelect
+ 0
+
+
+ CCXds100JtagSpeedList
+ 0
+ 0
+
+
+ CCXds100InterfaceRadio
+ 2
+
+
+ CCXds100InterfaceCmdLine
+ 0
+
+
+ CCXds100ProbeList
+ 0
+ 2
+
+
+ CCXds100SWOPortRadio
+ 0
+
+
+ CCXds100SWOPort
+ 1
+
+
+
+
+
+ $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+ 1
+
+
+ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+ 0
+
+
+
+
+ Release
+
+ ARM
+
+ 0
+
+ C-SPY
+ 2
+
+ 28
+ 1
+ 0
+
+ CInput
+ 1
+
+
+ CEndian
+ 1
+
+
+ CProcessor
+ 1
+
+
+ OCVariant
+ 0
+
+
+ MacOverride
+ 0
+
+
+ MacFile
+
+
+ MemOverride
+ 0
+
+
+ MemFile
+
+
+ RunToEnable
+ 1
+
+
+ RunToName
+ main
+
+
+ CExtraOptionsCheck
+ 0
+
+
+ CExtraOptions
+
+
+ CFpuProcessor
+ 1
+
+
+ OCDDFArgumentProducer
+
+
+ OCDownloadSuppressDownload
+ 0
+
+
+ OCDownloadVerifyAll
+ 0
+
+
+ OCProductVersion
+ 7.80.3.12143
+
+
+ OCDynDriverList
+ THIRDPARTY_ID
+
+
+ OCLastSavedByProductVersion
+ 7.80.3.12143
+
+
+ UseFlashLoader
+ 1
+
+
+ CLowLevel
+ 1
+
+
+ OCBE8Slave
+ 1
+
+
+ MacFile2
+
+
+ CDevice
+ 1
+
+
+ FlashLoadersV3
+ $TOOLKIT_DIR$\config\flashloader\Nuvoton\M251_APROM.board
+
+
+ OCImagesSuppressCheck1
+ 0
+
+
+ OCImagesPath1
+
+
+ OCImagesSuppressCheck2
+ 0
+
+
+ OCImagesPath2
+
+
+ OCImagesSuppressCheck3
+ 0
+
+
+ OCImagesPath3
+
+
+ OverrideDefFlashBoard
+ 0
+
+
+ OCImagesOffset1
+
+
+ OCImagesOffset2
+
+
+ OCImagesOffset3
+
+
+ OCImagesUse1
+ 0
+
+
+ OCImagesUse2
+ 0
+
+
+ OCImagesUse3
+ 0
+
+
+ OCDeviceConfigMacroFile
+ 1
+
+
+ OCDebuggerExtraOption
+ 1
+
+
+ OCAllMTBOptions
+ 1
+
+
+ OCMulticoreNrOfCores
+ 1
+
+
+ OCMulticoreMaster
+ 0
+
+
+ OCMulticorePort
+ 53461
+
+
+ OCMulticoreWorkspace
+
+
+ OCMulticoreSlaveProject
+
+
+ OCMulticoreSlaveConfiguration
+
+
+ OCDownloadExtraImage
+ 1
+
+
+ OCAttachSlave
+ 0
+
+
+
+
+ ARMSIM_ID
+ 2
+
+ 1
+ 1
+ 0
+
+ OCSimDriverInfo
+ 1
+
+
+ OCSimEnablePSP
+ 0
+
+
+ OCSimPspOverrideConfig
+ 0
+
+
+ OCSimPspConfigFile
+
+
+
+
+ ANGEL_ID
+ 2
+
+ 0
+ 1
+ 0
+
+ CCAngelHeartbeat
+ 1
+
+
+ CAngelCommunication
+ 1
+
+
+ CAngelCommBaud
+ 0
+ 3
+
+
+ CAngelCommPort
+ 0
+ 0
+
+
+ ANGELTCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoAngelLogfile
+ 0
+
+
+ AngelLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ CADI_ID
+ 2
+
+ 0
+ 1
+ 0
+
+ CCadiMemory
+ 1
+
+
+ Fast Model
+
+
+ CCADILogFileCheck
+ 0
+
+
+ CCADILogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ CMSISDAP_ID
+ 2
+
+ 4
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ CMSISDAPResetList
+ 1
+ 10
+
+
+ CMSISDAPHWResetDuration
+ 300
+
+
+ CMSISDAPHWResetDelay
+ 200
+
+
+ CMSISDAPDoLogfile
+ 0
+
+
+ CMSISDAPLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CMSISDAPInterfaceRadio
+ 0
+
+
+ CMSISDAPInterfaceCmdLine
+ 0
+
+
+ CMSISDAPMultiTargetEnable
+ 0
+
+
+ CMSISDAPMultiTarget
+ 0
+
+
+ CMSISDAPJtagSpeedList
+ 0
+ 0
+
+
+ CMSISDAPBreakpointRadio
+ 0
+
+
+ CMSISDAPRestoreBreakpointsCheck
+ 0
+
+
+ CMSISDAPUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ CMSISDAPMultiCPUEnable
+ 0
+
+
+ CMSISDAPMultiCPUNumber
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+ CMSISDAPProbeConfigRadio
+ 0
+
+
+ CMSISDAPSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+ OCJetEmuParams
+ 1
+
+
+ CCCMSISDAPUsbSerialNo
+
+
+ CCCMSISDAPUsbSerialNoSelect
+ 0
+
+
+
+
+ GDBSERVER_ID
+ 2
+
+ 0
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ TCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJTagBreakpointRadio
+ 0
+
+
+ CCJTagDoUpdateBreakpoints
+ 0
+
+
+ CCJTagUpdateBreakpoints
+ _call_main
+
+
+
+
+ IARROM_ID
+ 2
+
+ 1
+ 1
+ 0
+
+ CRomLogFileCheck
+ 0
+
+
+ CRomLogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ CRomCommPort
+ 0
+ 0
+
+
+ CRomCommBaud
+ 0
+ 7
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ IJET_ID
+ 2
+
+ 8
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ IjetResetList
+ 1
+ 10
+
+
+ IjetHWResetDuration
+ 300
+
+
+ IjetHWResetDelay
+ 200
+
+
+ IjetPowerFromProbe
+ 1
+
+
+ IjetPowerRadio
+ 0
+
+
+ IjetDoLogfile
+ 0
+
+
+ IjetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ IjetInterfaceRadio
+ 0
+
+
+ IjetInterfaceCmdLine
+ 0
+
+
+ IjetMultiTargetEnable
+ 0
+
+
+ IjetMultiTarget
+ 0
+
+
+ IjetScanChainNonARMDevices
+ 0
+
+
+ IjetIRLength
+ 0
+
+
+ IjetJtagSpeedList
+ 0
+ 0
+
+
+ IjetProtocolRadio
+ 0
+
+
+ IjetSwoPin
+ 0
+
+
+ IjetCpuClockEdit
+
+
+ IjetSwoPrescalerList
+ 1
+ 0
+
+
+ IjetBreakpointRadio
+ 0
+
+
+ IjetRestoreBreakpointsCheck
+ 0
+
+
+ IjetUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+ IjetProbeConfigRadio
+ 0
+
+
+ IjetMultiCPUEnable
+ 0
+
+
+ IjetMultiCPUNumber
+ 0
+
+
+ IjetSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+ OCJetEmuParams
+ 1
+
+
+ IjetPreferETB
+ 1
+
+
+ IjetTraceSettingsList
+ 0
+ 0
+
+
+ IjetTraceSizeList
+ 0
+ 4
+
+
+ FlashBoardPathSlave
+ 0
+
+
+ CCIjetUsbSerialNo
+
+
+ CCIjetUsbSerialNoSelect
+ 0
+
+
+
+
+ JLINK_ID
+ 2
+
+ 16
+ 1
+ 0
+
+ JLinkSpeed
+ 1000
+
+
+ CCJLinkDoLogfile
+ 0
+
+
+ CCJLinkLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJLinkHWResetDelay
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+ JLinkInitialSpeed
+ 1000
+
+
+ CCDoJlinkMultiTarget
+ 0
+
+
+ CCScanChainNonARMDevices
+ 0
+
+
+ CCJLinkMultiTarget
+ 0
+
+
+ CCJLinkIRLength
+ 0
+
+
+ CCJLinkCommRadio
+ 0
+
+
+ CCJLinkTCPIP
+ aaa.bbb.ccc.ddd
+
+
+ CCJLinkSpeedRadioV2
+ 0
+
+
+ CCUSBDevice
+ 1
+ 1
+
+
+ CCRDICatchReset
+ 0
+
+
+ CCRDICatchUndef
+ 0
+
+
+ CCRDICatchSWI
+ 0
+
+
+ CCRDICatchData
+ 0
+
+
+ CCRDICatchPrefetch
+ 0
+
+
+ CCRDICatchIRQ
+ 0
+
+
+ CCRDICatchFIQ
+ 0
+
+
+ CCJLinkBreakpointRadio
+ 0
+
+
+ CCJLinkDoUpdateBreakpoints
+ 0
+
+
+ CCJLinkUpdateBreakpoints
+ _call_main
+
+
+ CCJLinkInterfaceRadio
+ 0
+
+
+ CCJLinkResetList
+ 6
+ 5
+
+
+ CCJLinkInterfaceCmdLine
+ 0
+
+
+ CCCatchCORERESET
+ 0
+
+
+ CCCatchMMERR
+ 0
+
+
+ CCCatchNOCPERR
+ 0
+
+
+ CCCatchCHRERR
+ 0
+
+
+ CCCatchSTATERR
+ 0
+
+
+ CCCatchBUSERR
+ 0
+
+
+ CCCatchINTERR
+ 0
+
+
+ CCCatchSFERR
+ 0
+
+
+ CCCatchHARDERR
+ 0
+
+
+ CCCatchDummy
+ 0
+
+
+ OCJLinkScriptFile
+ 1
+
+
+ CCJLinkUsbSerialNo
+
+
+ CCTcpIpAlt
+ 0
+ 0
+
+
+ CCJLinkTcpIpSerialNo
+
+
+ CCCpuClockEdit
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ OCJLinkTraceSource
+ 0
+
+
+ OCJLinkTraceSourceDummy
+ 0
+
+
+ OCJLinkDeviceName
+ 1
+
+
+
+
+ LMIFTDI_ID
+ 2
+
+ 2
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ LmiftdiSpeed
+ 500
+
+
+ CCLmiftdiDoLogfile
+ 0
+
+
+ CCLmiftdiLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCLmiFtdiInterfaceRadio
+ 0
+
+
+ CCLmiFtdiInterfaceCmdLine
+ 0
+
+
+
+
+ MACRAIGOR_ID
+ 2
+
+ 3
+ 1
+ 0
+
+ jtag
+ 0
+ 0
+
+
+ EmuSpeed
+ 1
+
+
+ TCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ DoEmuMultiTarget
+ 0
+
+
+ EmuMultiTarget
+ 0@ARM7TDMI
+
+
+ EmuHWReset
+ 0
+
+
+ CEmuCommBaud
+ 0
+ 4
+
+
+ CEmuCommPort
+ 0
+ 4
+
+
+ jtago
+ 0
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+ UnusedAddr
+ 0x00800000
+
+
+ CCMacraigorHWResetDelay
+
+
+ CCJTagBreakpointRadio
+ 0
+
+
+ CCJTagDoUpdateBreakpoints
+ 0
+
+
+ CCJTagUpdateBreakpoints
+ _call_main
+
+
+ CCMacraigorInterfaceRadio
+ 0
+
+
+ CCMacraigorInterfaceCmdLine
+ 0
+
+
+
+
+ PEMICRO_ID
+ 2
+
+ 3
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ CCJPEMicroShowSettings
+ 0
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ RDI_ID
+ 2
+
+ 2
+ 1
+ 0
+
+ CRDIDriverDll
+ ###Uninitialized###
+
+
+ CRDILogFileCheck
+ 0
+
+
+ CRDILogFileEdit
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCRDIHWReset
+ 0
+
+
+ CCRDICatchReset
+ 0
+
+
+ CCRDICatchUndef
+ 0
+
+
+ CCRDICatchSWI
+ 0
+
+
+ CCRDICatchData
+ 0
+
+
+ CCRDICatchPrefetch
+ 0
+
+
+ CCRDICatchIRQ
+ 0
+
+
+ CCRDICatchFIQ
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ STLINK_ID
+ 2
+
+ 3
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ CCSTLinkInterfaceRadio
+ 0
+
+
+ CCSTLinkInterfaceCmdLine
+ 0
+
+
+ CCSTLinkResetList
+ 2
+ 0
+
+
+ CCCpuClockEdit
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCSTLinkDoUpdateBreakpoints
+ 0
+
+
+ CCSTLinkUpdateBreakpoints
+ _call_main
+
+
+ CCSTLinkCatchCORERESET
+ 0
+
+
+ CCSTLinkCatchMMERR
+ 0
+
+
+ CCSTLinkCatchNOCPERR
+ 0
+
+
+ CCSTLinkCatchCHRERR
+ 0
+
+
+ CCSTLinkCatchSTATERR
+ 0
+
+
+ CCSTLinkCatchBUSERR
+ 0
+
+
+ CCSTLinkCatchINTERR
+ 0
+
+
+ CCSTLinkCatchSFERR
+ 0
+
+
+ CCSTLinkCatchHARDERR
+ 0
+
+
+ CCSTLinkCatchDummy
+ 0
+
+
+ CCSTLinkUsbSerialNo
+
+
+ CCSTLinkUsbSerialNoSelect
+ 0
+
+
+ CCSTLinkJtagSpeedList
+ 0
+ 0
+
+
+ CCSTLinkDAPNumber
+
+
+
+
+ THIRDPARTY_ID
+ 2
+
+ 0
+ 1
+ 0
+
+ CThirdPartyDriverDll
+ $TOOLKIT_DIR$\..\..\..\Nuvoton Tools\Nu-Link_IAR\Nu-Link_IAR.dll
+
+
+ CThirdPartyLogFileCheck
+ 0
+
+
+ CThirdPartyLogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ TIFET_ID
+ 2
+
+ 1
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ CCMSPFetResetList
+ 0
+ 0
+
+
+ CCMSPFetInterfaceRadio
+ 0
+
+
+ CCMSPFetInterfaceCmdLine
+ 0
+
+
+ CCMSPFetTargetVccTypeDefault
+ 0
+
+
+ CCMSPFetTargetVoltage
+ ###Uninitialized###
+
+
+ CCMSPFetVCCDefault
+ 1
+
+
+ CCMSPFetTargetSettlingtime
+ 0
+
+
+ CCMSPFetRadioJtagSpeedType
+ 1
+
+
+ CCMSPFetConnection
+ 0
+ 0
+
+
+ CCMSPFetUsbComPort
+ Automatic
+
+
+ CCMSPFetAllowAccessToBSL
+ 0
+
+
+ CCMSPFetDoLogfile
+ 0
+
+
+ CCMSPFetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCMSPFetRadioEraseFlash
+ 1
+
+
+
+
+ XDS100_ID
+ 2
+
+ 6
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ TIPackageOverride
+ 0
+
+
+ TIPackage
+
+
+ BoardFile
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCXds100BreakpointRadio
+ 0
+
+
+ CCXds100DoUpdateBreakpoints
+ 0
+
+
+ CCXds100UpdateBreakpoints
+ _call_main
+
+
+ CCXds100CatchReset
+ 0
+
+
+ CCXds100CatchUndef
+ 0
+
+
+ CCXds100CatchSWI
+ 0
+
+
+ CCXds100CatchData
+ 0
+
+
+ CCXds100CatchPrefetch
+ 0
+
+
+ CCXds100CatchIRQ
+ 0
+
+
+ CCXds100CatchFIQ
+ 0
+
+
+ CCXds100CatchCORERESET
+ 0
+
+
+ CCXds100CatchMMERR
+ 0
+
+
+ CCXds100CatchNOCPERR
+ 0
+
+
+ CCXds100CatchCHRERR
+ 0
+
+
+ CCXds100CatchSTATERR
+ 0
+
+
+ CCXds100CatchBUSERR
+ 0
+
+
+ CCXds100CatchINTERR
+ 0
+
+
+ CCXds100CatchSFERR
+ 0
+
+
+ CCXds100CatchHARDERR
+ 0
+
+
+ CCXds100CatchDummy
+ 0
+
+
+ CCXds100CpuClockEdit
+
+
+ CCXds100SwoClockAuto
+ 0
+
+
+ CCXds100SwoClockEdit
+ 1000
+
+
+ CCXds100HWResetDelay
+ 0
+
+
+ CCXds100ResetList
+ 0
+ 0
+
+
+ CCXds100UsbSerialNo
+
+
+ CCXds100UsbSerialNoSelect
+ 0
+
+
+ CCXds100JtagSpeedList
+ 0
+ 0
+
+
+ CCXds100InterfaceRadio
+ 2
+
+
+ CCXds100InterfaceCmdLine
+ 0
+
+
+ CCXds100ProbeList
+ 0
+ 2
+
+
+ CCXds100SWOPortRadio
+ 0
+
+
+ CCXds100SWOPort
+ 1
+
+
+
+
+
+ $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+ 1
+
+
+ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+ 0
+
+
+
+
+
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.ewp b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.ewp
new file mode 100644
index 00000000000..8759c80add9
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.ewp
@@ -0,0 +1,2197 @@
+
+
+ 3
+
+ Debug
+
+ ARM
+
+ 1
+
+ General
+ 3
+
+ 31
+ 1
+ 1
+
+ ExePath
+ build\iar\Exe
+
+
+ ObjPath
+ build\iar\Obj
+
+
+ ListPath
+ build\iar\List
+
+
+ GEndianMode
+ 0
+
+
+ Input description
+ Automatic choice of formatter, without multibyte support.
+
+
+ Output description
+ Automatic choice of formatter, without multibyte support.
+
+
+ GOutputBinary
+ 1
+
+
+ OGCoreOrChip
+ 1
+
+
+ GRuntimeLibSelect
+ 0
+ 2
+
+
+ GRuntimeLibSelectSlave
+ 0
+ 2
+
+
+ RTDescription
+ To be used with the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.
+
+
+ OGProductVersion
+ 7.80.3.12143
+
+
+ OGLastSavedByProductVersion
+ 8.32.1.18618
+
+
+ GeneralEnableMisra
+ 0
+
+
+ GeneralMisraVerbose
+ 0
+
+
+ OGChipSelectEditMenu
+ M481AE series Nuvoton M480AE series (M481AE,M482AE,M483AE,M484AE,M485AE,M487AE)
+
+
+ GenLowLevelInterface
+ 1
+
+
+ GEndianModeBE
+ 1
+
+
+ OGBufferedTerminalOutput
+ 0
+
+
+ GenStdoutInterface
+ 0
+
+
+ GeneralMisraRules98
+ 0
+ 1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111
+
+
+ GeneralMisraVer
+ 0
+
+
+ GeneralMisraRules04
+ 0
+ 111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111
+
+
+ RTConfigPath2
+ $TOOLKIT_DIR$\inc\c\DLib_Config_Full.h
+
+
+ GBECoreSlave
+ 26
+ 39
+
+
+ OGUseCmsis
+ 0
+
+
+ OGUseCmsisDspLib
+ 0
+
+
+ GRuntimeLibThreads
+ 0
+
+
+ CoreVariant
+ 26
+ 39
+
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+
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diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.eww b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.eww
new file mode 100644
index 00000000000..fcdfcdfe308
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\libStdDriver.ewp
+
+
+
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.uvprojx b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.uvprojx
new file mode 100644
index 00000000000..c447d034e0a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.uvprojx
@@ -0,0 +1,587 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ libstddriver-m480
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::ARMCC
+ 0
+
+
+ M487JIDAE
+ Nuvoton
+ Nuvoton.NuMicro_DFP.1.3.9
+ http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack
+ IRAM(0x20000000,0x28000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000)
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M481_AP_512 -FS00 -FL080000 -FP0($$Device:M487JIDAE$Flash\M481_AP_512.FLM))
+ 0
+ $$Device:M487JIDAE$Device\M480\Include\M480.h
+ $$Device:M487JIDAE$SVD\Nuvoton\M481_v1.svd
+ 0
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+
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+ nu_crypto.c
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+
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+
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+
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+
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+ 1
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+
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+
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diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver_4.uvproj b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver_4.uvproj
new file mode 100644
index 00000000000..3f834f0d1b6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver_4.uvproj
@@ -0,0 +1,591 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ libStdDriver_4
+ 0x4
+ ARM-ADS
+
+
+ M487JIDAE
+ Nuvoton
+ IRAM(0x20000000-0x20027FFF) IROM(0-0x7FFFF) CLOCK(192000000) CPUTYPE("Cortex-M4") FPU2
+ undefined
+ 0
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+ --c99
+ ..\lib;..\inc;..\..\CMSIS\Include;..\..\Device\Nuvoton\M480\Include
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+
+
+
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+
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+
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+
+
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+
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+
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+
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+ 1
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+
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diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/nutool_clkcfg.h b/bsp/nuvoton/libraries/m480/StdDriver/lib/nutool_clkcfg.h
new file mode 100644
index 00000000000..950b09946e2
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/nutool_clkcfg.h
@@ -0,0 +1,26 @@
+/****************************************************************************
+ * @file nutool_clkcfg.h
+ * @version V1.05
+ * @Date 2020/04/15-11:28:38
+ * @brief NuMicro generated code file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NUTOOL_CLKCFG_H__
+#define __NUTOOL_CLKCFG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#undef __HXT
+#define __HXT (12000000UL) /*!< High Speed External Crystal Clock Frequency */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__NUTOOL_CLKCFG_H__*/
+
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_acmp.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_acmp.c
new file mode 100644
index 00000000000..6e42fd7a61c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_acmp.c
@@ -0,0 +1,75 @@
+/**************************************************************************//**
+ * @file acmp.c
+ * @version V1.00
+ * @brief M480 series Analog Comparator(ACMP) driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup ACMP_Driver ACMP Driver
+ @{
+*/
+
+
+/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Configure the specified ACMP module
+ *
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum Comparator number.
+ * @param[in] u32NegSrc Comparator negative input selection. Including:
+ * - \ref ACMP_CTL_NEGSEL_PIN
+ * - \ref ACMP_CTL_NEGSEL_CRV
+ * - \ref ACMP_CTL_NEGSEL_VBG
+ * - \ref ACMP_CTL_NEGSEL_DAC
+ * @param[in] u32HysSel The hysteresis function option. Including:
+ * - \ref ACMP_CTL_HYSTERESIS_30MV
+ * - \ref ACMP_CTL_HYSTERESIS_20MV
+ * - \ref ACMP_CTL_HYSTERESIS_10MV
+ * - \ref ACMP_CTL_HYSTERESIS_DISABLE
+ *
+ * @return None
+ *
+ * @details Configure hysteresis function, select the source of negative input and enable analog comparator.
+ */
+void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel)
+{
+ acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk);
+}
+
+/**
+ * @brief Close analog comparator
+ *
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum Comparator number.
+ *
+ * @return None
+ *
+ * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
+ */
+void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum)
+{
+ acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
+}
+
+
+
+/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group ACMP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_bpwm.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_bpwm.c
new file mode 100644
index 00000000000..4a6b08fbea6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_bpwm.c
@@ -0,0 +1,745 @@
+/**************************************************************************//**
+ * @file bpwm.c
+ * @version V1.00
+ * @brief M480 series BPWM driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup BPWM_Driver BPWM Driver
+ @{
+*/
+
+
+/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief Configure BPWM capture and get the nearest unit time.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32UnitTimeNsec The unit time of counter
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
+ * @return The nearest unit time in nano second.
+ * @details This function is used to Configure BPWM capture and get the nearest unit time.
+ */
+uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
+{
+ uint32_t u32Src;
+ uint32_t u32PWMClockSrc;
+ uint32_t u32NearestUnitTimeNsec;
+ uint16_t u16Prescale = 1U, u16CNR = 0xFFFFU;
+
+ if(bpwm == BPWM0)
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
+ }
+ else /* (bpwm == BPWM1) */
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
+ }
+
+ if(u32Src == 0U)
+ {
+ /* clock source is from PLL clock */
+ u32PWMClockSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ /* clock source is from PCLK */
+ SystemCoreClockUpdate();
+ if(bpwm == BPWM0)
+ {
+ u32PWMClockSrc = CLK_GetPCLK0Freq();
+ }
+ else /* (bpwm == BPWM1) */
+ {
+ u32PWMClockSrc = CLK_GetPCLK1Freq();
+ }
+ }
+
+ u32PWMClockSrc /= 1000UL;
+ for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++)
+ {
+ uint32_t u32Exit = 0U;
+ u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32PWMClockSrc;
+ if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
+ {
+ if (u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */
+ {
+ u32Exit = 1U;
+ }
+ else
+ {
+ u32Exit = 0U;
+ }
+ if (!(1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))
+ {
+ u32Exit = 1U;
+ }
+ else
+ {
+ u32Exit = 0U;
+ }
+ }
+ else
+ {
+ u32Exit = 1U;
+ }
+ if (u32Exit == 1U)
+ {
+ break;
+ }
+ else {}
+ }
+
+ /* convert to real register value */
+ /* all channels share a prescaler */
+ u16Prescale -= 1U;
+ BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u16Prescale);
+
+ /* set BPWM to down count type(edge aligned) */
+ (bpwm)->CTL1 = (1UL);
+
+ BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR);
+
+ return (u32NearestUnitTimeNsec);
+}
+
+/**
+ * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned auto-reload mode
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect
+ * existing frequency of other channel.
+ */
+uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+ uint32_t u32Src;
+ uint32_t u32PWMClockSrc;
+ uint32_t i;
+ uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
+
+ if(bpwm == BPWM0)
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
+ }
+ else /* (bpwm == BPWM1) */
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
+ }
+
+ if(u32Src == 0U)
+ {
+ /* clock source is from PLL clock */
+ u32PWMClockSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ /* clock source is from PCLK */
+ SystemCoreClockUpdate();
+ if(bpwm == BPWM0)
+ {
+ u32PWMClockSrc = CLK_GetPCLK0Freq();
+ }
+ else /* (bpwm == BPWM1) */
+ {
+ u32PWMClockSrc = CLK_GetPCLK1Freq();
+ }
+ }
+
+ for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */
+ {
+ i = (u32PWMClockSrc / u32Frequency) / u32Prescale;
+ /* If target value is larger than CNR, need to use a larger prescaler */
+ if(i < (0x10000U))
+ {
+ u32CNR = i;
+ break;
+ }
+ }
+ /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */
+ i = u32PWMClockSrc / (u32Prescale * u32CNR);
+
+ /* convert to real register value */
+ /* all channels share a prescaler */
+ u32Prescale -= 1U;
+ BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale);
+ /* set BPWM to down count type(edge aligned) */
+ (bpwm)->CTL1 = (1UL);
+
+ u32CNR -= 1U;
+ BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR);
+ if(u32DutyCycle)
+ {
+ BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL - 1UL);
+ (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2U));
+ (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum * (2U)) + (uint32_t)BPWM_WGCTL0_PRDPCTL0_Pos));
+ (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2U));
+ (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * (2U) + (uint32_t)BPWM_WGCTL1_CMPDCTL0_Pos));
+ }
+ else
+ {
+ BPWM_SET_CMR(bpwm, u32ChannelNum, 0U);
+ (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2U));
+ (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL0_ZPCTL0_Pos));
+ (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2U));
+ (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL1_CMPDCTL0_Pos));
+ }
+
+ return(i);
+}
+
+/**
+ * @brief Start BPWM module
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This function is used to start BPWM module.
+ * @note All channels share one counter.
+ */
+void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+ (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk;
+}
+
+/**
+ * @brief Stop BPWM module
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This function is used to stop BPWM module.
+ * @note All channels share one period.
+ */
+void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+ (bpwm)->PERIOD = 0U;
+}
+
+/**
+ * @brief Stop BPWM generation immediately by clear channel enable bit
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This function is used to stop BPWM generation immediately by clear channel enable bit.
+ * @note All channels share one counter.
+ */
+void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+ (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk;
+}
+
+/**
+ * @brief Enable selected channel to trigger ADC
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
+ * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT
+ * - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT
+ * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT
+ * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT
+ * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT
+ * - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT
+ * - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable selected channel to trigger ADC
+ */
+void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ if(u32ChannelNum < 4U)
+ {
+ (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8U));
+ (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8U));
+ }
+ else
+ {
+ (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) * 8U));
+ (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) * 8U));
+ }
+}
+
+/**
+ * @brief Disable selected channel to trigger ADC
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3
+ * @return None
+ * @details This function is used to disable selected channel to trigger ADC
+ */
+void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ if(u32ChannelNum < 4U)
+ {
+ (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8U));
+ }
+ else
+ {
+ (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) * 8U));
+ }
+}
+
+/**
+ * @brief Clear selected channel trigger ADC flag
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger ADC flag
+ */
+void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get selected channel trigger ADC flag
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @retval 0 The specified channel trigger ADC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger ADC to start of conversion flag is set
+ * @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel
+ */
+uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable capture of selected channel(s)
+ */
+void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+ (bpwm)->CAPINEN |= u32ChannelMask;
+ (bpwm)->CAPCTL |= u32ChannelMask;
+}
+
+/**
+ * @brief Disable capture of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable capture of selected channel(s)
+ */
+void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+ (bpwm)->CAPINEN &= ~u32ChannelMask;
+ (bpwm)->CAPCTL &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables BPWM output generation of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ * @details This function is used to enables BPWM output generation of selected channel(s)
+ */
+void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+ (bpwm)->POEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Disables BPWM output generation of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ * @details This function is used to disables BPWM output generation of selected channel(s)
+ */
+void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+ (bpwm)->POEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enable capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref BPWM_CAPTURE_INT_RISING_LATCH
+ * - \ref BPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable capture interrupt of selected channel.
+ */
+void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Disable capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref BPWM_CAPTURE_INT_RISING_LATCH
+ * - \ref BPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to disable capture interrupt of selected channel.
+ */
+void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Clear capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref BPWM_CAPTURE_INT_RISING_LATCH
+ * - \ref BPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to clear capture interrupt of selected channel.
+ */
+void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (bpwm)->CAPIF = (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Get capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @retval 0 No capture interrupt
+ * @retval 1 Rising edge latch interrupt
+ * @retval 2 Falling edge latch interrupt
+ * @retval 3 Rising and falling latch interrupt
+ * @details This function is used to get capture interrupt of selected channel.
+ */
+uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ return (((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \
+ (((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIF0_Msk << u32ChannelNum)) ? 1UL : 0UL));
+}
+/**
+ * @brief Enable duty interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntDutyType Duty interrupt type, could be either
+ * - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
+ * - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP
+ * @return None
+ * @details This function is used to enable duty interrupt of selected channel.
+ */
+void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
+{
+ (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum);
+}
+
+/**
+ * @brief Disable duty interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable duty interrupt of selected channel
+ */
+void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+
+ (bpwm)->INTEN &= ~((uint32_t)(BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear duty interrupt flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear duty interrupt flag of selected channel
+ */
+void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ (bpwm)->INTSTS = (BPWM_INTSTS_CMPUIF0_Msk | BPWM_INTSTS_CMPDIF0_Msk) << u32ChannelNum;
+}
+
+/**
+ * @brief Get duty interrupt flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Duty interrupt did not occur
+ * @retval 1 Duty interrupt occurred
+ * @details This function is used to get duty interrupt flag of selected channel
+ */
+uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIF0_Msk | BPWM_INTSTS_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
+ * @return None
+ * @details This function is used to enable period interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
+{
+ (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk;
+}
+
+/**
+ * @brief Disable period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to disable period interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk;
+}
+
+/**
+ * @brief Clear period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to clear period interrupt of selected channel
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk;
+}
+
+/**
+ * @brief Get period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occur
+ * @retval 1 Period interrupt occurred
+ * @details This function is used to get period interrupt of selected channel
+ * @note All channels share channel 0's setting.
+ */
+uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to enable zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk;
+}
+
+/**
+ * @brief Disable zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to disable zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk;
+}
+
+/**
+ * @brief Clear zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to clear zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk;
+}
+
+/**
+ * @brief Get zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return zero interrupt flag of specified channel
+ * @retval 0 zero interrupt did not occur
+ * @retval 1 zero interrupt occurred
+ * @details This function is used to get zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable load mode of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode BPWM counter loading mode.
+ * - \ref BPWM_LOAD_MODE_IMMEDIATE
+ * - \ref BPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to enable load mode of selected channel.
+ */
+void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+ (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Disable load mode of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode PWM counter loading mode.
+ * - \ref BPWM_LOAD_MODE_IMMEDIATE
+ * - \ref BPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to disable load mode of selected channel.
+ */
+void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+ (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Set BPWM clock source
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32ClkSrcSel BPWM external clock source.
+ * - \ref BPWM_CLKSRC_BPWM_CLK
+ * - \ref BPWM_CLKSRC_TIMER0
+ * - \ref BPWM_CLKSRC_TIMER1
+ * - \ref BPWM_CLKSRC_TIMER2
+ * - \ref BPWM_CLKSRC_TIMER3
+ * @return None
+ * @details This function is used to set BPWM clock source.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
+{
+ (bpwm)->CLKSRC = (u32ClkSrcSel);
+}
+
+/**
+ * @brief Get the time-base counter reached its maximum value flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return Count to max interrupt flag of specified channel
+ * @retval 0 Count to max interrupt did not occur
+ * @retval 1 Count to max interrupt occurred
+ * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the time-base counter reached its maximum value flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * - BPWM0 : BPWM Group 0
+ * - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+ (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk;
+}
+
+
+/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group BPWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_can.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_can.c
new file mode 100644
index 00000000000..8186886c2f8
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_can.c
@@ -0,0 +1,1292 @@
+/**************************************************************************//**
+ * @file can.c
+ * @version V2.00
+ * @brief M480 series CAN driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+ @{
+*/
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+ @{
+*/
+
+/** @cond HIDDEN_SYMBOLS */
+
+#if defined(CAN2)
+static uint8_t gu8LockCanIf[3ul][2ul] = {0ul}; /* The chip has three CANs. */
+#elif defined(CAN1)
+static uint8_t gu8LockCanIf[2ul][2ul] = {0ul}; /* The chip has two CANs. */
+#elif defined(CAN0) || defined(CAN)
+static uint8_t gu8LockCanIf[1ul][2ul] = {0ul}; /* The chip only has one CAN. */
+#endif
+
+#define RETRY_COUNTS (0x10000000ul)
+
+#define TSEG1_MIN 2ul
+#define TSEG1_MAX 16ul
+#define TSEG2_MIN 1ul
+#define TSEG2_MAX 8ul
+#define BRP_MIN 1ul
+#define BRP_MAX 1024ul /* 6-bit BRP field + 4-bit BRPE field*/
+#define SJW_MAX 4ul
+#define BRP_INC 1ul
+
+/* #define DEBUG_PRINTF printf */
+#define DEBUG_PRINTF(...)
+
+static uint32_t LockIF(CAN_T *tCAN);
+static uint32_t LockIF_TL(CAN_T *tCAN);
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo);
+static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2);
+
+/**
+ * @brief Check if any interface is available then lock it for usage.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @retval 0 IF0 is free
+ * @retval 1 IF1 is free
+ * @retval 2 No IF is free
+ * @details Search the first free message interface, starting from 0. If a interface is
+ * available, set a flag to lock the interface.
+ */
+static uint32_t LockIF(CAN_T *tCAN)
+{
+ uint32_t u32CanNo;
+ uint32_t u32FreeIfNo;
+ uint32_t u32IntMask;
+
+#if defined(CAN1)
+ if(tCAN == CAN0)
+ u32CanNo = 0ul;
+ else if(tCAN == CAN1)
+ u32CanNo = 1ul;
+ #if defined(CAN2)
+ else if(tCAN == CAN2)
+ u32CanNo = 2ul;
+ #endif
+#else /* defined(CAN0) || defined(CAN) */
+ u32CanNo = 0ul;
+#endif
+
+ u32FreeIfNo = 2ul;
+
+ /* Disable CAN interrupt */
+ u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+ tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+ /* Check interface 1 is available or not */
+ if((tCAN->IF[0ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul)
+ {
+ if(gu8LockCanIf[u32CanNo][0ul] == 0ul)
+ {
+ gu8LockCanIf[u32CanNo][0ul] = 1u;
+ u32FreeIfNo = 0ul;
+ }
+ else
+ {
+ }
+ }
+ else
+ {
+ }
+
+ /* Or check interface 2 is available or not */
+ if(u32FreeIfNo == 2ul)
+ {
+ if((tCAN->IF[1ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul)
+ {
+ if(gu8LockCanIf[u32CanNo][1ul] == 0ul)
+ {
+ gu8LockCanIf[u32CanNo][1ul] = 1u;
+ u32FreeIfNo = 1ul;
+ }
+ else
+ {
+ }
+ }
+ else
+ {
+ }
+ }
+ else
+ {
+ }
+
+ /* Enable CAN interrupt */
+ tCAN->CON |= u32IntMask;
+
+ return u32FreeIfNo;
+}
+
+/**
+ * @brief Check if any interface is available in a time limitation then lock it for usage.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @retval 0 IF0 is free
+ * @retval 1 IF1 is free
+ * @retval 2 No IF is free
+ * @details Search the first free message interface, starting from 0. If no interface is
+ * it will try again until time out. If a interface is available, set a flag to
+ * lock the interface.
+ */
+static uint32_t LockIF_TL(CAN_T *tCAN)
+{
+ uint32_t u32Count;
+ uint32_t u32FreeIfNo;
+
+ for(u32Count = 0ul; u32Count < RETRY_COUNTS; u32Count++)
+ {
+ if((u32FreeIfNo = LockIF(tCAN)) != 2ul)
+ {
+ break;
+ }
+ else
+ {
+ }
+ }
+
+ return u32FreeIfNo;
+}
+
+/**
+ * @brief Release locked interface.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32Info The interface number, 0 or 1.
+ * @return none
+ * @details Release the locked interface.
+ */
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo)
+{
+ uint32_t u32IntMask;
+ uint32_t u32CanNo;
+
+ if(u32IfNo >= 2ul)
+ {
+ }
+ else
+ {
+#if defined(CAN1)
+ if(tCAN == CAN0)
+ u32CanNo = 0ul;
+ else if(tCAN == CAN1)
+ u32CanNo = 1ul;
+ #if defined(CAN2)
+ else if(tCAN == CAN2)
+ u32CanNo = 2ul;
+ #endif
+#else /* defined(CAN0) || defined(CAN) */
+ u32CanNo = 0ul;
+#endif
+
+ /* Disable CAN interrupt */
+ u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+ tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+ gu8LockCanIf[u32CanNo][u32IfNo] = 0u;
+
+ /* Enable CAN interrupt */
+ tCAN->CON |= u32IntMask;
+ }
+}
+
+static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2)
+{
+ *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000;
+ if (*tseg2 < TSEG2_MIN)
+ {
+ *tseg2 = TSEG2_MIN;
+ }
+ else
+ {
+ }
+
+ if (*tseg2 > TSEG2_MAX)
+ {
+ *tseg2 = TSEG2_MAX;
+ }
+ else
+ {
+ }
+
+ *tseg1 = tseg - *tseg2;
+ if (*tseg1 > TSEG1_MAX)
+ {
+ *tseg1 = TSEG1_MAX;
+ *tseg2 = tseg - *tseg1;
+ }
+ else
+ {
+ }
+
+ return 1000 * (tseg + 1 - *tseg2) / (tseg + 1);
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+ * @brief Enter initialization mode
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u8Mask Following values can be used.
+ * \ref CAN_CON_DAR_Msk Disable automatic retransmission.
+ * \ref CAN_CON_EIE_Msk Enable error interrupt.
+ * \ref CAN_CON_SIE_Msk Enable status interrupt.
+ * \ref CAN_CON_IE_Msk CAN interrupt.
+ * @return None
+ * @details This function is used to set CAN to enter initialization mode and enable access bit timing
+ * register. After bit timing configuration ready, user must call CAN_LeaveInitMode()
+ * to leave initialization mode and lock bit timing register to let new configuration
+ * take effect.
+ */
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask)
+{
+ tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+}
+
+
+/**
+ * @brief Leave initialization mode
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @return None
+ * @details This function is used to set CAN to leave initialization mode to let
+ * bit timing configuration take effect after configuration ready.
+ */
+void CAN_LeaveInitMode(CAN_T *tCAN)
+{
+ tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
+ while(tCAN->CON & CAN_CON_INIT_Msk)
+ {
+ /* Check INIT bit is released */
+ }
+}
+
+/**
+ * @brief Wait message into message buffer in basic mode.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @return None
+ * @details This function is used to wait message into message buffer in basic mode. Please notice the
+ * function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode.
+ */
+void CAN_WaitMsg(CAN_T *tCAN)
+{
+ tCAN->STATUS = 0x0ul; /* clr status */
+
+ while(1)
+ {
+ if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) /* check new data */
+ {
+ /* New Data IN */
+ break;
+ }
+ else
+ {
+ }
+
+ if(tCAN->STATUS & CAN_STATUS_RXOK_Msk)
+ {
+ /* Rx OK */
+ }
+ else
+ {
+ }
+
+ if(tCAN->STATUS & CAN_STATUS_LEC_Msk)
+ {
+ /* Error */
+ }
+ else
+ {
+ }
+ }
+}
+
+/**
+ * @brief Get current bit rate
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @return Current Bit-Rate (kilo bit per second)
+ * @details Return current CAN bit rate according to the user bit-timing parameter settings
+ */
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN)
+{
+ uint32_t u32Tseg1, u32Tseg2;
+ uint32_t u32Bpr;
+
+ u32Tseg1 = (tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos;
+ u32Tseg2 = (tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos;
+ u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk) | (tCAN->BRPE << 6ul);
+
+ return (SystemCoreClock / (u32Bpr + 1ul) / (u32Tseg1 + u32Tseg2 + 3ul));
+}
+
+/**
+ * @brief Switch the CAN into test mode.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u8TestMask Specifies the configuration in test modes
+ * \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode
+ * \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode
+ * \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode
+ * \ref CAN_TEST_Tx_Msk Control CAN_TX pin bit field
+ * @return None
+ * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/
+ * LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user
+ * must call CAN_LeaveInitMode() to let the setting take effect.
+ */
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask)
+{
+ tCAN->CON |= CAN_CON_TEST_Msk;
+ tCAN->TEST = u8TestMask;
+}
+
+
+/**
+ * @brief Leave the test mode
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @return None
+ * @details This function is used to Leave the test mode (switch into normal mode).
+ */
+void CAN_LeaveTestMode(CAN_T *tCAN)
+{
+ tCAN->CON |= CAN_CON_TEST_Msk;
+ tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk);
+ tCAN->CON &= (~CAN_CON_TEST_Msk);
+}
+
+/**
+ * @brief Get the waiting status of a received message.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+ * @retval non-zero The corresponding message object has a new data bit is set.
+ * @retval 0 No message object has new data.
+ * @details This function is used to get the waiting status of a received message.
+ */
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj)
+{
+ return (u8MsgObj < 16ul ? tCAN->NDAT1 & (1ul << u8MsgObj) : tCAN->NDAT2 & (1ul << (u8MsgObj - 16ul)));
+}
+
+
+/**
+ * @brief Send CAN message in BASIC mode of test mode
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] pCanMsg Pointer to the message structure containing data to transmit.
+ * @return TRUE: Transmission OK
+ * FALSE: Check busy flag of interface 0 is timeout
+ * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API,
+ * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter
+ * basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode.
+ */
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
+{
+ uint32_t i = 0ul;
+ int32_t rev = 1l;
+
+ while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk)
+ {
+ }
+
+ tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+ if(pCanMsg->IdType == CAN_STD_ID)
+ {
+ /* standard ID*/
+ tCAN->IF[0].ARB1 = 0ul;
+ tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2ul) ;
+ }
+ else
+ {
+ /* extended ID*/
+ tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFFul;
+ tCAN->IF[0].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16ul | CAN_IF_ARB2_XTD_Msk;
+
+ }
+
+ if(pCanMsg->FrameType)
+ {
+ tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk;
+ }
+ else
+ {
+ tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+ }
+
+ tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC;
+ tCAN->IF[0].DAT_A1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]);
+ tCAN->IF[0].DAT_A2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]);
+ tCAN->IF[0].DAT_B1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]);
+ tCAN->IF[0].DAT_B2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]);
+
+ /* request transmission*/
+ tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk);
+ if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk)
+ {
+ /* Cannot clear busy for sending ...*/
+ rev = 0l; /* return FALSE */
+ }
+ else
+ {
+ tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; /* sending */
+
+ for(i = 0ul; i < 0xFFFFFul; i++)
+ {
+ if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul)
+ {
+ break;
+ }
+ else
+ {
+ }
+ }
+
+ if(i >= 0xFFFFFul)
+ {
+ /* Cannot send out... */
+ rev = 0l; /* return FALSE */
+ }
+ else
+ {
+ }
+ }
+
+ return rev;
+}
+
+/**
+ * @brief Get a message information in BASIC mode.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+ *
+ * @return FALSE No any message received.
+ * TRUE Receive a message success.
+ *
+ */
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
+{
+ int32_t rev = 1l;
+
+ if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0ul)
+ {
+ /* In basic mode, receive data always save in IF2 */
+ rev = 0; /* return FALSE */
+ }
+ else
+ {
+
+ tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+ tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk
+ | CAN_IF_CMASK_CONTROL_Msk
+ | CAN_IF_CMASK_DATAA_Msk
+ | CAN_IF_CMASK_DATAB_Msk;
+
+ if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul)
+ {
+ /* standard ID*/
+ pCanMsg->IdType = CAN_STD_ID;
+ pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FFul;
+
+ }
+ else
+ {
+ /* extended ID*/
+ pCanMsg->IdType = CAN_EXT_ID;
+ pCanMsg->Id = (tCAN->IF[1].ARB2 & 0x1FFFul) << 16;
+ pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1;
+ }
+
+ pCanMsg->FrameType = (((tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) >> CAN_IF_ARB2_DIR_Pos)) ? 0ul : 1ul;
+
+ pCanMsg->DLC = (uint8_t)(tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk);
+ pCanMsg->Data[0] = (uint8_t)(tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk);
+ pCanMsg->Data[1] = (uint8_t)((tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos);
+ pCanMsg->Data[2] = (uint8_t)(tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk);
+ pCanMsg->Data[3] = (uint8_t)((tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos);
+ pCanMsg->Data[4] = (uint8_t)(tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk);
+ pCanMsg->Data[5] = (uint8_t)((tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos);
+ pCanMsg->Data[6] = (uint8_t)(tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk);
+ pCanMsg->Data[7] = (uint8_t)((tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos);
+ }
+
+ return rev;
+}
+
+/**
+ * @brief Set Rx message object, include ID mask.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+ * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+ * This parameter can be one of the following values:
+ * \ref CAN_STD_ID (standard ID, 11-bit)
+ * \ref CAN_EXT_ID (extended ID, 29-bit)
+ * @param[in] u32id Specifies the identifier used for acceptance filtering.
+ * @param[in] u32idmask Specifies the identifier mask used for acceptance filtering.
+ * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+ * This parameter can be one of the following values:
+ * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+ * FALSE: for a FIFO receive object that is not the last one.
+ * @retval TRUE SUCCESS
+ * @retval FALSE No useful interface
+ * @details The function is used to configure a receive message object.
+ */
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast)
+{
+ int32_t rev = 1l;
+ uint32_t u32MsgIfNum;
+
+ /* Get and lock a free interface */
+ if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+ {
+ rev = 0; /* return FALSE */
+ }
+ else
+ {
+ /* Command Setting */
+ tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+ CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+ if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */
+ {
+ tCAN->IF[u32MsgIfNum].ARB1 = 0ul;
+ tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2;
+ }
+ else
+ {
+ tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul;
+ tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16;
+ }
+
+ tCAN->IF[u32MsgIfNum].MASK1 = (u32idmask & 0xFFFFul);
+ tCAN->IF[u32MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFFul;
+
+ /* tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */
+ tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+ if(u8singleOrFifoLast)
+ {
+ tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+ }
+ else
+ {
+ tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+ }
+
+ tCAN->IF[u32MsgIfNum].DAT_A1 = 0ul;
+ tCAN->IF[u32MsgIfNum].DAT_A2 = 0ul;
+ tCAN->IF[u32MsgIfNum].DAT_B1 = 0ul;
+ tCAN->IF[u32MsgIfNum].DAT_B2 = 0ul;
+
+ tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj;
+ ReleaseIF(tCAN, u32MsgIfNum);
+ }
+
+ return rev;
+}
+
+/**
+ * @brief Set Rx message object
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+ * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+ * This parameter can be one of the following values:
+ * \ref CAN_STD_ID (standard ID, 11-bit)
+ * \ref CAN_EXT_ID (extended ID, 29-bit)
+ * @param[in] u32id Specifies the identifier used for acceptance filtering.
+ * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+ * This parameter can be one of the following values:
+ * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+ * FALSE: for a FIFO receive object that is not the last one.
+ * @retval TRUE SUCCESS
+ * @retval FALSE No useful interface
+ * @details The function is used to configure a receive message object.
+ */
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast)
+{
+ int32_t rev = 1l;
+ uint32_t u32MsgIfNum;
+
+ /* Get and lock a free interface */
+ if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+ {
+ rev = 0; /* return FALSE */
+ }
+ else
+ {
+ /* Command Setting */
+ tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+ CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+ if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */
+ {
+ tCAN->IF[u32MsgIfNum].ARB1 = 0ul;
+ tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2;
+ }
+ else
+ {
+ tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul;
+ tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16;
+ }
+
+ /* tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */
+ tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+ if(u8singleOrFifoLast)
+ {
+ tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+ }
+ else
+ {
+ tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+ }
+
+ tCAN->IF[u32MsgIfNum].DAT_A1 = 0ul;
+ tCAN->IF[u32MsgIfNum].DAT_A2 = 0ul;
+ tCAN->IF[u32MsgIfNum].DAT_B1 = 0ul;
+ tCAN->IF[u32MsgIfNum].DAT_B2 = 0ul;
+
+ tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj;
+ ReleaseIF(tCAN, u32MsgIfNum);
+ }
+
+ return rev;
+}
+
+/**
+ * @brief Gets the message
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+ * @param[in] u8Release Specifies the message release indicator.
+ * This parameter can be one of the following values:
+ * TRUE: the message object is released when getting the data.
+ * FALSE:the message object is not released.
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+ * @retval TRUE Success
+ * @retval FALSE No any message received
+ * @details Gets the message, if received.
+ */
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg)
+{
+ int32_t rev = 1l;
+ uint32_t u32MsgIfNum;
+
+ if(!CAN_IsNewDataReceived(tCAN, u8MsgObj))
+ {
+ rev = 0; /* return FALSE */
+ }
+ else
+ {
+ /* Get and lock a free interface */
+ if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+ {
+ rev = 0; /* return FALSE */
+ }
+ else
+ {
+ tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+ /* read the message contents*/
+ tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk
+ | CAN_IF_CMASK_ARB_Msk
+ | CAN_IF_CMASK_CONTROL_Msk
+ | CAN_IF_CMASK_CLRINTPND_Msk
+ | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0ul)
+ | CAN_IF_CMASK_DATAA_Msk
+ | CAN_IF_CMASK_DATAB_Msk;
+
+ tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj;
+
+ while(tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
+ {
+ /*Wait*/
+ }
+
+ if((tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul)
+ {
+ /* standard ID*/
+ pCanMsg->IdType = CAN_STD_ID;
+ pCanMsg->Id = (tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2ul;
+ }
+ else
+ {
+ /* extended ID*/
+ pCanMsg->IdType = CAN_EXT_ID;
+ pCanMsg->Id = (((tCAN->IF[u32MsgIfNum].ARB2) & 0x1FFFul) << 16) | tCAN->IF[u32MsgIfNum].ARB1;
+ }
+
+ pCanMsg->DLC = (uint8_t)(tCAN->IF[u32MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk);
+ pCanMsg->Data[0] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk);
+ pCanMsg->Data[1] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos);
+ pCanMsg->Data[2] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk);
+ pCanMsg->Data[3] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos);
+ pCanMsg->Data[4] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk);
+ pCanMsg->Data[5] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos);
+ pCanMsg->Data[6] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk);
+ pCanMsg->Data[7] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos);
+
+ ReleaseIF(tCAN, u32MsgIfNum);
+ }
+ }
+
+ return rev;
+}
+
+
+/**
+ * @brief Set bus baud-rate.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+ *
+ * @return u32CurrentBitRate Real baud-rate value.
+ *
+ * @details The function is used to set bus timing parameter according current clock and target baud-rate.
+ */
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
+{
+ long rate;
+ long best_error = 1000000000, error = 0;
+ int best_tseg = 0, best_brp = 0, brp = 0;
+ int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0;
+ int spt_error = 1000, spt = 0, sampl_pt;
+ uint64_t clock_freq = (uint64_t)0, u64PCLK_DIV = (uint64_t)1;
+ uint32_t sjw = (uint32_t)1;
+
+ CAN_EnterInitMode(tCAN, (uint8_t)0);
+
+ SystemCoreClockUpdate();
+ if((tCAN == CAN0) || (tCAN == CAN2))
+ {
+ u64PCLK_DIV = (uint64_t)(CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk);
+ u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV);
+ }
+ else if(tCAN == CAN1)
+ {
+ u64PCLK_DIV = (uint64_t)((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) >> CLK_PCLKDIV_APB1DIV_Pos);
+ u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV);
+ }
+
+ clock_freq = SystemCoreClock / u64PCLK_DIV;
+
+ if(u32BaudRate >= (uint32_t)1000000)
+ {
+ u32BaudRate = (uint32_t)1000000;
+ }
+
+ /* Use CIA recommended sample points */
+ if (u32BaudRate > (uint32_t)800000)
+ {
+ sampl_pt = (int)750;
+ }
+ else if (u32BaudRate > (uint32_t)500000)
+ {
+ sampl_pt = (int)800;
+ }
+ else
+ {
+ sampl_pt = (int)875;
+ }
+
+ /* tseg even = round down, odd = round up */
+ for (tseg = (TSEG1_MAX + TSEG2_MAX) * 2ul + 1ul; tseg >= (TSEG1_MIN + TSEG2_MIN) * 2ul; tseg--)
+ {
+ tsegall = 1ul + tseg / 2ul;
+ /* Compute all possible tseg choices (tseg=tseg1+tseg2) */
+ brp = clock_freq / (tsegall * u32BaudRate) + tseg % 2;
+ /* chose brp step which is possible in system */
+ brp = (brp / BRP_INC) * BRP_INC;
+
+ if ((brp < BRP_MIN) || (brp > BRP_MAX))
+ {
+ continue;
+ }
+ rate = clock_freq / (brp * tsegall);
+
+ error = u32BaudRate - rate;
+
+ /* tseg brp biterror */
+ if (error < 0)
+ {
+ error = -error;
+ }
+ if (error > best_error)
+ {
+ continue;
+ }
+ best_error = error;
+ if (error == 0)
+ {
+ spt = can_update_spt(sampl_pt, tseg / 2, &tseg1, &tseg2);
+ error = sampl_pt - spt;
+ if (error < 0)
+ {
+ error = -error;
+ }
+ if (error > spt_error)
+ {
+ continue;
+ }
+ spt_error = error;
+ }
+ best_tseg = tseg / 2;
+ best_brp = brp;
+
+ if (error == 0)
+ {
+ break;
+ }
+ }
+
+ spt = can_update_spt(sampl_pt, best_tseg, &tseg1, &tseg2);
+
+ /* check for sjw user settings */
+ /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */
+ if (sjw > SJW_MAX)
+ {
+ sjw = SJW_MAX;
+ }
+ /* bt->sjw must not be higher than tseg2 */
+ if (tseg2 < sjw)
+ {
+ sjw = tseg2;
+ }
+
+ /* real bit-rate */
+ u32BaudRate = clock_freq / (best_brp * (tseg1 + tseg2 + 1));
+
+ tCAN->BTIME = ((uint32_t)(tseg2 - 1ul) << CAN_BTIME_TSEG2_Pos) | ((uint32_t)(tseg1 - 1ul) << CAN_BTIME_TSEG1_Pos) |
+ ((uint32_t)(best_brp - 1ul) & CAN_BTIME_BRP_Msk) | (sjw << CAN_BTIME_SJW_Pos);
+ tCAN->BRPE = ((uint32_t)(best_brp - 1ul) >> 6) & 0x0Ful;
+
+ /* printf("\n bitrate = %d \n", CAN_GetCANBitRate(tCAN)); */
+
+ CAN_LeaveInitMode(tCAN);
+
+ return u32BaudRate;
+}
+
+/**
+ * @brief The function is used to disable all CAN interrupt.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ *
+ * @return None
+ *
+ * @details No Status Change Interrupt and Error Status Interrupt will be generated.
+ */
+void CAN_Close(CAN_T *tCAN)
+{
+ CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+ * @brief Set CAN operation mode and target baud-rate.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+ * @param[in] u32Mode The CAN operation mode. Valid values are:
+ * - \ref CAN_NORMAL_MODE Normal operation.
+ * - \ref CAN_BASIC_MODE Basic mode.
+ * @return u32CurrentBitRate Real baud-rate value.
+ *
+ * @details Set bus timing parameter according current clock and target baud-rate.
+ * In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+ */
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode)
+{
+ uint32_t u32CurrentBitRate;
+
+ u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate);
+
+ if(u32Mode == CAN_BASIC_MODE)
+ {
+ CAN_EnterTestMode(tCAN, (uint8_t)CAN_TEST_BASIC_Msk);
+ }
+ else
+ {
+ }
+
+ return u32CurrentBitRate;
+}
+
+/**
+ * @brief The function is used to configure a transmit object.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+ *
+ * @retval FALSE No useful interface.
+ * @retval TRUE Config message object success.
+ *
+ * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM.
+ * They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.
+ */
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg)
+{
+ int32_t rev = 1l;
+ uint32_t u32MsgIfNum;
+
+ if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+ {
+ rev = 0; /* return FALSE */
+ }
+ else
+ {
+ /* update the contents needed for transmission*/
+ tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+ CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+ if(pCanMsg->IdType == CAN_STD_ID)
+ {
+ /* standard ID*/
+ tCAN->IF[u32MsgIfNum].ARB1 = 0ul;
+ tCAN->IF[u32MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+ }
+ else
+ {
+ /* extended ID*/
+ tCAN->IF[u32MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFFul;
+ tCAN->IF[u32MsgIfNum].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16 |
+ CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+ }
+
+ if(pCanMsg->FrameType)
+ {
+ tCAN->IF[u32MsgIfNum].ARB2 |= CAN_IF_ARB2_DIR_Msk;
+ }
+ else
+ {
+ tCAN->IF[u32MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+ }
+
+ tCAN->IF[u32MsgIfNum].DAT_A1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[1] << 8)) | pCanMsg->Data[0]);
+ tCAN->IF[u32MsgIfNum].DAT_A2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[3] << 8)) | pCanMsg->Data[2]);
+ tCAN->IF[u32MsgIfNum].DAT_B1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[5] << 8)) | pCanMsg->Data[4]);
+ tCAN->IF[u32MsgIfNum].DAT_B2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[7] << 8)) | pCanMsg->Data[6]);
+
+ tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk;
+ tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum;
+
+ ReleaseIF(tCAN, u32MsgIfNum);
+ }
+
+ return rev;
+}
+
+/**
+ * @brief Set transmit request bit.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ *
+ * @return TRUE: Start transmit message.
+ *
+ * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored.
+ */
+int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum)
+{
+ int32_t rev = 1l;
+ uint32_t u32MsgIfNum;
+
+ if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+ {
+ rev = 0; /* return FALSE */
+ }
+ else
+ {
+ tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+ /* read the message contents*/
+ tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk
+ | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+
+ tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum;
+
+ while(tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
+ {
+ /*Wait*/
+ }
+ tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+ tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum;
+
+ ReleaseIF(tCAN, u32MsgIfNum);
+ }
+
+ return rev;
+}
+
+/**
+ * @brief Enable CAN interrupt.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32Mask Interrupt Mask. Valid values are:
+ * - \ref CAN_CON_IE_Msk Module interrupt enable.
+ * - \ref CAN_CON_SIE_Msk Status change interrupt enable.
+ * - \ref CAN_CON_EIE_Msk Error interrupt enable.
+ *
+ * @return None
+ *
+ * @details The application software has two possibilities to follow the source of a message interrupt.
+ * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register.
+ */
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+ tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) |
+ (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+ * @brief Disable CAN interrupt.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk).
+ *
+ * @return None
+ *
+ * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
+ */
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+ tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)));
+}
+
+
+/**
+ * @brief The function is used to configure a receive message object.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+ * - \ref CAN_STD_ID The 11-bit identifier.
+ * - \ref CAN_EXT_ID The 29-bit identifier.
+ * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+ *
+ * @retval FALSE No useful interface.
+ * @retval TRUE Configure a receive message object success.
+ *
+ * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+ * will be set when a received Data Frame is accepted and stored in the Message Object.
+ */
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID)
+{
+ int32_t rev = (int32_t)TRUE;
+ uint32_t u32TimeOutCount = 0ul;
+
+ while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)TRUE) == (int32_t)FALSE)
+ {
+ if(++u32TimeOutCount >= RETRY_COUNTS)
+ {
+ rev = (int32_t)(FALSE); /* return FALSE */
+ break;
+ }
+ else
+ {
+ }
+ }
+
+ return rev;
+}
+
+/**
+ * @brief The function is used to configure a receive message object.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+ * - \ref CAN_STD_ID The 11-bit identifier.
+ * - \ref CAN_EXT_ID The 29-bit identifier.
+ * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+ * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering.
+ *
+ * @retval FALSE No useful interface.
+ * @retval TRUE Configure a receive message object success.
+ *
+ * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+ * will be set when a received Data Frame is accepted and stored in the Message Object.
+ */
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask)
+{
+ int32_t rev = (int32_t)TRUE;
+ uint32_t u32TimeOutCount = 0ul;
+
+ while(CAN_SetRxMsgObjAndMsk(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, u32IDMask, (uint8_t)TRUE) == (int32_t)FALSE)
+ {
+ if(++u32TimeOutCount >= RETRY_COUNTS)
+ {
+ rev = (int32_t)FALSE;
+ break;
+ }
+ else
+ {
+ }
+ }
+
+ return rev;
+}
+
+/**
+ * @brief The function is used to configure several receive message objects.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31).
+ * @param[in] u32MsgCount the number of MSG RAM of the FIFO.
+ * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+ * - \ref CAN_STD_ID The 11-bit identifier.
+ * - \ref CAN_EXT_ID The 29-bit identifier.
+ * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+ *
+ * @retval FALSE No useful interface.
+ * @retval TRUE Configure receive message objects success.
+ *
+ * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+ * and transmission by buffering the data to be transferred.
+ */
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID)
+{
+ int32_t rev = (int32_t)TRUE;
+ uint32_t i = 0ul;
+ uint32_t u32TimeOutCount;
+ uint32_t u32EOB_Flag = 0ul;
+
+ for(i = 1ul; i < u32MsgCount; i++)
+ {
+ u32TimeOutCount = 0ul;
+
+ u32MsgNum += (i - 1ul);
+
+ if(i == u32MsgCount)
+ {
+ u32EOB_Flag = 1ul;
+ }
+ else
+ {
+ }
+
+ while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)u32EOB_Flag) == (int32_t)FALSE)
+ {
+ if(++u32TimeOutCount >= RETRY_COUNTS)
+ {
+ rev = (int32_t)FALSE;
+ break;
+ }
+ else
+ {
+ }
+ }
+ }
+
+ return rev;
+}
+
+
+/**
+ * @brief Send CAN message.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+ *
+ * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n
+ * 2. When operation in normal mode: No useful interface. \n
+ * @retval TRUE Transmit Message success.
+ *
+ * @details The receive/transmit priority for the Message Objects is attached to the message number.
+ * Message Object 1 has the highest priority, while Message Object 32 has the lowest priority.
+ */
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg)
+{
+ int32_t rev = (int32_t)TRUE;
+ uint32_t u32Tmp;
+
+ u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk);
+
+ if((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp)
+ {
+ rev = CAN_BasicSendMsg(tCAN, pCanMsg);
+ }
+ else
+ {
+ if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == FALSE)
+ {
+ rev = (int32_t)FALSE;
+ }
+ else
+ {
+ CAN_TriggerTxMsg(tCAN, u32MsgNum);
+ }
+ }
+
+ return rev;
+}
+
+
+/**
+ * @brief Gets the message, if received.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+ *
+ * @retval FALSE No any message received.
+ * @retval TRUE Receive Message success.
+ *
+ * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+ * and transmission by buffering the data to be transferred.
+ */
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg)
+{
+ int32_t rev = (int32_t)TRUE;
+ uint32_t u32Tmp;
+
+ u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk);
+
+ if((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp)
+ {
+ rev = CAN_BasicReceiveMsg(tCAN, pCanMsg);
+ }
+ else
+ {
+ rev = CAN_ReadMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)TRUE, pCanMsg);
+ }
+
+ return rev;
+}
+
+/**
+ * @brief Clear interrupt pending bit.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ *
+ * @return None
+ *
+ * @details An interrupt remains pending until the application software has cleared it.
+ */
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum)
+{
+ uint32_t u32MsgIfNum;
+
+ if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+ {
+ u32MsgIfNum = 0ul;
+ }
+ else
+ {
+ }
+
+ tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+ tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum;
+
+ ReleaseIF(tCAN, u32MsgIfNum);
+}
+
+
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CAN_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ccap.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ccap.c
new file mode 100644
index 00000000000..5da53eb79b5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ccap.c
@@ -0,0 +1,296 @@
+/**************************************************************************//**
+ * @file ccap.c
+ * @version V1.00
+ * @brief M480 Series CCAP Driver Source File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include "NuMicro.h"
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CCAP_Driver CCAP Driver
+ @{
+*/
+
+
+/** @addtogroup CCAP_EXPORTED_FUNCTIONS CCAP Exported Functions
+ @{
+*/
+
+/**
+ * @brief Open engine clock and sensor clock
+ *
+ * @param[in] u32InFormat The bits corresponding VSP, HSP, PCLK, INFMT, SNRTYPE, OUTFMT, PDORD and PNFMT configurations.
+ * - VSP should be ether \ref CCAP_PAR_VSP_LOW or \ref CCAP_PAR_VSP_HIGH
+ * - HSP should be ether \ref CCAP_PAR_HSP_LOW or \ref CCAP_PAR_HSP_HIGH
+ * - PCLK should be ether \ref CCAP_PAR_PCLKP_LOW or \ref CCAP_PAR_PCLKP_HIGH
+ * - INFMT should be ether \ref CCAP_PAR_INFMT_YUV422 or \ref CCAP_PAR_INFMT_RGB565
+ * - SNRTYPE should be ether \ref CCAP_PAR_SENTYPE_CCIR601 or \ref CCAP_PAR_SENTYPE_CCIR656
+ * - OUTFMT should be one of the following setting
+ * - \ref CCAP_PAR_OUTFMT_YUV422
+ * - \ref CCAP_PAR_OUTFMT_ONLY_Y
+ * - \ref CCAP_PAR_OUTFMT_RGB555
+ * - \ref CCAP_PAR_OUTFMT_RGB565
+ * - PDORD should be one of the following setting
+ * - \ref CCAP_PAR_INDATORD_YUYV
+ * - \ref CCAP_PAR_INDATORD_YVYU
+ * - \ref CCAP_PAR_INDATORD_UYVY
+ * - \ref CCAP_PAR_INDATORD_VYUY
+ * - \ref CCAP_PAR_INDATORD_RGGB
+ * - \ref CCAP_PAR_INDATORD_BGGR
+ * - \ref CCAP_PAR_INDATORD_GBRG
+ * - \ref CCAP_PAR_INDATORD_GRBG
+ * - PNFMT should be one of the following setting
+ * - \ref CCAP_PAR_PLNFMT_YUV422
+ * - \ref CCAP_PAR_PLNFMT_YUV420
+ *
+ * @param[in] u32OutFormet Capture output format, should be one of following setting
+ * - \ref CCAP_CTL_PKTEN
+ *
+ * @return None
+ *
+ * @details Initialize the Image Capture Interface. Register a call back for driver internal using
+ */
+void CCAP_Open(uint32_t u32InFormat, uint32_t u32OutFormet)
+{
+ CCAP->PAR = (CCAP->PAR & ~(0x000007BFUL)) | u32InFormat;
+ CCAP->CTL = (CCAP->CTL & ~(0x00000040UL)) | u32OutFormet;
+}
+
+/**
+ * @brief Set Cropping Window Starting Address and Size
+ *
+ * @param[in] u32VStart: Cropping Window Vertical Starting Address. It should be 0 ~ 0x7FF.
+ *
+ * @param[in] u32HStart: Cropping Window Horizontal Starting Address. It should be 0 ~ 0x7FF.
+ *
+ * @param[in] u32Height: Cropping Window Height . It should be 0 ~ 0x7FF.
+ *
+ * @param[in] u32Width: Cropping Window Width. It should be 0 ~ 0x7FF.
+ *
+ * @return None
+ *
+ * @details Set Cropping Window Starting Address Register
+ */
+void CCAP_SetCroppingWindow(uint32_t u32VStart,uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width)
+{
+ CCAP->CWSP = (CCAP->CWSP & ~(CCAP_CWSP_CWSADDRV_Msk | CCAP_CWSP_CWSADDRH_Msk))
+ | (((u32VStart << 16) | u32HStart));
+
+ CCAP->CWS = (CCAP->CWS & ~(CCAP_CWS_CWH_Msk | CCAP_CWS_CWW_Msk))
+ | ((u32Height << 16)| u32Width);
+}
+
+
+/**
+ * @brief Set System Memory Packet Base Address0 Register
+ *
+ * @param[in] u32Address : set PKTBA0 register, It should be 0x0 ~ 0xFFFFFFFF
+ *
+ * @return None
+ *
+ * @details Set System Memory Packet Base Address Register
+ */
+void CCAP_SetPacketBuf(uint32_t u32Address )
+{
+ CCAP->PKTBA0 = u32Address;
+ CCAP->CTL |= CCAP_CTL_UPDATE_Msk;
+}
+
+/**
+ * @brief Close Camera Capture Interface
+ *
+ * @return None
+ */
+void CCAP_Close(void)
+{
+ CCAP->CTL &= ~CCAP_CTL_CCAPEN;
+}
+
+
+/**
+ * @brief Set CCAP Interrupt
+ *
+ * @param[in] u32IntMask Interrupt settings. It could be
+ * - \ref CCAP_INT_VIEN_Msk
+ * - \ref CCAP_INT_MEIEN_Msk
+ * - \ref CCAP_INT_ADDRMIEN_Msk
+ * @return None
+ *
+ * @details Set Video Frame End Interrupt Enable,
+ * System Memory Error Interrupt Enable,
+ * Address Match Interrupt Enable,
+ * Motion Detection Output Finish Interrupt Enable.
+ */
+void CCAP_EnableInt(uint32_t u32IntMask)
+{
+ CCAP->INT = (CCAP->INT & ~(CCAP_INT_VIEN_Msk | CCAP_INT_MEIEN_Msk | CCAP_INT_ADDRMIEN_Msk ) )
+ | u32IntMask;
+}
+
+/**
+ * @brief Disable CCAP Interrupt
+ *
+ * @param[in] u32IntMask Interrupt settings. It could be
+ * - \ref CCAP_INT_VINTF_Msk
+ * - \ref CCAP_INT_MEINTF_Msk
+ * - \ref CCAP_INT_ADDRMINTF_Msk
+
+ * @return None
+ *
+ * @details Disable Video Frame End Interrupt ,
+ * System Memory Error Interrupt ,
+ * Address Match Interrupt and
+ * Motion Detection Output Finish Interrupt .
+ */
+void CCAP_DisableInt(uint32_t u32IntMask)
+{
+ CCAP->INT = (CCAP->INT & ~(u32IntMask) ) ;
+}
+
+
+/**
+ * @brief Enable Monochrome CMOS Sensor
+ *
+ * @param[in] u32Interface I/O interface settings. It could be
+ * - \ref CCAP_CTL_MY8_MY4
+ * - \ref CCAP_CTL_MY8_MY8
+ * @return None
+ *
+ */
+void CCAP_EnableMono(uint32_t u32Interface)
+{
+ CCAP->CTL = (CCAP->CTL & ~CCAP_CTL_MY8_MY4) | CCAP_CTL_MONO_Msk |u32Interface;
+}
+
+/**
+ * @brief Disable Monochrome CMOS Sensor
+ *
+ * @return None
+ *
+ */
+void CCAP_DisableMono(void)
+{
+ CCAP->CTL |= CCAP_CTL_MONO_Msk;
+}
+
+/**
+ * @brief Enable Luminance 8-bit Y to 1-bit Y Conversion
+ *
+ * @param[in] u32th Luminance Y8 to Y1 Threshold Value, It should be 0 ~ 255.
+ *
+ * @return None
+ *
+ */
+void CCAP_EnableLumaYOne(uint32_t u32th)
+{
+ CCAP->CTL |= CCAP_CTL_Luma_Y_One_Msk;
+ CCAP->LUMA_Y1_THD = u32th & 0xff;
+}
+
+/**
+ * @brief Disable Luminance 8-bit Y to 1-bit Y Conversion
+ *
+ * @return None
+ *
+ */
+void CCAP_DisableLumaYOne(void)
+{
+ CCAP->CTL &= ~CCAP_CTL_Luma_Y_One_Msk;
+}
+
+/**
+ * @brief Start Camera Capture Interface
+ *
+ * @return None
+ */
+void CCAP_Start(void)
+{
+ CCAP->CTL |= CCAP_CTL_CCAPEN;
+}
+
+/**
+ * @brief Stop Camera Capture Interface
+ *
+ * @param[in] u32FrameComplete :
+ * TRUE: Capture module automatically disable the CCAP module after a frame had been captured
+ * FALSE: Stop Capture module now
+ * @return None
+ *
+ * @details if u32FrameComplete is set to TRUE then get a new frame and disable CCAP module
+ */
+void CCAP_Stop(uint32_t u32FrameComplete)
+{
+ if(u32FrameComplete==FALSE)
+ CCAP->CTL &= ~CCAP_CTL_CCAPEN;
+ else
+ {
+ CCAP->CTL |= CCAP_CTL_SHUTTER_Msk;
+ while(CCAP_IS_STOPPED());
+ }
+}
+
+/**
+ * @brief Set Packet Scaling Vertical and Horizontal Factor Register
+ *
+ * @param[in] u32VNumerator: Packet Scaling Vertical Factor N. It should be 0 ~ FFFF.
+ *
+ * @param[in] u32VDenominator: Packet Scaling Vertical Factor M. It should be 0 ~ FFFF.
+ *
+ * @param[in] u32HNumerator: Packet Scaling Vertical Factor N. It should be 0 ~ FFFF.
+ *
+ * @param[in] u32HDenominator: Packet Scaling Vertical Factor M. It should be 0 ~ FFFF.
+ *
+ * @return None
+ *
+ */
+void CCAP_SetPacketScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator)
+{
+ uint32_t u32NumeratorL, u32NumeratorH;
+ uint32_t u32DenominatorL, u32DenominatorH;
+
+ u32NumeratorL = u32VNumerator&0xFF;
+ u32NumeratorH=u32VNumerator>>8;
+ u32DenominatorL = u32VDenominator&0xFF;
+ u32DenominatorH = u32VDenominator>>8;
+ CCAP->PKTSL = (CCAP->PKTSL & ~(CCAP_PKTSL_PKTSVNL_Msk | CCAP_PKTSL_PKTSVML_Msk))
+ | ((u32NumeratorL << 24)| (u32DenominatorL << 16));
+ CCAP->PKTSM = (CCAP->PKTSM & ~(CCAP_PKTSM_PKTSVNH_Msk | CCAP_PKTSM_PKTSVMH_Msk))
+ | ((u32NumeratorH << 24) | (u32DenominatorH << 16));
+
+ u32NumeratorL = u32HNumerator&0xFF;
+ u32NumeratorH=u32HNumerator>>8;
+ u32DenominatorL = u32HDenominator&0xFF;
+ u32DenominatorH = u32HDenominator>>8;
+ CCAP->PKTSL = (CCAP->PKTSL & ~(CCAP_PKTSL_PKTSHNL_Msk | CCAP_PKTSL_PKTSHML_Msk))
+ | ((u32NumeratorL << 8)| u32DenominatorL);
+ CCAP->PKTSM = (CCAP->PKTSM & ~(CCAP_PKTSM_PKTSHNH_Msk | CCAP_PKTSM_PKTSHMH_Msk))
+ | ((u32NumeratorH << 8) | u32DenominatorH);
+}
+
+/**
+ * @brief Set Packet Frame Output Pixel Stride Width.
+ *
+ * @param[in] u32Stride : set PKTSTRIDE register, It should be 0x0 ~ 0x3FFF
+ *
+ * @return None
+ *
+ * @details Set Packet Frame Output Pixel Stride Width
+ */
+void CCAP_SetPacketStride(uint32_t u32Stride )
+{
+ CCAP->STRIDE = (CCAP->STRIDE & ~CCAP_STRIDE_PKTSTRIDE_Msk) | u32Stride;
+}
+
+
+/*@}*/ /* end of group CCAP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CCAP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_clk.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_clk.c
new file mode 100644
index 00000000000..1a23b44e10e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_clk.c
@@ -0,0 +1,1353 @@
+/**************************************************************************//**
+ * @file clk.c
+ * @version V3.00
+ * @brief M480 series CLK driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CLK_Driver CLK Driver
+ @{
+*/
+
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+ @{
+*/
+
+/**
+ * @brief Disable clock divider output function
+ * @param None
+ * @return None
+ * @details This function disable clock divider output function.
+ */
+void CLK_DisableCKO(void)
+{
+ /* Disable CKO clock source */
+ CLK_DisableModuleClock(CLKO_MODULE);
+}
+
+/**
+ * @brief This function enable clock divider output module clock,
+ * enable clock divider output function and set frequency selection.
+ * @param[in] u32ClkSrc is frequency divider function clock source. Including :
+ * - \ref CLK_CLKSEL1_CLKOSEL_HXT
+ * - \ref CLK_CLKSEL1_CLKOSEL_LXT
+ * - \ref CLK_CLKSEL1_CLKOSEL_HCLK
+ * - \ref CLK_CLKSEL1_CLKOSEL_HIRC
+ * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15.
+ * @param[in] u32ClkDivBy1En is clock divided by one enabled.
+ * @return None
+ * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n
+ * The formula is: \n
+ * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n
+ * This function is just used to set CKO clock.
+ * User must enable I/O for CKO clock output pin by themselves. \n
+ */
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
+{
+ /* CKO = clock source / 2^(u32ClkDiv + 1) */
+ CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
+
+ /* Enable CKO clock source */
+ CLK_EnableModuleClock(CLKO_MODULE);
+
+ /* Select CKO clock source */
+ CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0UL);
+}
+
+/**
+ * @brief Enter to Power-down mode
+ * @param None
+ * @return None
+ * @details This function is used to let system enter to Power-down mode. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_PowerDown(void)
+{
+ uint32_t u32HIRCTRIMCTL;
+
+ /* Set the processor uses deep sleep as its low power mode */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Set system Power-down enabled */
+ CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk);
+
+ /* Store HIRC control register */
+ u32HIRCTRIMCTL = SYS->IRCTCTL;
+
+ /* Disable HIRC auto trim */
+ SYS->IRCTCTL &= (~SYS_IRCTCTL_FREQSEL_Msk);
+
+ /* Chip enter Power-down mode after CPU run WFI instruction */
+ __WFI();
+
+ /* Restore HIRC control register */
+ SYS->IRCTCTL = u32HIRCTRIMCTL;
+}
+
+/**
+ * @brief Enter to Idle mode
+ * @param None
+ * @return None
+ * @details This function let system enter to Idle mode. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_Idle(void)
+{
+ /* Set the processor uses sleep as its low power mode */
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Set chip in idle mode because of WFI command */
+ CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
+
+ /* Chip enter idle mode after CPU run WFI instruction */
+ __WFI();
+}
+
+/**
+ * @brief Get external high speed crystal clock frequency
+ * @param None
+ * @return External high frequency crystal frequency
+ * @details This function get external high frequency crystal frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetHXTFreq(void)
+{
+ uint32_t u32Freq;
+
+ if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk)
+ {
+ u32Freq = __HXT;
+ }
+ else
+ {
+ u32Freq = 0UL;
+ }
+
+ return u32Freq;
+}
+
+
+/**
+ * @brief Get external low speed crystal clock frequency
+ * @param None
+ * @return External low speed crystal clock frequency
+ * @details This function get external low frequency crystal frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetLXTFreq(void)
+{
+ uint32_t u32Freq;
+ if((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk)
+ {
+ u32Freq = __LXT;
+ }
+ else
+ {
+ u32Freq = 0UL;
+ }
+
+ return u32Freq;
+}
+
+/**
+ * @brief Get PCLK0 frequency
+ * @param None
+ * @return PCLK0 frequency
+ * @details This function get PCLK0 frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetPCLK0Freq(void)
+{
+ uint32_t u32Freq;
+ SystemCoreClockUpdate();
+
+ if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV1)
+ {
+ u32Freq = SystemCoreClock;
+ }
+ else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV2)
+ {
+ u32Freq = SystemCoreClock / 2UL;
+ }
+ else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV4)
+ {
+ u32Freq = SystemCoreClock / 4UL;
+ }
+ else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV8)
+ {
+ u32Freq = SystemCoreClock / 8UL;
+ }
+ else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV16)
+ {
+ u32Freq = SystemCoreClock / 16UL;
+ }
+ else
+ {
+ u32Freq = SystemCoreClock;
+ }
+
+ return u32Freq;
+}
+
+
+/**
+ * @brief Get PCLK1 frequency
+ * @param None
+ * @return PCLK1 frequency
+ * @details This function get PCLK1 frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetPCLK1Freq(void)
+{
+ uint32_t u32Freq;
+ SystemCoreClockUpdate();
+
+ if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV1)
+ {
+ u32Freq = SystemCoreClock;
+ }
+ else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV2)
+ {
+ u32Freq = SystemCoreClock / 2UL;
+ }
+ else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV4)
+ {
+ u32Freq = SystemCoreClock / 4UL;
+ }
+ else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV8)
+ {
+ u32Freq = SystemCoreClock / 8UL;
+ }
+ else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV16)
+ {
+ u32Freq = SystemCoreClock / 16UL;
+ }
+ else
+ {
+ u32Freq = SystemCoreClock;
+ }
+
+ return u32Freq;
+}
+
+
+/**
+ * @brief Get HCLK frequency
+ * @param None
+ * @return HCLK frequency
+ * @details This function get HCLK frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetHCLKFreq(void)
+{
+ SystemCoreClockUpdate();
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief Get CPU frequency
+ * @param None
+ * @return CPU frequency
+ * @details This function get CPU frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetCPUFreq(void)
+{
+ SystemCoreClockUpdate();
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief Set HCLK frequency
+ * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is running up to 192MHz.
+ * @return HCLK frequency
+ * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
+{
+ uint32_t u32HIRCSTB;
+
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+ /* The range of u32Hclk is running up to 192 MHz */
+ if(u32Hclk > FREQ_192MHZ)
+ {
+ u32Hclk = FREQ_192MHZ;
+ }
+
+ /* Switch HCLK clock source to HIRC clock for safe */
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+ CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
+ CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
+
+ /* Configure PLL setting if HXT clock is enabled */
+ if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk)
+ {
+ u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk);
+ }
+ /* Configure PLL setting if HXT clock is not enabled */
+ else
+ {
+ u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk);
+
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+ }
+
+ /* Select HCLK clock source to PLL,
+ and update system core clock
+ */
+ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
+
+ /* Disable HIRC if HIRC is disabled before setting core clock */
+ if(u32HIRCSTB == 0UL)
+ {
+ CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+ }
+
+ /* Return actually HCLK frequency is PLL frequency divide 1 */
+ return u32Hclk;
+}
+
+/**
+ * @brief This function set HCLK clock source and HCLK clock divider
+ * @param[in] u32ClkSrc is HCLK clock source. Including :
+ * - \ref CLK_CLKSEL0_HCLKSEL_HXT
+ * - \ref CLK_CLKSEL0_HCLKSEL_LXT
+ * - \ref CLK_CLKSEL0_HCLKSEL_PLL
+ * - \ref CLK_CLKSEL0_HCLKSEL_LIRC
+ * - \ref CLK_CLKSEL0_HCLKSEL_HIRC
+ * @param[in] u32ClkDiv is HCLK clock divider. Including :
+ * - \ref CLK_CLKDIV0_HCLK(x)
+ * @return None
+ * @details This function set HCLK clock source and HCLK clock divider. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ uint32_t u32HIRCSTB;
+
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+ /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
+
+ /* Apply new Divider */
+ CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
+
+ /* Switch HCLK to new HCLK source */
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
+
+ /* Update System Core Clock */
+ SystemCoreClockUpdate();
+
+ /* Disable HIRC if HIRC is disabled before switching HCLK source */
+ if(u32HIRCSTB == 0UL)
+ {
+ CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+ }
+}
+
+/**
+ * @brief This function set selected module clock source and module clock divider
+ * @param[in] u32ModuleIdx is module index.
+ * @param[in] u32ClkSrc is module clock source.
+ * @param[in] u32ClkDiv is module clock divider.
+ * @return None
+ * @details Valid parameter combinations listed in following table:
+ *
+ * |Module index |Clock source |Divider |
+ * | :---------------- | :----------------------------------- | :-------------------------- |
+ * |\ref CCAP_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HXT |\ref CLK_CLKDIV3_CCAP(x) |
+ * |\ref CCAP_MODULE |\ref CLK_CLKSEL0_CCAPSEL_PLL |\ref CLK_CLKDIV3_CCAP(x) |
+ * |\ref CCAP_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HIRC |\ref CLK_CLKDIV3_CCAP(x) |
+ * |\ref CCAP_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HCLK |\ref CLK_CLKDIV3_CCAP(x) |
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) |
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL |\ref CLK_CLKDIV0_SDH0(x) |
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) |
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) |
+ * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HXT |\ref CLK_CLKDIV3_SDH1(x) |
+ * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_PLL |\ref CLK_CLKDIV3_SDH1(x) |
+ * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HIRC |\ref CLK_CLKDIV3_SDH1(x) |
+ * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HCLK |\ref CLK_CLKDIV3_SDH1(x) |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
+ * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
+ * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x |
+ * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PLL | x |
+ * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PCLK0 | x |
+ * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PLL | x |
+ * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PCLK1 | x |
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x |
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x |
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x |
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x |
+ * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PLL | x |
+ * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0 | x |
+ * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PLL | x |
+ * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1 | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK1 | x |
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HXT | x |
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x |
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x |
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) |
+ * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x |
+ * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x |
+ * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_HXT | x |
+ * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_PLL | x |
+ * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_HIRC | x |
+ * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_PCLK1 | x |
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT |\ref CLK_CLKDIV2_I2S0(x) |
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL |\ref CLK_CLKDIV2_I2S0(x) |
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC |\ref CLK_CLKDIV2_I2S0(x) |
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK0 |\ref CLK_CLKDIV2_I2S0(x) |
+ * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_HXT |\ref CLK_CLKDIV4_UART6(x) |
+ * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_LXT |\ref CLK_CLKDIV4_UART6(x) |
+ * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_PLL |\ref CLK_CLKDIV4_UART6(x) |
+ * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_HIRC |\ref CLK_CLKDIV4_UART6(x) |
+ * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_HXT |\ref CLK_CLKDIV4_UART7(x) |
+ * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_LXT |\ref CLK_CLKDIV4_UART7(x) |
+ * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_PLL |\ref CLK_CLKDIV4_UART7(x) |
+ * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_HIRC |\ref CLK_CLKDIV4_UART7(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) |
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) |
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) |
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) |
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) |
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) |
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) |
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) |
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) |
+ * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) |
+ * |\ref EADC1_MODULE | x |\ref CLK_CLKDIV2_EADC1(x) |
+ * |\ref EMAC_MODULE | x |\ref CLK_CLKDIV3_EMAC(x) |
+ *
+ */
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ uint32_t u32sel = 0U, u32div = 0U;
+
+ if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
+ {
+ /* Get clock divider control register address */
+ if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
+ {
+ if(MODULE_CLKDIV(u32ModuleIdx) == 2U && MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 31U) //EADC1
+ {
+ u32div = (uint32_t)&CLK->CLKDIV2;
+ }
+ else if(MODULE_CLKDIV(u32ModuleIdx) == 2U && MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 29U) //I2S0
+ {
+ u32div = (uint32_t)&CLK->CLKDIV2;
+ }
+ else if (MODULE_CLKDIV(u32ModuleIdx) == 2U)
+ {
+ u32div = (uint32_t)&CLK->CLKDIV3;
+ }
+ else if (MODULE_CLKDIV(u32ModuleIdx) == 3U)
+ {
+ u32div = (uint32_t)&CLK->CLKDIV4;
+ }
+ else
+ {
+ u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U);
+ }
+ }
+ else
+ {
+ /* Get clock divider control register address */
+ if(MODULE_CLKDIV(u32ModuleIdx) == 2U)
+ {
+ u32div = (uint32_t)&CLK->CLKDIV3;
+ }
+ else if (MODULE_CLKDIV(u32ModuleIdx) == 3U)
+ {
+ u32div = (uint32_t)&CLK->CLKDIV4;
+ }
+ else
+ {
+ u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U);
+ }
+ }
+
+ /* Apply new divider */
+ M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
+ }
+
+ if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
+ {
+ /* Get clock select control register address */
+ u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4U);
+ /* Set new clock selection setting */
+ M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
+ }
+}
+
+/**
+ * @brief Set SysTick clock source
+ * @param[in] u32ClkSrc is module clock source. Including:
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_LXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+ * @return None
+ * @details This function set SysTick clock source. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
+{
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+
+}
+
+/**
+ * @brief Enable clock source
+ * @param[in] u32ClkMask is clock source mask. Including :
+ * - \ref CLK_PWRCTL_HXTEN_Msk
+ * - \ref CLK_PWRCTL_LXTEN_Msk
+ * - \ref CLK_PWRCTL_HIRCEN_Msk
+ * - \ref CLK_PWRCTL_LIRCEN_Msk
+ * @return None
+ * @details This function enable clock source. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_EnableXtalRC(uint32_t u32ClkMask)
+{
+ CLK->PWRCTL |= u32ClkMask;
+}
+
+/**
+ * @brief Disable clock source
+ * @param[in] u32ClkMask is clock source mask. Including :
+ * - \ref CLK_PWRCTL_HXTEN_Msk
+ * - \ref CLK_PWRCTL_LXTEN_Msk
+ * - \ref CLK_PWRCTL_HIRCEN_Msk
+ * - \ref CLK_PWRCTL_LIRCEN_Msk
+ * @return None
+ * @details This function disable clock source. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_DisableXtalRC(uint32_t u32ClkMask)
+{
+ CLK->PWRCTL &= ~u32ClkMask;
+}
+
+/**
+ * @brief Enable module clock
+ * @param[in] u32ModuleIdx is module index. Including :
+ * - \ref PDMA_MODULE
+ * - \ref ISP_MODULE
+ * - \ref EBI_MODULE
+ * - \ref EMAC_MODULE
+ * - \ref SDH0_MODULE
+ * - \ref CRC_MODULE
+ * - \ref CCAP_MODULE
+ * - \ref SEN_MODULE
+ * - \ref HSUSBD_MODULE
+ * - \ref CRPT_MODULE
+ * - \ref SPIM_MODULE
+ * - \ref FMCIDLE_MODULE
+ * - \ref USBH_MODULE
+ * - \ref SDH1_MODULE
+ * - \ref WDT_MODULE
+ * - \ref RTC_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref CLKO_MODULE
+ * - \ref WWDT_MODULE
+ * - \ref ACMP01_MODULE
+ * - \ref I2C0_MODULE
+ * - \ref I2C1_MODULE
+ * - \ref I2C2_MODULE
+ * - \ref QSPI0_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref SPI2_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref UART2_MODULE
+ * - \ref UART3_MODULE
+ * - \ref UART4_MODULE
+ * - \ref UART5_MODULE
+ * - \ref UART6_MODULE
+ * - \ref UART7_MODULE
+ * - \ref CAN0_MODULE
+ * - \ref CAN1_MODULE
+ * - \ref OTG_MODULE
+ * - \ref USBD_MODULE
+ * - \ref EADC_MODULE
+ * - \ref I2S0_MODULE
+ * - \ref HSOTG_MODULE
+ * - \ref SC0_MODULE
+ * - \ref SC1_MODULE
+ * - \ref SC2_MODULE
+ * - \ref QSPI1_MODULE
+ * - \ref SPI3_MODULE
+ * - \ref USCI0_MODULE
+ * - \ref USCI1_MODULE
+ * - \ref DAC_MODULE
+ * - \ref CAN2_MODULE
+ * - \ref EPWM0_MODULE
+ * - \ref EPWM1_MODULE
+ * - \ref BPWM0_MODULE
+ * - \ref BPWM1_MODULE
+ * - \ref QEI0_MODULE
+ * - \ref QEI1_MODULE
+ * - \ref TRNG_MODULE
+ * - \ref ECAP0_MODULE
+ * - \ref ECAP1_MODULE
+ * - \ref CAN2_MODULE
+ * - \ref OPA_MODULE
+ * - \ref EADC1_MODULE
+ * @return None
+ * @details This function is used to enable module clock.
+ */
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
+{
+ uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
+
+ u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
+ u32tmpAddr = (uint32_t)&CLK->AHBCLK;
+ u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
+
+ *(volatile uint32_t *)u32tmpAddr |= u32tmpVal;
+}
+
+/**
+ * @brief Disable module clock
+ * @param[in] u32ModuleIdx is module index. Including :
+ * - \ref PDMA_MODULE
+ * - \ref ISP_MODULE
+ * - \ref EBI_MODULE
+ * - \ref EMAC_MODULE
+ * - \ref SDH0_MODULE
+ * - \ref CRC_MODULE
+ * - \ref CCAP_MODULE
+ * - \ref SEN_MODULE
+ * - \ref HSUSBD_MODULE
+ * - \ref CRPT_MODULE
+ * - \ref SPIM_MODULE
+ * - \ref FMCIDLE_MODULE
+ * - \ref USBH_MODULE
+ * - \ref SDH1_MODULE
+ * - \ref WDT_MODULE
+ * - \ref RTC_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref CLKO_MODULE
+ * - \ref WWDT_MODULE
+ * - \ref ACMP01_MODULE
+ * - \ref I2C0_MODULE
+ * - \ref I2C1_MODULE
+ * - \ref I2C2_MODULE
+ * - \ref QSPI0_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref SPI2_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref UART2_MODULE
+ * - \ref UART3_MODULE
+ * - \ref UART4_MODULE
+ * - \ref UART5_MODULE
+ * - \ref UART6_MODULE
+ * - \ref UART7_MODULE
+ * - \ref CAN0_MODULE
+ * - \ref CAN1_MODULE
+ * - \ref OTG_MODULE
+ * - \ref USBD_MODULE
+ * - \ref EADC_MODULE
+ * - \ref I2S0_MODULE
+ * - \ref HSOTG_MODULE
+ * - \ref SC0_MODULE
+ * - \ref SC1_MODULE
+ * - \ref SC2_MODULE
+ * - \ref QSPI1_MODULE
+ * - \ref SPI3_MODULE
+ * - \ref USCI0_MODULE
+ * - \ref USCI1_MODULE
+ * - \ref DAC_MODULE
+ * - \ref CAN2_MODULE
+ * - \ref EPWM0_MODULE
+ * - \ref EPWM1_MODULE
+ * - \ref BPWM0_MODULE
+ * - \ref BPWM1_MODULE
+ * - \ref QEI0_MODULE
+ * - \ref QEI1_MODULE
+ * - \ref TRNG_MODULE
+ * - \ref ECAP0_MODULE
+ * - \ref ECAP1_MODULE
+ * - \ref CAN2_MODULE
+ * - \ref OPA_MODULE
+ * - \ref EADC1_MODULE
+ * @return None
+ * @details This function is used to disable module clock.
+ */
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
+{
+ uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
+
+ u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
+ u32tmpAddr = (uint32_t)&CLK->AHBCLK;
+ u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
+
+ *(uint32_t *)u32tmpAddr &= u32tmpVal;
+}
+
+
+/**
+ * @brief Set PLL frequency
+ * @param[in] u32PllClkSrc is PLL clock source. Including :
+ * - \ref CLK_PLLCTL_PLLSRC_HXT
+ * - \ref CLK_PLLCTL_PLLSRC_HIRC
+ * @param[in] u32PllFreq is PLL frequency.
+ * @return PLL frequency
+ * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
+{
+ uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32PllClk;
+ uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32basFreq;
+
+ /* Disable PLL first to avoid unstable when setting PLL */
+ CLK_DisablePLL();
+
+ /* PLL source clock is from HXT */
+ if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
+ {
+ /* Enable HXT clock */
+ CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
+
+ /* Wait for HXT clock ready */
+ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+
+ /* Select PLL source clock from HXT */
+ u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
+ u32PllSrcClk = __HXT;
+
+ /* u32NR start from 2 */
+ u32NR = 2UL;
+ }
+
+ /* PLL source clock is from HIRC */
+ else
+ {
+ /* Enable HIRC clock */
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+
+ /* Wait for HIRC clock ready */
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+
+ /* Select PLL source clock from HIRC */
+ u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
+ u32PllSrcClk = __HIRC;
+
+ /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
+ u32NR = 4UL;
+ }
+
+ if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ))
+ {
+
+ /* Find best solution */
+ u32Min = (uint32_t) - 1;
+ u32MinNR = 0UL;
+ u32MinNF = 0UL;
+ u32MinNO = 0UL;
+ u32basFreq = u32PllFreq;
+
+ for(u32NO = 1UL; u32NO <= 4UL; u32NO++)
+ {
+ /* Break when get good results */
+ if (u32Min == 0UL)
+ {
+ break;
+ }
+
+ if (u32NO != 3UL)
+ {
+
+ if(u32NO == 4UL)
+ {
+ u32PllFreq = u32basFreq << 2;
+ }
+ else if(u32NO == 2UL)
+ {
+ u32PllFreq = u32basFreq << 1;
+ }
+ else
+ {
+ }
+
+ for(u32NR = 2UL; u32NR <= 32UL; u32NR++)
+ {
+ /* Break when get good results */
+ if (u32Min == 0UL)
+ {
+ break;
+ }
+
+ u32Tmp = u32PllSrcClk / u32NR;
+ if((u32Tmp >= 4000000UL) && (u32Tmp <= 8000000UL))
+ {
+ for(u32NF = 2UL; u32NF <= 513UL; u32NF++)
+ {
+ /* u32Tmp2 is shifted 2 bits to avoid overflow */
+ u32Tmp2 = (((u32Tmp * 2UL) >> 2) * u32NF);
+
+ if((u32Tmp2 >= FREQ_50MHZ) && (u32Tmp2 <= FREQ_125MHZ))
+ {
+ u32Tmp3 = (u32Tmp2 > (u32PllFreq>>2)) ? u32Tmp2 - (u32PllFreq>>2) : (u32PllFreq>>2) - u32Tmp2;
+ if(u32Tmp3 < u32Min)
+ {
+ u32Min = u32Tmp3;
+ u32MinNR = u32NR;
+ u32MinNF = u32NF;
+ u32MinNO = u32NO;
+
+ /* Break when get good results */
+ if(u32Min == 0UL)
+ {
+ break;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ /* Enable and apply new PLL setting. */
+ CLK->PLLCTL = u32CLK_SRC | ((u32MinNO - 1UL) << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL);
+
+ /* Wait for PLL clock stable */
+ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+
+ /* Actual PLL output clock frequency */
+ u32PllClk = u32PllSrcClk / (u32MinNO * (u32MinNR)) * (u32MinNF) * 2UL;
+ }
+ else
+ {
+ /* Wrong frequency request. Just return default setting. */
+ /* Apply default PLL setting and return */
+ if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
+ {
+ CLK->PLLCTL = CLK_PLLCTL_192MHz_HXT;
+ }
+ else
+ {
+ CLK->PLLCTL = CLK_PLLCTL_192MHz_HIRC;
+ }
+
+ /* Wait for PLL clock stable */
+ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+
+ /* Actual PLL output clock frequency */
+ u32PllClk = CLK_GetPLLClockFreq();
+ }
+
+ return u32PllClk;
+}
+
+/**
+ * @brief Disable PLL
+ * @param None
+ * @return None
+ * @details This function set PLL in Power-down mode. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_DisablePLL(void)
+{
+ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
+}
+
+
+/**
+ * @brief This function check selected clock source status
+ * @param[in] u32ClkMask is selected clock source. Including :
+ * - \ref CLK_STATUS_HXTSTB_Msk
+ * - \ref CLK_STATUS_LXTSTB_Msk
+ * - \ref CLK_STATUS_HIRCSTB_Msk
+ * - \ref CLK_STATUS_LIRCSTB_Msk
+ * - \ref CLK_STATUS_PLLSTB_Msk
+ * @retval 0 clock is not stable
+ * @retval 1 clock is stable
+ * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms)
+ */
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
+{
+ int32_t i32TimeOutCnt = 2160000;
+ uint32_t u32Ret = 1U;
+
+ while((CLK->STATUS & u32ClkMask) != u32ClkMask)
+ {
+ if(i32TimeOutCnt-- <= 0)
+ {
+ u32Ret = 0U;
+ break;
+ }
+ }
+ return u32Ret;
+}
+
+/**
+ * @brief Enable System Tick counter
+ * @param[in] u32ClkSrc is System Tick clock source. Including:
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_LXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK
+ * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
+ * @return None
+ * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
+{
+ /* Set System Tick counter disabled */
+ SysTick->CTRL = 0UL;
+
+ /* Set System Tick clock source */
+ if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK )
+ {
+ SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
+ }
+ else
+ {
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+ }
+
+ /* Set System Tick reload value */
+ SysTick->LOAD = u32Count;
+
+ /* Clear System Tick current value and counter flag */
+ SysTick->VAL = 0UL;
+
+ /* Set System Tick interrupt enabled and counter enabled */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+/**
+ * @brief Disable System Tick counter
+ * @param None
+ * @return None
+ * @details This function disable System Tick counter.
+ */
+void CLK_DisableSysTick(void)
+{
+ /* Set System Tick counter disabled */
+ SysTick->CTRL = 0UL;
+}
+
+
+/**
+ * @brief Power-down mode selected
+ * @param[in] u32PDMode is power down mode index. Including :
+ * - \ref CLK_PMUCTL_PDMSEL_PD
+ * - \ref CLK_PMUCTL_PDMSEL_LLPD
+ * - \ref CLK_PMUCTL_PDMSEL_FWPD
+ * - \ref CLK_PMUCTL_PDMSEL_SPD0
+ * - \ref CLK_PMUCTL_PDMSEL_SPD1
+ * - \ref CLK_PMUCTL_PDMSEL_DPD
+ * @return None
+ * @details This function is used to set power-down mode.
+ * @note Must enable LIRC clock before entering to Standby Power-down Mode
+ */
+
+void CLK_SetPowerDownMode(uint32_t u32PDMode)
+{
+ if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
+ {
+ if(u32PDMode == CLK_PMUCTL_PDMSEL_SPD0)
+ {
+ u32PDMode = CLK_PMUCTL_PDMSEL_SPD0;
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_SRETSEL_Msk)) | CLK_SPDSRETSEL_16K;
+ }
+ else if(u32PDMode == CLK_PMUCTL_PDMSEL_SPD1)
+ {
+ u32PDMode = CLK_PMUCTL_PDMSEL_SPD0;
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_SRETSEL_Msk)) | CLK_SPDSRETSEL_NO;
+ }
+ }
+ else
+ {
+ /* Enable LIRC clock before entering to Standby Power-down Mode */
+ if((u32PDMode == CLK_PMUCTL_PDMSEL_SPD0) || (u32PDMode == CLK_PMUCTL_PDMSEL_SPD1))
+ {
+ /* Enable LIRC clock */
+ CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk;
+
+ /* Wait for LIRC clock stable */
+ CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
+ }
+ }
+
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode;
+}
+
+
+/**
+ * @brief Set Wake-up pin trigger type at Deep Power down mode
+ *
+ * @param[in] u32TriggerType
+ * - \ref CLK_DPDWKPIN_RISING
+ * - \ref CLK_DPDWKPIN_FALLING
+ * - \ref CLK_DPDWKPIN_BOTHEDGE
+ * - \ref CLK_DPDWKPIN1_RISING
+ * - \ref CLK_DPDWKPIN1_FALLING
+ * - \ref CLK_DPDWKPIN1_BOTHEDGE
+ * - \ref CLK_DPDWKPIN2_RISING
+ * - \ref CLK_DPDWKPIN2_FALLING
+ * - \ref CLK_DPDWKPIN2_BOTHEDGE
+ * - \ref CLK_DPDWKPIN3_RISING
+ * - \ref CLK_DPDWKPIN3_FALLING
+ * - \ref CLK_DPDWKPIN3_BOTHEDGE
+ * - \ref CLK_DPDWKPIN4_RISING
+ * - \ref CLK_DPDWKPIN4_FALLING
+ * - \ref CLK_DPDWKPIN4_BOTHEDGE
+ * @return None
+ *
+ * @details This function is used to enable Wake-up pin trigger type.
+ */
+
+void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
+{
+ uint32_t u32Pin1, u32Pin2, u32Pin3, u32Pin4;
+
+ if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
+ {
+ u32Pin1 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN1_Pos);
+ u32Pin2 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN2_Pos);
+ u32Pin3 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN3_Pos);
+ u32Pin4 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN4_Pos);
+
+ if(u32Pin1)
+ {
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | u32TriggerType;
+ }
+ else if(u32Pin2)
+ {
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | u32TriggerType;
+ }
+ else if(u32Pin3)
+ {
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | u32TriggerType;
+ }
+ else if(u32Pin4)
+ {
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | u32TriggerType;
+ }
+ else
+ {
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
+ }
+ }
+ else
+ {
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
+ }
+}
+
+/**
+ * @brief Get power manager wake up source
+ *
+ * @param[in] None
+ * @return None
+ *
+ * @details This function get power manager wake up source.
+ */
+
+uint32_t CLK_GetPMUWKSrc(void)
+{
+ return (CLK->PMUSTS);
+}
+
+/**
+ * @brief Set specified GPIO as wake up source at Stand-by Power down mode
+ *
+ * @param[in] u32Port GPIO port. It could be 0~3.
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
+ * @param[in] u32TriggerType
+ * - \ref CLK_SPDWKPIN_RISING
+ * - \ref CLK_SPDWKPIN_FALLING
+ * @param[in] u32DebounceEn
+ * - \ref CLK_SPDWKPIN_DEBOUNCEEN
+ * - \ref CLK_SPDWKPIN_DEBOUNCEDIS
+ * @return None
+ *
+ * @details This function is used to set specified GPIO as wake up source
+ * at Stand-by Power down mode.
+ */
+void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
+{
+ uint32_t u32tmpAddr = 0UL;
+ uint32_t u32tmpVal = 0UL;
+
+ /* GPx Stand-by Power-down Wake-up Pin Select */
+ u32tmpAddr = (uint32_t)&CLK->PASWKCTL;
+ u32tmpAddr += (0x4UL * u32Port);
+
+ u32tmpVal = inpw((uint32_t *)u32tmpAddr);
+ u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) |
+ (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;
+ outpw((uint32_t *)u32tmpAddr, u32tmpVal);
+}
+
+/**
+ * @brief Get PLL clock frequency
+ * @param None
+ * @return PLL frequency
+ * @details This function get PLL frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetPLLClockFreq(void)
+{
+ uint32_t u32PllFreq = 0UL, u32PllReg;
+ uint32_t u32FIN, u32NF, u32NR, u32NO;
+ uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
+
+ u32PllReg = CLK->PLLCTL;
+
+ if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
+ {
+ u32PllFreq = 0UL; /* PLL is in power down mode or fix low */
+ }
+ else if((u32PllReg & CLK_PLLCTL_BP_Msk) == CLK_PLLCTL_BP_Msk)
+ {
+ if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC)
+ {
+ u32FIN = __HIRC; /* PLL source clock from HIRC */
+ }
+ else
+ {
+ u32FIN = __HXT; /* PLL source clock from HXT */
+ }
+
+ u32PllFreq = u32FIN;
+ }
+ else
+ {
+ if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC)
+ {
+ u32FIN = __HIRC; /* PLL source clock from HIRC */
+ }
+ else
+ {
+ u32FIN = __HXT; /* PLL source clock from HXT */
+ }
+ /* PLL is output enabled in normal work mode */
+ u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
+ u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
+ u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
+
+ /* u32FIN is shifted 2 bits to avoid overflow */
+ u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2) * 2UL;
+ }
+
+ return u32PllFreq;
+}
+
+/**
+ * @brief Get selected module clock source
+ * @param[in] u32ModuleIdx is module index.
+ * - \ref CCAP_MODULE
+ * - \ref SDH0_MODULE
+ * - \ref SDH1_MODULE
+ * - \ref WDT_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref CLKO_MODULE
+ * - \ref WWDT_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref EPWM0_MODULE
+ * - \ref EPWM1_MODULE
+ * - \ref BPWM0_MODULE
+ * - \ref BPWM1_MODULE
+ * - \ref QSPI0_MODULE
+ * - \ref QSPI1_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref SPI2_MODULE
+ * - \ref SPI3_MODULE
+ * - \ref SC0_MODULE
+ * - \ref SC1_MODULE
+ * - \ref SC2_MODULE
+ * - \ref RTC_MODULE
+ * - \ref I2S0_MODULE
+ * - \ref UART2_MODULE
+ * - \ref UART3_MODULE
+ * - \ref UART4_MODULE
+ * - \ref UART5_MODULE
+ * - \ref UART6_MODULE
+ * - \ref UART7_MODULE
+ * @return Selected module clock source setting
+ * @details This function get selected module clock source.
+ */
+uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
+{
+ uint32_t u32sel = 0;
+ uint32_t u32SelTbl[4] = {0x0, 0x4, 0x8, 0xC};
+
+ /* Get clock source selection setting */
+ if(u32ModuleIdx == EPWM0_MODULE)
+ return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos);
+ else if(u32ModuleIdx == EPWM1_MODULE)
+ return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos);
+ else if(u32ModuleIdx == BPWM0_MODULE)
+ return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos);
+ else if(u32ModuleIdx == BPWM1_MODULE)
+ return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos);
+ else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
+ {
+ /* Get clock select control register address */
+ u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
+ /* Get clock source selection setting */
+ return ((M32(u32sel) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx));
+ }
+ else
+ return 0;
+}
+
+/**
+ * @brief Get selected module clock divider number
+ * @param[in] u32ModuleIdx is module index.
+ * - \ref CCAP_MODULE
+ * - \ref SDH0_MODULE
+ * - \ref SDH1_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref UART2_MODULE
+ * - \ref UART3_MODULE
+ * - \ref UART4_MODULE
+ * - \ref UART5_MODULE
+ * - \ref UART6_MODULE
+ * - \ref UART7_MODULE
+ * - \ref SC0_MODULE
+ * - \ref SC1_MODULE
+ * - \ref SC2_MODULE
+ * - \ref I2S0_MODULE
+ * - \ref EADC_MODULE
+ * - \ref EADC1_MODULE
+ * - \ref EMAC_MODULE
+ * @return Selected module clock divider number setting
+ * @details This function get selected module clock divider number.
+ */
+uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
+{
+ uint32_t u32div = 0;
+ uint32_t u32DivTbl[4] = {0x0, 0x4, 0xc, 0x10};
+
+ if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
+ {
+ /* Get clock divider control register address */
+ u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
+ if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
+ {
+ if(MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 31U) //EADC1
+ u32div = (uint32_t)&CLK->CLKDIV2;
+ else if(MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 29U) //I2S0
+ u32div = (uint32_t)&CLK->CLKDIV2;
+ }
+ /* Get clock divider number setting */
+ return ((M32(u32div) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx));
+ }
+ else
+ return 0;
+}
+
+
+/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CLK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crc.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crc.c
new file mode 100644
index 00000000000..0de1d365770
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crc.c
@@ -0,0 +1,95 @@
+/**************************************************************************//**
+ * @file crc.c
+ * @version V1.00
+ * @brief M480 CRC driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CRC_Driver CRC Driver
+ @{
+*/
+
+/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
+ @{
+*/
+
+/**
+ * @brief CRC Open
+ *
+ * @param[in] u32Mode CRC operation polynomial mode. Valid values are:
+ * - \ref CRC_CCITT
+ * - \ref CRC_8
+ * - \ref CRC_16
+ * - \ref CRC_32
+ * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with:
+ * - \ref CRC_CHECKSUM_COM
+ * - \ref CRC_CHECKSUM_RVS
+ * - \ref CRC_WDATA_COM
+ * - \ref CRC_WDATA_RVS
+ * @param[in] u32Seed Seed value.
+ * @param[in] u32DataLen CPU Write Data Length. Valid values are:
+ * - \ref CRC_CPU_WDATA_8
+ * - \ref CRC_CPU_WDATA_16
+ * - \ref CRC_CPU_WDATA_32
+ *
+ * @return None
+ *
+ * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
+ * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
+ */
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
+{
+ CRC->SEED = u32Seed;
+ CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
+
+ /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */
+ CRC->CTL |= CRC_CTL_CHKSINIT_Msk;
+}
+
+/**
+ * @brief Get CRC Checksum
+ *
+ * @param[in] None
+ *
+ * @return Checksum Result
+ *
+ * @details This macro gets the CRC checksum result by current CRC polynomial mode.
+ */
+uint32_t CRC_GetChecksum(void)
+{
+ uint32_t ret;
+
+ switch(CRC->CTL & CRC_CTL_CRCMODE_Msk)
+ {
+ case CRC_CCITT:
+ case CRC_16:
+ ret = (CRC->CHECKSUM & 0xFFFFU);
+ break;
+ case CRC_32:
+ ret = (CRC->CHECKSUM);
+ break;
+ case CRC_8:
+ ret = (CRC->CHECKSUM & 0xFFU);
+ break;
+ default:
+ ret = 0U;
+ break;
+ }
+
+ return ret;
+}
+
+/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CRC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crypto.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crypto.c
new file mode 100644
index 00000000000..fd4bfe884a9
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crypto.c
@@ -0,0 +1,1995 @@
+/**************************************************************************//**
+ * @file crypto.c
+ * @version V1.10
+ * @brief Cryptographic Accelerator driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include
+#include "NuMicro.h"
+
+/** @cond HIDDEN_SYMBOLS */
+
+#define ENABLE_DEBUG 0
+
+#if ENABLE_DEBUG
+#define CRPT_DBGMSG printf
+#else
+#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */
+#endif
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CRYPTO_Driver CRYPTO Driver
+ @{
+*/
+
+
+/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
+ @{
+*/
+
+/** @cond HIDDEN_SYMBOLS */
+
+static uint32_t g_AES_CTL[4];
+static uint32_t g_TDES_CTL[4];
+
+static char hex_char_tbl[] = "0123456789abcdef";
+
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count);
+static char get_Nth_nibble_char(uint32_t val32, uint32_t idx);
+static void Hex2Reg(char input[], uint32_t volatile reg[]);
+static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]);
+static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift);
+static char ch2hex(char ch);
+static int get_nibble_value(char c);
+
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+ * @brief Open PRNG function
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32KeySize is PRNG key size, including:
+ * - \ref PRNG_KEY_SIZE_64
+ * - \ref PRNG_KEY_SIZE_128
+ * - \ref PRNG_KEY_SIZE_192
+ * - \ref PRNG_KEY_SIZE_256
+ * @param[in] u32SeedReload is PRNG seed reload or not, including:
+ * - \ref PRNG_SEED_CONT
+ * - \ref PRNG_SEED_RELOAD
+ * @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD.
+ * @return None
+ */
+void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed)
+{
+ if (u32SeedReload)
+ {
+ crpt->PRNG_SEED = u32Seed;
+ }
+
+ crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
+ (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);
+}
+
+/**
+ * @brief Start to generate one PRNG key.
+ * @param[in] crpt Reference to Crypto module.
+ * @return None
+ */
+void PRNG_Start(CRPT_T *crpt)
+{
+ crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk;
+}
+
+/**
+ * @brief Read the PRNG key.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[out] u32RandKey The key buffer to store newly generated PRNG key.
+ * @return None
+ */
+void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[])
+{
+ uint32_t i, wcnt;
+
+ wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U;
+
+ for (i = 0U; i < wcnt; i++)
+ {
+ u32RandKey[i] = crpt->PRNG_KEY[i];
+ }
+
+ crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk;
+}
+
+
+/**
+ * @brief Open AES encrypt/decrypt function.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32Channel AES channel. Must be 0~3.
+ * @param[in] u32EncDec 1: AES encode; 0: AES decode
+ * @param[in] u32OpMode AES operation mode, including:
+ * - \ref AES_MODE_ECB
+ * - \ref AES_MODE_CBC
+ * - \ref AES_MODE_CFB
+ * - \ref AES_MODE_OFB
+ * - \ref AES_MODE_CTR
+ * - \ref AES_MODE_CBC_CS1
+ * - \ref AES_MODE_CBC_CS2
+ * - \ref AES_MODE_CBC_CS3
+ * @param[in] u32KeySize is AES key size, including:
+ * - \ref AES_KEY_SIZE_128
+ * - \ref AES_KEY_SIZE_192
+ * - \ref AES_KEY_SIZE_256
+ * @param[in] u32SwapType is AES input/output data swap control, including:
+ * - \ref AES_NO_SWAP
+ * - \ref AES_OUT_SWAP
+ * - \ref AES_IN_SWAP
+ * - \ref AES_IN_OUT_SWAP
+ * @return None
+ */
+void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec,
+ uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType)
+{
+ crpt->AES_CTL = (u32Channel << CRPT_AES_CTL_CHANNEL_Pos) |
+ (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) |
+ (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) |
+ (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) |
+ (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos);
+ g_AES_CTL[u32Channel] = crpt->AES_CTL;
+}
+
+/**
+ * @brief Start AES encrypt/decrypt
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32Channel AES channel. Must be 0~3.
+ * @param[in] u32DMAMode AES DMA control, including:
+ * - \ref CRYPTO_DMA_ONE_SHOT One shop AES encrypt/decrypt.
+ * - \ref CRYPTO_DMA_CONTINUE Continuous AES encrypt/decrypt.
+ * - \ref CRYPTO_DMA_LAST Last AES encrypt/decrypt of a series of AES_Start.
+ * @return None
+ */
+void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode)
+{
+ crpt->AES_CTL = g_AES_CTL[u32Channel];
+ crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos);
+}
+
+/**
+ * @brief Set AES keys
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32Channel AES channel. Must be 0~3.
+ * @param[in] au32Keys An word array contains AES keys.
+ * @param[in] u32KeySize is AES key size, including:
+ * - \ref AES_KEY_SIZE_128
+ * - \ref AES_KEY_SIZE_192
+ * - \ref AES_KEY_SIZE_256
+ * @return None
+ */
+void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize)
+{
+ uint32_t i, wcnt, key_reg_addr;
+
+ key_reg_addr = (uint32_t)&crpt->AES0_KEY[0] + (u32Channel * 0x3CUL);
+ wcnt = 4UL + u32KeySize*2UL;
+
+ for (i = 0U; i < wcnt; i++)
+ {
+ outpw(key_reg_addr, au32Keys[i]);
+ key_reg_addr += 4UL;
+ }
+}
+
+/**
+ * @brief Set AES initial vectors
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32Channel AES channel. Must be 0~3.
+ * @param[in] au32IV A four entry word array contains AES initial vectors.
+ * @return None
+ */
+void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[])
+{
+ uint32_t i, key_reg_addr;
+
+ key_reg_addr = (uint32_t)&crpt->AES0_IV[0] + (u32Channel * 0x3CUL);
+
+ for (i = 0U; i < 4U; i++)
+ {
+ outpw(key_reg_addr, au32IV[i]);
+ key_reg_addr += 4UL;
+ }
+}
+
+/**
+ * @brief Set AES DMA transfer configuration.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32Channel AES channel. Must be 0~3.
+ * @param[in] u32SrcAddr AES DMA source address
+ * @param[in] u32DstAddr AES DMA destination address
+ * @param[in] u32TransCnt AES DMA transfer byte count
+ * @return None
+ */
+void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr,
+ uint32_t u32DstAddr, uint32_t u32TransCnt)
+{
+ uint32_t reg_addr;
+
+ reg_addr = (uint32_t)&crpt->AES0_SADDR + (u32Channel * 0x3CUL);
+ outpw(reg_addr, u32SrcAddr);
+
+ reg_addr = (uint32_t)&crpt->AES0_DADDR + (u32Channel * 0x3CUL);
+ outpw(reg_addr, u32DstAddr);
+
+ reg_addr = (uint32_t)&crpt->AES0_CNT + (u32Channel * 0x3CUL);
+ outpw(reg_addr, u32TransCnt);
+}
+
+/**
+ * @brief Open TDES encrypt/decrypt function.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32Channel TDES channel. Must be 0~3.
+ * @param[in] u32EncDec 1: TDES encode; 0: TDES decode
+ * @param[in] Is3DES 1: TDES; 0: DES
+ * @param[in] Is3Key 1: TDES 3 key mode; 0: TDES 2 key mode
+ * @param[in] u32OpMode TDES operation mode, including:
+ * - \ref TDES_MODE_ECB
+ * - \ref TDES_MODE_CBC
+ * - \ref TDES_MODE_CFB
+ * - \ref TDES_MODE_OFB
+ * - \ref TDES_MODE_CTR
+ * @param[in] u32SwapType is TDES input/output data swap control and word swap control, including:
+ * - \ref TDES_NO_SWAP
+ * - \ref TDES_WHL_SWAP
+ * - \ref TDES_OUT_SWAP
+ * - \ref TDES_OUT_WHL_SWAP
+ * - \ref TDES_IN_SWAP
+ * - \ref TDES_IN_WHL_SWAP
+ * - \ref TDES_IN_OUT_SWAP
+ * - \ref TDES_IN_OUT_WHL_SWAP
+ * @return None
+ */
+void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key,
+ uint32_t u32OpMode, uint32_t u32SwapType)
+{
+ g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) |
+ (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) |
+ u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos);
+ if (Is3DES)
+ {
+ g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk;
+ }
+ if (Is3Key)
+ {
+ g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk;
+ }
+}
+
+/**
+ * @brief Start TDES encrypt/decrypt
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32Channel TDES channel. Must be 0~3.
+ * @param[in] u32DMAMode TDES DMA control, including:
+ * - \ref CRYPTO_DMA_ONE_SHOT One shop TDES encrypt/decrypt.
+ * - \ref CRYPTO_DMA_CONTINUE Continuous TDES encrypt/decrypt.
+ * - \ref CRYPTO_DMA_LAST Last TDES encrypt/decrypt of a series of TDES_Start.
+ * @return None
+ */
+void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode)
+{
+ g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_START_Msk | (u32DMAMode << CRPT_TDES_CTL_DMALAST_Pos);
+ crpt->TDES_CTL = g_TDES_CTL[u32Channel];
+}
+
+/**
+ * @brief Set TDES keys
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32Channel TDES channel. Must be 0~3.
+ * @param[in] au32Keys The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word.
+ * @return None
+ */
+void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2])
+{
+ uint32_t i, reg_addr;
+
+ reg_addr = (uint32_t)&crpt->TDES0_KEY1H + (0x40UL * u32Channel);
+
+ for (i = 0U; i < 3U; i++)
+ {
+ outpw(reg_addr, au32Keys[i][0]); /* TDESn_KEYxH */
+ reg_addr += 4UL;
+ outpw(reg_addr, au32Keys[i][1]); /* TDESn_KEYxL */
+ reg_addr += 4UL;
+ }
+}
+
+/**
+ * @brief Set TDES initial vectors
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32Channel TDES channel. Must be 0~3.
+ * @param[in] u32IVH TDES initial vector high word.
+ * @param[in] u32IVL TDES initial vector low word.
+ * @return None
+ */
+void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL)
+{
+ uint32_t reg_addr;
+
+ reg_addr = (uint32_t)&crpt->TDES0_IVH + (u32Channel * 0x40UL);
+ outpw(reg_addr, u32IVH);
+
+ reg_addr = (uint32_t)&crpt->TDES0_IVL + (u32Channel * 0x40UL);
+ outpw(reg_addr, u32IVL);
+}
+
+/**
+ * @brief Set TDES DMA transfer configuration.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32Channel TDES channel. Must be 0~3.
+ * @param[in] u32SrcAddr TDES DMA source address
+ * @param[in] u32DstAddr TDES DMA destination address
+ * @param[in] u32TransCnt TDES DMA transfer byte count
+ * @return None
+ */
+void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr,
+ uint32_t u32DstAddr, uint32_t u32TransCnt)
+{
+ uint32_t reg_addr;
+
+ reg_addr = (uint32_t)&crpt->TDES0_SA + (u32Channel * 0x40UL);
+ outpw(reg_addr, u32SrcAddr);
+
+ reg_addr = (uint32_t)&crpt->TDES0_DA + (u32Channel * 0x40UL);
+ outpw(reg_addr, u32DstAddr);
+
+ reg_addr = (uint32_t)&crpt->TDES0_CNT + (u32Channel * 0x40UL);
+ outpw(reg_addr, u32TransCnt);
+}
+
+/**
+ * @brief Open SHA encrypt function.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32OpMode SHA operation mode, including:
+ * - \ref SHA_MODE_SHA1
+ * - \ref SHA_MODE_SHA224
+ * - \ref SHA_MODE_SHA256
+ * - \ref SHA_MODE_SHA384
+ * - \ref SHA_MODE_SHA512
+ * @param[in] u32SwapType is SHA input/output data swap control, including:
+ * - \ref SHA_NO_SWAP
+ * - \ref SHA_OUT_SWAP
+ * - \ref SHA_IN_SWAP
+ * - \ref SHA_IN_OUT_SWAP
+ * @param[in] hmac_key_len HMAC key byte count
+ * @return None
+ */
+void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len)
+{
+ crpt->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) |
+ (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos);
+
+ if (hmac_key_len != 0UL)
+ {
+ crpt->HMAC_KEYCNT = hmac_key_len;
+
+ if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0)
+ crpt->HMAC_CTL |= (1<<4); /* M480MD HMACEN is CRYPTO_HMAC_CTL[4] */
+ else
+ crpt->HMAC_CTL |= (1<<11); /* M480LD HMACEN is CRYPTO_HMAC_CTL[11] */
+ }
+}
+
+/**
+ * @brief Start SHA encrypt
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32DMAMode TDES DMA control, including:
+ * - \ref CRYPTO_DMA_ONE_SHOT One shop SHA encrypt.
+ * - \ref CRYPTO_DMA_CONTINUE Continuous SHA encrypt.
+ * - \ref CRYPTO_DMA_LAST Last SHA encrypt of a series of SHA_Start.
+ * @return None
+ */
+void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode)
+{
+ crpt->HMAC_CTL &= ~(0x7UL << CRPT_HMAC_CTL_DMALAST_Pos);
+ crpt->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos);
+}
+
+/**
+ * @brief Set SHA DMA transfer
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] u32SrcAddr SHA DMA source address
+ * @param[in] u32TransCnt SHA DMA transfer byte count
+ * @return None
+ */
+void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt)
+{
+ crpt->HMAC_SADDR = u32SrcAddr;
+ crpt->HMAC_DMACNT = u32TransCnt;
+}
+
+/**
+ * @brief Read the SHA digest.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[out] u32Digest The SHA encrypt output digest.
+ * @return None
+ */
+void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[])
+{
+ uint32_t i, wcnt, reg_addr;
+
+ i = (crpt->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos;
+
+ if (i == SHA_MODE_SHA1)
+ {
+ wcnt = 5UL;
+ }
+ else if (i == SHA_MODE_SHA224)
+ {
+ wcnt = 7UL;
+ }
+ else if (i == SHA_MODE_SHA256)
+ {
+ wcnt = 8UL;
+ }
+ else if (i == SHA_MODE_SHA384)
+ {
+ wcnt = 12UL;
+ }
+ else
+ {
+ /* SHA_MODE_SHA512 */
+ wcnt = 16UL;
+ }
+
+ reg_addr = (uint32_t)&(crpt->HMAC_DGST[0]);
+ for (i = 0UL; i < wcnt; i++)
+ {
+ u32Digest[i] = inpw(reg_addr);
+ reg_addr += 4UL;
+ }
+}
+
+/** @cond HIDDEN_SYMBOLS */
+
+/*-----------------------------------------------------------------------------------------------*/
+/* */
+/* ECC */
+/* */
+/*-----------------------------------------------------------------------------------------------*/
+
+#define ECCOP_POINT_MUL (0x0UL << CRPT_ECC_CTL_ECCOP_Pos)
+#define ECCOP_MODULE (0x1UL << CRPT_ECC_CTL_ECCOP_Pos)
+#define ECCOP_POINT_ADD (0x2UL << CRPT_ECC_CTL_ECCOP_Pos)
+#define ECCOP_POINT_DOUBLE (0x0UL << CRPT_ECC_CTL_ECCOP_Pos)
+
+#define MODOP_DIV (0x0UL << CRPT_ECC_CTL_MODOP_Pos)
+#define MODOP_MUL (0x1UL << CRPT_ECC_CTL_MODOP_Pos)
+#define MODOP_ADD (0x2UL << CRPT_ECC_CTL_MODOP_Pos)
+#define MODOP_SUB (0x3UL << CRPT_ECC_CTL_MODOP_Pos)
+
+enum
+{
+ CURVE_GF_P,
+ CURVE_GF_2M,
+};
+
+/*-----------------------------------------------------*/
+/* Define elliptic curve (EC): */
+/*-----------------------------------------------------*/
+
+typedef struct e_curve_t
+{
+ E_ECC_CURVE curve_id;
+ int32_t Echar;
+ char Ea[144];
+ char Eb[144];
+ char Px[144];
+ char Py[144];
+ int32_t Epl;
+ char Pp[176];
+ int32_t Eol;
+ char Eorder[176];
+ int32_t key_len;
+ int32_t irreducible_k1;
+ int32_t irreducible_k2;
+ int32_t irreducible_k3;
+ int32_t GF;
+} ECC_CURVE;
+
+const ECC_CURVE _Curve[] =
+{
+ {
+ /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */
+ CURVE_P_192,
+ 48, /* Echar */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC", /* "000000000000000000000000000000000000000000000003" */
+ "64210519e59c80e70fa7e9ab72243049feb8deecc146b9b1",
+ "188da80eb03090f67cbf20eb43a18800f4ff0afd82ff1012",
+ "07192b95ffc8da78631011ed6b24cdd573f977a11e794811",
+ 58, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF", /* "6277101735386680763835789423207666416083908700390324961279" */
+ 58, /* Eol */
+ "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831", /* "6277101735386680763835789423176059013767194773182842284081" */
+ 192, /* key_len */
+ 7,
+ 2,
+ 1,
+ CURVE_GF_P
+ },
+ {
+ /* NIST: Curve P-224 : y^2=x^3-ax+b (mod p) */
+ CURVE_P_224,
+ 56, /* Echar */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE", /* "00000000000000000000000000000000000000000000000000000003" */
+ "b4050a850c04b3abf54132565044b0b7d7bfd8ba270b39432355ffb4",
+ "b70e0cbd6bb4bf7f321390b94a03c1d356c21122343280d6115c1d21",
+ "bd376388b5f723fb4c22dfe6cd4375a05a07476444d5819985007e34",
+ 70, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "0026959946667150639794667015087019630673557916260026308143510066298881" */
+ 70, /* Eol */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D", /* "0026959946667150639794667015087019625940457807714424391721682722368061" */
+ 224, /* key_len */
+ 9,
+ 8,
+ 3,
+ CURVE_GF_P
+ },
+ {
+ /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */
+ CURVE_P_256,
+ 64, /* Echar */
+ "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC", /* "0000000000000000000000000000000000000000000000000000000000000003" */
+ "5ac635d8aa3a93e7b3ebbd55769886bc651d06b0cc53b0f63bce3c3e27d2604b",
+ "6b17d1f2e12c4247f8bce6e563a440f277037d812deb33a0f4a13945d898c296",
+ "4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5",
+ 78, /* Epl */
+ "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF", /* "115792089210356248762697446949407573530086143415290314195533631308867097853951" */
+ 78, /* Eol */
+ "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551", /* "115792089210356248762697446949407573529996955224135760342422259061068512044369" */
+ 256, /* key_len */
+ 10,
+ 5,
+ 2,
+ CURVE_GF_P
+ },
+ {
+ /* NIST: Curve P-384 : y^2=x^3-ax+b (mod p) */
+ CURVE_P_384,
+ 96, /* Echar */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC", /* "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */
+ "b3312fa7e23ee7e4988e056be3f82d19181d9c6efe8141120314088f5013875ac656398d8a2ed19d2a85c8edd3ec2aef",
+ "aa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7",
+ "3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f",
+ 116, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF", /* "39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319" */
+ 116, /* Eol */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973", /* "39402006196394479212279040100143613805079739270465446667946905279627659399113263569398956308152294913554433653942643" */
+ 384, /* key_len */
+ 12,
+ 3,
+ 2,
+ CURVE_GF_P
+ },
+ {
+ /* NIST: Curve P-521 : y^2=x^3-ax+b (mod p)*/
+ CURVE_P_521,
+ 131, /* Echar */
+ "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC", /* "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */
+ "051953eb9618e1c9a1f929a21a0b68540eea2da725b99b315f3b8b489918ef109e156193951ec7e937b1652c0bd3bb1bf073573df883d2c34f1ef451fd46b503f00",
+ "0c6858e06b70404e9cd9e3ecb662395b4429c648139053fb521f828af606b4d3dbaa14b5e77efe75928fe1dc127a2ffa8de3348b3c1856a429bf97e7e31c2e5bd66",
+ "11839296a789a3bc0045c8a5fb42c7d1bd998f54449579b446817afbd17273e662c97ee72995ef42640c550b9013fad0761353c7086a272c24088be94769fd16650",
+ 157, /* Epl */
+ "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397656052122559640661454554977296311391480858037121987999716643812574028291115057151" */
+ 157, /* Eol */
+ "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397655394245057746333217197532963996371363321113864768612440380340372808892707005449" */
+ 521, /* key_len */
+ 32,
+ 32,
+ 32,
+ CURVE_GF_P
+ },
+ {
+ /* NIST: Curve B-163 : y^2+xy=x^3+ax^2+b */
+ CURVE_B_163,
+ 41, /* Echar */
+ "00000000000000000000000000000000000000001",
+ "20a601907b8c953ca1481eb10512f78744a3205fd",
+ "3f0eba16286a2d57ea0991168d4994637e8343e36",
+ "0d51fbc6c71a0094fa2cdd545b11c5c0c797324f1",
+ 68, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+ 49, /* Eol */
+ "40000000000000000000292FE77E70C12A4234C33", /* "5846006549323611672814742442876390689256843201587" */
+ 163, /* key_len */
+ 7,
+ 6,
+ 3,
+ CURVE_GF_2M
+ },
+ {
+ /* NIST: Curve B-233 : y^2+xy=x^3+ax^2+b */
+ CURVE_B_233,
+ 59, /* Echar 59 */
+ "00000000000000000000000000000000000000000000000000000000001",
+ "066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad",
+ "0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b",
+ "1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052",
+ 68, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+ 70, /* Eol */
+ "1000000000000000000000000000013E974E72F8A6922031D2603CFE0D7", /* "6901746346790563787434755862277025555839812737345013555379383634485463" */
+ 233, /* key_len */
+ 74,
+ 74,
+ 74,
+ CURVE_GF_2M
+ },
+ {
+ /* NIST: Curve B-283 : y^2+xy=x^3+ax^2+b */
+ CURVE_B_283,
+ 71, /* Echar */
+ "00000000000000000000000000000000000000000000000000000000000000000000001",
+ "27b680ac8b8596da5a4af8a19a0303fca97fd7645309fa2a581485af6263e313b79a2f5",
+ "5f939258db7dd90e1934f8c70b0dfec2eed25b8557eac9c80e2e198f8cdbecd86b12053",
+ "3676854fe24141cb98fe6d4b20d02b4516ff702350eddb0826779c813f0df45be8112f4",
+ 68, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+ 85, /* Eol */
+ "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF90399660FC938A90165B042A7CEFADB307", /* "7770675568902916283677847627294075626569625924376904889109196526770044277787378692871" */
+ 283, /* key_len */
+ 12,
+ 7,
+ 5,
+ CURVE_GF_2M
+ },
+ {
+ /* NIST: Curve B-409 : y^2+xy=x^3+ax^2+b */
+ CURVE_B_409,
+ 103, /* Echar */
+ "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+ "021a5c2c8ee9feb5c4b9a753b7b476b7fd6422ef1f3dd674761fa99d6ac27c8a9a197b272822f6cd57a55aa4f50ae317b13545f",
+ "15d4860d088ddb3496b0c6064756260441cde4af1771d4db01ffe5b34e59703dc255a868a1180515603aeab60794e54bb7996a7",
+ "061b1cfab6be5f32bbfa78324ed106a7636b9c5a7bd198d0158aa4f5488d08f38514f1fdf4b4f40d2181b3681c364ba0273c706",
+ 68, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+ 123, /* Eol */
+ "10000000000000000000000000000000000000000000000000001E2AAD6A612F33307BE5FA47C3C9E052F838164CD37D9A21173", /* "661055968790248598951915308032771039828404682964281219284648798304157774827374805208143723762179110965979867288366567526771" */
+ 409, /* key_len */
+ 87,
+ 87,
+ 87,
+ CURVE_GF_2M
+ },
+ {
+ /* NIST: Curve B-571 : y^2+xy=x^3+ax^2+b */
+ CURVE_B_571,
+ 143, /* Echar */
+ "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+ "2f40e7e2221f295de297117b7f3d62f5c6a97ffcb8ceff1cd6ba8ce4a9a18ad84ffabbd8efa59332be7ad6756a66e294afd185a78ff12aa520e4de739baca0c7ffeff7f2955727a",
+ "303001d34b856296c16c0d40d3cd7750a93d1d2955fa80aa5f40fc8db7b2abdbde53950f4c0d293cdd711a35b67fb1499ae60038614f1394abfa3b4c850d927e1e7769c8eec2d19",
+ "37bf27342da639b6dccfffeb73d69d78c6c27a6009cbbca1980f8533921e8a684423e43bab08a576291af8f461bb2a8b3531d2f0485c19b16e2f1516e23dd3c1a4827af1b8ac15b",
+ 68, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+ 172, /* Eol */
+ "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE661CE18FF55987308059B186823851EC7DD9CA1161DE93D5174D66E8382E9BB2FE84E47", /* "3864537523017258344695351890931987344298927329706434998657235251451519142289560424536143999389415773083133881121926944486246872462816813070234528288303332411393191105285703" */
+ 571, /* key_len */
+ 10,
+ 5,
+ 2,
+ CURVE_GF_2M
+ },
+ {
+ /* NIST: Curve K-163 : y^2+xy=x^3+ax^2+b */
+ CURVE_K_163,
+ 41, /* Echar */
+ "00000000000000000000000000000000000000001",
+ "00000000000000000000000000000000000000001",
+ "2fe13c0537bbc11acaa07d793de4e6d5e5c94eee8",
+ "289070fb05d38ff58321f2e800536d538ccdaa3d9",
+ 68, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+ 49, /* Eol */
+ "4000000000000000000020108A2E0CC0D99F8A5EF", /* "5846006549323611672814741753598448348329118574063" */
+ 163, /* key_len */
+ 7,
+ 6,
+ 3,
+ CURVE_GF_2M
+ },
+ {
+ /* NIST: Curve K-233 : y^2+xy=x^3+ax^2+b */
+ CURVE_K_233,
+ 59, /* Echar 59 */
+ "00000000000000000000000000000000000000000000000000000000000",
+ "00000000000000000000000000000000000000000000000000000000001",
+ "17232ba853a7e731af129f22ff4149563a419c26bf50a4c9d6eefad6126",
+ "1db537dece819b7f70f555a67c427a8cd9bf18aeb9b56e0c11056fae6a3",
+ 68, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+ 70, /* Eol */
+ "8000000000000000000000000000069D5BB915BCD46EFB1AD5F173ABDF", /* "3450873173395281893717377931138512760570940988862252126328087024741343" */
+ 233, /* key_len */
+ 74,
+ 74,
+ 74,
+ CURVE_GF_2M
+ },
+ {
+ /* NIST: Curve K-283 : y^2+xy=x^3+ax^2+b */
+ CURVE_K_283,
+ 71, /* Echar */
+ "00000000000000000000000000000000000000000000000000000000000000000000000",
+ "00000000000000000000000000000000000000000000000000000000000000000000001",
+ "503213f78ca44883f1a3b8162f188e553cd265f23c1567a16876913b0c2ac2458492836",
+ "1ccda380f1c9e318d90f95d07e5426fe87e45c0e8184698e45962364e34116177dd2259",
+ 68, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+ 85, /* Eol */
+ "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9AE2ED07577265DFF7F94451E061E163C61", /* "3885337784451458141838923813647037813284811733793061324295874997529815829704422603873" */
+ 283, /* key_len */
+ 12,
+ 7,
+ 5,
+ CURVE_GF_2M
+ },
+ {
+ /* NIST: Curve K-409 : y^2+xy=x^3+ax^2+b */
+ CURVE_K_409,
+ 103, /* Echar */
+ "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+ "060f05f658f49c1ad3ab1890f7184210efd0987e307c84c27accfb8f9f67cc2c460189eb5aaaa62ee222eb1b35540cfe9023746",
+ "1e369050b7c4e42acba1dacbf04299c3460782f918ea427e6325165e9ea10e3da5f6c42e9c55215aa9ca27a5863ec48d8e0286b",
+ 68, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+ 123, /* Eol */
+ "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5F83B2D4EA20400EC4557D5ED3E3E7CA5B4B5C83B8E01E5FCF", /* "330527984395124299475957654016385519914202341482140609642324395022880711289249191050673258457777458014096366590617731358671" */
+ 409, /* key_len */
+ 87,
+ 87,
+ 87,
+ CURVE_GF_2M
+ },
+ {
+ /* NIST: Curve K-571 : y^2+xy=x^3+ax^2+b */
+ CURVE_K_571,
+ 143, /* Echar */
+ "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+ "26eb7a859923fbc82189631f8103fe4ac9ca2970012d5d46024804801841ca44370958493b205e647da304db4ceb08cbbd1ba39494776fb988b47174dca88c7e2945283a01c8972",
+ "349dc807f4fbf374f4aeade3bca95314dd58cec9f307a54ffc61efc006d8a2c9d4979c0ac44aea74fbebbb9f772aedcb620b01a7ba7af1b320430c8591984f601cd4c143ef1c7a3",
+ 68, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+ 172, /* Eol */
+ "20000000000000000000000000000000000000000000000000000000000000000000000131850E1F19A63E4B391A8DB917F4138B630D84BE5D639381E91DEB45CFE778F637C1001", /* "1932268761508629172347675945465993672149463664853217499328617625725759571144780212268133978522706711834706712800825351461273674974066617311929682421617092503555733685276673" */
+ 571, /* key_len */
+ 10,
+ 5,
+ 2,
+ CURVE_GF_2M
+ },
+ {
+ /* Koblitz: Curve secp192k1 : y2 = x3+ax+b over Fp */
+ CURVE_KO_192,
+ 48, /* Echar */
+ "00000000000000000000000000000000000000000",
+ "00000000000000000000000000000000000000003",
+ "DB4FF10EC057E9AE26B07D0280B7F4341DA5D1B1EAE06C7D",
+ "9B2F2F6D9C5628A7844163D015BE86344082AA88D95E2F9D",
+ 58, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFEE37", /* p */
+ 58, /* Eol */
+ "FFFFFFFFFFFFFFFFFFFFFFFE26F2FC170F69466A74DEFD8D", /* n */
+ 192, /* key_len */
+ 7,
+ 2,
+ 1,
+ CURVE_GF_P
+ },
+ {
+ /* Koblitz: Curve secp224k1 : y2 = x3+ax+b over Fp */
+ CURVE_KO_224,
+ 56, /* Echar */
+ "00000000000000000000000000000000000000000000000000000000",
+ "00000000000000000000000000000000000000000000000000000005",
+ "A1455B334DF099DF30FC28A169A467E9E47075A90F7E650EB6B7A45C",
+ "7E089FED7FBA344282CAFBD6F7E319F7C0B0BD59E2CA4BDB556D61A5",
+ 70, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFE56D", /* p */
+ 70, /* Eol */
+ "0000000000000000000000000001DCE8D2EC6184CAF0A971769FB1F7", /* n */
+ 224, /* key_len */
+ 7,
+ 2,
+ 1,
+ CURVE_GF_P
+ },
+ {
+ /* Koblitz: Curve secp256k1 : y2 = x3+ax+b over Fp */
+ CURVE_KO_256,
+ 64, /* Echar */
+ "0000000000000000000000000000000000000000000000000000000000000000",
+ "0000000000000000000000000000000000000000000000000000000000000007",
+ "79BE667EF9DCBBAC55A06295CE870B07029BFCDB2DCE28D959F2815B16F81798",
+ "483ADA7726A3C4655DA4FBFC0E1108A8FD17B448A68554199C47D08FFB10D4B8",
+ 78, /* Epl */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFC2F", /* p */
+ 78, /* Eol */
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBAAEDCE6AF48A03BBFD25E8CD0364141", /* n */
+ 256, /* key_len */
+ 7,
+ 2,
+ 1,
+ CURVE_GF_P
+ },
+ {
+ /* Brainpool: Curve brainpoolP256r1 */
+ CURVE_BP_256,
+ 64, /* Echar */
+ "7D5A0975FC2C3057EEF67530417AFFE7FB8055C126DC5C6CE94A4B44F330B5D9", /* A */
+ "26DC5C6CE94A4B44F330B5D9BBD77CBF958416295CF7E1CE6BCCDC18FF8C07B6", /* B */
+ "8BD2AEB9CB7E57CB2C4B482FFC81B7AFB9DE27E1E3BD23C23A4453BD9ACE3262", /* x */
+ "547EF835C3DAC4FD97F8461A14611DC9C27745132DED8E545C1D54C72F046997", /* y */
+ 78, /* Epl */
+ "A9FB57DBA1EEA9BC3E660A909D838D726E3BF623D52620282013481D1F6E5377", /* p */
+ 78, /* Eol */
+ "A9FB57DBA1EEA9BC3E660A909D838D718C397AA3B561A6F7901E0E82974856A7", /* q */
+ 256, /* key_len */
+ 7,
+ 2,
+ 1,
+ CURVE_GF_P
+ },
+ {
+ /* Brainpool: Curve brainpoolP384r1 */
+ CURVE_BP_384,
+ 96, /* Echar */
+ "7BC382C63D8C150C3C72080ACE05AFA0C2BEA28E4FB22787139165EFBA91F90F8AA5814A503AD4EB04A8C7DD22CE2826", /* A */
+ "04A8C7DD22CE28268B39B55416F0447C2FB77DE107DCD2A62E880EA53EEB62D57CB4390295DBC9943AB78696FA504C11", /* B */
+ "1D1C64F068CF45FFA2A63A81B7C13F6B8847A3E77EF14FE3DB7FCAFE0CBD10E8E826E03436D646AAEF87B2E247D4AF1E", /* x */
+ "8ABE1D7520F9C2A45CB1EB8E95CFD55262B70B29FEEC5864E19C054FF99129280E4646217791811142820341263C5315", /* y */
+ 116, /* Epl */
+ "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B412B1DA197FB71123ACD3A729901D1A71874700133107EC53", /* p */
+ 116, /* Eol */
+ "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B31F166E6CAC0425A7CF3AB6AF6B7FC3103B883202E9046565", /* q */
+ 384, /* key_len */
+ 7,
+ 2,
+ 1,
+ CURVE_GF_P
+ },
+ {
+ /* Brainpool: Curve brainpoolP512r1 */
+ CURVE_BP_512,
+ 128, /* Echar */
+ "7830A3318B603B89E2327145AC234CC594CBDD8D3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CA", /* A */
+ "3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CADC083E67984050B75EBAE5DD2809BD638016F723", /* B */
+ "81AEE4BDD82ED9645A21322E9C4C6A9385ED9F70B5D916C1B43B62EEF4D0098EFF3B1F78E2D0D48D50D1687B93B97D5F7C6D5047406A5E688B352209BCB9F822", /* x */
+ "7DDE385D566332ECC0EABFA9CF7822FDF209F70024A57B1AA000C55B881F8111B2DCDE494A5F485E5BCA4BD88A2763AED1CA2B2FA8F0540678CD1E0F3AD80892", /* y */
+ 156, /* Epl */
+ "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA703308717D4D9B009BC66842AECDA12AE6A380E62881FF2F2D82C68528AA6056583A48F3", /* p */
+ 156, /* Eol */
+ "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA70330870553E5C414CA92619418661197FAC10471DB1D381085DDADDB58796829CA90069", /* q */
+ 512, /* key_len */
+ 7,
+ 2,
+ 1,
+ CURVE_GF_P
+ },
+};
+
+static ECC_CURVE *pCurve;
+static ECC_CURVE Curve_Copy;
+
+static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve);
+static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve);
+static void run_ecc_codec(CRPT_T *crpt, uint32_t mode);
+
+static char temp_hex_str[160];
+
+
+#if ENABLE_DEBUG
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count)
+{
+ int32_t i;
+
+ printf("%s => ", str);
+ for (i = 0; i < count; i++)
+ {
+ printf("0x%08x ", regs[i]);
+ }
+ printf("\n");
+}
+#else
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count)
+{
+}
+#endif
+
+static char ch2hex(char ch)
+{
+ if (ch <= '9')
+ {
+ ch = ch - '0';
+ }
+ else if ((ch <= 'z') && (ch >= 'a'))
+ {
+ ch = ch - 'a' + 10U;
+ }
+ else
+ {
+ ch = ch - 'A' + 10U;
+ }
+ return ch;
+}
+
+static void Hex2Reg(char input[], uint32_t volatile reg[])
+{
+ char hex;
+ int si, ri;
+ uint32_t i, val32;
+
+ si = (int)strlen(input) - 1;
+ ri = 0;
+
+ while (si >= 0)
+ {
+ val32 = 0UL;
+ for (i = 0UL; (i < 8UL) && (si >= 0); i++)
+ {
+ hex = ch2hex(input[si]);
+ val32 |= (uint32_t)hex << (i * 4UL);
+ si--;
+ }
+ reg[ri++] = val32;
+ }
+}
+
+static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift)
+{
+ uint32_t hex, carry;
+ int si, ri;
+ uint32_t i, val32;
+
+ si = (int)strlen(input) - 1;
+ ri = 0L;
+ carry = 0UL;
+ while (si >= 0)
+ {
+ val32 = 0UL;
+ for (i = 0UL; (i < 8UL) && (si >= 0L); i++)
+ {
+ hex = (uint32_t)ch2hex(input[si]);
+ hex <<= shift;
+
+ val32 |= (uint32_t)((hex & 0xFUL) | carry) << (i * 4UL);
+ carry = (hex >> 4UL) & 0xFUL;
+ si--;
+ }
+ reg[ri++] = val32;
+ }
+ if (carry != 0UL)
+ {
+ reg[ri] = carry;
+ }
+}
+
+/**
+ * @brief Extract specified nibble from an unsigned word in character format.
+ * For example:
+ * Suppose val32 is 0x786543210, get_Nth_nibble_char(val32, 3) will return a '3'.
+ * @param[in] val32 The input unsigned word
+ * @param[in] idx The Nth nibble to be extracted.
+ * @return The nibble in character format.
+ */
+static char get_Nth_nibble_char(uint32_t val32, uint32_t idx)
+{
+ return hex_char_tbl[ (val32 >> (idx * 4U)) & 0xfU ];
+}
+
+
+static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[])
+{
+ int32_t idx, ri;
+ uint32_t i;
+
+ output[count] = 0U;
+ idx = count - 1;
+
+ for (ri = 0; idx >= 0; ri++)
+ {
+ for (i = 0UL; (i < 8UL) && (idx >= 0); i++)
+ {
+ output[idx] = get_Nth_nibble_char(reg[ri], i);
+ idx--;
+ }
+ }
+}
+
+static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve)
+{
+ uint32_t i;
+ ECC_CURVE *ret = NULL;
+
+ for (i = 0UL; i < sizeof(_Curve) / sizeof(ECC_CURVE); i++)
+ {
+ if (ecc_curve == _Curve[i].curve_id)
+ {
+ memcpy((char *)&Curve_Copy, &_Curve[i], sizeof(ECC_CURVE));
+ ret = &Curve_Copy; /* (ECC_CURVE *)&_Curve[i]; */
+ }
+ if (ret != NULL)
+ {
+ break;
+ }
+ }
+ return ret;
+}
+
+static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve)
+{
+ int32_t i, ret = 0;
+
+ pCurve = get_curve(ecc_curve);
+ if (pCurve == NULL)
+ {
+ CRPT_DBGMSG("Cannot find curve %d!!\n", ecc_curve);
+ ret = -1;
+ }
+
+ if (ret == 0)
+ {
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_A[i] = 0UL;
+ crpt->ECC_B[i] = 0UL;
+ crpt->ECC_X1[i] = 0UL;
+ crpt->ECC_Y1[i] = 0UL;
+ crpt->ECC_N[i] = 0UL;
+ }
+
+ Hex2Reg(pCurve->Ea, crpt->ECC_A);
+ Hex2Reg(pCurve->Eb, crpt->ECC_B);
+ Hex2Reg(pCurve->Px, crpt->ECC_X1);
+ Hex2Reg(pCurve->Py, crpt->ECC_Y1);
+
+ CRPT_DBGMSG("Key length = %d\n", pCurve->key_len);
+ dump_ecc_reg("CRPT_ECC_CURVE_A", crpt->ECC_A, 10);
+ dump_ecc_reg("CRPT_ECC_CURVE_B", crpt->ECC_B, 10);
+ dump_ecc_reg("CRPT_ECC_POINT_X1", crpt->ECC_X1, 10);
+ dump_ecc_reg("CRPT_ECC_POINT_Y1", crpt->ECC_Y1, 10);
+
+ if (pCurve->GF == (int)CURVE_GF_2M)
+ {
+ crpt->ECC_N[0] = 0x1UL;
+ crpt->ECC_N[(pCurve->key_len) / 32] |= (1UL << ((pCurve->key_len) % 32));
+ crpt->ECC_N[(pCurve->irreducible_k1) / 32] |= (1UL << ((pCurve->irreducible_k1) % 32));
+ crpt->ECC_N[(pCurve->irreducible_k2) / 32] |= (1UL << ((pCurve->irreducible_k2) % 32));
+ crpt->ECC_N[(pCurve->irreducible_k3) / 32] |= (1UL << ((pCurve->irreducible_k3) % 32));
+ }
+ else
+ {
+ Hex2Reg(pCurve->Pp, crpt->ECC_N);
+ }
+ }
+ dump_ecc_reg("CRPT_ECC_CURVE_N", crpt->ECC_N, 10);
+ return ret;
+}
+
+static int get_nibble_value(char c)
+{
+ if ((c >= '0') && (c <= '9'))
+ {
+ c = c - '0';
+ }
+
+ if ((c >= 'a') && (c <= 'f'))
+ {
+ c = c - 'a' + (char)10;
+ }
+
+ if ((c >= 'A') && (c <= 'F'))
+ {
+ c = c - 'A' + (char)10;
+ }
+ return (int)c;
+}
+
+static int ecc_strcmp(char *s1, char *s2)
+{
+ char c1, c2;
+
+ while (*s1 == '0') s1++;
+ while (*s2 == '0') s2++;
+
+ for ( ; *s1 || *s2; s1++, s2++)
+ {
+ if ((*s1 >= 'A') && (*s1 <= 'Z'))
+ c1 = *s1 + 32;
+ else
+ c1 = *s1;
+
+ if ((*s2 >= 'A') && (*s2 <= 'Z'))
+ c2 = *s2 + 32;
+ else
+ c2 = *s2;
+
+ if (c1 != c2)
+ return 1;
+ }
+ return 0;
+}
+
+volatile uint32_t g_ECC_done, g_ECCERR_done;
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+ * @brief ECC interrupt service routine. User application must invoke this function in
+ * his CRYPTO_IRQHandler() to let Crypto driver know ECC processing was done.
+ * @param[in] crpt Reference to Crypto module.
+ * @return none
+ */
+void ECC_Complete(CRPT_T *crpt)
+{
+ if (crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk)
+ {
+ g_ECC_done = 1UL;
+ crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk;
+ /* printf("ECC done IRQ.\n"); */
+ }
+
+ if (crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk)
+ {
+ g_ECCERR_done = 1UL;
+ crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk;
+ /* printf("ECCERRIF is set!!\n"); */
+ }
+}
+
+/**
+ * @brief Check if the private key is located in valid range of curve.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[in] private_k The input private key.
+ * @return 1 Is valid.
+ * @return 0 Is not valid.
+ * @return -1 Invalid curve.
+ */
+int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[])
+{
+ uint32_t i;
+ int ret = -1;
+
+ pCurve = get_curve(ecc_curve);
+ if (pCurve == NULL)
+ {
+ ret = -1;
+ }
+
+ if (strlen(private_k) < strlen(pCurve->Eorder))
+ {
+ ret = 1;
+ }
+
+ if (strlen(private_k) > strlen(pCurve->Eorder))
+ {
+ ret = 0;
+ }
+
+ for (i = 0UL; i < strlen(private_k); i++)
+ {
+ if (get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i]))
+ {
+ ret = 1;
+ break;
+ }
+ if (get_nibble_value(private_k[i]) > get_nibble_value(pCurve->Eorder[i]))
+ {
+ ret = 0;
+ break;
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Given a private key and curve to generate the public key pair.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] private_k The input private key.
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[out] public_k1 The output public key 1.
+ * @param[out] public_k2 The output public key 2.
+ * @return 0 Success.
+ * @return -1 "ecc_curve" value is invalid.
+ */
+int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[])
+{
+ int32_t i, ret = 0;
+
+ if (ecc_init_curve(crpt, ecc_curve) != 0)
+ {
+ ret = -1;
+ }
+
+ if (ret == 0)
+ {
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_K[i] = 0UL;
+ }
+ Hex2Reg(private_k, crpt->ECC_K);
+
+ /* set FSEL (Field selection) */
+ if (pCurve->GF == (int)CURVE_GF_2M)
+ {
+ crpt->ECC_CTL = 0UL;
+ }
+ else
+ {
+ /* CURVE_GF_P */
+ crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+ }
+
+ g_ECC_done = g_ECCERR_done = 0UL;
+ crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |
+ ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;
+
+ while ((g_ECC_done | g_ECCERR_done) == 0UL)
+ {
+ }
+
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1);
+ Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Given a private key and curve to generate the public key pair.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[out] x1 The x-coordinate of input point.
+ * @param[out] y1 The y-coordinate of input point.
+ * @param[in] k The private key
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[out] x2 The x-coordinate of output point.
+ * @param[out] y2 The y-coordinate of output point.
+ * @return 0 Success.
+ * @return -1 "ecc_curve" value is invalid.
+ */
+int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[])
+{
+ int32_t i, ret = 0;
+
+ if (ecc_init_curve(crpt, ecc_curve) != 0)
+ {
+ ret = -1;
+ }
+
+ if (ret == 0)
+ {
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_X1[i] = 0UL;
+ crpt->ECC_Y1[i] = 0UL;
+ crpt->ECC_K[i] = 0UL;
+ }
+ Hex2Reg(x1, crpt->ECC_X1);
+ Hex2Reg(y1, crpt->ECC_Y1);
+ Hex2Reg(k, crpt->ECC_K);
+
+ /* set FSEL (Field selection) */
+ if (pCurve->GF == (int)CURVE_GF_2M)
+ {
+ crpt->ECC_CTL = 0UL;
+ }
+ else
+ {
+ /* CURVE_GF_P */
+ crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+ }
+
+ g_ECC_done = g_ECCERR_done = 0UL;
+ crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |
+ ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;
+
+ while ((g_ECC_done | g_ECCERR_done) == 0UL)
+ {
+ }
+
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, x2);
+ Reg2Hex(pCurve->Echar, crpt->ECC_Y1, y2);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[in] private_k One's own private key.
+ * @param[in] public_k1 The other party's publick key 1.
+ * @param[in] public_k2 The other party's publick key 2.
+ * @param[out] secret_z The ECC CDH secret Z.
+ * @return 0 Success.
+ * @return -1 "ecc_curve" value is invalid.
+ */
+int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[])
+{
+ int32_t i, ret = 0;
+
+ if (ecc_init_curve(crpt, ecc_curve) != 0)
+ {
+ ret = -1;
+ }
+
+ if (ret == 0)
+ {
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_K[i] = 0UL;
+ crpt->ECC_X1[i] = 0UL;
+ crpt->ECC_Y1[i] = 0UL;
+ }
+
+ if ((ecc_curve == CURVE_B_163) || (ecc_curve == CURVE_B_233) || (ecc_curve == CURVE_B_283) ||
+ (ecc_curve == CURVE_B_409) || (ecc_curve == CURVE_B_571) || (ecc_curve == CURVE_K_163))
+ {
+ Hex2RegEx(private_k, crpt->ECC_K, 1);
+ }
+ else if ((ecc_curve == CURVE_K_233) || (ecc_curve == CURVE_K_283) ||
+ (ecc_curve == CURVE_K_409) || (ecc_curve == CURVE_K_571))
+ {
+ Hex2RegEx(private_k, crpt->ECC_K, 2);
+ }
+ else
+ {
+ Hex2Reg(private_k, crpt->ECC_K);
+ }
+
+ Hex2Reg(public_k1, crpt->ECC_X1);
+ Hex2Reg(public_k2, crpt->ECC_Y1);
+
+ /* set FSEL (Field selection) */
+ if (pCurve->GF == (int)CURVE_GF_2M)
+ {
+ crpt->ECC_CTL = 0UL;
+ }
+ else
+ {
+ /* CURVE_GF_P */
+ crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+ }
+ g_ECC_done = g_ECCERR_done = 0UL;
+ crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |
+ ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;
+
+ while ((g_ECC_done | g_ECCERR_done) == 0UL)
+ {
+ }
+
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, secret_z);
+ }
+
+ return ret;
+}
+
+/** @cond HIDDEN_SYMBOLS */
+
+static void run_ecc_codec(CRPT_T *crpt, uint32_t mode)
+{
+ if ((mode & CRPT_ECC_CTL_ECCOP_Msk) == ECCOP_MODULE)
+ {
+ crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+ }
+ else
+ {
+ if (pCurve->GF == (int)CURVE_GF_2M)
+ {
+ /* point */
+ crpt->ECC_CTL = 0UL;
+ }
+ else
+ {
+ /* CURVE_GF_P */
+ crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+ }
+ }
+
+ g_ECC_done = g_ECCERR_done = 0UL;
+ crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | mode | CRPT_ECC_CTL_START_Msk;
+ while ((g_ECC_done | g_ECCERR_done) == 0UL)
+ {
+ }
+
+ while (crpt->ECC_STS & CRPT_ECC_STS_BUSY_Msk)
+ {
+ }
+}
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+ * @brief ECDSA digital signature generation.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[in] message The hash value of source context.
+ * @param[in] d The private key.
+ * @param[in] k The selected random integer.
+ * @param[out] R R of the (R,S) pair digital signature
+ * @param[out] S S of the (R,S) pair digital signature
+ * @return 0 Success.
+ * @return -1 "ecc_curve" value is invalid.
+ */
+int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
+ char *d, char *k, char *R, char *S)
+{
+ uint32_t volatile temp_result1[18], temp_result2[18];
+ int32_t i, ret = 0;
+
+ if (ecc_init_curve(crpt, ecc_curve) != 0)
+ {
+ ret = -1;
+ }
+
+ if (ret == 0)
+ {
+ /*
+ * 1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1)
+ * (1) Use SHA to calculate e
+ */
+
+ /* 2. Select a random integer k form [1, n-1]
+ * (1) Notice that n is order, not prime modulus or irreducible polynomial function
+ */
+
+ /*
+ * 3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2
+ * (1) Write the curve parameter A, B, and curve length M to corresponding registers
+ * (2) Write the prime modulus or irreducible polynomial function to N registers according
+ * (3) Write the point G(x, y) to X1, Y1 registers
+ * (4) Write the random integer k to K register
+ * (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+ * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field
+ * (7) Set START(CRPT_ECC_CTL[0]) to 1
+ * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (9) Write the curve order and curve length to N ,M registers according
+ * (10) Write 0x0 to Y1 registers
+ * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+ * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+ * (13) Set START(CRPT_ECC_CTL[0]) to 1 *
+ * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (15) Read X1 registers to get r
+ */
+
+ /* 3-(4) Write the random integer k to K register */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_K[i] = 0UL;
+ }
+ Hex2Reg(k, crpt->ECC_K);
+
+ run_ecc_codec(crpt, ECCOP_POINT_MUL);
+
+ /* 3-(9) Write the curve order to N registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_N[i] = 0UL;
+ }
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+ /* 3-(10) Write 0x0 to Y1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_Y1[i] = 0UL;
+ }
+
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
+
+ /* 3-(15) Read X1 registers to get r */
+ for (i = 0; i < 18; i++)
+ {
+ temp_result1[i] = crpt->ECC_X1[i];
+ }
+
+ Reg2Hex(pCurve->Echar, temp_result1, R);
+
+ /*
+ * 4. Compute s = k ? 1 ¡Ñ (e + d ¡Ñ r)(mod n). If s = 0, go to step 2
+ * (1) Write the curve order to N registers according
+ * (2) Write 0x1 to Y1 registers
+ * (3) Write the random integer k to X1 registers according
+ * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+ * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00
+ * (6) Set START(CRPT_ECC_CTL[0]) to 1
+ * (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (8) Read X1 registers to get k^-1
+ * (9) Write the curve order and curve length to N ,M registers
+ * (10) Write r, d to X1, Y1 registers
+ * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+ * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+ * (13) Set START(CRPT_ECC_CTL[0]) to 1
+ * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (15) Write the curve order to N registers
+ * (16) Write e to Y1 registers
+ * (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+ * (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+ * (19) Set START(CRPT_ECC_CTL[0]) to 1
+ * (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (21) Write the curve order and curve length to N ,M registers
+ * (22) Write k^-1 to Y1 registers
+ * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+ * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+ * (25) Set START(CRPT_ECC_CTL[0]) to 1
+ * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (27) Read X1 registers to get s
+ */
+
+ /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */
+
+ /* 4-(1) Write the curve order to N registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_N[i] = 0UL;
+ }
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+ /* 4-(2) Write 0x1 to Y1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_Y1[i] = 0UL;
+ }
+ crpt->ECC_Y1[0] = 0x1UL;
+
+ /* 4-(3) Write the random integer k to X1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_X1[i] = 0UL;
+ }
+ Hex2Reg(k, crpt->ECC_X1);
+
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV);
+
+#if ENABLE_DEBUG
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+ CRPT_DBGMSG("(7) output = %s\n", temp_hex_str);
+#endif
+
+ /* 4-(8) Read X1 registers to get k^-1 */
+
+ for (i = 0; i < 18; i++)
+ {
+ temp_result2[i] = crpt->ECC_X1[i];
+ }
+
+#if ENABLE_DEBUG
+ Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+ CRPT_DBGMSG("k^-1 = %s\n", temp_hex_str);
+#endif
+
+ /* 4-(9) Write the curve order and curve length to N ,M registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_N[i] = 0UL;
+ }
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+ /* 4-(10) Write r, d to X1, Y1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_X1[i] = temp_result1[i];
+ }
+
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_Y1[i] = 0UL;
+ }
+ Hex2Reg(d, crpt->ECC_Y1);
+
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);
+
+#if ENABLE_DEBUG
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+ CRPT_DBGMSG("(14) output = %s\n", temp_hex_str);
+#endif
+
+ /* 4-(15) Write the curve order to N registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_N[i] = 0UL;
+ }
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+ /* 4-(16) Write e to Y1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_Y1[i] = 0UL;
+ }
+ Hex2Reg(message, crpt->ECC_Y1);
+
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
+
+#if ENABLE_DEBUG
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+ CRPT_DBGMSG("(20) output = %s\n", temp_hex_str);
+#endif
+
+ /* 4-(21) Write the curve order and curve length to N ,M registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_N[i] = 0UL;
+ }
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+ /* 4-(22) Write k^-1 to Y1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_Y1[i] = temp_result2[i];
+ }
+
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);
+
+ /* 4-(27) Read X1 registers to get s */
+ for (i = 0; i < 18; i++)
+ {
+ temp_result2[i] = crpt->ECC_X1[i];
+ }
+
+ Reg2Hex(pCurve->Echar, temp_result2, S);
+
+ } /* ret == 0 */
+
+ return ret;
+}
+
+/**
+ * @brief ECDSA dogotal signature verification.
+ * @param[in] crpt Reference to Crypto module.
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[in] message The hash value of source context.
+ * @param[in] public_k1 The public key 1.
+ * @param[in] public_k2 The public key 2.
+ * @param[in] R R of the (R,S) pair digital signature
+ * @param[in] S S of the (R,S) pair digital signature
+ * @return 0 Success.
+ * @return -1 "ecc_curve" value is invalid.
+ * @return -2 Verification failed.
+ */
+int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
+ char *public_k1, char *public_k2, char *R, char *S)
+{
+ uint32_t temp_result1[18], temp_result2[18];
+ uint32_t temp_x[18], temp_y[18];
+ int32_t i, ret = 0;
+
+ /*
+ * 1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid
+ * 2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation
+ * (1) Use SHA to calculate e
+ */
+
+ /*
+ * 3. Compute w = s^-1 (mod n)
+ * (1) Write the curve order to N registers
+ * (2) Write 0x1 to Y1 registers
+ * (3) Write s to X1 registers
+ * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+ * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00
+ * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field
+ * (7) Set START(CRPT_ECC_CTL[0]) to 1
+ * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (9) Read X1 registers to get w
+ */
+
+ if (ecc_init_curve(crpt, ecc_curve) != 0)
+ {
+ ret = -1;
+ }
+
+ if (ret == 0)
+ {
+ /* 3-(1) Write the curve order to N registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_N[i] = 0UL;
+ }
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+ /* 3-(2) Write 0x1 to Y1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_Y1[i] = 0UL;
+ }
+ crpt->ECC_Y1[0] = 0x1UL;
+
+ /* 3-(3) Write s to X1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_X1[i] = 0UL;
+ }
+ Hex2Reg(S, crpt->ECC_X1);
+
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV);
+
+ /* 3-(9) Read X1 registers to get w */
+ for (i = 0; i < 18; i++)
+ {
+ temp_result2[i] = crpt->ECC_X1[i];
+ }
+
+#if ENABLE_DEBUG
+ CRPT_DBGMSG("e = %s\n", message);
+ Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+ CRPT_DBGMSG("w = %s\n", temp_hex_str);
+ CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder);
+#endif
+
+ /*
+ * 4. Compute u1 = e ¡Ñ w (mod n) and u2 = r ¡Ñ w (mod n)
+ * (1) Write the curve order and curve length to N ,M registers
+ * (2) Write e, w to X1, Y1 registers
+ * (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+ * (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+ * (5) Set START(CRPT_ECC_CTL[0]) to 1
+ * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (7) Read X1 registers to get u1
+ * (8) Write the curve order and curve length to N ,M registers
+ * (9) Write r, w to X1, Y1 registers
+ * (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+ * (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+ * (12) Set START(CRPT_ECC_CTL[0]) to 1
+ * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (14) Read X1 registers to get u2
+ */
+
+ /* 4-(1) Write the curve order and curve length to N ,M registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_N[i] = 0UL;
+ }
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+ /* 4-(2) Write e, w to X1, Y1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_X1[i] = 0UL;
+ }
+ Hex2Reg(message, crpt->ECC_X1);
+
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_Y1[i] = temp_result2[i];
+ }
+
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);
+
+ /* 4-(7) Read X1 registers to get u1 */
+ for (i = 0; i < 18; i++)
+ {
+ temp_result1[i] = crpt->ECC_X1[i];
+ }
+
+#if ENABLE_DEBUG
+ Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str);
+ CRPT_DBGMSG("u1 = %s\n", temp_hex_str);
+#endif
+
+ /* 4-(8) Write the curve order and curve length to N ,M registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_N[i] = 0UL;
+ }
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+ /* 4-(9) Write r, w to X1, Y1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_X1[i] = 0UL;
+ }
+ Hex2Reg(R, crpt->ECC_X1);
+
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_Y1[i] = temp_result2[i];
+ }
+
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);
+
+ /* 4-(14) Read X1 registers to get u2 */
+ for (i = 0; i < 18; i++)
+ {
+ temp_result2[i] = crpt->ECC_X1[i];
+ }
+
+#if ENABLE_DEBUG
+ Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+ CRPT_DBGMSG("u2 = %s\n", temp_hex_str);
+#endif
+
+ /*
+ * 5. Compute X¡¦ (x1¡¦, y1¡¦) = u1 * G + u2 * Q
+ * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
+ * (2) Write the point G(x, y) to X1, Y1 registers
+ * (3) Write u1 to K registers
+ * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+ * (5) Set START(CRPT_ECC_CTL[0]) to 1
+ * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (7) Read X1, Y1 registers to get u1*G
+ * (8) Write the curve parameter A, B, N, and curve length M to corresponding registers
+ * (9) Write the public key Q(x,y) to X1, Y1 registers
+ * (10) Write u2 to K registers
+ * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+ * (12) Set START(CRPT_ECC_CTL[0]) to 1
+ * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (14) Write the curve parameter A, B, N, and curve length M to corresponding registers
+ * (15) Write the result data u1*G to X2, Y2 registers
+ * (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10
+ * (17) Set START(CRPT_ECC_CTL[0]) to 1
+ * (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (19) Read X1, Y1 registers to get X¡¦(x1¡¦, y1¡¦)
+ * (20) Write the curve order and curve length to N ,M registers
+ * (21) Write x1¡¦ to X1 registers
+ * (22) Write 0x0 to Y1 registers
+ * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+ * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+ * (25) Set START(CRPT_ECC_CTL[0]) to 1
+ * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+ * (27) Read X1 registers to get x1¡¦ (mod n)
+ *
+ * 6. The signature is valid if x1¡¦ = r, otherwise it is invalid
+ */
+
+ /*
+ * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
+ * (2) Write the point G(x, y) to X1, Y1 registers
+ */
+ ecc_init_curve(crpt, ecc_curve);
+
+ /* (3) Write u1 to K registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_K[i] = temp_result1[i];
+ }
+
+ run_ecc_codec(crpt, ECCOP_POINT_MUL);
+
+ /* (7) Read X1, Y1 registers to get u1*G */
+ for (i = 0; i < 18; i++)
+ {
+ temp_x[i] = crpt->ECC_X1[i];
+ temp_y[i] = crpt->ECC_Y1[i];
+ }
+
+#if ENABLE_DEBUG
+ Reg2Hex(pCurve->Echar, temp_x, temp_hex_str);
+ CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str);
+ Reg2Hex(pCurve->Echar, temp_y, temp_hex_str);
+ CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str);
+#endif
+
+ /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */
+ ecc_init_curve(crpt, ecc_curve);
+
+ /* (9) Write the public key Q(x,y) to X1, Y1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_X1[i] = 0UL;
+ crpt->ECC_Y1[i] = 0UL;
+ }
+
+ Hex2Reg(public_k1, crpt->ECC_X1);
+ Hex2Reg(public_k2, crpt->ECC_Y1);
+
+ /* (10) Write u2 to K registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_K[i] = temp_result2[i];
+ }
+
+ run_ecc_codec(crpt, ECCOP_POINT_MUL);
+
+ for (i = 0; i < 18; i++)
+ {
+ temp_result1[i] = crpt->ECC_X1[i];
+ temp_result2[i] = crpt->ECC_Y1[i];
+ }
+
+#if ENABLE_DEBUG
+ Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str);
+ CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str);
+ Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+ CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str);
+#endif
+
+ /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */
+ ecc_init_curve(crpt, ecc_curve);
+
+ /* Write the result data u2*Q to X1, Y1 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_X1[i] = temp_result1[i];
+ crpt->ECC_Y1[i] = temp_result2[i];
+ }
+
+ /* (15) Write the result data u1*G to X2, Y2 registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_X2[i] = temp_x[i];
+ crpt->ECC_Y2[i] = temp_y[i];
+ }
+
+ run_ecc_codec(crpt, ECCOP_POINT_ADD);
+
+ /* (19) Read X1, Y1 registers to get X¡¦(x1¡¦, y1¡¦) */
+ for (i = 0; i < 18; i++)
+ {
+ temp_x[i] = crpt->ECC_X1[i];
+ temp_y[i] = crpt->ECC_Y1[i];
+ }
+
+#if ENABLE_DEBUG
+ Reg2Hex(pCurve->Echar, temp_x, temp_hex_str);
+ CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str);
+ Reg2Hex(pCurve->Echar, temp_y, temp_hex_str);
+ CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str);
+#endif
+
+ /* (20) Write the curve order and curve length to N ,M registers */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_N[i] = 0UL;
+ }
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+ /*
+ * (21) Write x1¡¦ to X1 registers
+ * (22) Write 0x0 to Y1 registers
+ */
+ for (i = 0; i < 18; i++)
+ {
+ crpt->ECC_X1[i] = temp_x[i];
+ crpt->ECC_Y1[i] = 0UL;
+ }
+
+#if ENABLE_DEBUG
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+ CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str);
+ Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str);
+ CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str);
+#endif
+
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
+
+ /* (27) Read X1 registers to get x1¡¦ (mod n) */
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+ CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str);
+
+ /* 6. The signature is valid if x1¡¦ = r, otherwise it is invalid */
+
+ /* Compare with test pattern to check if r is correct or not */
+ if (ecc_strcmp(temp_hex_str, R) != 0)
+ {
+ CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n");
+ CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R);
+ ret = -2;
+ }
+ } /* ret == 0 */
+
+ return ret;
+}
+
+/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CRYPTO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_dac.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_dac.c
new file mode 100644
index 00000000000..1ed45773952
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_dac.c
@@ -0,0 +1,90 @@
+/**************************************************************************//**
+ * @file dac.c
+ * @version V1.00
+ * @brief M480 series DAC driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup DAC_Driver DAC Driver
+ @{
+*/
+
+/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make DAC module be ready to convert.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M480 DAC.
+ * @param[in] u32TrgSrc Decides the trigger source. Valid values are:
+ * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger
+ * - \ref DAC_SOFTWARE_TRIGGER :Software trigger
+ * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger
+ * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger
+ * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger
+ * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger
+ * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger
+ * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger
+ * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger
+ * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger
+ * - \ref DAC_EPWM0_TRIGGER :EPWM0 trigger
+ * - \ref DAC_EPWM1_TRIGGER :EPWM1 trigger
+ * @return None
+ * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger.
+ * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register.
+ * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1,
+ * external STDAC pin, timer event, or EPWM event.
+ */
+void DAC_Open(DAC_T *dac,
+ uint32_t u32Ch,
+ uint32_t u32TrgSrc)
+{
+ dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk);
+ dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk);
+}
+
+/**
+ * @brief Disable DAC analog power.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M480 DAC.
+ * @return None
+ * @details Disable DAC analog power for saving power consumption.
+ */
+void DAC_Close(DAC_T *dac, uint32_t u32Ch)
+{
+ dac->CTL &= (~DAC_CTL_DACEN_Msk);
+}
+
+/**
+ * @brief Set delay time for DAC to become stable.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds.
+ * @return Real DAC conversion settling time (micro second).
+ * @details For example, DAC controller clock speed is 160MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0xA0.
+ * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed.
+ */
+uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
+{
+
+ dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL);
+
+ return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq());
+}
+
+
+
+/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group DAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_eadc.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_eadc.c
new file mode 100644
index 00000000000..f7ef09d97ba
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_eadc.c
@@ -0,0 +1,143 @@
+/**************************************************************************//**
+ * @file eadc.c
+ * @version V2.00
+ * @brief M480 series EADC driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EADC_Driver EADC Driver
+ @{
+*/
+
+/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make EADC_module be ready to convert.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32InputMode Decides the input mode.
+ * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode.
+ * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type.
+ * @return None
+ * @details This function is used to set analog input mode and enable A/D Converter.
+ * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
+ * @note
+ */
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
+{
+ eadc->CTL &= (~EADC_CTL_DIFFEN_Msk);
+
+ eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk);
+ while (!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {}
+}
+
+/**
+ * @brief Disable EADC_module.
+ * @param[in] eadc The pointer of the specified EADC module..
+ * @return None
+ * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
+ */
+void EADC_Close(EADC_T *eadc)
+{
+ eadc->CTL &= ~EADC_CTL_ADCEN_Msk;
+}
+
+/**
+ * @brief Configure the sample control logic module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+ * @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
+ * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger
+ * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger
+ * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger
+ * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger
+ * - \ref EADC_ADINT0_TRIGGER : EADC ADINT0 interrupt EOC pulse trigger
+ * - \ref EADC_ADINT1_TRIGGER : EADC ADINT1 interrupt EOC pulse trigger
+ * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger
+ * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger
+ * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger
+ * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger
+ * - \ref EADC_EPWM0TG0_TRIGGER : EPWM0TG0 trigger
+ * - \ref EADC_EPWM0TG1_TRIGGER : EPWM0TG1 trigger
+ * - \ref EADC_EPWM0TG2_TRIGGER : EPWM0TG2 trigger
+ * - \ref EADC_EPWM0TG3_TRIGGER : EPWM0TG3 trigger
+ * - \ref EADC_EPWM0TG4_TRIGGER : EPWM0TG4 trigger
+ * - \ref EADC_EPWM0TG5_TRIGGER : EPWM0TG5 trigger
+ * - \ref EADC_EPWM1TG0_TRIGGER : EPWM1TG0 trigger
+ * - \ref EADC_EPWM1TG1_TRIGGER : EPWM1TG1 trigger
+ * - \ref EADC_EPWM1TG2_TRIGGER : EPWM1TG2 trigger
+ * - \ref EADC_EPWM1TG3_TRIGGER : EPWM1TG3 trigger
+ * - \ref EADC_EPWM1TG4_TRIGGER : EPWM1TG4 trigger
+ * - \ref EADC_EPWM1TG5_TRIGGER : EPWM1TG5 trigger
+ * - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger
+ * - \ref EADC_BPWM1TG_TRIGGER : BPWM1TG trigger
+ * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
+ * @return None
+ * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.
+ * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
+ */
+void EADC_ConfigSampleModule(EADC_T *eadc, \
+ uint32_t u32ModuleNum, \
+ uint32_t u32TriggerSrc, \
+ uint32_t u32Channel)
+{
+ eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk);
+ eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel);
+}
+
+
+/**
+ * @brief Set trigger delay time.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+ * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.
+ * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16
+ * @return None
+ * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).
+ * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
+ */
+void EADC_SetTriggerDelayTime(EADC_T *eadc, \
+ uint32_t u32ModuleNum, \
+ uint32_t u32TriggerDelayTime, \
+ uint32_t u32DelayClockDivider)
+{
+ eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk);
+ eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);
+}
+
+/**
+ * @brief Set ADC extend sample time.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+ * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
+ * @return None
+ * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
+ * user can extend A/D sampling time after trigger source is coming to get enough sampling time.
+ */
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
+{
+ eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk;
+
+ eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);
+
+}
+
+/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EADC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ebi.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ebi.c
new file mode 100644
index 00000000000..2a2bd28de6e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ebi.c
@@ -0,0 +1,195 @@
+/**************************************************************************//**
+ * @file ebi.c
+ * @version V3.00
+ * @brief M480 series External Bus Interface(EBI) driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EBI_Driver EBI Driver
+ @{
+*/
+
+
+/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Initialize EBI for specify Bank
+ *
+ * @param[in] u32Bank Bank number for EBI. Valid values are:
+ * - \ref EBI_BANK0
+ * - \ref EBI_BANK1
+ * - \ref EBI_BANK2
+ * @param[in] u32DataWidth Data bus width. Valid values are:
+ * - \ref EBI_BUSWIDTH_8BIT
+ * - \ref EBI_BUSWIDTH_16BIT
+ * @param[in] u32TimingClass Default timing configuration. Valid values are:
+ * - \ref EBI_TIMING_FASTEST
+ * - \ref EBI_TIMING_VERYFAST
+ * - \ref EBI_TIMING_FAST
+ * - \ref EBI_TIMING_NORMAL
+ * - \ref EBI_TIMING_SLOW
+ * - \ref EBI_TIMING_VERYSLOW
+ * - \ref EBI_TIMING_SLOWEST
+ * @param[in] u32BusMode Set EBI bus operate mode. Valid values are:
+ * - \ref EBI_OPMODE_NORMAL
+ * - \ref EBI_OPMODE_CACCESS
+ * - \ref EBI_OPMODE_ADSEPARATE
+ * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are:
+ * - \ref EBI_CS_ACTIVE_HIGH
+ * - \ref EBI_CS_ACTIVE_LOW
+ *
+ * @return None
+ *
+ * @details This function is used to open specify EBI bank with different bus width, timing setting and \n
+ * active level of CS pin to access EBI device.
+ * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.
+ */
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
+{
+ uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U;
+ uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U;
+ volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index0 );
+ volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 );
+
+ if(u32DataWidth == EBI_BUSWIDTH_8BIT)
+ {
+ *pu32EBICTL &= ~EBI_CTL_DW16_Msk;
+ }
+ else
+ {
+ *pu32EBICTL |= EBI_CTL_DW16_Msk;
+ }
+
+ *pu32EBICTL |= u32BusMode;
+
+ switch(u32TimingClass)
+ {
+ case EBI_TIMING_FASTEST:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+ (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
+ *pu32EBITCTL = 0x0U;
+ break;
+
+ case EBI_TIMING_VERYFAST:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+ (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+ (0x3U << EBI_CTL_TALE_Pos) ;
+ *pu32EBITCTL = 0x03003318U;
+ break;
+
+ case EBI_TIMING_FAST:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+ (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
+ *pu32EBITCTL = 0x0U;
+ break;
+
+ case EBI_TIMING_NORMAL:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+ (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+ (0x3U << EBI_CTL_TALE_Pos) ;
+ *pu32EBITCTL = 0x03003318U;
+ break;
+
+ case EBI_TIMING_SLOW:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+ (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+ (0x7U << EBI_CTL_TALE_Pos) ;
+ *pu32EBITCTL = 0x07007738U;
+ break;
+
+ case EBI_TIMING_VERYSLOW:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+ (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+ (0x7U << EBI_CTL_TALE_Pos) ;
+ *pu32EBITCTL = 0x07007738U;
+ break;
+
+ case EBI_TIMING_SLOWEST:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+ (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+ (0x7U << EBI_CTL_TALE_Pos) ;
+ *pu32EBITCTL = 0x07007738U;
+ break;
+
+ default:
+ *pu32EBICTL &= ~EBI_CTL_EN_Msk;
+ break;
+ }
+}
+
+/**
+ * @brief Disable EBI on specify Bank
+ *
+ * @param[in] u32Bank Bank number for EBI. Valid values are:
+ * - \ref EBI_BANK0
+ * - \ref EBI_BANK1
+ * - \ref EBI_BANK2
+ *
+ * @return None
+ *
+ * @details This function is used to close specify EBI function.
+ */
+void EBI_Close(uint32_t u32Bank)
+{
+ uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U;
+ volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index );
+
+ *pu32EBICTL &= ~EBI_CTL_EN_Msk;
+}
+
+/**
+ * @brief Set EBI Bus Timing for specify Bank
+ *
+ * @param[in] u32Bank Bank number for EBI. Valid values are:
+ * - \ref EBI_BANK0
+ * - \ref EBI_BANK1
+ * - \ref EBI_BANK2
+ * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.
+ * @param[in] u32MclkDiv Divider for MCLK. Valid values are:
+ * - \ref EBI_MCLKDIV_1
+ * - \ref EBI_MCLKDIV_2
+ * - \ref EBI_MCLKDIV_4
+ * - \ref EBI_MCLKDIV_8
+ * - \ref EBI_MCLKDIV_16
+ * - \ref EBI_MCLKDIV_32
+ * - \ref EBI_MCLKDIV_64
+ * - \ref EBI_MCLKDIV_128
+ *
+ * @return None
+ *
+ * @details This function is used to configure specify EBI bus timing for access EBI device.
+ */
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
+{
+ uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U;
+ uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U;
+ volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index0 );
+ volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 );
+
+ *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);
+ *pu32EBITCTL = u32TimingConfig;
+}
+
+/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EBI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ecap.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ecap.c
new file mode 100644
index 00000000000..f0a9e772809
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ecap.c
@@ -0,0 +1,118 @@
+/**************************************************************************//**
+ * @file ecap.c
+ * @version V3.00
+ * @brief Enhanced Input Capture Timer (ECAP) driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup ECAP_Driver ECAP Driver
+ @{
+*/
+
+/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions
+ @{
+*/
+
+/**
+ * @brief Enable ECAP function
+ * @param[in] ecap The pointer of the specified ECAP module.
+ * @param[in] u32FuncMask Input capture function select
+ * - \ref ECAP_DISABLE_COMPARE
+ * - \ref ECAP_COMPARE_FUNCTION
+ * @return None
+ * @details This macro enable input capture function and select compare and reload function.
+ */
+void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask)
+{
+ /* Clear Input capture mode*/
+ ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk);
+
+ /* Enable Input Capture and set mode */
+ ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask);
+}
+
+
+
+/**
+ * @brief Disable ECAP function
+ * @param[in] ecap The pointer of the specified ECAP module.
+ * @return None
+ * @details This macro disable input capture function.
+ */
+void ECAP_Close(ECAP_T* ecap)
+{
+ /* Disable Input Capture*/
+ ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk;
+}
+
+/**
+ * @brief This macro is used to enable input channel interrupt
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Mask The input channel Mask
+ * - \ref ECAP_CTL0_CAPIEN0_Msk
+ * - \ref ECAP_CTL0_CAPIEN1_Msk
+ * - \ref ECAP_CTL0_CAPIEN2_Msk
+ * - \ref ECAP_CTL0_OVIEN_Msk
+ * - \ref ECAP_CTL0_CMPIEN_Msk
+ * @return None
+ * @details This macro will enable the input channel_n interrupt.
+ */
+void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask)
+{
+ /* Enable input channel interrupt */
+ ecap->CTL0 |= (u32Mask);
+
+ /* Enable NVIC ECAP IRQ */
+ if(ecap == (ECAP_T*)ECAP0)
+ {
+ NVIC_EnableIRQ((IRQn_Type)ECAP0_IRQn);
+ }
+ else
+ {
+ NVIC_EnableIRQ((IRQn_Type)ECAP1_IRQn);
+ }
+}
+
+/**
+ * @brief This macro is used to disable input channel interrupt
+ * @param[in] ecap Specify ECAP port
+ * @param[in] u32Mask The input channel number
+ * - \ref ECAP_CTL0_CAPIEN0_Msk
+ * - \ref ECAP_CTL0_CAPIEN1_Msk
+ * - \ref ECAP_CTL0_CAPIEN2_Msk
+ * - \ref ECAP_CTL0_OVIEN_Msk
+ * - \ref ECAP_CTL0_CMPIEN_Msk
+ * @return None
+ * @details This macro will disable the input channel_n interrupt.
+ */
+void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask)
+{
+ /* Disable input channel interrupt */
+ ecap->CTL0 &= ~(u32Mask);
+
+ /* Disable NVIC ECAP IRQ */
+ if(ecap == (ECAP_T*)ECAP0)
+ {
+ NVIC_DisableIRQ((IRQn_Type)ECAP0_IRQn);
+ }
+ else
+ {
+ NVIC_DisableIRQ((IRQn_Type)ECAP1_IRQn);
+ }
+}
+
+/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group ECAP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_emac.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_emac.c
new file mode 100644
index 00000000000..2b93f1ddd9c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_emac.c
@@ -0,0 +1,1178 @@
+/**************************************************************************//**
+ * @file emac.c
+ * @version V1.00
+ * @brief M480 EMAC driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include
+#include
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EMAC_Driver EMAC Driver
+ @{
+*/
+
+
+/* Below are structure, definitions, static variables used locally by EMAC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */
+/** @cond HIDDEN_SYMBOLS */
+
+/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
+ @{
+*/
+
+/* PHY Register Description */
+#define PHY_CNTL_REG 0x00UL /*!< PHY control register address */
+#define PHY_STATUS_REG 0x01UL /*!< PHY status register address */
+#define PHY_ID1_REG 0x02UL /*!< PHY ID1 register */
+#define PHY_ID2_REG 0x03UL /*!< PHY ID2 register */
+#define PHY_ANA_REG 0x04UL /*!< PHY auto-negotiation advertisement register */
+#define PHY_ANLPA_REG 0x05UL /*!< PHY auto-negotiation link partner availability register */
+#define PHY_ANE_REG 0x06UL /*!< PHY auto-negotiation expansion register */
+
+/* PHY Control Register */
+#define PHY_CNTL_RESET_PHY (1UL << 15UL)
+#define PHY_CNTL_DR_100MB (1UL << 13UL)
+#define PHY_CNTL_ENABLE_AN (1UL << 12UL)
+#define PHY_CNTL_POWER_DOWN (1UL << 11UL)
+#define PHY_CNTL_RESTART_AN (1UL << 9UL)
+#define PHY_CNTL_FULLDUPLEX (1UL << 8UL)
+
+/* PHY Status Register */
+#define PHY_STATUS_AN_COMPLETE (1UL << 5UL)
+#define PHY_STATUS_LINK_VALID (1UL << 2UL)
+
+/* PHY Auto-negotiation Advertisement Register */
+#define PHY_ANA_DR100_TX_FULL (1UL << 8UL)
+#define PHY_ANA_DR100_TX_HALF (1UL << 7UL)
+#define PHY_ANA_DR10_TX_FULL (1UL << 6UL)
+#define PHY_ANA_DR10_TX_HALF (1UL << 5UL)
+#define PHY_ANA_IEEE_802_3_CSMA_CD (1UL << 0UL)
+
+/* PHY Auto-negotiation Link Partner Advertisement Register */
+#define PHY_ANLPA_DR100_TX_FULL (1UL << 8UL)
+#define PHY_ANLPA_DR100_TX_HALF (1UL << 7UL)
+#define PHY_ANLPA_DR10_TX_FULL (1UL << 6UL)
+#define PHY_ANLPA_DR10_TX_HALF (1UL << 5UL)
+
+/* EMAC Tx/Rx descriptor's owner bit */
+#define EMAC_DESC_OWN_EMAC 0x80000000UL /*!< Set owner to EMAC */
+#define EMAC_DESC_OWN_CPU 0x00000000UL /*!< Set owner to CPU */
+
+/* Rx Frame Descriptor Status */
+#define EMAC_RXFD_RTSAS 0x0080UL /*!< Time Stamp Available */
+#define EMAC_RXFD_RP 0x0040UL /*!< Runt Packet */
+#define EMAC_RXFD_ALIE 0x0020UL /*!< Alignment Error */
+#define EMAC_RXFD_RXGD 0x0010UL /*!< Receiving Good packet received */
+#define EMAC_RXFD_PTLE 0x0008UL /*!< Packet Too Long Error */
+#define EMAC_RXFD_CRCE 0x0002UL /*!< CRC Error */
+#define EMAC_RXFD_RXINTR 0x0001UL /*!< Interrupt on receive */
+
+/* Tx Frame Descriptor's Control bits */
+#define EMAC_TXFD_TTSEN 0x08UL /*!< Tx time stamp enable */
+#define EMAC_TXFD_INTEN 0x04UL /*!< Tx interrupt enable */
+#define EMAC_TXFD_CRCAPP 0x02UL /*!< Append CRC */
+#define EMAC_TXFD_PADEN 0x01UL /*!< Padding mode enable */
+
+/* Tx Frame Descriptor Status */
+#define EMAC_TXFD_TXINTR 0x0001UL /*!< Interrupt on Transmit */
+#define EMAC_TXFD_DEF 0x0002UL /*!< Transmit deferred */
+#define EMAC_TXFD_TXCP 0x0008UL /*!< Transmission Completion */
+#define EMAC_TXFD_EXDEF 0x0010UL /*!< Exceed Deferral */
+#define EMAC_TXFD_NCS 0x0020UL /*!< No Carrier Sense Error */
+#define EMAC_TXFD_TXABT 0x0040UL /*!< Transmission Abort */
+#define EMAC_TXFD_LC 0x0080UL /*!< Late Collision */
+#define EMAC_TXFD_TXHA 0x0100UL /*!< Transmission halted */
+#define EMAC_TXFD_PAU 0x0200UL /*!< Paused */
+#define EMAC_TXFD_SQE 0x0400UL /*!< SQE error */
+#define EMAC_TXFD_TTSAS 0x0800UL /*!< Time Stamp available */
+
+/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */
+
+/** @addtogroup EMAC_EXPORTED_TYPEDEF EMAC Exported Type Defines
+ @{
+*/
+
+/** Tx/Rx buffer descriptor structure */
+typedef struct
+{
+ uint32_t u32Status1; /*!< Status word 1 */
+ uint32_t u32Data; /*!< Pointer to data buffer */
+ uint32_t u32Status2; /*!< Status word 2 */
+ uint32_t u32Next; /*!< Pointer to next descriptor */
+ uint32_t u32Backup1; /*!< For backup descriptor fields over written by time stamp */
+ uint32_t u32Backup2; /*!< For backup descriptor fields over written by time stamp */
+} EMAC_DESCRIPTOR_T;
+
+/** Tx/Rx buffer structure */
+typedef struct
+{
+ uint8_t au8Buf[EMAC_MAX_PKT_SIZE];
+} EMAC_FRAME_T;
+
+/*@}*/ /* end of group EMAC_EXPORTED_TYPEDEF */
+
+/* local variables */
+static volatile EMAC_DESCRIPTOR_T rx_desc[EMAC_RX_DESC_SIZE];
+static volatile EMAC_FRAME_T rx_buf[EMAC_RX_DESC_SIZE];
+static volatile EMAC_DESCRIPTOR_T tx_desc[EMAC_TX_DESC_SIZE];
+static volatile EMAC_FRAME_T tx_buf[EMAC_TX_DESC_SIZE];
+
+
+static uint32_t u32CurrentTxDesc, u32NextTxDesc, u32CurrentRxDesc;
+static uint32_t s_u32EnableTs = 0UL;
+
+static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data);
+static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr);
+static void EMAC_TxDescInit(void);
+static void EMAC_RxDescInit(void);
+static uint32_t EMAC_Subsec2Nsec(uint32_t subsec);
+static uint32_t EMAC_Nsec2Subsec(uint32_t nsec);
+
+/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Write PHY register
+ * @param[in] u32Reg PHY register number
+ * @param[in] u32Addr PHY address, this address is board dependent
+ * @param[in] u32Data data to write to PHY register
+ * @return None
+ */
+static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data)
+{
+ /* Set data register */
+ EMAC->MIIMDAT = u32Data ;
+ /* Set PHY address, PHY register address, busy bit and write bit */
+ EMAC->MIIMCTL = u32Reg | (u32Addr << 8) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MIIMCTL_MDCON_Msk;
+
+ /* Wait write complete by polling busy bit. */
+ while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk)
+ {
+ ;
+ }
+
+}
+
+/**
+ * @brief Read PHY register
+ * @param[in] u32Reg PHY register number
+ * @param[in] u32Addr PHY address, this address is board dependent
+ * @return Value read from PHY register
+ */
+static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr)
+{
+ /* Set PHY address, PHY register address, busy bit */
+ EMAC->MIIMCTL = u32Reg | (u32Addr << EMAC_MIIMCTL_PHYADDR_Pos) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk;
+
+ /* Wait read complete by polling busy bit */
+ while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk)
+ {
+ ;
+ }
+
+ /* Get return data */
+ return EMAC->MIIMDAT;
+}
+
+/**
+ * @brief Initialize PHY chip, check for the auto-negotiation result.
+ * @param None
+ * @return None
+ */
+void EMAC_PhyInit(void)
+{
+ uint32_t reg;
+ uint32_t i = 0UL;
+
+ /* Reset Phy Chip */
+ EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, PHY_CNTL_RESET_PHY);
+
+ /* Wait until reset complete */
+ while (1)
+ {
+ reg = EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) ;
+
+ if ((reg & PHY_CNTL_RESET_PHY) == 0UL)
+ {
+ break;
+ }
+ }
+
+ while (!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID))
+ {
+ if (i++ > 80000UL) /* Cable not connected */
+ {
+ EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+ EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+ break;
+ }
+ }
+
+ if (i <= 80000UL)
+ {
+ /* Configure auto negotiation capability */
+ EMAC_MdioWrite(PHY_ANA_REG, EMAC_PHY_ADDR, PHY_ANA_DR100_TX_FULL |
+ PHY_ANA_DR100_TX_HALF |
+ PHY_ANA_DR10_TX_FULL |
+ PHY_ANA_DR10_TX_HALF |
+ PHY_ANA_IEEE_802_3_CSMA_CD);
+ /* Restart auto negotiation */
+ EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) | PHY_CNTL_RESTART_AN);
+
+ /* Wait for auto-negotiation complete */
+ while (!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_AN_COMPLETE))
+ {
+ ;
+ }
+
+ /* Check link valid again. Some PHYs needs to check result after link valid bit set */
+ while (!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID))
+ {
+ ;
+ }
+
+ /* Check link partner capability */
+ reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ;
+
+ if (reg & PHY_ANLPA_DR100_TX_FULL)
+ {
+ EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
+ EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
+ }
+ else if (reg & PHY_ANLPA_DR100_TX_HALF)
+ {
+ EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
+ EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+ }
+ else if (reg & PHY_ANLPA_DR10_TX_FULL)
+ {
+ EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+ EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
+ }
+ else
+ {
+ EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+ EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+ }
+ }
+}
+
+/**
+ * @brief Initial EMAC Tx descriptors and get Tx descriptor base address
+ * @param None
+ * @return None
+ */
+static void EMAC_TxDescInit(void)
+{
+ uint32_t i;
+
+ /* Get Frame descriptor's base address. */
+ EMAC->TXDSA = (uint32_t)&tx_desc[0];
+ u32NextTxDesc = u32CurrentTxDesc = (uint32_t)&tx_desc[0];
+
+ for (i = 0UL; i < EMAC_TX_DESC_SIZE; i++)
+ {
+
+ if (s_u32EnableTs)
+ {
+ tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN;
+ }
+ else
+ {
+ tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN | EMAC_TXFD_TTSEN;
+ }
+
+ tx_desc[i].u32Data = (uint32_t)((uint32_t)&tx_buf[i]);
+ tx_desc[i].u32Backup1 = tx_desc[i].u32Data;
+ tx_desc[i].u32Status2 = 0UL;
+ tx_desc[i].u32Next = (uint32_t)&tx_desc[(i + 1UL) % EMAC_TX_DESC_SIZE];
+ tx_desc[i].u32Backup2 = tx_desc[i].u32Next;
+
+ }
+
+}
+
+
+/**
+ * @brief Initial EMAC Rx descriptors and get Rx descriptor base address
+ * @param None
+ * @return None
+ */
+static void EMAC_RxDescInit(void)
+{
+
+ uint32_t i;
+
+ /* Get Frame descriptor's base address. */
+ EMAC->RXDSA = (uint32_t)&rx_desc[0];
+ u32CurrentRxDesc = (uint32_t)&rx_desc[0];
+
+ for (i = 0UL; i < EMAC_RX_DESC_SIZE; i++)
+ {
+ rx_desc[i].u32Status1 = EMAC_DESC_OWN_EMAC;
+ rx_desc[i].u32Data = (uint32_t)((uint32_t)&rx_buf[i]);
+ rx_desc[i].u32Backup1 = rx_desc[i].u32Data;
+ rx_desc[i].u32Status2 = 0UL;
+ rx_desc[i].u32Next = (uint32_t)&rx_desc[(i + 1UL) % EMAC_RX_DESC_SIZE];
+ rx_desc[i].u32Backup2 = rx_desc[i].u32Next;
+ }
+
+}
+
+/**
+ * @brief Convert subsecond value to nano second
+ * @param[in] subsec Subsecond value to be convert
+ * @return Nano second
+ */
+static uint32_t EMAC_Subsec2Nsec(uint32_t subsec)
+{
+ /* 2^31 subsec == 10^9 ns */
+ uint64_t i;
+ i = 1000000000ull * (uint64_t)subsec;
+ i >>= 31;
+ return ((uint32_t)i);
+}
+
+/**
+ * @brief Convert nano second to subsecond value
+ * @param[in] nsec Nano second to be convert
+ * @return Subsecond
+ */
+static uint32_t EMAC_Nsec2Subsec(uint32_t nsec)
+{
+ /* 10^9 ns = 2^31 subsec */
+ uint64_t i;
+ i = (1ull << 31) * nsec;
+ i /= 1000000000ull;
+ return ((uint32_t)i);
+}
+
+
+/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */
+
+
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Initialize EMAC interface, including descriptors, MAC address, and PHY.
+ * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address
+ * @return None
+ * @note This API configures EMAC to receive all broadcast and multicast packets, but could configure to other settings with
+ * \ref EMAC_ENABLE_RECV_BCASTPKT, \ref EMAC_DISABLE_RECV_BCASTPKT, \ref EMAC_ENABLE_RECV_MCASTPKT, and \ref EMAC_DISABLE_RECV_MCASTPKT
+ * @note Receive(RX) and transmit(TX) are not enabled yet, application must call \ref EMAC_ENABLE_RX and \ref EMAC_ENABLE_TX to
+ * enable receive and transmit function.
+ */
+void EMAC_Open(uint8_t *pu8MacAddr)
+{
+ /* Enable transmit and receive descriptor */
+ EMAC_TxDescInit();
+ EMAC_RxDescInit();
+
+ /* Set the CAM Control register and the MAC address value */
+ EMAC_SetMacAddr(pu8MacAddr);
+
+ /* Configure the MAC interrupt enable register. */
+ EMAC->INTEN = EMAC_INTEN_RXIEN_Msk |
+ EMAC_INTEN_TXIEN_Msk |
+ EMAC_INTEN_RXGDIEN_Msk |
+ EMAC_INTEN_TXCPIEN_Msk |
+ EMAC_INTEN_RXBEIEN_Msk |
+ EMAC_INTEN_TXBEIEN_Msk |
+ EMAC_INTEN_RDUIEN_Msk |
+ EMAC_INTEN_TSALMIEN_Msk |
+ EMAC_INTEN_WOLIEN_Msk;
+
+ /* Configure the MAC control register. */
+ EMAC->CTL = EMAC_CTL_STRIPCRC_Msk |
+ EMAC_CTL_RMIIEN_Msk;
+
+ /* Accept packets for us and all broadcast and multicast packets */
+ EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk |
+ EMAC_CAMCTL_AMP_Msk |
+ EMAC_CAMCTL_ABP_Msk;
+
+ /* Limit the max receive frame length to 1514 + 4 */
+ EMAC->MRFL = EMAC_MAX_PKT_SIZE;
+}
+
+/**
+ * @brief This function stop all receive and transmit activity and disable MAC interface
+ * @param None
+ * @return None
+ */
+
+void EMAC_Close(void)
+{
+ EMAC->CTL |= EMAC_CTL_RST_Msk;
+
+ while (EMAC->CTL & EMAC_CTL_RST_Msk) {}
+}
+
+/**
+ * @brief Set the device MAC address
+ * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address
+ * @return None
+ */
+void EMAC_SetMacAddr(uint8_t *pu8MacAddr)
+{
+ EMAC_EnableCamEntry(0UL, pu8MacAddr);
+
+}
+
+/**
+ * @brief Fill a CAM entry for MAC address comparison.
+ * @param[in] u32Entry MAC entry to fill. Entry 0 is used to store device MAC address, do not overwrite the setting in it.
+ * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address
+ * @return None
+ */
+void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[])
+{
+ uint32_t u32Lsw, u32Msw;
+ uint32_t reg;
+ u32Lsw = (uint32_t)(((uint32_t)pu8MacAddr[4] << 24) |
+ ((uint32_t)pu8MacAddr[5] << 16));
+ u32Msw = (uint32_t)(((uint32_t)pu8MacAddr[0] << 24) |
+ ((uint32_t)pu8MacAddr[1] << 16) |
+ ((uint32_t)pu8MacAddr[2] << 8) |
+ (uint32_t)pu8MacAddr[3]);
+
+ reg = (uint32_t)&EMAC->CAM0M + u32Entry * 2UL * 4UL;
+ *(uint32_t volatile *)reg = u32Msw;
+ reg = (uint32_t)&EMAC->CAM0L + u32Entry * 2UL * 4UL;
+ *(uint32_t volatile *)reg = u32Lsw;
+
+ EMAC->CAMEN |= (1UL << u32Entry);
+}
+
+/**
+ * @brief Disable a specified CAM entry
+ * @param[in] u32Entry CAM entry to be disabled
+ * @return None
+ */
+void EMAC_DisableCamEntry(uint32_t u32Entry)
+{
+ EMAC->CAMEN &= ~(1UL << u32Entry);
+}
+
+
+/**
+ * @brief Receive an Ethernet packet
+ * @param[in] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed)
+ * @param[in] pu32Size Received packet size (without 4 byte CRC).
+ * @return Packet receive success or not
+ * @retval 0 No packet available for receive
+ * @retval 1 A packet is received
+ * @note Return 0 doesn't guarantee the packet will be sent and received successfully.
+ */
+uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size)
+{
+ EMAC_DESCRIPTOR_T *desc;
+ uint32_t status, reg;
+ uint32_t u32Count = 0UL;
+
+ /* Clear Rx interrupt flags */
+ reg = EMAC->INTSTS;
+ EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all RX related interrupt status */
+
+ if (reg & EMAC_INTSTS_RXBEIF_Msk)
+ {
+ /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+ while (1) {}
+ }
+ else
+ {
+
+ /* Get Rx Frame Descriptor */
+ desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
+
+ /* If we reach last recv Rx descriptor, leave the loop */
+ if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) /* ownership=CPU */
+ {
+
+ status = desc->u32Status1 >> 16;
+
+ /* If Rx frame is good, process received frame */
+ if (status & EMAC_RXFD_RXGD)
+ {
+ /* lower 16 bit in descriptor status1 stores the Rx packet length */
+ *pu32Size = desc->u32Status1 & 0xFFFFUL;
+ memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size);
+ u32Count = 1UL;
+ }
+ else
+ {
+ /* Save Error status if necessary */
+ if (status & EMAC_RXFD_RP) {}
+
+ if (status & EMAC_RXFD_ALIE) {}
+
+ if (status & EMAC_RXFD_PTLE) {}
+
+ if (status & EMAC_RXFD_CRCE) {}
+ }
+ }
+ }
+
+ return (u32Count);
+}
+
+/**
+ * @brief Receive an Ethernet packet and the time stamp while it's received
+ * @param[out] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed)
+ * @param[out] pu32Size Received packet size (without 4 byte CRC).
+ * @param[out] pu32Sec Second value while packet received
+ * @param[out] pu32Nsec Nano second value while packet received
+ * @return Packet receive success or not
+ * @retval 0 No packet available for receive
+ * @retval 1 A packet is received
+ * @note Return 0 doesn't guarantee the packet will be sent and received successfully.
+ * @note Largest Ethernet packet is 1514 bytes after stripped CRC, application must give
+ * a buffer large enough to store such packet
+ */
+uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec)
+{
+ EMAC_DESCRIPTOR_T *desc;
+ uint32_t status, reg;
+ uint32_t u32Count = 0UL;
+
+ /* Clear Rx interrupt flags */
+ reg = EMAC->INTSTS;
+ EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all Rx related interrupt status */
+
+ if (reg & EMAC_INTSTS_RXBEIF_Msk)
+ {
+ /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+ while (1) {}
+ }
+ else
+ {
+
+ /* Get Rx Frame Descriptor */
+ desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
+
+ /* If we reach last recv Rx descriptor, leave the loop */
+ if (EMAC->CRXDSA != (uint32_t)desc)
+ {
+ if ((desc->u32Status1 | EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) /* ownership=CPU */
+ {
+
+ status = desc->u32Status1 >> 16;
+
+ /* If Rx frame is good, process received frame */
+ if (status & EMAC_RXFD_RXGD)
+ {
+ /* lower 16 bit in descriptor status1 stores the Rx packet length */
+ *pu32Size = desc->u32Status1 & 0xFFFFUL;
+ memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size);
+
+ *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */
+ *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */
+
+ u32Count = 1UL;
+ }
+ else
+ {
+ /* Save Error status if necessary */
+ if (status & EMAC_RXFD_RP) {}
+
+ if (status & EMAC_RXFD_ALIE) {}
+
+ if (status & EMAC_RXFD_PTLE) {}
+
+ if (status & EMAC_RXFD_CRCE) {}
+ }
+ }
+ }
+ }
+
+ return (u32Count);
+}
+
+/**
+ * @brief Clean up process after a packet is received
+ * @param None
+ * @return None
+ * @details EMAC Rx interrupt service routine \b must call this API to release the resource use by receive process
+ * @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1
+ */
+void EMAC_RecvPktDone(void)
+{
+ EMAC_DESCRIPTOR_T *desc;
+ /* Get Rx Frame Descriptor */
+ desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
+
+ /* Restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+ desc->u32Data = desc->u32Backup1;
+ desc->u32Next = desc->u32Backup2;
+
+ /* Change ownership to DMA for next use */
+ desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
+
+ /* Get Next Frame Descriptor pointer to process */
+ desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+
+ /* Save last processed Rx descriptor */
+ u32CurrentRxDesc = (uint32_t)desc;
+
+ EMAC_TRIGGER_RX();
+}
+
+
+/**
+ * @brief Send an Ethernet packet
+ * @param[in] pu8Data Pointer to a buffer holds the packet to transmit
+ * @param[in] u32Size Packet size (without 4 byte CRC).
+ * @return Packet transmit success or not
+ * @retval 0 Transmit failed due to descriptor unavailable.
+ * @retval 1 Packet is copied to descriptor and triggered to transmit.
+ * @note Return 1 doesn't guarantee the packet will be sent and received successfully.
+ */
+uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size)
+{
+ EMAC_DESCRIPTOR_T *desc;
+ uint32_t status;
+ uint32_t ret = 0UL;
+ /* Get Tx frame descriptor & data pointer */
+ desc = (EMAC_DESCRIPTOR_T *)u32NextTxDesc;
+
+ status = desc->u32Status1;
+
+ /* Check descriptor ownership */
+ if ((status & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC)
+ {
+ memcpy((uint8_t *)desc->u32Data, pu8Data, u32Size);
+
+ /* Set Tx descriptor transmit byte count */
+ desc->u32Status2 = u32Size;
+
+ /* Change descriptor ownership to EMAC */
+ desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
+
+ /* Get next Tx descriptor */
+ u32NextTxDesc = (uint32_t)(desc->u32Next);
+
+ /* Trigger EMAC to send the packet */
+ EMAC_TRIGGER_TX();
+ ret = 1UL;
+ }
+
+ return (ret);
+}
+
+
+/**
+ * @brief Clean up process after packet(s) are sent
+ * @param None
+ * @return Number of packet sent between two function calls
+ * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDoneTS to
+ * release the resource use by transmit process
+ */
+uint32_t EMAC_SendPktDone(void)
+{
+ EMAC_DESCRIPTOR_T *desc;
+ uint32_t status, reg;
+ uint32_t last_tx_desc;
+ uint32_t u32Count = 0UL;
+
+ reg = EMAC->INTSTS;
+ /* Clear Tx interrupt flags */
+ EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk);
+
+
+ if (reg & EMAC_INTSTS_TXBEIF_Msk)
+ {
+ /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+ while (1) {}
+ }
+ else
+ {
+ /* Process the descriptor(s). */
+ last_tx_desc = EMAC->CTXDSA ;
+ /* Get our first descriptor to process */
+ desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc;
+
+ do
+ {
+ /* Descriptor ownership is still EMAC, so this packet haven't been send. */
+ if (desc->u32Status1 & EMAC_DESC_OWN_EMAC)
+ {
+ break;
+ }
+
+ /* Get Tx status stored in descriptor */
+ status = desc->u32Status2 >> 16UL;
+
+ if (status & EMAC_TXFD_TXCP)
+ {
+ u32Count++;
+ }
+ else
+ {
+ /* Do nothing here on error. */
+ if (status & EMAC_TXFD_TXABT) {}
+
+ if (status & EMAC_TXFD_DEF) {}
+
+ if (status & EMAC_TXFD_PAU) {}
+
+ if (status & EMAC_TXFD_EXDEF) {}
+
+ if (status & EMAC_TXFD_NCS) {}
+
+ if (status & EMAC_TXFD_SQE) {}
+
+ if (status & EMAC_TXFD_LC) {}
+
+ if (status & EMAC_TXFD_TXHA) {}
+ }
+
+ /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+ desc->u32Data = desc->u32Backup1;
+ desc->u32Next = desc->u32Backup2;
+ /* go to next descriptor in link */
+ desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+ } while (last_tx_desc != (uint32_t)desc); /* If we reach last sent Tx descriptor, leave the loop */
+
+ /* Save last processed Tx descriptor */
+ u32CurrentTxDesc = (uint32_t)desc;
+ }
+
+ return (u32Count);
+}
+
+/**
+ * @brief Clean up process after a packet is sent, and get the time stamp while packet is sent
+ * @param[in] pu32Sec Second value while packet sent
+ * @param[in] pu32Nsec Nano second value while packet sent
+ * @return If a packet sent successfully
+ * @retval 0 No packet sent successfully, and the value in *pu32Sec and *pu32Nsec are meaningless
+ * @retval 1 A packet sent successfully, and the value in *pu32Sec and *pu32Nsec is the time stamp while packet sent
+ * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDone to
+ * release the resource use by transmit process
+ */
+uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec)
+{
+
+ EMAC_DESCRIPTOR_T *desc;
+ uint32_t status, reg;
+ uint32_t u32Count = 0UL;
+
+ reg = EMAC->INTSTS;
+ /* Clear Tx interrupt flags */
+ EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk);
+
+
+ if (reg & EMAC_INTSTS_TXBEIF_Msk)
+ {
+ /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+ while (1) {}
+ }
+ else
+ {
+ /* Process the descriptor.
+ Get our first descriptor to process */
+ desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc;
+
+ /* Descriptor ownership is still EMAC, so this packet haven't been send. */
+ if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC)
+ {
+ /* Get Tx status stored in descriptor */
+ status = desc->u32Status2 >> 16UL;
+
+ if (status & EMAC_TXFD_TXCP)
+ {
+ u32Count = 1UL;
+ *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */
+ *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */
+ }
+ else
+ {
+ /* Do nothing here on error. */
+ if (status & EMAC_TXFD_TXABT) {}
+
+ if (status & EMAC_TXFD_DEF) {}
+
+ if (status & EMAC_TXFD_PAU) {}
+
+ if (status & EMAC_TXFD_EXDEF) {}
+
+ if (status & EMAC_TXFD_NCS) {}
+
+ if (status & EMAC_TXFD_SQE) {}
+
+ if (status & EMAC_TXFD_LC) {}
+
+ if (status & EMAC_TXFD_TXHA) {}
+ }
+
+ /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+ desc->u32Data = desc->u32Backup1;
+ desc->u32Next = desc->u32Backup2;
+ /* go to next descriptor in link */
+ desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+
+ /* Save last processed Tx descriptor */
+ u32CurrentTxDesc = (uint32_t)desc;
+ }
+ }
+
+ return (u32Count);
+}
+
+/**
+ * @brief Enable IEEE1588 time stamp function and set current time
+ * @param[in] u32Sec Second value
+ * @param[in] u32Nsec Nano second value
+ * @return None
+ */
+void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec)
+{
+ double f;
+ uint32_t reg;
+ EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;
+ EMAC->UPDSEC = u32Sec; /* Assume current time is 0 sec + 0 nano sec */
+ EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+
+ /* PTP source clock is 160MHz (Real chip using PLL). Each tick is 6.25ns
+ Assume we want to set each tick to 100ns.
+ Increase register = (100 * 2^31) / (10^9) = 214.71 =~ 215 = 0xD7
+ Addend register = 2^32 * tick_freq / (160MHz), where tick_freq = (2^31 / 215) MHz
+ From above equation, addend register = 2^63 / (160M * 215) ~= 268121280 = 0xFFB34C0
+ So:
+ EMAC->TSIR = 0xD7;
+ EMAC->TSAR = 0x1E70C600; */
+ f = (100.0 * 2147483648.0) / (1000000000.0) + 0.5;
+ EMAC->TSINC = (reg = (uint32_t)f);
+ f = (double)9223372036854775808.0 / ((double)(CLK_GetHCLKFreq()) * (double)reg);
+ EMAC->TSADDEND = (uint32_t)f;
+ EMAC->TSCTL |= (EMAC_TSCTL_TSUPDATE_Msk | EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); /* Fine update */
+}
+
+/**
+ * @brief Disable IEEE1588 time stamp function
+ * @param None
+ * @return None
+ */
+void EMAC_DisableTS(void)
+{
+ EMAC->TSCTL = 0UL;
+}
+
+/**
+ * @brief Get current time stamp
+ * @param[out] pu32Sec Current second value
+ * @param[out] pu32Nsec Current nano second value
+ * @return None
+ */
+void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec)
+{
+ /* Must read TSLSR firstly. Hardware will preserve TSMSR value at the time TSLSR read. */
+ *pu32Nsec = EMAC_Subsec2Nsec(EMAC->TSSUBSEC);
+ *pu32Sec = EMAC->TSSEC;
+}
+
+/**
+ * @brief Set current time stamp
+ * @param[in] u32Sec Second value
+ * @param[in] u32Nsec Nano second value
+ * @return None
+ */
+void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec)
+{
+ /* Disable time stamp counter before update time value (clear EMAC_TSCTL_TSIEN_Msk) */
+ EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;
+ EMAC->UPDSEC = u32Sec;
+ EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+ EMAC->TSCTL |= (EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk);
+
+}
+
+/**
+ * @brief Enable alarm function and set alarm time
+ * @param[in] u32Sec Second value to trigger alarm
+ * @param[in] u32Nsec Nano second value to trigger alarm
+ * @return None
+ */
+void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec)
+{
+
+ EMAC->ALMSEC = u32Sec;
+ EMAC->ALMSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+ EMAC->TSCTL |= EMAC_TSCTL_TSALMEN_Msk;
+
+}
+
+/**
+ * @brief Disable alarm function
+ * @param None
+ * @return None
+ */
+void EMAC_DisableAlarm(void)
+{
+
+ EMAC->TSCTL &= ~EMAC_TSCTL_TSALMEN_Msk;
+
+}
+
+/**
+ * @brief Add a offset to current time
+ * @param[in] u32Neg Offset is negative value (u32Neg == 1) or positive value (u32Neg == 0).
+ * @param[in] u32Sec Second value to add to current time
+ * @param[in] u32Nsec Nano second value to add to current time
+ * @return None
+ */
+void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec)
+{
+ EMAC->UPDSEC = u32Sec;
+ EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+
+ if (u32Neg)
+ {
+ EMAC->UPDSUBSEC |= BIT31; /* Set bit 31 indicates this is a negative value */
+ }
+
+ EMAC->TSCTL |= EMAC_TSCTL_TSUPDATE_Msk;
+
+}
+
+/**
+ * @brief Check Ethernet link status
+ * @param None
+ * @return Current link status, could be one of following value.
+ * - \ref EMAC_LINK_DOWN
+ * - \ref EMAC_LINK_100F
+ * - \ref EMAC_LINK_100H
+ * - \ref EMAC_LINK_10F
+ * - \ref EMAC_LINK_10H
+ * @note This API should be called regularly to sync EMAC setting with real connection status
+ */
+uint32_t EMAC_CheckLinkStatus(void)
+{
+ uint32_t reg, ret = EMAC_LINK_DOWN;
+
+ /* Check link valid again */
+ if (EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID)
+ {
+ /* Check link partner capability */
+ reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ;
+
+ if (reg & PHY_ANLPA_DR100_TX_FULL)
+ {
+ EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
+ EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
+ ret = EMAC_LINK_100F;
+ }
+ else if (reg & PHY_ANLPA_DR100_TX_HALF)
+ {
+ EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
+ EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+ ret = EMAC_LINK_100H;
+ }
+ else if (reg & PHY_ANLPA_DR10_TX_FULL)
+ {
+ EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+ EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
+ ret = EMAC_LINK_10F;
+ }
+ else
+ {
+ EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+ EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+ ret = EMAC_LINK_10H;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Fill a MAC address to list and enable.
+ * @param A MAC address
+ * @return The CAM index
+ * @retval -1 Failed to fill the MAC address.
+ * @retval 0~(EMAC_CAMENTRY_NB-1) The index number of entry location.
+ */
+int32_t EMAC_FillCamEntry(uint8_t pu8MacAddr[])
+{
+ uint32_t *EMAC_CAMxM;
+ uint32_t *EMAC_CAMxL;
+ int32_t index;
+ uint8_t mac[6];
+
+ for (index = 0; index < EMAC_CAMENTRY_NB; index ++)
+ {
+ EMAC_CAMxM = (uint32_t *)((uint32_t)&EMAC->CAM0M + (index * 8));
+ EMAC_CAMxL = (uint32_t *)((uint32_t)&EMAC->CAM0L + (index * 8));
+
+ mac[0] = (*EMAC_CAMxM >> 24) & 0xff;
+ mac[1] = (*EMAC_CAMxM >> 16) & 0xff;
+ mac[2] = (*EMAC_CAMxM >> 8) & 0xff;
+ mac[3] = (*EMAC_CAMxM) & 0xff;
+ mac[4] = (*EMAC_CAMxL >> 24) & 0xff;
+ mac[5] = (*EMAC_CAMxL >> 16) & 0xff;
+
+ if (memcmp(mac, pu8MacAddr, sizeof(mac)) == 0)
+ {
+ goto exit_emac_fillcamentry;
+ }
+
+ if (*EMAC_CAMxM == 0 && *EMAC_CAMxL == 0)
+ {
+ break;
+ }
+ }
+
+ if (index < EMAC_CAMENTRY_NB)
+ {
+ EMAC_EnableCamEntry(index, pu8MacAddr);
+ goto exit_emac_fillcamentry;
+ }
+
+ return -1;
+
+exit_emac_fillcamentry:
+
+ return index;
+}
+
+/**
+ * @brief Send an Ethernet packet
+ * @param[in] u32Size Packet size (without 4 byte CRC).
+ * @return Packet transmit success or not
+ * @retval 0 Transmit failed due to descriptor unavailable.
+ * @retval 1 Triggered to transmit.
+ * @note Return 1 doesn't guarantee the packet will be sent and received successfully.
+ */
+uint32_t EMAC_SendPktWoCopy(uint32_t u32Size)
+{
+ EMAC_DESCRIPTOR_T *desc;
+ uint32_t status;
+ uint32_t ret = 0UL;
+ /* Get Tx frame descriptor & data pointer */
+ desc = (EMAC_DESCRIPTOR_T *)u32NextTxDesc;
+
+ status = desc->u32Status1;
+
+ /* Check descriptor ownership */
+ if ((status & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC)
+ {
+ /* Set Tx descriptor transmit byte count */
+ desc->u32Status2 = u32Size;
+
+ /* Change descriptor ownership to EMAC */
+ desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
+
+ /* Get next Tx descriptor */
+ u32NextTxDesc = (uint32_t)(desc->u32Next);
+
+ /* Trigger EMAC to send the packet */
+ EMAC_TRIGGER_TX();
+ ret = 1UL;
+ }
+
+ return (ret);
+}
+
+/**
+ * @brief Get avaiable TX buffer address
+ * @param None
+ * @return An avaiable TX buffer.
+ * @note This API should be called before EMAC_SendPkt_WoCopy calling. Caller will do data-copy.
+ */
+uint8_t *EMAC_ClaimFreeTXBuf(void)
+{
+ EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)u32NextTxDesc;
+
+ if (desc->u32Status1 & EMAC_DESC_OWN_EMAC)
+ {
+ return (NULL);
+ }
+ else
+ {
+ return (uint8_t *)desc->u32Data;
+ }
+}
+
+/**
+ * @brief Get data length of avaiable RX buffer.
+ * @param None
+ * @return An data length of avaiable RX buffer.
+ * @note This API should be called before EMAC_RecvPktDone_WoTrigger calling. Caller will do data-copy.
+ */
+uint32_t EMAC_GetAvailRXBufSize(uint8_t** ppuDataBuf)
+{
+ EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
+
+ if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) /* ownership=CPU */
+ {
+ uint32_t status = desc->u32Status1 >> 16;
+
+ /* It is good and no CRC error. */
+ if ((status & EMAC_RXFD_RXGD) && !(status & EMAC_RXFD_CRCE))
+ {
+ *ppuDataBuf = (uint8_t*)desc->u32Backup1;
+ return desc->u32Status1 & 0xFFFFUL;
+ }
+ else
+ {
+ // Drop it
+ EMAC_RecvPktDone();
+ }
+ }
+
+ return 0;
+}
+
+
+/**
+ * @brief Clean up process after a packet is received.
+ * @param None
+ * @return None
+ * @details Caller must call the function to release the resource.
+ * @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1
+ * @note This function is without doing EMAC_TRIGGER_RX.
+ */
+void EMAC_RecvPktDoneWoRxTrigger(void)
+{
+ EMAC_DESCRIPTOR_T *desc;
+ /* Get Rx Frame Descriptor */
+ desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
+
+ /* Restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+ desc->u32Data = desc->u32Backup1;
+ desc->u32Next = desc->u32Backup2;
+
+ /* Change ownership to DMA for next use */
+ desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
+
+ /* Get Next Frame Descriptor pointer to process */
+ desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+
+ /* Save last processed Rx descriptor */
+ u32CurrentRxDesc = (uint32_t)desc;
+}
+
+
+/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EMAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_epwm.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_epwm.c
new file mode 100644
index 00000000000..e082fa5dba8
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_epwm.c
@@ -0,0 +1,1699 @@
+/**************************************************************************//**
+ * @file epwm.c
+ * @version V3.00
+ * $Revision: 3 $
+ * @brief M480 series EPWM driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EPWM_Driver EPWM Driver
+ @{
+*/
+
+
+/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief Configure EPWM capture and get the nearest unit time.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32UnitTimeNsec The unit time of counter
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
+ * @return The nearest unit time in nano second.
+ * @details This function is used to Configure EPWM capture and get the nearest unit time.
+ */
+uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
+{
+ uint32_t u32Src;
+ uint32_t u32EPWMClockSrc;
+ uint32_t u32NearestUnitTimeNsec;
+ uint32_t u16Prescale = 1U, u16CNR = 0xFFFFU;
+
+ if(epwm == EPWM0)
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk;
+ }
+ else /* (epwm == EPWM1) */
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk;
+ }
+
+ if(u32Src == 0U)
+ {
+ /* clock source is from PLL clock */
+ u32EPWMClockSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ /* clock source is from PCLK */
+ SystemCoreClockUpdate();
+ if(epwm == EPWM0)
+ {
+ u32EPWMClockSrc = CLK_GetPCLK0Freq();
+ }
+ else /* (epwm == EPWM1) */
+ {
+ u32EPWMClockSrc = CLK_GetPCLK1Freq();
+ }
+ }
+
+ u32EPWMClockSrc /= 1000U;
+ for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++)
+ {
+ uint32_t u32Exit = 0U;
+ u32NearestUnitTimeNsec = (1000000U * u16Prescale) / u32EPWMClockSrc;
+ if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
+ {
+ if(u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */
+ {
+ u32Exit = 1U;
+ }
+ else
+ {
+ u32Exit = 0U;
+ }
+ if(!((1000000U * (u16Prescale + 1U) > (u32NearestUnitTimeNsec * u32EPWMClockSrc))))
+ {
+ u32Exit = 1U;
+ }
+ else
+ {
+ u32Exit = 0U;
+ }
+ }
+ else
+ {
+ u32Exit = 1U;
+ }
+ if (u32Exit == 1U)
+ {
+ break;
+ }
+ else {}
+ }
+
+ /* convert to real register value */
+ /* every two channels share a prescaler */
+ u16Prescale -= 1U;
+ EPWM_SET_PRESCALER(epwm, u32ChannelNum, u16Prescale);
+
+ /* set EPWM to down count type(edge aligned) */
+ (epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1U))) | (1UL << (u32ChannelNum << 1U));
+ /* set EPWM to auto-reload mode */
+ (epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
+ EPWM_SET_CNR(epwm, u32ChannelNum, u16CNR);
+
+ return (u32NearestUnitTimeNsec);
+}
+
+/**
+ * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
+ * existing frequency of other channel.
+ * @note This function is used for initial stage.
+ * To change duty cycle later, it should get the configured period value and calculate the new comparator value.
+ */
+uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+ uint32_t u32Src;
+ uint32_t u32EPWMClockSrc;
+ uint32_t i;
+ uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
+
+ if(epwm == EPWM0)
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk;
+ }
+ else /* (epwm == EPWM1) */
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk;
+ }
+
+ if(u32Src == 0U)
+ {
+ /* clock source is from PLL clock */
+ u32EPWMClockSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ /* clock source is from PCLK */
+ SystemCoreClockUpdate();
+ if(epwm == EPWM0)
+ {
+ u32EPWMClockSrc = CLK_GetPCLK0Freq();
+ }
+ else /* (epwm == EPWM1) */
+ {
+ u32EPWMClockSrc = CLK_GetPCLK1Freq();
+ }
+ }
+
+ for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */
+ {
+ i = (u32EPWMClockSrc / u32Frequency) / u32Prescale;
+ /* If target value is larger than CNR, need to use a larger prescaler */
+ if(i < (0x10000U))
+ {
+ u32CNR = i;
+ break;
+ }
+ }
+ /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */
+ i = u32EPWMClockSrc / (u32Prescale * u32CNR);
+
+ /* convert to real register value */
+ /* every two channels share a prescaler */
+ u32Prescale -= 1U;
+ EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale);
+ /* set EPWM to up counter type(edge aligned) and auto-reload mode */
+ (epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1U))|((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum)));
+
+ u32CNR -= 1U;
+ EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
+ EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 100U);
+
+ (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1U))) | \
+ ((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos));
+ (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~((EPWM_WGCTL1_CMPDCTL0_Msk | EPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1U))) | \
+ ((uint32_t)EPWM_OUTPUT_LOW << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL1_CMPUCTL0_Pos));
+
+ return(i);
+}
+
+/**
+ * @brief Start EPWM module
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to start EPWM module.
+ */
+void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->CNTEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Stop EPWM module
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop EPWM module.
+ */
+void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1UL << i))
+ {
+ (epwm)->PERIOD[i] = 0U;
+ }
+ }
+}
+
+/**
+ * @brief Stop EPWM generation immediately by clear channel enable bit
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop EPWM generation immediately by clear channel enable bit.
+ */
+void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->CNTEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enable selected channel to trigger ADC
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
+ * - \ref EPWM_TRG_ADC_EVEN_ZERO
+ * - \ref EPWM_TRG_ADC_EVEN_PERIOD
+ * - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD
+ * - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP
+ * - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN
+ * - \ref EPWM_TRG_ADC_ODD_ZERO
+ * - \ref EPWM_TRG_ADC_ODD_PERIOD
+ * - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD
+ * - \ref EPWM_TRG_ADC_ODD_COMPARE_UP
+ * - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN
+ * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP
+ * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN
+ * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP
+ * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN
+ * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP
+ * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN
+ * @return None
+ * @details This function is used to enable selected channel to trigger ADC.
+ */
+void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ if(u32ChannelNum < 4U)
+ {
+ (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3U));
+ (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3));
+ }
+ else
+ {
+ (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) << 3U));
+ (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) << 3U));
+ }
+}
+
+/**
+ * @brief Disable selected channel to trigger ADC
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger ADC.
+ */
+void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ if(u32ChannelNum < 4U)
+ {
+ (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3U));
+ }
+ else
+ {
+ (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) << 3U));
+ }
+}
+
+/**
+ * @brief Enable and configure trigger ADC prescale
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @param[in] u32Prescale ADC prescale. Valid values are between 0 to 0xF.
+ * @param[in] u32PrescaleCnt ADC prescale counter. Valid values are between 0 to 0xF.
+ * @retval 0 Success.
+ * @retval -1 Failed.
+ * @details This function is used to enable and configure trigger ADC prescale.
+ * @note User can configure only when ADC trigger prescale is disabled.
+ * @note ADC prescale counter must less than ADC prescale.
+ */
+int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt)
+{
+ /* User can write only when PSCENn(n = 0 ~ 5) is 0 */
+ if ((epwm)->EADCPSCCTL & (1UL << u32ChannelNum))
+ return (-1);
+
+ if(u32ChannelNum < 4UL)
+ {
+ (epwm)->EADCPSC0 = ((epwm)->EADCPSC0 & ~((EPWM_EADCPSC0_EADCPSC0_Msk) << (u32ChannelNum << 3))) | \
+ (u32Prescale << (u32ChannelNum << 3));
+ (epwm)->EADCPSCNT0 = ((epwm)->EADCPSCNT0 & ~((EPWM_EADCPSCNT0_PSCNT0_Msk) << (u32ChannelNum << 3))) | \
+ (u32PrescaleCnt << (u32ChannelNum << 3));
+ }
+ else
+ {
+ (epwm)->EADCPSC1 = ((epwm)->EADCPSC1 & ~((EPWM_EADCPSC1_EADCPSC4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \
+ (u32Prescale << ((u32ChannelNum - 4UL) << 3));
+ (epwm)->EADCPSCNT1 = ((epwm)->EADCPSCNT1 & ~((EPWM_EADCPSCNT1_PSCNT4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \
+ (u32PrescaleCnt << ((u32ChannelNum - 4UL) << 3));
+ }
+
+ (epwm)->EADCPSCCTL |= EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum;
+
+ return 0;
+}
+
+/**
+ * @brief Disable Trigger ADC prescale function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable trigger ADC prescale.
+ */
+void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->EADCPSCCTL &= ~(EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear selected channel trigger ADC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger ADC flag.
+ */
+void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get selected channel trigger ADC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 The specified channel trigger ADC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger ADC to start of conversion flag is set
+ * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel.
+ */
+uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum))?1UL:0UL);
+}
+
+/**
+ * @brief Enable selected channel to trigger DAC
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions:
+ * - \ref EPWM_TRIGGER_DAC_ZERO
+ * - \ref EPWM_TRIGGER_DAC_PERIOD
+ * - \ref EPWM_TRIGGER_DAC_COMPARE_UP
+ * - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN
+ * @return None
+ * @details This function is used to enable selected channel to trigger DAC.
+ */
+void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum);
+}
+
+/**
+ * @brief Disable selected channel to trigger DAC
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger DAC.
+ */
+void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | \
+ EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear selected channel trigger DAC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. This parameter is not used
+ * @param[in] u32Condition The condition to trigger DAC. This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger DAC flag.
+ */
+void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk;
+}
+
+/**
+ * @brief Get selected channel trigger DAC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. This parameter is not used
+ * @retval 0 The specified channel trigger DAC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger DAC to start of conversion flag is set
+ * @details This function is used to get selected channel trigger DAC flag.
+ */
+uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk)?1UL:0UL);
+}
+
+/**
+ * @brief This function enable fault brake of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
+ * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32BrakeSource Fault brake source, could be one of following source
+ * - \ref EPWM_FB_EDGE_ADCRM
+ * - \ref EPWM_FB_EDGE_ACMP0
+ * - \ref EPWM_FB_EDGE_ACMP1
+ * - \ref EPWM_FB_EDGE_BKP0
+ * - \ref EPWM_FB_EDGE_BKP1
+ * - \ref EPWM_FB_EDGE_SYS_CSS
+ * - \ref EPWM_FB_EDGE_SYS_BOD
+ * - \ref EPWM_FB_EDGE_SYS_RAM
+ * - \ref EPWM_FB_EDGE_SYS_COR
+ * - \ref EPWM_FB_LEVEL_ADCRM
+ * - \ref EPWM_FB_LEVEL_ACMP0
+ * - \ref EPWM_FB_LEVEL_ACMP1
+ * - \ref EPWM_FB_LEVEL_BKP0
+ * - \ref EPWM_FB_LEVEL_BKP1
+ * - \ref EPWM_FB_LEVEL_SYS_CSS
+ * - \ref EPWM_FB_LEVEL_SYS_BOD
+ * - \ref EPWM_FB_LEVEL_SYS_RAM
+ * - \ref EPWM_FB_LEVEL_SYS_COR
+ * @return None
+ * @details This function is used to enable fault brake of selected channel(s).
+ * The write-protection function should be disabled before using this function.
+ */
+void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
+{
+ uint32_t i;
+
+ for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1UL << i))
+ {
+ if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \
+ (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \
+ (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \
+ (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR))
+ {
+ (epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk));
+ (epwm)->FAILBRK |= (u32BrakeSource & 0xFU);
+ }
+ else
+ {
+ (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource;
+ }
+ }
+
+ if(u32LevelMask & (1UL << i))
+ {
+ if((i & 0x1U) == 0U)
+ {
+ /* set brake action as high level for even channel */
+ (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;
+ (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);
+ }
+ else
+ {
+ /* set brake action as high level for odd channel */
+ (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;
+ (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos);
+ }
+ }
+ else
+ {
+ if((i & 0x1U) == 0U)
+ {
+ /* set brake action as low level for even channel */
+ (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;
+ (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);
+ }
+ else
+ {
+ /* set brake action as low level for odd channel */
+ (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;
+ (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos);
+ }
+ }
+ }
+}
+
+/**
+ * @brief Enable capture of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable capture of selected channel(s).
+ */
+void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->CAPINEN |= u32ChannelMask;
+ (epwm)->CAPCTL |= u32ChannelMask;
+}
+
+/**
+ * @brief Disable capture of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable capture of selected channel(s).
+ */
+void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->CAPINEN &= ~u32ChannelMask;
+ (epwm)->CAPCTL &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables EPWM output generation of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ * @details This function is used to enable EPWM output generation of selected channel(s).
+ */
+void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->POEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Disables EPWM output generation of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ * @details This function is used to disable EPWM output generation of selected channel(s).
+ */
+void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->POEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables PDMA transfer of selected channel for EPWM capture
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number.
+ * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE.
+ * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either
+ * - \ref EPWM_CAPTURE_PDMA_RISING_LATCH
+ * - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH
+ * - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture.
+ * @note This function can only selects even or odd channel of pairs to do PDMA transfer.
+ */
+void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
+{
+ uint32_t u32IsOddCh;
+ u32IsOddCh = u32ChannelNum & 0x1U;
+ (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1U) << 3U))) | \
+ (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \
+ u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1U) << 3U));
+}
+
+/**
+ * @brief Disables PDMA transfer of selected channel for EPWM capture
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number.
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture.
+ */
+void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1U) << 3U));
+}
+
+/**
+ * @brief Enable Dead zone of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone.
+ * @return None
+ * @details This function is used to enable Dead zone of selected channel.
+ * The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration)
+{
+ /* every two channels share the same setting */
+ (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTCNT_Msk;
+ (epwm)->DTCTL[(u32ChannelNum) >> 1U] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration;
+}
+
+/**
+ * @brief Disable Dead zone of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable Dead zone of selected channel.
+ * The write-protection function should be disabled before using this function.
+ */
+void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ /* every two channels shares the same setting */
+ (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTEN_Msk;
+}
+
+/**
+ * @brief Enable capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ * - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable capture interrupt of selected channel.
+ */
+void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (epwm)->CAPIEN |= (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Disable capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ * - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to disable capture interrupt of selected channel.
+ */
+void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Clear capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ * - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to clear capture interrupt of selected channel.
+ */
+void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (epwm)->CAPIF = (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Get capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 No capture interrupt
+ * @retval 1 Rising edge latch interrupt
+ * @retval 2 Falling edge latch interrupt
+ * @retval 3 Rising and falling latch interrupt
+ * @details This function is used to get capture interrupt of selected channel.
+ */
+uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \
+ (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL));
+}
+/**
+ * @brief Enable duty interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntDutyType Duty interrupt type, could be either
+ * - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
+ * - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP
+ * @return None
+ * @details This function is used to enable duty interrupt of selected channel.
+ */
+void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
+{
+ (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
+}
+
+/**
+ * @brief Disable duty interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable duty interrupt of selected channel.
+ */
+void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTEN0 &= ~((uint32_t)(EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear duty interrupt flag of selected channel.
+ */
+void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
+}
+
+/**
+ * @brief Get duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Duty interrupt did not occur
+ * @retval 1 Duty interrupt occurred
+ * @details This function is used to get duty interrupt flag of selected channel.
+ */
+uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief This function enable fault brake interrupt
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ * - \ref EPWM_FB_EDGE
+ * - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to enable fault brake interrupt.
+ * The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+ (epwm)->INTEN1 |= (0x7UL << u32BrakeSource);
+}
+
+/**
+ * @brief This function disable fault brake interrupt
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ * - \ref EPWM_FB_EDGE
+ * - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to disable fault brake interrupt.
+ * The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+ (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource);
+}
+
+/**
+ * @brief This function clear fault brake interrupt of selected source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ * - \ref EPWM_FB_EDGE
+ * - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to clear fault brake interrupt of selected source.
+ * The write-protection function should be disabled before using this function.
+ */
+void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+ (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource);
+}
+
+/**
+ * @brief This function get fault brake interrupt flag of selected source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source, could be either
+ * - \ref EPWM_FB_EDGE
+ * - \ref EPWM_FB_LEVEL
+ * @return Fault brake interrupt flag of specified source
+ * @retval 0 Fault brake interrupt did not occurred
+ * @retval 1 Fault brake interrupt occurred
+ * @details This function is used to get fault brake interrupt flag of selected source.
+ */
+uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+ return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
+ * @return None
+ * @details This function is used to enable period interrupt of selected channel.
+ */
+void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
+{
+ (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Disable period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable period interrupt of selected channel.
+ */
+void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear period interrupt of selected channel.
+ */
+void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTSTS0 = ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Get period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occur
+ * @retval 1 Period interrupt occurred
+ * @details This function is used to get period interrupt of selected channel.
+ */
+uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable zero interrupt of selected channel.
+ */
+void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Disable zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable zero interrupt of selected channel.
+ */
+void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear zero interrupt of selected channel.
+ */
+void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTSTS0 = ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Get zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Zero interrupt flag of specified channel
+ * @retval 0 Zero interrupt did not occur
+ * @retval 1 Zero interrupt occurred
+ * @details This function is used to get zero interrupt of selected channel.
+ */
+uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable interrupt flag accumulator of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535.
+ * @param[in] u32IntAccSrc Interrupt flag accumulator source selection.
+ * - \ref EPWM_IFA_ZERO_POINT
+ * - \ref EPWM_IFA_PERIOD_POINT
+ * - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT
+ * - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator of selected channel.
+ */
+void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
+{
+ (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \
+ (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt) );
+}
+
+/**
+ * @brief Disable interrupt flag accumulator of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to Disable interrupt flag accumulator of selected channel.
+ */
+void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk));
+}
+
+/**
+ * @brief Enable interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->AINTEN |= (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->AINTEN &= ~(1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Clear interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->AINTSTS = (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Get interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 Accumulator interrupt did not occur
+ * @retval 1 Accumulator interrupt occurred
+ * @details This function is used to Get interrupt flag accumulator interrupt of selected channel.
+ */
+uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable accumulator PDMA of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel.
+ */
+void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->APDMACTL |= (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable accumulator PDMA of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel.
+ */
+void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Enable interrupt flag accumulator stop mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator stop mode of selected channel.
+ */
+void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->IFA[u32ChannelNum] |= EPWM_IFA0_STPMOD_Msk;
+}
+
+/**
+ * @brief Disable interrupt flag accumulator stop mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable interrupt flag accumulator stop mode of selected channel.
+ */
+void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->IFA[u32ChannelNum] &= ~EPWM_IFA0_STPMOD_Msk;
+}
+
+/**
+ * @brief Clear free trigger duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear free trigger duty interrupt flag of selected channel.
+ */
+void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U));
+}
+
+/**
+ * @brief Get free trigger duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Free trigger duty interrupt did not occur
+ * @retval 1 Free trigger duty interrupt occurred
+ * @details This function is used to get free trigger duty interrupt flag of selected channel.
+ */
+uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable load mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode EPWM counter loading mode.
+ * - \ref EPWM_LOAD_MODE_IMMEDIATE
+ * - \ref EPWM_LOAD_MODE_WINDOW
+ * - \ref EPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to enable load mode of selected channel.
+ */
+void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+ (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Disable load mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode EPWM counter loading mode.
+ * - \ref EPWM_LOAD_MODE_IMMEDIATE
+ * - \ref EPWM_LOAD_MODE_WINDOW
+ * - \ref EPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to disable load mode of selected channel.
+ */
+void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+ (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Configure synchronization phase of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32SyncSrc EPWM synchronize source selection.
+ * - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC
+ * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO
+ * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR
+ * - \ref EPWM_SYNC_OUT_DISABLE
+ * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment after synchronizing.
+ * - \ref EPWM_PHS_DIR_DECREMENT
+ * - \ref EPWM_PHS_DIR_INCREMENT
+ * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535.
+ * @return None
+ * @details This function is used to configure synchronization phase of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
+{
+ /* every two channels shares the same setting */
+ u32ChannelNum >>= 1U;
+ (epwm)->SYNC = (((epwm)->SYNC & ~(((3UL << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)) | ((1UL << EPWM_SYNC_PHSDIR0_Pos) << u32ChannelNum))) | \
+ (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | ((u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)));
+ (epwm)->PHS[(u32ChannelNum)] = u32StartPhase;
+}
+
+
+/**
+ * @brief Enable SYNC phase of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1UL << i))
+ {
+ (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));
+ }
+ }
+}
+
+/**
+ * @brief Disable SYNC phase of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1UL << i))
+ {
+ (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));
+ }
+ }
+}
+
+/**
+ * @brief Enable EPWM SYNC_IN noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector.
+ * The valid value is 0~7.
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ * - \ref EPWM_NF_CLK_DIV_1
+ * - \ref EPWM_NF_CLK_DIV_2
+ * - \ref EPWM_NF_CLK_DIV_4
+ * - \ref EPWM_NF_CLK_DIV_8
+ * - \ref EPWM_NF_CLK_DIV_16
+ * - \ref EPWM_NF_CLK_DIV_32
+ * - \ref EPWM_NF_CLK_DIV_64
+ * - \ref EPWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable EPWM SYNC_IN noise filter function.
+ */
+void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+ (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \
+ ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk);
+}
+
+/**
+ * @brief Disable EPWM SYNC_IN noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to Disable EPWM SYNC_IN noise filter function.
+ */
+void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm)
+{
+ (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk;
+}
+
+/**
+ * @brief Enable EPWM SYNC input pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to enable EPWM SYNC input pin inverse function.
+ */
+void EPWM_EnableSyncPinInverse(EPWM_T *epwm)
+{
+ (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk;
+}
+
+/**
+ * @brief Disable EPWM SYNC input pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to Disable EPWM SYNC input pin inverse function.
+ */
+void EPWM_DisableSyncPinInverse(EPWM_T *epwm)
+{
+ (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk);
+}
+
+/**
+ * @brief Set EPWM clock source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32ClkSrcSel EPWM external clock source.
+ * - \ref EPWM_CLKSRC_EPWM_CLK
+ * - \ref EPWM_CLKSRC_TIMER0
+ * - \ref EPWM_CLKSRC_TIMER1
+ * - \ref EPWM_CLKSRC_TIMER2
+ * - \ref EPWM_CLKSRC_TIMER3
+ * @return None
+ * @details This function is used to set EPWM clock source.
+ * @note Every two channels share the same setting.
+ * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1.
+ */
+void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
+{
+ (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1U) << 3U))) | \
+ (u32ClkSrcSel << ((u32ChannelNum >> 1U) << 3U));
+}
+
+/**
+ * @brief Enable EPWM brake noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ * - \ref EPWM_NF_CLK_DIV_1
+ * - \ref EPWM_NF_CLK_DIV_2
+ * - \ref EPWM_NF_CLK_DIV_4
+ * - \ref EPWM_NF_CLK_DIV_8
+ * - \ref EPWM_NF_CLK_DIV_16
+ * - \ref EPWM_NF_CLK_DIV_32
+ * - \ref EPWM_NF_CLK_DIV_64
+ * - \ref EPWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable EPWM brake noise filter function.
+ */
+void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+ (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3U))) | \
+ (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3U));
+}
+
+/**
+ * @brief Disable EPWM brake noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable EPWM brake noise filter function.
+ */
+void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+ (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3U));
+}
+
+/**
+ * @brief Enable EPWM brake pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to enable EPWM brake pin inverse function.
+ */
+void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+ (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3U));
+}
+
+/**
+ * @brief Disable EPWM brake pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable EPWM brake pin inverse function.
+ */
+void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+ (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Set EPWM brake pin source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE.
+ * @return None
+ * @details This function is used to set EPWM brake pin source.
+ */
+void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
+{
+ (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3U))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3U)));
+}
+
+/**
+ * @brief Set EPWM leading edge blanking function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32TrigSrcSel Leading edge blanking source selection.
+ * - \ref EPWM_LEBCTL_SRCEN0
+ * - \ref EPWM_LEBCTL_SRCEN2
+ * - \ref EPWM_LEBCTL_SRCEN4
+ * - \ref EPWM_LEBCTL_SRCEN0_2
+ * - \ref EPWM_LEBCTL_SRCEN0_4
+ * - \ref EPWM_LEBCTL_SRCEN2_4
+ * - \ref EPWM_LEBCTL_SRCEN0_2_4
+ * @param[in] u32TrigType Leading edge blanking trigger type.
+ * - \ref EPWM_LEBCTL_TRGTYPE_RISING
+ * - \ref EPWM_LEBCTL_TRGTYPE_FALLING
+ * - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING
+ * @param[in] u32BlankingCnt Leading Edge Blanking Counter. Valid values are between 1~512.
+ This counter value decides leading edge blanking window size, and this counter clock base is ECLK.
+ * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE).
+ * - \ref FALSE
+ * - \ref TRUE
+ * @return None
+ * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition.
+ * @note EPWM leading edge blanking function is only used for brake source from ACMP.
+ */
+void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable)
+{
+ (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable);
+ /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */
+ (epwm)->LEBCNT = (u32BlankingCnt) - 1U;
+}
+
+/**
+ * @brief Get the time-base counter reached its maximum value flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Count to max interrupt flag of specified channel
+ * @retval 0 Count to max interrupt did not occur
+ * @retval 1 Count to max interrupt occurred
+ * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
+ */
+uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the time-base counter reached its maximum value flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
+ */
+void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Enable fault detect of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @param[in] u32AfterPrescaler Fault Detect Clock Source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
+ * @param[in] u32ClkSel Fault Detect Clock Select.
+ * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_1
+ * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_2
+ * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_4
+ * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_8
+ * @return None
+ * @details This function is used to enable fault detect of selected channel.
+ */
+void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel)
+{
+ (epwm)->FDEN = ((epwm)->FDEN & ~(EPWM_FDEN_FDCKS0_Msk << (u32ChannelNum))) | \
+ ((EPWM_FDEN_FDEN0_Msk | ((u32AfterPrescaler) << EPWM_FDEN_FDCKS0_Pos)) << (u32ChannelNum));
+ (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & ~EPWM_FDCTL0_FDCKSEL_Msk) | (u32ClkSel);
+}
+
+/**
+ * @brief Disable fault detect of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to disable fault detect of selected channel.
+ */
+void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->FDEN &= ~(EPWM_FDEN_FDEN0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Enable fault detect output of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to enable fault detect output of selected channel.
+ */
+void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->FDEN &= ~(EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable fault detect output of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to disable fault detect output of selected channel.
+ */
+void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->FDEN |= (EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Enable fault detect deglitch function of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @param[in] u32DeglitchSmpCycle Deglitch Sampling Cycle. Valid values are between 0~7.
+ * @return None
+ * @details This function is used to enable fault detect deglitch function of selected channel.
+ */
+void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle)
+{
+ (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_DGSMPCYC_Msk)) | \
+ (EPWM_FDCTL0_FDDGEN_Msk | ((u32DeglitchSmpCycle) << EPWM_FDCTL0_DGSMPCYC_Pos));
+}
+
+/**
+ * @brief Disable fault detect deglitch function of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to disable fault detect deglitch function of selected channel.
+ */
+void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDDGEN_Msk;
+}
+
+/**
+ * @brief Enable fault detect mask function of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @param[in] u32MaskCnt Transition mask counter. Valid values are between 0~0x7F.
+ * @return None
+ * @details This function is used to enable fault detect mask function of selected channel.
+ */
+void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt)
+{
+ (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_TRMSKCNT_Msk)) | (EPWM_FDCTL0_FDMSKEN_Msk | (u32MaskCnt));
+}
+
+/**
+ * @brief Disable fault detect mask function of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to disable fault detect mask function of selected channel.
+ */
+void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDMSKEN_Msk;
+}
+
+/**
+ * @brief Enable fault detect interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to enable fault detect interrupt of selected channel.
+ */
+void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->FDIEN |= (EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable fault detect interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to disable fault detect interrupt of selected channel.
+ */
+void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->FDIEN &= ~(EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Clear fault detect interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to clear fault detect interrupt of selected channel.
+ */
+void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->FDSTS = (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Get fault detect interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @retval 0 Fault detect interrupt did not occur.
+ * @retval 1 Fault detect interrupt occurred.
+ * @details This function is used to Get fault detect interrupt of selected channel.
+ */
+uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->FDSTS & (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EPWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_fmc.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_fmc.c
new file mode 100644
index 00000000000..d3bbd345dc3
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_fmc.c
@@ -0,0 +1,1041 @@
+/**************************************************************************//**
+ * @file fmc.c
+ * @version V1.00
+ * @brief M480 series FMC driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+ @{
+*/
+
+
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Disable FMC ISP function.
+ * @return None
+ */
+void FMC_Close(void)
+{
+ FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
+}
+
+/**
+ * @brief Config XOM Region
+ * @param[in] u32XomNum The XOM number(0~3)
+ * @param[in] u32XomBase The XOM region base address.
+ * @param[in] u8XomPage The XOM page number of region size.
+ *
+ * @retval 0 Success
+ * @retval 1 XOM is has already actived.
+ * @retval -1 Program failed.
+ * @retval -2 Invalid XOM number.
+ *
+ * @details Program XOM base address and XOM size(page)
+ */
+int32_t FMC_ConfigXOM(uint32_t u32XomNum, uint32_t u32XomBase, uint8_t u8XomPage)
+{
+ int32_t ret = 0;
+
+ if(u32XomNum >= 4UL)
+ {
+ ret = -2;
+ }
+
+ if(ret == 0)
+ {
+ ret = FMC_GetXOMState(u32XomNum);
+ }
+
+ if(ret == 0)
+ {
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u);
+ FMC->ISPDAT = u32XomBase;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
+
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+ {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+
+ if(ret == 0)
+ {
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x04u);
+ FMC->ISPDAT = u8XomPage;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
+
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+ {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+
+ if(ret == 0)
+ {
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x08u);
+ FMC->ISPDAT = 0u;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
+
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+ {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 4096 bytes.
+ * @param[in] u32PageAddr Address of the flash page to be erased.
+ * It must be a 4096 bytes aligned address.
+ * @return ISP page erase success or not.
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ */
+int32_t FMC_Erase(uint32_t u32PageAddr)
+{
+ int32_t ret = 0;
+
+ if (u32PageAddr == FMC_SPROM_BASE)
+ {
+ ret = FMC_Erase_SPROM();
+ }
+
+ if (ret == 0)
+ {
+ FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+ FMC->ISPADDR = u32PageAddr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+ {
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+ return ret;
+}
+
+
+/**
+ * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase SPROM. The page size is 4096 bytes.
+ * @return SPROM page erase success or not.
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ */
+int32_t FMC_Erase_SPROM(void)
+{
+ int32_t ret = 0;
+
+ FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+ FMC->ISPADDR = FMC_SPROM_BASE;
+ FMC->ISPDAT = 0x0055AA03UL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+ {
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+ ret = -1;
+ }
+ return ret;
+}
+
+/**
+ * @brief Execute FMC_ISPCMD_BLOCK_ERASE command to erase a flash block. The block size is 4 pages.
+ * @param[in] u32BlockAddr Address of the flash block to be erased.
+ * It must be a 4 pages aligned address.
+ * @return ISP page erase success or not.
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ */
+int32_t FMC_Erase_Block(uint32_t u32BlockAddr)
+{
+ int32_t ret = 0;
+
+ FMC->ISPCMD = FMC_ISPCMD_BLOCK_ERASE;
+ FMC->ISPADDR = u32BlockAddr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+ {
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+ ret = -1;
+ }
+ return ret;
+}
+
+/**
+ * @brief Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block.
+ * @param[in] u32BankAddr Base address of the flash bank to be erased.
+ * @return ISP page erase success or not.
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ */
+int32_t FMC_Erase_Bank(uint32_t u32BankAddr)
+{
+ int32_t ret = 0;
+
+ FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE;
+ FMC->ISPADDR = u32BankAddr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+ {
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+ ret = -1;
+ }
+ return ret;
+}
+
+/**
+ * @brief Execute Erase XOM Region
+ *
+ * @param[in] u32XomNum The XOMRn(n=0~3)
+ *
+ * @return XOM erase success or not.
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ * @retval -2 Invalid XOM number.
+ *
+ * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM.
+ */
+int32_t FMC_EraseXOM(uint32_t u32XomNum)
+{
+ uint32_t u32Addr;
+ int32_t i32Active, err = 0;
+
+ if(u32XomNum >= 4UL)
+ {
+ err = -2;
+ }
+
+ if(err == 0)
+ {
+ i32Active = FMC_GetXOMState(u32XomNum);
+
+ if(i32Active)
+ {
+ switch(u32XomNum)
+ {
+ case 0u:
+ u32Addr = (FMC->XOMR0STS & 0xFFFFFF00u) >> 8u;
+ break;
+ case 1u:
+ u32Addr = (FMC->XOMR1STS & 0xFFFFFF00u) >> 8u;
+ break;
+ case 2u:
+ u32Addr = (FMC->XOMR2STS & 0xFFFFFF00u) >> 8u;
+ break;
+ case 3u:
+ u32Addr = (FMC->XOMR3STS & 0xFFFFFF00u) >> 8u;
+ break;
+ default:
+ break;
+ }
+ FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+ FMC->ISPADDR = u32Addr;
+ FMC->ISPDAT = 0x55aa03u;
+ FMC->ISPTRG = 0x1u;
+#if ISBEN
+ __ISB();
+#endif
+ while(FMC->ISPTRG) {}
+
+ /* Check ISPFF flag to know whether erase OK or fail. */
+ if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+ {
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+ err = -1;
+ }
+ }
+ else
+ {
+ err = -1;
+ }
+ }
+ return err;
+}
+
+/**
+ * @brief Check the XOM is actived or not.
+ *
+ * @param[in] u32XomNum The xom number(0~3).
+ *
+ * @retval 1 XOM is actived.
+ * @retval 0 XOM is not actived.
+ * @retval -2 Invalid XOM number.
+ *
+ * @details To get specify XOMRn(n=0~3) active status
+ */
+int32_t FMC_GetXOMState(uint32_t u32XomNum)
+{
+ uint32_t u32act;
+ int32_t ret = 0;
+
+ if(u32XomNum >= 4UL)
+ {
+ ret = -2;
+ }
+
+ if(ret >= 0)
+ {
+ u32act = (((FMC->XOMSTS) & 0xful) & (1ul << u32XomNum)) >> u32XomNum;
+ ret = (int32_t)u32act;
+ }
+ return ret;
+}
+
+/**
+ * @brief Get the current boot source.
+ * @return The current boot source.
+ * @retval 0 Is boot from APROM.
+ * @retval 1 Is boot from LDROM.
+ * @retval 2 Is boot from Boot Loader.
+ */
+int32_t FMC_GetBootSource (void)
+{
+ if (FMC->ISPCTL & FMC_ISPCTL_BL_Msk)
+ {
+ return 2;
+ }
+ if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk)
+ {
+ return 1;
+ }
+ return 0;
+}
+
+
+/**
+ * @brief Enable FMC ISP function
+ * @return None
+ */
+void FMC_Open(void)
+{
+ FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk;
+}
+
+
+/**
+ * @brief Execute FMC_ISPCMD_READ command to read a word from flash.
+ * @param[in] u32Addr Address of the flash location to be read.
+ * It must be a word aligned address.
+ * @return The word data read from specified flash address.
+ */
+uint32_t FMC_Read(uint32_t u32Addr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ;
+ FMC->ISPADDR = u32Addr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ return FMC->ISPDAT;
+}
+
+
+/**
+ * @brief Execute FMC_ISPCMD_READ_64 command to read a double-word from flash.
+ * @param[in] u32addr Address of the flash location to be read.
+ * It must be a double-word aligned address.
+ * @param[out] u32data0 Place holder of word 0 read from flash address u32addr.
+ * @param[out] u32data1 Place holder of word 0 read from flash address u32addr+4.
+ * @return 0 Success
+ * @return -1 Failed
+ */
+int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1)
+{
+ int32_t ret = 0;
+
+ FMC->ISPCMD = FMC_ISPCMD_READ_64;
+ FMC->ISPADDR = u32addr;
+ FMC->ISPDAT = 0x0UL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+ {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ else
+ {
+ *u32data0 = FMC->MPDAT0;
+ *u32data1 = FMC->MPDAT1;
+ }
+ return ret;
+}
+
+
+/**
+ * @brief Get the base address of Data Flash if enabled.
+ * @retval The base address of Data Flash
+ */
+uint32_t FMC_ReadDataFlashBaseAddr(void)
+{
+ return FMC->DFBA;
+}
+
+/**
+ * @brief Set boot source from LDROM or APROM after next software reset
+ * @param[in] i32BootSrc
+ * 1: Boot from LDROM
+ * 0: Boot from APROM
+ * @return None
+ * @details This function is used to switch APROM boot or LDROM boot. User need to call
+ * FMC_SetBootSource to select boot source first, then use CPU reset or
+ * System Reset Request to reset system.
+ */
+void FMC_SetBootSource(int32_t i32BootSrc)
+{
+ if(i32BootSrc)
+ {
+ FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */
+ }
+ else
+ {
+ FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */
+ }
+}
+
+/**
+ * @brief Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash.
+ * @param[in] u32Addr Address of the flash location to be programmed.
+ * It must be a word aligned address.
+ * @param[in] u32Data The word data to be programmed.
+ * @return None
+ */
+void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
+{
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = u32Addr;
+ FMC->ISPDAT = u32Data;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+}
+
+/**
+ * @brief Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash.
+ * @param[in] u32addr Address of the flash location to be programmed.
+ * It must be a double-word aligned address.
+ * @param[in] u32data0 The word data to be programmed to flash address u32addr.
+ * @param[in] u32data1 The word data to be programmed to flash address u32addr+4.
+ * @return 0 Success
+ * @return -1 Failed
+ */
+int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1)
+{
+ int32_t ret = 0;
+
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64;
+ FMC->ISPADDR = u32addr;
+ FMC->MPDAT0 = u32data0;
+ FMC->MPDAT1 = u32data1;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+ {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ return ret;
+}
+
+
+/**
+ * @brief Program Multi-Word data into specified address of flash.
+ * @param[in] u32Addr Start flash address in APROM where the data chunk to be programmed into.
+ * This address must be 8-bytes aligned to flash address.
+ * @param[in] pu32Buf Buffer that carry the data chunk.
+ * @param[in] u32Len Length of the data chunk in bytes.
+ * @retval >=0 Number of data bytes were programmed.
+ * @return -1 Invalid address.
+ */
+int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)
+{
+ int i, idx, retval = 0;
+
+ if ((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0))
+ {
+ return -1;
+ }
+
+ u32Len = u32Len - (u32Len % 8); /* u32Len must be multiple of 8. */
+
+ idx = 0;
+
+ while (u32Len >= 8)
+ {
+ FMC->ISPADDR = u32Addr;
+ FMC->MPDAT0 = pu32Buf[idx++];
+ FMC->MPDAT1 = pu32Buf[idx++];
+ FMC->MPDAT2 = pu32Buf[idx++];
+ FMC->MPDAT3 = pu32Buf[idx++];
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM_MUL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ for (i = 16; i < FMC_MULTI_WORD_PROG_LEN; )
+ {
+ while (FMC->MPSTS & (FMC_MPSTS_D0_Msk | FMC_MPSTS_D1_Msk))
+ ;
+ retval += 8;
+ u32Len -= 8;
+ if (u32Len < 8)
+ {
+ return retval;
+ }
+
+ if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk))
+ {
+ /* printf(" [WARNING] busy cleared after D0D1 cleared!\n"); */
+ i += 8;
+ break;
+ }
+
+ FMC->MPDAT0 = pu32Buf[idx++];
+ FMC->MPDAT1 = pu32Buf[idx++];
+
+ if (i == FMC_MULTI_WORD_PROG_LEN/4)
+ break; // done
+
+ while (FMC->MPSTS & (FMC_MPSTS_D2_Msk | FMC_MPSTS_D3_Msk))
+ ;
+ retval += 8;
+ u32Len -= 8;
+ if (u32Len < 8)
+ {
+ return retval;
+ }
+
+ if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk))
+ {
+ /* printf(" [WARNING] busy cleared after D2D3 cleared!\n"); */
+ i += 8;
+ break;
+ }
+
+ FMC->MPDAT2 = pu32Buf[idx++];
+ FMC->MPDAT3 = pu32Buf[idx++];
+ }
+
+ if (i != FMC_MULTI_WORD_PROG_LEN)
+ {
+ /* printf(" [WARNING] Multi-word program interrupted at 0x%x !!\n", i); */
+ return retval;
+ }
+
+ while (FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) ;
+
+ u32Addr += FMC_MULTI_WORD_PROG_LEN;
+ }
+ return retval;
+}
+
+
+/**
+ * @brief Program a 64-bits data to the specified OTP.
+ * @param[in] otp_num The OTP number.
+ * @param[in] low_word Low word of the 64-bits data.
+ * @param[in] high_word Low word of the 64-bits data.
+ * @retval 0 Success
+ * @retval -1 Program failed.
+ * @retval -2 Invalid OTP number.
+ */
+int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word)
+{
+ int32_t ret = 0;
+
+ if (otp_num > 255UL)
+ {
+ ret = -2;
+ }
+
+ if (ret == 0)
+ {
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL;
+ FMC->ISPDAT = low_word;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+ {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+
+ if (ret == 0)
+ {
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL + 4UL;
+ FMC->ISPDAT = high_word;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+ {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Read the 64-bits data from the specified OTP.
+ * @param[in] otp_num The OTP number.
+ * @param[in] low_word Low word of the 64-bits data.
+ * @param[in] high_word Low word of the 64-bits data.
+ * @retval 0 Success
+ * @retval -1 Read failed.
+ * @retval -2 Invalid OTP number.
+ */
+int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word)
+{
+ int32_t ret = 0;
+
+ if (otp_num > 255UL)
+ {
+ ret = -2;
+ }
+
+ if (ret == 0)
+ {
+ FMC->ISPCMD = FMC_ISPCMD_READ_64;
+ FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL ;
+ FMC->ISPDAT = 0x0UL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+ {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ else
+ {
+ *low_word = FMC->MPDAT0;
+ *high_word = FMC->MPDAT1;
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Lock the specified OTP.
+ * @param[in] otp_num The OTP number.
+ * @retval 0 Success
+ * @retval -1 Failed to write OTP lock bits.
+ * @retval -2 Invalid OTP number.
+ */
+int32_t FMC_Lock_OTP(uint32_t otp_num)
+{
+ int32_t ret = 0;
+
+ if (otp_num > 255UL)
+ {
+ ret = -2;
+ }
+
+ if (ret == 0)
+ {
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL;
+ FMC->ISPDAT = 0UL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+ {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Check the OTP is locked or not.
+ * @param[in] otp_num The OTP number.
+ * @retval 1 OTP is locked.
+ * @retval 0 OTP is not locked.
+ * @retval -1 Failed to read OTP lock bits.
+ * @retval -2 Invalid OTP number.
+ */
+int32_t FMC_Is_OTP_Locked(uint32_t otp_num)
+{
+ int32_t ret = 0;
+
+ if (otp_num > 255UL)
+ {
+ ret = -2;
+ }
+
+ if (ret == 0)
+ {
+ FMC->ISPCMD = FMC_ISPCMD_READ;
+ FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+ {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ else
+ {
+ if (FMC->ISPDAT != 0xFFFFFFFFUL)
+ {
+ ret = 1; /* Lock work was progrmmed. OTP was locked. */
+ }
+ }
+ }
+ return ret;
+}
+
+/**
+ * @brief Execute FMC_ISPCMD_READ command to read User Configuration.
+ * @param[out] u32Config A two-word array.
+ * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1.
+ * @param[in] u32Count Available word count in u32Config.
+ * @return Success or not.
+ * @retval 0 Success.
+ * @retval -1 Invalid parameter.
+ */
+int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count)
+{
+ int32_t ret = 0;
+
+ u32Config[0] = FMC_Read(FMC_CONFIG_BASE);
+
+ if (u32Count < 2UL)
+ {
+ ret = -1;
+ }
+ else
+ {
+ u32Config[1] = FMC_Read(FMC_CONFIG_BASE+4UL);
+ }
+ return ret;
+}
+
+
+/**
+ * @brief Execute ISP commands to erase then write User Configuration.
+ * @param[in] u32Config A two-word array.
+ * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1.
+ * @param[in] u32Count The number of User Configuration words to be written.
+ * @return Success or not.
+ * @retval 0 Success
+ * @retval -1 Failed
+ */
+int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count)
+{
+ int i;
+
+ FMC_ENABLE_CFG_UPDATE();
+ FMC_Erase(FMC_CONFIG_BASE);
+
+ if ((FMC_Read(FMC_CONFIG_BASE) != 0xFFFFFFFF) || (FMC_Read(FMC_CONFIG_BASE+4) != 0xFFFFFFFF) ||
+ (FMC_Read(FMC_CONFIG_BASE+8) != 0xFFFF5A5A))
+ {
+ FMC_DISABLE_CFG_UPDATE();
+ return -1;
+ }
+
+ for (i = 0; i < u32Count; i++)
+ {
+ FMC_Write(FMC_CONFIG_BASE+i*4UL, u32Config[i]);
+
+ if (FMC_Read(FMC_CONFIG_BASE+i*4UL) != u32Config[i])
+ {
+ FMC_DISABLE_CFG_UPDATE();
+ return -1;
+ }
+ }
+
+ FMC_DISABLE_CFG_UPDATE();
+ return 0;
+}
+
+
+/**
+ * @brief Run CRC32 checksum calculation and get result.
+ * @param[in] u32addr Starting flash address. It must be a page aligned address.
+ * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.
+ * @return Success or not.
+ * @retval 0 Success.
+ * @retval 0xFFFFFFFF Invalid parameter.
+ */
+uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count)
+{
+ uint32_t ret;
+
+ if ((u32addr % 512UL) || (u32count % 512UL))
+ {
+ ret = 0xFFFFFFFF;
+ }
+ else
+ {
+ FMC->ISPCMD = FMC_ISPCMD_RUN_CKS;
+ FMC->ISPADDR = u32addr;
+ FMC->ISPDAT = u32count;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ FMC->ISPCMD = FMC_ISPCMD_READ_CKS;
+ FMC->ISPADDR = u32addr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ ret = FMC->ISPDAT;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Run flash all one verification and get result.
+ * @param[in] u32addr Starting flash address. It must be a page aligned address.
+ * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.
+ * @retval READ_ALLONE_YES The contents of verified flash area are 0xFFFFFFFF.
+ * @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xFFFFFFFF.
+ * @retval READ_ALLONE_CMD_FAIL Unexpected error occurred.
+ */
+uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count)
+{
+ uint32_t ret = READ_ALLONE_CMD_FAIL;
+
+ FMC->ISPSTS = 0x80UL; /* clear check all one bit */
+
+ FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1;
+ FMC->ISPADDR = u32addr;
+ FMC->ISPDAT = u32count;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ do
+ {
+ FMC->ISPCMD = FMC_ISPCMD_READ_ALL1;
+ FMC->ISPADDR = u32addr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+ }
+ while (FMC->ISPDAT == 0UL);
+
+ if (FMC->ISPDAT == READ_ALLONE_YES)
+ {
+ ret = FMC->ISPDAT;
+ }
+
+ if (FMC->ISPDAT == READ_ALLONE_NOT)
+ {
+ ret = FMC->ISPDAT;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Setup security key.
+ * @param[in] key Key 0~2 to be setup.
+ * @param[in] kpmax Maximum unmatched power-on counting number.
+ * @param[in] kemax Maximum unmatched counting number.
+ * @param[in] lock_CONFIG 1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG.
+ * @param[in] lock_SPROM 1: Security key lock SPROM to write-protect. 0: Don't lock SPROM.
+ * @retval 0 Success.
+ * @retval -1 Key is locked. Cannot overwrite the current key.
+ * @retval -2 Failed to erase flash.
+ * @retval -3 Failed to program key.
+ * @retval -4 Key lock function failed.
+ * @retval -5 CONFIG lock function failed.
+ * @retval -6 SPROM lock function failed.
+ * @retval -7 KPMAX function failed.
+ * @retval -8 KEMAX function failed.
+ */
+int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax,
+ const int32_t lock_CONFIG, const int32_t lock_SPROM)
+{
+ uint32_t lock_ctrl = 0UL;
+ uint32_t u32KeySts;
+ int32_t ret = 0;
+
+ if (FMC->KPKEYSTS != 0x200UL)
+ {
+ ret = -1;
+ }
+
+ if (FMC_Erase(FMC_KPROM_BASE))
+ {
+ ret = -2;
+ }
+
+ if (FMC_Erase(FMC_KPROM_BASE+0x200UL))
+ {
+ ret = -3;
+ }
+
+ if (!lock_CONFIG)
+ {
+ lock_ctrl |= 0x1UL;
+ }
+
+ if (!lock_SPROM)
+ {
+ lock_ctrl |= 0x2UL;
+ }
+
+ if (ret == 0)
+ {
+ FMC_Write(FMC_KPROM_BASE, key[0]);
+ FMC_Write(FMC_KPROM_BASE+0x4UL, key[1]);
+ FMC_Write(FMC_KPROM_BASE+0x8UL, key[2]);
+ FMC_Write(FMC_KPROM_BASE+0xCUL, kpmax);
+ FMC_Write(FMC_KPROM_BASE+0x10UL, kemax);
+ FMC_Write(FMC_KPROM_BASE+0x14UL, lock_ctrl);
+
+ while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }
+
+ u32KeySts = FMC->KPKEYSTS;
+
+ if (!(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk))
+ {
+ /* Security key lock failed! */
+ ret = -4;
+ }
+ else if ((lock_CONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) ||
+ ((!lock_CONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk)))
+ {
+ /* CONFIG lock failed! */
+ ret = -5;
+ }
+ else if ((lock_SPROM && (!(u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) ||
+ ((!lock_SPROM) && (u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk)))
+ {
+ /* CONFIG lock failed! */
+ ret = -6;
+ }
+ else if (((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != kpmax)
+ {
+ /* KPMAX failed! */
+ ret = -7;
+ }
+ else if (((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != kemax)
+ {
+ /* KEMAX failed! */
+ ret = -8;
+ }
+ }
+ return ret;
+}
+
+
+/**
+ * @brief Execute security key comparison.
+ * @param[in] key Key 0~2 to be compared.
+ * @retval 0 Key matched.
+ * @retval -1 Forbidden. Times of key comparison mismatch reach the maximum count.
+ * @retval -2 Key mismatched.
+ * @retval -3 No security key lock. Key comparison is not required.
+ */
+int32_t FMC_CompareSPKey(uint32_t key[3])
+{
+ uint32_t u32KeySts;
+ int32_t ret = 0;
+
+ if (FMC->KPKEYSTS & FMC_KPKEYSTS_FORBID_Msk)
+ {
+ /* FMC_CompareSPKey - FORBID! */
+ ret = -1;
+ }
+
+ if (!(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYLOCK_Msk))
+ {
+ /* FMC_CompareSPKey - key is not locked! */
+ ret = -3;
+ }
+
+ if (ret == 0)
+ {
+ FMC->KPKEY0 = key[0];
+ FMC->KPKEY1 = key[1];
+ FMC->KPKEY2 = key[2];
+ FMC->KPKEYTRG = FMC_KPKEYTRG_KPKEYGO_Msk | FMC_KPKEYTRG_TCEN_Msk;
+
+ while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }
+
+ u32KeySts = FMC->KPKEYSTS;
+
+ if (!(u32KeySts & FMC_KPKEYSTS_KEYMATCH_Msk))
+ {
+ /* Key mismatched! */
+ ret = -2;
+ }
+ else if (u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk)
+ {
+ /* Key matched, but still be locked! */
+ ret = -2;
+ }
+ }
+ return ret;
+}
+
+
+/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group FMC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_gpio.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_gpio.c
new file mode 100644
index 00000000000..c40a68aae3b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_gpio.c
@@ -0,0 +1,153 @@
+/**************************************************************************//**
+ * @file gpio.c
+ * @version V3.00
+ * @brief M480 series GPIO driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+ @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set GPIO operation mode
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ * @param[in] u32Mode Operation mode. It could be \n
+ * GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI.
+ *
+ * @return None
+ *
+ * @details This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t i;
+
+ for(i = 0ul; i < GPIO_PIN_MAX; i++)
+ {
+ if((u32PinMask & (1ul << i))==(1ul << i))
+ {
+ port->MODE = (port->MODE & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
+ }
+ }
+}
+
+/**
+ * @brief Enable GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Pin The pin of specified GPIO port.
+ * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be 0 ~ 13 for PE GPIO port.
+ * It could be 0 ~ 11 for PG GPIO port.
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
+{
+ port->INTTYPE = (port->INTTYPE&~(1ul<> 24) & 0xFFUL) << u32Pin);
+ port->INTEN = (port->INTEN&~(0x00010001ul<INTTYPE &= ~(1UL << u32Pin);
+ port->INTEN &= ~((0x00010001UL) << u32Pin);
+}
+
+/**
+ * @brief Set GPIO slew rate control
+ *
+ * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * @param[in] u32Mode Slew rate mode. \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V)
+ * \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V)
+ * \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V)
+ *
+ * @return None
+ *
+ * @details This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t i;
+
+ for(i = 0ul; i < GPIO_PIN_MAX; i++)
+ {
+ if(u32PinMask & (1ul << i))
+ {
+ port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
+ }
+ }
+}
+
+/**
+ * @brief Set GPIO Pull-up and Pull-down control
+ *
+ * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH
+ * @param[in] u32PinMask The pin of specified GPIO port. It could be 0 ~ 15.
+ * @param[in] u32Mode The pin mode of specified GPIO pin. It could be
+ * \ref GPIO_PUSEL_DISABLE
+ * \ref GPIO_PUSEL_PULL_UP
+ * \ref GPIO_PUSEL_PULL_DOWN
+ *
+ * @return None
+ *
+ * @details Set the pin mode of specified GPIO pin.
+ */
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t i;
+
+ for(i = 0ul; i < GPIO_PIN_MAX; i++)
+ {
+ if(u32PinMask & (1ul << i))
+ {
+ port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
+ }
+ }
+}
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2011~2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_hsusbd.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_hsusbd.c
new file mode 100644
index 00000000000..48474fa875f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_hsusbd.c
@@ -0,0 +1,725 @@
+/**************************************************************************//**
+ * @file hsusbd.c
+ * @version V1.00
+ * @brief M480 HSUSBD driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup HSUSBD_Driver HSUSBD Driver
+ @{
+*/
+
+
+/** @addtogroup HSUSBD_EXPORTED_FUNCTIONS HSUSBD Exported Functions
+ @{
+*/
+/*--------------------------------------------------------------------------*/
+/** @cond HIDDEN_SYMBOLS */
+/* Global variables for Control Pipe */
+S_HSUSBD_CMD_T gUsbCmd;
+S_HSUSBD_INFO_T *g_hsusbd_sInfo;
+
+HSUSBD_VENDOR_REQ g_hsusbd_pfnVendorRequest = NULL;
+HSUSBD_CLASS_REQ g_hsusbd_pfnClassRequest = NULL;
+HSUSBD_SET_INTERFACE_REQ g_hsusbd_pfnSetInterface = NULL;
+uint32_t g_u32HsEpStallLock = 0ul; /* Bit map flag to lock specified EP when SET_FEATURE */
+
+static uint8_t *g_hsusbd_CtrlInPointer = 0;
+static uint32_t g_hsusbd_CtrlMaxPktSize = 64ul;
+static uint8_t g_hsusbd_UsbConfig = 0ul;
+static uint8_t g_hsusbd_UsbAltInterface = 0ul;
+static uint8_t g_hsusbd_EnableTestMode = 0ul;
+static uint8_t g_hsusbd_TestSelector = 0ul;
+
+#ifdef __ICCARM__
+#pragma data_alignment=4
+static uint8_t g_hsusbd_buf[12];
+#else
+static uint8_t g_hsusbd_buf[12] __attribute__((aligned(4)));
+#endif
+
+uint8_t volatile g_hsusbd_Configured = 0ul;
+uint8_t g_hsusbd_CtrlZero = 0ul;
+uint8_t g_hsusbd_UsbAddr = 0ul;
+uint8_t g_hsusbd_ShortPacket = 0ul;
+uint32_t volatile g_hsusbd_DmaDone = 0ul;
+uint32_t g_hsusbd_CtrlInSize = 0ul;
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+ * @brief HSUSBD Initial
+ *
+ * @param[in] param Descriptor
+ * @param[in] pfnClassReq Class Request Callback Function
+ * @param[in] pfnSetInterface SetInterface Request Callback Function
+ *
+ * @return None
+ *
+ * @details This function is used to initial HSUSBD.
+ */
+void HSUSBD_Open(S_HSUSBD_INFO_T *param, HSUSBD_CLASS_REQ pfnClassReq, HSUSBD_SET_INTERFACE_REQ pfnSetInterface)
+{
+ g_hsusbd_sInfo = param;
+ g_hsusbd_pfnClassRequest = pfnClassReq;
+ g_hsusbd_pfnSetInterface = pfnSetInterface;
+
+ /* get EP0 maximum packet size */
+ g_hsusbd_CtrlMaxPktSize = g_hsusbd_sInfo->gu8DevDesc[7];
+
+ /* Initial USB engine */
+ //HSUSBD->PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk | HSUSBD_PHYCTL_DPPUEN_Msk);
+ HSUSBD_ENABLE_PHY();
+ while((HSUSBD->BUSINTSTS & HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk) != HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk ){}
+ HSUSBD_CLR_SE0();
+
+ /* wait PHY clock ready */
+ while (1)
+ {
+ HSUSBD->EP[EPA].EPMPS = 0x20ul;
+ if (HSUSBD->EP[EPA].EPMPS == 0x20ul)
+ {
+ HSUSBD->EP[EPA].EPMPS = 0x0ul;
+ break;
+ }
+ }
+ /* Force SE0, and then clear it to connect*/
+ HSUSBD_SET_SE0();
+}
+
+/**
+ * @brief HSUSBD Start
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details This function is used to start transfer
+ */
+void HSUSBD_Start(void)
+{
+ HSUSBD_CLR_SE0();
+}
+
+/**
+ * @brief Process Setup Packet
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details This function is used to process Setup packet.
+ */
+void HSUSBD_ProcessSetupPacket(void)
+{
+ /* Setup packet process */
+ gUsbCmd.bmRequestType = (uint8_t)(HSUSBD->SETUP1_0 & 0xfful);
+ gUsbCmd.bRequest = (uint8_t)((HSUSBD->SETUP1_0 >> 8) & 0xfful);
+ gUsbCmd.wValue = (uint16_t)HSUSBD->SETUP3_2;
+ gUsbCmd.wIndex = (uint16_t)HSUSBD->SETUP5_4;
+ gUsbCmd.wLength = (uint16_t)HSUSBD->SETUP7_6;
+
+ /* USB device request in setup packet: offset 0, D[6..5]: 0=Standard, 1=Class, 2=Vendor, 3=Reserved */
+ switch (gUsbCmd.bmRequestType & 0x60ul)
+ {
+ case REQ_STANDARD:
+ {
+ HSUSBD_StandardRequest();
+ break;
+ }
+ case REQ_CLASS:
+ {
+ if (g_hsusbd_pfnClassRequest != NULL)
+ {
+ g_hsusbd_pfnClassRequest();
+ }
+ break;
+ }
+ case REQ_VENDOR:
+ {
+ if (g_hsusbd_pfnVendorRequest != NULL)
+ {
+ g_hsusbd_pfnVendorRequest();
+ }
+ break;
+ }
+ default:
+ {
+ /* Setup error, stall the device */
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Get Descriptor request
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details This function is used to process GetDescriptor request.
+ */
+int HSUSBD_GetDescriptor(void)
+{
+ uint32_t u32Len;
+ int val = 0;
+
+ u32Len = gUsbCmd.wLength;
+ g_hsusbd_CtrlZero = (uint8_t)0ul;
+
+ switch ((gUsbCmd.wValue & 0xff00ul) >> 8)
+ {
+ /* Get Device Descriptor */
+ case DESC_DEVICE:
+ {
+ u32Len = Minimum(u32Len, LEN_DEVICE);
+ HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8DevDesc, u32Len);
+ break;
+ }
+ /* Get Configuration Descriptor */
+ case DESC_CONFIG:
+ {
+ uint32_t u32TotalLen;
+ if ((HSUSBD->OPER & 0x04ul) == 0x04ul)
+ {
+ u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[3];
+ u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
+
+ if (u32Len > u32TotalLen)
+ {
+ u32Len = u32TotalLen;
+ if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul)
+ {
+ g_hsusbd_CtrlZero = (uint8_t)1ul;
+ }
+ }
+ HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8ConfigDesc, u32Len);
+ }
+ else
+ {
+ u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[3];
+ u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[2] + (u32TotalLen << 8);
+
+ if (u32Len > u32TotalLen)
+ {
+ u32Len = u32TotalLen;
+ if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul)
+ {
+ g_hsusbd_CtrlZero = (uint8_t)1ul;
+ }
+ }
+ HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FullConfigDesc, u32Len);
+ }
+
+ break;
+ }
+ /* Get Qualifier Descriptor */
+ case DESC_QUALIFIER:
+ {
+ u32Len = Minimum(u32Len, LEN_QUALIFIER);
+ HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8QualDesc, u32Len);
+ break;
+ }
+ /* Get Other Speed Descriptor - Full speed */
+ case DESC_OTHERSPEED:
+ {
+ uint32_t u32TotalLen;
+ if ((HSUSBD->OPER & 0x04ul) == 0x04ul)
+ {
+ u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[3];
+ u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[2] + (u32TotalLen << 8);
+
+ if (u32Len > u32TotalLen)
+ {
+ u32Len = u32TotalLen;
+ if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul)
+ {
+ g_hsusbd_CtrlZero = (uint8_t)1ul;
+ }
+ }
+ HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HSOtherConfigDesc, u32Len);
+ }
+ else
+ {
+ u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[3];
+ u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[2] + (u32TotalLen << 8);
+
+ if (u32Len > u32TotalLen)
+ {
+ u32Len = u32TotalLen;
+ if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul)
+ {
+ g_hsusbd_CtrlZero = (uint8_t)1ul;
+ }
+ }
+ HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FSOtherConfigDesc, u32Len);
+ }
+
+ break;
+ }
+ /* Get HID Descriptor */
+ case DESC_HID:
+ {
+ uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */
+ u32Len = Minimum(u32Len, LEN_HID);
+ u32ConfigDescOffset = g_hsusbd_sInfo->gu32ConfigHidDescIdx[gUsbCmd.wIndex & 0xfful];
+ HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len);
+ break;
+ }
+ /* Get Report Descriptor */
+ case DESC_HID_RPT:
+ {
+ if (u32Len > g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful])
+ {
+ u32Len = g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful];
+ if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul)
+ {
+ g_hsusbd_CtrlZero = (uint8_t)1ul;
+ }
+ }
+ HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HidReportDesc[gUsbCmd.wIndex & 0xfful], u32Len);
+ break;
+ }
+ /* Get String Descriptor */
+ case DESC_STRING:
+ {
+ if((gUsbCmd.wValue & 0xfful) < 8ul)
+ {
+ if (u32Len > g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0])
+ {
+ u32Len = g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0];
+ if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul)
+ {
+ g_hsusbd_CtrlZero = (uint8_t)1ul;
+ }
+ }
+ HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful], u32Len);
+ }
+ else
+ {
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+ val = 1;
+ }
+ break;
+ }
+ default:
+ /* Not support. Reply STALL. */
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+ val = 1;
+ break;
+ }
+ return val;
+}
+
+
+/**
+ * @brief Process USB standard request
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details This function is used to process USB Standard Request.
+ */
+void HSUSBD_StandardRequest(void)
+{
+ /* clear global variables for new request */
+ g_hsusbd_CtrlInPointer = 0;
+ g_hsusbd_CtrlInSize = 0ul;
+
+ if ((gUsbCmd.bmRequestType & 0x80ul) == 0x80ul) /* request data transfer direction */
+ {
+ /* Device to host */
+ switch (gUsbCmd.bRequest)
+ {
+ case GET_CONFIGURATION:
+ {
+ /* Return current configuration setting */
+ HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbConfig, 1ul);
+
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
+ break;
+ }
+ case GET_DESCRIPTOR:
+ {
+ if (!HSUSBD_GetDescriptor())
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
+ }
+ break;
+ }
+ case GET_INTERFACE:
+ {
+ /* Return current interface setting */
+ HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbAltInterface, 1ul);
+
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
+ break;
+ }
+ case GET_STATUS:
+ {
+ /* Device */
+ if (gUsbCmd.bmRequestType == 0x80ul)
+ {
+ if ((g_hsusbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul)
+ {
+ g_hsusbd_buf[0] = (uint8_t)1ul; /* Self-Powered */
+ }
+ else
+ {
+ g_hsusbd_buf[0] = (uint8_t)0ul; /* bus-Powered */
+ }
+ }
+ /* Interface */
+ else if (gUsbCmd.bmRequestType == 0x81ul)
+ {
+ g_hsusbd_buf[0] = (uint8_t)0ul;
+ }
+ /* Endpoint */
+ else if (gUsbCmd.bmRequestType == 0x82ul)
+ {
+ uint8_t ep = (uint8_t)(gUsbCmd.wIndex & 0xFul);
+ g_hsusbd_buf[0] = (uint8_t)HSUSBD_GetStall((uint32_t)ep)? (uint8_t)1 : (uint8_t)0;
+ }
+ g_hsusbd_buf[1] = (uint8_t)0ul;
+ HSUSBD_PrepareCtrlIn(g_hsusbd_buf, 2ul);
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
+ break;
+ }
+ default:
+ {
+ /* Setup error, stall the device */
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+ break;
+ }
+ }
+ }
+ else
+ {
+ /* Host to device */
+ switch (gUsbCmd.bRequest)
+ {
+ case CLEAR_FEATURE:
+ {
+ if((gUsbCmd.wValue & 0xfful) == FEATURE_ENDPOINT_HALT)
+ {
+
+ uint32_t epNum, i;
+
+ /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
+ a flag: g_u32HsEpStallLock is added to support it */
+ epNum = (uint32_t)(gUsbCmd.wIndex & 0xFul);
+ for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == epNum) && ((g_u32HsEpStallLock & (1ul << i)) == 0ul))
+ {
+ HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xeful) | HSUSBD_EP_RSPCTL_TOGGLE;
+ }
+ }
+ }
+ /* Status stage */
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+ break;
+ }
+ case SET_ADDRESS:
+ {
+ g_hsusbd_UsbAddr = (uint8_t)gUsbCmd.wValue;
+ /* Status Stage */
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+ break;
+ }
+ case SET_CONFIGURATION:
+ {
+ g_hsusbd_UsbConfig = (uint8_t)gUsbCmd.wValue;
+ g_hsusbd_Configured = (uint8_t)1ul;
+ /* Status stage */
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+ break;
+ }
+ case SET_FEATURE:
+ {
+ if ((gUsbCmd.wValue & 0x3ul) == 2ul) /* TEST_MODE */
+ {
+ g_hsusbd_EnableTestMode = (uint8_t)1ul;
+ g_hsusbd_TestSelector = (uint8_t)(gUsbCmd.wIndex >> 8);
+ }
+ if ((gUsbCmd.wValue & 0x3ul) == 3ul) /* HNP ebable */
+ {
+ HSOTG->CTL |= (HSOTG_CTL_HNPREQEN_Msk | HSOTG_CTL_BUSREQ_Msk);
+ }
+
+ /* Status stage */
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+ break;
+ }
+ case SET_INTERFACE:
+ {
+ g_hsusbd_UsbAltInterface = (uint8_t)gUsbCmd.wValue;
+ if (g_hsusbd_pfnSetInterface != NULL)
+ {
+ g_hsusbd_pfnSetInterface((uint32_t)g_hsusbd_UsbAltInterface);
+ }
+ /* Status stage */
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+ break;
+ }
+ default:
+ {
+ /* Setup error, stall the device */
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+ break;
+ }
+ }
+ }
+}
+
+/**
+ * @brief Update Device State
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details This function is used to update Device state when Setup packet complete
+ */
+/** @cond HIDDEN_SYMBOLS */
+#define TEST_J 0x01ul
+#define TEST_K 0x02ul
+#define TEST_SE0_NAK 0x03ul
+#define TEST_PACKET 0x04ul
+#define TEST_FORCE_ENABLE 0x05ul
+/** @endcond HIDDEN_SYMBOLS */
+
+void HSUSBD_UpdateDeviceState(void)
+{
+ switch (gUsbCmd.bRequest)
+ {
+ case SET_ADDRESS:
+ {
+ HSUSBD_SET_ADDR(g_hsusbd_UsbAddr);
+ break;
+ }
+ case SET_CONFIGURATION:
+ {
+ if (g_hsusbd_UsbConfig == 0ul)
+ {
+ uint32_t volatile i;
+ /* Reset PID DATA0 */
+ for (i=0ul; iEP[i].EPCFG & 0x1ul) == 0x1ul)
+ {
+ HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE;
+ }
+ }
+ }
+ break;
+ }
+ case SET_FEATURE:
+ {
+ if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT)
+ {
+ uint32_t idx;
+ idx = (uint32_t)(gUsbCmd.wIndex & 0xFul);
+ HSUSBD_SetStall(idx);
+ }
+ else if (g_hsusbd_EnableTestMode)
+ {
+ g_hsusbd_EnableTestMode = (uint8_t)0ul;
+ if (g_hsusbd_TestSelector == TEST_J)
+ {
+ HSUSBD->TEST = TEST_J;
+ }
+ else if (g_hsusbd_TestSelector == TEST_K)
+ {
+ HSUSBD->TEST = TEST_K;
+ }
+ else if (g_hsusbd_TestSelector == TEST_SE0_NAK)
+ {
+ HSUSBD->TEST = TEST_SE0_NAK;
+ }
+ else if (g_hsusbd_TestSelector == TEST_PACKET)
+ {
+ HSUSBD->TEST = TEST_PACKET;
+ }
+ else if (g_hsusbd_TestSelector == TEST_FORCE_ENABLE)
+ {
+ HSUSBD->TEST = TEST_FORCE_ENABLE;
+ }
+ }
+ break;
+ }
+ case CLEAR_FEATURE:
+ {
+ if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT)
+ {
+ uint32_t idx;
+ idx = (uint32_t)(gUsbCmd.wIndex & 0xFul);
+ HSUSBD_ClearStall(idx);
+ }
+ break;
+ }
+ default:
+ break;
+ }
+}
+
+
+/**
+ * @brief Prepare Control IN transaction
+ *
+ * @param[in] pu8Buf Control IN data pointer
+ * @param[in] u32Size IN transfer size
+ *
+ * @return None
+ *
+ * @details This function is used to prepare Control IN transfer
+ */
+void HSUSBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size)
+{
+ g_hsusbd_CtrlInPointer = pu8Buf;
+ g_hsusbd_CtrlInSize = u32Size;
+}
+
+
+
+/**
+ * @brief Start Control IN transfer
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details This function is used to start Control IN
+ */
+void HSUSBD_CtrlIn(void)
+{
+ uint32_t volatile i, cnt;
+ uint8_t u8Value;
+ if(g_hsusbd_CtrlInSize >= g_hsusbd_CtrlMaxPktSize)
+ {
+ /* Data size > MXPLD */
+ cnt = g_hsusbd_CtrlMaxPktSize >> 2;
+ for (i=0ul; iCEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer;
+ g_hsusbd_CtrlInPointer = (uint8_t *)(g_hsusbd_CtrlInPointer + 4ul);
+ }
+ HSUSBD_START_CEP_IN(g_hsusbd_CtrlMaxPktSize);
+ g_hsusbd_CtrlInSize -= g_hsusbd_CtrlMaxPktSize;
+ }
+ else
+ {
+ /* Data size <= MXPLD */
+ cnt = g_hsusbd_CtrlInSize >> 2;
+ for (i=0ul; iCEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer;
+ g_hsusbd_CtrlInPointer += 4ul;
+ }
+
+ for (i=0ul; i<(g_hsusbd_CtrlInSize % 4ul); i++)
+ {
+ u8Value = *(uint8_t *)(g_hsusbd_CtrlInPointer+i);
+ outpb(&HSUSBD->CEPDAT, u8Value);
+ }
+
+ HSUSBD_START_CEP_IN(g_hsusbd_CtrlInSize);
+ g_hsusbd_CtrlInPointer = 0;
+ g_hsusbd_CtrlInSize = 0ul;
+ }
+}
+
+/**
+ * @brief Start Control OUT transaction
+ *
+ * @param[in] pu8Buf Control OUT data pointer
+ * @param[in] u32Size OUT transfer size
+ *
+ * @return None
+ *
+ * @details This function is used to start Control OUT transfer
+ */
+void HSUSBD_CtrlOut(uint8_t pu8Buf[], uint32_t u32Size)
+{
+ uint32_t volatile i;
+ while(1)
+ {
+ if ((HSUSBD->CEPINTSTS & HSUSBD_CEPINTSTS_RXPKIF_Msk) == HSUSBD_CEPINTSTS_RXPKIF_Msk)
+ {
+ for (i=0ul; iCEPDAT);
+ }
+ HSUSBD->CEPINTSTS = HSUSBD_CEPINTSTS_RXPKIF_Msk;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Clear all software flags
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details This function is used to clear all software control flag
+ */
+void HSUSBD_SwReset(void)
+{
+ /* Reset all variables for protocol */
+ g_hsusbd_UsbAddr = (uint8_t)0ul;
+ g_hsusbd_DmaDone = 0ul;
+ g_hsusbd_ShortPacket = (uint8_t)0ul;
+ g_hsusbd_Configured = (uint8_t)0ul;
+
+ /* Reset USB device address */
+ HSUSBD_SET_ADDR(0ul);
+}
+
+/**
+ * @brief HSUSBD Set Vendor Request
+ *
+ * @param[in] pfnVendorReq Vendor Request Callback Function
+ *
+ * @return None
+ *
+ * @details This function is used to set HSUSBD vendor request callback function
+ */
+void HSUSBD_SetVendorRequest(HSUSBD_VENDOR_REQ pfnVendorReq)
+{
+ g_hsusbd_pfnVendorRequest = pfnVendorReq;
+}
+
+
+/*@}*/ /* end of group HSUSBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group HSUSBD_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2c.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2c.c
new file mode 100644
index 00000000000..436b7e586b6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2c.c
@@ -0,0 +1,1486 @@
+/**************************************************************************//**
+ * @file i2c.c
+ * @version V3.00
+ * @brief M480 series I2C driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup I2C_Driver I2C Driver
+ @{
+*/
+
+
+/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+ @{
+*/
+
+/**
+ * @brief Enable specify I2C Controller and set Clock Divider
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u32BusClock The target I2C bus clock in Hz
+ *
+ * @return Actual I2C bus clock frequency
+ *
+ * @details The function enable the specify I2C Controller and set proper Clock Divider
+ * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock.
+ * I2C Bus clock = PCLK / (4*(divider+1).
+ *
+ */
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
+{
+ uint32_t u32Div;
+ uint32_t u32Pclk;
+
+ if(i2c == I2C1)
+ {
+ u32Pclk = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32Pclk = CLK_GetPCLK0Freq();
+ }
+
+ u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */
+ i2c->CLKDIV = u32Div;
+
+ /* Enable I2C */
+ i2c->CTL0 |= I2C_CTL0_I2CEN_Msk;
+
+ return (u32Pclk / ((u32Div + 1U) << 2U));
+}
+
+/**
+ * @brief Disable specify I2C Controller
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Reset I2C Controller and disable specify I2C port.
+ *
+ */
+
+void I2C_Close(I2C_T *i2c)
+{
+ /* Reset I2C Controller */
+ if((uint32_t)i2c == I2C0_BASE)
+ {
+ SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
+ }
+ else if((uint32_t)i2c == I2C1_BASE)
+ {
+ SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
+ }
+ else if((uint32_t)i2c == I2C2_BASE)
+ {
+ SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk;
+ }
+
+ /* Disable I2C */
+ i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk;
+}
+
+/**
+ * @brief Clear Time-out Counter flag
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag .
+ *
+ */
+void I2C_ClearTimeoutFlag(I2C_T *i2c)
+{
+ i2c->TOCTL |= I2C_TOCTL_TOIF_Msk;
+}
+
+/**
+ * @brief Set Control bit of I2C Controller
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8Start Set I2C START condition
+ * @param[in] u8Stop Set I2C STOP condition
+ * @param[in] u8Si Clear SI flag
+ * @param[in] u8Ack Set I2C ACK bit
+ *
+ * @return None
+ *
+ * @details The function set I2C Control bit of I2C Bus protocol.
+ *
+ */
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
+{
+ uint32_t u32Reg = 0U;
+
+ if(u8Start)
+ {
+ u32Reg |= I2C_CTL_STA;
+ }
+
+ if(u8Stop)
+ {
+ u32Reg |= I2C_CTL_STO;
+ }
+
+ if(u8Si)
+ {
+ u32Reg |= I2C_CTL_SI;
+ }
+
+ if(u8Ack)
+ {
+ u32Reg |= I2C_CTL_AA;
+ }
+
+ i2c->CTL0 = (i2c->CTL0 & ~0x3CU) | u32Reg;
+}
+
+/**
+ * @brief Disable Interrupt of I2C Controller
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details The function is used for disable I2C interrupt
+ *
+ */
+void I2C_DisableInt(I2C_T *i2c)
+{
+ i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk;
+}
+
+/**
+ * @brief Enable Interrupt of I2C Controller
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details The function is used for enable I2C interrupt
+ *
+ */
+void I2C_EnableInt(I2C_T *i2c)
+{
+ i2c->CTL0 |= I2C_CTL0_INTEN_Msk;
+}
+
+/**
+ * @brief Get I2C Bus Clock
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return The actual I2C Bus clock in Hz
+ *
+ * @details To get the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
+{
+ uint32_t u32Divider = i2c->CLKDIV;
+ uint32_t u32Pclk;
+
+ if(i2c == I2C1)
+ {
+ u32Pclk = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32Pclk = CLK_GetPCLK0Freq();
+ }
+
+ return (u32Pclk / ((u32Divider + 1U) << 2U));
+}
+
+/**
+ * @brief Set I2C Bus Clock
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u32BusClock The target I2C Bus Clock in Hz
+ *
+ * @return The actual I2C Bus Clock in Hz
+ *
+ * @details To set the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
+{
+ uint32_t u32Div;
+ uint32_t u32Pclk;
+
+ if(i2c == I2C1)
+ {
+ u32Pclk = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32Pclk = CLK_GetPCLK0Freq();
+ }
+
+ u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */
+ i2c->CLKDIV = u32Div;
+
+ return (u32Pclk / ((u32Div + 1U) << 2U));
+}
+
+/**
+ * @brief Get Interrupt Flag
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C interrupt flag status
+ *
+ * @details To get I2C Bus interrupt flag.
+ */
+uint32_t I2C_GetIntFlag(I2C_T *i2c)
+{
+ uint32_t u32Value;
+
+ if((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk)
+ {
+ u32Value = 1U;
+ }
+ else
+ {
+ u32Value = 0U;
+ }
+
+ return u32Value;
+}
+
+/**
+ * @brief Get I2C Bus Status Code
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C Status Code
+ *
+ * @details To get I2C Bus Status Code.
+ */
+uint32_t I2C_GetStatus(I2C_T *i2c)
+{
+ return (i2c->STATUS0);
+}
+
+/**
+ * @brief Read a Byte from I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C Data
+ *
+ * @details To read a bytes data from specify I2C port.
+ */
+uint8_t I2C_GetData(I2C_T *i2c)
+{
+ return (uint8_t)(i2c->DAT);
+}
+
+/**
+ * @brief Send a byte to I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8Data The data to send to I2C bus
+ *
+ * @return None
+ *
+ * @details This function is used to write a byte to specified I2C port
+ */
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
+{
+ i2c->DAT = u8Data;
+}
+
+/**
+ * @brief Set 7-bit Slave Address and GC Mode
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8SlaveNo Set the number of I2C address register (0~3)
+ * @param[in] u8SlaveAddr 7-bit slave address
+ * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE)
+ *
+ * @return None
+ *
+ * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3)
+ * and enable GC Mode.
+ *
+ */
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
+{
+ switch(u8SlaveNo)
+ {
+ case 1:
+ i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
+ break;
+ case 2:
+ i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
+ break;
+ case 3:
+ i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
+ break;
+ case 0:
+ default:
+ i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
+ break;
+ }
+}
+
+/**
+ * @brief Configure the mask bits of 7-bit Slave Address
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3)
+ * @param[in] u8SlaveAddrMask A byte for slave address mask
+ *
+ * @return None
+ *
+ * @details This function is used to set 7-bit slave addresses.
+ *
+ */
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
+{
+ switch(u8SlaveNo)
+ {
+ case 1:
+ i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1U;
+ break;
+ case 2:
+ i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1U;
+ break;
+ case 3:
+ i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1U;
+ break;
+ case 0:
+ default:
+ i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1U;
+ break;
+ }
+}
+
+/**
+ * @brief Enable Time-out Counter Function and support Long Time-out
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1)
+ *
+ * @return None
+ *
+ * @details This function enable Time-out Counter function and configure DIV4 to support Long
+ * Time-out.
+ *
+ */
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
+{
+ if(u8LongTimeout)
+ {
+ i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk;
+ }
+ else
+ {
+ i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk;
+ }
+
+ i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+}
+
+/**
+ * @brief Disable Time-out Counter Function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details To disable Time-out Counter function in I2CTOC register.
+ *
+ */
+void I2C_DisableTimeout(I2C_T *i2c)
+{
+ i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+}
+
+/**
+ * @brief Enable I2C Wake-up Function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details To enable Wake-up function of I2C Wake-up control register.
+ *
+ */
+void I2C_EnableWakeup(I2C_T *i2c)
+{
+ i2c->WKCTL |= I2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief Disable I2C Wake-up Function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details To disable Wake-up function of I2C Wake-up control register.
+ *
+ */
+void I2C_DisableWakeup(I2C_T *i2c)
+{
+ i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief To get SMBus Status
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return SMBus status
+ *
+ * @details To get the Bus Management status of I2C_BUSSTS register
+ *
+ */
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c)
+{
+ return (i2c->BUSSTS);
+}
+
+/**
+ * @brief Clear SMBus Interrupt Flag
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag
+ *
+ * @return None
+ *
+ * @details To clear flags of I2C_BUSSTS status register if interrupt set.
+ *
+ */
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)
+{
+ i2c->BUSSTS = u8SMBusIntFlag;
+}
+
+/**
+ * @brief Set SMBus Bytes Counts of Transmission or Reception
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u32PktSize Transmit / Receive bytes
+ *
+ * @return None
+ *
+ * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
+ *
+ */
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)
+{
+ i2c->PKTSIZE = u32PktSize;
+}
+
+/**
+ * @brief Init SMBus Host/Device Mode
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0))
+ *
+ * @return None
+ *
+ * @details Using SMBus communication must specify the port is a Host or a Device.
+ *
+ */
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)
+{
+ /* Clear BMHEN, BMDEN of BUSCTL Register */
+ i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk);
+
+ /* Set SMBus Host/Device Mode, and enable Bus Management*/
+ if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE)
+ {
+ i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk);
+ }
+ else
+ {
+ i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk);
+ }
+}
+
+/**
+ * @brief Disable SMBus function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode.
+ *
+ */
+void I2C_SMBusClose(I2C_T *i2c)
+{
+
+ i2c->BUSCTL = 0x00U;
+}
+
+/**
+ * @brief Enable SMBus PEC Transmit Function
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE)
+ *
+ * @return None
+ *
+ * @details When enable CRC check function, the Host or Device needs to transmit CRC byte.
+ *
+ */
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)
+{
+ i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk;
+
+ if(u8PECTxEn)
+ {
+ i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk);
+ }
+ else
+ {
+ i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk;
+ }
+}
+
+/**
+ * @brief Get SMBus CRC value
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return A byte is packet error check value
+ *
+ * @details The CRC check value after a transmission or a reception by count by using CRC8
+ *
+ */
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
+{
+ return (uint8_t)i2c->PKTCRC;
+}
+
+/**
+ * @brief Calculate Time-out of SMBus idle period
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] us Time-out length(us)
+ * @param[in] u32Hclk I2C peripheral clock frequency
+ *
+ * @return None
+ *
+ * @details This function is used to set SMBus Time-out length when bus is in Idle state.
+ *
+ */
+
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk)
+{
+ uint32_t u32Div, u32Hclk_kHz;
+
+ i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk;
+ u32Hclk_kHz = u32Hclk / 1000U;
+ u32Div = (((us * u32Hclk_kHz) / 1000U) >> 2U) - 1U;
+ if(u32Div > 255U)
+ {
+ i2c->BUSTOUT = 0xFFU;
+ }
+ else
+ {
+ i2c->BUSTOUT = u32Div;
+ }
+
+}
+
+/**
+ * @brief Calculate Time-out of SMBus active period
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] ms Time-out length(ms)
+ * @param[in] u32Pclk peripheral clock frequency
+ *
+ * @return None
+ *
+ * @details This function is used to set SMBus Time-out length when bus is in active state.
+ * Time-out length is calculate the SCL line "one clock" pull low timing.
+ *
+ */
+
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
+{
+ uint32_t u32Div, u32Pclk_kHz;
+
+ i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
+
+ /* DIV4 disabled */
+ i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+ u32Pclk_kHz = u32Pclk / 1000U;
+ u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;
+ if(u32Div <= 0xFFU)
+ {
+ i2c->BUSTOUT = u32Div;
+ }
+ else
+ {
+ /* DIV4 enabled */
+ i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+ i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */
+ }
+}
+
+/**
+ * @brief Calculate Cumulative Clock low Time-out of SMBus active period
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] ms Time-out length(ms)
+ * @param[in] u32Pclk peripheral clock frequency
+ *
+ * @return None
+ *
+ * @details This function is used to set SMBus Time-out length when bus is in Active state.
+ * Time-out length is calculate the SCL line "clocks" low cumulative timing.
+ *
+ */
+
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
+{
+ uint32_t u32Div, u32Pclk_kHz;
+
+ i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
+
+ /* DIV4 disabled */
+ i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+ u32Pclk_kHz = u32Pclk / 1000U;
+ u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;
+ if(u32Div <= 0xFFU)
+ {
+ i2c->CLKTOUT = u32Div;
+ }
+ else
+ {
+ /* DIV4 enabled */
+ i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+ i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */
+ }
+}
+
+
+/**
+ * @brief Write a byte to Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] data Write a byte data to Slave
+ *
+ * @retval 0 Write data success
+ * @retval 1 Write data fail, or bus occurs error events
+ *
+ * @details The function is used for I2C Master write a byte data to Slave.
+ *
+ */
+
+uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+
+ I2C_START(i2c);
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x18u: /* Slave Address ACK */
+ I2C_SET_DATA(i2c, data); /* Write data to I2CDAT */
+ break;
+ case 0x20u: /* Slave Address NACK */
+ case 0x30u: /* Master transmit data NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x28u:
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
+}
+
+/**
+ * @brief Write multi bytes to Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] *data Pointer to array to write data to Slave
+ * @param[in] u32wLen How many bytes need to write to Slave
+ *
+ * @return A length of how many bytes have been transmitted.
+ *
+ * @details The function is used for I2C Master write multi bytes data to Slave.
+ *
+ */
+
+uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+ uint32_t u32txLen = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x18u: /* Slave Address ACK */
+ case 0x28u:
+ if(u32txLen < u32wLen)
+ {
+ I2C_SET_DATA(i2c, data[u32txLen++]); /* Write Data to I2CDAT */
+ }
+ else
+ {
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ }
+ break;
+ case 0x20u: /* Slave Address NACK */
+ case 0x30u: /* Master transmit data NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ return u32txLen; /* Return bytes length that have been transmitted */
+}
+
+/**
+ * @brief Specify a byte register address and write a byte to Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u8DataAddr Specify a address (1 byte) of data write to
+ * @param[in] data A byte data to write it to Slave
+ *
+ * @retval 0 Write data success
+ * @retval 1 Write data fail, or bus occurs error events
+ *
+ * @details The function is used for I2C Master specify a address that data write to in Slave.
+ *
+ */
+
+uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+ uint32_t u32txLen = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Send Slave address with write bit */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x18u: /* Slave Address ACK */
+ I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
+ break;
+ case 0x20u: /* Slave Address NACK */
+ case 0x30u: /* Master transmit data NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x28u:
+ if(u32txLen < 1u)
+ {
+ I2C_SET_DATA(i2c, data);
+ u32txLen++;
+ }
+ else
+ {
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ }
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
+}
+
+
+/**
+ * @brief Specify a byte register address and write multi bytes to Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u8DataAddr Specify a address (1 byte) of data write to
+ * @param[in] *data Pointer to array to write data to Slave
+ * @param[in] u32wLen How many bytes need to write to Slave
+ *
+ * @return A length of how many bytes have been transmitted.
+ *
+ * @details The function is used for I2C Master specify a byte address that multi data bytes write to in Slave.
+ *
+ */
+
+uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+ uint32_t u32txLen = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI;
+ break;
+ case 0x18u: /* Slave Address ACK */
+ I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
+ break;
+ case 0x20u: /* Slave Address NACK */
+ case 0x30u: /* Master transmit data NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x28u:
+ if(u32txLen < u32wLen)
+ {
+ I2C_SET_DATA(i2c, data[u32txLen++]);
+ }
+ else
+ {
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ }
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+
+ return u32txLen; /* Return bytes length that have been transmitted */
+}
+
+/**
+ * @brief Specify two bytes register address and Write a byte to Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u16DataAddr Specify a address (2 byte) of data write to
+ * @param[in] data Write a byte data to Slave
+ *
+ * @retval 0 Write data success
+ * @retval 1 Write data fail, or bus occurs error events
+ *
+ * @details The function is used for I2C Master specify two bytes address that data write to in Slave.
+ *
+ */
+
+uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
+ uint32_t u32txLen = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x18u: /* Slave Address ACK */
+ I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
+ break;
+ case 0x20u: /* Slave Address NACK */
+ case 0x30u: /* Master transmit data NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x28u:
+ if(u8Addr)
+ {
+ I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
+ u8Addr = 0u;
+ }
+ else if((u32txLen < 1u) && (u8Addr == 0u))
+ {
+ I2C_SET_DATA(i2c, data);
+ u32txLen++;
+ }
+ else
+ {
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ }
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
+}
+
+
+/**
+ * @brief Specify two bytes register address and write multi bytes to Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u16DataAddr Specify a address (2 bytes) of data write to
+ * @param[in] data[] A data array for write data to Slave
+ * @param[in] u32wLen How many bytes need to write to Slave
+ *
+ * @return A length of how many bytes have been transmitted.
+ *
+ * @details The function is used for I2C Master specify a byte address that multi data write to in Slave.
+ *
+ */
+
+uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
+ uint32_t u32txLen = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x18u: /* Slave Address ACK */
+ I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
+ break;
+ case 0x20u: /* Slave Address NACK */
+ case 0x30u: /* Master transmit data NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x28u:
+ if(u8Addr)
+ {
+ I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
+ u8Addr = 0u;
+ }
+ else if((u32txLen < u32wLen) && (u8Addr == 0u))
+ {
+ I2C_SET_DATA(i2c, data[u32txLen++]); /* Write data to Register I2CDAT*/
+ }
+ else
+ {
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ }
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ return u32txLen; /* Return bytes length that have been transmitted */
+}
+
+/**
+ * @brief Read a byte from Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ *
+ * @return Read a byte data from Slave
+ *
+ * @details The function is used for I2C Master to read a byte data from Slave.
+ *
+ */
+uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x40u: /* Slave Address ACK */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x48u: /* Slave Address NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x58u:
+ rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ if(u8Err)
+ {
+ rdata = 0u; /* If occurs error, return 0 */
+ }
+ return rdata; /* Return read data */
+}
+
+
+/**
+ * @brief Read multi bytes from Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[out] rdata[] A data array to store data from Slave
+ * @param[in] u32rLen How many bytes need to read from Slave
+ *
+ * @return A length of how many bytes have been received
+ *
+ * @details The function is used for I2C Master to read multi data bytes from Slave.
+ *
+ *
+ */
+uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+ uint32_t u32rxLen = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x40u: /* Slave Address ACK */
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
+ break;
+ case 0x48u: /* Slave Address NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x50u:
+ rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
+ if(u32rxLen < (u32rLen - 1u))
+ {
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
+ }
+ else
+ {
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ }
+ break;
+ case 0x58u:
+ rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ return u32rxLen; /* Return bytes length that have been received */
+}
+
+
+/**
+ * @brief Specify a byte register address and read a byte from Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u8DataAddr Specify a address(1 byte) of data read from
+ *
+ * @return Read a byte data from Slave
+ *
+ * @details The function is used for I2C Master specify a byte address that a data byte read from Slave.
+ *
+ *
+ */
+uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x18u: /* Slave Address ACK */
+ I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
+ break;
+ case 0x20u: /* Slave Address NACK */
+ case 0x30u: /* Master transmit data NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x28u:
+ u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */
+ break;
+ case 0x10u:
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x40u: /* Slave Address ACK */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x48u: /* Slave Address NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x58u:
+ rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ if(u8Err)
+ {
+ rdata = 0u; /* If occurs error, return 0 */
+ }
+ return rdata; /* Return read data */
+}
+
+/**
+ * @brief Specify a byte register address and read multi bytes from Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u8DataAddr Specify a address (1 bytes) of data read from
+ * @param[out] rdata[] A data array to store data from Slave
+ * @param[in] u32rLen How many bytes need to read from Slave
+ *
+ * @return A length of how many bytes have been received
+ *
+ * @details The function is used for I2C Master specify a byte address that multi data bytes read from Slave.
+ *
+ *
+ */
+uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+ uint32_t u32rxLen = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x18u: /* Slave Address ACK */
+ I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
+ break;
+ case 0x20u: /* Slave Address NACK */
+ case 0x30u: /* Master transmit data NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x28u:
+ u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */
+ break;
+ case 0x10u:
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x40u: /* Slave Address ACK */
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
+ break;
+ case 0x48u: /* Slave Address NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x50u:
+ rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
+ if(u32rxLen < (u32rLen - 1u))
+ {
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
+ }
+ else
+ {
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ }
+ break;
+ case 0x58u:
+ rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ return u32rxLen; /* Return bytes length that have been received */
+}
+
+/**
+ * @brief Specify two bytes register address and read a byte from Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u16DataAddr Specify an address(2 bytes) of data read from
+ *
+ * @return Read a byte data from Slave
+ *
+ * @details The function is used for I2C Master specify two bytes address that a data byte read from Slave.
+ *
+ *
+ */
+uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Addr = 1u, u8Ctrl = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x18u: /* Slave Address ACK */
+ I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
+ break;
+ case 0x20u: /* Slave Address NACK */
+ case 0x30u: /* Master transmit data NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x28u:
+ if(u8Addr)
+ {
+ I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
+ u8Addr = 0u;
+ }
+ else
+ {
+ u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */
+ }
+ break;
+ case 0x10u:
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x40u: /* Slave Address ACK */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x48u: /* Slave Address NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x58u:
+ rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ if(u8Err)
+ {
+ rdata = 0u; /* If occurs error, return 0 */
+ }
+ return rdata; /* Return read data */
+}
+
+/**
+ * @brief Specify two bytes register address and read multi bytes from Slave
+ *
+ * @param[in] *i2c Point to I2C peripheral
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u16DataAddr Specify a address (2 bytes) of data read from
+ * @param[out] rdata[] A data array to store data from Slave
+ * @param[in] u32rLen How many bytes need to read from Slave
+ *
+ * @return A length of how many bytes have been received
+ *
+ * @details The function is used for I2C Master specify two bytes address that multi data bytes read from Slave.
+ *
+ *
+ */
+uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen)
+{
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
+ uint32_t u32rxLen = 0u;
+
+ I2C_START(i2c); /* Send START */
+ while(u8Xfering && (u8Err == 0u))
+ {
+ I2C_WAIT_READY(i2c) {}
+ switch(I2C_GET_STATUS(i2c))
+ {
+ case 0x08u:
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x18u: /* Slave Address ACK */
+ I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
+ break;
+ case 0x20u: /* Slave Address NACK */
+ case 0x30u: /* Master transmit data NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x28u:
+ if(u8Addr)
+ {
+ I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
+ u8Addr = 0u;
+ }
+ else
+ {
+ u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */
+ }
+ break;
+ case 0x10u:
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ break;
+ case 0x40u: /* Slave Address ACK */
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
+ break;
+ case 0x48u: /* Slave Address NACK */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Err = 1u;
+ break;
+ case 0x50u:
+ rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
+ if(u32rxLen < (u32rLen - 1u))
+ {
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
+ }
+ else
+ {
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */
+ }
+ break;
+ case 0x58u:
+ rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
+ u8Xfering = 0u;
+ break;
+ case 0x38u: /* Arbitration Lost */
+ default: /* Unknow status */
+ I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
+ u8Ctrl = I2C_CTL_SI;
+ u8Err = 1u;
+ break;
+ }
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
+ }
+ return u32rxLen; /* Return bytes length that have been received */
+}
+
+
+/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group I2C_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2s.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2s.c
new file mode 100644
index 00000000000..6e0e5bb6f2b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2s.c
@@ -0,0 +1,250 @@
+/**************************************************************************//**
+ * @file i2s.c
+ * @version V0.10
+ * @brief M480 I2S driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup I2S_Driver I2S Driver
+ @{
+*/
+
+/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions
+ @{
+*/
+
+static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s);
+
+/**
+ * @brief This function is used to get I2S source clock frequency.
+ * @param[in] i2s is the base address of I2S module.
+ * @return I2S source clock frequency (Hz).
+ */
+static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)
+{
+ uint32_t u32Freq, u32ClkSrcSel;
+
+ /* get I2S selection clock source */
+ u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S0SEL_Msk;
+
+ switch (u32ClkSrcSel)
+ {
+ case CLK_CLKSEL3_I2S0SEL_HXT:
+ u32Freq = __HXT;
+ break;
+
+ case CLK_CLKSEL3_I2S0SEL_PLL:
+ u32Freq = CLK_GetPLLClockFreq();
+ break;
+
+ case CLK_CLKSEL3_I2S0SEL_HIRC:
+ u32Freq = __HIRC;
+ break;
+
+ case CLK_CLKSEL3_I2S0SEL_PCLK0:
+ u32Freq = (uint32_t)CLK_GetPCLK0Freq();
+ break;
+
+ default:
+ u32Freq = __HIRC;
+ break;
+ }
+
+ return u32Freq;
+}
+
+/**
+ * @brief This function configures some parameters of I2S interface for general purpose use.
+ * The sample rate may not be used from the parameter, it depends on system's clock settings,
+ * but real sample rate used by system will be returned for reference.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32MasterSlave I2S operation mode. Valid values are:
+ * - \ref I2S_MODE_MASTER
+ * - \ref I2S_MODE_SLAVE
+ * @param[in] u32SampleRate Sample rate
+ * @param[in] u32WordWidth Data length. Valid values are:
+ * - \ref I2S_DATABIT_8
+ * - \ref I2S_DATABIT_16
+ * - \ref I2S_DATABIT_24
+ * - \ref I2S_DATABIT_32
+ * @param[in] u32MonoData: Set audio data to mono or not. Valid values are:
+ * - \ref I2S_ENABLE_MONO
+ * - \ref I2S_DISABLE_MONO
+ * @param[in] u32DataFormat: Data format. This is also used to select I2S or PCM(TDM) function. Valid values are:
+ * - \ref I2S_FORMAT_I2S
+ * - \ref I2S_FORMAT_I2S_MSB
+ * - \ref I2S_FORMAT_I2S_LSB
+ * - \ref I2S_FORMAT_PCM
+ * - \ref I2S_FORMAT_PCM_MSB
+ * - \ref I2S_FORMAT_PCM_LSB
+ * @return Real sample rate.
+ */
+uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat)
+{
+ uint16_t u16Divider;
+ uint32_t u32BitRate, u32SrcClk;
+
+ SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk;
+
+ i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat;
+ i2s->CTL1 = I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8;
+
+ u32SrcClk = I2S_GetSourceClockFreq(i2s);
+
+ u32BitRate = u32SampleRate * (((u32WordWidth>>4U) & 0x3U) + 1U) * 16U;
+ //u16Divider = (uint16_t)((u32SrcClk/u32BitRate) >> 1U) - 1U;
+ u16Divider = (uint16_t)((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U;
+ i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8U);
+
+ /* calculate real sample rate */
+ u32BitRate = u32SrcClk / (2U*((uint32_t)u16Divider+1U));
+ u32SampleRate = u32BitRate / ((((u32WordWidth>>4U) & 0x3U) + 1U) * 16U);
+
+ i2s->CTL0 |= I2S_CTL0_I2SEN_Msk;
+
+ return u32SampleRate;
+}
+
+/**
+ * @brief Disable I2S function and I2S clock.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ */
+void I2S_Close(I2S_T *i2s)
+{
+ i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk;
+}
+
+/**
+ * @brief This function enables the interrupt according to the mask parameter.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Mask is the combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * @return none
+ */
+void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)
+{
+ i2s->IEN |= u32Mask;
+}
+
+/**
+ * @brief This function disables the interrupt according to the mask parameter.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Mask is the combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * @return none
+ */
+void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)
+{
+ i2s->IEN &= ~u32Mask;
+}
+
+/**
+ * @brief Enable MCLK .
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32BusClock is the target MCLK clock
+ * @return Actual MCLK clock
+ */
+uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)
+{
+ uint8_t u8Divider;
+ uint32_t u32SrcClk, u32Reg, u32Clock;
+
+ u32SrcClk = I2S_GetSourceClockFreq(i2s);
+ if (u32BusClock == u32SrcClk)
+ {
+ u8Divider = 0U;
+ }
+ else
+ {
+ u8Divider = (uint8_t)(u32SrcClk/u32BusClock) >> 1U;
+ }
+
+ i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider;
+
+ i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk;
+
+ u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk;
+
+ if (u32Reg == 0U)
+ {
+ u32Clock = u32SrcClk;
+ }
+ else
+ {
+ u32Clock = ((u32SrcClk >> 1U) / u32Reg);
+ }
+
+ return u32Clock;
+}
+
+/**
+ * @brief Disable MCLK .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ */
+void I2S_DisableMCLK(I2S_T *i2s)
+{
+ i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk;
+}
+
+/**
+ * @brief Configure FIFO threshold setting.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7.
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7.
+ * @return None
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+ */
+void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+ i2s->CTL1 = ((i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) |
+ (u32TxThreshold << I2S_CTL1_TXTH_Pos) |
+ (u32RxThreshold << I2S_CTL1_RXTH_Pos));
+}
+
+
+/**
+ * @brief Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32ChannelWidth Channel width. Valid values are:
+ * - \ref I2S_TDM_WIDTH_8BIT
+ * - \ref I2S_TDM_WIDTH_16BIT
+ * - \ref I2S_TDM_WIDTH_24BIT
+ * - \ref I2S_TDM_WIDTH_32BIT
+ * @param[in] u32ChannelNum Channel number. Valid values are:
+ * - \ref I2S_TDM_2CH
+ * - \ref I2S_TDM_4CH
+ * - \ref I2S_TDM_6CH
+ * - \ref I2S_TDM_8CH
+ * @param[in] u32SyncWidth Width for sync pulse. Valid values are:
+ * - \ref I2S_TDM_SYNC_ONE_BCLK
+ * - \ref I2S_TDM_SYNC_ONE_CHANNEL
+ * @return None
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+ */
+void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth)
+{
+ i2s->CTL0 = ((i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) |
+ (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) |
+ (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) |
+ (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos));
+}
+
+/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group I2S_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_pdma.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_pdma.c
new file mode 100644
index 00000000000..a4abf2f5e92
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_pdma.c
@@ -0,0 +1,487 @@
+/**************************************************************************//**
+ * @file pdma.c
+ * @version V1.00
+ * @brief M480 series PDMA driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+static uint8_t u32ChSelect[PDMA_CH_MAX];
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup PDMA_Driver PDMA Driver
+ @{
+*/
+
+
+/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
+ @{
+*/
+
+/**
+ * @brief PDMA Open
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @param[in] u32Mask Channel enable bits.
+ *
+ * @return None
+ *
+ * @details This function enable the PDMA channels.
+ */
+void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask)
+{
+ uint32_t i;
+
+ for (i=0UL; iDSCT[i].CTL = 0UL;
+ u32ChSelect[i] = PDMA_MEM;
+ }
+ }
+
+ pdma->CHCTL |= u32Mask;
+}
+
+/**
+ * @brief PDMA Close
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @return None
+ *
+ * @details This function disable all PDMA channels.
+ */
+void PDMA_Close(PDMA_T * pdma)
+{
+ pdma->CHCTL = 0UL;
+}
+
+/**
+ * @brief Set PDMA Transfer Count
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Width Data width. Valid values are
+ * - \ref PDMA_WIDTH_8
+ * - \ref PDMA_WIDTH_16
+ * - \ref PDMA_WIDTH_32
+ * @param[in] u32TransCount Transfer count
+ *
+ * @return None
+ *
+ * @details This function set the selected channel data width and transfer count.
+ */
+void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
+{
+ pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
+ pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos));
+}
+
+/**
+ * @brief Set PDMA Stride Mode
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32DestLen Destination stride count
+ * @param[in] u32SrcLen Source stride count
+ * @param[in] u32TransCount Transfer count
+ *
+ * @return None
+ *
+ * @details This function set the selected stride mode.
+ */
+void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount)
+{
+ pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;
+ pdma->STRIDE[u32Ch].ASOCR =((u32DestLen-1)<<16) | (u32SrcLen-1);
+ pdma->STRIDE[u32Ch].STCR = u32TransCount-1;
+}
+
+/**
+ * @brief Set PDMA Repeat
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32DestInterval Destination address interval count
+ * @param[in] u32SrcInterval Source address interval count
+ * @param[in] u32RepeatCount Repeat count
+ *
+ * @return None
+ *
+ * @details This function set the selected repeat.
+ */
+void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount)
+{
+ pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;
+ pdma->REPEAT[u32Ch].AICTL =((u32DestInterval)<<16) | (u32SrcInterval);
+ pdma->REPEAT[u32Ch].RCNT = u32RepeatCount;
+}
+
+/**
+ * @brief Set PDMA Transfer Address
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32SrcAddr Source address
+ * @param[in] u32SrcCtrl Source control attribute. Valid values are
+ * - \ref PDMA_SAR_INC
+ * - \ref PDMA_SAR_FIX
+ * @param[in] u32DstAddr destination address
+ * @param[in] u32DstCtrl destination control attribute. Valid values are
+ * - \ref PDMA_DAR_INC
+ * - \ref PDMA_DAR_FIX
+ *
+ * @return None
+ *
+ * @details This function set the selected channel source/destination address and attribute.
+ */
+void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
+{
+ pdma->DSCT[u32Ch].SA = u32SrcAddr;
+ pdma->DSCT[u32Ch].DA = u32DstAddr;
+ pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
+ pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
+}
+
+/**
+ * @brief Set PDMA Transfer Mode
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Peripheral The selected peripheral. Valid values are
+ * - \ref PDMA_MEM
+ * - \ref PDMA_USB_TX
+ * - \ref PDMA_USB_RX
+ * - \ref PDMA_UART0_TX
+ * - \ref PDMA_UART0_RX
+ * - \ref PDMA_UART1_TX
+ * - \ref PDMA_UART1_RX
+ * - \ref PDMA_UART2_TX
+ * - \ref PDMA_UART2_RX
+ * - \ref PDMA_UART3_TX
+ * - \ref PDMA_UART3_RX
+ * - \ref PDMA_UART4_TX
+ * - \ref PDMA_UART4_RX
+ * - \ref PDMA_UART5_TX
+ * - \ref PDMA_UART5_RX
+ * - \ref PDMA_USCI0_TX
+ * - \ref PDMA_USCI0_RX
+ * - \ref PDMA_USCI1_TX
+ * - \ref PDMA_USCI1_RX
+ * - \ref PDMA_QSPI0_TX
+ * - \ref PDMA_QSPI0_RX
+ * - \ref PDMA_SPI0_TX
+ * - \ref PDMA_SPI0_RX
+ * - \ref PDMA_SPI1_TX
+ * - \ref PDMA_SPI1_RX
+ * - \ref PDMA_SPI2_TX
+ * - \ref PDMA_SPI2_RX
+ * - \ref PDMA_SPI3_TX
+ * - \ref PDMA_SPI3_RX
+ * - \ref PDMA_EPWM0_P1_RX
+ * - \ref PDMA_EPWM0_P2_RX
+ * - \ref PDMA_EPWM0_P3_RX
+ * - \ref PDMA_EPWM1_P1_RX
+ * - \ref PDMA_EPWM1_P2_RX
+ * - \ref PDMA_EPWM1_P3_RX
+ * - \ref PDMA_I2C0_TX
+ * - \ref PDMA_I2C0_RX
+ * - \ref PDMA_I2C1_TX
+ * - \ref PDMA_I2C1_RX
+ * - \ref PDMA_I2C2_TX
+ * - \ref PDMA_I2C2_RX
+ * - \ref PDMA_I2S0_TX
+ * - \ref PDMA_I2S0_RX
+ * - \ref PDMA_TMR0
+ * - \ref PDMA_TMR1
+ * - \ref PDMA_TMR2
+ * - \ref PDMA_TMR3
+ * - \ref PDMA_EADC0_RX
+ * - \ref PDMA_DAC0_TX
+ * - \ref PDMA_DAC1_TX
+ * - \ref PDMA_EPWM0_CH0_TX
+ * - \ref PDMA_EPWM0_CH1_TX
+ * - \ref PDMA_EPWM0_CH2_TX
+ * - \ref PDMA_EPWM0_CH3_TX
+ * - \ref PDMA_EPWM0_CH4_TX
+ * - \ref PDMA_EPWM0_CH5_TX
+ * - \ref PDMA_EPWM1_CH0_TX
+ * - \ref PDMA_EPWM1_CH1_TX
+ * - \ref PDMA_EPWM1_CH2_TX
+ * - \ref PDMA_EPWM1_CH3_TX
+ * - \ref PDMA_EPWM1_CH4_TX
+ * - \ref PDMA_EPWM1_CH5_TX
+ * - \ref PDMA_UART6_TX
+ * - \ref PDMA_UART6_RX
+ * - \ref PDMA_UART7_TX
+ * - \ref PDMA_UART7_RX
+ * - \ref PDMA_EADC1_RX
+ * @param[in] u32ScatterEn Scatter-gather mode enable
+ * @param[in] u32DescAddr Scatter-gather descriptor address
+ *
+ * @return None
+ *
+ * @details This function set the selected channel transfer mode. Include peripheral setting.
+ */
+void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
+{
+ u32ChSelect[u32Ch] = u32Peripheral;
+ switch(u32Ch)
+ {
+ case 0ul:
+ pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
+ break;
+ case 1ul:
+ pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
+ break;
+ case 2ul:
+ pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
+ break;
+ case 3ul:
+ pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
+ break;
+ case 4ul:
+ pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
+ break;
+ case 5ul:
+ pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
+ break;
+ case 6ul:
+ pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
+ break;
+ case 7ul:
+ pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
+ break;
+ case 8ul:
+ pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
+ break;
+ case 9ul:
+ pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
+ break;
+ case 10ul:
+ pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos);
+ break;
+ case 11ul:
+ pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos);
+ break;
+ case 12ul:
+ pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral;
+ break;
+ case 13ul:
+ pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC13_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC13_Pos);
+ break;
+ case 14ul:
+ pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC14_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC14_Pos);
+ break;
+ case 15ul:
+ pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC15_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC15_Pos);
+ break;
+ default:
+ break;
+ }
+
+ if(u32ScatterEn)
+ {
+ pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
+ pdma->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA);
+ }
+ else
+ {
+ pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
+ }
+}
+
+/**
+ * @brief Set PDMA Burst Type and Size
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32BurstType Burst mode or single mode. Valid values are
+ * - \ref PDMA_REQ_SINGLE
+ * - \ref PDMA_REQ_BURST
+ * @param[in] u32BurstSize Set the size of burst mode. Valid values are
+ * - \ref PDMA_BURST_128
+ * - \ref PDMA_BURST_64
+ * - \ref PDMA_BURST_32
+ * - \ref PDMA_BURST_16
+ * - \ref PDMA_BURST_8
+ * - \ref PDMA_BURST_4
+ * - \ref PDMA_BURST_2
+ * - \ref PDMA_BURST_1
+ *
+ * @return None
+ *
+ * @details This function set the selected channel burst type and size.
+ */
+void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
+{
+ pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
+ pdma->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
+}
+
+/**
+ * @brief Enable timeout function
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @param[in] u32Mask Channel enable bits.
+ *
+ * @return None
+ *
+ * @details This function enable timeout function of the selected channel(s).
+ */
+void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask)
+{
+ pdma->TOUTEN |= u32Mask;
+}
+
+/**
+ * @brief Disable timeout function
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ *
+ * @param[in] u32Mask Channel enable bits.
+ *
+ * @return None
+ *
+ * @details This function disable timeout function of the selected channel(s).
+ */
+void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask)
+{
+ pdma->TOUTEN &= ~u32Mask;
+}
+
+/**
+ * @brief Set PDMA Timeout Count
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel,
+ * @param[in] u32OnOff Enable/disable time out function
+ * @param[in] u32TimeOutCnt Timeout count
+ *
+ * @return None
+ *
+ * @details This function set the timeout count.
+ * @note M480 only supported channel 0/1.
+ */
+void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
+{
+ switch(u32Ch)
+ {
+ case 0ul:
+ pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
+ break;
+ case 1ul:
+ pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
+ break;
+ default:
+ break;
+ }
+
+ if (u32OnOff)
+ pdma->TOUTEN |= (1 << u32Ch);
+ else
+ pdma->TOUTEN &= ~(1 << u32Ch);
+}
+
+/**
+ * @brief Trigger PDMA
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ *
+ * @return None
+ *
+ * @details This function trigger the selected channel.
+ */
+void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch)
+{
+ if(u32ChSelect[u32Ch] == PDMA_MEM)
+ {
+ pdma->SWREQ = (1ul << u32Ch);
+ }
+ else {}
+}
+
+/**
+ * @brief Enable Interrupt
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Mask The Interrupt Type. Valid values are
+ * - \ref PDMA_INT_TRANS_DONE
+ * - \ref PDMA_INT_TEMPTY
+ * - \ref PDMA_INT_TIMEOUT
+ *
+ * @return None
+ *
+ * @details This function enable the selected channel interrupt.
+ */
+void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask)
+{
+ switch(u32Mask)
+ {
+ case PDMA_INT_TRANS_DONE:
+ pdma->INTEN |= (1ul << u32Ch);
+ break;
+ case PDMA_INT_TEMPTY:
+ pdma->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
+ break;
+ case PDMA_INT_TIMEOUT:
+ pdma->TOUTIEN |= (1ul << u32Ch);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Disable Interrupt
+ *
+ * @param[in] pdma The pointer of the specified PDMA module
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Mask The Interrupt Type. Valid values are
+ * - \ref PDMA_INT_TRANS_DONE
+ * - \ref PDMA_INT_TEMPTY
+ * - \ref PDMA_INT_TIMEOUT
+ *
+ * @return None
+ *
+ * @details This function disable the selected channel interrupt.
+ */
+void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask)
+{
+ switch(u32Mask)
+ {
+ case PDMA_INT_TRANS_DONE:
+ pdma->INTEN &= ~(1ul << u32Ch);
+ break;
+ case PDMA_INT_TEMPTY:
+ pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
+ break;
+ case PDMA_INT_TIMEOUT:
+ pdma->TOUTIEN &= ~(1ul << u32Ch);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PDMA_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qei.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qei.c
new file mode 100644
index 00000000000..225b7e16737
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qei.c
@@ -0,0 +1,144 @@
+/**************************************************************************//**
+ * @file qei.c
+ * @version V3.00
+ * @brief Quadrature Encoder Interface (QEI) driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup QEI_Driver QEI Driver
+ @{
+*/
+
+/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Close QEI function
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return None
+ * @details This function reset QEI configuration and stop QEI counting.
+ */
+void QEI_Close(QEI_T* qei)
+{
+ /* Reset QEI configuration */
+ qei->CTL = (uint32_t)0;
+}
+
+/**
+ * @brief Disable QEI interrupt
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32IntSel Interrupt type selection.
+ * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt
+ * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt
+ * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt
+ * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt
+ * @return None
+ * @details This function disable QEI specified interrupt.
+ */
+void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel)
+{
+ /* Disable QEI specified interrupt */
+ QEI_DISABLE_INT(qei, u32IntSel);
+
+ /* Disable NVIC QEI IRQ */
+ if(qei ==(QEI_T*)QEI0)
+ {
+ NVIC_DisableIRQ((IRQn_Type)QEI0_IRQn);
+ }
+ else
+ {
+ NVIC_DisableIRQ((IRQn_Type)QEI1_IRQn);
+ }
+}
+
+/**
+ * @brief Enable QEI interrupt
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32IntSel Interrupt type selection.
+ * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt
+ * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt
+ * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt
+ * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt
+ * @return None
+ * @details This function enable QEI specified interrupt.
+ */
+void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel)
+{
+ /* Enable QEI specified interrupt */
+ QEI_ENABLE_INT(qei, u32IntSel);
+
+ /* Enable NVIC QEI IRQ */
+ if(qei == (QEI_T*)QEI0)
+ {
+ NVIC_EnableIRQ(QEI0_IRQn);
+ }
+ else
+ {
+ NVIC_EnableIRQ(QEI1_IRQn);
+ }
+}
+
+/**
+ * @brief Open QEI in specified mode and enable input
+ * @param[in] qei The pointer of the specified QEI module.
+ * @param[in] u32Mode QEI counting mode.
+ * - \ref QEI_CTL_X4_FREE_COUNTING_MODE
+ * - \ref QEI_CTL_X2_FREE_COUNTING_MODE
+ * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE
+ * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE
+ * @param[in] u32Value The counter maximum value in compare-counting mode.
+ * @return None
+ * @details This function set QEI in specified mode and enable input.
+ */
+void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value)
+{
+ /* Set QEI function configuration */
+ /* Set QEI counting mode */
+ /* Enable IDX, QEA and QEB input to QEI controller */
+ qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk);
+
+ /* Set QEI maximum count value in in compare-counting mode */
+ qei->CNTMAX = u32Value;
+}
+
+/**
+ * @brief Start QEI function
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return None
+ * @details This function enable QEI function and start QEI counting.
+ */
+void QEI_Start(QEI_T* qei)
+{
+ /* Enable QEI controller function */
+ qei->CTL |= QEI_CTL_QEIEN_Msk;
+}
+
+/**
+ * @brief Stop QEI function
+ * @param[in] qei The pointer of the specified QEI module.
+ * @return None
+ * @details This function disable QEI function and stop QEI counting.
+ */
+void QEI_Stop(QEI_T* qei)
+{
+ /* Disable QEI controller function */
+ qei->CTL &= (~QEI_CTL_QEIEN_Msk);
+}
+
+
+/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group QEI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qspi.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qspi.c
new file mode 100644
index 00000000000..b0f3ff2b5a3
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qspi.c
@@ -0,0 +1,856 @@
+/**************************************************************************//**
+ * @file qspi.c
+ * @version V3.00
+ * @brief M480 series QSPI driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup QSPI_Driver QSPI Driver
+ @{
+*/
+
+
+/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make QSPI module be ready to transfer.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER)
+ * @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3)
+ * @param[in] u32DataWidth Decides the data width of a QSPI transaction.
+ * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz.
+ * @return Actual frequency of QSPI peripheral clock.
+ * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
+ * slave selection function is disabled.
+ * In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0.
+ * The actual clock rate may be different from the target QSPI clock rate.
+ * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the
+ * actual QSPI clock rate will be 6MHz.
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+ * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+ * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
+ * @note In slave mode, the QSPI peripheral clock rate will be equal to APB clock rate.
+ */
+uint32_t QSPI_Open(QSPI_T *qspi,
+ uint32_t u32MasterSlave,
+ uint32_t u32QSPIMode,
+ uint32_t u32DataWidth,
+ uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U;
+
+ if(u32DataWidth == 32U)
+ {
+ u32DataWidth = 0U;
+ }
+
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+
+ if(u32MasterSlave == QSPI_MASTER)
+ {
+ /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
+ qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
+
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+ qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk;
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Select PCLK as the clock source of QSPI */
+ if (qspi == QSPI0)
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
+ else if (qspi == QSPI1)
+ CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_QSPI1SEL_Msk)) | CLK_CLKSEL3_QSPI1SEL_PCLK1;
+ }
+
+ /* Check clock source of QSPI */
+ if (qspi == QSPI0)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32ClkSrc = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if (qspi == QSPI1)
+ {
+ if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ u32ClkSrc = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Set DIVIDER = 0 */
+ qspi->CLKDIV = 0U;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ qspi->CLKDIV = 0U;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock == 0U)
+ {
+ /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */
+ qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */
+ if(u32Div > 0xFFU)
+ {
+ u32Div = 0xFFU;
+ qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+ }
+ else
+ {
+ qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (u32Div + 1U));
+ }
+ }
+ }
+ else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */
+ {
+ /* Default setting: slave selection signal is low level active. */
+ qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
+
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+ qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk;
+
+ /* Set DIVIDER = 0 */
+ qspi->CLKDIV = 0U;
+
+ /* Select PCLK as the clock source of QSPI */
+ if (qspi == QSPI0)
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
+ /* Return slave peripheral clock rate */
+ u32RetValue = CLK_GetPCLK0Freq();
+ }
+ else if (qspi == QSPI1)
+ {
+ CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_QSPI1SEL_Msk)) | CLK_CLKSEL3_QSPI1SEL_PCLK1;
+ /* Return slave peripheral clock rate */
+ u32RetValue = CLK_GetPCLK1Freq();
+ }
+ }
+
+ return u32RetValue;
+}
+
+/**
+ * @brief Disable QSPI controller.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None
+ * @details This function will reset QSPI controller.
+ */
+void QSPI_Close(QSPI_T *qspi)
+{
+ /* Reset QSPI */
+ if (qspi == QSPI0)
+ {
+ SYS->IPRST1 |= SYS_IPRST1_QSPI0RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_QSPI0RST_Msk;
+ }
+ else if (qspi == QSPI1)
+ {
+ SYS->IPRST2 |= SYS_IPRST2_QSPI1RST_Msk;
+ SYS->IPRST2 &= ~SYS_IPRST2_QSPI1RST_Msk;
+ }
+}
+
+/**
+ * @brief Clear RX FIFO buffer.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None
+ * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1.
+ */
+void QSPI_ClearRxFIFO(QSPI_T *qspi)
+{
+ qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk;
+}
+
+/**
+ * @brief Clear TX FIFO buffer.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None
+ * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1.
+ * @note The TX shift register will not be cleared.
+ */
+void QSPI_ClearTxFIFO(QSPI_T *qspi)
+{
+ qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk;
+}
+
+/**
+ * @brief Disable the automatic slave selection function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None
+ * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
+ */
+void QSPI_DisableAutoSS(QSPI_T *qspi)
+{
+ qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk);
+}
+
+/**
+ * @brief Enable the automatic slave selection function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS)
+ * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW)
+ * @return None
+ * @details This function will enable the automatic slave selection function. Only available in Master mode.
+ * The slave selection pin and the active level will be set in this function.
+ */
+void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+ qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk);
+}
+
+/**
+ * @brief Set the QSPI bus clock.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz.
+ * @return Actual frequency of QSPI bus clock.
+ * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate.
+ * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock
+ * rate will be 6 MHz.
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+ * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+ * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
+ */
+uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc, u32HCLKFreq;
+ uint32_t u32Div, u32RetValue;
+
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Select PCLK as the clock source of QSPI */
+ if (qspi == QSPI0)
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
+ else if (qspi == QSPI1)
+ CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_QSPI1SEL_Msk)) | CLK_CLKSEL3_QSPI1SEL_PCLK1;
+ }
+
+ /* Check clock source of QSPI */
+ if (qspi == QSPI0)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32ClkSrc = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if (qspi == QSPI1)
+ {
+ if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ u32ClkSrc = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Set DIVIDER = 0 */
+ qspi->CLKDIV = 0U;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ qspi->CLKDIV = 0U;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock == 0U)
+ {
+ /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */
+ qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */
+ if(u32Div > 0x1FFU)
+ {
+ u32Div = 0x1FFU;
+ qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+ }
+ else
+ {
+ qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (u32Div + 1U));
+ }
+ }
+
+ return u32RetValue;
+}
+
+/**
+ * @brief Configure FIFO threshold setting.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7.
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7.
+ * @return None
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+ */
+void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+ qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) |
+ (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) |
+ (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos);
+}
+
+/**
+ * @brief Get the actual frequency of QSPI bus clock. Only available in Master mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return Actual QSPI bus clock frequency in Hz.
+ * @details This function will calculate the actual QSPI bus clock rate according to the QSPInSEL and DIVIDER settings. Only available in Master mode.
+ */
+uint32_t QSPI_GetBusClock(QSPI_T *qspi)
+{
+ uint32_t u32Div;
+ uint32_t u32ClkSrc;
+
+ /* Get DIVIDER setting */
+ u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos;
+
+ /* Check clock source of QSPI */
+ if (qspi == QSPI0)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32ClkSrc = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if (qspi == QSPI1)
+ {
+ if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ u32ClkSrc = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+
+ /* Return QSPI bus clock rate */
+ return (u32ClkSrc / (u32Div + 1U));
+}
+
+/**
+ * @brief Enable interrupt function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt enable bit.
+ * This parameter decides which interrupts will be enabled. It is combination of:
+ * - \ref QSPI_UNIT_INT_MASK
+ * - \ref QSPI_SSACT_INT_MASK
+ * - \ref QSPI_SSINACT_INT_MASK
+ * - \ref QSPI_SLVUR_INT_MASK
+ * - \ref QSPI_SLVBE_INT_MASK
+ * - \ref QSPI_TXUF_INT_MASK
+ * - \ref QSPI_FIFO_TXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXOV_INT_MASK
+ * - \ref QSPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Enable QSPI related interrupts specified by u32Mask parameter.
+ */
+void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
+{
+ /* Enable unit transfer interrupt flag */
+ if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
+ {
+ qspi->CTL |= QSPI_CTL_UNITIEN_Msk;
+ }
+
+ /* Enable slave selection signal active interrupt flag */
+ if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
+ {
+ qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk;
+ }
+
+ /* Enable slave selection signal inactive interrupt flag */
+ if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
+ {
+ qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk;
+ }
+
+ /* Enable slave TX under run interrupt flag */
+ if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
+ {
+ qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk;
+ }
+
+ /* Enable slave bit count error interrupt flag */
+ if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
+ {
+ qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk;
+ }
+
+ /* Enable slave TX underflow interrupt flag */
+ if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
+ {
+ qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk;
+ }
+
+ /* Enable TX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
+ {
+ qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk;
+ }
+
+ /* Enable RX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
+ {
+ qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk;
+ }
+
+ /* Enable RX overrun interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
+ {
+ qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk;
+ }
+
+ /* Enable RX time-out interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
+ {
+ qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk;
+ }
+}
+
+/**
+ * @brief Disable interrupt function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * This parameter decides which interrupts will be disabled. It is combination of:
+ * - \ref QSPI_UNIT_INT_MASK
+ * - \ref QSPI_SSACT_INT_MASK
+ * - \ref QSPI_SSINACT_INT_MASK
+ * - \ref QSPI_SLVUR_INT_MASK
+ * - \ref QSPI_SLVBE_INT_MASK
+ * - \ref QSPI_TXUF_INT_MASK
+ * - \ref QSPI_FIFO_TXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXOV_INT_MASK
+ * - \ref QSPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Disable QSPI related interrupts specified by u32Mask parameter.
+ */
+void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask)
+{
+ /* Disable unit transfer interrupt flag */
+ if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
+ {
+ qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk;
+ }
+
+ /* Disable slave selection signal active interrupt flag */
+ if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
+ {
+ qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk;
+ }
+
+ /* Disable slave selection signal inactive interrupt flag */
+ if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
+ {
+ qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk;
+ }
+
+ /* Disable slave TX under run interrupt flag */
+ if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
+ {
+ qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk;
+ }
+
+ /* Disable slave bit count error interrupt flag */
+ if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
+ {
+ qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk;
+ }
+
+ /* Disable slave TX underflow interrupt flag */
+ if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
+ {
+ qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk;
+ }
+
+ /* Disable TX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
+ {
+ qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk;
+ }
+
+ /* Disable RX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
+ {
+ qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk;
+ }
+
+ /* Disable RX overrun interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
+ {
+ qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk;
+ }
+
+ /* Disable RX time-out interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
+ {
+ qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk;
+ }
+}
+
+/**
+ * @brief Get interrupt flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be read. It is combination of:
+ * - \ref QSPI_UNIT_INT_MASK
+ * - \ref QSPI_SSACT_INT_MASK
+ * - \ref QSPI_SSINACT_INT_MASK
+ * - \ref QSPI_SLVUR_INT_MASK
+ * - \ref QSPI_SLVBE_INT_MASK
+ * - \ref QSPI_TXUF_INT_MASK
+ * - \ref QSPI_FIFO_TXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXOV_INT_MASK
+ * - \ref QSPI_FIFO_RXTO_INT_MASK
+ *
+ * @return Interrupt flags of selected sources.
+ * @details Get QSPI related interrupt flags specified by u32Mask parameter.
+ */
+uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
+{
+ uint32_t u32IntFlag = 0U, u32TmpVal;
+
+ u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk;
+ /* Check unit transfer interrupt flag */
+ if((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= QSPI_UNIT_INT_MASK;
+ }
+
+ u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk;
+ /* Check slave selection signal active interrupt flag */
+ if((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= QSPI_SSACT_INT_MASK;
+ }
+
+ u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk;
+ /* Check slave selection signal inactive interrupt flag */
+ if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= QSPI_SSINACT_INT_MASK;
+ }
+
+ u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk;
+ /* Check slave TX under run interrupt flag */
+ if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= QSPI_SLVUR_INT_MASK;
+ }
+
+ u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk;
+ /* Check slave bit count error interrupt flag */
+ if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= QSPI_SLVBE_INT_MASK;
+ }
+
+ u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk;
+ /* Check slave TX underflow interrupt flag */
+ if((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= QSPI_TXUF_INT_MASK;
+ }
+
+ u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk;
+ /* Check TX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK;
+ }
+
+ u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk;
+ /* Check RX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK;
+ }
+
+ u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk;
+ /* Check RX overrun interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK;
+ }
+
+ u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk;
+ /* Check RX time-out interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK;
+ }
+
+ return u32IntFlag;
+}
+
+/**
+ * @brief Clear interrupt flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be cleared. It could be the combination of:
+ * - \ref QSPI_UNIT_INT_MASK
+ * - \ref QSPI_SSACT_INT_MASK
+ * - \ref QSPI_SSINACT_INT_MASK
+ * - \ref QSPI_SLVUR_INT_MASK
+ * - \ref QSPI_SLVBE_INT_MASK
+ * - \ref QSPI_TXUF_INT_MASK
+ * - \ref QSPI_FIFO_RXOV_INT_MASK
+ * - \ref QSPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Clear QSPI related interrupt flags specified by u32Mask parameter.
+ */
+void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask)
+{
+ if(u32Mask & QSPI_UNIT_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
+ }
+
+ if(u32Mask & QSPI_SSACT_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
+ }
+
+ if(u32Mask & QSPI_SSINACT_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
+ }
+
+ if(u32Mask & QSPI_SLVUR_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
+ }
+
+ if(u32Mask & QSPI_SLVBE_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
+ }
+
+ if(u32Mask & QSPI_TXUF_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
+ }
+
+ if(u32Mask & QSPI_FIFO_RXOV_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
+ }
+
+ if(u32Mask & QSPI_FIFO_RXTO_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
+ }
+}
+
+/**
+ * @brief Get QSPI status.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Mask The combination of all related sources.
+ * Each bit corresponds to a source.
+ * This parameter decides which flags will be read. It is combination of:
+ * - \ref QSPI_BUSY_MASK
+ * - \ref QSPI_RX_EMPTY_MASK
+ * - \ref QSPI_RX_FULL_MASK
+ * - \ref QSPI_TX_EMPTY_MASK
+ * - \ref QSPI_TX_FULL_MASK
+ * - \ref QSPI_TXRX_RESET_MASK
+ * - \ref QSPI_QSPIEN_STS_MASK
+ * - \ref QSPI_SSLINE_STS_MASK
+ *
+ * @return Flags of selected sources.
+ * @details Get QSPI related status specified by u32Mask parameter.
+ */
+uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask)
+{
+ uint32_t u32Flag = 0U, u32TmpValue;
+
+ u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk;
+ /* Check busy status */
+ if((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue))
+ {
+ u32Flag |= QSPI_BUSY_MASK;
+ }
+
+ u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk;
+ /* Check RX empty flag */
+ if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue))
+ {
+ u32Flag |= QSPI_RX_EMPTY_MASK;
+ }
+
+ u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk;
+ /* Check RX full flag */
+ if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue))
+ {
+ u32Flag |= QSPI_RX_FULL_MASK;
+ }
+
+ u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk;
+ /* Check TX empty flag */
+ if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue))
+ {
+ u32Flag |= QSPI_TX_EMPTY_MASK;
+ }
+
+ u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk;
+ /* Check TX full flag */
+ if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue))
+ {
+ u32Flag |= QSPI_TX_FULL_MASK;
+ }
+
+ u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk;
+ /* Check TX/RX reset flag */
+ if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue))
+ {
+ u32Flag |= QSPI_TXRX_RESET_MASK;
+ }
+
+ u32TmpValue = qspi->STATUS & QSPI_STATUS_QSPIENSTS_Msk;
+ /* Check QSPIEN flag */
+ if((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue))
+ {
+ u32Flag |= QSPI_QSPIEN_STS_MASK;
+ }
+
+ u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk;
+ /* Check QSPIx_SS line status */
+ if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue))
+ {
+ u32Flag |= QSPI_SSLINE_STS_MASK;
+ }
+
+ return u32Flag;
+}
+
+
+
+/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group QSPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_rtc.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_rtc.c
new file mode 100644
index 00000000000..0df0ccb4432
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_rtc.c
@@ -0,0 +1,1095 @@
+/**************************************************************************//**
+ * @file rtc.c
+ * @version V3.00
+ * @brief M480 series RTC driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @cond HIDDEN_SYMBOLS */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro, type and constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_GLOBALS
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global file scope (static) variables */
+/*---------------------------------------------------------------------------------------------------------*/
+static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay;
+static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec;
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+ @{
+*/
+
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+ @{
+*/
+
+/**
+ * @brief Initialize RTC module and start counting
+ *
+ * @param[in] sPt Specify the time property and current date and time. It includes: \n
+ * u32Year: Year value, range between 2000 ~ 2099. \n
+ * u32Month: Month value, range between 1 ~ 12. \n
+ * u32Day: Day value, range between 1 ~ 31. \n
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY] \n
+ * u32Hour: Hour value, range between 0 ~ 23. \n
+ * u32Minute: Minute value, range between 0 ~ 59. \n
+ * u32Second: Second value, range between 0 ~ 59. \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This function is used to: \n
+ * 1. Write initial key to let RTC start count. \n
+ * 2. Input parameter indicates start date/time. \n
+ * 3. User has to make sure that parameters of RTC date/time are reasonable. \n
+ * @note Null pointer for using default starting date/time.
+ */
+void RTC_Open(S_RTC_TIME_DATA_T *sPt)
+{
+ RTC->INIT = RTC_INIT_KEY;
+
+ if(RTC->INIT != RTC_INIT_ACTIVE_Msk)
+ {
+ RTC->INIT = RTC_INIT_KEY;
+ while(RTC->INIT != RTC_INIT_ACTIVE_Msk)
+ {
+ }
+ }
+
+ if(sPt == 0)
+ {
+ }
+ else
+ {
+ /* Set RTC date and time */
+ RTC_SetDateAndTime(sPt);
+ }
+}
+
+/**
+ * @brief Disable RTC Clock
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This API will disable RTC peripheral clock and stops RTC counting.
+ */
+void RTC_Close(void)
+{
+ CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
+}
+
+/**
+ * @brief Set Frequency Compensation Data
+ *
+ * @param[in] i32FrequencyX10000 Specify the RTC clock X10000, ex: 327736512 means 32773.6512.
+ *
+ * @return None
+ *
+ */
+void RTC_32KCalibration(int32_t i32FrequencyX10000)
+{
+ uint64_t u64Compensate;
+ int32_t i32RegInt,i32RegFra ;
+
+ if(!(SYS->CSERVER & 0x1))
+ {
+ u64Compensate = (uint64_t)(0x2710000000000);
+ u64Compensate = (uint64_t)(u64Compensate / (uint64_t)i32FrequencyX10000);
+
+ if(u64Compensate >= (uint64_t)0x400000)
+ {
+ u64Compensate = (uint64_t)0x3FFFFF;
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->FREQADJ = (uint32_t)u64Compensate;
+ }
+ else
+ {
+ /* Compute Integer and Fraction for RTC register*/
+ i32RegInt = (i32FrequencyX10000/10000) - 32752;
+ i32RegFra = ((((i32FrequencyX10000%10000)) * 64) + 5000) / 10000;
+
+ if(i32RegFra >= 0x40)
+ {
+ i32RegFra = 0x0;
+ i32RegInt++;
+ }
+
+ /* Judge Integer part is reasonable */
+ if ( (i32RegInt < 0) | (i32RegInt > 31) )
+ {
+ return;
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->FREQADJ = (uint32_t)((i32RegInt<<8) | i32RegFra);
+ }
+
+}
+
+/**
+ * @brief Get Current RTC Date and Time
+ *
+ * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n
+ * u32Year: Year value \n
+ * u32Month: Month value \n
+ * u32Day: Day value \n
+ * u32DayOfWeek: Day of week \n
+ * u32Hour: Hour value \n
+ * u32Minute: Minute value \n
+ * u32Second: Second value \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to get the current RTC date and time value.
+ */
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Tmp;
+
+ sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
+ sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+
+ /* Get [Date digit] data */
+ g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;
+ g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;
+ g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;
+ g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;
+ g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;
+ g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos;
+
+ /* Get [Time digit] data */
+ g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;
+ g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;
+ g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;
+ g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;
+ g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;
+ g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos;
+
+ /* Compute to 20XX year */
+ u32Tmp = (g_u32hiYear * 10ul);
+ u32Tmp += g_u32loYear;
+ sPt->u32Year = u32Tmp + RTC_YEAR2000;
+
+ /* Compute 0~12 month */
+ u32Tmp = (g_u32hiMonth * 10ul);
+ sPt->u32Month = u32Tmp + g_u32loMonth;
+
+ /* Compute 0~31 day */
+ u32Tmp = (g_u32hiDay * 10ul);
+ sPt->u32Day = u32Tmp + g_u32loDay;
+
+ /* Compute 12/24 hour */
+ if(sPt->u32TimeScale == RTC_CLOCK_12)
+ {
+ u32Tmp = (g_u32hiHour * 10ul);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
+
+ if(sPt->u32Hour >= 21ul)
+ {
+ sPt->u32AmPm = RTC_PM;
+ sPt->u32Hour -= 20ul;
+ }
+ else
+ {
+ sPt->u32AmPm = RTC_AM;
+ }
+
+ u32Tmp = (g_u32hiMin * 10ul);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10ul);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ }
+ else
+ {
+ u32Tmp = (g_u32hiHour * 10ul);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp;
+
+ u32Tmp = (g_u32hiMin * 10ul);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10ul);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ }
+}
+
+/**
+ * @brief Get RTC Alarm Date and Time
+ *
+ * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n
+ * u32Year: Year value \n
+ * u32Month: Month value \n
+ * u32Day: Day value \n
+ * u32DayOfWeek: Day of week \n
+ * u32Hour: Hour value \n
+ * u32Minute: Minute value \n
+ * u32Second: Second value \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to get the RTC alarm date and time setting.
+ */
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Tmp;
+
+ sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
+ sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+
+ /* Get alarm [Date digit] data */
+ RTC_WaitAccessEnable();
+ g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;
+ g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;
+ g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;
+ g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;
+ g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;
+ g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos;
+
+ /* Get alarm [Time digit] data */
+ RTC_WaitAccessEnable();
+ g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;
+ g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;
+ g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;
+ g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;
+ g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;
+ g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos;
+
+ /* Compute to 20XX year */
+ u32Tmp = (g_u32hiYear * 10ul);
+ u32Tmp += g_u32loYear;
+ sPt->u32Year = u32Tmp + RTC_YEAR2000;
+
+ /* Compute 0~12 month */
+ u32Tmp = (g_u32hiMonth * 10ul);
+ sPt->u32Month = u32Tmp + g_u32loMonth;
+
+ /* Compute 0~31 day */
+ u32Tmp = (g_u32hiDay * 10ul);
+ sPt->u32Day = u32Tmp + g_u32loDay;
+
+ /* Compute 12/24 hour */
+ if(sPt->u32TimeScale == RTC_CLOCK_12)
+ {
+ u32Tmp = (g_u32hiHour * 10ul);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
+
+ if(sPt->u32Hour >= 21ul)
+ {
+ sPt->u32AmPm = RTC_PM;
+ sPt->u32Hour -= 20ul;
+ }
+ else
+ {
+ sPt->u32AmPm = RTC_AM;
+ }
+
+ u32Tmp = (g_u32hiMin * 10ul);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10ul);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+
+ }
+ else
+ {
+ u32Tmp = (g_u32hiHour * 10ul);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp;
+
+ u32Tmp = (g_u32hiMin * 10ul);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10ul);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ }
+}
+
+/**
+ * @brief Update Current RTC Date and Time
+ *
+ * @param[in] sPt Specify the time property and current date and time. It includes: \n
+ * u32Year: Year value, range between 2000 ~ 2099. \n
+ * u32Month: Month value, range between 1 ~ 12. \n
+ * u32Day: Day value, range between 1 ~ 31. \n
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY] \n
+ * u32Hour: Hour value, range between 0 ~ 23. \n
+ * u32Minute: Minute value, range between 0 ~ 59. \n
+ * u32Second: Second value, range between 0 ~ 59. \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to update current date and time to RTC.
+ */
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32RegCAL, u32RegTIME;
+
+ if(sPt == 0ul)
+ {
+ }
+ else
+ {
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ if(sPt->u32TimeScale == RTC_CLOCK_12)
+ {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+ /*-------------------------------------------------------------------------------------------------*/
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ /*-------------------------------------------------------------------------------------------------*/
+ if(sPt->u32AmPm == RTC_PM)
+ {
+ sPt->u32Hour += 20ul;
+ }
+ }
+ else
+ {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ /* Set Day of the Week */
+ RTC_WaitAccessEnable();
+ RTC->WEEKDAY = sPt->u32DayOfWeek;
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Current Date and Time */
+ /*-----------------------------------------------------------------------------------------------------*/
+ u32RegCAL = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20;
+ u32RegCAL |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16);
+ u32RegCAL |= ((sPt->u32Month / 10ul) << 12);
+ u32RegCAL |= ((sPt->u32Month % 10ul) << 8);
+ u32RegCAL |= ((sPt->u32Day / 10ul) << 4);
+ u32RegCAL |= (sPt->u32Day % 10ul);
+
+ u32RegTIME = ((sPt->u32Hour / 10ul) << 20);
+ u32RegTIME |= ((sPt->u32Hour % 10ul) << 16);
+ u32RegTIME |= ((sPt->u32Minute / 10ul) << 12);
+ u32RegTIME |= ((sPt->u32Minute % 10ul) << 8);
+ u32RegTIME |= ((sPt->u32Second / 10ul) << 4);
+ u32RegTIME |= (sPt->u32Second % 10ul);
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Calender and Time Loading */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ RTC->CAL = (uint32_t)u32RegCAL;
+ RTC_WaitAccessEnable();
+ RTC->TIME = (uint32_t)u32RegTIME;
+ }
+}
+
+/**
+ * @brief Update RTC Alarm Date and Time
+ *
+ * @param[in] sPt Specify the time property and alarm date and time. It includes: \n
+ * u32Year: Year value, range between 2000 ~ 2099. \n
+ * u32Month: Month value, range between 1 ~ 12. \n
+ * u32Day: Day value, range between 1 ~ 31. \n
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY] \n
+ * u32Hour: Hour value, range between 0 ~ 23. \n
+ * u32Minute: Minute value, range between 0 ~ 59. \n
+ * u32Second: Second value, range between 0 ~ 59. \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to update alarm date and time setting to RTC.
+ */
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32RegCALM, u32RegTALM;
+
+ if(sPt == 0)
+ {
+ }
+ else
+ {
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ if(sPt->u32TimeScale == RTC_CLOCK_12)
+ {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+ /*-------------------------------------------------------------------------------------------------*/
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ /*-------------------------------------------------------------------------------------------------*/
+ if(sPt->u32AmPm == RTC_PM)
+ {
+ sPt->u32Hour += 20ul;
+ }
+ }
+ else
+ {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Alarm Date and Time */
+ /*-----------------------------------------------------------------------------------------------------*/
+ u32RegCALM = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20;
+ u32RegCALM |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16);
+ u32RegCALM |= ((sPt->u32Month / 10ul) << 12);
+ u32RegCALM |= ((sPt->u32Month % 10ul) << 8);
+ u32RegCALM |= ((sPt->u32Day / 10ul) << 4);
+ u32RegCALM |= (sPt->u32Day % 10ul);
+
+ u32RegTALM = ((sPt->u32Hour / 10ul) << 20);
+ u32RegTALM |= ((sPt->u32Hour % 10ul) << 16);
+ u32RegTALM |= ((sPt->u32Minute / 10ul) << 12);
+ u32RegTALM |= ((sPt->u32Minute % 10ul) << 8);
+ u32RegTALM |= ((sPt->u32Second / 10ul) << 4);
+ u32RegTALM |= (sPt->u32Second % 10ul);
+
+ RTC_WaitAccessEnable();
+ RTC->CALM = (uint32_t)u32RegCALM;
+ RTC_WaitAccessEnable();
+ RTC->TALM = (uint32_t)u32RegTALM;
+ }
+}
+
+/**
+ * @brief Update RTC Current Date
+ *
+ * @param[in] u32Year The year calendar digit of current RTC setting.
+ * @param[in] u32Month The month calendar digit of current RTC setting.
+ * @param[in] u32Day The day calendar digit of current RTC setting.
+ * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY]
+ *
+ * @return None
+ *
+ * @details This API is used to update current date to RTC.
+ */
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
+{
+ uint32_t u32RegCAL;
+
+ u32RegCAL = ((u32Year - RTC_YEAR2000) / 10ul) << 20;
+ u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10ul) << 16);
+ u32RegCAL |= ((u32Month / 10ul) << 12);
+ u32RegCAL |= ((u32Month % 10ul) << 8);
+ u32RegCAL |= ((u32Day / 10ul) << 4);
+ u32RegCAL |= (u32Day % 10ul);
+
+ /* Set Day of the Week */
+ RTC_WaitAccessEnable();
+ RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
+
+ /* Set RTC Calender Loading */
+ RTC_WaitAccessEnable();
+ RTC->CAL = (uint32_t)u32RegCAL;
+}
+
+/**
+ * @brief Update RTC Current Time
+ *
+ * @param[in] u32Hour The hour time digit of current RTC setting.
+ * @param[in] u32Minute The minute time digit of current RTC setting.
+ * @param[in] u32Second The second time digit of current RTC setting.
+ * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+ * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+ *
+ * @return None
+ *
+ * @details This API is used to update current time to RTC.
+ */
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+ uint32_t u32RegTIME;
+
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
+ {
+ u32Hour += 20ul;
+ }
+
+ u32RegTIME = ((u32Hour / 10ul) << 20);
+ u32RegTIME |= ((u32Hour % 10ul) << 16);
+ u32RegTIME |= ((u32Minute / 10ul) << 12);
+ u32RegTIME |= ((u32Minute % 10ul) << 8);
+ u32RegTIME |= ((u32Second / 10ul) << 4);
+ u32RegTIME |= (u32Second % 10ul);
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ if(u32TimeMode == RTC_CLOCK_12)
+ {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+ }
+ else
+ {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->TIME = (uint32_t)u32RegTIME;
+}
+
+/**
+ * @brief Update RTC Alarm Date
+ *
+ * @param[in] u32Year The year calendar digit of RTC alarm setting.
+ * @param[in] u32Month The month calendar digit of RTC alarm setting.
+ * @param[in] u32Day The day calendar digit of RTC alarm setting.
+ *
+ * @return None
+ *
+ * @details This API is used to update alarm date setting to RTC.
+ */
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
+{
+ uint32_t u32RegCALM;
+
+ u32RegCALM = ((u32Year - RTC_YEAR2000) / 10ul) << 20;
+ u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10ul) << 16);
+ u32RegCALM |= ((u32Month / 10ul) << 12);
+ u32RegCALM |= ((u32Month % 10ul) << 8);
+ u32RegCALM |= ((u32Day / 10ul) << 4);
+ u32RegCALM |= (u32Day % 10ul);
+
+ RTC_WaitAccessEnable();
+
+ /* Set RTC Alarm Date */
+ RTC->CALM = (uint32_t)u32RegCALM;
+}
+
+/**
+ * @brief Update RTC Alarm Time
+ *
+ * @param[in] u32Hour The hour time digit of RTC alarm setting.
+ * @param[in] u32Minute The minute time digit of RTC alarm setting.
+ * @param[in] u32Second The second time digit of RTC alarm setting.
+ * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+ * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+ *
+ * @return None
+ *
+ * @details This API is used to update alarm time setting to RTC.
+ */
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+ uint32_t u32RegTALM;
+
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
+ {
+ u32Hour += 20ul;
+ }
+
+ u32RegTALM = ((u32Hour / 10ul) << 20);
+ u32RegTALM |= ((u32Hour % 10ul) << 16);
+ u32RegTALM |= ((u32Minute / 10ul) << 12);
+ u32RegTALM |= ((u32Minute % 10ul) << 8);
+ u32RegTALM |= ((u32Second / 10ul) << 4);
+ u32RegTALM |= (u32Second % 10ul);
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ if(u32TimeMode == RTC_CLOCK_12)
+ {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+ }
+ else
+ {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ /* Set RTC Alarm Time */
+ RTC_WaitAccessEnable();
+ RTC->TALM = (uint32_t)u32RegTALM;
+}
+
+/**
+ * @brief Set RTC Alarm Date Mask Function
+ *
+ * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled.
+ * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled.
+ * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled.
+ * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled.
+ * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled.
+ * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled.
+ *
+ * @return None
+ *
+ * @details This API is used to enable or disable RTC alarm date mask function.
+ */
+void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk)
+{
+ RTC_WaitAccessEnable();
+ RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) |
+ ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) |
+ ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) |
+ ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) |
+ ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) |
+ ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos);
+}
+
+/**
+ * @brief Set RTC Alarm Time Mask Function
+ *
+ * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled.
+ * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled.
+ * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled.
+ * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled.
+ * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled.
+ * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled.
+ *
+ * @return None
+ *
+ * @details This API is used to enable or disable RTC alarm time mask function.
+ */
+void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk)
+{
+ RTC_WaitAccessEnable();
+ RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) |
+ ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) |
+ ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) |
+ ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) |
+ ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) |
+ ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos);
+}
+
+/**
+ * @brief Get Day of the Week
+ *
+ * @param None
+ *
+ * @retval 0 Sunday
+ * @retval 1 Monday
+ * @retval 2 Tuesday
+ * @retval 3 Wednesday
+ * @retval 4 Thursday
+ * @retval 5 Friday
+ * @retval 6 Saturday
+ *
+ * @details This API is used to get day of the week of current RTC date.
+ */
+uint32_t RTC_GetDayOfWeek(void)
+{
+ return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);
+}
+
+/**
+ * @brief Set RTC Tick Period Time
+ *
+ * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n
+ * It consists of:
+ * - \ref RTC_TICK_1_SEC : Time tick is 1 second
+ * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second
+ * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second
+ * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second
+ * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second
+ * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second
+ * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second
+ * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second
+ *
+ * @return None
+ *
+ * @details This API is used to set RTC tick period time for each tick interrupt.
+ */
+void RTC_SetTickPeriod(uint32_t u32TickSelection)
+{
+ RTC_WaitAccessEnable();
+
+ RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection;
+}
+
+/**
+ * @brief Enable RTC Interrupt
+ *
+ * @param[in] u32IntFlagMask Specify the interrupt source. It consists of:
+ * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt
+ * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt
+ * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt
+ *
+ * @return None
+ *
+ * @details This API is used to enable the specify RTC interrupt function.
+ */
+void RTC_EnableInt(uint32_t u32IntFlagMask)
+{
+ RTC_WaitAccessEnable();
+ RTC->INTEN |= u32IntFlagMask;
+}
+
+/**
+ * @brief Disable RTC Interrupt
+ *
+ * @param[in] u32IntFlagMask Specify the interrupt source. It consists of:
+ * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt
+ * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt
+ * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt
+ *
+ * @return None
+ *
+ * @details This API is used to disable the specify RTC interrupt function.
+ */
+void RTC_DisableInt(uint32_t u32IntFlagMask)
+{
+ RTC_WaitAccessEnable();
+ RTC->INTEN &= ~u32IntFlagMask;
+ RTC_WaitAccessEnable();
+ RTC->INTSTS = u32IntFlagMask;
+}
+
+/**
+ * @brief Enable Spare Registers Access
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This API is used to enable the spare registers 0~19 can be accessed.
+ */
+void RTC_EnableSpareAccess(void)
+{
+ RTC_WaitAccessEnable();
+
+ RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
+}
+
+/**
+ * @brief Disable Spare Register
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This API is used to disable the spare register 0~19 cannot be accessed.
+ */
+void RTC_DisableSpareRegister(void)
+{
+ RTC_WaitAccessEnable();
+
+ RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
+}
+
+/**
+ * @brief Static Tamper Detect
+ *
+ * @param[in] u32TamperSelect Tamper pin select. Possible options are
+ * - \ref RTC_TAMPER5_SELECT
+ * - \ref RTC_TAMPER4_SELECT
+ * - \ref RTC_TAMPER3_SELECT
+ * - \ref RTC_TAMPER2_SELECT
+ * - \ref RTC_TAMPER1_SELECT
+ * - \ref RTC_TAMPER0_SELECT
+ *
+ * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are
+ * - \ref RTC_TAMPER_HIGH_LEVEL_DETECT
+ * - \ref RTC_TAMPER_LOW_LEVEL_DETECT
+ *
+ * @param[in] u32DebounceEn Tamper pin de-bounce enable
+ * - \ref RTC_TAMPER_DEBOUNCE_ENABLE
+ * - \ref RTC_TAMPER_DEBOUNCE_DISABLE
+ *
+ * @return None
+ *
+ * @details This API is used to enable the tamper pin detect function with specify trigger condition.
+ */
+void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn)
+{
+ uint32_t i;
+ uint32_t u32Reg;
+ uint32_t u32TmpReg;
+
+ RTC_WaitAccessEnable();
+ u32Reg = RTC->TAMPCTL;
+
+ u32TmpReg = ( RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) |
+ (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos) );
+
+ for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++)
+ {
+ if(u32TamperSelect & (0x1ul << i))
+ {
+ u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk|RTC_TAMPCTL_TAMP0LV_Msk|RTC_TAMPCTL_TAMP0DBEN_Msk) << (i*4ul));
+ u32Reg |= (u32TmpReg << (i*4ul));
+ }
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->TAMPCTL = u32Reg;
+
+}
+
+/**
+ * @brief Static Tamper Disable
+ *
+ * @param[in] u32TamperSelect Tamper pin select. Possible options are
+ * - \ref RTC_TAMPER5_SELECT
+ * - \ref RTC_TAMPER4_SELECT
+ * - \ref RTC_TAMPER3_SELECT
+ * - \ref RTC_TAMPER2_SELECT
+ * - \ref RTC_TAMPER1_SELECT
+ * - \ref RTC_TAMPER0_SELECT
+ *
+ * @return None
+ *
+ * @details This API is used to disable the static tamper pin detect.
+ */
+void RTC_StaticTamperDisable(uint32_t u32TamperSelect)
+{
+ uint32_t i;
+ uint32_t u32Reg;
+ uint32_t u32TmpReg;
+
+ RTC_WaitAccessEnable();
+ u32Reg = RTC->TAMPCTL;
+
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk);
+
+ for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++)
+ {
+ if(u32TamperSelect & (0x1ul << i))
+ {
+ u32Reg &= ~(u32TmpReg << (i*4ul));
+ }
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->TAMPCTL = u32Reg;
+}
+
+/**
+ * @brief Dynamic Tamper Detect
+ *
+ * @param[in] u32PairSel Tamper pin detection enable. Possible options are
+ * - \ref RTC_PAIR0_SELECT
+ * - \ref RTC_PAIR1_SELECT
+ * - \ref RTC_PAIR2_SELECT
+ *
+ * @param[in] u32DebounceEn Tamper pin de-bounce enable
+ * - \ref RTC_TAMPER_DEBOUNCE_ENABLE
+ * - \ref RTC_TAMPER_DEBOUNCE_DISABLE
+ *
+ * @param[in] u32Pair1Source Dynamic Pair 1 Input Source Select
+ * 0: Pair 1 source select tamper 2
+ * 1: Pair 1 source select tamper 0
+ *
+ * @param[in] u32Pair2Source Dynamic Pair 2 Input Source Select
+ * 0: Pair 2 source select tamper 4
+ * 1: Pair 2 source select tamper 0
+ *
+ * @return None
+ *
+ * @details This API is used to enable the dynamic tamper.
+ */
+void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source)
+{
+ uint32_t i;
+ uint32_t u32Reg;
+ uint32_t u32TmpReg;
+ uint32_t u32Tamper2Debounce, u32Tamper4Debounce;
+
+ RTC_WaitAccessEnable();
+ u32Reg = RTC->TAMPCTL;
+
+ u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk;
+ u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk;
+
+ u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk |
+ RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk);
+ u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk);
+ u32Reg |= ((u32Pair1Source & 0x1ul) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1ul) << RTC_TAMPCTL_DYN2ISS_Pos);
+
+ if(u32DebounceEn)
+ {
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk |
+ RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+ }
+ else
+ {
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+ }
+
+ for(i = 0ul; i < MAX_PAIR_NUM; i++)
+ {
+ if(u32PairSel & (0x1ul << i))
+ {
+ u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i*8ul));
+ u32Reg |= (u32TmpReg << (i*8ul));
+ }
+ }
+
+ if((u32Pair1Source) && (u32PairSel & RTC_PAIR1_SELECT))
+ {
+ u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk;
+ u32Reg |= u32Tamper2Debounce;
+ }
+
+ if((u32Pair2Source) && (u32PairSel & RTC_PAIR2_SELECT))
+ {
+ u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk;
+ u32Reg |= u32Tamper4Debounce;
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->TAMPCTL = u32Reg;
+}
+
+/**
+ * @brief Dynamic Tamper Disable
+ *
+ * @param[in] u32PairSel Tamper pin detection enable. Possible options are
+ * - \ref RTC_PAIR0_SELECT
+ * - \ref RTC_PAIR1_SELECT
+ * - \ref RTC_PAIR2_SELECT
+ *
+ * @return None
+ *
+ * @details This API is used to disable the dynamic tamper.
+ */
+void RTC_DynamicTamperDisable(uint32_t u32PairSel)
+{
+ uint32_t i;
+ uint32_t u32Reg;
+ uint32_t u32TmpReg;
+ uint32_t u32Tamper2En = 0ul, u32Tamper4En = 0ul;
+
+ RTC_WaitAccessEnable();
+ u32Reg = RTC->TAMPCTL;
+
+ if((u32Reg & RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & RTC_PAIR1_SELECT))
+ {
+ u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk;
+ }
+
+ if((u32Reg & RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & RTC_PAIR2_SELECT))
+ {
+ u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk;
+ }
+
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+
+ for(i = 0ul; i < MAX_PAIR_NUM; i++)
+ {
+ if(u32PairSel & (0x1ul << i))
+ {
+ u32Reg &= ~(u32TmpReg << ((i*8ul)));
+ }
+ }
+
+ u32Reg |= (u32Tamper2En | u32Tamper4En);
+
+ RTC_WaitAccessEnable();
+ RTC->TAMPCTL = u32Reg;
+}
+
+/**
+ * @brief Config dynamic tamper
+ *
+ * @param[in] u32ChangeRate The dynamic tamper output change rate
+ * - \ref RTC_2POW10_CLK
+ * - \ref RTC_2POW11_CLK
+ * - \ref RTC_2POW12_CLK
+ * - \ref RTC_2POW13_CLK
+ * - \ref RTC_2POW14_CLK
+ * - \ref RTC_2POW15_CLK
+ * - \ref RTC_2POW16_CLK
+ * - \ref RTC_2POW17_CLK
+ *
+ * @param[in] u32SeedReload Reload new seed or not
+ * 0: not reload new seed
+ * 1: reload new seed
+ *
+ * @param[in] u32RefPattern Reference pattern
+ * - \ref REF_RANDOM_PATTERN
+ * - \ref REF_PREVIOUS_PATTERN
+ * - \ref REF_SEED
+ *
+ * @param[in] u32Seed Seed Value (0x0 ~ 0xFFFFFFFF)
+ *
+ * @return None
+ *
+ * @details This API is used to config dynamic tamper setting.
+ */
+void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed)
+{
+ uint32_t u32Reg;
+ RTC_WaitAccessEnable();
+ u32Reg = RTC->TAMPCTL;
+
+ u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk);
+
+ u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1ul) << RTC_TAMPCTL_SEEDRLD_Pos) |
+ ((u32RefPattern & 0x3ul) << RTC_TAMPCTL_DYNSRC_Pos);
+
+ RTC_WaitAccessEnable();
+ RTC->TAMPSEED = u32Seed; /* need set seed value before re-load seed */
+ RTC_WaitAccessEnable();
+ RTC->TAMPCTL = u32Reg;
+}
+
+/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group RTC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sc.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sc.c
new file mode 100644
index 00000000000..785b86cd4b2
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sc.c
@@ -0,0 +1,400 @@
+/**************************************************************************//**
+ * @file sc.c
+ * @version V3.00
+ * @brief M480 Smartcard(SC) driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */
+/** @cond HIDDEN_SYMBOLS */
+static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL};
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SC_Driver SC Driver
+ @{
+*/
+
+/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function indicates specified smartcard slot status
+ * @param[in] sc Base address of smartcard module
+ * @return Card insert status
+ * @retval TRUE Card insert
+ * @retval FALSE Card remove
+ */
+uint32_t SC_IsCardInserted(SC_T *sc)
+{
+ uint32_t ret;
+ /* put conditions into two variable to remove IAR compilation warning */
+ uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos);
+ uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos);
+
+ if((sc == SC0) && (u32CardStateIgnore[0] == 1UL))
+ {
+ ret = (uint32_t)TRUE;
+ }
+ else if((sc == SC1) && (u32CardStateIgnore[1] == 1UL))
+ {
+ ret = (uint32_t)TRUE;
+ }
+ else if((sc == SC2) && (u32CardStateIgnore[2] == 1UL))
+ {
+ ret = (uint32_t)TRUE;
+ }
+ else if(cond1 != cond2)
+ {
+ ret = (uint32_t)FALSE;
+ }
+ else
+ {
+ ret = (uint32_t)TRUE;
+ }
+ return ret;
+}
+
+/**
+ * @brief This function reset both transmit and receive FIFO of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @return None
+ */
+void SC_ClearFIFO(SC_T *sc)
+{
+ while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)
+ {
+ ;
+ }
+ sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk);
+}
+
+/**
+ * @brief This function disable specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @return None
+ */
+void SC_Close(SC_T *sc)
+{
+ sc->INTEN = 0UL;
+ while(sc->PINCTL & SC_PINCTL_SYNC_Msk)
+ {
+ ;
+ }
+ sc->PINCTL = 0UL;
+ sc->ALTCTL = 0UL;
+ while(sc->CTL & SC_CTL_SYNC_Msk)
+ {
+ ;
+ }
+ sc->CTL = 0UL;
+}
+
+/**
+ * @brief This function initialized smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32CardDet Card detect polarity, select the CD pin state which indicates card absent. Could be
+ * -\ref SC_PIN_STATE_HIGH
+ * -\ref SC_PIN_STATE_LOW
+ * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present
+ * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be
+ * -\ref SC_PIN_STATE_HIGH
+ * -\ref SC_PIN_STATE_LOW
+ * @return None
+ */
+void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR)
+{
+ uint32_t u32Reg = 0UL, u32Intf;
+
+ if(sc == SC0)
+ {
+ u32Intf = 0UL;
+ }
+ else if(sc == SC1)
+ {
+ u32Intf = 1UL;
+ }
+ else
+ {
+ u32Intf = 2UL;
+ }
+
+ if(u32CardDet != SC_PIN_STATE_IGNORE)
+ {
+ u32Reg = u32CardDet ? 0UL: SC_CTL_CDLV_Msk;
+ u32CardStateIgnore[u32Intf] = 0UL;
+ }
+ else
+ {
+ u32CardStateIgnore[u32Intf] = 1UL;
+ }
+ sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk;
+ while(sc->CTL & SC_CTL_SYNC_Msk)
+ {
+ ;
+ }
+ sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg;
+}
+
+/**
+ * @brief This function reset specified smartcard module to its default state for activate smartcard
+ * @param[in] sc Base address of smartcard module
+ * @return None
+ */
+void SC_ResetReader(SC_T *sc)
+{
+ uint32_t u32Intf;
+
+ if(sc == SC0)
+ {
+ u32Intf = 0UL;
+ }
+ else if(sc == SC1)
+ {
+ u32Intf = 1UL;
+ }
+ else
+ {
+ u32Intf = 2UL;
+ }
+
+ /* Reset FIFO, enable auto de-activation while card removal */
+ sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk);
+ /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */
+ while(sc->CTL & SC_CTL_SYNC_Msk)
+ {
+ ;
+ }
+ sc->CTL &= ~(SC_CTL_RXTRGLV_Msk |
+ SC_CTL_CDDBSEL_Msk |
+ SC_CTL_TXRTY_Msk |
+ SC_CTL_TXRTYEN_Msk |
+ SC_CTL_RXRTY_Msk |
+ SC_CTL_RXRTYEN_Msk);
+ while(sc->CTL & SC_CTL_SYNC_Msk)
+ {
+ ;
+ }
+ /* Enable auto convention, and all three smartcard internal timers */
+ sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk;
+ /* Disable Rx timeout */
+ sc->RXTOUT = 0UL;
+ /* 372 clocks per ETU by default */
+ sc->ETUCTL= 371UL;
+
+
+ /* Enable necessary interrupt for smartcard operation */
+ if(u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */
+ {
+ sc->INTEN = (SC_INTEN_RDAIEN_Msk |
+ SC_INTEN_TERRIEN_Msk |
+ SC_INTEN_TMR0IEN_Msk |
+ SC_INTEN_TMR1IEN_Msk |
+ SC_INTEN_TMR2IEN_Msk |
+ SC_INTEN_BGTIEN_Msk |
+ SC_INTEN_ACERRIEN_Msk);
+ }
+ else
+ {
+ sc->INTEN = (SC_INTEN_RDAIEN_Msk |
+ SC_INTEN_TERRIEN_Msk |
+ SC_INTEN_TMR0IEN_Msk |
+ SC_INTEN_TMR1IEN_Msk |
+ SC_INTEN_TMR2IEN_Msk |
+ SC_INTEN_BGTIEN_Msk |
+ SC_INTEN_CDIEN_Msk |
+ SC_INTEN_ACERRIEN_Msk);
+ }
+ return;
+}
+
+/**
+ * @brief This function block guard time (BGT) of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32
+ * @return None
+ */
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT)
+{
+ sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos);
+}
+
+/**
+ * @brief This function character guard time (CGT) of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267
+ * @return None
+ */
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT)
+{
+ u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11UL: 12UL;
+ sc->EGT = u32CGT;
+}
+
+/**
+ * @brief This function stop all smartcard timer of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @return None
+ * @note This function stop the timers within smartcard module, \b not timer module
+ */
+void SC_StopAllTimer(SC_T *sc)
+{
+ while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)
+ {
+ ;
+ }
+ sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk);
+}
+
+/**
+ * @brief This function configure and start a smartcard timer of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32TimerNum Timer to start. Valid values are 0, 1, 2.
+ * @param[in] u32Mode Timer operating mode, valid values are:
+ * - \ref SC_TMR_MODE_0
+ * - \ref SC_TMR_MODE_1
+ * - \ref SC_TMR_MODE_2
+ * - \ref SC_TMR_MODE_3
+ * - \ref SC_TMR_MODE_4
+ * - \ref SC_TMR_MODE_5
+ * - \ref SC_TMR_MODE_6
+ * - \ref SC_TMR_MODE_7
+ * - \ref SC_TMR_MODE_8
+ * - \ref SC_TMR_MODE_F
+ * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs.
+ * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs
+ * @return None
+ * @note This function start the timer within smartcard module, \b not timer module
+ * @note Depend on the timer operating mode, timer may not start counting immediately
+ */
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount)
+{
+ uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL));
+ while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)
+ {
+ ;
+ }
+ if(u32TimerNum == 0UL)
+ {
+ while(sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk)
+ {
+ ;
+ }
+ sc->TMRCTL0 = reg;
+ sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk;
+ }
+ else if(u32TimerNum == 1UL)
+ {
+ while(sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk)
+ {
+ ;
+ }
+ sc->TMRCTL1 = reg;
+ sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk;
+ }
+ else /* timer 2 */
+ {
+ while(sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk)
+ {
+ ;
+ }
+ sc->TMRCTL2 = reg;
+ sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk;
+ }
+}
+
+/**
+ * @brief This function stop a smartcard timer of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32TimerNum Timer to stop. Valid values are 0, 1, 2.
+ * @return None
+ * @note This function stop the timer within smartcard module, \b not timer module
+ */
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum)
+{
+ while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)
+ {
+ ;
+ }
+ if(u32TimerNum == 0UL)
+ {
+ sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk;
+ }
+ else if(u32TimerNum == 1UL)
+ {
+ sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk;
+ }
+ else /* timer 2 */
+ {
+ sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk;
+ }
+}
+
+/**
+ * @brief This function gets smartcard clock frequency.
+ * @param[in] sc Base address of smartcard module
+ * @return Smartcard frequency in kHz
+ */
+uint32_t SC_GetInterfaceClock(SC_T *sc)
+{
+ uint32_t u32ClkSrc, u32Num, u32Clk;
+
+ if(sc == SC0)
+ {
+ u32Num = 0UL;
+ }
+ else if(sc == SC1)
+ {
+ u32Num = 1UL;
+ }
+ else
+ {
+ u32Num = 2UL;
+ }
+
+ u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk;
+
+ /* Get smartcard module clock */
+ if(u32ClkSrc == 0UL)
+ {
+ u32Clk = __HXT;
+ }
+ else if(u32ClkSrc == 1UL)
+ {
+ u32Clk = CLK_GetPLLClockFreq();
+ }
+ else if(u32ClkSrc == 2UL)
+ {
+ if(u32Num == 1UL)
+ {
+ u32Clk = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32Clk = CLK_GetPCLK0Freq();
+ }
+ }
+ else
+ {
+ u32Clk = __HIRC;
+ }
+
+ u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL) * 1000UL;
+ return u32Clk;
+}
+
+/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_scuart.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_scuart.c
new file mode 100644
index 00000000000..7fa2f5a38e5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_scuart.c
@@ -0,0 +1,242 @@
+/**************************************************************************//**
+ * @file scuart.c
+ * @version V3.00
+ * @brief M480 Smartcard UART mode (SCUART) driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+static uint32_t SCUART_GetClock(SC_T *sc);
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SCUART_Driver SCUART Driver
+ @{
+*/
+
+
+/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+ @{
+*/
+
+/**
+ * @brief The function is used to disable smartcard interface UART mode.
+ * @param sc The base address of smartcard module.
+ * @return None
+ */
+void SCUART_Close(SC_T* sc)
+{
+ sc->INTEN = 0UL;
+ sc->UARTCTL = 0UL;
+ sc->CTL = 0UL;
+
+}
+/** @cond HIDDEN_SYMBOLS */
+/**
+ * @brief This function returns module clock of specified SC interface
+ * @param[in] sc The base address of smartcard module.
+ * @return Module clock of specified SC interface
+ */
+static uint32_t SCUART_GetClock(SC_T *sc)
+{
+ uint32_t u32ClkSrc, u32Num, u32Clk;
+
+ if(sc == SC0)
+ {
+ u32Num = 0UL;
+ }
+ else if(sc == SC1)
+ {
+ u32Num = 1UL;
+ }
+ else
+ {
+ u32Num = 2UL;
+ }
+
+ u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk;
+
+ /* Get smartcard module clock */
+ if(u32ClkSrc == 0UL)
+ {
+ u32Clk = __HXT;
+ }
+ else if(u32ClkSrc == 1UL)
+ {
+ u32Clk = CLK_GetPLLClockFreq();
+ }
+ else if(u32ClkSrc == 2UL)
+ {
+ if(u32Num == 1UL)
+ {
+ u32Clk = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32Clk = CLK_GetPCLK0Freq();
+ }
+ }
+ else
+ {
+ u32Clk = __HIRC;
+ }
+
+ u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL);
+
+
+ return u32Clk;
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+ * @brief This function use to enable smartcard module UART mode and set baudrate.
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] u32baudrate Target baudrate of smartcard module.
+ * @return Actual baudrate of smartcard mode
+ * @details This function configures character width to 8 bits, 1 stop bit, and no parity.
+ * And can use \ref SCUART_SetLineConfig function to update these settings
+ * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled
+ * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1
+ * register. Since the baudrate divider is 12-bit wide and must be larger than 4,
+ * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to
+ * 4096. Otherwise this function cannot configure SCUART to work with target baudrate.
+ */
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate)
+{
+ uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+ /* Calculate divider for target baudrate */
+ u32Div = (u32Clk + (u32baudrate >> 1) - 1UL) / u32baudrate - 1UL;
+
+ /* Enable smartcard interface and stop bit = 1 */
+ sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk;
+ /* Enable UART mode, disable parity and 8 bit per character */
+ sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk;
+ sc->ETUCTL = u32Div;
+
+ return(u32Clk / (u32Div + 1UL));
+}
+
+/**
+ * @brief The function is used to read Rx data from RX FIFO.
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] pu8RxBuf The buffer to store receive the data
+ * @param[in] u32ReadBytes Target number of characters to receive
+ * @return Actual character number reads to buffer
+ * @note This function does not block and return immediately if there's no data available
+ */
+uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+ uint32_t u32Count;
+
+ for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++)
+ {
+ if(SCUART_GET_RX_EMPTY(sc)) /* no data available */
+ {
+ break;
+ }
+ pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); /* get data from FIFO */
+ }
+
+ return u32Count;
+}
+
+/**
+ * @brief This function use to configure smartcard UART mode line setting.
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change.
+ * @param[in] u32DataWidth The data length, could be
+ * - \ref SCUART_CHAR_LEN_5
+ * - \ref SCUART_CHAR_LEN_6
+ * - \ref SCUART_CHAR_LEN_7
+ * - \ref SCUART_CHAR_LEN_8
+ * @param[in] u32Parity The parity setting, could be
+ * - \ref SCUART_PARITY_NONE
+ * - \ref SCUART_PARITY_ODD
+ * - \ref SCUART_PARITY_EVEN
+ * @param[in] u32StopBits The stop bit length, could be
+ * - \ref SCUART_STOP_BIT_1
+ * - \ref SCUART_STOP_BIT_2
+ * @return Actual baudrate of smartcard
+ * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled
+ * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1
+ * register. Since the baudrate divider is 12-bit wide and must be larger than 4,
+ * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to
+ * 4096. Otherwise this function cannot configure SCUART to work with target baudrate.
+ */
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits)
+{
+
+ uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+ if(u32Baudrate == 0UL) /* keep original baudrate setting */
+ {
+ u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk;
+ }
+ else
+ {
+ /* Calculate divider for target baudrate */
+ u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL)/ u32Baudrate - 1UL;
+ sc->ETUCTL = u32Div;
+ }
+ /* Set stop bit */
+ sc->CTL = u32StopBits | SC_CTL_SCEN_Msk;
+ /* Set character width and parity */
+ sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk;
+
+ return(u32Clk / (u32Div + 1UL));
+}
+
+/**
+ * @brief This function use to set receive timeout count.
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF,
+ * set this value to 0 will disable timeout counter
+ * @return None
+ * @details The time-out counter resets and starts counting whenever the RX buffer received a
+ * new data word. Once the counter decrease to 1 and no new data is received or CPU
+ * does not read any data from FIFO, a receiver time-out interrupt will be generated.
+ */
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC)
+{
+ sc->RXTOUT= u32TOC;
+}
+
+
+/**
+ * @brief This function is to write data into transmit FIFO to send data out.
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.
+ * @param[in] u32WriteBytes Number of data to send.
+ * @return None
+ * @note This function blocks until all data write into FIFO
+ */
+void SCUART_Write(SC_T* sc,uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+ uint32_t u32Count;
+
+ for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++)
+ {
+ /* Wait 'til FIFO not full */
+ while(SCUART_GET_TX_FULL(sc))
+ {
+ ;
+ }
+ /* Write 1 byte to FIFO */
+ sc->DAT = pu8TxBuf[u32Count];
+ }
+}
+
+
+/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SCUART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sdh.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sdh.c
new file mode 100644
index 00000000000..dbb323b3890
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sdh.c
@@ -0,0 +1,1275 @@
+/**************************************************************************//**
+ * @file SDH.c
+ * @version V1.00
+ * @brief M480 SDH driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include
+#include
+#include
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SDH_Driver SDH Driver
+ @{
+*/
+
+
+/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions
+ @{
+*/
+#define SDH_BLOCK_SIZE 512ul
+
+/** @cond HIDDEN_SYMBOLS */
+
+/* global variables */
+/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */
+/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */
+/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */
+
+static uint32_t _SDH0_ReferenceClock, _SDH1_ReferenceClock;
+
+#ifdef __ICCARM__
+#pragma data_alignment = 4
+static uint8_t _SDH0_ucSDHCBuffer[512];
+static uint8_t _SDH1_ucSDHCBuffer[512];
+#else
+static uint8_t _SDH0_ucSDHCBuffer[512] __attribute__((aligned(4)));
+static uint8_t _SDH1_ucSDHCBuffer[512] __attribute__((aligned(4)));
+#endif
+
+SDH_INFO_T SD0, SD1;
+
+void SDH_CheckRB(SDH_T *sdh)
+{
+ while(1)
+ {
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+ while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+ {
+ }
+ if ((sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk) == SDH_INTSTS_DAT0STS_Msk)
+ {
+ break;
+ }
+ }
+}
+
+
+uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg)
+{
+ volatile uint32_t buf, val = 0ul;
+ SDH_INFO_T *pSD;
+
+ if (sdh == SDH0)
+ {
+ pSD = &SD0;
+ }
+ else
+ {
+ pSD = &SD1;
+ }
+
+ sdh->CMDARG = uArg;
+ buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)|(SDH_CTL_COEN_Msk);
+ sdh->CTL = buf;
+
+ while ((sdh->CTL & SDH_CTL_COEN_Msk) == SDH_CTL_COEN_Msk)
+ {
+ if (pSD->IsCardInsert == 0ul)
+ {
+ val = SDH_NO_SD_CARD;
+ }
+ }
+ return val;
+}
+
+
+uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t ntickCount)
+{
+ volatile uint32_t buf;
+ SDH_INFO_T *pSD;
+
+ if (sdh == SDH0)
+ {
+ pSD = &SD0;
+ }
+ else
+ {
+ pSD = &SD1;
+ }
+
+ sdh->CMDARG = uArg;
+ buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk);
+ sdh->CTL = buf;
+
+ if (ntickCount > 0ul)
+ {
+ while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk)
+ {
+ if(ntickCount-- == 0ul)
+ {
+ sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */
+ return 2ul;
+ }
+ if (pSD->IsCardInsert == FALSE)
+ {
+ return SDH_NO_SD_CARD;
+ }
+ }
+ }
+ else
+ {
+ while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk)
+ {
+ if (pSD->IsCardInsert == FALSE)
+ {
+ return SDH_NO_SD_CARD;
+ }
+ }
+ }
+
+ if (pSD->R7Flag)
+ {
+ uint32_t tmp0 = 0ul, tmp1= 0ul;
+ tmp1 = sdh->RESP1 & 0xfful;
+ tmp0 = sdh->RESP0 & 0xful;
+ if ((tmp1 != 0x55ul) && (tmp0 != 0x01ul))
+ {
+ pSD->R7Flag = 0ul;
+ return SDH_CMD8_ERROR;
+ }
+ }
+
+ if (!pSD->R3Flag)
+ {
+ if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) /* check CRC7 */
+ {
+ return Successful;
+ }
+ else
+ {
+ return SDH_CRC7_ERROR;
+ }
+ }
+ else
+ {
+ /* ignore CRC error for R3 case */
+ pSD->R3Flag = 0ul;
+ sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+ return Successful;
+ }
+}
+
+
+uint32_t SDH_Swap32(uint32_t val)
+{
+ uint32_t buf;
+
+ buf = val;
+ val <<= 24;
+ val |= (buf<<8) & 0xff0000ul;
+ val |= (buf>>8) & 0xff00ul;
+ val |= (buf>>24)& 0xfful;
+ return val;
+}
+
+/* Get 16 bytes CID or CSD */
+uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t puR2ptr[])
+{
+ uint32_t i, buf;
+ uint32_t tmpBuf[5];
+ SDH_INFO_T *pSD;
+
+ if (sdh == SDH0)
+ {
+ pSD = &SD0;
+ }
+ else
+ {
+ pSD = &SD1;
+ }
+
+ sdh->CMDARG = uArg;
+ buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk);
+ sdh->CTL = buf;
+
+ while ((sdh->CTL & SDH_CTL_R2EN_Msk) == SDH_CTL_R2EN_Msk)
+ {
+ if (pSD->IsCardInsert == FALSE)
+ {
+ return SDH_NO_SD_CARD;
+ }
+ }
+
+ if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk)
+ {
+ for (i=0ul; i<5ul; i++)
+ {
+ tmpBuf[i] = SDH_Swap32(sdh->FB[i]);
+ }
+ for (i=0ul; i<4ul; i++)
+ {
+ puR2ptr[i] = ((tmpBuf[i] & 0x00fffffful)<<8) | ((tmpBuf[i+1ul] & 0xff000000ul)>>24);
+ }
+ }
+ else
+ {
+ return SDH_CRC7_ERROR;
+ }
+ return Successful;
+}
+
+
+uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg)
+{
+ volatile uint32_t buf;
+ SDH_INFO_T *pSD;
+
+ if (sdh == SDH0)
+ {
+ pSD = &SD0;
+ }
+ else
+ {
+ pSD = &SD1;
+ }
+
+ sdh->CMDARG = uArg;
+ buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)|
+ (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+
+ sdh->CTL = buf;
+
+ while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk)
+ {
+ if (pSD->IsCardInsert == FALSE)
+ {
+ return SDH_NO_SD_CARD;
+ }
+ }
+
+ while ((sdh->CTL & SDH_CTL_DIEN_Msk) == SDH_CTL_DIEN_Msk)
+ {
+ if (pSD->IsCardInsert == FALSE)
+ {
+ return SDH_NO_SD_CARD;
+ }
+ }
+
+ if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk)
+ {
+ /* check CRC7 */
+ return SDH_CRC7_ERROR;
+ }
+
+ if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk)
+ {
+ /* check CRC16 */
+ return SDH_CRC16_ERROR;
+ }
+ return 0ul;
+}
+
+/* there are 8 bits for divider0, maximum is 256 */
+#define SDH_CLK_DIV0_MAX 256ul
+
+void SDH_Set_clock(SDH_T *sdh, uint32_t sd_clock_khz)
+{
+ uint32_t rate, div1;
+ static uint32_t u32SD_ClkSrc = 0ul, u32SD_PwrCtl = 0ul;
+
+ SYS_UnlockReg();
+
+ /* initial state, clock source use HIRC */
+ if (sd_clock_khz <= 400ul)
+ {
+ u32SD_PwrCtl = CLK->PWRCTL;
+ if ((u32SD_PwrCtl & CLK_PWRCTL_HIRCEN_Msk) != 0x4ul)
+ {
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+ }
+
+ if (sdh == SDH0)
+ {
+ u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk);
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | CLK_CLKSEL0_SDH0SEL_HIRC;
+ _SDH0_ReferenceClock = (__HIRC / 1000ul);
+ }
+ else
+ {
+ u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH1SEL_Msk);
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | CLK_CLKSEL0_SDH1SEL_HIRC;
+ _SDH1_ReferenceClock = (__HIRC / 1000ul);
+ }
+ }
+ /* transfer state, clock source use sys_init() */
+ else
+ {
+ CLK->PWRCTL = u32SD_PwrCtl;
+ if (sdh == SDH0)
+ {
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | u32SD_ClkSrc;
+ if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HXT)
+ {
+ _SDH0_ReferenceClock = (CLK_GetHXTFreq() / 1000ul);
+ }
+ else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HIRC)
+ {
+ _SDH0_ReferenceClock = (__HIRC / 1000ul);
+ }
+ else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_PLL)
+ {
+ _SDH0_ReferenceClock = (CLK_GetPLLClockFreq() / 1000ul);
+ }
+ else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HCLK)
+ {
+ _SDH0_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul);
+ }
+ }
+ else
+ {
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | u32SD_ClkSrc;
+ if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HXT)
+ {
+ _SDH1_ReferenceClock = (CLK_GetHXTFreq() / 1000ul);
+ }
+ else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HIRC)
+ {
+ _SDH1_ReferenceClock = (__HIRC / 1000ul);
+ }
+ else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_PLL)
+ {
+ _SDH1_ReferenceClock = (CLK_GetPLLClockFreq() / 1000ul);
+ }
+ else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HCLK)
+ {
+ _SDH1_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul);
+ }
+ }
+
+ if(sd_clock_khz >= 50000ul)
+ {
+ sd_clock_khz = 50000ul;
+ }
+ }
+ if (sdh == SDH0)
+ {
+ rate = _SDH0_ReferenceClock / sd_clock_khz;
+
+ /* choose slower clock if system clock cannot divisible by wanted clock */
+ if ((_SDH0_ReferenceClock % sd_clock_khz) != 0ul)
+ {
+ rate++;
+ }
+ }
+ else
+ {
+ rate = _SDH1_ReferenceClock / sd_clock_khz;
+
+ /* choose slower clock if system clock cannot divisible by wanted clock */
+ if ((_SDH1_ReferenceClock % sd_clock_khz) != 0ul)
+ {
+ rate++;
+ }
+ }
+
+ if(rate >= SDH_CLK_DIV0_MAX)
+ {
+ rate = SDH_CLK_DIV0_MAX;
+ }
+
+ /*--- calculate the second divider CLKDIV0[SDHOST_N]*/
+ div1 = (rate - 1ul) & 0xFFul;
+
+ /*--- setup register */
+ if (sdh == SDH0)
+ {
+ CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk;
+ CLK->CLKDIV0 |= (div1 << CLK_CLKDIV0_SDH0DIV_Pos);
+ }
+ else
+ {
+ CLK->CLKDIV3 &= ~CLK_CLKDIV3_SDH1DIV_Msk;
+ CLK->CLKDIV3 |= (div1 << CLK_CLKDIV3_SDH1DIV_Pos);
+ }
+ return;
+}
+
+uint32_t SDH_CardDetection(SDH_T *sdh)
+{
+ uint32_t i, val = TRUE;
+ SDH_INFO_T *pSD;
+
+ if (sdh == SDH0)
+ {
+ pSD = &SD0;
+ }
+ else
+ {
+ pSD = &SD1;
+ }
+
+
+ if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) == SDH_INTEN_CDSRC_Msk) /* Card detect pin from GPIO */
+ {
+ if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) /* Card remove */
+ {
+ pSD->IsCardInsert = (uint8_t)FALSE;
+ val = FALSE;
+ }
+ else
+ {
+ pSD->IsCardInsert = (uint8_t)TRUE;
+ }
+ }
+ else if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) != SDH_INTEN_CDSRC_Msk)
+ {
+ sdh->CTL |= SDH_CTL_CLKKEEP_Msk;
+ for(i= 0ul; i < 5000ul; i++)
+ {
+ }
+
+ if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) /* Card insert */
+ {
+ pSD->IsCardInsert = (uint8_t)TRUE;
+ }
+ else
+ {
+ pSD->IsCardInsert = (uint8_t)FALSE;
+ val = FALSE;
+ }
+
+ sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk;
+ }
+
+ return val;
+}
+
+uint32_t SDH_Init(SDH_T *sdh)
+{
+ uint32_t volatile i, status;
+ uint32_t resp;
+ uint32_t CIDBuffer[4];
+ uint32_t volatile u32CmdTimeOut;
+ SDH_INFO_T *pSD;
+
+ if (sdh == SDH0)
+ {
+ pSD = &SD0;
+ }
+ else
+ {
+ pSD = &SD1;
+ }
+
+ /* set the clock to 300KHz */
+ SDH_Set_clock(sdh, 300ul);
+
+ /* power ON 74 clock */
+ sdh->CTL |= SDH_CTL_CLK74OEN_Msk;
+
+ while ((sdh->CTL & SDH_CTL_CLK74OEN_Msk) == SDH_CTL_CLK74OEN_Msk)
+ {
+ if (pSD->IsCardInsert == FALSE)
+ {
+ return SDH_NO_SD_CARD;
+ }
+ }
+
+ SDH_SDCommand(sdh, 0ul, 0ul); /* reset all cards */
+ for (i=0x1000ul; i>0ul; i--)
+ {
+ }
+
+ /* initial SDHC */
+ pSD->R7Flag = 1ul;
+ u32CmdTimeOut = 0xFFFFFul;
+
+ i = SDH_SDCmdAndRsp(sdh, 8ul, 0x00000155ul, u32CmdTimeOut);
+ if (i == Successful)
+ {
+ /* SD 2.0 */
+ SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+ pSD->R3Flag = 1ul;
+ SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 2.7v-3.6v */
+ resp = sdh->RESP0;
+
+ while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */
+ {
+ SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+ pSD->R3Flag = 1ul;
+ SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
+ resp = sdh->RESP0;
+ }
+ if ((resp & 0x00400000ul) == 0x00400000ul)
+ {
+ pSD->CardType = SDH_TYPE_SD_HIGH;
+ }
+ else
+ {
+ pSD->CardType = SDH_TYPE_SD_LOW;
+ }
+ }
+ else
+ {
+ /* SD 1.1 */
+ SDH_SDCommand(sdh, 0ul, 0ul); /* reset all cards */
+ for (i=0x100ul; i>0ul; i--)
+ {
+ }
+
+ i = SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+ if (i == 2ul) /* MMC memory */
+ {
+
+ SDH_SDCommand(sdh, 0ul, 0ul); /* reset */
+ for (i=0x100ul; i>0ul; i--)
+ {
+ }
+
+ pSD->R3Flag = 1ul;
+
+ if (SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut) != 2ul) /* eMMC memory */
+ {
+ resp = sdh->RESP0;
+ while ((resp & 0x00800000ul) != 0x00800000ul)
+ {
+ /* check if card is ready */
+ pSD->R3Flag = 1ul;
+
+ SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut); /* high voltage */
+ resp = sdh->RESP0;
+ }
+
+ if ((resp & 0x00400000ul) == 0x00400000ul)
+ {
+ pSD->CardType = SDH_TYPE_EMMC;
+ }
+ else
+ {
+ pSD->CardType = SDH_TYPE_MMC;
+ }
+ }
+ else
+ {
+ pSD->CardType = SDH_TYPE_UNKNOWN;
+ return SDH_ERR_DEVICE;
+ }
+ }
+ else if (i == 0ul) /* SD Memory */
+ {
+ pSD->R3Flag = 1ul;
+ SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
+ resp = sdh->RESP0;
+ while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */
+ {
+ SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+ pSD->R3Flag = 1ul;
+ SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
+ resp = sdh->RESP0;
+ }
+ pSD->CardType = SDH_TYPE_SD_LOW;
+ }
+ else
+ {
+ pSD->CardType = SDH_TYPE_UNKNOWN;
+ return SDH_INIT_ERROR;
+ }
+ }
+
+ if (pSD->CardType != SDH_TYPE_UNKNOWN)
+ {
+ SDH_SDCmdAndRsp2(sdh, 2ul, 0x00ul, CIDBuffer);
+ if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
+ {
+ if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x10000ul, 0ul)) != Successful) /* set RCA */
+ {
+ return status;
+ }
+ pSD->RCA = 0x10000ul;
+ }
+ else
+ {
+ if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x00ul, 0ul)) != Successful) /* get RCA */
+ {
+ return status;
+ }
+ else
+ {
+ pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000;
+ }
+ }
+ }
+ return Successful;
+}
+
+
+uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD)
+{
+ uint32_t volatile status=0ul;
+ uint16_t current_comsumption, busy_status0;
+
+ sdh->DMASA = (uint32_t)pSD->dmabuf;
+ sdh->BLEN = 63ul;
+
+ if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x00ffff01ul)) != Successful)
+ {
+ return Fail;
+ }
+
+ current_comsumption = (uint16_t)(*pSD->dmabuf) << 8;
+ current_comsumption |= (uint16_t)(*(pSD->dmabuf + 1));
+ if (!current_comsumption)
+ {
+ return Fail;
+ }
+
+ busy_status0 = (uint16_t)(*(pSD->dmabuf + 28)) << 8;
+ busy_status0 |= (uint16_t)(*(pSD->dmabuf + 29));
+
+ if (!busy_status0) /* function ready */
+ {
+ sdh->DMASA = (uint32_t)pSD->dmabuf;
+ sdh->BLEN = 63ul; /* 512 bit */
+
+ if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x80ffff01ul)) != Successful)
+ {
+ return Fail;
+ }
+
+ /* function change timing: 8 clocks */
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+ while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+ {
+ }
+
+ current_comsumption = (uint16_t)(*pSD->dmabuf) << 8;
+ current_comsumption |= (uint16_t)(*(pSD->dmabuf + 1));
+ if (!current_comsumption)
+ {
+ return Fail;
+ }
+
+ return Successful;
+ }
+ else
+ {
+ return Fail;
+ }
+}
+
+
+uint32_t SDH_SelectCardType(SDH_T *sdh)
+{
+ uint32_t volatile status=0ul;
+ uint32_t param;
+ SDH_INFO_T *pSD;
+
+ if (sdh == SDH0)
+ {
+ pSD = &SD0;
+ }
+ else
+ {
+ pSD = &SD1;
+ }
+
+ if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful)
+ {
+ return status;
+ }
+
+ SDH_CheckRB(sdh);
+
+ /* if SD card set 4bit */
+ if (pSD->CardType == SDH_TYPE_SD_HIGH)
+ {
+ sdh->DMASA = (uint32_t)pSD->dmabuf;
+ sdh->BLEN = 0x07ul; /* 64 bit */
+ sdh->DMACTL |= SDH_DMACTL_DMARST_Msk;
+ while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == 0x2);
+
+ if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful)
+ {
+ return status;
+ }
+ if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful)
+ {
+ return status;
+ }
+
+ if ((*pSD->dmabuf & 0xful) == 0x2ul)
+ {
+ status = SDH_SwitchToHighSpeed(sdh, pSD);
+ if (status == Successful)
+ {
+ /* divider */
+ SDH_Set_clock(sdh, SDHC_FREQ);
+ }
+ }
+
+ if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful)
+ {
+ return status;
+ }
+ if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) /* set bus width */
+ {
+ return status;
+ }
+
+ sdh->CTL |= SDH_CTL_DBW_Msk;
+ }
+ else if (pSD->CardType == SDH_TYPE_SD_LOW)
+ {
+ sdh->DMASA = (uint32_t)pSD->dmabuf;;
+ sdh->BLEN = 0x07ul;
+
+ if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful)
+ {
+ return status;
+ }
+ if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful)
+ {
+ return status;
+ }
+
+ /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */
+ if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful)
+ {
+ return status;
+ }
+
+ if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful)
+ {
+ return status;
+ }
+
+ sdh->CTL |= SDH_CTL_DBW_Msk;
+ }
+ else if ((pSD->CardType == SDH_TYPE_MMC) ||(pSD->CardType == SDH_TYPE_EMMC))
+ {
+
+ if(pSD->CardType == SDH_TYPE_MMC)
+ {
+ sdh->CTL &= ~SDH_CTL_DBW_Msk;
+ }
+
+ /*--- sent CMD6 to MMC card to set bus width to 4 bits mode */
+ /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */
+ param = (3ul << 24) | (183ul << 16) | (1ul << 8);
+ if ((status = SDH_SDCmdAndRsp(sdh, 6ul, param, 0ul)) != Successful)
+ {
+ return status;
+ }
+ SDH_CheckRB(sdh);
+
+ sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */
+
+ }
+
+ if ((status = SDH_SDCmdAndRsp(sdh, 16ul, SDH_BLOCK_SIZE, 0ul)) != Successful)
+ {
+ return status;
+ }
+ sdh->BLEN = SDH_BLOCK_SIZE - 1ul;
+
+ SDH_SDCommand(sdh, 7ul, 0ul);
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+ while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+ {
+ }
+
+ sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk;
+
+ return Successful;
+}
+
+void SDH_Get_SD_info(SDH_T *sdh)
+{
+ unsigned int R_LEN, C_Size, MULT, size;
+ uint32_t Buffer[4];
+ //unsigned char *ptr;
+ SDH_INFO_T *pSD;
+
+ if (sdh == SDH0)
+ {
+ pSD = &SD0;
+ }
+ else
+ {
+ pSD = &SD1;
+ }
+
+ SDH_SDCmdAndRsp2(sdh, 9ul, pSD->RCA, Buffer);
+
+ if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
+ {
+ /* for MMC/eMMC card */
+ if ((Buffer[0] & 0xc0000000) == 0xc0000000)
+ {
+ /* CSD_STRUCTURE [127:126] is 3 */
+ /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */
+ SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul);
+
+ //ptr = (uint8_t *)((uint32_t)_SDH_ucSDHCBuffer );
+ sdh->DMASA = (uint32_t)pSD->dmabuf;;
+ sdh->BLEN = 511ul; /* read 512 bytes for EXT_CSD */
+
+ if (SDH_SDCmdAndRspDataIn(sdh, 8ul, 0x00ul) == Successful)
+ {
+ SDH_SDCommand(sdh, 7ul, 0ul);
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+ while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+ {
+ }
+
+ pSD->totalSectorN = (uint32_t)(*(pSD->dmabuf+215))<<24;
+ pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf+214))<<16;
+ pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf+213))<<8;
+ pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf+212));
+ pSD->diskSize = pSD->totalSectorN / 2ul;
+ }
+ }
+ else
+ {
+ /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */
+ R_LEN = (Buffer[1] & 0x000f0000ul) >> 16;
+ C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30);
+ MULT = (Buffer[2] & 0x00038000ul) >> 15;
+ size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<diskSize = size / 1024ul;
+ pSD->totalSectorN = size / 512ul;
+ }
+ }
+ else
+ {
+ if ((Buffer[0] & 0xc0000000) != 0x0ul)
+ {
+ C_Size = ((Buffer[1] & 0x0000003ful) << 16) | ((Buffer[2] & 0xffff0000ul) >> 16);
+ size = (C_Size+1ul) * 512ul; /* Kbytes */
+
+ pSD->diskSize = size;
+ pSD->totalSectorN = size << 1;
+ }
+ else
+ {
+ R_LEN = (Buffer[1] & 0x000f0000ul) >> 16;
+ C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30);
+ MULT = (Buffer[2] & 0x00038000ul) >> 15;
+ size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<diskSize = size / 1024ul;
+ pSD->totalSectorN = size / 512ul;
+ }
+ }
+ pSD->sectorSize = (int)512;
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+/**
+ * @brief This function use to reset SD function and select card detection source and pin.
+ *
+ * @param[in] sdh Select SDH0 or SDH1.
+ * @param[in] u32CardDetSrc Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3)
+ *
+ * @return None
+ */
+void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc)
+{
+ sdh->DMACTL = SDH_DMACTL_DMARST_Msk;
+ while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == SDH_DMACTL_DMARST_Msk)
+ {
+ }
+
+ sdh->DMACTL = SDH_DMACTL_DMAEN_Msk;
+
+ sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk;
+ while ((sdh->GCTL & SDH_GCTL_GCTLRST_Msk) == SDH_GCTL_GCTLRST_Msk)
+ {
+ }
+
+ if (sdh == SDH0)
+ {
+ NVIC_EnableIRQ(SDH0_IRQn);
+ memset(&SD0, 0, sizeof(SDH_INFO_T));
+ SD0.dmabuf = _SDH0_ucSDHCBuffer;
+ }
+ else if (sdh == SDH1)
+ {
+ NVIC_EnableIRQ(SDH1_IRQn);
+ memset(&SD1, 0, sizeof(SDH_INFO_T));
+ SD1.dmabuf = _SDH1_ucSDHCBuffer;
+ }
+ else
+ {
+ }
+
+ sdh->GCTL = SDH_GCTL_SDEN_Msk;
+
+ if ((u32CardDetSrc & CardDetect_From_DAT3) == CardDetect_From_DAT3)
+ {
+ sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk;
+ }
+ else
+ {
+ sdh->INTEN |= SDH_INTEN_CDSRC_Msk;
+ }
+ sdh->INTEN |= SDH_INTEN_CDIEN_Msk;
+
+ sdh->CTL |= SDH_CTL_CTLRST_Msk;
+ while ((sdh->CTL & SDH_CTL_CTLRST_Msk) == SDH_CTL_CTLRST_Msk)
+ {
+ }
+}
+
+/**
+ * @brief This function use to initial SD card.
+ *
+ * @param[in] sdh Select SDH0 or SDH1.
+ *
+ * @return None
+ *
+ * @details This function is used to initial SD card.
+ * SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source.
+ * And then switch back to the user's setting.
+ */
+uint32_t SDH_Probe(SDH_T *sdh)
+{
+ uint32_t val;
+
+ sdh->GINTEN = 0ul;
+ sdh->CTL &= ~SDH_CTL_SDNWR_Msk;
+ sdh->CTL |= 0x09ul << SDH_CTL_SDNWR_Pos; /* set SDNWR = 9 */
+ sdh->CTL &= ~SDH_CTL_BLKCNT_Msk;
+ sdh->CTL |= 0x01ul << SDH_CTL_BLKCNT_Pos; /* set BLKCNT = 1 */
+ sdh->CTL &= ~SDH_CTL_DBW_Msk; /* SD 1-bit data bus */
+
+ if(!(SDH_CardDetection(sdh)))
+ {
+ return SDH_NO_SD_CARD;
+ }
+
+ if ((val = SDH_Init(sdh)) != 0ul)
+ {
+ return val;
+ }
+
+ /* divider */
+ if ((SD0.CardType == SDH_TYPE_MMC) || (SD1.CardType == SDH_TYPE_MMC))
+ {
+ SDH_Set_clock(sdh, MMC_FREQ);
+ }
+ else
+ {
+ SDH_Set_clock(sdh, SD_FREQ);
+ }
+ SDH_Get_SD_info(sdh);
+
+ if ((val = SDH_SelectCardType(sdh)) != 0ul)
+ {
+ return val;
+ }
+
+ return 0ul;
+}
+
+/**
+ * @brief This function use to read data from SD card.
+ *
+ * @param[in] sdh Select SDH0 or SDH1.
+ * @param[out] pu8BufAddr The buffer to receive the data from SD card.
+ * @param[in] u32StartSec The start read sector address.
+ * @param[in] u32SecCount The the read sector number of data
+ *
+ * @return None
+ */
+uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
+{
+ uint32_t volatile bIsSendCmd = FALSE, buf;
+ uint32_t volatile reg;
+ uint32_t volatile i, loop, status;
+ uint32_t blksize = SDH_BLOCK_SIZE;
+
+ SDH_INFO_T *pSD;
+ if (sdh == SDH0)
+ {
+ pSD = &SD0;
+ }
+ else
+ {
+ pSD = &SD1;
+ }
+
+ if (u32SecCount == 0ul)
+ {
+ return SDH_SELECT_ERROR;
+ }
+
+ if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful)
+ {
+ return status;
+ }
+ SDH_CheckRB(sdh);
+
+ sdh->BLEN = blksize - 1ul; /* the actual byte count is equal to (SDBLEN+1) */
+
+ if ( (pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC) )
+ {
+ sdh->CMDARG = u32StartSec;
+ }
+ else
+ {
+ sdh->CMDARG = u32StartSec * blksize;
+ }
+
+ sdh->DMASA = (uint32_t)pu8BufAddr;
+
+ loop = u32SecCount / 255ul;
+ for (i=0ul; iDataReadyFlag = (uint8_t)FALSE;
+ reg = sdh->CTL & ~SDH_CTL_CMDCODE_Msk;
+ reg = reg | 0xff0000ul; /* set BLK_CNT to 255 */
+ if (bIsSendCmd == FALSE)
+ {
+ sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+ bIsSendCmd = TRUE;
+ }
+ else
+ {
+ sdh->CTL = reg | SDH_CTL_DIEN_Msk;
+ }
+
+ while(!pSD->DataReadyFlag)
+ {
+ if(pSD->DataReadyFlag)
+ {
+ break;
+ }
+ if (pSD->IsCardInsert == FALSE)
+ {
+ return SDH_NO_SD_CARD;
+ }
+ }
+
+ if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */
+ {
+ return SDH_CRC7_ERROR;
+ }
+
+ if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */
+ {
+ return SDH_CRC16_ERROR;
+ }
+ }
+
+ loop = u32SecCount % 255ul;
+ if (loop != 0ul)
+ {
+ pSD->DataReadyFlag = (uint8_t)FALSE;
+ reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk);
+ reg = reg & (~SDH_CTL_BLKCNT_Msk);
+ reg |= (loop << 16); /* setup SDCR_BLKCNT */
+
+ if (bIsSendCmd == FALSE)
+ {
+ sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+ bIsSendCmd = TRUE;
+ }
+ else
+ {
+ sdh->CTL = reg | SDH_CTL_DIEN_Msk;
+ }
+
+ while(!pSD->DataReadyFlag)
+ {
+ if (pSD->IsCardInsert == FALSE)
+ {
+ return SDH_NO_SD_CARD;
+ }
+ }
+
+ if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */
+ {
+ return SDH_CRC7_ERROR;
+ }
+
+ if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */
+ {
+ return SDH_CRC16_ERROR;
+ }
+ }
+
+ if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) /* stop command */
+ {
+ return SDH_CRC7_ERROR;
+ }
+ SDH_CheckRB(sdh);
+
+ SDH_SDCommand(sdh, 7ul, 0ul);
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+ while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+ {
+ }
+
+ return Successful;
+}
+
+
+/**
+ * @brief This function use to write data to SD card.
+ *
+ * @param[in] sdh Select SDH0 or SDH1.
+ * @param[in] pu8BufAddr The buffer to send the data to SD card.
+ * @param[in] u32StartSec The start write sector address.
+ * @param[in] u32SecCount The the write sector number of data.
+ *
+ * @return \ref SDH_SELECT_ERROR : u32SecCount is zero. \n
+ * \ref SDH_NO_SD_CARD : SD card be removed. \n
+ * \ref SDH_CRC_ERROR : CRC error happen. \n
+ * \ref SDH_CRC7_ERROR : CRC7 error happen. \n
+ * \ref Successful : Write data to SD card success.
+ */
+uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
+{
+ uint32_t volatile bIsSendCmd = FALSE;
+ uint32_t volatile reg;
+ uint32_t volatile i, loop, status;
+
+ SDH_INFO_T *pSD;
+
+ if (sdh == SDH0)
+ {
+ pSD = &SD0;
+ }
+ else
+ {
+ pSD = &SD1;
+ }
+
+ if (u32SecCount == 0ul)
+ {
+ return SDH_SELECT_ERROR;
+ }
+
+ if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful)
+ {
+ return status;
+ }
+
+ SDH_CheckRB(sdh);
+
+ /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */
+ sdh->BLEN = SDH_BLOCK_SIZE - 1ul;
+
+ if ((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC))
+ {
+ sdh->CMDARG = u32StartSec;
+ }
+ else
+ {
+ sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE; /* set start address for SD CMD */
+ }
+
+ sdh->DMASA = (uint32_t)pu8BufAddr;
+ loop = u32SecCount / 255ul; /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */
+ for (i=0ul; iDataReadyFlag = (uint8_t)FALSE;
+ reg = sdh->CTL & 0xff00c080;
+ reg = reg | 0xff0000ul; /* set BLK_CNT to 0xFF=255 */
+ if (!bIsSendCmd)
+ {
+ sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
+ bIsSendCmd = TRUE;
+ }
+ else
+ {
+ sdh->CTL = reg | SDH_CTL_DOEN_Msk;
+ }
+
+ while(!pSD->DataReadyFlag)
+ {
+ if (pSD->IsCardInsert == FALSE)
+ {
+ return SDH_NO_SD_CARD;
+ }
+ }
+
+ if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul)
+ {
+ sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+ return SDH_CRC_ERROR;
+ }
+ }
+
+ loop = u32SecCount % 255ul;
+ if (loop != 0ul)
+ {
+ pSD->DataReadyFlag = (uint8_t)FALSE;
+ reg = (sdh->CTL & 0xff00c080) | (loop << 16);
+ if (!bIsSendCmd)
+ {
+ sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
+ bIsSendCmd = TRUE;
+ }
+ else
+ {
+ sdh->CTL = reg | SDH_CTL_DOEN_Msk;
+ }
+
+ while(!pSD->DataReadyFlag)
+ {
+ if (pSD->IsCardInsert == FALSE)
+ {
+ return SDH_NO_SD_CARD;
+ }
+ }
+
+ if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul)
+ {
+ sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+ return SDH_CRC_ERROR;
+ }
+ }
+ sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+
+ if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) /* stop command */
+ {
+ return SDH_CRC7_ERROR;
+ }
+ SDH_CheckRB(sdh);
+
+ SDH_SDCommand(sdh, 7ul, 0ul);
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+ while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+ {
+ }
+
+ return Successful;
+}
+
+/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SDH_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
+
+
+
+
+
+
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spi.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spi.c
new file mode 100644
index 00000000000..0b4c5c789ef
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spi.c
@@ -0,0 +1,1443 @@
+/**************************************************************************//**
+ * @file spi.c
+ * @version V3.00
+ * @brief M480 series SPI driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SPI_Driver SPI Driver
+ @{
+*/
+
+
+/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+ @{
+*/
+static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s);
+
+/**
+ * @brief This function make SPI module be ready to transfer.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)
+ * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3)
+ * @param[in] u32DataWidth Decides the data width of a SPI transaction.
+ * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz.
+ * @return Actual frequency of SPI peripheral clock.
+ * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
+ * slave selection function is disabled.
+ * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0.
+ * The actual clock rate may be different from the target SPI clock rate.
+ * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the
+ * actual SPI clock rate will be 6MHz.
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+ * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+ * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
+ * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
+ */
+uint32_t SPI_Open(SPI_T *spi,
+ uint32_t u32MasterSlave,
+ uint32_t u32SPIMode,
+ uint32_t u32DataWidth,
+ uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U;
+
+ /* Disable I2S mode */
+ spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
+
+ if(u32DataWidth == 32U)
+ {
+ u32DataWidth = 0U;
+ }
+
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+
+ if(u32MasterSlave == SPI_MASTER)
+ {
+ /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
+ spi->SSCTL = SPI_SS_ACTIVE_LOW;
+
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+ spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Select PCLK as the clock source of SPI */
+ if(spi == SPI0)
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
+ }
+ else if(spi == SPI1)
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;
+ }
+ else if(spi == SPI2)
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;
+ }
+ else
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;
+ }
+ }
+
+ /* Check clock source of SPI */
+ if(spi == SPI0)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ u32ClkSrc = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if(spi == SPI1)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32ClkSrc = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if(spi == SPI2)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1)
+ {
+ u32ClkSrc = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32ClkSrc = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Set DIVIDER = 0 */
+ spi->CLKDIV = 0U;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ spi->CLKDIV = 0U;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock == 0U)
+ {
+ /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */
+ if(u32Div > 0xFFU)
+ {
+ u32Div = 0xFFU;
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+ }
+ else
+ {
+ spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (u32Div + 1U));
+ }
+ }
+ }
+ else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */
+ {
+ /* Default setting: slave selection signal is low level active. */
+ spi->SSCTL = SPI_SS_ACTIVE_LOW;
+
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+ spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
+
+ /* Set DIVIDER = 0 */
+ spi->CLKDIV = 0U;
+
+ /* Select PCLK as the clock source of SPI */
+ if(spi == SPI0)
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
+ /* Return slave peripheral clock rate */
+ u32RetValue = CLK_GetPCLK1Freq();
+ }
+ else if(spi == SPI1)
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;
+ /* Return slave peripheral clock rate */
+ u32RetValue = CLK_GetPCLK0Freq();
+ }
+ else if(spi == SPI2)
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;
+ /* Return slave peripheral clock rate */
+ u32RetValue = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;
+ /* Return slave peripheral clock rate */
+ u32RetValue = CLK_GetPCLK0Freq();
+ }
+ }
+
+ return u32RetValue;
+}
+
+/**
+ * @brief Disable SPI controller.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None
+ * @details This function will reset SPI controller.
+ */
+void SPI_Close(SPI_T *spi)
+{
+ if(spi == SPI0)
+ {
+ /* Reset SPI */
+ SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
+ }
+ else if(spi == SPI1)
+ {
+ /* Reset SPI */
+ SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
+ }
+ else if(spi == SPI2)
+ {
+ /* Reset SPI */
+ SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
+ }
+ else
+ {
+ /* Reset SPI */
+ SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk;
+ SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk;
+ }
+}
+
+/**
+ * @brief Clear RX FIFO buffer.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None
+ * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1.
+ */
+void SPI_ClearRxFIFO(SPI_T *spi)
+{
+ spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk;
+}
+
+/**
+ * @brief Clear TX FIFO buffer.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None
+ * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1.
+ * @note The TX shift register will not be cleared.
+ */
+void SPI_ClearTxFIFO(SPI_T *spi)
+{
+ spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk;
+}
+
+/**
+ * @brief Disable the automatic slave selection function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None
+ * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
+ */
+void SPI_DisableAutoSS(SPI_T *spi)
+{
+ spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);
+}
+
+/**
+ * @brief Enable the automatic slave selection function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS)
+ * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW)
+ * @return None
+ * @details This function will enable the automatic slave selection function. Only available in Master mode.
+ * The slave selection pin and the active level will be set in this function.
+ */
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+ spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk);
+}
+
+/**
+ * @brief Set the SPI bus clock.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz.
+ * @return Actual frequency of SPI bus clock.
+ * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate.
+ * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock
+ * rate will be 6 MHz.
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+ * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+ * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
+ */
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc, u32HCLKFreq;
+ uint32_t u32Div, u32RetValue;
+
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Select PCLK as the clock source of SPI */
+ if(spi == SPI0)
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
+ else if(spi == SPI1)
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;
+ else if(spi == SPI2)
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;
+ else
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;
+ }
+
+ /* Check clock source of SPI */
+ if(spi == SPI0)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ u32ClkSrc = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if(spi == SPI1)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32ClkSrc = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if(spi == SPI2)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ u32ClkSrc = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32ClkSrc = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Set DIVIDER = 0 */
+ spi->CLKDIV = 0U;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ spi->CLKDIV = 0U;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock == 0U)
+ {
+ /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */
+ if(u32Div > 0x1FFU)
+ {
+ u32Div = 0x1FFU;
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+ }
+ else
+ {
+ spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (u32Div + 1U));
+ }
+ }
+
+ return u32RetValue;
+}
+
+/**
+ * @brief Configure FIFO threshold setting.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. If data width is 8~16 bits, it could be 0 ~ 7.
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. If data width is 8~16 bits, it could be 0 ~ 7.
+ * @return None
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+ */
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+ spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |
+ (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
+ (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos);
+}
+
+/**
+ * @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return Actual SPI bus clock frequency in Hz.
+ * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode.
+ */
+uint32_t SPI_GetBusClock(SPI_T *spi)
+{
+ uint32_t u32Div;
+ uint32_t u32ClkSrc;
+
+ /* Get DIVIDER setting */
+ u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos;
+
+ /* Check clock source of SPI */
+ if(spi == SPI0)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ u32ClkSrc = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if(spi == SPI1)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32ClkSrc = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if(spi == SPI2)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ u32ClkSrc = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32ClkSrc = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+
+ /* Return SPI bus clock rate */
+ return (u32ClkSrc / (u32Div + 1U));
+}
+
+/**
+ * @brief Enable interrupt function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt enable bit.
+ * This parameter decides which interrupts will be enabled. It is combination of:
+ * - \ref SPI_UNIT_INT_MASK
+ * - \ref SPI_SSACT_INT_MASK
+ * - \ref SPI_SSINACT_INT_MASK
+ * - \ref SPI_SLVUR_INT_MASK
+ * - \ref SPI_SLVBE_INT_MASK
+ * - \ref SPI_TXUF_INT_MASK
+ * - \ref SPI_FIFO_TXTH_INT_MASK
+ * - \ref SPI_FIFO_RXTH_INT_MASK
+ * - \ref SPI_FIFO_RXOV_INT_MASK
+ * - \ref SPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Enable SPI related interrupts specified by u32Mask parameter.
+ */
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
+{
+ /* Enable unit transfer interrupt flag */
+ if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
+ {
+ spi->CTL |= SPI_CTL_UNITIEN_Msk;
+ }
+
+ /* Enable slave selection signal active interrupt flag */
+ if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
+ {
+ spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;
+ }
+
+ /* Enable slave selection signal inactive interrupt flag */
+ if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
+ {
+ spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;
+ }
+
+ /* Enable slave TX under run interrupt flag */
+ if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
+ {
+ spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;
+ }
+
+ /* Enable slave bit count error interrupt flag */
+ if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
+ {
+ spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;
+ }
+
+ /* Enable slave TX underflow interrupt flag */
+ if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
+ {
+ spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
+ }
+
+ /* Enable TX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
+ {
+ spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
+ }
+
+ /* Enable RX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
+ {
+ spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
+ }
+
+ /* Enable RX overrun interrupt flag */
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
+ {
+ spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
+ }
+
+ /* Enable RX time-out interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
+ {
+ spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
+ }
+}
+
+/**
+ * @brief Disable interrupt function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * This parameter decides which interrupts will be disabled. It is combination of:
+ * - \ref SPI_UNIT_INT_MASK
+ * - \ref SPI_SSACT_INT_MASK
+ * - \ref SPI_SSINACT_INT_MASK
+ * - \ref SPI_SLVUR_INT_MASK
+ * - \ref SPI_SLVBE_INT_MASK
+ * - \ref SPI_TXUF_INT_MASK
+ * - \ref SPI_FIFO_TXTH_INT_MASK
+ * - \ref SPI_FIFO_RXTH_INT_MASK
+ * - \ref SPI_FIFO_RXOV_INT_MASK
+ * - \ref SPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Disable SPI related interrupts specified by u32Mask parameter.
+ */
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
+{
+ /* Disable unit transfer interrupt flag */
+ if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
+ {
+ spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
+ }
+
+ /* Disable slave selection signal active interrupt flag */
+ if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
+ {
+ spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
+ }
+
+ /* Disable slave selection signal inactive interrupt flag */
+ if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
+ {
+ spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
+ }
+
+ /* Disable slave TX under run interrupt flag */
+ if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
+ {
+ spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
+ }
+
+ /* Disable slave bit count error interrupt flag */
+ if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
+ {
+ spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
+ }
+
+ /* Disable slave TX underflow interrupt flag */
+ if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
+ {
+ spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
+ }
+
+ /* Disable TX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
+ {
+ spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
+ }
+
+ /* Disable RX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
+ {
+ spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
+ }
+
+ /* Disable RX overrun interrupt flag */
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
+ {
+ spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
+ }
+
+ /* Disable RX time-out interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
+ {
+ spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
+ }
+}
+
+/**
+ * @brief Get interrupt flag.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be read. It is combination of:
+ * - \ref SPI_UNIT_INT_MASK
+ * - \ref SPI_SSACT_INT_MASK
+ * - \ref SPI_SSINACT_INT_MASK
+ * - \ref SPI_SLVUR_INT_MASK
+ * - \ref SPI_SLVBE_INT_MASK
+ * - \ref SPI_TXUF_INT_MASK
+ * - \ref SPI_FIFO_TXTH_INT_MASK
+ * - \ref SPI_FIFO_RXTH_INT_MASK
+ * - \ref SPI_FIFO_RXOV_INT_MASK
+ * - \ref SPI_FIFO_RXTO_INT_MASK
+ *
+ * @return Interrupt flags of selected sources.
+ * @details Get SPI related interrupt flags specified by u32Mask parameter.
+ */
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+ uint32_t u32IntFlag = 0U, u32TmpVal;
+
+ u32TmpVal = spi->STATUS & SPI_STATUS_UNITIF_Msk;
+ /* Check unit transfer interrupt flag */
+ if((u32Mask & SPI_UNIT_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= SPI_UNIT_INT_MASK;
+ }
+
+ u32TmpVal = spi->STATUS & SPI_STATUS_SSACTIF_Msk;
+ /* Check slave selection signal active interrupt flag */
+ if((u32Mask & SPI_SSACT_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= SPI_SSACT_INT_MASK;
+ }
+
+ u32TmpVal = spi->STATUS & SPI_STATUS_SSINAIF_Msk;
+ /* Check slave selection signal inactive interrupt flag */
+ if((u32Mask & SPI_SSINACT_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= SPI_SSINACT_INT_MASK;
+ }
+
+ u32TmpVal = spi->STATUS & SPI_STATUS_SLVURIF_Msk;
+ /* Check slave TX under run interrupt flag */
+ if((u32Mask & SPI_SLVUR_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= SPI_SLVUR_INT_MASK;
+ }
+
+ u32TmpVal = spi->STATUS & SPI_STATUS_SLVBEIF_Msk;
+ /* Check slave bit count error interrupt flag */
+ if((u32Mask & SPI_SLVBE_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= SPI_SLVBE_INT_MASK;
+ }
+
+ u32TmpVal = spi->STATUS & SPI_STATUS_TXUFIF_Msk;
+ /* Check slave TX underflow interrupt flag */
+ if((u32Mask & SPI_TXUF_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= SPI_TXUF_INT_MASK;
+ }
+
+ u32TmpVal = spi->STATUS & SPI_STATUS_TXTHIF_Msk;
+ /* Check TX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= SPI_FIFO_TXTH_INT_MASK;
+ }
+
+ u32TmpVal = spi->STATUS & SPI_STATUS_RXTHIF_Msk;
+ /* Check RX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= SPI_FIFO_RXTH_INT_MASK;
+ }
+
+ u32TmpVal = spi->STATUS & SPI_STATUS_RXOVIF_Msk;
+ /* Check RX overrun interrupt flag */
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= SPI_FIFO_RXOV_INT_MASK;
+ }
+
+ u32TmpVal = spi->STATUS & SPI_STATUS_RXTOIF_Msk;
+ /* Check RX time-out interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal))
+ {
+ u32IntFlag |= SPI_FIFO_RXTO_INT_MASK;
+ }
+
+ return u32IntFlag;
+}
+
+/**
+ * @brief Clear interrupt flag.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be cleared. It could be the combination of:
+ * - \ref SPI_UNIT_INT_MASK
+ * - \ref SPI_SSACT_INT_MASK
+ * - \ref SPI_SSINACT_INT_MASK
+ * - \ref SPI_SLVUR_INT_MASK
+ * - \ref SPI_SLVBE_INT_MASK
+ * - \ref SPI_TXUF_INT_MASK
+ * - \ref SPI_FIFO_RXOV_INT_MASK
+ * - \ref SPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Clear SPI related interrupt flags specified by u32Mask parameter.
+ */
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+ if(u32Mask & SPI_UNIT_INT_MASK)
+ {
+ spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
+ }
+
+ if(u32Mask & SPI_SSACT_INT_MASK)
+ {
+ spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
+ }
+
+ if(u32Mask & SPI_SSINACT_INT_MASK)
+ {
+ spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
+ }
+
+ if(u32Mask & SPI_SLVUR_INT_MASK)
+ {
+ spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
+ }
+
+ if(u32Mask & SPI_SLVBE_INT_MASK)
+ {
+ spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
+ }
+
+ if(u32Mask & SPI_TXUF_INT_MASK)
+ {
+ spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
+ }
+
+ if(u32Mask & SPI_FIFO_RXOV_INT_MASK)
+ {
+ spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
+ }
+
+ if(u32Mask & SPI_FIFO_RXTO_INT_MASK)
+ {
+ spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
+ }
+}
+
+/**
+ * @brief Get SPI status.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Mask The combination of all related sources.
+ * Each bit corresponds to a source.
+ * This parameter decides which flags will be read. It is combination of:
+ * - \ref SPI_BUSY_MASK
+ * - \ref SPI_RX_EMPTY_MASK
+ * - \ref SPI_RX_FULL_MASK
+ * - \ref SPI_TX_EMPTY_MASK
+ * - \ref SPI_TX_FULL_MASK
+ * - \ref SPI_TXRX_RESET_MASK
+ * - \ref SPI_SPIEN_STS_MASK
+ * - \ref SPI_SSLINE_STS_MASK
+ *
+ * @return Flags of selected sources.
+ * @details Get SPI related status specified by u32Mask parameter.
+ */
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
+{
+ uint32_t u32Flag = 0U, u32TmpValue;
+
+ u32TmpValue = spi->STATUS & SPI_STATUS_BUSY_Msk;
+ /* Check busy status */
+ if((u32Mask & SPI_BUSY_MASK) && (u32TmpValue))
+ {
+ u32Flag |= SPI_BUSY_MASK;
+ }
+
+ u32TmpValue = spi->STATUS & SPI_STATUS_RXEMPTY_Msk;
+ /* Check RX empty flag */
+ if((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpValue))
+ {
+ u32Flag |= SPI_RX_EMPTY_MASK;
+ }
+
+ u32TmpValue = spi->STATUS & SPI_STATUS_RXFULL_Msk;
+ /* Check RX full flag */
+ if((u32Mask & SPI_RX_FULL_MASK) && (u32TmpValue))
+ {
+ u32Flag |= SPI_RX_FULL_MASK;
+ }
+
+ u32TmpValue = spi->STATUS & SPI_STATUS_TXEMPTY_Msk;
+ /* Check TX empty flag */
+ if((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpValue))
+ {
+ u32Flag |= SPI_TX_EMPTY_MASK;
+ }
+
+ u32TmpValue = spi->STATUS & SPI_STATUS_TXFULL_Msk;
+ /* Check TX full flag */
+ if((u32Mask & SPI_TX_FULL_MASK) && (u32TmpValue))
+ {
+ u32Flag |= SPI_TX_FULL_MASK;
+ }
+
+ u32TmpValue = spi->STATUS & SPI_STATUS_TXRXRST_Msk;
+ /* Check TX/RX reset flag */
+ if((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpValue))
+ {
+ u32Flag |= SPI_TXRX_RESET_MASK;
+ }
+
+ u32TmpValue = spi->STATUS & SPI_STATUS_SPIENSTS_Msk;
+ /* Check SPIEN flag */
+ if((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpValue))
+ {
+ u32Flag |= SPI_SPIEN_STS_MASK;
+ }
+
+ u32TmpValue = spi->STATUS & SPI_STATUS_SSLINE_Msk;
+ /* Check SPIx_SS line status */
+ if((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpValue))
+ {
+ u32Flag |= SPI_SSLINE_STS_MASK;
+ }
+
+ return u32Flag;
+}
+
+
+/**
+ * @brief This function is used to get I2S source clock frequency.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return I2S source clock frequency (Hz).
+ * @details Return the source clock frequency according to the setting of SPI0SEL (CLKSEL2[27:26]).
+ */
+static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s)
+{
+ uint32_t u32Freq;
+
+ if(i2s == SPI0)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
+ {
+ u32Freq = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
+ {
+ u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ u32Freq = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32Freq = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if(i2s == SPI1)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+ {
+ u32Freq = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+ {
+ u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32Freq = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32Freq = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else if(i2s == SPI2)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+ {
+ u32Freq = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+ {
+ u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ u32Freq = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ u32Freq = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ else
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT)
+ {
+ u32Freq = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL)
+ {
+ u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ u32Freq = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32Freq = __HIRC; /* Clock source is HIRC */
+ }
+ }
+
+ return u32Freq;
+}
+
+/**
+ * @brief This function configures some parameters of I2S interface for general purpose use.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below.
+ * - \ref SPII2S_MODE_MASTER
+ * - \ref SPII2S_MODE_SLAVE
+ * @param[in] u32SampleRate Sample rate
+ * @param[in] u32WordWidth Data length. Valid values are listed below.
+ * - \ref SPII2S_DATABIT_8
+ * - \ref SPII2S_DATABIT_16
+ * - \ref SPII2S_DATABIT_24
+ * - \ref SPII2S_DATABIT_32
+ * @param[in] u32Channels Audio format. Valid values are listed below.
+ * - \ref SPII2S_MONO
+ * - \ref SPII2S_STEREO
+ * @param[in] u32DataFormat Data format. Valid values are listed below.
+ * - \ref SPII2S_FORMAT_I2S
+ * - \ref SPII2S_FORMAT_MSB
+ * - \ref SPII2S_FORMAT_PCMA
+ * - \ref SPII2S_FORMAT_PCMB
+ * @return Real sample rate of master mode or peripheral clock rate of slave mode.
+ * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters.
+ * Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled.
+ * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference.
+ * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
+ */
+uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat)
+{
+ uint32_t u32Divider;
+ uint32_t u32BitRate, u32SrcClk, u32RetValue;
+
+ /* Reset SPI/I2S */
+ if(i2s == SPI0)
+ {
+ SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
+ }
+ else if(i2s == SPI1)
+ {
+ SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
+ }
+ else if(i2s == SPI2)
+ {
+ SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
+ }
+ else
+ {
+ SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk;
+ SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk;
+ }
+
+ /* Configure I2S controller */
+ i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat;
+ /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */
+ SPI_SetFIFO(i2s, 2, 1);
+
+ if(u32MasterSlave == SPI_MASTER)
+ {
+ /* Get the source clock rate */
+ u32SrcClk = SPII2S_GetSourceClockFreq(i2s);
+
+ /* Calculate the bit clock rate */
+ u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U;
+ u32Divider = ((u32SrcClk / u32BitRate) >> 1U) - 1U;
+ //u32Divider = ((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U;
+ /* Set BCLKDIV setting */
+ i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos);
+
+ /* Calculate bit clock rate */
+ u32BitRate = u32SrcClk / ((u32Divider + 1U) * 2U);
+ /* Calculate real sample rate */
+ u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U);
+
+ /* Enable TX function, RX function and I2S mode. */
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+
+ /* Return the real sample rate */
+ u32RetValue = u32SampleRate;
+ }
+ else
+ {
+ /* Set BCLKDIV = 0 */
+ i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk;
+
+ if(i2s == SPI0)
+ {
+ /* Set the peripheral clock rate to equal APB clock rate */
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
+ /* Enable TX function, RX function and I2S mode. */
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+ /* Return slave peripheral clock rate */
+ u32RetValue = CLK_GetPCLK1Freq();
+ }
+ else if(i2s == SPI1)
+ {
+ /* Set the peripheral clock rate to equal APB clock rate */
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;
+ /* Enable TX function, RX function and I2S mode. */
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+ /* Return slave peripheral clock rate */
+ u32RetValue = CLK_GetPCLK0Freq();
+ }
+ else if(i2s == SPI2)
+ {
+ /* Set the peripheral clock rate to equal APB clock rate */
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;
+ /* Enable TX function, RX function and I2S mode. */
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+ /* Return slave peripheral clock rate */
+ u32RetValue = CLK_GetPCLK1Freq();
+ }
+ else
+ {
+ /* Set the peripheral clock rate to equal APB clock rate */
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;
+ /* Enable TX function, RX function and I2S mode. */
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+ /* Return slave peripheral clock rate */
+ u32RetValue = CLK_GetPCLK0Freq();
+ }
+ }
+
+ return u32RetValue;
+}
+
+/**
+ * @brief Disable I2S function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details Disable I2S function.
+ */
+void SPII2S_Close(SPI_T *i2s)
+{
+ i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
+}
+
+/**
+ * @brief Enable interrupt function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref SPII2S_FIFO_TXTH_INT_MASK
+ * - \ref SPII2S_FIFO_RXTH_INT_MASK
+ * - \ref SPII2S_FIFO_RXOV_INT_MASK
+ * - \ref SPII2S_FIFO_RXTO_INT_MASK
+ * - \ref SPII2S_TXUF_INT_MASK
+ * - \ref SPII2S_RIGHT_ZC_INT_MASK
+ * - \ref SPII2S_LEFT_ZC_INT_MASK
+ * @return None
+ * @details This function enables the interrupt according to the u32Mask parameter.
+ */
+void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask)
+{
+ /* Enable TX threshold interrupt flag */
+ if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK)
+ {
+ i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
+ }
+
+ /* Enable RX threshold interrupt flag */
+ if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK)
+ {
+ i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
+ }
+
+ /* Enable RX overrun interrupt flag */
+ if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK)
+ {
+ i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
+ }
+
+ /* Enable RX time-out interrupt flag */
+ if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK)
+ {
+ i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
+ }
+
+ /* Enable TX underflow interrupt flag */
+ if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK)
+ {
+ i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
+ }
+
+ /* Enable right channel zero cross interrupt flag */
+ if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK)
+ {
+ i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk;
+ }
+
+ /* Enable left channel zero cross interrupt flag */
+ if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK)
+ {
+ i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk;
+ }
+}
+
+/**
+ * @brief Disable interrupt function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref SPII2S_FIFO_TXTH_INT_MASK
+ * - \ref SPII2S_FIFO_RXTH_INT_MASK
+ * - \ref SPII2S_FIFO_RXOV_INT_MASK
+ * - \ref SPII2S_FIFO_RXTO_INT_MASK
+ * - \ref SPII2S_TXUF_INT_MASK
+ * - \ref SPII2S_RIGHT_ZC_INT_MASK
+ * - \ref SPII2S_LEFT_ZC_INT_MASK
+ * @return None
+ * @details This function disables the interrupt according to the u32Mask parameter.
+ */
+void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask)
+{
+ /* Disable TX threshold interrupt flag */
+ if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK)
+ {
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
+ }
+
+ /* Disable RX threshold interrupt flag */
+ if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK)
+ {
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
+ }
+
+ /* Disable RX overrun interrupt flag */
+ if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK)
+ {
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
+ }
+
+ /* Disable RX time-out interrupt flag */
+ if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK)
+ {
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
+ }
+
+ /* Disable TX underflow interrupt flag */
+ if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK)
+ {
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
+ }
+
+ /* Disable right channel zero cross interrupt flag */
+ if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK)
+ {
+ i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk;
+ }
+
+ /* Disable left channel zero cross interrupt flag */
+ if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK)
+ {
+ i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk;
+ }
+}
+
+/**
+ * @brief Enable master clock (MCLK).
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32BusClock The target MCLK clock rate.
+ * @return Actual MCLK clock rate
+ * @details Set the master clock rate according to u32BusClock parameter and enable master clock output.
+ * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.
+ */
+uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock)
+{
+ uint32_t u32Divider;
+ uint32_t u32SrcClk, u32RetValue;
+
+ u32SrcClk = SPII2S_GetSourceClockFreq(i2s);
+ if(u32BusClock == u32SrcClk)
+ {
+ u32Divider = 0U;
+ }
+ else
+ {
+ u32Divider = (u32SrcClk / u32BusClock) >> 1U;
+ /* MCLKDIV is a 6-bit width configuration. The maximum value is 0x3F. */
+ if(u32Divider > 0x3FU)
+ {
+ u32Divider = 0x3FU;
+ }
+ }
+
+ /* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */
+ i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos);
+
+ /* Enable MCLK output */
+ i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk;
+
+ if(u32Divider == 0U)
+ {
+ u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */
+ }
+ else
+ {
+ u32RetValue = ((u32SrcClk >> 1U) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */
+ }
+
+ return u32RetValue;
+}
+
+/**
+ * @brief Disable master clock (MCLK).
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output.
+ */
+void SPII2S_DisableMCLK(SPI_T *i2s)
+{
+ i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk;
+}
+
+/**
+ * @brief Configure FIFO threshold setting.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
+ * @return None
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+ */
+void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+ i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |
+ (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
+ (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos);
+}
+
+/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spim.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spim.c
new file mode 100644
index 00000000000..6715f446971
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spim.c
@@ -0,0 +1,1308 @@
+/**************************************************************************//**
+ * @file spim.c
+ * @version V1.00
+ * @brief M480 series SPIM driver
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SPIM_Driver SPIM Driver
+ @{
+*/
+
+/** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions
+ @{
+*/
+
+
+/** @cond HIDDEN_SYMBOLS */
+
+
+#define ENABLE_DEBUG 0
+
+#if ENABLE_DEBUG
+#define SPIM_DBGMSG printf
+#else
+#define SPIM_DBGMSG(...) do { } while (0) /* disable debug */
+#endif
+
+static volatile uint8_t g_Supported_List[] =
+{
+ MFGID_WINBOND,
+ MFGID_MXIC,
+ MFGID_EON,
+ MFGID_ISSI,
+ MFGID_SPANSION
+};
+
+static void N_delay(int n);
+static void SwitchNBitOutput(uint32_t u32NBit);
+static void SwitchNBitInput(uint32_t u32NBit);
+static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx);
+static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx);
+static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
+static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
+static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
+static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
+static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
+static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
+static int spim_is_write_done(uint32_t u32NBit);
+static int spim_wait_write_done(uint32_t u32NBit);
+static void spim_set_write_enable(int isEn, uint32_t u32NBit);
+static void spim_enable_spansion_quad_mode(int isEn);
+static void spim_eon_set_qpi_mode(int isEn);
+static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit);
+static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd,
+ uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync);
+static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx,
+ uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync);
+
+
+static void N_delay(int n)
+{
+ while (n-- > 0)
+ {
+ __NOP();
+ }
+}
+
+static void SwitchNBitOutput(uint32_t u32NBit)
+{
+ switch (u32NBit)
+ {
+ case 1UL:
+ SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */
+ break;
+
+ case 2UL:
+ SPIM_ENABLE_DUAL_OUTPUT_MODE(); /* 2-bit, Output. */
+ break;
+
+ case 4UL:
+ SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 4-bit, Output. */
+ break;
+
+ default:
+ break;
+ }
+}
+
+static void SwitchNBitInput(uint32_t u32NBit)
+{
+ switch (u32NBit)
+ {
+ case 1UL:
+ SPIM_ENABLE_SING_INPUT_MODE(); /* 1-bit, Input. */
+ break;
+
+ case 2UL:
+ SPIM_ENABLE_DUAL_INPUT_MODE(); /* 2-bit, Input. */
+ break;
+
+ case 4UL:
+ SPIM_ENABLE_QUAD_INPUT_MODE(); /* 4-bit, Input. */
+ break;
+
+ default:
+ break;
+ }
+}
+
+
+/**
+ * @brief Write data to SPI slave.
+ * @param pu8TxBuf Transmit buffer.
+ * @param u32NTx Number of bytes to transmit.
+ * @return None.
+ */
+static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx)
+{
+ uint32_t buf_idx = 0UL;
+
+ while (u32NTx)
+ {
+ uint32_t dataNum = 0UL, dataNum2;
+
+ if (u32NTx >= 16UL)
+ {
+ dataNum = 4UL;
+ }
+ else if (u32NTx >= 12UL)
+ {
+ dataNum = 3UL;
+ }
+ else if (u32NTx >= 8UL)
+ {
+ dataNum = 2UL;
+ }
+ else if (u32NTx >= 4UL)
+ {
+ dataNum = 1UL;
+ }
+
+ dataNum2 = dataNum;
+ while (dataNum2)
+ {
+ uint32_t tmp;
+
+ memcpy(&tmp, &pu8TxBuf[buf_idx], 4U);
+ buf_idx += 4UL;
+ u32NTx -= 4UL;
+
+ dataNum2 --;
+ /* *((__O uint32_t *) &SPIM->TX0 + dataNum2) = tmp; */
+ SPIM->TX[dataNum2] = tmp;
+ }
+
+ if (dataNum)
+ {
+ SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
+ SPIM_SET_DATA_WIDTH(32UL);
+ SPIM_SET_DATA_NUM(dataNum);
+ SPIM_SET_GO();
+ SPIM_WAIT_FREE();
+ }
+
+ if (u32NTx && (u32NTx < 4UL))
+ {
+ uint32_t rnm, tmp;
+
+ rnm = u32NTx;
+ memcpy(&tmp, &pu8TxBuf[buf_idx], u32NTx);
+ buf_idx += u32NTx;
+ u32NTx = 0UL;
+ SPIM->TX[0] = tmp;
+
+ SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
+ SPIM_SET_DATA_WIDTH(rnm * 8UL);
+ SPIM_SET_DATA_NUM(1UL);
+ SPIM_SET_GO();
+ SPIM_WAIT_FREE();
+ }
+ }
+}
+
+/**
+ * @brief Read data from SPI slave.
+ * @param pu8TxBuf Receive buffer.
+ * @param u32NRx Size of receive buffer in bytes.
+ * @return None.
+ */
+static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx)
+{
+ uint32_t buf_idx = 0UL;
+
+ while (u32NRx)
+ {
+ uint32_t dataNum = 0UL; /* number of words */
+
+ if (u32NRx >= 16UL)
+ {
+ dataNum = 4UL;
+ }
+ else if (u32NRx >= 12UL)
+ {
+ dataNum = 3UL;
+ }
+ else if (u32NRx >= 8UL)
+ {
+ dataNum = 2UL;
+ }
+ else if (u32NRx >= 4UL)
+ {
+ dataNum = 1UL;
+ }
+
+ if (dataNum)
+ {
+ SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
+ SPIM_SET_DATA_WIDTH(32UL);
+ SPIM_SET_DATA_NUM(dataNum);
+ SPIM_SET_GO();
+ SPIM_WAIT_FREE();
+ }
+
+ while (dataNum)
+ {
+ uint32_t tmp;
+
+ tmp = SPIM->RX[dataNum-1UL];
+ memcpy(&pu8RxBuf[buf_idx], &tmp, 4U);
+ buf_idx += 4UL;
+ dataNum --;
+ u32NRx -= 4UL;
+ }
+
+ if (u32NRx && (u32NRx < 4UL))
+ {
+ uint32_t tmp;
+
+ SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
+ SPIM_SET_DATA_WIDTH(u32NRx * 8UL);
+ SPIM_SET_DATA_NUM(1UL);
+ SPIM_SET_GO();
+ SPIM_WAIT_FREE();
+
+ tmp = SPIM->RX[0];
+ memcpy(&pu8RxBuf[buf_idx], &tmp, u32NRx);
+ buf_idx += u32NRx;
+ u32NRx = 0UL;
+ }
+ }
+}
+
+/**
+ * @brief Issue Read Status Register #1 command.
+ * @param dataBuf Receive buffer.
+ * @param u32NRx Size of receive buffer.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[] = {OPCODE_RDSR}; /* 1-byte Read Status Register #1 command. */
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SwitchNBitInput(u32NBit);
+ spim_read(dataBuf, u32NRx);
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+
+/**
+ * @brief Issue Write Status Register #1 command.
+ * @param dataBuf Transmit buffer.
+ * @param u32NTx Size of transmit buffer.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[] = {OPCODE_WRSR, 0x00U}; /* 1-byte Write Status Register #1 command + 1-byte data. */
+
+ cmdBuf[1] = dataBuf[0];
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+
+/**
+ * @brief Issue Read Status Register #2 command.
+ * @param dataBuf Receive buffer.
+ * @param u32NRx Size of receive buffer.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[] = {OPCODE_RDSR2}; /* 1-byte Read Status Register #1 command. */
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SwitchNBitInput(u32NBit);
+ spim_read(dataBuf, u32NRx);
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+
+/**
+ * @brief Issue Winbond Write Status Register command. This command write both Status Register-1
+ * and Status Register-2.
+ * @param dataBuf Transmit buffer.
+ * @param u32NTx Size of transmit buffer.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[3] = {OPCODE_WRSR, 0U, 0U};
+
+ cmdBuf[1] = dataBuf[0];
+ cmdBuf[2] = dataBuf[1];
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+
+#if 0 /* not used */
+/**
+ * @brief Issue Write Status Register #3 command.
+ * @param dataBuf Transmit buffer.
+ * @param u32NTx Size of transmit buffer.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[] = {OPCODE_WRSR3, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */
+ cmdBuf[1] = dataBuf[0];
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+#endif
+
+/**
+ * @brief Issue Read Status Register #3 command.
+ * @param dataBuf Receive buffer.
+ * @param u32NRx Size of receive buffer.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[] = {OPCODE_RDSR3}; /* 1-byte Read Status Register #1 command. */
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SwitchNBitInput(u32NBit);
+ spim_read(dataBuf, u32NRx);
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+
+#if 0 /* not used */
+/**
+ * @brief Issue Write Security Register command.
+ * @param dataBuf Transmit buffer.
+ * @param u32NTx Size of transmit buffer.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[] = {OPCODE_WRSCUR, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */
+ cmdBuf[1] = dataBuf[0];
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+#endif
+
+/**
+ * @brief Issue Read Security Register command.
+ * @param dataBuf Receive buffer.
+ * @param u32NRx Size of receive buffer.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[] = {OPCODE_RDSCUR}; /* 1-byte Read Status Register #1 command. */
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SwitchNBitInput(u32NBit);
+ spim_read(dataBuf, u32NRx);
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+
+/**
+ * @brief Check if Erase/Write is done.
+ * @return 0: Not done. 1: Done.
+ */
+static int spim_is_write_done(uint32_t u32NBit)
+{
+ uint8_t status[1];
+ SPIM_ReadStatusRegister(status, sizeof (status), u32NBit);
+ return ! (status[0] & SR_WIP);
+}
+
+/**
+ * @brief Wait until Erase/Write done.
+ * @param u32NBit N-bit transmit/receive.
+ * @return 0 SPIM write done.
+ */
+static int spim_wait_write_done(uint32_t u32NBit)
+{
+ uint32_t count;
+ int ret = -1;
+
+ for (count = 0UL; count < SystemCoreClock/1000UL; count++)
+ {
+ if (spim_is_write_done(u32NBit))
+ {
+ ret = 0;
+ break;
+ }
+ }
+ if (ret != 0)
+ {
+ SPIM_DBGMSG("spim_wait_write_done time-out!!\n");
+ }
+ return ret;
+}
+
+/**
+ * @brief Issue Write Enable/disable command.
+ * @param isEn Enable/disable.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+static void spim_set_write_enable(int isEn, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[] = {0U}; /* 1-byte Write Enable command. */
+ cmdBuf[0] = isEn ? OPCODE_WREN : OPCODE_WRDI;
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+ * @brief Get SPIM serial clock.
+ * @return SPI serial clock.
+ * @details This function calculates the serial clock of SPI in Hz.
+ */
+uint32_t SPIM_GetSClkFreq(void)
+{
+ uint32_t clkDiv = SPIM_GET_CLOCK_DIVIDER();
+
+ return clkDiv ? SystemCoreClock / (clkDiv * 2U) : SystemCoreClock;
+}
+
+/**
+ * @brief Initialize SPIM flash.
+ * @param clrWP Clear Write Protect or not.
+ * @return 0 Success.
+ * @return -1 Unrecognized manufacture ID or failed on reading manufacture ID.
+ */
+int SPIM_InitFlash(int clrWP)
+{
+ uint8_t idBuf[3];
+ uint8_t cmdBuf[1];
+ uint32_t i;
+ int32_t ret = -1;
+
+ SPIM_SET_SS_ACTLVL(0);
+
+ /*
+ * Because not sure in SPI or QPI mode, do QPI reset and then SPI reset.
+ */
+ /* QPI Reset Enable */
+ cmdBuf[0] = OPCODE_RSTEN;
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+
+ /* QPI Reset */
+ cmdBuf[0] = OPCODE_RST;
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+
+ /* SPI ResetEnable */
+ cmdBuf[0] = OPCODE_RSTEN;
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+
+ /* SPI Reset */
+ cmdBuf[0] = OPCODE_RST;
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+
+ if (clrWP)
+ {
+ uint8_t dataBuf[] = {0x00U};
+
+ spim_set_write_enable(1, 1UL); /* Clear Block Protect. */
+ SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), 1U);
+ spim_wait_write_done(1UL);
+ }
+
+ SPIM_ReadJedecId(idBuf, sizeof (idBuf), 1UL);
+
+ /* printf("ID: 0x%x, 0x%x, px%x\n", idBuf[0], idBuf[1], idBuf[2]); */
+
+ for (i = 0UL; i < sizeof(g_Supported_List)/sizeof(g_Supported_List[0]); i++)
+ {
+ if (idBuf[0] == g_Supported_List[i])
+ {
+ ret = 0;
+ }
+ }
+ if (ret != 0)
+ {
+ SPIM_DBGMSG("Flash initialize failed!! 0x%x\n", idBuf[0]);
+ }
+ return ret;
+}
+
+/**
+ * @brief Issue JEDEC ID command.
+ * @param idBuf ID buffer.
+ * @param u32NRx Size of ID buffer.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[] = { OPCODE_RDID }; /* 1-byte JEDEC ID command. */
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SwitchNBitInput(u32NBit);
+ spim_read(idBuf, u32NRx);
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+
+/** @cond HIDDEN_SYMBOLS */
+
+static void spim_enable_spansion_quad_mode(int isEn)
+{
+ uint8_t cmdBuf[3];
+ uint8_t dataBuf[1], status1;
+
+ cmdBuf[0] = 0x5U; /* Read Status Register-1 */
+
+ SPIM_SET_SS_EN(1);
+ SwitchNBitOutput(1UL);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SwitchNBitInput(1UL);
+ spim_read(dataBuf, sizeof (dataBuf));
+ SPIM_SET_SS_EN(0);
+ /* SPIM_DBGMSG("SR1 = 0x%x\n", dataBuf[0]); */
+
+ status1 = dataBuf[0];
+
+ cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */
+
+ SPIM_SET_SS_EN(1);
+ SwitchNBitOutput(1UL);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SwitchNBitInput(1UL);
+ spim_read(dataBuf, sizeof (dataBuf));
+ SPIM_SET_SS_EN(0);
+ /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */
+
+ spim_set_write_enable(1, 1UL);
+
+ cmdBuf[0] = 0x1U; /* Write register */
+ cmdBuf[1] = status1;
+
+ if (isEn)
+ {
+ cmdBuf[2] = dataBuf[0] | 0x2U; /* set QUAD */
+ }
+ else
+ {
+ cmdBuf[2] = dataBuf[0] & ~0x2U; /* clear QUAD */
+ }
+
+ SPIM_SET_SS_EN(1);
+ SwitchNBitOutput(1UL);
+ spim_write(cmdBuf, 3UL);
+ SPIM_SET_SS_EN(0);
+
+ spim_set_write_enable(0, 1UL);
+
+
+ cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */
+
+ SPIM_SET_SS_EN(1);
+ SwitchNBitOutput(1UL);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SwitchNBitInput(1UL);
+ spim_read(dataBuf, sizeof (dataBuf));
+ SPIM_SET_SS_EN(0);
+
+ /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */
+ N_delay(10000);
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+ * @brief Set Quad Enable/disable.
+ * @param isEn Enable/disable.
+ * @param u32NBit N-bit transmit/receive.
+ * @return None.
+ */
+void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit)
+{
+ uint8_t idBuf[3];
+ uint8_t dataBuf[2];
+
+ SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit);
+
+ SPIM_DBGMSG("SPIM_SetQuadEnable - Flash ID is 0x%x\n", idBuf[0]);
+
+ switch (idBuf[0])
+ {
+ case MFGID_WINBOND: /* Winbond SPI flash */
+ SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
+ SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
+ SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
+ if (isEn)
+ {
+ dataBuf[1] |= SR2_QE;
+ }
+ else
+ {
+ dataBuf[1] &= ~SR2_QE;
+ }
+
+ spim_set_write_enable(1, u32NBit); /* Write Enable. */
+ SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit);
+ spim_wait_write_done(u32NBit);
+
+ SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
+ SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
+ SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
+ break;
+
+ case MFGID_MXIC: /* MXIC SPI flash. */
+ case MFGID_EON:
+ case MFGID_ISSI: /* ISSI SPI flash. */
+ spim_set_write_enable(1, u32NBit); /* Write Enable. */
+ dataBuf[0] = isEn ? SR_QE : 0U;
+ SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), u32NBit);
+ spim_wait_write_done(u32NBit);
+ break;
+
+ case MFGID_SPANSION:
+ spim_enable_spansion_quad_mode(isEn);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Enter/exit QPI mode.
+ * @param isEn Enable/disable.
+ * @return None.
+ */
+static void spim_eon_set_qpi_mode(int isEn)
+{
+ uint8_t cmdBuf[1]; /* 1-byte command. */
+
+ uint8_t status[1];
+ SPIM_ReadStatusRegister(status, sizeof (status), 1UL);
+ SPIM_DBGMSG("Status: 0x%x\n", status[0]);
+
+ if (isEn) /* Assume in SPI mode. */
+ {
+ cmdBuf[0] = OPCODE_ENQPI;
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(1UL);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+ }
+ else /* Assume in QPI mode. */
+ {
+ cmdBuf[0] = OPCODE_EXQPI;
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(4UL);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+ }
+
+ SPIM_ReadStatusRegister(status, sizeof (status), 1UL);
+ SPIM_DBGMSG("Status: 0x%x\n", status[0]);
+}
+
+
+static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit)
+{
+ uint8_t cmdBuf[2];
+ uint8_t dataBuf[1];
+
+ cmdBuf[0] = OPCODE_BRRD;
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, 1UL);
+ SwitchNBitInput(1UL);
+ spim_read(dataBuf, 1UL);
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+
+ SPIM_DBGMSG("Bank Address register= 0x%x\n", dataBuf[0]);
+
+ cmdBuf[0] = OPCODE_BRWR;
+
+ if (isEn)
+ {
+ cmdBuf[1] = dataBuf[0] | 0x80U; /* set EXTADD */
+ }
+ else
+ {
+ cmdBuf[1] = dataBuf[0] & ~0x80U; /* clear EXTADD */
+ }
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(1UL);
+ spim_write(cmdBuf, 2UL);
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+
+/** @cond HIDDEN_SYMBOLS */
+
+/**
+ * @brief Query 4-byte address mode enabled or not.
+ * @param u32NBit N-bit transmit/receive.
+ * @return 0: 4-byte address mode disabled. 1: 4-byte address mode enabled.
+ */
+int SPIM_Is4ByteModeEnable(uint32_t u32NBit)
+{
+ int isEn = 0;
+ int isSupt = 0;
+ uint8_t idBuf[3];
+ uint8_t dataBuf[1];
+
+ SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit);
+
+ /* Based on Flash size, check if 4-byte address mode is supported. */
+ switch (idBuf[0])
+ {
+ case MFGID_WINBOND:
+ case MFGID_MXIC:
+ case MFGID_EON:
+ isSupt = (idBuf[2] < 0x19U) ? 0L : 1L;
+ break;
+
+ case MFGID_ISSI:
+ isSupt = (idBuf[2] < 0x49U) ? 0L : 1L;
+ break;
+
+ default:
+ break;
+ }
+
+ if (isSupt != 0)
+ {
+ if (idBuf[0] == MFGID_WINBOND)
+ {
+ /* Winbond SPI flash. */
+ SPIM_ReadStatusRegister3(dataBuf, sizeof (dataBuf), u32NBit);
+ isEn = !! (dataBuf[0] & SR3_ADR);
+ }
+ else if ((idBuf[0] == MFGID_MXIC) || (idBuf[0] ==MFGID_EON))
+ {
+ /* MXIC/EON SPI flash. */
+ SPIM_ReadSecurityRegister(dataBuf, sizeof (dataBuf), u32NBit);
+ isEn = !! (dataBuf[0] & SCUR_4BYTE);
+ }
+ }
+
+ return isEn;
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+/**
+ * @brief Enter/Exit 4-byte address mode.
+ * @param isEn Enable/disable.
+ * @param u32NBit N-bit transmit/receive.
+ * @return 0 success
+ * -1 failed
+ */
+int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit)
+{
+ int isSupt = 0L, ret = -1;
+ uint8_t idBuf[3];
+ uint8_t cmdBuf[1]; /* 1-byte Enter/Exit 4-Byte Mode command. */
+
+ SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit);
+
+ /* Based on Flash size, check if 4-byte address mode is supported. */
+ switch (idBuf[0])
+ {
+ case MFGID_WINBOND:
+ case MFGID_MXIC:
+ case MFGID_EON:
+ isSupt = (idBuf[2] < 0x19U) ? 0L : 1L;
+ break;
+
+ case MFGID_ISSI:
+ isSupt = (idBuf[2] < 0x49U) ? 0L : 1L;
+ break;
+
+ case MFGID_SPANSION:
+ SPIM_SPANSION_4Bytes_Enable(isEn, u32NBit);
+ isSupt = 1L;
+ ret = 0L;
+ break;
+
+ default:
+ break;
+ }
+
+ if ((isSupt) && (idBuf[0] != MFGID_SPANSION))
+ {
+ cmdBuf[0] = isEn ? OPCODE_EN4B : OPCODE_EX4B;
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+
+ /*
+ * FIXME: Per test, 4BYTE Indicator bit doesn't set after EN4B, which
+ * doesn't match spec(MX25L25635E), so skip the check below.
+ */
+ if (idBuf[0] != MFGID_MXIC)
+ {
+ if (isEn)
+ {
+ while (! SPIM_Is4ByteModeEnable(u32NBit)) { }
+ }
+ else
+ {
+ while (SPIM_Is4ByteModeEnable(u32NBit)) { }
+ }
+ }
+ ret = 0;
+ }
+ return ret;
+}
+
+
+void SPIM_WinbondUnlock(uint32_t u32NBit)
+{
+ uint8_t idBuf[3];
+ uint8_t dataBuf[4];
+
+ SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit);
+
+ if ((idBuf[0] != MFGID_WINBOND) || (idBuf[1] != 0x40) || (idBuf[2] != 0x16))
+ {
+ SPIM_DBGMSG("SPIM_WinbondUnlock - Not W25Q32, do nothing.\n");
+ return;
+ }
+
+ SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
+ SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
+ SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
+ dataBuf[1] &= ~0x40; /* clear Status Register-1 SEC bit */
+
+ spim_set_write_enable(1, u32NBit); /* Write Enable. */
+ SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit);
+ spim_wait_write_done(u32NBit);
+
+ SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
+ SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
+ SPIM_DBGMSG("Status Register (after unlock): 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
+}
+
+/**
+ * @brief Erase whole chip.
+ * @param u32NBit N-bit transmit/receive.
+ * @param isSync Block or not.
+ * @return None.
+ */
+void SPIM_ChipErase(uint32_t u32NBit, int isSync)
+{
+ uint8_t cmdBuf[] = { OPCODE_CHIP_ERASE }; /* 1-byte Chip Erase command. */
+
+ spim_set_write_enable(1, u32NBit); /* Write Enable. */
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, sizeof (cmdBuf));
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+
+ if (isSync)
+ {
+ spim_wait_write_done(u32NBit);
+ }
+}
+
+
+/**
+ * @brief Erase one block.
+ * @param u32Addr Block to erase which contains the u32Addr.
+ * @param is4ByteAddr 4-byte u32Address or not.
+ * @param u8ErsCmd Erase command.
+ * @param u32NBit N-bit transmit/receive.
+ * @param isSync Block or not.
+ * @return None.
+ */
+void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync)
+{
+ uint8_t cmdBuf[16];
+ uint32_t buf_idx = 0UL;
+
+ spim_set_write_enable(1, u32NBit); /* Write Enable. */
+
+ cmdBuf[buf_idx++] = u8ErsCmd;
+
+ if (is4ByteAddr)
+ {
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL);
+ }
+ else
+ {
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL);
+ }
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+ SwitchNBitOutput(u32NBit);
+ spim_write(cmdBuf, buf_idx);
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+
+ if (isSync)
+ {
+ spim_wait_write_done(u32NBit);
+ }
+}
+
+
+/** @cond HIDDEN_SYMBOLS */
+
+/**
+ * @brief Write data in the same page by I/O mode.
+ * @param u32Addr Start u32Address to write.
+ * @param is4ByteAddr 4-byte u32Address or not.
+ * @param u32NTx Number of bytes to write.
+ * @param pu8TxBuf Transmit buffer.
+ * @param wrCmd Write command.
+ * @param u32NBitCmd N-bit transmit command.
+ * @param u32NBitAddr N-bit transmit u32Address.
+ * @param u32NBitDat N-bit transmit/receive data.
+ * @param isSync Block or not.
+ * @return None.
+ */
+static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd,
+ uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync)
+{
+ uint8_t cmdBuf[16];
+ uint32_t buf_idx;
+
+ spim_set_write_enable(1, u32NBitCmd); /* Write Enable. */
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+
+ SwitchNBitOutput(u32NBitCmd);
+ cmdBuf[0] = wrCmd;
+ spim_write(cmdBuf, 1UL); /* Write out command. */
+
+ buf_idx = 0UL;
+ if (is4ByteAddr)
+ {
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+ cmdBuf[buf_idx++] = (uint8_t) u32Addr;
+ }
+ else
+ {
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+ cmdBuf[buf_idx++] = (uint8_t) u32Addr;
+ }
+
+ SwitchNBitOutput(u32NBitAddr);
+ spim_write(cmdBuf, buf_idx); /* Write out u32Address. */
+
+ SwitchNBitOutput(u32NBitDat);
+ spim_write(pu8TxBuf, u32NTx); /* Write out data. */
+
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+
+ if (isSync)
+ {
+ spim_wait_write_done(u32NBitCmd);
+ }
+}
+
+/**
+ * @brief Write data in the same page by Page Write mode.
+ * @param u32Addr Start u32Address to write.
+ * @param is4ByteAddr 4-byte u32Address or not.
+ * @param u32NTx Number of bytes to write.
+ * @param pu8TxBuf Transmit buffer.
+ * @param wrCmd Write command.
+ * @param isSync Block or not.
+ * @return None.
+ */
+static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx,
+ uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync)
+{
+ if ((wrCmd == CMD_QUAD_PAGE_PROGRAM_WINBOND) ||
+ (wrCmd == CMD_QUAD_PAGE_PROGRAM_MXIC))
+ {
+ SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */
+ }
+ else if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON)
+ {
+ SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */
+ spim_eon_set_qpi_mode(1); /* Enter QPI mode. */
+ }
+
+ SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEWRITE);/* Switch to Page Write mode. */
+ SPIM_SET_SPIM_MODE(wrCmd); /* SPIM mode. */
+ SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */
+
+ SPIM->SRAMADDR = (uint32_t) pu8TxBuf; /* SRAM u32Address. */
+ SPIM->DMACNT = u32NTx; /* Transfer length. */
+ SPIM->FADDR = u32Addr; /* Flash u32Address.*/
+ SPIM_SET_GO(); /* Go. */
+
+ if (isSync)
+ {
+ SPIM_WAIT_FREE();
+ }
+
+ if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON)
+ {
+ spim_eon_set_qpi_mode(0); /* Exit QPI mode. */
+ }
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+ * @brief Write data to SPI Flash by sending commands manually (I/O mode).
+ * @param u32Addr: Start u32Address to write.
+ * @param is4ByteAddr: 4-byte u32Address or not.
+ * @param u32NTx: Number of bytes to write.
+ * @param pu8TxBuf: Transmit buffer.
+ * @param wrCmd: Write command.
+ * @param u32NBitCmd: N-bit transmit command.
+ * @param u32NBitAddr: N-bit transmit u32Address.
+ * @param u32NBitDat: N-bit transmit/receive data.
+ * @return None.
+ */
+void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd,
+ uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat)
+{
+ uint32_t pageOffset, toWr;
+ uint32_t buf_idx = 0UL;
+
+ pageOffset = u32Addr % 256UL;
+
+ if ((pageOffset + u32NTx) <= 256UL) /* Do all the bytes fit onto one page ? */
+ {
+ SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, u32NTx, &pu8TxBuf[buf_idx],
+ wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1);
+ }
+ else
+ {
+ toWr = 256UL - pageOffset; /* Size of data remaining on the first page. */
+
+ SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx],
+ wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1);
+ u32Addr += toWr; /* Advance indicator. */
+ u32NTx -= toWr;
+ buf_idx += toWr;
+
+ while (u32NTx)
+ {
+ toWr = 256UL;
+ if (toWr > u32NTx)
+ {
+ toWr = u32NTx;
+ }
+
+ SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx],
+ wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1);
+ u32Addr += toWr; /* Advance indicator. */
+ u32NTx -= toWr;
+ buf_idx += toWr;
+ }
+ }
+}
+
+/**
+ * @brief Read data from SPI Flash by sending commands manually (I/O mode).
+ * @param u32Addr Start u32Address to read.
+ * @param is4ByteAddr 4-byte u32Address or not.
+ * @param u32NRx Number of bytes to read.
+ * @param pu8RxBuf Receive buffer.
+ * @param rdCmd Read command.
+ * @param u32NBitCmd N-bit transmit command.
+ * @param u32NBitAddr N-bit transmit u32Address.
+ * @param u32NBitDat N-bit transmit/receive data.
+ * @param u32NDummy Number of dummy bytes following address.
+ * @return None.
+ */
+void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd,
+ uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy)
+{
+ uint8_t cmdBuf[16];
+ uint32_t buf_idx;
+
+ SPIM_SET_SS_EN(1); /* CS activated. */
+
+ cmdBuf[0] = rdCmd;
+ SwitchNBitOutput(u32NBitCmd);
+ spim_write(cmdBuf, 1UL); /* Write out command. */
+
+ buf_idx = 0UL;
+ if (is4ByteAddr)
+ {
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+ cmdBuf[buf_idx++] = (uint8_t) u32Addr;
+ }
+ else
+ {
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+ cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+ cmdBuf[buf_idx++] = (uint8_t) u32Addr;
+ }
+ SwitchNBitOutput(u32NBitAddr);
+ spim_write(cmdBuf, buf_idx); /* Write out u32Address. */
+
+ buf_idx = 0UL;
+ while (u32NDummy --)
+ {
+ cmdBuf[buf_idx++] = 0x00U;
+ }
+
+ /* Same bit mode as above. */
+ spim_write(cmdBuf, buf_idx); /* Write out dummy bytes. */
+
+ SwitchNBitInput(u32NBitDat);
+ spim_read(pu8RxBuf, u32NRx); /* Read back data. */
+
+ SPIM_SET_SS_EN(0); /* CS deactivated. */
+}
+
+/**
+ * @brief Write data to SPI Flash by Page Write mode.
+ * @param u32Addr Start address to write.
+ * @param is4ByteAddr 4-byte address or not.
+ * @param u32NTx Number of bytes to write.
+ * @param pu8TxBuf Transmit buffer.
+ * @param wrCmd Write command.
+ * @return None.
+ */
+void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd)
+{
+ uint32_t pageOffset, toWr;
+ uint32_t buf_idx = 0UL;
+
+ pageOffset = u32Addr % 256UL;
+
+ if ((pageOffset + u32NTx) <= 256UL)
+ {
+ /* Do all the bytes fit onto one page ? */
+ SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, u32NTx, pu8TxBuf, wrCmd, 1);
+ }
+ else
+ {
+ toWr = 256UL - pageOffset; /* Size of data remaining on the first page. */
+
+ SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1);
+
+ u32Addr += toWr; /* Advance indicator. */
+ u32NTx -= toWr;
+ buf_idx += toWr;
+
+ while (u32NTx)
+ {
+ toWr = 256UL;
+ if (toWr > u32NTx)
+ {
+ toWr = u32NTx;
+ }
+
+ SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1);
+
+ u32Addr += toWr; /* Advance indicator. */
+ u32NTx -= toWr;
+ buf_idx += toWr;
+ }
+ }
+}
+
+/**
+ * @brief Read data from SPI Flash by Page Read mode.
+ * @param u32Addr Start address to read.
+ * @param is4ByteAddr 4-byte u32Address or not.
+ * @param u32NRx Number of bytes to read.
+ * @param pu8RxBuf Receive buffer.
+ * @param u32RdCmd Read command.
+ * @param isSync Block or not.
+ * @return None.
+ */
+void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[],
+ uint32_t u32RdCmd, int isSync)
+{
+ SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEREAD); /* Switch to Page Read mode. */
+ SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */
+ SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */
+
+ SPIM->SRAMADDR = (uint32_t) pu8RxBuf; /* SRAM u32Address. */
+ SPIM->DMACNT = u32NRx; /* Transfer length. */
+ SPIM->FADDR = u32Addr; /* Flash u32Address.*/
+ SPIM_SET_GO(); /* Go. */
+
+ if (isSync)
+ {
+ SPIM_WAIT_FREE(); /* Wait for DMA done. */
+ }
+}
+
+/**
+ * @brief Enter Direct Map mode.
+ * @param is4ByteAddr 4-byte u32Address or not.
+ * @param u32RdCmd Read command.
+ * @param u32IdleIntvl Idle interval.
+ * @return None.
+ */
+void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl)
+{
+ SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-byte u32Address. */
+ SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */
+ SPIM_SET_IDL_INTVL(u32IdleIntvl); /* Idle interval. */
+ SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_DIRECTMAP); /* Switch to Direct Map mode. */
+}
+
+/**
+ * @brief Exit Direct Map mode.
+ * @return None.
+ */
+void SPIM_ExitDirectMapMode(void)
+{
+ SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch back to Normal mode. */
+}
+
+
+/*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SPIM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sys.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sys.c
new file mode 100644
index 00000000000..e5e12896e7c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sys.c
@@ -0,0 +1,284 @@
+/**************************************************************************//**
+ * @file sys.c
+ * @version V1.00
+ * @brief M480 series SYS driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "NuMicro.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+ @{
+*/
+
+
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear reset source
+ * @param[in] u32Src is system reset source. Including :
+ * - \ref SYS_RSTSTS_CPULKRF_Msk
+ * - \ref SYS_RSTSTS_CPURF_Msk
+ * - \ref SYS_RSTSTS_SYSRF_Msk
+ * - \ref SYS_RSTSTS_BODRF_Msk
+ * - \ref SYS_RSTSTS_LVRF_Msk
+ * - \ref SYS_RSTSTS_WDTRF_Msk
+ * - \ref SYS_RSTSTS_PINRF_Msk
+ * - \ref SYS_RSTSTS_PORF_Msk
+ * @return None
+ * @details This function clear the selected system reset source.
+ */
+void SYS_ClearResetSrc(uint32_t u32Src)
+{
+ SYS->RSTSTS |= u32Src;
+}
+
+/**
+ * @brief Get Brown-out detector output status
+ * @param None
+ * @retval 0 System voltage is higher than BODVL setting or BODEN is 0.
+ * @retval 1 System voltage is lower than BODVL setting.
+ * @details This function get Brown-out detector output status.
+ */
+uint32_t SYS_GetBODStatus(void)
+{
+ return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
+}
+
+/**
+ * @brief Get reset status register value
+ * @param None
+ * @return Reset source
+ * @details This function get the system reset status register value.
+ */
+uint32_t SYS_GetResetSrc(void)
+{
+ return (SYS->RSTSTS);
+}
+
+/**
+ * @brief Check if register is locked nor not
+ * @param None
+ * @retval 0 Write-protection function is disabled.
+ * 1 Write-protection function is enabled.
+ * @details This function check register write-protection bit setting.
+ */
+uint32_t SYS_IsRegLocked(void)
+{
+ return SYS->REGLCTL & 1UL ? 0UL : 1UL;
+}
+
+/**
+ * @brief Get product ID
+ * @param None
+ * @return Product ID
+ * @details This function get product ID.
+ */
+uint32_t SYS_ReadPDID(void)
+{
+ return SYS->PDID;
+}
+
+/**
+ * @brief Reset chip with chip reset
+ * @param None
+ * @return None
+ * @details This function reset chip with chip reset.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_ResetChip(void)
+{
+ SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
+}
+
+/**
+ * @brief Reset chip with CPU reset
+ * @param None
+ * @return None
+ * @details This function reset CPU with CPU reset.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_ResetCPU(void)
+{
+ SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
+}
+
+/**
+ * @brief Reset selected module
+ * @param[in] u32ModuleIndex is module index. Including :
+ * - \ref PDMA_RST
+ * - \ref EBI_RST
+ * - \ref EMAC_RST
+ * - \ref SDH0_RST
+ * - \ref CRC_RST
+ * - \ref CCAP_RST
+ * - \ref HSUSBD_RST
+ * - \ref CRPT_RST
+ * - \ref SPIM_RST
+ * - \ref USBH_RST
+ * - \ref SDH1_RST
+ * - \ref GPIO_RST
+ * - \ref TMR0_RST
+ * - \ref TMR1_RST
+ * - \ref TMR2_RST
+ * - \ref TMR3_RST
+ * - \ref ACMP01_RST
+ * - \ref I2C0_RST
+ * - \ref I2C1_RST
+ * - \ref I2C2_RST
+ * - \ref QSPI0_RST
+ * - \ref SPI0_RST
+ * - \ref SPI1_RST
+ * - \ref SPI2_RST
+ * - \ref UART0_RST
+ * - \ref UART1_RST
+ * - \ref UART2_RST
+ * - \ref UART3_RST
+ * - \ref UART4_RST
+ * - \ref UART5_RST
+ * - \ref UART6_RST
+ * - \ref UART7_RST
+ * - \ref CAN0_RST
+ * - \ref CAN1_RST
+ * - \ref OTG_RST
+ * - \ref USBD_RST
+ * - \ref EADC_RST
+ * - \ref I2S0_RST
+ * - \ref HSOTG_RST
+ * - \ref TRNG_RST
+ * - \ref SC0_RST
+ * - \ref SC1_RST
+ * - \ref SC2_RST
+ * - \ref QSPI1_RST
+ * - \ref SPI3_RST
+ * - \ref USCI0_RST
+ * - \ref USCI1_RST
+ * - \ref DAC_RST
+ * - \ref EPWM0_RST
+ * - \ref EPWM1_RST
+ * - \ref BPWM0_RST
+ * - \ref BPWM1_RST
+ * - \ref QEI0_RST
+ * - \ref QEI1_RST
+ * - \ref ECAP0_RST
+ * - \ref ECAP1_RST
+ * - \ref CAN2_RST
+ * - \ref OPA_RST
+ * - \ref EADC1_RST
+ * @return None
+ * @details This function reset selected module.
+ */
+void SYS_ResetModule(uint32_t u32ModuleIndex)
+{
+ uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
+
+ /* Generate reset signal to the corresponding module */
+ u32tmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL));
+ u32tmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL));
+ *(uint32_t *)u32tmpAddr |= u32tmpVal;
+
+ /* Release corresponding module from reset state */
+ u32tmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL));
+ *(uint32_t *)u32tmpAddr &= u32tmpVal;
+}
+
+/**
+ * @brief Enable and configure Brown-out detector function
+ * @param[in] i32Mode is reset or interrupt mode. Including :
+ * - \ref SYS_BODCTL_BOD_RST_EN
+ * - \ref SYS_BODCTL_BOD_INTERRUPT_EN
+ * @param[in] u32BODLevel is Brown-out voltage level. Including :
+ * - \ref SYS_BODCTL_BODVL_3_0V
+ * - \ref SYS_BODCTL_BODVL_2_8V
+ * - \ref SYS_BODCTL_BODVL_2_6V
+ * - \ref SYS_BODCTL_BODVL_2_4V
+ * - \ref SYS_BODCTL_BODVL_2_2V
+ * - \ref SYS_BODCTL_BODVL_2_0V
+ * - \ref SYS_BODCTL_BODVL_1_8V
+ * - \ref SYS_BODCTL_BODVL_1_6V
+ * @return None
+ * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
+{
+ /* Enable Brown-out Detector function */
+ SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;
+
+ /* Enable Brown-out interrupt or reset function */
+ SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | (uint32_t)i32Mode;
+
+ /* Select Brown-out Detector threshold voltage */
+ SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;
+}
+
+/**
+ * @brief Disable Brown-out detector function
+ * @param None
+ * @return None
+ * @details This function disable Brown-out detector function.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_DisableBOD(void)
+{
+ SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
+}
+
+/**
+ * @brief Set Power Level
+ * @param[in] u32PowerLevel is power level setting. Including :
+ * - \ref SYS_PLCTL_PLSEL_PL0
+ * - \ref SYS_PLCTL_PLSEL_PL1
+ * @return None
+ * @details This function select power level.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_SetPowerLevel(uint32_t u32PowerLevel)
+{
+ /* Set power voltage level */
+ SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel);
+}
+
+/**
+ * @brief Set Reference Voltage
+ * @param[in] u32VRefCTL is reference voltage setting. Including :
+ * - \ref SYS_VREFCTL_VREF_PIN
+ * - \ref SYS_VREFCTL_VREF_1_6V
+ * - \ref SYS_VREFCTL_VREF_2_0V
+ * - \ref SYS_VREFCTL_VREF_2_5V
+ * - \ref SYS_VREFCTL_VREF_3_0V
+ * - \ref SYS_VREFCTL_VREF_AVDD
+ * @return None
+ * @details This function select reference voltage.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_SetVRef(uint32_t u32VRefCTL)
+{
+ /* Set reference voltage */
+ SYS->VREFCTL = (SYS->VREFCTL & (~SYS_VREFCTL_VREFCTL_Msk)) | (u32VRefCTL);
+}
+
+/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SYS_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer.c
new file mode 100644
index 00000000000..1987445777b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer.c
@@ -0,0 +1,353 @@
+/**************************************************************************//**
+ * @file timer.c
+ * @brief M480 Timer Controller(Timer) driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup TIMER_Driver TIMER Driver
+ @{
+*/
+
+/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+ @{
+*/
+
+/**
+ * @brief Open Timer with Operate Mode and Frequency
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Mode Operation mode. Possible options are
+ * - \ref TIMER_ONESHOT_MODE
+ * - \ref TIMER_PERIODIC_MODE
+ * - \ref TIMER_TOGGLE_MODE
+ * - \ref TIMER_CONTINUOUS_MODE
+ * @param[in] u32Freq Target working frequency
+ *
+ * @return Real timer working frequency
+ *
+ * @details This API is used to configure timer to operate in specified mode and frequency.
+ * If timer cannot work in target frequency, a closest frequency will be chose and returned.
+ * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
+ * \ref TIMER_Start macro or program registers directly.
+ */
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
+{
+ uint32_t u32Clk = TIMER_GetModuleClock(timer);
+ uint32_t u32Cmpr = 0UL, u32Prescale = 0UL;
+
+ /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */
+ if(u32Freq > (u32Clk / 2UL))
+ {
+ u32Cmpr = 2UL;
+ }
+ else
+ {
+ u32Cmpr = u32Clk / u32Freq;
+ u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */
+ if (u32Prescale > 0UL)
+ u32Cmpr = u32Cmpr / (u32Prescale + 1UL);
+ }
+
+ timer->CTL = u32Mode | u32Prescale;
+ timer->CMP = u32Cmpr;
+
+ return(u32Clk / (u32Cmpr * (u32Prescale + 1UL)));
+}
+
+/**
+ * @brief Stop Timer Counting
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This API stops timer counting and disable all timer interrupt function.
+ */
+void TIMER_Close(TIMER_T *timer)
+{
+ timer->CTL = 0UL;
+ timer->EXTCTL = 0UL;
+}
+
+/**
+ * @brief Create a specify Delay Time
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
+ *
+ * @return None
+ *
+ * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode.
+ * @note This API overwrites the register setting of the timer used to count the delay time.
+ * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
+ */
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
+{
+ uint32_t u32Clk = TIMER_GetModuleClock(timer);
+ uint32_t u32Prescale = 0UL, delay = (SystemCoreClock / u32Clk) + 1UL;
+ uint32_t u32Cmpr, u32NsecPerTick;
+
+ /* Clear current timer configuration */
+ timer->CTL = 0UL;
+ timer->EXTCTL = 0UL;
+
+ if(u32Clk <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */
+ {
+ if(u32Usec < 1000UL)
+ {
+ u32Usec = 1000UL;
+ }
+ if(u32Usec > 1000000UL)
+ {
+ u32Usec = 1000000UL;
+ }
+ }
+ else
+ {
+ if(u32Usec < 100UL)
+ {
+ u32Usec = 100UL;
+ }
+ if(u32Usec > 1000000UL)
+ {
+ u32Usec = 1000000UL;
+ }
+ }
+
+ if(u32Clk <= 1000000UL)
+ {
+ u32Prescale = 0UL;
+ u32NsecPerTick = 1000000000UL / u32Clk;
+ u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick;
+ }
+ else
+ {
+ u32Cmpr = u32Usec * (u32Clk / 1000000UL);
+ u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */
+ if (u32Prescale > 0UL)
+ u32Cmpr = u32Cmpr / (u32Prescale + 1UL);
+ }
+
+ timer->CMP = u32Cmpr;
+ timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;
+
+ /* When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
+ And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. */
+ for(; delay > 0UL; delay--)
+ {
+ __NOP();
+ }
+
+ while(timer->CTL & TIMER_CTL_ACTSTS_Msk)
+ {
+ ;
+ }
+}
+
+/**
+ * @brief Enable Timer Capture Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32CapMode Timer capture mode. Could be
+ * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
+ * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
+ * @param[in] u32Edge Timer capture trigger edge. Possible values are
+ * - \ref TIMER_CAPTURE_EVENT_FALLING
+ * - \ref TIMER_CAPTURE_EVENT_RISING
+ * - \ref TIMER_CAPTURE_EVENT_FALLING_RISING
+ * - \ref TIMER_CAPTURE_EVENT_RISING_FALLING
+ *
+ * @return None
+ *
+ * @details This API is used to enable timer capture function with specify capture trigger edge \n
+ * to get current counter value or reset counter value to 0.
+ * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
+ */
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
+{
+ timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |
+ u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+ * @brief Disable Timer Capture Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This API is used to disable the timer capture function.
+ */
+void TIMER_DisableCapture(TIMER_T *timer)
+{
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+ * @brief Enable Timer Counter Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Edge Detection edge of counter pin. Could be ether
+ * - \ref TIMER_COUNTER_EVENT_FALLING, or
+ * - \ref TIMER_COUNTER_EVENT_RISING
+ *
+ * @return None
+ *
+ * @details This function is used to enable the timer counter function with specify detection edge.
+ * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
+ * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
+ */
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
+{
+ timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
+ timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
+}
+
+/**
+ * @brief Disable Timer Counter Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This API is used to disable the timer event counter function.
+ */
+void TIMER_DisableEventCounter(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
+}
+
+/**
+ * @brief Get Timer Clock Frequency
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return Timer clock frequency
+ *
+ * @details This API is used to get the timer clock frequency.
+ * @note This API cannot return correct clock rate if timer source is from external clock input.
+ */
+uint32_t TIMER_GetModuleClock(TIMER_T *timer)
+{
+ uint32_t u32Src, u32Clk;
+ const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC};
+
+ if(timer == TIMER0)
+ {
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
+ }
+ else if(timer == TIMER1)
+ {
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
+ }
+ else if(timer == TIMER2)
+ {
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos;
+ }
+ else /* Timer 3 */
+ {
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos;
+ }
+
+ if(u32Src == 2UL)
+ {
+ if((timer == TIMER0) || (timer == TIMER1))
+ {
+ u32Clk = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32Clk = CLK_GetPCLK1Freq();
+ }
+ }
+ else
+ {
+ u32Clk = au32Clk[u32Src];
+ }
+
+ return u32Clk;
+}
+
+
+
+/**
+ * @brief This function is used to enable the Timer frequency counter function
+ * @param[in] timer The base address of Timer module. Can be \ref TIMER0 or \ref TIMER2
+ * @param[in] u32DropCount This parameter has no effect in M480 series BSP
+ * @param[in] u32Timeout This parameter has no effect in M480 series BSP
+ * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE
+ * @return None
+ * @details This function is used to calculate input event frequency. After enable
+ * this function, a pair of timers, TIMER0 and TIMER1, or TIMER2 and TIMER3
+ * will be configured for this function. The mode used to calculate input
+ * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical
+ * Reference Manual
+ */
+void TIMER_EnableFreqCounter(TIMER_T *timer,
+ uint32_t u32DropCount,
+ uint32_t u32Timeout,
+ uint32_t u32EnableInt)
+{
+ TIMER_T *t; /* store the timer base to configure compare value */
+
+ t = (timer == TIMER0) ? TIMER1 : TIMER3;
+
+ t->CMP = 0xFFFFFFUL;
+ t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL;
+ timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk;
+
+ return;
+}
+/**
+ * @brief This function is used to disable the Timer frequency counter function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+void TIMER_DisableFreqCounter(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_INTRGEN_Msk;
+}
+
+
+/**
+ * @brief This function is used to select the interrupt source used to trigger other modules.
+ * @param[in] timer The base address of Timer module
+ * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be:
+ * - \ref TIMER_TRGSRC_TIMEOUT_EVENT
+ * - \ref TIMER_TRGSRC_CAPTURE_EVENT
+ * @return None
+ */
+void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
+{
+ timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src;
+}
+
+/**
+ * @brief This function is used to set modules trigger by timer interrupt
+ * @param[in] timer The base address of Timer module
+ * @param[in] u32Mask The mask of modules (EPWM, EADC, DAC and PDMA) trigger by timer. Is the combination of
+ * - \ref TIMER_TRG_TO_EPWM,
+ * - \ref TIMER_TRG_TO_EADC,
+ * - \ref TIMER_TRG_TO_DAC, and
+ * - \ref TIMER_TRG_TO_PDMA
+ * @return None
+ */
+void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
+{
+ timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGEPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask;
+}
+
+/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TIMER_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer_pwm.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer_pwm.c
new file mode 100644
index 00000000000..15d180f2658
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer_pwm.c
@@ -0,0 +1,443 @@
+/**************************************************************************//**
+ * @file timer_pwm.c
+ * @brief M480 Timer PWM Controller(Timer PWM) driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver
+ @{
+*/
+
+/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set PWM Counter Clock Source
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32CntClkSrc PWM counter clock source, could be one of following source
+ * - \ref TPWM_CNTR_CLKSRC_TMR_CLK
+ * - \ref TPWM_CNTR_CLKSRC_TIMER0_INT
+ * - \ref TPWM_CNTR_CLKSRC_TIMER1_INT
+ * - \ref TPWM_CNTR_CLKSRC_TIMER2_INT
+ * - \ref TPWM_CNTR_CLKSRC_TIMER3_INT
+ *
+ * @return None
+ *
+ * @details This function is used to set PWM counter clock source.
+ */
+void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc)
+{
+ (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc;
+}
+
+/**
+ * @brief Configure PWM Output Frequency and Duty Cycle
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Frequency Target generator frequency.
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%...
+ *
+ * @return Nearest frequency clock in nano second
+ *
+ * @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode.
+ * @note This API is only available if Timer PWM counter clock source is from TMRx_CLK.
+ */
+uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+ uint32_t u32PWMClockFreq, u32TargetFreq;
+ uint32_t u32Prescaler = 0x1000UL, u32Period, u32CMP;
+
+ if((timer == TIMER0) || (timer == TIMER1))
+ {
+ u32PWMClockFreq = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32PWMClockFreq = CLK_GetPCLK1Freq();
+ }
+
+ /* Calculate u16PERIOD and u16PSC */
+ for(u32Prescaler = 1UL; u32Prescaler <= 0x1000UL; u32Prescaler++)
+ {
+ u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency;
+
+ /* If target u32Period is larger than 0x10000, need to use a larger prescaler */
+ if(u32Period <= 0x10000UL)
+ {
+ break;
+ }
+ }
+ /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */
+ u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period;
+
+ /* Set PWM to up count type */
+ timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos);
+
+ /* Set PWM to auto-reload mode */
+ timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | TPWM_AUTO_RELOAD_MODE;
+
+ /* Convert to real register value */
+ TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL));
+
+ TPWM_SET_PERIOD(timer, (u32Period - 1UL));
+ if(u32DutyCycle)
+ {
+ u32CMP = (u32DutyCycle * u32Period) / 100UL;
+ }
+ else
+ {
+ u32CMP = 0UL;
+ }
+
+ TPWM_SET_CMPDAT(timer, u32CMP);
+
+ return (u32TargetFreq);
+}
+
+/**
+ * @brief Enable Dead-Time Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion.
+ *
+ * @return None
+ *
+ * @details This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source.
+ * @note The register write-protection function should be disabled before using this function.
+ */
+void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount)
+{
+ timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount;
+}
+
+/**
+ * @brief Enable Dead-Time Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion.
+ *
+ * @return None
+ *
+ * @details This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale.
+ * @note The register write-protection function should be disabled before using this function.
+ */
+void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount)
+{
+ timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount;
+}
+
+/**
+ * @brief Disable Dead-Time Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable Dead-time of selected channel.
+ * @note The register write-protection function should be disabled before using this function.
+ */
+void TPWM_DisableDeadTime(TIMER_T *timer)
+{
+ timer->PWMDTCTL = 0x0UL;
+}
+
+/**
+ * @brief Enable PWM Counter
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable PWM generator and start counter counting.
+ */
+void TPWM_EnableCounter(TIMER_T *timer)
+{
+ timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk;
+}
+
+/**
+ * @brief Disable PWM Generator
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit.
+ */
+void TPWM_DisableCounter(TIMER_T *timer)
+{
+ timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk;
+}
+
+/**
+ * @brief Enable Trigger ADC
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Condition The condition to trigger ADC. It could be one of following conditions:
+ * - \ref TPWM_TRIGGER_ADC_AT_ZERO_POINT
+ * - \ref TPWM_TRIGGER_ADC_AT_PERIOD_POINT
+ * - \ref TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT
+ * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT
+ * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified counter compare event to trigger ADC.
+ */
+void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition)
+{
+ timer->PWMEADCTS = TIMER_PWMEADCTS_TRGEN_Msk | u32Condition;
+}
+
+/**
+ * @brief Disable Trigger ADC
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable counter compare event to trigger ADC.
+ */
+void TPWM_DisableTriggerADC(TIMER_T *timer)
+{
+ timer->PWMEADCTS = 0x0UL;
+}
+
+/**
+ * @brief Enable Fault Brake Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32CH0Level PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting
+ * - \ref TPWM_OUTPUT_TOGGLE
+ * - \ref TPWM_OUTPUT_NOTHING
+ * - \ref TPWM_OUTPUT_LOW
+ * - \ref TPWM_OUTPUT_HIGH
+ * @param[in] u32CH1Level PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting
+ * - \ref TPWM_OUTPUT_TOGGLE
+ * - \ref TPWM_OUTPUT_NOTHING
+ * - \ref TPWM_OUTPUT_LOW
+ * - \ref TPWM_OUTPUT_HIGH
+ * @param[in] u32BrakeSource Fault brake source, combination of following source
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM
+ *
+ * @return None
+ *
+ * @details This function is used to enable fault brake function.
+ * @note The register write-protection function should be disabled before using this function.
+ */
+void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource)
+{
+ timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL);
+ timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) |
+ (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos);
+}
+
+/**
+ * @brief Enable Fault Brake Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32IntSource Interrupt source, could be one of following source
+ * - \ref TPWM_BRAKE_EDGE
+ * - \ref TPWM_BRAKE_LEVEL
+ *
+ * @return None
+ *
+ * @details This function is used to enable fault brake interrupt.
+ * @note The register write-protection function should be disabled before using this function.
+ */
+void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource)
+{
+ timer->PWMINTEN1 |= u32IntSource;
+}
+
+/**
+ * @brief Disable Fault Brake Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32IntSource Interrupt source, could be one of following source
+ * - \ref TPWM_BRAKE_EDGE
+ * - \ref TPWM_BRAKE_LEVEL
+ *
+ * @return None
+ *
+ * @details This function is used to disable fault brake interrupt.
+ * @note The register write-protection function should be disabled before using this function.
+ */
+void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource)
+{
+ timer->PWMINTEN1 &= ~u32IntSource;
+}
+
+/**
+ * @brief Indicate Fault Brake Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32IntSource Interrupt source, could be one of following source
+ * - \ref TPWM_BRAKE_EDGE
+ * - \ref TPWM_BRAKE_LEVEL
+ *
+ * @return Fault brake interrupt flag of specified source
+ * @retval 0 Fault brake interrupt did not occurred
+ * @retval 1 Fault brake interrupt occurred
+ *
+ * @details This function is used to indicate fault brake interrupt flag occurred or not of selected source.
+ */
+uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource)
+{
+ return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource))? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Fault Brake Interrupt Flags
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32IntSource Interrupt source, could be one of following source
+ * - \ref TPWM_BRAKE_EDGE
+ * - \ref TPWM_BRAKE_LEVEL
+ *
+ * @return None
+ *
+ * @details This function is used to clear fault brake interrupt flags of selected source.
+ * @note The register write-protection function should be disabled before using this function.
+ */
+void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource)
+{
+ timer->PWMINTSTS1 = (0x3UL << u32IntSource);
+}
+
+/**
+ * @brief Enable load mode of selected channel
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32LoadMode Timer PWM counter loading mode, could be one of following mode
+ * - \ref TPWM_LOAD_MODE_PERIOD
+ * - \ref TPWM_LOAD_MODE_IMMEDIATE
+ * - \ref TPWM_LOAD_MODE_CENTER
+ *
+ * @return None
+ *
+ * @details This function is used to enable load mode of selected channel.
+ * @note The default loading mode is period loading mode.
+ */
+void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode)
+{
+ timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode;
+}
+
+/**
+ * @brief Enable brake pin noise filter function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32BrakePinSrc The external brake pin source, could be one of following source
+ * - \ref TPWM_TM_BRAKE0
+ * - \ref TPWM_TM_BRAKE1
+ * - \ref TPWM_TM_BRAKE2
+ * - \ref TPWM_TM_BRAKE3
+ * @param[in] u32DebounceCnt This value controls the real debounce sample time.
+ * The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt).
+ * @param[in] u32ClkSrcSel Brake pin detector debounce clock source, could be one of following source
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_1
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_2
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_4
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_8
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_16
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_32
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_64
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_128
+ *
+ * @return None
+ *
+ * @details This function is used to enable external brake pin detector noise filter function.
+ */
+void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel)
+{
+ timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) |
+ (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) |
+ (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) |
+ (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk;
+}
+
+/**
+ * @brief Disable brake pin noise filter function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable external brake pin detector noise filter function.
+ */
+void TPWM_DisableBrakePinDebounce(TIMER_T *timer)
+{
+ timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk;
+}
+
+
+/**
+ * @brief Enable brake pin inverse function
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @return None
+ * @details This function is used to enable PWM brake pin inverse function.
+ */
+void TPWM_EnableBrakePinInverse(TIMER_T *timer)
+{
+ timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk;
+}
+
+/**
+ * @brief Disable brake pin inverse function
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @return None
+ * @details This function is used to disable PWM brake pin inverse function.
+ */
+void TPWM_DisableBrakePinInverse(TIMER_T *timer)
+{
+ timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk;
+}
+
+/**
+ * @brief Set brake pin source
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32BrakePinNum Brake pin selection. One of the following:
+ * - \ref TPWM_TM_BRAKE0
+ * - \ref TPWM_TM_BRAKE1
+ * - \ref TPWM_TM_BRAKE2
+ * - \ref TPWM_TM_BRAKE3
+ * @return None
+ * @details This function is used to set PWM brake pin source.
+ */
+void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum)
+{
+ timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos));
+}
+
+
+/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TIMER_PWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_trng.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_trng.c
new file mode 100644
index 00000000000..98449d1a85d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_trng.c
@@ -0,0 +1,172 @@
+/**************************************************************************//**
+ * @file trng.c
+ * @version V1.00
+ * @brief M480 series TRNG driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup TRNG_Driver TRNG Driver
+ @{
+*/
+
+
+/** @addtogroup TRNG_EXPORTED_FUNCTIONS TRNG Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Initialize TRNG hardware.
+ * @return None
+ */
+void TRNG_Open(void)
+{
+ SYS->IPRST1 |= SYS_IPRST1_TRNGRST_Msk;
+ SYS->IPRST1 ^= SYS_IPRST1_TRNGRST_Msk;
+
+ TRNG->CTL |= TRNG_CTL_TRNGEN_Msk;
+
+ TRNG->ACT |= TRNG_ACT_ACT_Msk;
+
+ /* Waiting for ready */
+ while ((TRNG->CTL & TRNG_CTL_READY_Msk) == 0);
+}
+
+
+/**
+ * @brief Generate a 32-bits random number word.
+ * @param[out] u32RndNum The output 32-bits word random number.
+ *
+ * @return Success or time-out.
+ * @retval 0 Success
+ * @retval -1 Time-out. TRNG hardware may not be enabled.
+ */
+int32_t TRNG_GenWord(uint32_t *u32RndNum)
+{
+ uint32_t i, u32Reg, timeout;
+
+ *u32RndNum = 0;
+ u32Reg = TRNG->CTL;
+
+ for (i = 0; i < 4; i++)
+ {
+ TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg;
+
+ /* TRNG should generate one byte per 125*8 us */
+ for (timeout = (CLK_GetHCLKFreq() / 100); timeout > 0; timeout--)
+ {
+ if (TRNG->CTL & TRNG_CTL_DVIF_Msk)
+ break;
+ }
+
+ if (timeout == 0)
+ return -1;
+
+ *u32RndNum |= ((TRNG->DATA & 0xff) << i*8);
+
+ }
+ return 0;
+}
+
+/**
+ * @brief Generate a big number in binary format.
+ * @param[out] u8BigNum The output big number.
+ * @param[in] i32Len Request bit length of the output big number. It must be multiple of 8.
+ *
+ * @return Success or time-out.
+ * @retval 0 Success
+ * @retval -1 Time-out. TRNG hardware may not be enabled.
+ */
+int32_t TRNG_GenBignum(uint8_t u8BigNum[], int32_t i32Len)
+{
+ uint32_t i, u32Reg, timeout;
+
+ u32Reg = TRNG->CTL;
+
+ for (i = 0; i < i32Len/8; i++)
+ {
+ TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg;
+
+ /* TRNG should generate one byte per 125*8 us */
+ for (timeout = (CLK_GetHCLKFreq() / 100); timeout > 0; timeout--)
+ {
+ if (TRNG->CTL & TRNG_CTL_DVIF_Msk)
+ break;
+ }
+
+ if (timeout == 0)
+ return -1;
+
+ u8BigNum[i] = (TRNG->DATA & 0xff);
+ }
+ return 0;
+}
+
+/**
+ * @brief Generate a big number in hex format.
+ * @param[out] cBigNumHex The output hex format big number.
+ * @param[in] i32Len Request bit length of the output big number. It must be multiple of 8.
+ *
+ * @return Success or time-out.
+ * @retval 0 Success
+ * @retval -1 Time-out. TRNG hardware may not be enabled.
+ */
+int32_t TRNG_GenBignumHex(char cBigNumHex[], int32_t i32Len)
+{
+ uint32_t i, idx, u32Reg, timeout;
+ uint32_t data;
+
+ u32Reg = TRNG->CTL;
+ idx = 0;
+ for (i = 0; i < i32Len/8; i++)
+ {
+ TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg;
+
+ /* TRNG should generate one byte per 125*8 us */
+ for (timeout = (CLK_GetHCLKFreq() / 100); timeout > 0; timeout--)
+ {
+ if (TRNG->CTL & TRNG_CTL_DVIF_Msk)
+ break;
+ }
+
+ if (timeout == 0)
+ return -1;
+
+ data = (TRNG->DATA & 0xff);
+
+ if (data >= 0xA0)
+ cBigNumHex[idx++] = ((data >> 4) & 0xf) - 10 + 'A';
+ else
+ cBigNumHex[idx++] = ((data >> 4) & 0xf) + '0';
+
+ data &= 0xf;
+ if (data >= 0xA)
+ cBigNumHex[idx++] = data - 10 + 'A';
+ else
+ cBigNumHex[idx++] = data + '0';
+ }
+ cBigNumHex[idx] = 0;
+ return 0;
+}
+
+
+/*@}*/ /* end of group TRNG_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TRNG_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2019 Nuvoton Technology Corp. ***/
+
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_uart.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_uart.c
new file mode 100644
index 00000000000..9687f89ad6f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_uart.c
@@ -0,0 +1,656 @@
+/**************************************************************************//**
+ * @file uart.c
+ * @version V3.00
+ * @brief M480 series UART driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup UART_Driver UART Driver
+ @{
+*/
+
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear UART specified interrupt flag
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module.
+ * - \ref UART_INTSTS_LININT_Msk : LIN bus interrupt
+ * - \ref UART_INTSTS_WKIF_Msk : Wake-up interrupt
+ * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
+ * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt
+ * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt
+ *
+ * @return None
+ *
+ * @details The function is used to clear UART specified interrupt flag.
+ */
+
+void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag)
+{
+
+ if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */
+ {
+ uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk;
+ uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
+ }
+
+ if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */
+ {
+ uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
+ }
+ else
+ {
+ }
+
+ if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */
+ {
+ uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
+ }
+
+ if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */
+ {
+ uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk |
+ UART_WKSTS_RFRTWKF_Msk |UART_WKSTS_RS485WKF_Msk |
+ UART_WKSTS_TOUTWKF_Msk;
+ }
+
+ if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */
+ {
+ uart->INTSTS = UART_INTSTS_LINIF_Msk;
+ uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk |
+ UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
+ UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ;
+ }
+}
+
+
+/**
+ * @brief Disable UART interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to disable UART interrupt.
+ */
+void UART_Close(UART_T* uart)
+{
+ uart->INTEN = 0ul;
+}
+
+
+/**
+ * @brief Disable UART auto flow control function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to disable UART auto flow control.
+ */
+void UART_DisableFlowCtrl(UART_T* uart)
+{
+ uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
+}
+
+
+/**
+ * @brief Disable UART specified interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module.
+ * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
+ *
+ * @return None
+ *
+ * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
+ */
+void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag)
+{
+ /* Disable UART specified interrupt */
+ UART_DISABLE_INT(uart, u32InterruptFlag);
+}
+
+
+/**
+ * @brief Enable UART auto flow control function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to Enable UART auto flow control.
+ */
+void UART_EnableFlowCtrl(UART_T* uart)
+{
+ /* Set RTS pin output is low level active */
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+
+ /* Set CTS pin input is low level active */
+ uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
+
+ /* Set RTS and CTS auto flow control enable */
+ uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
+}
+
+
+/**
+ * @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module:
+ * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
+ *
+ * @return None
+ *
+ * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ */
+void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag)
+{
+ /* Enable UART specified interrupt */
+ UART_ENABLE_INT(uart, u32InterruptFlag);
+}
+
+
+/**
+ * @brief Open and set UART function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32baudrate The baudrate of UART module.
+ *
+ * @return None
+ *
+ * @details This function use to enable UART function and set baud-rate.
+ */
+void UART_Open(UART_T* uart, uint32_t u32baudrate)
+{
+ uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
+ uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC};
+ uint32_t u32Baud_Div = 0ul;
+
+
+ if(uart==(UART_T*)UART0)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
+ }
+ else if(uart==(UART_T*)UART1)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
+ }
+ else if(uart==(UART_T*)UART2)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
+ }
+ else if(uart==(UART_T*)UART3)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
+ }
+ else if(uart==(UART_T*)UART4)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
+ }
+ else if(uart==(UART_T*)UART5)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
+ }
+
+ /* Select UART function */
+ uart->FUNCSEL = UART_FUNCSEL_UART;
+
+ /* Set UART line configuration */
+ uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
+
+ /* Set UART Rx and RTS trigger level */
+ uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if(u32UartClkSrcSel == 1ul)
+ {
+ u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+ }
+
+ /* Set UART baud rate */
+ if(u32baudrate != 0ul)
+ {
+ u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+ if(u32Baud_Div > 0xFFFFul)
+ {
+ uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+ }
+ else
+ {
+ uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+ }
+ }
+}
+
+
+/**
+ * @brief Read UART data
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO.
+ * @param[in] u32ReadBytes The the read bytes number of data.
+ *
+ * @return u32Count Receive byte count
+ *
+ * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
+ */
+uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+ uint32_t u32Count, u32delayno;
+ uint32_t u32Exit = 0ul;
+
+ for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
+ {
+ u32delayno = 0ul;
+
+ while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */
+ {
+ u32delayno++;
+ if(u32delayno >= 0x40000000ul)
+ {
+ u32Exit = 1ul;
+ break;
+ }
+ else
+ {
+ }
+ }
+
+ if(u32Exit == 1ul)
+ {
+ break;
+ }
+ else
+ {
+ pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */
+ }
+ }
+
+ return u32Count;
+
+}
+
+
+/**
+ * @brief Set UART line configuration
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32baudrate The register value of baudrate of UART module.
+ * If u32baudrate = 0, UART baudrate will not change.
+ * @param[in] u32data_width The data length of UART module.
+ * - \ref UART_WORD_LEN_5
+ * - \ref UART_WORD_LEN_6
+ * - \ref UART_WORD_LEN_7
+ * - \ref UART_WORD_LEN_8
+ * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module.
+ * - \ref UART_PARITY_NONE
+ * - \ref UART_PARITY_ODD
+ * - \ref UART_PARITY_EVEN
+ * - \ref UART_PARITY_MARK
+ * - \ref UART_PARITY_SPACE
+ * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module.
+ * - \ref UART_STOP_BIT_1
+ * - \ref UART_STOP_BIT_1_5
+ * - \ref UART_STOP_BIT_2
+ *
+ * @return None
+ *
+ * @details This function use to config UART line setting.
+ */
+void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
+{
+ uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
+ uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC};
+ uint32_t u32Baud_Div = 0ul;
+
+
+ if(uart==(UART_T*)UART0)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
+ }
+ else if(uart==(UART_T*)UART1)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
+ }
+ else if(uart==(UART_T*)UART2)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
+ }
+ else if(uart==(UART_T*)UART3)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
+ }
+ else if(uart==(UART_T*)UART4)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
+ }
+ else if(uart==(UART_T*)UART5)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
+ }
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if(u32UartClkSrcSel == 1ul)
+ {
+ u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ }
+
+ /* Set UART baud rate */
+ if(u32baudrate != 0ul)
+ {
+ u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+ if(u32Baud_Div > 0xFFFFul)
+ {
+ uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+ }
+ else
+ {
+ uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+ }
+ }
+
+ /* Set UART line configuration */
+ uart->LINE = u32data_width | u32parity | u32stop_bits;
+}
+
+
+/**
+ * @brief Set Rx timeout count
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32TOC Rx timeout counter.
+ *
+ * @return None
+ *
+ * @details This function use to set Rx timeout count.
+ */
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
+{
+ /* Set time-out interrupt comparator */
+ uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
+
+ /* Set time-out counter enable */
+ uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
+}
+
+
+/**
+ * @brief Select and configure IrDA function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32Buadrate The baudrate of UART module.
+ * @param[in] u32Direction The direction of UART module in IrDA mode:
+ * - \ref UART_IRDA_TXEN
+ * - \ref UART_IRDA_RXEN
+ *
+ * @return None
+ *
+ * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
+ */
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
+{
+ uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
+ uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC};
+ uint32_t u32Baud_Div;
+
+ /* Select IrDA function mode */
+ uart->FUNCSEL = UART_FUNCSEL_IrDA;
+
+
+ if(uart==UART0)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
+ }
+ else if(uart==UART1)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
+ }
+ else if(uart==UART2)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
+ }
+ else if(uart==UART3)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
+ }
+ else if(uart==UART4)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
+ }
+ else if(uart==UART5)
+ {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
+ }
+
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if(u32UartClkSrcSel == 1ul)
+ {
+ u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ }
+
+ /* Set UART IrDA baud rate in mode 0 */
+ if(u32Buadrate != 0ul)
+ {
+ u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate);
+
+ if(u32Baud_Div < 0xFFFFul)
+ {
+ uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
+ }
+ else
+ {
+ }
+ }
+
+ /* Configure IrDA relative settings */
+ if(u32Direction == UART_IRDA_RXEN)
+ {
+ uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/
+ uart->IRDA &= ~UART_IRDA_TXEN_Msk;
+ }
+ else
+ {
+ uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/
+ uart->IRDA |= UART_IRDA_TXEN_Msk;
+ }
+
+}
+
+
+/**
+ * @brief Select and configure RS485 function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32Mode The operation mode(NMM/AUD/AAD).
+ * - \ref UART_ALTCTL_RS485NMM_Msk
+ * - \ref UART_ALTCTL_RS485AUD_Msk
+ * - \ref UART_ALTCTL_RS485AAD_Msk
+ * @param[in] u32Addr The RS485 address.
+ *
+ * @return None
+ *
+ * @details The function is used to set RS485 relative setting.
+ */
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
+{
+ /* Select UART RS485 function mode */
+ uart->FUNCSEL = UART_FUNCSEL_RS485;
+
+ /* Set RS585 configuration */
+ uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
+ uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
+}
+
+
+/**
+ * @brief Select and configure LIN function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32Mode The LIN direction :
+ * - \ref UART_ALTCTL_LINTXEN_Msk
+ * - \ref UART_ALTCTL_LINRXEN_Msk
+ * @param[in] u32BreakLength The break field length.
+ *
+ * @return None
+ *
+ * @details The function is used to set LIN relative setting.
+ */
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
+{
+ /* Select LIN function mode */
+ uart->FUNCSEL = UART_FUNCSEL_LIN;
+
+ /* Select LIN function setting : Tx enable, Rx enable and break field length */
+ uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
+ uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
+}
+
+
+/**
+ * @brief Write UART data
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
+ * @param[out] u32WriteBytes The byte number of data.
+ *
+ * @return u32Count transfer byte count
+ *
+ * @details The function is to write data into TX buffer to transmit data by UART.
+ */
+uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+ uint32_t u32Count, u32delayno;
+ uint32_t u32Exit = 0ul;
+
+ for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
+ {
+ u32delayno = 0ul;
+ while(uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) /* Check Tx Full */
+ {
+ u32delayno++;
+ if(u32delayno >= 0x40000000ul)
+ {
+ u32Exit = 1ul;
+ break;
+ }
+ else
+ {
+ }
+ }
+
+ if(u32Exit == 1ul)
+ {
+ break;
+ }
+ else
+ {
+ uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
+ }
+ }
+
+ return u32Count;
+}
+
+
+/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group UART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
+
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usbd.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usbd.c
new file mode 100644
index 00000000000..fd783140238
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usbd.c
@@ -0,0 +1,745 @@
+/**************************************************************************//**
+ * @file usbd.c
+ * @version V1.00
+ * @brief M480 USBD driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include "NuMicro.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup USBD_Driver USBD Driver
+ @{
+*/
+
+
+/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+ @{
+*/
+
+/* Global variables for Control Pipe */
+uint8_t g_usbd_SetupPacket[8] = {0ul}; /*!< Setup packet buffer */
+volatile uint8_t g_usbd_RemoteWakeupEn = 0ul; /*!< Remote wake up function enable flag */
+
+/**
+ * @cond HIDDEN_SYMBOLS
+ */
+static uint8_t *g_usbd_CtrlInPointer = 0;
+static uint8_t *g_usbd_CtrlOutPointer = 0;
+static volatile uint32_t g_usbd_CtrlInSize = 0ul;
+static volatile uint32_t g_usbd_CtrlOutSize = 0ul;
+static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0ul;
+static volatile uint32_t g_usbd_UsbAddr = 0ul;
+static volatile uint32_t g_usbd_UsbConfig = 0ul;
+static volatile uint32_t g_usbd_CtrlMaxPktSize = 8ul;
+static volatile uint32_t g_usbd_UsbAltInterface = 0ul;
+static volatile uint32_t g_usbd_CtrlOutToggle = 0;
+static volatile uint8_t g_usbd_CtrlInZeroFlag = 0ul;
+/**
+ * @endcond
+ */
+
+const S_USBD_INFO_T *g_usbd_sInfo; /*!< A pointer for USB information structure */
+
+VENDOR_REQ g_usbd_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */
+CLASS_REQ g_usbd_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */
+SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */
+SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */
+uint32_t g_u32EpStallLock = 0ul; /*!< Bit map flag to lock specified EP when SET_FEATURE */
+
+/**
+ * @brief This function makes USBD module to be ready to use
+ *
+ * @param[in] param The structure of USBD information.
+ * @param[in] pfnClassReq USB Class request callback function.
+ * @param[in] pfnSetInterface USB Set Interface request callback function.
+ *
+ * @return None
+ *
+ * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus.
+ */
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
+{
+ g_usbd_sInfo = param;
+ g_usbd_pfnClassRequest = pfnClassReq;
+ g_usbd_pfnSetInterface = pfnSetInterface;
+
+ /* get EP0 maximum packet size */
+ g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7];
+
+ /* Initial USB engine */
+ USBD->ATTR = 0x6D0ul;
+ /* Force SE0 */
+ USBD_SET_SE0();
+}
+
+/**
+ * @brief This function makes USB host to recognize the device
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer.
+ */
+void USBD_Start(void)
+{
+ /* Disable software-disconnect function */
+ USBD_CLR_SE0();
+ USBD->ATTR = 0x7D0ul;
+
+ /* Clear USB-related interrupts before enable interrupt */
+ USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+
+ /* Enable USB-related interrupts. */
+ USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+}
+
+/**
+ * @brief Get the received SETUP packet
+ *
+ * @param[in] buf A buffer pointer used to store 8-byte SETUP packet.
+ *
+ * @return None
+ *
+ * @details Store SETUP packet to a user-specified buffer.
+ *
+ */
+void USBD_GetSetupPacket(uint8_t *buf)
+{
+ USBD_MemCopy(buf, g_usbd_SetupPacket, 8ul);
+}
+
+/**
+ * @brief Process SETUP packet
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Parse SETUP packet and perform the corresponding action.
+ *
+ */
+void USBD_ProcessSetupPacket(void)
+{
+ g_usbd_CtrlOutToggle = 0;
+ /* Get SETUP packet from USB buffer */
+ USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8ul);
+
+ /* Check the request type */
+ switch(g_usbd_SetupPacket[0] & 0x60ul)
+ {
+ case REQ_STANDARD:
+ {
+ USBD_StandardRequest();
+ break;
+ }
+ case REQ_CLASS:
+ {
+ if(g_usbd_pfnClassRequest != NULL)
+ {
+ g_usbd_pfnClassRequest();
+ }
+ break;
+ }
+ case REQ_VENDOR:
+ {
+ if(g_usbd_pfnVendorRequest != NULL)
+ {
+ g_usbd_pfnVendorRequest();
+ }
+ break;
+ }
+ default:
+ {
+ /* Setup error, stall the device */
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Process GetDescriptor request
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Parse GetDescriptor request and perform the corresponding action.
+ *
+ */
+void USBD_GetDescriptor(void)
+{
+ uint32_t u32Len;
+
+ g_usbd_CtrlInZeroFlag = (uint8_t)0ul;
+ u32Len = 0ul;
+ u32Len = g_usbd_SetupPacket[7];
+ u32Len <<= 8ul;
+ u32Len += g_usbd_SetupPacket[6];
+
+ switch(g_usbd_SetupPacket[3])
+ {
+ /* Get Device Descriptor */
+ case DESC_DEVICE:
+ {
+ u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE);
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len);
+
+ break;
+ }
+ /* Get Configuration Descriptor */
+ case DESC_CONFIG:
+ {
+ uint32_t u32TotalLen;
+
+ u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3];
+ u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
+
+ if (u32Len > u32TotalLen)
+ {
+ u32Len = u32TotalLen;
+ if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul)
+ {
+ g_usbd_CtrlInZeroFlag = (uint8_t)1ul;
+ }
+ }
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len);
+
+ break;
+ }
+
+ /* Get BOS Descriptor */
+ case DESC_BOS:
+ {
+ if (g_usbd_sInfo->gu8BosDesc == 0)
+ {
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ }
+ else
+ {
+ u32Len = USBD_Minimum(u32Len, LEN_BOS+LEN_BOSCAP);
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8BosDesc, u32Len);
+ }
+ break;
+ }
+ /* Get HID Descriptor */
+ case DESC_HID:
+ {
+ /* CV3.0 HID Class Descriptor Test,
+ Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */
+ uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */
+ u32Len = USBD_Minimum(u32Len, LEN_HID);
+ u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]];
+ USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len);
+
+ break;
+ }
+ /* Get Report Descriptor */
+ case DESC_HID_RPT:
+ {
+ if (u32Len > g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]])
+ {
+ u32Len = g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]];
+ if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul)
+ {
+ g_usbd_CtrlInZeroFlag = (uint8_t)1ul;
+ }
+ }
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len);
+ break;
+ }
+ /* Get String Descriptor */
+ case DESC_STRING:
+ {
+ /* Get String Descriptor */
+ if(g_usbd_SetupPacket[2] < 4ul)
+ {
+ if (u32Len > g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0])
+ {
+ u32Len = g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0];
+ if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul)
+ {
+ g_usbd_CtrlInZeroFlag = (uint8_t)1ul;
+ }
+ }
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len);
+ break;
+ }
+ else
+ {
+ /* Not support. Reply STALL. */
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ break;
+ }
+ }
+ default:
+ /* Not support. Reply STALL.*/
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ break;
+ }
+}
+
+/**
+ * @brief Process standard request
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Parse standard request and perform the corresponding action.
+ *
+ */
+void USBD_StandardRequest(void)
+{
+ uint32_t addr;
+ /* clear global variables for new request */
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0ul;
+
+ if((g_usbd_SetupPacket[0] & 0x80ul) == 0x80ul) /* request data transfer direction */
+ {
+ /* Device to host */
+ switch(g_usbd_SetupPacket[1])
+ {
+ case GET_CONFIGURATION:
+ {
+ /* Return current configuration setting */
+ /* Data stage */
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+ M8(addr) = (uint8_t)g_usbd_UsbConfig;
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 1ul);
+ /* Status stage */
+ USBD_PrepareCtrlOut(0, 0ul);
+ break;
+ }
+ case GET_DESCRIPTOR:
+ {
+ USBD_GetDescriptor();
+ USBD_PrepareCtrlOut(0, 0ul); /* For status stage */
+ break;
+ }
+ case GET_INTERFACE:
+ {
+ /* Return current interface setting */
+ /* Data stage */
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+ M8(addr) = (uint8_t)g_usbd_UsbAltInterface;
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 1ul);
+ /* Status stage */
+ USBD_PrepareCtrlOut(0, 0ul);
+ break;
+ }
+ case GET_STATUS:
+ {
+ /* Device */
+ if(g_usbd_SetupPacket[0] == 0x80ul)
+ {
+ uint8_t u8Tmp;
+
+ u8Tmp = (uint8_t)0ul;
+ if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul)
+ {
+ u8Tmp |= (uint8_t)1ul; /* Self-Powered/Bus-Powered.*/
+ }
+ if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x20ul) == 0x20ul)
+ {
+ u8Tmp |= (uint8_t)(g_usbd_RemoteWakeupEn << 1ul); /* Remote wake up */
+ }
+
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+ M8(addr) = u8Tmp;
+
+ }
+ /* Interface */
+ else if(g_usbd_SetupPacket[0] == 0x81ul)
+ {
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+ M8(addr) = (uint8_t)0ul;
+ }
+ /* Endpoint */
+ else if(g_usbd_SetupPacket[0] == 0x82ul)
+ {
+ uint8_t ep = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul);
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+ M8(addr) = (uint8_t)(USBD_GetStall(ep) ? 1ul : 0ul);
+ }
+
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1ul;
+ M8(addr) = (uint8_t)0ul;
+ /* Data stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 2ul);
+ /* Status stage */
+ USBD_PrepareCtrlOut(0, 0ul);
+ break;
+ }
+ default:
+ {
+ /* Setup error, stall the device */
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ break;
+ }
+ }
+ }
+ else
+ {
+ /* Host to device */
+ switch(g_usbd_SetupPacket[1])
+ {
+ case CLEAR_FEATURE:
+ {
+ if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
+ {
+ uint32_t epNum, i;
+
+ /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
+ a flag: g_u32EpStallLock is added to support it */
+ epNum = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul);
+ for(i = 0ul; i < USBD_MAX_EP; i++)
+ {
+ if(((USBD->EP[i].CFG & 0xFul) == epNum) && ((g_u32EpStallLock & (1ul << i)) == 0ul))
+ {
+ USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk;
+ USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
+ }
+ }
+ }
+ else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
+ {
+ g_usbd_RemoteWakeupEn = (uint8_t)0;
+ }
+
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+ break;
+ }
+ case SET_ADDRESS:
+ {
+ g_usbd_UsbAddr = g_usbd_SetupPacket[2];
+ /* Status Stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+
+ break;
+ }
+ case SET_CONFIGURATION:
+ {
+ g_usbd_UsbConfig = g_usbd_SetupPacket[2];
+
+ if(g_usbd_pfnSetConfigCallback)
+ {
+ g_usbd_pfnSetConfigCallback();
+ }
+
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+ break;
+ }
+ case SET_FEATURE:
+ {
+ if( (g_usbd_SetupPacket[0] & 0xFul) == 0ul ) /* 0: device */
+ {
+ if((g_usbd_SetupPacket[2] == 3ul) && (g_usbd_SetupPacket[3] == 0ul)) /* 3: HNP enable */
+ {
+ OTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk);
+ }
+ }
+ if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
+ {
+ USBD_SetStall((uint8_t)(g_usbd_SetupPacket[4] & 0xFul));
+ }
+ else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
+ {
+ g_usbd_RemoteWakeupEn = (uint8_t)1ul;
+ }
+
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+
+ break;
+ }
+ case SET_INTERFACE:
+ {
+ g_usbd_UsbAltInterface = g_usbd_SetupPacket[2];
+ if(g_usbd_pfnSetInterface != NULL)
+ {
+ g_usbd_pfnSetInterface(g_usbd_UsbAltInterface);
+ }
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+ break;
+ }
+ default:
+ {
+ /* Setup error, stall the device */
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ break;
+ }
+ }
+ }
+}
+
+/**
+ * @brief Prepare the first Control IN pipe
+ *
+ * @param[in] pu8Buf The pointer of data sent to USB host.
+ * @param[in] u32Size The IN transfer size.
+ *
+ * @return None
+ *
+ * @details Prepare data for Control IN transfer.
+ *
+ */
+void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size)
+{
+ uint32_t addr;
+ if(u32Size > g_usbd_CtrlMaxPktSize)
+ {
+ /* Data size > MXPLD */
+ g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize;
+ g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize;
+ USBD_SET_DATA1(EP0);
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+ USBD_MemCopy((uint8_t *)addr, pu8Buf, g_usbd_CtrlMaxPktSize);
+ USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
+ }
+ else
+ {
+ /* Data size <= MXPLD */
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0ul;
+ USBD_SET_DATA1(EP0);
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+ USBD_MemCopy((uint8_t *)addr, pu8Buf, u32Size);
+ USBD_SET_PAYLOAD_LEN(EP0, u32Size);
+ }
+}
+
+/**
+ * @brief Repeat Control IN pipe
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function processes the remained data of Control IN transfer.
+ *
+ */
+void USBD_CtrlIn(void)
+{
+ uint32_t addr;
+
+ if(g_usbd_CtrlInSize)
+ {
+ /* Process remained data */
+ if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize)
+ {
+ /* Data size > MXPLD */
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+ USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize);
+ USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
+ g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize;
+ g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize;
+ }
+ else
+ {
+ /* Data size <= MXPLD */
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+ USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize);
+ USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize);
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0ul;
+ }
+ }
+ else
+ {
+ /* In ACK for Set address */
+ if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS))
+ {
+ addr = USBD_GET_ADDR();
+ if((addr != g_usbd_UsbAddr) && (addr == 0ul))
+ {
+ USBD_SET_ADDR(g_usbd_UsbAddr);
+ }
+ }
+
+ /* For the case of data size is integral times maximum packet size */
+ if(g_usbd_CtrlInZeroFlag)
+ {
+ USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+ g_usbd_CtrlInZeroFlag = (uint8_t)0ul;
+ }
+ }
+}
+
+/**
+ * @brief Prepare the first Control OUT pipe
+ *
+ * @param[in] pu8Buf The pointer of data received from USB host.
+ * @param[in] u32Size The OUT transfer size.
+ *
+ * @return None
+ *
+ * @details This function is used to prepare the first Control OUT transfer.
+ *
+ */
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
+{
+ g_usbd_CtrlOutPointer = pu8Buf;
+ g_usbd_CtrlOutSize = 0ul;
+ g_usbd_CtrlOutSizeLimit = u32Size;
+ USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
+}
+
+/**
+ * @brief Repeat Control OUT pipe
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function processes the successive Control OUT transfer.
+ *
+ */
+void USBD_CtrlOut(void)
+{
+ uint32_t u32Size;
+ uint32_t addr;
+
+ if (g_usbd_CtrlOutToggle != (USBD->EPSTS0 & USBD_EPSTS0_EPSTS1_Msk))
+ {
+ g_usbd_CtrlOutToggle = USBD->EPSTS0 & USBD_EPSTS0_EPSTS1_Msk;
+ if (g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit)
+ {
+ u32Size = USBD_GET_PAYLOAD_LEN(EP1);
+ addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1);
+ USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)addr, u32Size);
+ g_usbd_CtrlOutPointer += u32Size;
+ g_usbd_CtrlOutSize += u32Size;
+
+ if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit)
+ {
+ USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
+ }
+ }
+ }
+ else
+ {
+ USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
+ }
+}
+
+/**
+ * @brief Reset software flags
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function resets all variables for protocol and resets USB device address to 0.
+ *
+ */
+void USBD_SwReset(void)
+{
+ uint32_t i;
+
+ /* Reset all variables for protocol */
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0ul;
+ g_usbd_CtrlOutPointer = 0;
+ g_usbd_CtrlOutSize = 0ul;
+ g_usbd_CtrlOutSizeLimit = 0ul;
+ g_u32EpStallLock = 0ul;
+ memset(g_usbd_SetupPacket, 0, 8ul);
+
+ /* Reset PID DATA0 */
+ for(i=0ul; iEP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
+ }
+
+ /* Reset USB device address */
+ USBD_SET_ADDR(0ul);
+}
+
+/**
+ * @brief USBD Set Vendor Request
+ *
+ * @param[in] pfnVendorReq Vendor Request Callback Function
+ *
+ * @return None
+ *
+ * @details This function is used to set USBD vendor request callback function
+ */
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
+{
+ g_usbd_pfnVendorRequest = pfnVendorReq;
+}
+
+/**
+ * @brief The callback function which called when get SET CONFIGURATION request
+ *
+ * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request
+ *
+ * @return None
+ *
+ * @details This function is used to set the callback function which will be called at SET CONFIGURATION request.
+ */
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback)
+{
+ g_usbd_pfnSetConfigCallback = pfnSetConfigCallback;
+}
+
+
+/**
+ * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request.
+ *
+ * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked
+ *
+ * @return None
+ *
+ * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request.
+ * If ep stall locked, user needs to reset USB device or re-configure device to clear it.
+ */
+void USBD_LockEpStall(uint32_t u32EpBitmap)
+{
+ g_u32EpStallLock = u32EpBitmap;
+}
+
+
+/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USBD_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_i2c.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_i2c.c
new file mode 100644
index 00000000000..ee62fca567b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_i2c.c
@@ -0,0 +1,1679 @@
+/****************************************************************************//**
+ * @file usci_i2c.c
+ * @version V3.00
+ * @brief M480 series USCI I2C(UI2C) driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup USCI_I2C_Driver USCI_I2C Driver
+ @{
+*/
+
+
+/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function makes USCI_I2C module be ready and set the wanted bus clock
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u32BusClock The target bus speed of USCI_I2C module.
+ *
+ * @return Actual USCI_I2C bus clock frequency.
+ *
+ * @details Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format).
+ */
+uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock)
+{
+ uint32_t u32ClkDiv;
+ uint32_t u32Pclk;
+
+ if( ui2c == UI2C0 )
+ {
+ u32Pclk = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32Pclk = CLK_GetPCLK1Freq();
+ }
+
+ u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */
+
+ /* Enable USCI_I2C protocol */
+ ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk;
+ ui2c->CTL = 4U << UI2C_CTL_FUNMODE_Pos;
+
+ /* Data format configuration */
+ /* 8 bit data length */
+ ui2c->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk;
+ ui2c->LINECTL |= 8U << UI2C_LINECTL_DWIDTH_Pos;
+
+ /* MSB data format */
+ ui2c->LINECTL &= ~UI2C_LINECTL_LSB_Msk;
+
+ /* Set USCI_I2C bus clock */
+ ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk;
+ ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos);
+ ui2c->PROTCTL |= UI2C_PROTCTL_PROTEN_Msk;
+
+ return ( u32Pclk / ((u32ClkDiv+1U)<<1U) );
+}
+
+/**
+ * @brief This function closes the USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details Close USCI_I2C protocol function.
+ */
+void UI2C_Close(UI2C_T *ui2c)
+{
+ /* Disable USCI_I2C function */
+ ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk;
+}
+
+/**
+ * @brief This function clears the time-out flag
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details Clear time-out flag when time-out flag is set.
+ */
+void UI2C_ClearTimeoutFlag(UI2C_T *ui2c)
+{
+ ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk;
+}
+
+/**
+ * @brief This function sets the control bit of the USCI_I2C module.
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8Start Set START bit to USCI_I2C module.
+ * @param[in] u8Stop Set STOP bit to USCI_I2C module.
+ * @param[in] u8Ptrg Set PTRG bit to USCI_I2C module.
+ * @param[in] u8Ack Set ACK bit to USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details The function set USCI_I2C control bit of USCI_I2C bus protocol.
+ */
+void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack)
+{
+ uint32_t u32Reg = 0U;
+ uint32_t u32Val = ui2c->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk);
+
+ if (u8Start)
+ {
+ u32Reg |= UI2C_PROTCTL_STA_Msk;
+ }
+ if (u8Stop)
+ {
+ u32Reg |= UI2C_PROTCTL_STO_Msk;
+ }
+ if (u8Ptrg)
+ {
+ u32Reg |= UI2C_PROTCTL_PTRG_Msk;
+ }
+ if (u8Ack)
+ {
+ u32Reg |= UI2C_PROTCTL_AA_Msk;
+ }
+
+ ui2c->PROTCTL = u32Val | u32Reg;
+}
+
+/**
+ * @brief This function disables the interrupt of USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to an interrupt enable bit.
+ * This parameter decides which interrupts will be disabled. It is combination of:
+ * - \ref UI2C_TO_INT_MASK
+ * - \ref UI2C_STAR_INT_MASK
+ * - \ref UI2C_STOR_INT_MASK
+ * - \ref UI2C_NACK_INT_MASK
+ * - \ref UI2C_ARBLO_INT_MASK
+ * - \ref UI2C_ERR_INT_MASK
+ * - \ref UI2C_ACK_INT_MASK
+ *
+ * @return None
+ *
+ * @details The function is used to disable USCI_I2C bus interrupt events.
+ */
+void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask)
+{
+ /* Disable time-out interrupt flag */
+ if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK)
+ {
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk;
+ }
+
+ /* Disable start condition received interrupt flag */
+ if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK)
+ {
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk;
+ }
+
+ /* Disable stop condition received interrupt flag */
+ if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK)
+ {
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk;
+ }
+
+ /* Disable non-acknowledge interrupt flag */
+ if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK)
+ {
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk;
+ }
+
+ /* Disable arbitration lost interrupt flag */
+ if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK)
+ {
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk;
+ }
+
+ /* Disable error interrupt flag */
+ if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK)
+ {
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk;
+ }
+
+ /* Disable acknowledge interrupt flag */
+ if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK)
+ {
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk;
+ }
+}
+
+/**
+ * @brief This function enables the interrupt of USCI_I2C module.
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt enable bit.
+ * This parameter decides which interrupts will be enabled. It is combination of:
+ * - \ref UI2C_TO_INT_MASK
+ * - \ref UI2C_STAR_INT_MASK
+ * - \ref UI2C_STOR_INT_MASK
+ * - \ref UI2C_NACK_INT_MASK
+ * - \ref UI2C_ARBLO_INT_MASK
+ * - \ref UI2C_ERR_INT_MASK
+ * - \ref UI2C_ACK_INT_MASK
+ * @return None
+ *
+ * @details The function is used to enable USCI_I2C bus interrupt events.
+ */
+void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask)
+{
+ /* Enable time-out interrupt flag */
+ if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK)
+ {
+ ui2c->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk;
+ }
+
+ /* Enable start condition received interrupt flag */
+ if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK)
+ {
+ ui2c->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk;
+ }
+
+ /* Enable stop condition received interrupt flag */
+ if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK)
+ {
+ ui2c->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk;
+ }
+
+ /* Enable non-acknowledge interrupt flag */
+ if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK)
+ {
+ ui2c->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk;
+ }
+
+ /* Enable arbitration lost interrupt flag */
+ if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK)
+ {
+ ui2c->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk;
+ }
+
+ /* Enable error interrupt flag */
+ if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK)
+ {
+ ui2c->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk;
+ }
+
+ /* Enable acknowledge interrupt flag */
+ if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK)
+ {
+ ui2c->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk;
+ }
+}
+
+/**
+ * @brief This function returns the real bus clock of USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return Actual USCI_I2C bus clock frequency.
+ *
+ * @details The function returns the actual USCI_I2C module bus clock.
+ */
+uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c)
+{
+ uint32_t u32Divider;
+ uint32_t u32Pclk;
+
+ if (ui2c == UI2C0)
+ {
+ u32Pclk = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32Pclk = CLK_GetPCLK1Freq();
+ }
+
+ u32Divider = (ui2c->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos;
+
+ return ( u32Pclk / ((u32Divider+1U)<<1U) );
+}
+
+/**
+ * @brief This function sets bus clock frequency of USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u32BusClock The target bus speed of USCI_I2C module.
+ *
+ * @return Actual USCI_I2C bus clock frequency.
+ *
+ * @details Use this function set USCI_I2C bus clock frequency and return actual bus clock.
+ */
+uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock)
+{
+ uint32_t u32ClkDiv;
+ uint32_t u32Pclk;
+
+ if( ui2c == UI2C0 )
+ {
+ u32Pclk = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32Pclk = CLK_GetPCLK1Freq();
+ }
+
+ u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */
+
+ /* Set USCI_I2C bus clock */
+ ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk;
+ ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos);
+
+ return ( u32Pclk / ((u32ClkDiv+1U)<<1U) );
+}
+
+/**
+ * @brief This function gets the interrupt flag of USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be read. It is combination of:
+ * - \ref UI2C_TO_INT_MASK
+ * - \ref UI2C_STAR_INT_MASK
+ * - \ref UI2C_STOR_INT_MASK
+ * - \ref UI2C_NACK_INT_MASK
+ * - \ref UI2C_ARBLO_INT_MASK
+ * - \ref UI2C_ERR_INT_MASK
+ * - \ref UI2C_ACK_INT_MASK
+ *
+ * @return Interrupt flags of selected sources.
+ *
+ * @details Use this function to get USCI_I2C interrupt flag when module occurs interrupt event.
+ */
+uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask)
+{
+ uint32_t u32IntFlag = 0U;
+ uint32_t u32TmpValue;
+
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_TOIF_Msk;
+ /* Check Time-out Interrupt Flag */
+ if((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue))
+ {
+ u32IntFlag |= UI2C_TO_INT_MASK;
+ }
+
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STARIF_Msk;
+ /* Check Start Condition Received Interrupt Flag */
+ if((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue))
+ {
+ u32IntFlag |= UI2C_STAR_INT_MASK;
+ }
+
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STORIF_Msk;
+ /* Check Stop Condition Received Interrupt Flag */
+ if((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue))
+ {
+ u32IntFlag |= UI2C_STOR_INT_MASK;
+ }
+
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_NACKIF_Msk;
+ /* Check Non-Acknowledge Interrupt Flag */
+ if((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue))
+ {
+ u32IntFlag |= UI2C_NACK_INT_MASK;
+ }
+
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk;
+ /* Check Arbitration Lost Interrupt Flag */
+ if((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue))
+ {
+ u32IntFlag |= UI2C_ARBLO_INT_MASK;
+ }
+
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ERRIF_Msk;
+ /* Check Error Interrupt Flag */
+ if((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue))
+ {
+ u32IntFlag |= UI2C_ERR_INT_MASK;
+ }
+
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ACKIF_Msk;
+ /* Check Acknowledge Interrupt Flag */
+ if((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue))
+ {
+ u32IntFlag |= UI2C_ACK_INT_MASK;
+ }
+
+ return u32IntFlag;
+}
+
+/**
+ * @brief This function clears the interrupt flag of USCI_I2C module.
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be cleared. It is combination of:
+ * - \ref UI2C_TO_INT_MASK
+ * - \ref UI2C_STAR_INT_MASK
+ * - \ref UI2C_STOR_INT_MASK
+ * - \ref UI2C_NACK_INT_MASK
+ * - \ref UI2C_ARBLO_INT_MASK
+ * - \ref UI2C_ERR_INT_MASK
+ * - \ref UI2C_ACK_INT_MASK
+ *
+ * @return None
+ *
+ * @details Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag.
+ */
+void UI2C_ClearIntFlag(UI2C_T *ui2c, uint32_t u32Mask)
+{
+ /* Clear Time-out Interrupt Flag */
+ if(u32Mask & UI2C_TO_INT_MASK)
+ {
+ ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk;
+ }
+
+ /* Clear Start Condition Received Interrupt Flag */
+ if(u32Mask & UI2C_STAR_INT_MASK)
+ {
+ ui2c->PROTSTS = UI2C_PROTSTS_STARIF_Msk;
+ }
+
+ /* Clear Stop Condition Received Interrupt Flag */
+ if(u32Mask & UI2C_STOR_INT_MASK)
+ {
+ ui2c->PROTSTS = UI2C_PROTSTS_STORIF_Msk;
+ }
+
+ /* Clear Non-Acknowledge Interrupt Flag */
+ if(u32Mask & UI2C_NACK_INT_MASK)
+ {
+ ui2c->PROTSTS = UI2C_PROTSTS_NACKIF_Msk;
+ }
+
+ /* Clear Arbitration Lost Interrupt Flag */
+ if(u32Mask & UI2C_ARBLO_INT_MASK)
+ {
+ ui2c->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk;
+ }
+
+ /* Clear Error Interrupt Flag */
+ if(u32Mask & UI2C_ERR_INT_MASK)
+ {
+ ui2c->PROTSTS = UI2C_PROTSTS_ERRIF_Msk;
+ }
+
+ /* Clear Acknowledge Interrupt Flag */
+ if(u32Mask & UI2C_ACK_INT_MASK)
+ {
+ ui2c->PROTSTS = UI2C_PROTSTS_ACKIF_Msk;
+ }
+}
+
+/**
+ * @brief This function returns the data stored in data register of USCI_I2C module.
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return USCI_I2C data.
+ *
+ * @details To read a byte data from USCI_I2C module receive data register.
+ */
+uint32_t UI2C_GetData(UI2C_T *ui2c)
+{
+ return ( ui2c->RXDAT );
+}
+
+/**
+ * @brief This function writes a byte data to data register of USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8Data The data which will be written to data register of USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details To write a byte data to transmit data register to transmit data.
+ */
+void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data)
+{
+ ui2c->TXDAT = u8Data;
+}
+
+/**
+ * @brief Configure slave address and enable GC mode
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveNo Slave channel number [0/1]
+ * @param[in] u16SlaveAddr The slave address.
+ * @param[in] u8GCMode GC mode enable or not. Valid values are:
+ * - \ref UI2C_GCMODE_ENABLE
+ * - \ref UI2C_GCMODE_DISABLE
+ *
+ * @return None
+ *
+ * @details To configure USCI_I2C module slave address and GC mode.
+ */
+void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode)
+{
+ if(u8SlaveNo)
+ {
+ ui2c->DEVADDR1 = u16SlaveAddr;
+ }
+ else
+ {
+ ui2c->DEVADDR0 = u16SlaveAddr;
+ }
+
+ ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) |u8GCMode;
+}
+
+/**
+ * @brief Configure the mask bit of slave address.
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveNo Slave channel number [0/1]
+ * @param[in] u16SlaveAddrMask The slave address mask.
+ *
+ * @return None
+ *
+ * @details To configure USCI_I2C module slave address mask bit.
+ * @note The corresponding address bit is "Don't Care".
+ */
+void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask)
+{
+ if(u8SlaveNo)
+ {
+ ui2c->ADDRMSK1 = u16SlaveAddrMask;
+ }
+ else
+ {
+ ui2c->ADDRMSK0 = u16SlaveAddrMask;
+ }
+}
+
+/**
+ * @brief This function enables time-out function and configures timeout counter
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u32TimeoutCnt Timeout counter. Valid values are between 0~0x3FF
+ *
+ * @return None
+ *
+ * @details To enable USCI_I2C bus time-out function and set time-out counter.
+ */
+void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt)
+{
+ ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos);
+ ui2c->BRGEN = (ui2c->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk;
+}
+
+/**
+ * @brief This function disables time-out function
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details To disable USCI_I2C bus time-out function.
+ */
+void UI2C_DisableTimeout(UI2C_T *ui2c)
+{
+ ui2c->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk;
+ ui2c->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk;
+}
+
+/**
+ * @brief This function enables the wakeup function of USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8WakeupMode The wake-up mode selection. Valid values are:
+ * - \ref UI2C_DATA_TOGGLE_WK
+ * - \ref UI2C_ADDR_MATCH_WK
+ *
+ * @return None
+ *
+ * @details To enable USCI_I2C module wake-up function.
+ */
+void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode)
+{
+ ui2c->WKCTL = (ui2c->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk);
+}
+
+/**
+ * @brief This function disables the wakeup function of USCI_I2C module
+ *
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.
+ *
+ * @return None
+ *
+ * @details To disable USCI_I2C module wake-up function.
+ */
+void UI2C_DisableWakeup(UI2C_T *ui2c)
+{
+ ui2c->WKCTL &= ~UI2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief Write a byte to Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] data Write a byte data to Slave
+ *
+ * @retval 0 Write data success
+ * @retval 1 Write data fail, or bus occurs error events
+ *
+ * @details The function is used for USCI_I2C Master write a byte data to Slave.
+ *
+ */
+
+uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data)
+{
+ uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U;
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */
+ eEvent = MASTER_SEND_ADDRESS;
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (eEvent == MASTER_SEND_ADDRESS)
+ {
+ UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */
+ eEvent = MASTER_SEND_DATA;
+ }
+ else
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ u8Err = 1U;
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ u8Err = 1U;
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */
+ }
+
+ return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
+}
+
+/**
+ * @brief Write multi bytes to Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] *data Pointer to array to write data to Slave
+ * @param[in] u32wLen How many bytes need to write to Slave
+ *
+ * @return A length of how many bytes have been transmitted.
+ *
+ * @details The function is used for USCI_I2C Master write multi bytes data to Slave.
+ *
+ */
+
+uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen)
+{
+ uint8_t u8Xfering = 1U, u8Ctrl = 0U;
+ uint32_t u32txLen = 0U;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (u32txLen < u32wLen)
+ UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */
+ else
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */
+ }
+
+ return u32txLen; /* Return bytes length that have been transmitted */
+}
+
+/**
+ * @brief Specify a byte register address and write a byte to Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u8DataAddr Specify a address (1 byte) of data write to
+ * @param[in] data A byte data to write it to Slave
+ *
+ * @retval 0 Write data success
+ * @retval 1 Write data fail, or bus occurs error events
+ *
+ * @details The function is used for USCI_I2C Master specify a address that data write to in Slave.
+ *
+ */
+
+uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data)
+{
+ uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U;
+ uint32_t u32txLen = 0U;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (u32txLen == 0U)
+ {
+ UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */
+ u32txLen++;
+ }
+ else if (u32txLen == 1U)
+ {
+ UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */
+ u32txLen++;
+ }
+ else
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ u8Err = 1U;
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ u8Err = 1U;
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */
+ }
+
+ return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
+}
+
+
+/**
+ * @brief Specify a byte register address and write multi bytes to Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u8DataAddr Specify a address (1 byte) of data write to
+ * @param[in] *data Pointer to array to write data to Slave
+ * @param[in] u32wLen How many bytes need to write to Slave
+ *
+ * @return A length of how many bytes have been transmitted.
+ *
+ * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes write to in Slave.
+ *
+ */
+
+uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen)
+{
+ uint8_t u8Xfering = 1U, u8Ctrl = 0U;
+ uint32_t u32txLen = 0U;
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */
+ eEvent = MASTER_SEND_ADDRESS;
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (eEvent == MASTER_SEND_ADDRESS)
+ {
+ UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */
+ eEvent = MASTER_SEND_DATA;
+ }
+ else
+ {
+ if (u32txLen < u32wLen)
+ UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */
+ else
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ }
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */
+ }
+
+ return u32txLen; /* Return bytes length that have been transmitted */
+}
+
+/**
+ * @brief Specify two bytes register address and Write a byte to Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u16DataAddr Specify a address (2 byte) of data write to
+ * @param[in] data Write a byte data to Slave
+ *
+ * @retval 0 Write data success
+ * @retval 1 Write data fail, or bus occurs error events
+ *
+ * @details The function is used for USCI_I2C Master specify two bytes address that data write to in Slave.
+ *
+ */
+
+uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data)
+{
+ uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U;
+ uint32_t u32txLen = 0U;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (u32txLen == 0U)
+ {
+ UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte data address to UI2C_TXDAT */
+ u32txLen++;
+ }
+ else if (u32txLen == 1U)
+ {
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */
+ u32txLen++;
+ }
+ else if (u32txLen == 2U)
+ {
+ UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */
+ u32txLen++;
+ }
+ else
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ u8Err = 1U;
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ u8Err = 1U;
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */
+ }
+
+ return (u8Err | u8Xfering);
+}
+
+
+/**
+ * @brief Specify two bytes register address and write multi bytes to Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u16DataAddr Specify a address (2 bytes) of data write to
+ * @param[in] *data Pointer to array to write data to Slave
+ * @param[in] u32wLen How many bytes need to write to Slave
+ *
+ * @return A length of how many bytes have been transmitted.
+ *
+ * @details The function is used for USCI_I2C Master specify a byte address that multi data write to in Slave.
+ *
+ */
+
+uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen)
+{
+ uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U;
+ uint32_t u32txLen = 0U;
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */
+ eEvent = MASTER_SEND_ADDRESS;
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (eEvent == MASTER_SEND_ADDRESS)
+ {
+ UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte data address to UI2C_TXDAT */
+ eEvent = MASTER_SEND_DATA;
+ }
+ else if (eEvent == MASTER_SEND_DATA)
+ {
+ if (u8Addr)
+ {
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */
+ u8Addr = 0;
+ }
+ else
+ {
+ if (u32txLen < u32wLen)
+ {
+ UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */
+ }
+ else
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ }
+ }
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */
+ }
+
+ return u32txLen; /* Return bytes length that have been transmitted */
+}
+
+/**
+ * @brief Read a byte from Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ *
+ * @return Read a byte data from Slave
+ *
+ * @details The function is used for USCI_I2C Master to read a byte data from Slave.
+ *
+ */
+uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr)
+{
+ uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U;
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */
+ eEvent = MASTER_SEND_H_RD_ADDRESS;
+ u8Ctrl = UI2C_CTL_PTRG;
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+ eEvent = MASTER_READ_DATA;
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+
+ if (eEvent == MASTER_SEND_H_RD_ADDRESS)
+ {
+ u8Err = 1U;
+ }
+ else
+ {
+ rdata = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */
+ }
+
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ u8Err = 1U;
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */
+ }
+
+ if (u8Err)
+ rdata = 0U;
+
+ return rdata; /* Return read data */
+}
+
+
+/**
+ * @brief Read multi bytes from Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[out] *rdata Point to array to store data from Slave
+ * @param[in] u32rLen How many bytes need to read from Slave
+ *
+ * @return A length of how many bytes have been received
+ *
+ * @details The function is used for USCI_I2C Master to read multi data bytes from Slave.
+ *
+ *
+ */
+uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen)
+{
+ uint8_t u8Xfering = 1U, u8Ctrl = 0U;
+ uint32_t u32rxLen = 0U;
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */
+ eEvent = MASTER_SEND_H_RD_ADDRESS;
+ u8Ctrl = UI2C_CTL_PTRG;
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (eEvent == MASTER_SEND_H_RD_ADDRESS)
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+ eEvent = MASTER_READ_DATA;
+ }
+ else
+ {
+ rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */
+
+ if (u32rxLen < (u32rLen - 1U))
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+ else
+ u8Ctrl = UI2C_CTL_PTRG;
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+
+ if (eEvent == MASTER_READ_DATA)
+ rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */
+
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */
+ }
+
+ return u32rxLen; /* Return bytes length that have been received */
+}
+
+
+/**
+ * @brief Specify a byte register address and read a byte from Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u8DataAddr Specify a address(1 byte) of data read from
+ *
+ * @return Read a byte data from Slave
+ *
+ * @details The function is used for USCI_I2C Master specify a byte address that a data byte read from Slave.
+ *
+ *
+ */
+uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
+{
+ uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U;
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+
+ if (eEvent == MASTER_SEND_START)
+ {
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */
+ eEvent = MASTER_SEND_ADDRESS;
+ }
+ else if (eEvent == MASTER_SEND_REPEAT_START)
+ {
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */
+ eEvent = MASTER_SEND_H_RD_ADDRESS;
+ }
+
+ u8Ctrl = UI2C_CTL_PTRG;
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (eEvent == MASTER_SEND_ADDRESS)
+ {
+ UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */
+ u8Ctrl = UI2C_CTL_PTRG;
+ eEvent = MASTER_SEND_DATA;
+ }
+ else if (eEvent == MASTER_SEND_DATA)
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */
+ eEvent = MASTER_SEND_REPEAT_START;
+ }
+ else
+ {
+ /* SLA+R ACK */
+ u8Ctrl = UI2C_CTL_PTRG;
+ eEvent = MASTER_READ_DATA;
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+
+ if (eEvent == MASTER_READ_DATA)
+ {
+ rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */
+ }
+ else
+ {
+ u8Err = 1U;
+ }
+
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ u8Err = 1U;
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */
+ }
+
+ if (u8Err)
+ rdata = 0U; /* If occurs error, return 0 */
+
+ return rdata; /* Return read data */
+}
+
+/**
+ * @brief Specify a byte register address and read multi bytes from Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u8DataAddr Specify a address (1 bytes) of data read from
+ * @param[out] *rdata Point to array to store data from Slave
+ * @param[in] u32rLen How many bytes need to read from Slave
+ *
+ * @return A length of how many bytes have been received
+ *
+ * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes read from Slave.
+ *
+ *
+ */
+uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen)
+{
+ uint8_t u8Xfering = 1U, u8Ctrl = 0U;
+ uint32_t u32rxLen = 0U;
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+
+ if (eEvent == MASTER_SEND_START)
+ {
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */
+ eEvent = MASTER_SEND_ADDRESS;
+ }
+ else if (eEvent == MASTER_SEND_REPEAT_START)
+ {
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */
+ eEvent = MASTER_SEND_H_RD_ADDRESS;
+ }
+
+ u8Ctrl = UI2C_CTL_PTRG;
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (eEvent == MASTER_SEND_ADDRESS)
+ {
+ UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */
+ u8Ctrl = UI2C_CTL_PTRG;
+ eEvent = MASTER_SEND_DATA;
+ }
+ else if (eEvent == MASTER_SEND_DATA)
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */
+ eEvent = MASTER_SEND_REPEAT_START;
+ }
+ else if (eEvent == MASTER_SEND_H_RD_ADDRESS)
+ {
+ /* SLA+R ACK */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+ eEvent = MASTER_READ_DATA;
+ }
+ else
+ {
+ rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */
+
+ if (u32rxLen < u32rLen - 1U)
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+ else
+ u8Ctrl = UI2C_CTL_PTRG;
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+
+ if (eEvent == MASTER_READ_DATA)
+ rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */
+
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */
+ }
+
+ return u32rxLen; /* Return bytes length that have been received */
+}
+
+/**
+ * @brief Specify two bytes register address and read a byte from Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u16DataAddr Specify a address(2 byte) of data read from
+ *
+ * @return Read a byte data from Slave
+ *
+ * @details The function is used for USCI_I2C Master specify two bytes address that a data byte read from Slave.
+ *
+ *
+ */
+uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)
+{
+ uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Addr = 1U, u8Ctrl = 0U;
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+
+ if (eEvent == MASTER_SEND_START)
+ {
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */
+ eEvent = MASTER_SEND_ADDRESS;
+ }
+ else if (eEvent == MASTER_SEND_REPEAT_START)
+ {
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */
+ eEvent = MASTER_SEND_H_RD_ADDRESS;
+ }
+
+ u8Ctrl = UI2C_CTL_PTRG;
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (eEvent == MASTER_SEND_ADDRESS)
+ {
+ UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte address of register */
+ eEvent = MASTER_SEND_DATA;
+ }
+ else if (eEvent == MASTER_SEND_DATA)
+ {
+ if (u8Addr)
+ {
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */
+ u8Addr = 0;
+ }
+ else
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */
+ eEvent = MASTER_SEND_REPEAT_START;
+ }
+ }
+ else
+ {
+ /* SLA+R ACK */
+ u8Ctrl = UI2C_CTL_PTRG;
+ eEvent = MASTER_READ_DATA;
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+
+ if (eEvent == MASTER_READ_DATA)
+ {
+ rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */
+ }
+ else
+ {
+ u8Err = 1U;
+ }
+
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ u8Err = 1U;
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */
+ }
+
+ if (u8Err)
+ rdata = 0U; /* If occurs error, return 0 */
+
+ return rdata; /* Return read data */
+}
+
+/**
+ * @brief Specify two bytes register address and read multi bytes from Slave
+ *
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)
+ * @param[in] u16DataAddr Specify a address (2 bytes) of data read from
+ * @param[out] *rdata Point to array to store data from Slave
+ * @param[in] u32rLen How many bytes need to read from Slave
+ *
+ * @return A length of how many bytes have been received
+ *
+ * @details The function is used for USCI_I2C Master specify two bytes address that multi data bytes read from Slave.
+ *
+ *
+ */
+uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen)
+{
+ uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U;
+ uint32_t u32rxLen = 0U;
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+ UI2C_START(ui2c); /* Send START */
+
+ while (u8Xfering)
+ {
+ while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */
+
+ switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+ {
+ case UI2C_PROTSTS_STARIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */
+
+ if (eEvent == MASTER_SEND_START)
+ {
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */
+ eEvent = MASTER_SEND_ADDRESS;
+ }
+ else if (eEvent == MASTER_SEND_REPEAT_START)
+ {
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */
+ eEvent = MASTER_SEND_H_RD_ADDRESS;
+ }
+
+ u8Ctrl = UI2C_CTL_PTRG;
+ break;
+
+ case UI2C_PROTSTS_ACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */
+
+ if (eEvent == MASTER_SEND_ADDRESS)
+ {
+ UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte address of register */
+ eEvent = MASTER_SEND_DATA;
+ }
+ else if (eEvent == MASTER_SEND_DATA)
+ {
+ if (u8Addr)
+ {
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */
+ u8Addr = 0;
+ }
+ else
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */
+ eEvent = MASTER_SEND_REPEAT_START;
+ }
+ }
+ else if (eEvent == MASTER_SEND_H_RD_ADDRESS)
+ {
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+ eEvent = MASTER_READ_DATA;
+ }
+ else
+ {
+ rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */
+
+ if (u32rxLen < u32rLen - 1U)
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+ else
+ u8Ctrl = UI2C_CTL_PTRG;
+ }
+
+ break;
+
+ case UI2C_PROTSTS_NACKIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */
+
+ if (eEvent == MASTER_READ_DATA)
+ rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */
+
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+
+ break;
+
+ case UI2C_PROTSTS_STORIF_Msk:
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */
+ u8Xfering = 0U;
+ break;
+
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */
+ default: /* Unknow status */
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */
+ break;
+ }
+
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */
+ }
+
+ return u32rxLen; /* Return bytes length that have been received */
+}
+
+/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USCI_I2C_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_spi.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_spi.c
new file mode 100644
index 00000000000..69744f4644a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_spi.c
@@ -0,0 +1,664 @@
+/****************************************************************************//**
+ * @file usci_spi.c
+ * @version V3.00
+ * @brief M480 series USCI_SPI driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup USCI_SPI_Driver USCI_SPI Driver
+ @{
+*/
+
+
+/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make USCI_SPI module be ready to transfer.
+ * By default, the USCI_SPI transfer sequence is MSB first, the slave selection
+ * signal is active low and the automatic slave select function is disabled. In
+ * Slave mode, the u32BusClock must be NULL and the USCI_SPI clock
+ * divider setting will be 0.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are:
+ * - \ref USPI_SLAVE
+ * - \ref USPI_MASTER
+ * @param[in] u32SPIMode Decide the transfer timing. Valid values are:
+ * - \ref USPI_MODE_0
+ * - \ref USPI_MODE_1
+ * - \ref USPI_MODE_2
+ * - \ref USPI_MODE_3
+ * @param[in] u32DataWidth The data width of a USCI_SPI transaction.
+ * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz.
+ * @return Actual frequency of USCI_SPI peripheral clock.
+ */
+uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
+{
+ uint32_t u32ClkDiv = 0ul;
+ uint32_t u32Pclk;
+ uint32_t u32UspiClk = 0ul;
+
+ if(uspi == (USPI_T *)USPI0)
+ {
+ u32Pclk = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32Pclk = CLK_GetPCLK1Freq();
+ }
+
+ if(u32BusClock != 0ul)
+ {
+ u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */
+ }
+ else {}
+
+ /* Enable USCI_SPI protocol */
+ uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
+ uspi->CTL = 1ul << USPI_CTL_FUNMODE_Pos;
+
+ /* Data format configuration */
+ if(u32DataWidth == 16ul)
+ {
+ u32DataWidth = 0ul;
+ }
+ else {}
+ uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk;
+ uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos);
+
+ /* MSB data format */
+ uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk;
+
+ /* Set slave selection signal active low */
+ if(u32MasterSlave == USPI_MASTER)
+ {
+ uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk;
+ }
+ else
+ {
+ uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk;
+ }
+
+ /* Set operating mode and transfer timing */
+ uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk);
+ uspi->PROTCTL |= (u32MasterSlave | u32SPIMode);
+
+ /* Set USCI_SPI bus clock */
+ uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
+ uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
+ uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk;
+
+ if(u32BusClock != 0ul)
+ {
+ u32UspiClk = (uint32_t)( u32Pclk / ((u32ClkDiv+1ul)<<1) );
+ }
+ else {}
+
+ return u32UspiClk;
+}
+
+/**
+ * @brief Disable USCI_SPI function mode.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ */
+void USPI_Close(USPI_T *uspi)
+{
+ uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
+}
+
+/**
+ * @brief Clear Rx buffer.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ */
+void USPI_ClearRxBuf(USPI_T *uspi)
+{
+ uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk;
+}
+
+/**
+ * @brief Clear Tx buffer.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ */
+void USPI_ClearTxBuf(USPI_T *uspi)
+{
+ uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk;
+}
+
+/**
+ * @brief Disable the automatic slave select function.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ */
+void USPI_DisableAutoSS(USPI_T *uspi)
+{
+ uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk);
+}
+
+/**
+ * @brief Enable the automatic slave select function. Only available in Master mode.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32SSPinMask This parameter is not used.
+ * @param[in] u32ActiveLevel The active level of slave select signal. Valid values are:
+ * - \ref USPI_SS_ACTIVE_HIGH
+ * - \ref USPI_SS_ACTIVE_LOW
+ * @return None
+ */
+void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+ uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel;
+ uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk;
+}
+
+/**
+ * @brief Set the USCI_SPI bus clock. Only available in Master mode.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock.
+ * @return Actual frequency of USCI_SPI peripheral clock.
+ */
+uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock)
+{
+ uint32_t u32ClkDiv;
+ uint32_t u32Pclk;
+
+ if(uspi == USPI0)
+ {
+ u32Pclk = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32Pclk = CLK_GetPCLK1Freq();
+ }
+
+ u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */
+
+ /* Set USCI_SPI bus clock */
+ uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
+ uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
+
+ return ( u32Pclk / ((u32ClkDiv+1ul)<<1) );
+}
+
+/**
+ * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return Actual USCI_SPI bus clock frequency.
+ */
+uint32_t USPI_GetBusClock(USPI_T *uspi)
+{
+ uint32_t u32BusClk;
+ uint32_t u32ClkDiv;
+
+ u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos;
+
+ if(uspi == USPI0)
+ {
+ u32BusClk = (uint32_t)( CLK_GetPCLK0Freq() / ((u32ClkDiv+1ul)<<1) );
+ }
+ else
+ {
+ u32BusClk = (uint32_t)( CLK_GetPCLK1Freq() / ((u32ClkDiv+1ul)<<1) );
+ }
+
+ return u32BusClk;
+}
+
+/**
+ * @brief Enable related interrupts specified by u32Mask parameter.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * This parameter decides which interrupts will be enabled. Valid values are:
+ * - \ref USPI_SSINACT_INT_MASK
+ * - \ref USPI_SSACT_INT_MASK
+ * - \ref USPI_SLVTO_INT_MASK
+ * - \ref USPI_SLVBE_INT_MASK
+ * - \ref USPI_TXUDR_INT_MASK
+ * - \ref USPI_RXOV_INT_MASK
+ * - \ref USPI_TXST_INT_MASK
+ * - \ref USPI_TXEND_INT_MASK
+ * - \ref USPI_RXST_INT_MASK
+ * - \ref USPI_RXEND_INT_MASK
+ * @return None
+ */
+void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask)
+{
+ /* Enable slave selection signal inactive interrupt flag */
+ if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)
+ {
+ uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk;
+ }
+ else {}
+ /* Enable slave selection signal active interrupt flag */
+ if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)
+ {
+ uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk;
+ }
+ else {}
+ /* Enable slave time-out interrupt flag */
+ if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)
+ {
+ uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk;
+ }
+ else {}
+
+ /* Enable slave bit count error interrupt flag */
+ if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)
+ {
+ uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk;
+ }
+ else {}
+ /* Enable TX under run interrupt flag */
+ if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)
+ {
+ uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk;
+ }
+ else {}
+ /* Enable RX overrun interrupt flag */
+ if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
+ {
+ uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk;
+ }
+ else {}
+ /* Enable TX start interrupt flag */
+ if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
+ {
+ uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk;
+ }
+ else {}
+ /* Enable TX end interrupt flag */
+ if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)
+ {
+ uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk;
+ }
+ else {}
+ /* Enable RX start interrupt flag */
+ if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
+ {
+ uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk;
+ }
+ else {}
+ /* Enable RX end interrupt flag */
+ if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)
+ {
+ uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk;
+ }
+ else {}
+}
+
+/**
+ * @brief Disable related interrupts specified by u32Mask parameter.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * This parameter decides which interrupts will be disabled. Valid values are:
+ * - \ref USPI_SSINACT_INT_MASK
+ * - \ref USPI_SSACT_INT_MASK
+ * - \ref USPI_SLVTO_INT_MASK
+ * - \ref USPI_SLVBE_INT_MASK
+ * - \ref USPI_TXUDR_INT_MASK
+ * - \ref USPI_RXOV_INT_MASK
+ * - \ref USPI_TXST_INT_MASK
+ * - \ref USPI_TXEND_INT_MASK
+ * - \ref USPI_RXST_INT_MASK
+ * - \ref USPI_RXEND_INT_MASK
+ * @return None
+ */
+void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask)
+{
+ /* Disable slave selection signal inactive interrupt flag */
+ if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)
+ {
+ uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk;
+ }
+ else {}
+ /* Disable slave selection signal active interrupt flag */
+ if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)
+ {
+ uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk;
+ }
+ else {}
+ /* Disable slave time-out interrupt flag */
+ if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)
+ {
+ uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk;
+ }
+ else {}
+ /* Disable slave bit count error interrupt flag */
+ if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)
+ {
+ uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk;
+ }
+ else {}
+ /* Disable TX under run interrupt flag */
+ if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)
+ {
+ uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk;
+ }
+ else {}
+ /* Disable RX overrun interrupt flag */
+ if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
+ {
+ uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk;
+ }
+ else {}
+ /* Disable TX start interrupt flag */
+ if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
+ {
+ uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk;
+ }
+ else {}
+ /* Disable TX end interrupt flag */
+ if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)
+ {
+ uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk;
+ }
+ else {}
+ /* Disable RX start interrupt flag */
+ if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
+ {
+ uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk;
+ }
+ else {}
+ /* Disable RX end interrupt flag */
+ if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)
+ {
+ uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk;
+ }
+ else {}
+}
+
+/**
+ * @brief Get interrupt flag.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be read. It is combination of:
+ * - \ref USPI_SSINACT_INT_MASK
+ * - \ref USPI_SSACT_INT_MASK
+ * - \ref USPI_SLVTO_INT_MASK
+ * - \ref USPI_SLVBE_INT_MASK
+ * - \ref USPI_TXUDR_INT_MASK
+ * - \ref USPI_RXOV_INT_MASK
+ * - \ref USPI_TXST_INT_MASK
+ * - \ref USPI_TXEND_INT_MASK
+ * - \ref USPI_RXST_INT_MASK
+ * - \ref USPI_RXEND_INT_MASK
+ * @return Interrupt flags of selected sources.
+ */
+uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)
+{
+ uint32_t u32TmpFlag;
+ uint32_t u32IntFlag = 0ul;
+
+ /* Check slave selection signal inactive interrupt flag */
+ u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSINAIF_Msk;
+ if(((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK) && (u32TmpFlag==USPI_PROTSTS_SSINAIF_Msk) )
+ {
+ u32IntFlag |= USPI_SSINACT_INT_MASK;
+ }
+ else {}
+ /* Check slave selection signal active interrupt flag */
+
+ u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSACTIF_Msk;
+ if(((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk))
+ {
+ u32IntFlag |= USPI_SSACT_INT_MASK;
+ }
+ else {}
+
+ /* Check slave time-out interrupt flag */
+ u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVTOIF_Msk;
+ if(((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVTOIF_Msk))
+ {
+ u32IntFlag |= USPI_SLVTO_INT_MASK;
+ }
+ else {}
+
+ /* Check slave bit count error interrupt flag */
+ u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVBEIF_Msk;
+ if(((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVBEIF_Msk))
+ {
+ u32IntFlag |= USPI_SLVBE_INT_MASK;
+ }
+ else {}
+
+ /* Check TX under run interrupt flag */
+ u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk;
+ if(((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_TXUDRIF_Msk))
+ {
+ u32IntFlag |= USPI_TXUDR_INT_MASK;
+ }
+ else {}
+
+ /* Check RX overrun interrupt flag */
+ u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXOVIF_Msk;
+ if(((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_RXOVIF_Msk))
+ {
+ u32IntFlag |= USPI_RXOV_INT_MASK;
+ }
+ else {}
+
+ /* Check TX start interrupt flag */
+ u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXSTIF_Msk;
+ if(((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXSTIF_Msk))
+ {
+ u32IntFlag |= USPI_TXST_INT_MASK;
+ }
+ else {}
+
+ /* Check TX end interrupt flag */
+ u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXENDIF_Msk;
+ if(((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXENDIF_Msk))
+ {
+ u32IntFlag |= USPI_TXEND_INT_MASK;
+ }
+ else {}
+
+ /* Check RX start interrupt flag */
+ u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXSTIF_Msk;
+ if(((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXSTIF_Msk))
+ {
+ u32IntFlag |= USPI_RXST_INT_MASK;
+ }
+ else {}
+
+ /* Check RX end interrupt flag */
+ u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXENDIF_Msk;
+ if(((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXENDIF_Msk))
+ {
+ u32IntFlag |= USPI_RXEND_INT_MASK;
+ }
+ else {}
+ return u32IntFlag;
+}
+
+/**
+ * @brief Clear interrupt flag.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be cleared. It could be the combination of:
+ * - \ref USPI_SSINACT_INT_MASK
+ * - \ref USPI_SSACT_INT_MASK
+ * - \ref USPI_SLVTO_INT_MASK
+ * - \ref USPI_SLVBE_INT_MASK
+ * - \ref USPI_TXUDR_INT_MASK
+ * - \ref USPI_RXOV_INT_MASK
+ * - \ref USPI_TXST_INT_MASK
+ * - \ref USPI_TXEND_INT_MASK
+ * - \ref USPI_RXST_INT_MASK
+ * - \ref USPI_RXEND_INT_MASK
+ * @return None
+ */
+void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask)
+{
+ /* Clear slave selection signal inactive interrupt flag */
+ if((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK)
+ {
+ uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk;
+ }
+ else {}
+ /* Clear slave selection signal active interrupt flag */
+ if((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK)
+ {
+ uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk;
+ }
+ else {}
+ /* Clear slave time-out interrupt flag */
+ if((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK)
+ {
+ uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk;
+ }
+ else {}
+ /* Clear slave bit count error interrupt flag */
+ if((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK)
+ {
+ uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk;
+ }
+ else {}
+ /* Clear TX under run interrupt flag */
+ if((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK)
+ {
+ uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk;
+ }
+ else {}
+ /* Clear RX overrun interrupt flag */
+ if((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK)
+ {
+ uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk;
+ }
+ else {}
+ /* Clear TX start interrupt flag */
+ if((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK)
+ {
+ uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk;
+ }
+ else {}
+ /* Clear TX end interrupt flag */
+ if((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK)
+ {
+ uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk;
+ }
+ else {}
+ /* Clear RX start interrupt flag */
+ if((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK)
+ {
+ uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk;
+ }
+ else {}
+
+ /* Clear RX end interrupt flag */
+ if((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK)
+ {
+ uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk;
+ }
+ else {}
+}
+
+/**
+ * @brief Get USCI_SPI status.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @param[in] u32Mask The combination of all related sources.
+ * Each bit corresponds to a source.
+ * This parameter decides which flags will be read. It is combination of:
+ * - \ref USPI_BUSY_MASK
+ * - \ref USPI_RX_EMPTY_MASK
+ * - \ref USPI_RX_FULL_MASK
+ * - \ref USPI_TX_EMPTY_MASK
+ * - \ref USPI_TX_FULL_MASK
+ * - \ref USPI_SSLINE_STS_MASK
+ * @return Flags of selected sources.
+ */
+uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask)
+{
+ uint32_t u32Flag = 0ul;
+ uint32_t u32TmpFlag;
+
+ /* Check busy status */
+ u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_BUSY_Msk;
+ if(((u32Mask & USPI_BUSY_MASK)==USPI_BUSY_MASK) && (u32TmpFlag & USPI_PROTSTS_BUSY_Msk))
+ {
+ u32Flag |= USPI_BUSY_MASK;
+ }
+ else {}
+
+ /* Check RX empty flag */
+ u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk;
+ if(((u32Mask & USPI_RX_EMPTY_MASK)==USPI_RX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_RXEMPTY_Msk))
+ {
+ u32Flag |= USPI_RX_EMPTY_MASK;
+ }
+ else {}
+
+ /* Check RX full flag */
+ u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXFULL_Msk;
+ if(((u32Mask & USPI_RX_FULL_MASK)==USPI_RX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_RXFULL_Msk))
+ {
+ u32Flag |= USPI_RX_FULL_MASK;
+ }
+ else {}
+
+ /* Check TX empty flag */
+ u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk;
+ if(((u32Mask & USPI_TX_EMPTY_MASK)==USPI_TX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_TXEMPTY_Msk))
+ {
+ u32Flag |= USPI_TX_EMPTY_MASK;
+ }
+ else {}
+
+ /* Check TX full flag */
+ u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXFULL_Msk;
+ if(((u32Mask & USPI_TX_FULL_MASK)==USPI_TX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_TXFULL_Msk))
+ {
+ u32Flag |= USPI_TX_FULL_MASK;
+ }
+ else {}
+
+ /* Check USCI_SPI_SS line status */
+ u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSLINE_Msk;
+ if(((u32Mask & USPI_SSLINE_STS_MASK)==USPI_SSLINE_STS_MASK) && (u32TmpFlag & USPI_PROTSTS_SSLINE_Msk))
+ {
+ u32Flag |= USPI_SSLINE_STS_MASK;
+ }
+ else {}
+ return u32Flag;
+}
+
+/**
+ * @brief Enable USCI_SPI Wake-up Function.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ */
+void USPI_EnableWakeup(USPI_T *uspi)
+{
+ uspi->WKCTL |= USPI_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief Disable USCI_SPI Wake-up Function.
+ * @param[in] uspi The pointer of the specified USCI_SPI module.
+ * @return None
+ */
+void USPI_DisableWakeup(USPI_T *uspi)
+{
+ uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk;
+}
+
+/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USCI_SPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_uart.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_uart.c
new file mode 100644
index 00000000000..94c1fc99aec
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_uart.c
@@ -0,0 +1,702 @@
+/**************************************************************************//**
+ * @file usci_uart.c
+ * @version V3.00
+ * @brief M480 series USCI UART (UUART) driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup USCI_UART_Driver USCI_UART Driver
+ @{
+*/
+
+/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear USCI_UART specified interrupt flag
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be cleared. It could be the combination of:
+ * - \ref UUART_ABR_INT_MASK
+ * - \ref UUART_RLS_INT_MASK
+ * - \ref UUART_BUF_RXOV_INT_MASK
+ * - \ref UUART_TXST_INT_MASK
+ * - \ref UUART_TXEND_INT_MASK
+ * - \ref UUART_RXST_INT_MASK
+ * - \ref UUART_RXEND_INT_MASK
+ *
+ * @return None
+ *
+ * @details The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter.
+ */
+
+void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask)
+{
+
+ if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */
+ {
+ uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk;
+ }
+
+ if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */
+ {
+ uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk);
+ }
+
+ if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */
+ {
+ uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk;
+ }
+
+ if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */
+ {
+ uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk;
+ }
+
+ if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */
+ {
+ uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk;
+ }
+
+ if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */
+ {
+ uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk;
+ }
+
+ if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */
+ {
+ uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk;
+ }
+
+}
+
+/**
+ * @brief Get USCI_UART specified interrupt flag
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be read. It is combination of:
+ * - \ref UUART_ABR_INT_MASK
+ * - \ref UUART_RLS_INT_MASK
+ * - \ref UUART_BUF_RXOV_INT_MASK
+ * - \ref UUART_TXST_INT_MASK
+ * - \ref UUART_TXEND_INT_MASK
+ * - \ref UUART_RXST_INT_MASK
+ * - \ref UUART_RXEND_INT_MASK
+ *
+ * @return Interrupt flags of selected sources.
+ *
+ * @details The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter.
+ */
+
+uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask)
+{
+ uint32_t u32IntFlag = 0ul;
+ uint32_t u32Tmp1, u32Tmp2;
+
+ /* Check Auto-baud Rate Interrupt Flag */
+ u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK);
+ u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk);
+ if(u32Tmp1 && u32Tmp2)
+ {
+ u32IntFlag |= UUART_ABR_INT_MASK;
+ }
+
+ /* Check Receive Line Status Interrupt Flag */
+ u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK);
+ u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk));
+ if(u32Tmp1 && u32Tmp2)
+ {
+ u32IntFlag |= UUART_RLS_INT_MASK;
+ }
+
+ /* Check Receive Buffer Over-run Error Interrupt Flag */
+ u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK);
+ u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk);
+ if(u32Tmp1 && u32Tmp2)
+ {
+ u32IntFlag |= UUART_BUF_RXOV_INT_MASK;
+ }
+
+ /* Check Transmit Start Interrupt Flag */
+ u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK);
+ u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk);
+ if(u32Tmp1 && u32Tmp2)
+ {
+ u32IntFlag |= UUART_TXST_INT_MASK;
+ }
+
+ /* Check Transmit End Interrupt Flag */
+ u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK);
+ u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk);
+ if(u32Tmp1 && u32Tmp2)
+ {
+ u32IntFlag |= UUART_TXEND_INT_MASK;
+ }
+
+ /* Check Receive Start Interrupt Flag */
+ u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK);
+ u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk);
+ if(u32Tmp1 && u32Tmp2)
+ {
+ u32IntFlag |= UUART_RXST_INT_MASK;
+ }
+
+ /* Check Receive End Interrupt Flag */
+ u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK);
+ u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk);
+ if(u32Tmp1 && u32Tmp2)
+ {
+ u32IntFlag |= UUART_RXEND_INT_MASK;
+ }
+
+ return u32IntFlag;
+
+}
+
+
+/**
+ * @brief Disable USCI_UART function mode
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to disable USCI_UART function mode.
+ */
+void UUART_Close(UUART_T* uuart)
+{
+ uuart->CTL = 0ul;
+}
+
+
+/**
+ * @brief Disable interrupt function.
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt enable bit.
+ * This parameter decides which interrupts will be disabled. It is combination of:
+ * - \ref UUART_ABR_INT_MASK
+ * - \ref UUART_RLS_INT_MASK
+ * - \ref UUART_BUF_RXOV_INT_MASK
+ * - \ref UUART_TXST_INT_MASK
+ * - \ref UUART_TXEND_INT_MASK
+ * - \ref UUART_RXST_INT_MASK
+ * - \ref UUART_RXEND_INT_MASK
+ *
+ * @return None
+ *
+ * @details The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter.
+ */
+void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask)
+{
+
+ /* Disable Auto-baud rate interrupt flag */
+ if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK)
+ {
+ uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk;
+ }
+
+ /* Disable receive line status interrupt flag */
+ if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK)
+ {
+ uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk;
+ }
+
+ /* Disable RX overrun interrupt flag */
+ if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK)
+ {
+ uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk;
+ }
+
+ /* Disable TX start interrupt flag */
+ if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK)
+ {
+ uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk;
+ }
+
+ /* Disable TX end interrupt flag */
+ if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK)
+ {
+ uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk;
+ }
+
+ /* Disable RX start interrupt flag */
+ if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK)
+ {
+ uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk;
+ }
+
+ /* Disable RX end interrupt flag */
+ if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK)
+ {
+ uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk;
+ }
+}
+
+
+/**
+ * @brief Enable interrupt function.
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt enable bit.
+ * This parameter decides which interrupts will be enabled. It is combination of:
+ * - \ref UUART_ABR_INT_MASK
+ * - \ref UUART_RLS_INT_MASK
+ * - \ref UUART_BUF_RXOV_INT_MASK
+ * - \ref UUART_TXST_INT_MASK
+ * - \ref UUART_TXEND_INT_MASK
+ * - \ref UUART_RXST_INT_MASK
+ * - \ref UUART_RXEND_INT_MASK
+ *
+ * @return None
+ *
+ * @details The function is used to enable USCI_UART related interrupts specified by u32Mask parameter.
+ */
+void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask)
+{
+ /* Enable Auto-baud rate interrupt flag */
+ if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK)
+ {
+ uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk;
+ }
+
+ /* Enable receive line status interrupt flag */
+ if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK)
+ {
+ uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk;
+ }
+
+ /* Enable RX overrun interrupt flag */
+ if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK)
+ {
+ uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk;
+ }
+
+ /* Enable TX start interrupt flag */
+ if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK)
+ {
+ uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk;
+ }
+
+ /* Enable TX end interrupt flag */
+ if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK)
+ {
+ uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk;
+ }
+
+ /* Enable RX start interrupt flag */
+ if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK)
+ {
+ uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk;
+ }
+
+ /* Enable RX end interrupt flag */
+ if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK)
+ {
+ uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk;
+ }
+}
+
+
+/**
+ * @brief Open and set USCI_UART function
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ * @param[in] u32baudrate The baud rate of USCI_UART module.
+ *
+ * @return Real baud rate of USCI_UART module.
+ *
+ * @details This function use to enable USCI_UART function and set baud-rate.
+ */
+uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate)
+{
+ uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv;
+ uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;
+ uint32_t u32Div;
+
+ /* Get PCLK frequency */
+ if( uuart == UUART0)
+ {
+ u32PCLKFreq = CLK_GetPCLK0Freq();
+ }
+ else
+ {
+ u32PCLKFreq = CLK_GetPCLK1Freq();
+ }
+
+ u32Div = u32PCLKFreq / u32baudrate;
+ u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate;
+ u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul));
+
+ if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul;
+
+ u32Tmp = 0x400ul * 0x10ul;
+ for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++)
+ {
+ if(u32Div <= (u32Tmp * u32PDSCnt)) break;
+ }
+
+ if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul;
+
+ u32Div = u32Div / u32PDSCnt;
+
+ /* Find best solution */
+ u32Min = (uint32_t) - 1;
+ u32MinDSCnt = 0ul;
+ u32MinClkDiv = 0ul;
+ u32Tmp = 0ul;
+
+ for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */
+ {
+
+ u32ClkDiv = u32Div / u32DSCnt;
+
+ if(u32ClkDiv > 0x400ul)
+ {
+ u32ClkDiv = 0x400ul;
+ u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
+ u32Tmp2 = u32Tmp + 1ul;
+ }
+ else
+ {
+ u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
+ u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div;
+ }
+
+ if(u32Tmp >= u32Tmp2)
+ {
+ u32ClkDiv = u32ClkDiv + 1ul;
+ }
+ else u32Tmp2 = u32Tmp;
+
+ if(u32Tmp2 < u32Min)
+ {
+ u32Min = u32Tmp2;
+ u32MinDSCnt = u32DSCnt;
+ u32MinClkDiv = u32ClkDiv;
+
+ /* Break when get good results */
+ if(u32Min == 0ul)
+ {
+ break;
+ }
+ }
+ }
+
+ /* Enable USCI_UART protocol */
+ uuart->CTL &= ~UUART_CTL_FUNMODE_Msk;
+ uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos;
+
+ /* Set USCI_UART line configuration */
+ uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk;
+ uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos); /* Set falling edge detection */
+
+ /* Set USCI_UART baud rate */
+ uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) |
+ ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) |
+ ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos);
+
+ uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk;
+
+ return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv);
+}
+
+
+/**
+ * @brief Read USCI_UART data
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ * @param[in] pu8RxBuf The buffer to receive the data of receive buffer.
+ * @param[in] u32ReadBytes The read bytes number of data.
+ *
+ * @return Receive byte count
+ *
+ * @details The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf.
+ */
+uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+ uint32_t u32Count, u32delayno;
+
+ for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
+ {
+ u32delayno = 0ul;
+
+ while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */
+ {
+ u32delayno++;
+ if(u32delayno >= 0x40000000ul)
+ {
+ break;
+ }
+ }
+
+ if(u32delayno >= 0x40000000ul)
+ {
+ break;
+ }
+
+ pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT; /* Get Data from USCI RX */
+ }
+
+ return u32Count;
+
+}
+
+
+/**
+ * @brief Set USCI_UART line configuration
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ * @param[in] u32baudrate The register value of baud rate of USCI_UART module.
+ * If u32baudrate = 0, USCI_UART baud rate will not change.
+ * @param[in] u32data_width The data length of USCI_UART module.
+ * - \ref UUART_WORD_LEN_6
+ * - \ref UUART_WORD_LEN_7
+ * - \ref UUART_WORD_LEN_8
+ * - \ref UUART_WORD_LEN_9
+ * @param[in] u32parity The parity setting (none/odd/even) of USCI_UART module.
+ * - \ref UUART_PARITY_NONE
+ * - \ref UUART_PARITY_ODD
+ * - \ref UUART_PARITY_EVEN
+ * @param[in] u32stop_bits The stop bit length (1/2 bit) of USCI_UART module.
+ * - \ref UUART_STOP_BIT_1
+ * - \ref UUART_STOP_BIT_2
+ *
+ * @return Real baud rate of USCI_UART module.
+ *
+ * @details This function use to config USCI_UART line setting.
+ */
+uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
+{
+ uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv;
+ uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;
+ uint32_t u32Div;
+
+ /* Get PCLK frequency */
+ if(uuart == UUART0)
+ {
+ u32PCLKFreq = CLK_GetPCLK0Freq();
+ }
+ else /* UUART1 */
+ {
+ u32PCLKFreq = CLK_GetPCLK1Freq();
+ }
+
+ if(u32baudrate != 0ul)
+ {
+ u32Div = u32PCLKFreq / u32baudrate;
+ u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate;
+ u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul));
+
+ if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul;
+
+ u32Tmp = 0x400ul * 0x10ul;
+ for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++)
+ {
+ if(u32Div <= (u32Tmp * u32PDSCnt)) break;
+ }
+
+ if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul;
+
+ u32Div = u32Div / u32PDSCnt;
+
+ /* Find best solution */
+ u32Min = (uint32_t) - 1;
+ u32MinDSCnt = 0ul;
+ u32MinClkDiv = 0ul;
+
+ for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */
+ {
+ u32ClkDiv = u32Div / u32DSCnt;
+
+ if(u32ClkDiv > 0x400ul)
+ {
+ u32ClkDiv = 0x400ul;
+ u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
+ u32Tmp2 = u32Tmp + 1ul;
+ }
+ else
+ {
+ u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
+ u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div;
+ }
+
+ if(u32Tmp >= u32Tmp2)
+ {
+ u32ClkDiv = u32ClkDiv + 1ul;
+ }
+ else u32Tmp2 = u32Tmp;
+
+ if(u32Tmp2 < u32Min)
+ {
+ u32Min = u32Tmp2;
+ u32MinDSCnt = u32DSCnt;
+ u32MinClkDiv = u32ClkDiv;
+
+ /* Break when get good results */
+ if(u32Min == 0ul)
+ {
+ break;
+ }
+ }
+ }
+
+ /* Set USCI_UART baud rate */
+ uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) |
+ ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) |
+ ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos);
+ }
+ else
+ {
+ u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul;
+ u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul;
+ u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul;
+ }
+
+ /* Set USCI_UART line configuration */
+ uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width;
+ uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk |
+ UUART_PROTCTL_PARITYEN_Msk)) | u32parity;
+ uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk ) | u32stop_bits;
+
+ return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv);
+}
+
+
+/**
+ * @brief Write USCI_UART data
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ * @param[in] pu8TxBuf The buffer to send the data to USCI transmission buffer.
+ * @param[out] u32WriteBytes The byte number of data.
+ *
+ * @return Transfer byte count
+ *
+ * @details The function is to write data into TX buffer to transmit data by USCI_UART.
+ */
+uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+ uint32_t u32Count, u32delayno;
+
+ for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
+ {
+ u32delayno = 0ul;
+ while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) /* Wait Tx empty */
+ {
+ u32delayno++;
+ if(u32delayno >= 0x40000000ul)
+ {
+ break;
+ }
+ }
+
+ if(u32delayno >= 0x40000000ul)
+ {
+ break;
+ }
+
+ uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */
+ }
+
+ return u32Count;
+
+}
+
+
+/**
+ * @brief Enable USCI_UART Wake-up Function
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ * @param[in] u32WakeupMode The wakeup mode of USCI_UART module.
+ * - \ref UUART_PROTCTL_DATWKEN_Msk : Data wake-up Mode
+ * - \ref UUART_PROTCTL_CTSWKEN_Msk : nCTS wake-up Mode
+ *
+ * @return None
+ *
+ * @details The function is used to enable Wake-up function of USCI_UART.
+ */
+void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode)
+{
+ uuart->PROTCTL |= u32WakeupMode;
+ uuart->WKCTL |= UUART_WKCTL_WKEN_Msk;
+}
+
+
+/**
+ * @brief Disable USCI_UART Wake-up Function
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to disable Wake-up function of USCI_UART.
+ */
+void UUART_DisableWakeup(UUART_T* uuart)
+{
+ uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk|UUART_PROTCTL_CTSWKEN_Msk);
+ uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief Enable USCI_UART auto flow control
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to enable USCI_UART auto flow control.
+ */
+void UUART_EnableFlowCtrl(UUART_T* uuart)
+{
+ /* Set RTS signal is low level active */
+ uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk;
+
+ /* Set CTS signal is low level active */
+ uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk;
+
+ /* Enable CTS and RTS auto flow control function */
+ uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk;
+}
+
+/**
+ * @brief Disable USCI_UART auto flow control
+ *
+ * @param[in] uuart The pointer of the specified USCI_UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to disable USCI_UART auto flow control.
+ */
+void UUART_DisableFlowCtrl(UUART_T* uuart)
+{
+ /* Disable CTS and RTS auto flow control function */
+ uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk);
+}
+
+
+
+
+/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USCI_UART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wdt.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wdt.c
new file mode 100644
index 00000000000..fe4d433b866
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wdt.c
@@ -0,0 +1,69 @@
+/**************************************************************************//**
+ * @file wdt.c
+ * @version V3.00
+ * @brief M480 series WDT driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+ @{
+*/
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief Initialize WDT and start counting
+ *
+ * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:
+ * - \ref WDT_TIMEOUT_2POW4
+ * - \ref WDT_TIMEOUT_2POW6
+ * - \ref WDT_TIMEOUT_2POW8
+ * - \ref WDT_TIMEOUT_2POW10
+ * - \ref WDT_TIMEOUT_2POW12
+ * - \ref WDT_TIMEOUT_2POW14
+ * - \ref WDT_TIMEOUT_2POW16
+ * - \ref WDT_TIMEOUT_2POW18
+ * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are:
+ * - \ref WDT_RESET_DELAY_1026CLK
+ * - \ref WDT_RESET_DELAY_130CLK
+ * - \ref WDT_RESET_DELAY_18CLK
+ * - \ref WDT_RESET_DELAY_3CLK
+ * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE.
+ * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE.
+ *
+ * @return None
+ *
+ * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n
+ * enable or disable WDT time-out reset system or wake-up system.
+ * @note Please make sure that Register Write-Protection Function has been disabled before using this function.
+ */
+void WDT_Open(uint32_t u32TimeoutInterval,
+ uint32_t u32ResetDelay,
+ uint32_t u32EnableReset,
+ uint32_t u32EnableWakeup)
+{
+ WDT->ALTCTL = u32ResetDelay;
+
+ WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk |
+ (u32EnableReset << WDT_CTL_RSTEN_Pos) |
+ (u32EnableWakeup << WDT_CTL_WKEN_Pos);
+ return;
+}
+
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wwdt.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wwdt.c
new file mode 100644
index 00000000000..3f1d13a1510
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wwdt.c
@@ -0,0 +1,69 @@
+/**************************************************************************//**
+ * @file wwdt.c
+ * @version V3.00
+ * @brief M480 series WWDT driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup WWDT_Driver WWDT Driver
+ @{
+*/
+
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief Open WWDT and start counting
+ *
+ * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are:
+ * - \ref WWDT_PRESCALER_1
+ * - \ref WWDT_PRESCALER_2
+ * - \ref WWDT_PRESCALER_4
+ * - \ref WWDT_PRESCALER_8
+ * - \ref WWDT_PRESCALER_16
+ * - \ref WWDT_PRESCALER_32
+ * - \ref WWDT_PRESCALER_64
+ * - \ref WWDT_PRESCALER_128
+ * - \ref WWDT_PRESCALER_192
+ * - \ref WWDT_PRESCALER_256
+ * - \ref WWDT_PRESCALER_384
+ * - \ref WWDT_PRESCALER_512
+ * - \ref WWDT_PRESCALER_768
+ * - \ref WWDT_PRESCALER_1024
+ * - \ref WWDT_PRESCALER_1536
+ * - \ref WWDT_PRESCALER_2048
+ * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F.
+ * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE.
+ *
+ * @return None
+ *
+ * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value.
+ * @note This WWDT_CTL register can be write only one time after chip is powered on or reset.
+ */
+void WWDT_Open(uint32_t u32PreScale,
+ uint32_t u32CmpValue,
+ uint32_t u32EnableInt)
+{
+ WWDT->CTL = u32PreScale |
+ (u32CmpValue << WWDT_CTL_CMPDAT_Pos) |
+ ((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0U) |
+ WWDT_CTL_WWDTEN_Msk;
+ return;
+}
+
+/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WWDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/SConscript b/bsp/nuvoton/libraries/m480/USBHostLib/SConscript
new file mode 100644
index 00000000000..bf3b5901e85
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/USBHostLib/SConscript
@@ -0,0 +1,12 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+group = []
+if GetDepend('BSP_USING_HSUSBH') or GetDepend('BSP_USING_USBH'):
+ src = Glob('*src/*.c') + Glob('src/*.cpp')
+ CPPPATH = [cwd + '/inc']
+ group = DefineGroup('m480_usbhostlib', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/inc/config.h b/bsp/nuvoton/libraries/m480/USBHostLib/inc/config.h
new file mode 100644
index 00000000000..0dab057ac32
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/USBHostLib/inc/config.h
@@ -0,0 +1,114 @@
+/**************************************************************************//**
+ * @file config.h
+ * @version V1.00
+ * @brief This header file defines the configuration of USB Host library.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef _USBH_CONFIG_H_
+#define _USBH_CONFIG_H_
+
+/// @cond HIDDEN_SYMBOLS
+
+#include
+#include
+/*----------------------------------------------------------------------------------------*/
+/* Hardware settings */
+/*----------------------------------------------------------------------------------------*/
+#define HCLK_MHZ 192 /* used for loop-delay. must be larger than
+ true HCLK clock MHz */
+
+#define ENABLE_OHCI_IRQ() NVIC_EnableIRQ(USBH_IRQn)
+#define DISABLE_OHCI_IRQ() NVIC_DisableIRQ(USBH_IRQn)
+#define ENABLE_EHCI_IRQ() NVIC_EnableIRQ(HSUSBH_IRQn)
+#define DISABLE_EHCI_IRQ() NVIC_DisableIRQ(HSUSBH_IRQn)
+
+#define ENABLE_OHCI /* Enable OHCI host controller */
+
+#if defined(BSP_USING_HSUSBH)
+#define ENABLE_EHCI /* Enable EHCI host controller */
+#endif
+
+#define EHCI_PORT_CNT 1 /* Number of EHCI roothub ports */
+#define OHCI_PORT_CNT 2 /* Number of OHCI roothub ports */
+#define OHCI_PER_PORT_POWER /* OHCI root hub per port powered */
+
+#define OHCI_ISO_DELAY 4 /* preserved number frames while scheduling
+ OHCI isochronous transfer */
+
+#define EHCI_ISO_DELAY 2 /* preserved number of frames while
+ scheduling EHCI isochronous transfer */
+
+#define EHCI_ISO_RCLM_RANGE 32 /* When inspecting activated iTD/siTD,
+ unconditionally reclaim iTD/isTD scheduled
+ in just elapsed EHCI_ISO_RCLM_RANGE ms. */
+
+#define MAX_DESC_BUFF_SIZE 512 /* To hold the configuration descriptor, USB
+ core will allocate a buffer with this size
+ for each connected device. USB core does
+ not release it until device disconnected. */
+
+/*----------------------------------------------------------------------------------------*/
+/* Memory allocation settings */
+/*----------------------------------------------------------------------------------------*/
+
+#define STATIC_MEMORY_ALLOC 0 /* pre-allocate static memory blocks. No dynamic memory aloocation.
+ But the maximum number of connected devices and transfers are
+ limited. */
+
+#define MAX_UDEV_DRIVER 8 /*!< Maximum number of registered drivers */
+#define MAX_ALT_PER_IFACE 8 /*!< maximum number of alternative interfaces per interface */
+#define MAX_EP_PER_IFACE 6 /*!< maximum number of endpoints per interface */
+#define MAX_HUB_DEVICE 8 /*!< Maximum number of hub devices */
+
+/* Host controller hardware transfer descriptors memory pool. ED/TD/ITD of OHCI and QH/QTD of EHCI
+ are all allocated from this pool. Allocated unit size is determined by MEM_POOL_UNIT_SIZE.
+ May allocate one or more units depend on hardware descriptor type. */
+
+#define MEM_POOL_UNIT_SIZE 64 /*!< A fixed hard coding setting. Do not change it! */
+#define MEM_POOL_UNIT_NUM 256 /*!< Increase this or heap size if memory allocate failed. */
+
+/*----------------------------------------------------------------------------------------*/
+/* Re-defined staff for various compiler */
+/*----------------------------------------------------------------------------------------*/
+#ifdef __ICCARM__
+#define __inline inline
+#endif
+
+
+/*----------------------------------------------------------------------------------------*/
+/* Debug settings */
+/*----------------------------------------------------------------------------------------*/
+#define ENABLE_ERROR_MSG /* enable debug messages */
+#define ENABLE_DEBUG_MSG /* enable debug messages */
+//#define ENABLE_VERBOSE_DEBUG /* verbos debug messages */
+//#define DUMP_DESCRIPTOR /* dump descriptors */
+
+#ifdef ENABLE_ERROR_MSG
+#define USB_error rt_kprintf
+#else
+#define USB_error(...)
+#endif
+
+#ifdef ENABLE_DEBUG_MSG
+#define USB_debug rt_kprintf
+#ifdef ENABLE_VERBOSE_DEBUG
+#define USB_vdebug rt_kprintf
+#else
+#define USB_vdebug(...)
+#endif
+#else
+#define USB_debug(...)
+#define USB_vdebug(...)
+#endif
+
+
+/// @endcond HIDDEN_SYMBOLS
+
+#endif /* _USBH_CONFIG_H_ */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/inc/ehci.h b/bsp/nuvoton/libraries/m480/USBHostLib/inc/ehci.h
new file mode 100644
index 00000000000..f99a4abde34
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/USBHostLib/inc/ehci.h
@@ -0,0 +1,281 @@
+/**************************************************************************//**
+ * @file ehci.h
+ * @version V1.00
+ * @brief USB EHCI host controller driver header file.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef _USBH_EHCI_H_
+#define _USBH_EHCI_H_
+
+/// @cond HIDDEN_SYMBOLS
+
+struct utr_t;
+struct udev_t;
+struct qh_t;
+struct iso_ep_t;
+struct ep_info_t;
+
+/*----------------------------------------------------------------------------------------*/
+/* Periodic Frame List Size (256, 512, or 1024) */
+/*----------------------------------------------------------------------------------------*/
+#define FL_SIZE 1024 /* frame list size can be 256, 512, or 1024 */
+#define NUM_IQH 11 /* depends on FL_SIZE, 256:9, 512:10, 1024:11 */
+
+
+/*----------------------------------------------------------------------------------------*/
+/* Interrupt Threshold Control (1, 2, 4, 6, .. 64) */
+/*----------------------------------------------------------------------------------------*/
+#define UCMDR_INT_THR_CTRL (0x1< of QH */
+} qTD_T;
+
+
+#define QTD_LIST_END 0x1 /* Indicate the terminate of qTD list. */
+#define QTD_PTR(x) ((qTD_T *)((uint32_t)(x) & ~0x1F))
+
+/*
+ * Status: qTD Token[7:0]
+ */
+#define QTD_STS_PS_OUT (0<<0) /* directs the HC to issue an OUT PID */
+#define QTD_STS_PS_PING (1<<0) /* directs the HC to issue an PING PID */
+#define QTD_STS_SPLIT_STRAT (0<<1) /* directs the HC to issue an Start split */
+#define QTD_STS_SPLIT_COMPLETE (1<<1) /* directs the HC to issue an Complete split */
+#define QTD_STS_MISS_MF (1<<2) /* miss a required complete-split transaction */
+#define QTD_STS_XactErr (1<<3) /* Transaction Error occurred */
+#define QTD_STS_BABBLE (1<<4) /* Babble Detected */
+#define QTD_STS_DATA_BUFF_ERR (1<<5) /* Data Buffer Error */
+#define QTD_STS_HALT (1<<6) /* Halted */
+#define QTD_STS_ACTIVE (1<<7) /* Active */
+
+/*
+ * PID: qTD Token[9:8]
+ */
+#define QTD_PID_Msk (0x3<<8)
+#define QTD_PID_OUT (0<<8) /* generates token (E1H) */
+#define QTD_PID_IN (1<<8) /* generates token (69H) */
+#define QTD_PID_SETUP (2<<8) /* generates token (2DH) */
+
+#define QTD_ERR_COUNTER (3<<10) /* Token[11:10] */
+#define QTD_IOC (1<<15) /* Token[15] - Interrupt On Complete */
+#define QTD_TODO_LEN_Pos 16 /* Token[31:16] - Total Bytes to Transfer */
+#define QTD_TODO_LEN(x) (((x)>>16) & 0x7FFF)
+#define QTD_DT (1UL<<31) /* Token[31] - Data Toggle */
+
+/*----------------------------------------------------------------------------------------*/
+/* Queue Head (QH) */
+/*----------------------------------------------------------------------------------------*/
+typedef struct qh_t
+{
+ /* OHCI spec. Endpoint descriptor */
+ uint32_t HLink; /* Queue Head Horizontal Link Pointer */
+ uint32_t Chrst; /* Endpoint Characteristics: QH DWord 1 */
+ uint32_t Cap; /* Endpoint Capabilities: QH DWord 2 */
+ uint32_t Curr_qTD; /* Current qTD Pointer */
+ /*
+ * The followings are qTD Transfer Overlay
+ */
+ uint32_t OL_Next_qTD; /* Next qTD Pointer */
+ uint32_t OL_Alt_Next_qTD; /* Alternate Next qTD Pointer */
+ uint32_t OL_Token; /* qTD Token */
+ uint32_t OL_Bptr[5]; /* qTD Buffer Page Pointer List */
+ /*
+ * The following members are used by USB Host libary.
+ */
+ qTD_T *dummy; /* point to the inactive dummy qTD */
+ qTD_T *qtd_list; /* currently linked qTD transfers */
+ qTD_T *done_list; /* currently linked qTD transfers */
+ struct qh_t *next; /* point to the next QH in remove list */
+} QH_T;
+
+/* HLink[0] T field of "Queue Head Horizontal Link Pointer" */
+#define QH_HLNK_END 0x1
+
+/*
+ * HLink[2:1] Typ field of "Queue Head Horizontal Link Pointer"
+ */
+#define QH_HLNK_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0)
+#define QH_HLNK_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2)
+#define QH_HLNK_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4)
+#define QH_HLNK_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6)
+#define QH_PTR(x) ((QH_T *)((uint32_t)(x) & ~0x1F))
+
+/*
+ * Bit fields of "Endpoint Characteristics"
+ */
+#define QH_NAK_RL (4L<<28) /* Chrst[31:28] - NAK Count Reload */
+#define QH_CTRL_EP_FLAG (1<<27) /* Chrst[27] - Control Endpoint Flag */
+#define QH_RCLM_LIST_HEAD (1<<15) /* Chrst[15] - Head of Reclamation List Flag */
+#define QH_DTC (1<<14) /* Chrst[14] - Data Toggle Control */
+#define QH_EPS_FULL (0<<12) /* Chrst[13:12] - Endpoint Speed (Full) */
+#define QH_EPS_LOW (1<<12) /* Chrst[13:12] - Endpoint Speed (Low) */
+#define QH_EPS_HIGH (2<<12) /* Chrst[13:12] - Endpoint Speed (High) */
+#define QH_I_NEXT (1<<7) /* Chrst[7] - Inactivate on Next Transaction */
+
+/*
+ * Bit fields of "Endpoint Capabilities"
+ */
+#define QH_MULT_Pos 30 /* Cap[31:30] - High-Bandwidth Pipe Multiplier */
+#define QH_HUB_PORT_Pos 23 /* Cap[29:23] - Hub Port Number */
+#define QH_HUB_ADDR_Pos 16 /* Cap[22:16] - Hub Addr */
+#define QH_C_MASK_Msk 0xFF00 /* Cap[15:8] - uFrame C-mask */
+#define QH_S_MASK_Msk 0x00FF /* Cap[7:0] - uFrame S-mask */
+
+
+/*----------------------------------------------------------------------------------------*/
+/* Isochronous (High-Speed) Transfer Descriptor (iTD) */
+/*----------------------------------------------------------------------------------------*/
+typedef struct itd_t
+{
+ uint32_t Next_Link; /* Next Link Pointer */
+ uint32_t Transaction[8]; /* Transaction Status and Control */
+ uint32_t Bptr[7]; /* Buffer Page Pointer List */
+ /*
+ * The following members are used by USB Host libary.
+ */
+ struct iso_ep_t *iso_ep; /* associated isochronous information block */
+ struct utr_t *utr; /* associated UTR */
+ uint32_t buff_base; /* buffer base address */
+ uint8_t fidx; /* iTD's first index to UTR iso frames */
+ uint8_t trans_mask; /* mask of activated transactions in iTD */
+ uint32_t sched_frnidx; /* scheduled frame index */
+ struct itd_t *next; /* used by software to maintain iTD list */
+} iTD_T;
+
+/*
+ * Next_Link[2:1] Typ field of "Next Schedule Element Pointer" Typ field
+ */
+#define ITD_HLNK_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0)
+#define ITD_HLNK_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2)
+#define ITD_HLNK_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4)
+#define ITD_HLNK_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6)
+#define ITD_PTR(x) ((iTD_T *)((uint32_t)(x) & ~0x1F))
+
+/*
+ * Transaction[8]
+ */
+#define ITD_STATUS(x) (((x)>>28)&0xF)
+#define ITD_STATUS_ACTIVE (0x80000000UL) /* Active */
+#define ITD_STATUS_BUFF_ERR (0x40000000UL) /* Data Buffer Error */
+#define ITD_STATUS_BABBLE (0x20000000UL) /* Babble Detected */
+#define ITD_STATUS_XACT_ERR (0x10000000UL) /* Transcation Error */
+
+#define ITD_XLEN_Pos 16
+#define ITD_XFER_LEN(x) (((x)>>16)&0xFFF)
+#define ITD_IOC (1<<15)
+#define ITD_PG_Pos 12
+#define ITD_XFER_OFF_Msk 0xFFF
+
+/*
+ * Bptr[7]
+ */
+#define ITD_BUFF_PAGE_Pos 12
+/* Bptr[0] */
+#define ITD_EP_NUM_Pos 8
+#define ITD_EP_NUM(itd) (((itd)->Bptr[0]>>8)&0xF)
+#define ITD_DEV_ADDR_Pos 0
+#define ITD_DEV_ADDR(itd) ((itd)->Bptr[0]&0x7F)
+/* Bptr[1] */
+#define ITD_DIR_IN (1<<11)
+#define ITD_DIR_OUT (0<<11)
+#define ITD_MAX_PKTSZ_Pos 0
+#define ITD_MAX_PKTSZ(itd) ((itd)->Bptr[1]&0x7FF)
+
+/*----------------------------------------------------------------------------------------*/
+/* Split Isochronous (Full-Speed) Transfer Descriptor (siTD) */
+/*----------------------------------------------------------------------------------------*/
+typedef struct sitd_t
+{
+ uint32_t Next_Link; /* Next Link Pointer */
+ uint32_t Chrst; /* Endpoint and Transaction Translator Characteristics */
+ uint32_t Sched; /* Micro-frame Schedule Control */
+ uint32_t StsCtrl; /* siTD Transfer Status and Control */
+ uint32_t Bptr[2]; /* Buffer Page Pointer List */
+ uint32_t BackLink; /* siTD Back Link Pointer */
+ /*
+ * The following members are used by USB Host libary.
+ */
+ struct iso_ep_t *iso_ep; /* associated isochronous information block */
+ struct utr_t *utr; /* associated UTR */
+ uint8_t fidx; /* iTD's first index to UTR iso frames */
+ uint32_t sched_frnidx; /* scheduled frame index */
+ struct sitd_t *next; /* used by software to maintain siTD list */
+} siTD_T;
+
+#define SITD_LIST_END 0x1 /* Indicate the terminate of siTD list. */
+
+#define SITD_XFER_IO_Msk (1UL<<31)
+#define SITD_XFER_IN (1UL<<31)
+#define SITD_XFER_OUT (0UL<<31)
+
+#define SITD_PORT_NUM_Pos 24
+#define SITD_HUB_ADDR_Pos 16
+#define SITD_EP_NUM_Pos 8
+#define SITD_DEV_ADDR_Pos 0
+
+#define SITD_IOC (1UL<<31)
+#define SITD_XFER_CNT_Pos 16
+#define SITD_XFER_CNT_Msk (0x3FF<>28) & 0x0F)
+#define TD_CC_SET(td, cc) (td) = ((td) & 0x0FFFFFFF) | (((cc) & 0x0F) << 28)
+#define TD_T_DATA0 0x02000000
+#define TD_T_DATA1 0x03000000
+#define TD_R 0x00040000
+#define TD_DP 0x00180000
+#define TD_DP_IN 0x00100000
+#define TD_DP_OUT 0x00080000
+#define MAXPSW 8
+/* steel TD reserved bits to keep driver data */
+#define TD_TYPE_Msk (0x3<<16)
+#define TD_TYPE_CTRL (0x0<<16)
+#define TD_TYPE_BULK (0x1<<16)
+#define TD_TYPE_INT (0x2<<16)
+#define TD_TYPE_ISO (0x3<<16)
+#define TD_CTRL_Msk (0x7<<15)
+#define TD_CTRL_DATA (1<<15)
+
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of. It must be 256-byte aligned.
+ */
+typedef struct
+{
+ uint32_t int_table[32]; /* Interrupt ED table */
+ uint16_t frame_no; /* current frame number */
+ uint16_t pad1; /* set to 0 on each frame_no change */
+ uint32_t done_head; /* info returned for an interrupt */
+ uint8_t reserved_for_hc[116];
+} HCCA_T;
+
+
+/// @endcond
+
+#endif /* _USBH_OHCI_H_ */
diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/inc/usb.h b/bsp/nuvoton/libraries/m480/USBHostLib/inc/usb.h
new file mode 100644
index 00000000000..5d6772f27aa
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/USBHostLib/inc/usb.h
@@ -0,0 +1,486 @@
+/**************************************************************************//**
+ * @file usb.h
+ * @version V1.00
+ * @brief USB Host library header file.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef _USBH_H_
+#define _USBH_H_
+
+#include "config.h"
+#include "usbh_lib.h"
+#include "ehci.h"
+#include "ohci.h"
+
+/// @cond HIDDEN_SYMBOLS
+
+struct utr_t;
+struct udev_t;
+struct hub_dev_t;
+struct iface_t;
+struct ep_info_t;
+
+/*----------------------------------------------------------------------------------*/
+/* USB device request setup packet */
+/*----------------------------------------------------------------------------------*/
+#ifdef __ICCARM__
+typedef struct
+{
+ __packed uint8_t bmRequestType;
+ __packed uint8_t bRequest;
+ __packed uint16_t wValue;
+ __packed uint16_t wIndex;
+ __packed uint16_t wLength;
+} DEV_REQ_T;
+#else
+typedef struct __attribute__((__packed__))
+{
+ uint8_t bmRequestType;
+ uint8_t bRequest;
+ uint16_t wValue;
+ uint16_t wIndex;
+ uint16_t wLength;
+}
+DEV_REQ_T;
+#endif
+
+/*
+ * bmRequestType[7] - Data transfer direction
+ */
+#define REQ_TYPE_OUT 0x00
+#define REQ_TYPE_IN 0x80
+/*
+ * bmRequestType[6:5] - Type
+ */
+#define REQ_TYPE_STD_DEV 0x00
+#define REQ_TYPE_CLASS_DEV 0x20
+#define REQ_TYPE_VENDOR_DEV 0x40
+/*
+ * bmRequestType[4:0] - Recipient
+ */
+#define REQ_TYPE_TO_DEV 0x00
+#define REQ_TYPE_TO_IFACE 0x01
+#define REQ_TYPE_TO_EP 0x02
+#define REQ_TYPE_TO_OTHER 0x03
+/*
+ * Standard Requests
+ */
+#define USB_REQ_GET_STATUS 0x00
+#define USB_REQ_CLEAR_FEATURE 0x01
+#define USB_REQ_SET_FEATURE 0x03
+#define USB_REQ_SET_ADDRESS 0x05
+#define USB_REQ_GET_DESCRIPTOR 0x06
+#define USB_REQ_SET_CONFIGURATION 0x09
+#define USB_REQ_SET_INTERFACE 0x0B
+/*
+ * Descriptor Types
+ */
+#define USB_DT_STANDARD 0x00
+#define USB_DT_CLASS 0x20
+#define USB_DT_VENDOR 0x40
+
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONFIGURATION 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+#define USB_DT_DEVICE_QUALIFIER 0x06
+#define USB_DT_OTHER_SPEED_CONF 0x07
+#define USB_DT_IFACE_POWER 0x08
+
+
+
+/*----------------------------------------------------------------------------------*/
+/* USB standard descriptors */
+/*----------------------------------------------------------------------------------*/
+
+/* Descriptor header */
+#ifdef __ICCARM__
+typedef struct
+{
+ __packed uint8_t bLength;
+ __packed uint8_t bDescriptorType;
+} DESC_HDR_T;
+#else
+typedef struct __attribute__((__packed__))
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+}
+DESC_HDR_T;
+#endif
+
+/*----------------------------------------------------------------------------------*/
+/* USB device descriptor */
+/*----------------------------------------------------------------------------------*/
+#ifdef __ICCARM__
+typedef struct /*!< device descriptor structure */
+{
+ __packed uint8_t bLength; /*!< Length of device descriptor */
+ __packed uint8_t bDescriptorType; /*!< Device descriptor type */
+ __packed uint16_t bcdUSB; /*!< USB version number */
+ __packed uint8_t bDeviceClass; /*!< Device class code */
+ __packed uint8_t bDeviceSubClass; /*!< Device subclass code */
+ __packed uint8_t bDeviceProtocol; /*!< Device protocol code */
+ __packed uint8_t bMaxPacketSize0; /*!< Maximum packet size of control endpoint*/
+ __packed uint16_t idVendor; /*!< Vendor ID */
+ __packed uint16_t idProduct; /*!< Product ID */
+ __packed uint16_t bcdDevice; /*!< Device ID */
+ __packed uint8_t iManufacturer; /*!< Manufacture description string ID */
+ __packed uint8_t iProduct; /*!< Product description string ID */
+ __packed uint8_t iSerialNumber; /*!< Serial number description string ID */
+ __packed uint8_t bNumConfigurations; /*!< Total number of configurations */
+} DESC_DEV_T; /*!< device descriptor structure */
+#else
+/*----------------------------------------------------------------------------------*/
+/* USB device descriptor */
+/*----------------------------------------------------------------------------------*/
+typedef struct __attribute__((__packed__)) /*!< device descriptor structure */
+{
+ uint8_t bLength; /*!< Length of device descriptor */
+ uint8_t bDescriptorType; /*!< Device descriptor type */
+ uint16_t bcdUSB; /*!< USB version number */
+ uint8_t bDeviceClass; /*!< Device class code */
+ uint8_t bDeviceSubClass; /*!< Device subclass code */
+ uint8_t bDeviceProtocol; /*!< Device protocol code */
+ uint8_t bMaxPacketSize0; /*!< Maximum packet size of control endpoint*/
+ uint16_t idVendor; /*!< Vendor ID */
+ uint16_t idProduct; /*!< Product ID */
+ uint16_t bcdDevice; /*!< Device ID */
+ uint8_t iManufacturer; /*!< Manufacture description string ID */
+ uint8_t iProduct; /*!< Product description string ID */
+ uint8_t iSerialNumber; /*!< Serial number description string ID */
+ uint8_t bNumConfigurations; /*!< Total number of configurations */
+}
+DESC_DEV_T; /*!< device descriptor structure */
+#endif
+
+/*
+ * Configuration Descriptor
+ */
+#ifdef __ICCARM__
+typedef struct usb_config_descriptor /*!< Configuration descriptor structure */
+{
+ __packed uint8_t bLength; /*!< Length of configuration descriptor */
+ __packed uint8_t bDescriptorType; /*!< Descriptor type */
+ __packed uint16_t wTotalLength; /*!< Total length of this configuration */
+ __packed uint8_t bNumInterfaces; /*!< Total number of interfaces */
+ __packed uint8_t bConfigurationValue; /*!< Configuration descriptor number */
+ __packed uint8_t iConfiguration; /*!< String descriptor ID */
+ __packed uint8_t bmAttributes; /*!< Configuration characteristics */
+ __packed uint8_t MaxPower; /*!< Maximum power consumption */
+} DESC_CONF_T; /*!< Configuration descriptor structure */
+#else
+typedef struct __attribute__((__packed__)) usb_config_descriptor /*!< Configuration descriptor structure */
+{
+ uint8_t bLength; /*!< Length of configuration descriptor */
+ uint8_t bDescriptorType; /*!< Descriptor type */
+ uint16_t wTotalLength; /*!< Total length of this configuration */
+ uint8_t bNumInterfaces; /*!< Total number of interfaces */
+ uint8_t bConfigurationValue; /*!< Configuration descriptor number */
+ uint8_t iConfiguration; /*!< String descriptor ID */
+ uint8_t bmAttributes; /*!< Configuration characteristics */
+ uint8_t MaxPower; /*!< Maximum power consumption */
+} DESC_CONF_T; /*!< Configuration descriptor structure */
+#endif
+
+/*
+ * Interface Descriptor
+ */
+#ifdef __ICCARM__
+typedef struct usb_interface_descriptor /*!< Interface descriptor structure */
+{
+ __packed uint8_t bLength; /*!< Length of interface descriptor */
+ __packed uint8_t bDescriptorType; /*!< Descriptor type */
+ __packed uint8_t bInterfaceNumber; /*!< Interface number */
+ __packed uint8_t bAlternateSetting;/*!< Alternate setting number */
+ __packed uint8_t bNumEndpoints; /*!< Number of endpoints */
+ __packed uint8_t bInterfaceClass; /*!< Interface class code */
+ __packed uint8_t bInterfaceSubClass; /*!< Interface subclass code */
+ __packed uint8_t bInterfaceProtocol; /*!< Interface protocol code */
+ __packed uint8_t iInterface; /*!< Interface ID */
+} DESC_IF_T; /*!< Interface descriptor structure */
+#else
+typedef struct __attribute__((__packed__)) usb_interface_descriptor /*!< Interface descriptor structure */
+{
+ uint8_t bLength; /*!< Length of interface descriptor */
+ uint8_t bDescriptorType; /*!< Descriptor type */
+ uint8_t bInterfaceNumber; /*!< Interface number */
+ uint8_t bAlternateSetting; /*!< Alternate setting number */
+ uint8_t bNumEndpoints; /*!< Number of endpoints */
+ uint8_t bInterfaceClass; /*!< Interface class code */
+ uint8_t bInterfaceSubClass; /*!< Interface subclass code */
+ uint8_t bInterfaceProtocol; /*!< Interface protocol code */
+ uint8_t iInterface; /*!< Interface ID */
+} DESC_IF_T; /*!< Interface descriptor structure */
+#endif
+
+/*
+ * Interface descriptor bInterfaceClass[7:0]
+ */
+#if 0
+#define USB_CLASS_AUDIO 0x01
+#define USB_CLASS_COMM 0x02
+#define USB_CLASS_HID 0x03
+#define USB_CLASS_PRINTER 0x07
+#define USB_CLASS_MASS_STORAGE 0x08
+#define USB_CLASS_HUB 0x09
+#define USB_CLASS_DATA 0x0A
+#define USB_CLASS_VIDEO 0x0E
+#endif
+/*
+ * Endpoint Descriptor
+ */
+#ifdef __ICCARM__
+typedef struct usb_endpoint_descriptor /*!< Endpoint descriptor structure */
+{
+ __packed uint8_t bLength; /*!< Length of endpoint descriptor */
+ __packed uint8_t bDescriptorType; /*!< Descriptor type */
+ __packed uint8_t bEndpointAddress; /*!< Endpoint address */
+ __packed uint8_t bmAttributes; /*!< Endpoint attribute */
+ __packed uint16_t wMaxPacketSize; /*!< Maximum packet size */
+ __packed uint8_t bInterval; /*!< Synchronous transfer interval */
+ __packed uint8_t bRefresh; /*!< Refresh */
+ __packed uint8_t bSynchAddress; /*!< Sync address */
+} DESC_EP_T; /*!< Endpoint descriptor structure */
+#else
+typedef struct __attribute__((__packed__)) usb_endpoint_descriptor /*!< Endpoint descriptor structure */
+{
+ uint8_t bLength; /*!< Length of endpoint descriptor */
+ uint8_t bDescriptorType; /*!< Descriptor type */
+ uint8_t bEndpointAddress; /*!< Endpoint address */
+ uint8_t bmAttributes; /*!< Endpoint attribute */
+ uint16_t wMaxPacketSize; /*!< Maximum packet size */
+ uint8_t bInterval; /*!< Synchronous transfer interval */
+ uint8_t bRefresh; /*!< Refresh */
+ uint8_t bSynchAddress; /*!< Sync address */
+} DESC_EP_T; /*!< Endpoint descriptor structure */
+#endif
+
+/*
+ * Endpoint descriptor bEndpointAddress[7] - direction
+ */
+#define EP_ADDR_DIR_MASK 0x80
+#define EP_ADDR_DIR_IN 0x80
+#define EP_ADDR_DIR_OUT 0x00
+
+/*
+ * Endpoint descriptor bmAttributes[1:0] - transfer type
+ */
+#define EP_ATTR_TT_MASK 0x03
+#define EP_ATTR_TT_CTRL 0x00
+#define EP_ATTR_TT_ISO 0x01
+#define EP_ATTR_TT_BULK 0x02
+#define EP_ATTR_TT_INT 0x03
+
+
+/*----------------------------------------------------------------------------------*/
+/* USB Host controller driver */
+/*----------------------------------------------------------------------------------*/
+typedef struct
+{
+ int (*init) (void);
+ void (*shutdown) (void);
+ void (*suspend) (void);
+ void (*resume) (void);
+ int (*ctrl_xfer)(struct utr_t *utr);
+ int (*bulk_xfer)(struct utr_t *utr);
+ int (*int_xfer)(struct utr_t *utr);
+ int (*iso_xfer)(struct utr_t *utr);
+ int (*quit_xfer)(struct utr_t *utr, struct ep_info_t *ep);
+
+ /* root hub support */
+ int (*rthub_port_reset)(int port);
+ int (*rthub_polling) (void);
+} HC_DRV_T;
+
+
+/*----------------------------------------------------------------------------------*/
+/* USB device driver */
+/*----------------------------------------------------------------------------------*/
+typedef struct
+{
+ int (*probe) (struct iface_t *iface);
+ void (*disconnect) (struct iface_t *iface);
+ void (*suspend) (struct iface_t *iface);
+ void (*resume) (struct iface_t *iface);
+} UDEV_DRV_T;
+
+
+/*----------------------------------------------------------------------------------*/
+/* USB device */
+/*----------------------------------------------------------------------------------*/
+
+typedef enum
+{
+ SPEED_LOW,
+ SPEED_FULL,
+ SPEED_HIGH
+} SPEED_E;
+
+typedef struct ep_info_t
+{
+ uint8_t bEndpointAddress;
+ uint8_t bmAttributes;
+ uint8_t bInterval;
+ uint8_t bToggle;
+ uint16_t wMaxPacketSize;
+ void *hw_pipe; /*!< point to the HC assocaied endpoint \hideinitializer */
+} EP_INFO_T;
+
+typedef struct udev_t
+{
+ DESC_DEV_T descriptor; /*!< Device descriptor. \hideinitializer */
+ struct hub_dev_t *parent; /*!< parent hub device \hideinitializer */
+ uint8_t port_num; /*!< The hub port this device connected on \hideinitializer */
+ uint8_t dev_num; /*!< device number \hideinitializer */
+ int8_t cur_conf; /*!< Currentll selected configuration \hideinitializer */
+ SPEED_E speed; /*!< device speed (low/full/high) \hideinitializer */
+ /*
+ * The followings are lightweight USB stack internal used .
+ */
+ uint8_t *cfd_buff; /*!< Configuration descriptor buffer. \hideinitializer */
+ EP_INFO_T ep0; /*!< Endpoint 0 \hideinitializer */
+ HC_DRV_T *hc_driver; /*!< host controller driver \hideinitializer */
+ struct iface_t *iface_list; /*!< Working interface list \hideinitializer */
+ struct udev_t *next; /*!< link for global usb device list \hideinitializer */
+} UDEV_T;
+
+typedef struct alt_iface_t
+{
+ DESC_IF_T *ifd; /*!< point to the location of this alternative interface descriptor in UDEV_T->cfd_buff */
+ EP_INFO_T ep[MAX_EP_PER_IFACE]; /*!< endpoints of this alternative interface */
+} ALT_IFACE_T;
+
+typedef struct iface_t
+{
+ UDEV_T *udev; /*!< USB device \hideinitializer */
+ uint8_t if_num; /*!< Interface number \hideinitializer */
+ uint8_t num_alt; /*!< Number of alternative interface \hideinitializer */
+ ALT_IFACE_T *aif; /*!< Point to the active alternative interface */
+ ALT_IFACE_T alt[MAX_ALT_PER_IFACE]; /*!< List of alternative interface \hideinitializer */
+ UDEV_DRV_T *driver; /*!< Interface associated driver \hideinitializer */
+ void *context; /*!< Reference to device context \hideinitializer */
+ struct iface_t *next; /*!< Point to next interface of the same device. Started from UDEV_T->iface_list \hideinitializer */
+} IFACE_T;
+
+
+/*----------------------------------------------------------------------------------*/
+/* URB (USB Request Block) */
+/*----------------------------------------------------------------------------------*/
+
+#define IF_PER_UTR 8 /* number of frames per UTR isochronous transfer (DO NOT modify it!) */
+
+typedef void (*FUNC_UTR_T)(struct utr_t *);
+
+typedef struct utr_t
+{
+ UDEV_T *udev; /*!< point to associated USB device \hideinitializer */
+ DEV_REQ_T setup; /*!< buffer for setup packet \hideinitializer */
+ EP_INFO_T *ep; /*!< associated endpoint \hideinitializer */
+ uint8_t *buff; /*!< transfer buffer \hideinitializer */
+ uint8_t bIsTransferDone; /*!< tansfer done? \hideinitializer */
+ uint32_t data_len; /*!< length of data to be transferred \hideinitializer */
+ uint32_t xfer_len; /*!< length of transferred data \hideinitializer */
+ uint8_t bIsoNewSched; /*!< New schedule isochronous transfer \hideinitializer */
+ uint16_t iso_sf; /*!< Isochronous start frame number \hideinitializer */
+ uint16_t iso_xlen[IF_PER_UTR]; /*!< transfer length of isochronous frames \hideinitializer */
+ uint8_t * iso_buff[IF_PER_UTR]; /*!< transfer buffer address of isochronous frames \hideinitializer */
+ int iso_status[IF_PER_UTR]; /*!< transfer status of isochronous frames \hideinitializer */
+ int td_cnt; /*!< number of transfer descriptors \hideinitializer */
+ int status; /*!< return status \hideinitializer */
+ int interval; /*!< interrupt/isochronous interval \hideinitializer */
+ void *context; /*!< point to deivce proprietary data area \hideinitializer */
+ FUNC_UTR_T func; /*!< tansfer done call-back function \hideinitializer */
+ struct utr_t *next; /* point to the next UTR of the same endpoint. \hideinitializer */
+} UTR_T;
+
+
+/*----------------------------------------------------------------------------------*/
+/* Global variables */
+/*----------------------------------------------------------------------------------*/
+extern USBH_T *_ohci;
+extern HSUSBH_T *_ehci;
+
+extern HC_DRV_T ohci_driver;
+extern HC_DRV_T ehci_driver;
+
+extern UDEV_T * g_udev_list;
+
+/*----------------------------------------------------------------------------------*/
+/* USB stack exported functions */
+/*----------------------------------------------------------------------------------*/
+extern void usbh_delay_ms(int msec);
+
+extern void dump_ohci_regs(void);
+extern void dump_ohci_ports(void);
+extern void dump_ohci_int_table(void);
+extern void dump_ehci_regs(void);
+extern void dump_ehci_qtd(qTD_T *qtd);
+extern void dump_ehci_asynclist(void);
+extern void dump_ehci_period_frame_list_simple(void);
+extern void usbh_dump_buff_bytes(uint8_t *buff, int nSize);
+extern void usbh_dump_interface_descriptor(DESC_IF_T *if_desc);
+extern void usbh_dump_endpoint_descriptor(DESC_EP_T *ep_desc);
+extern void usbh_dump_iface(IFACE_T *iface);
+extern void usbh_dump_ep_info(EP_INFO_T *ep);
+
+/*
+ * Memory management functions
+ */
+extern void usbh_memory_init(void);
+extern uint32_t usbh_memory_used(void);
+extern void * usbh_alloc_mem(int size);
+extern void usbh_free_mem(void *p, int size);
+extern int alloc_dev_address(void);
+extern void free_dev_address(int dev_addr);
+extern UDEV_T * alloc_device(void);
+extern void free_device(UDEV_T *udev);
+extern UTR_T * alloc_utr(UDEV_T *udev);
+extern void free_utr(UTR_T *utr);
+extern ED_T * alloc_ohci_ED(void);
+extern void free_ohci_ED(ED_T *ed);
+extern TD_T * alloc_ohci_TD(UTR_T *utr);
+extern void free_ohci_TD(TD_T *td);
+extern QH_T * alloc_ehci_QH(void);
+extern void free_ehci_QH(QH_T *qh);
+extern qTD_T * alloc_ehci_qTD(UTR_T *utr);
+extern void free_ehci_qTD(qTD_T *qtd);
+extern iTD_T * alloc_ehci_iTD(void);
+extern void free_ehci_iTD(iTD_T *itd);
+extern siTD_T * alloc_ehci_siTD(void);
+extern void free_ehci_siTD(siTD_T *sitd);
+
+
+extern void usbh_hub_init(void);
+extern int usbh_connect_device(UDEV_T *);
+extern void usbh_disconnect_device(UDEV_T *);
+extern int usbh_register_driver(UDEV_DRV_T *driver);
+extern EP_INFO_T * usbh_iface_find_ep(IFACE_T *iface, uint8_t ep_addr, uint8_t dir_type);
+extern int usbh_reset_device(UDEV_T *);
+extern int usbh_reset_port(UDEV_T *);
+
+/*
+ * USB Standard Request functions
+ */
+extern int usbh_get_device_descriptor(UDEV_T *udev, DESC_DEV_T *desc_buff);
+extern int usbh_get_config_descriptor(UDEV_T *udev, uint8_t *desc_buff, int buff_len);
+extern int usbh_set_configuration(UDEV_T *udev, uint8_t conf_val);
+extern int usbh_set_interface(IFACE_T *iface, uint16_t alt_setting);
+extern int usbh_clear_halt(UDEV_T *udev, uint16_t ep_addr);
+
+extern int usbh_ctrl_xfer(UDEV_T *udev, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t *buff, uint32_t *xfer_len, uint32_t timeout);
+extern int usbh_bulk_xfer(UTR_T *utr);
+extern int usbh_int_xfer(UTR_T *utr);
+extern int usbh_iso_xfer(UTR_T *utr);
+extern int usbh_quit_utr(UTR_T *utr);
+extern int usbh_quit_xfer(UDEV_T *udev, EP_INFO_T *ep);
+
+
+/// @endcond HIDDEN_SYMBOLS
+
+#endif /* _USBH_H_ */
diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/inc/usbh_lib.h b/bsp/nuvoton/libraries/m480/USBHostLib/inc/usbh_lib.h
new file mode 100644
index 00000000000..7b8795b72e6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/USBHostLib/inc/usbh_lib.h
@@ -0,0 +1,186 @@
+/**************************************************************************//**
+ * @file usbh_lib.h
+ * @version V1.10
+ * @brief USB Host library exported header file.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef _USBH_LIB_H_
+#define _USBH_LIB_H_
+
+#include "NuMicro.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup LIBRARY Library
+ @{
+*/
+
+/** @addtogroup USBH_Library USB Host Library
+ @{
+*/
+
+/** @addtogroup USBH_EXPORTED_CONSTANTS USB Host Exported Constants
+ @{
+*/
+
+#define USBH_OK 0 /*!< No error. */
+#define USBH_ERR_MEMORY_OUT -10 /*!< Out of memory. */
+#define USBH_ERR_IF_ALT_LIMIT -11 /*!< Number of alternative interface > MAX_ALT_PER_IFACE */
+#define USBH_ERR_IF_EP_LIMIT -15 /*!< Number of endpoints > MAX_EP_PER_IFACE */
+#define USBH_ERR_NOT_SUPPORTED -101 /*!< Device/Class/Transfer not supported */
+#define USBH_ERR_NOT_MATCHED -103 /*!< Not macthed */
+#define USBH_ERR_NOT_EXPECTED -104 /*!< Unknown or unexpected */
+#define USBH_ERR_INVALID_PARAM -105 /*!< Invalid parameter */
+#define USBH_ERR_NOT_FOUND -106 /*!< Device or interface not found */
+#define USBH_ERR_EP_NOT_FOUND -107 /*!< Endpoint not found */
+#define USBH_ERR_DESCRIPTOR -137 /*!< Failed to parse USB descriptors */
+#define USBH_ERR_SET_DEV_ADDR -139 /*!< Failed to set device address */
+#define USBH_ERR_SET_CONFIG -151 /*!< Failed to set device configuration */
+
+#define USBH_ERR_TRANSFER -201 /*!< USB transfer error */
+#define USBH_ERR_TIMEOUT -203 /*!< USB transfer time-out */
+#define USBH_ERR_ABORT -205 /*!< USB transfer aborted due to disconnect or reset */
+#define USBH_ERR_PORT_RESET -255 /*!< Hub port reset failed */
+#define USBH_ERR_SCH_OVERRUN -257 /*!< USB isochronous schedule overrun */
+#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */
+
+#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */
+#define USBH_ERR_BABBLE_DETECTED -272 /*!< A ¡§babble¡¨ is detected during the transaction */
+#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */
+
+#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */
+#define USBH_ERR_CRC -281 /*!< USB trasfer CRC error */
+#define USBH_ERR_BIT_STUFF -282 /*!< USB transfer bit stuffing error */
+#define USBH_ERR_DATA_TOGGLE -283 /*!< USB trasfer data toggle error */
+#define USBH_ERR_STALL -284 /*!< USB trasfer STALL error */
+#define USBH_ERR_DEV_NO_RESP -285 /*!< USB trasfer device no response error */
+#define USBH_ERR_PID_CHECK -286 /*!< USB trasfer PID check failure */
+#define USBH_ERR_UNEXPECT_PID -287 /*!< USB trasfer unexpected PID error */
+#define USBH_ERR_DATA_OVERRUN -288 /*!< USB trasfer data overrun error */
+#define USBH_ERR_DATA_UNDERRUN -289 /*!< USB trasfer data underrun error */
+#define USBH_ERR_BUFF_OVERRUN -292 /*!< USB trasfer buffer overrun error */
+#define USBH_ERR_BUFF_UNDERRUN -293 /*!< USB trasfer buffer underrun error */
+#define USBH_ERR_NOT_ACCESS0 -294 /*!< USB trasfer not accessed error */
+#define USBH_ERR_NOT_ACCESS1 -295 /*!< USB trasfer not accessed error */
+
+#define USBH_ERR_OHCI_INIT -301 /*!< Failed to initialize OHIC controller. */
+#define USBH_ERR_OHCI_EP_BUSY -303 /*!< The endpoint is under transfer. */
+
+#define USBH_ERR_EHCI_INIT -501 /*!< Failed to initialize EHCI controller. */
+#define USBH_ERR_EHCI_QH_BUSY -503 /*!< the Queue Head is busy. */
+
+#define UMAS_OK 0 /*!< No error. */
+#define UMAS_ERR_NO_DEVICE -1031 /*!< No Mass Stroage Device found. */
+#define UMAS_ERR_IO -1033 /*!< Device read/write failed. */
+#define UMAS_ERR_INIT_DEVICE -1035 /*!< failed to init MSC device */
+#define UMAS_ERR_CMD_STATUS -1037 /*!< SCSI command status failed */
+#define UMAS_ERR_IVALID_PARM -1038 /*!< Invalid parameter. */
+#define UMAS_ERR_DRIVE_NOT_FOUND -1039 /*!< drive not found */
+
+#define HID_RET_OK 0 /*!< Return with no errors. */
+#define HID_RET_DEV_NOT_FOUND -1081 /*!< HID device not found or removed. */
+#define HID_RET_IO_ERR -1082 /*!< USB transfer failed. */
+#define HID_RET_INVALID_PARAMETER -1083 /*!< Invalid parameter. */
+#define HID_RET_OUT_OF_MEMORY -1084 /*!< Out of memory. */
+#define HID_RET_NOT_SUPPORTED -1085 /*!< Function not supported. */
+#define HID_RET_EP_NOT_FOUND -1086 /*!< Endpoint not found. */
+#define HID_RET_PARSING -1087 /*!< Failed to parse HID descriptor */
+#define HID_RET_XFER_IS_RUNNING -1089 /*!< The transfer has been enabled. */
+#define HID_RET_REPORT_NOT_FOUND -1090 /*!< The transfer has been enabled. */
+
+#define UAC_RET_OK 0 /*!< Return with no errors. */
+#define UAC_RET_DEV_NOT_FOUND -2001 /*!< Audio Class device not found or removed. */
+#define UAC_RET_FUNC_NOT_FOUND -2002 /*!< Audio device has no this function. */
+#define UAC_RET_IO_ERR -2003 /*!< USB transfer failed. */
+#define UAC_RET_DATA_LEN -2004 /*!< Unexpected transfer length */
+#define UAC_RET_INVALID -2005 /*!< Invalid parameter or usage. */
+#define UAC_RET_OUT_OF_MEMORY -2007 /*!< Out of memory. */
+#define UAC_RET_DRV_NOT_SUPPORTED -2009 /*!< Function not supported by this UAC driver. */
+#define UAC_RET_DEV_NOT_SUPPORTED -2011 /*!< Function not supported by the UAC device. */
+#define UAC_RET_PARSER -2013 /*!< Failed to parse UAC descriptor */
+#define UAC_RET_IS_STREAMING -2015 /*!< Audio pipe is on streaming. */
+
+
+/*@}*/ /* end of group USBH_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USBH_EXPORTED_TYPEDEF USB Host Typedef
+ @{
+*/
+struct udev_t;
+typedef void (CONN_FUNC)(struct udev_t *udev, int param);
+
+struct line_coding_t;
+struct cdc_dev_t;
+typedef void (CDC_CB_FUNC)(struct cdc_dev_t *cdev, uint8_t *rdata, int data_len);
+
+struct usbhid_dev;
+typedef void (HID_IR_FUNC)(struct usbhid_dev *hdev, uint16_t ep_addr, int status, uint8_t *rdata, uint32_t data_len); /*!< interrupt in callback function \hideinitializer */
+typedef void (HID_IW_FUNC)(struct usbhid_dev *hdev, uint16_t ep_addr, int status, uint8_t *wbuff, uint32_t *data_len); /*!< interrupt out callback function \hideinitializer */
+
+struct uac_dev_t;
+typedef int (UAC_CB_FUNC)(struct uac_dev_t *dev, uint8_t *data, int len); /*!< audio in callback function \hideinitializer */
+
+/*@}*/ /* end of group USBH_EXPORTED_STRUCT */
+
+
+
+/** @addtogroup USBH_EXPORTED_FUNCTIONS USB Host Exported Functions
+ @{
+*/
+
+/*------------------------------------------------------------------*/
+/* */
+/* USB Core Library APIs */
+/* */
+/*------------------------------------------------------------------*/
+extern void usbh_core_init(void);
+extern int usbh_pooling_root_hubs(void);
+extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func);
+extern void usbh_suspend(void);
+extern void usbh_resume(void);
+extern struct udev_t * usbh_find_device(char *hub_id, int port);
+
+/**
+ * @brief A function return current tick count.
+ * @return Current tick.
+ * @details User application must provide this function to return current tick.
+ * The tick should increase by 1 for every 10 ms.
+ */
+extern uint32_t usbh_get_ticks(void); /* This function must be provided by user application. */
+extern uint32_t usbh_tick_from_millisecond(uint32_t msec); /* This function must be provided by user application. */
+
+
+/// @cond HIDDEN_SYMBOLS
+
+extern void dump_ohci_regs(void);
+extern void dump_ehci_regs(void);
+extern void dump_ohci_ports(void);
+extern void dump_ehci_ports(void);
+extern uint32_t usbh_memory_used(void);
+
+/// @endcond HIDDEN_SYMBOLS
+
+
+/*@}*/ /* end of group USBH_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USBH_Library */
+
+/*@}*/ /* end of group LIBRARY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _USBH_LIB_H_ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
+
+
+
diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci.c b/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci.c
new file mode 100644
index 00000000000..9138c237a49
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci.c
@@ -0,0 +1,1306 @@
+/**************************************************************************//**
+ * @file ehci.c
+ * @version V1.10
+ * @brief USB Host library EHCI (USB 2.0) host controller driver.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include
+#include
+
+#include "NuMicro.h"
+
+#include "usb.h"
+#include "hub.h"
+
+
+/// @cond HIDDEN_SYMBOLS
+
+static QH_T *_H_qh; /* head of reclamation list */
+static qTD_T *_ghost_qtd; /* used as a terminator qTD */
+static QH_T *qh_remove_list;
+
+extern ISO_EP_T *iso_ep_list; /* list of activated isochronous pipes */
+extern int ehci_iso_xfer(UTR_T *utr); /* EHCI isochronous transfer function */
+extern int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep);
+
+#ifdef __ICCARM__
+#pragma data_alignment=4096
+uint32_t _PFList[FL_SIZE]; /* Periodic frame list (IAR) */
+#else
+uint32_t _PFList[FL_SIZE] __attribute__((aligned(4096))); /* Periodic frame list */
+#endif
+
+QH_T * _Iqh[NUM_IQH];
+
+
+#ifdef ENABLE_ERROR_MSG
+void dump_ehci_regs()
+{
+ USB_debug("Dump HSUSBH(EHCI) registers:\n");
+ USB_debug(" UCMDR = 0x%x\n", _ehci->UCMDR);
+ USB_debug(" USTSR = 0x%x\n", _ehci->USTSR);
+ USB_debug(" UIENR = 0x%x\n", _ehci->UIENR);
+ USB_debug(" UFINDR = 0x%x\n", _ehci->UFINDR);
+ USB_debug(" UPFLBAR = 0x%x\n", _ehci->UPFLBAR);
+ USB_debug(" UCALAR = 0x%x\n", _ehci->UCALAR);
+ USB_debug(" UASSTR = 0x%x\n", _ehci->UASSTR);
+ USB_debug(" UCFGR = 0x%x\n", _ehci->UCFGR);
+ USB_debug(" UPSCR = 0x%x\n", _ehci->UPSCR[0]);
+ USB_debug(" PHYCTL0 = 0x%x\n", _ehci->USBPCR0);
+ USB_debug(" PHYCTL1 = 0x%x\n", _ehci->USBPCR1);
+}
+
+void dump_ehci_ports()
+{
+ USB_debug("_ehci port0=0x%x, port1=0x%x\n", _ehci->UPSCR[0], _ehci->UPSCR[1]);
+}
+
+void dump_ehci_qtd(qTD_T *qtd)
+{
+ USB_debug(" [qTD] - 0x%08x\n", (int)qtd);
+ USB_debug(" 0x%08x (Next qtd Pointer)\n", qtd->Next_qTD);
+ USB_debug(" 0x%08x (Alternate Next qtd Pointer)\n", qtd->Alt_Next_qTD);
+ USB_debug(" 0x%08x (qtd Token) PID: %s, Bytes: %d, IOC: %d\n", qtd->Token, (((qtd->Token>>8)&0x3)==0) ? "OUT" : ((((qtd->Token>>8)&0x3)==1) ? "IN" : "SETUP"), (qtd->Token>>16)&0x7FFF, (qtd->Token>>15)&0x1);
+ USB_debug(" 0x%08x (Buffer Pointer (page 0))\n", qtd->Bptr[0]);
+ //USB_debug(" 0x%08x (Buffer Pointer (page 1))\n", qtd->Bptr[1]);
+ //USB_debug(" 0x%08x (Buffer Pointer (page 2))\n", qtd->Bptr[2]);
+ //USB_debug(" 0x%08x (Buffer Pointer (page 3))\n", qtd->Bptr[3]);
+ //USB_debug(" 0x%08x (Buffer Pointer (page 4))\n", qtd->Bptr[4]);
+ USB_debug("\n");
+}
+
+void dump_ehci_asynclist(void)
+{
+ QH_T *qh = _H_qh;
+ qTD_T *qtd;
+
+ USB_debug(">>> Dump EHCI Asynchronous List <<<\n");
+ do
+ {
+ USB_debug("[QH] - 0x%08x\n", (int)qh);
+ USB_debug(" 0x%08x (Queue Head Horizontal Link Pointer, Queue Head DWord 0)\n", qh->HLink);
+ USB_debug(" 0x%08x (Endpoint Characteristics) DevAddr: %d, EP: 0x%x, PktSz: %d, Speed: %s\n", qh->Chrst, qh->Chrst&0x7F, (qh->Chrst>>8)&0xF, (qh->Chrst>>16)&0x7FF, ((qh->Chrst>>12)&0x3 == 0) ? "Full" : (((qh->Chrst>>12)&0x3 == 1) ? "Low" : "High"));
+ USB_debug(" 0x%08x (Endpoint Capabilities: Queue Head DWord 2)\n", qh->Cap);
+ USB_debug(" 0x%08x (Current qtd Pointer)\n", qh->Curr_qTD);
+ USB_debug(" --- Overlay Area ---\n");
+ USB_debug(" 0x%08x (Next qtd Pointer)\n", qh->OL_Next_qTD);
+ USB_debug(" 0x%08x (Alternate Next qtd Pointer)\n", qh->OL_Alt_Next_qTD);
+ USB_debug(" 0x%08x (qtd Token)\n", qh->OL_Token);
+ USB_debug(" 0x%08x (Buffer Pointer (page 0))\n", qh->OL_Bptr[0]);
+ USB_debug("\n");
+
+ qtd = QTD_PTR(qh->Curr_qTD);
+ while (qtd != NULL)
+ {
+ dump_ehci_qtd(qtd);
+ qtd = QTD_PTR(qtd->Next_qTD);
+ }
+ qh = QH_PTR(qh->HLink);
+ }
+ while (qh != _H_qh);
+}
+
+void dump_ehci_asynclist_simple(void)
+{
+ QH_T *qh = _H_qh;
+
+ USB_debug(">>> EHCI Asynchronous List <<<\n");
+ USB_debug("[QH] => ");
+ do
+ {
+ USB_debug("0x%08x ", (int)qh);
+ qh = QH_PTR(qh->HLink);
+ }
+ while (qh != _H_qh);
+ USB_debug("\n");
+}
+
+void dump_ehci_period_frame_list_simple(void)
+{
+ QH_T *qh = _Iqh[NUM_IQH-1];
+
+ USB_debug(">>> EHCI period frame list simple <<<\n");
+ USB_debug("[FList] => ");
+ do
+ {
+ USB_debug("0x%08x ", (int)qh);
+ qh = QH_PTR(qh->HLink);
+ }
+ while (qh != NULL);
+ USB_debug("\n");
+}
+
+void dump_ehci_period_frame_list()
+{
+ int i;
+ QH_T *qh;
+
+ for (i = 0; i < FL_SIZE; i++)
+ {
+ USB_debug("!%02d: ", i);
+ qh = QH_PTR(_PFList[i]);;
+ while (qh != NULL)
+ {
+ // USB_debug("0x%x (0x%x) => ", (int)qh, qh->HLink);
+ USB_debug("0x%x => ", (int)qh);
+ qh = QH_PTR(qh->HLink);
+ }
+ USB_debug("0\n");
+ }
+}
+
+#endif /* ENABLE_ERROR_MSG */
+
+static void init_periodic_frame_list()
+{
+ QH_T *qh_p;
+ int i, idx, interval;
+
+ memset(_PFList, 0, sizeof(_PFList));
+
+ iso_ep_list = NULL;
+
+ for (i = NUM_IQH-1; i >= 0; i--) /* interval = i^2 */
+ {
+ _Iqh[i] = alloc_ehci_QH();
+
+ _Iqh[i]->HLink = QH_HLNK_END;
+ _Iqh[i]->Curr_qTD = (uint32_t)_ghost_qtd;
+ _Iqh[i]->OL_Next_qTD = QTD_LIST_END;
+ _Iqh[i]->OL_Alt_Next_qTD = (uint32_t)_ghost_qtd;
+ _Iqh[i]->OL_Token = QTD_STS_HALT;
+
+ interval = 0x1 << i;
+
+ for (idx = interval - 1; idx < FL_SIZE; idx += interval)
+ {
+ if (_PFList[idx] == 0) /* is empty list, insert directly */
+ {
+ _PFList[idx] = QH_HLNK_QH(_Iqh[i]);
+ }
+ else
+ {
+ qh_p = QH_PTR(_PFList[idx]);
+
+ while (1)
+ {
+ if (qh_p == _Iqh[i])
+ break; /* already chained by previous visit */
+
+ if (qh_p->HLink == QH_HLNK_END) /* reach end of list? */
+ {
+ qh_p->HLink = QH_HLNK_QH(_Iqh[i]);
+ break;
+ }
+ qh_p = QH_PTR(qh_p->HLink);
+ }
+ }
+ }
+ }
+}
+
+static QH_T * get_int_tree_head_node(int interval)
+{
+ int i;
+
+ interval /= 8; /* each frame list entry for 8 micro-frame */
+
+ for (i = 0; i < NUM_IQH-1; i++)
+ {
+ interval >>= 1;
+ if (interval == 0)
+ return _Iqh[i];
+ }
+ return _Iqh[NUM_IQH-1];
+}
+
+static int make_int_s_mask(int bInterval)
+{
+ int order, interval;
+
+ interval = 1;
+ while (bInterval > 1)
+ {
+ interval *= 2;
+ bInterval--;
+ }
+
+ if (interval < 2)
+ return 0xFF; /* interval 1 */
+ if (interval < 4)
+ return 0x55; /* interval 2 */
+ if (interval < 8)
+ return 0x22; /* interval 4 */
+ for (order = 0; (interval > 1); order++)
+ {
+ interval >>= 1;
+ }
+ return (0x1 << (order % 8));
+}
+
+static int ehci_init(void)
+{
+ int timeout = 250*1000; /* EHCI reset time-out 250 ms */
+
+ /*------------------------------------------------------------------------------------*/
+ /* Reset EHCI host controller */
+ /*------------------------------------------------------------------------------------*/
+ _ehci->UCMDR = HSUSBH_UCMDR_HCRST_Msk;
+ while ((_ehci->UCMDR & HSUSBH_UCMDR_HCRST_Msk) && (timeout > 0))
+ {
+ usbh_delay_ms(1);
+ timeout -= 1000;
+ }
+ if (_ehci->UCMDR & HSUSBH_UCMDR_HCRST_Msk)
+ return USBH_ERR_EHCI_INIT;
+
+ _ehci->UCMDR = UCMDR_INT_THR_CTRL | HSUSBH_UCMDR_RUN_Msk;
+
+ _ghost_qtd = alloc_ehci_qTD(NULL);
+ _ghost_qtd->Token = 0x11197B3F; //QTD_STS_HALT; visit_qtd() will not remove a qTD with this mark. It represents a qhost qTD.
+
+ /*------------------------------------------------------------------------------------*/
+ /* Initialize asynchronous list */
+ /*------------------------------------------------------------------------------------*/
+ qh_remove_list = NULL;
+
+ /* Create the QH list head with H-bit 1 */
+ _H_qh = alloc_ehci_QH();
+ _H_qh->HLink = QH_HLNK_QH(_H_qh); /* circular link to itself, the only one QH */
+ _H_qh->Chrst = QH_RCLM_LIST_HEAD; /* it's the head of reclamation list */
+ _H_qh->Curr_qTD = (uint32_t)_ghost_qtd;
+ _H_qh->OL_Next_qTD = QTD_LIST_END;
+ _H_qh->OL_Alt_Next_qTD = (uint32_t)_ghost_qtd;
+ _H_qh->OL_Token = QTD_STS_HALT;
+ _ehci->UCALAR = (uint32_t)_H_qh;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Initialize periodic list */
+ /*------------------------------------------------------------------------------------*/
+ if (FL_SIZE == 256)
+ _ehci->UCMDR |= (0x2<UCMDR |= (0x1<UCMDR |= (0x0<UPFLBAR = (uint32_t)_PFList;
+
+ /*------------------------------------------------------------------------------------*/
+ /* start run */
+ /*------------------------------------------------------------------------------------*/
+
+ _ehci->UCFGR = 0x1; /* enable port routing to EHCI */
+ _ehci->UIENR = HSUSBH_UIENR_USBIEN_Msk | HSUSBH_UIENR_UERRIEN_Msk | HSUSBH_UIENR_HSERREN_Msk | HSUSBH_UIENR_IAAEN_Msk;
+
+ usbh_delay_ms(1); /* delay 1 ms */
+
+ _ehci->UPSCR[0] = HSUSBH_UPSCR_PP_Msk; /* enable port 1 port power */
+ _ehci->UPSCR[1] = HSUSBH_UPSCR_PP_Msk | HSUSBH_UPSCR_PO_Msk; /* set port 2 owner to OHCI */
+
+ init_periodic_frame_list();
+
+ usbh_delay_ms(10); /* delay 10 ms */
+
+ return 0;
+}
+
+static void ehci_suspend(void)
+{
+ if (_ehci->UPSCR[0] & 0x1)
+ _ehci->UPSCR[0] |= HSUSBH_UPSCR_SUSPEND_Msk;
+}
+
+static void ehci_resume(void)
+{
+ if (_ehci->UPSCR[0] & 0x1)
+ _ehci->UPSCR[0] = (HSUSBH->UPSCR[0] & ~HSUSBH_UPSCR_SUSPEND_Msk) | HSUSBH_UPSCR_FPR_Msk;
+}
+
+static void ehci_shutdown(void)
+{
+ ehci_suspend();
+}
+
+static void move_qh_to_remove_list(QH_T *qh)
+{
+ QH_T *q;
+
+ // USB_debug("move_qh_to_remove_list - 0x%x (0x%x)\n", (int)qh, qh->Chrst);
+
+ /* check if this ED found in ed_remove_list */
+ q = qh_remove_list;
+ while (q)
+ {
+ if (q == qh) /* This QH found in qh_remove_list. */
+ {
+ return; /* Do nothing, return... */
+ }
+ q = q->next;
+ }
+
+ DISABLE_EHCI_IRQ();
+
+ /*------------------------------------------------------------------------------------*/
+ /* Search asynchronous frame list and remove qh if found in list. */
+ /*------------------------------------------------------------------------------------*/
+ q = _H_qh; /* find and remove it from asynchronous list */
+ while (QH_PTR(q->HLink) != _H_qh)
+ {
+ if (QH_PTR(q->HLink) == qh)
+ {
+ /* q's next QH is qh, found... */
+ q->HLink = qh->HLink; /* remove qh from list */
+
+ qh->next = qh_remove_list; /* add qh to qh_remove_list */
+ qh_remove_list = qh;
+ _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA interrupt */
+ ENABLE_EHCI_IRQ();
+ return; /* done */
+ }
+ q = QH_PTR(q->HLink); /* advance to next QH in asynchronous list */
+ }
+
+ /*------------------------------------------------------------------------------------*/
+ /* Search periodic frame list and remove qh if found in list. */
+ /*------------------------------------------------------------------------------------*/
+ q = _Iqh[NUM_IQH-1];
+ while (q->HLink != QH_HLNK_END)
+ {
+ if (QH_PTR(q->HLink) == qh)
+ {
+ /* q's next QH is qh, found... */
+ q->HLink = qh->HLink; /* remove qh from list */
+
+ qh->next = qh_remove_list; /* add qh to qh_remove_list */
+ qh_remove_list = qh;
+ _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA interrupt */
+ ENABLE_EHCI_IRQ();
+ return; /* done */
+ }
+ q = QH_PTR(q->HLink); /* advance to next QH in asynchronous list */
+ }
+ ENABLE_EHCI_IRQ();
+}
+
+static void append_to_qtd_list_of_QH(QH_T *qh, qTD_T *qtd)
+{
+ qTD_T *q;
+
+ if (qh->qtd_list == NULL)
+ {
+ qh->qtd_list = qtd;
+ }
+ else
+ {
+ q = qh->qtd_list;
+ while (q->next != NULL)
+ {
+ q = q->next;
+ }
+ q->next = qtd;
+ }
+}
+
+/*
+ * If ep==NULL, it's a control endpoint QH.
+ */
+static void write_qh(UDEV_T *udev, EP_INFO_T *ep, QH_T *qh)
+{
+ uint32_t chrst, cap;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Write QH DWord 1 - Endpoint Characteristics */
+ /*------------------------------------------------------------------------------------*/
+ if (ep == NULL) /* is control endpoint? */
+ {
+ if (udev->descriptor.bMaxPacketSize0 == 0)
+ {
+ if (udev->speed == SPEED_LOW) /* give a default maximum packet size */
+ udev->descriptor.bMaxPacketSize0 = 8;
+ else
+ udev->descriptor.bMaxPacketSize0 = 64;
+ }
+ chrst = QH_DTC | QH_NAK_RL | (udev->descriptor.bMaxPacketSize0 << 16);
+ if (udev->speed != SPEED_HIGH)
+ chrst |= QH_CTRL_EP_FLAG; /* non-high-speed control endpoint */
+ }
+ else /* not a control endpoint */
+ {
+ chrst = QH_NAK_RL | (ep->wMaxPacketSize << 16);
+ chrst |= ((ep->bEndpointAddress & 0xf) << 8); /* Endpoint Address */
+ }
+
+ if (udev->speed == SPEED_LOW)
+ chrst |= QH_EPS_LOW;
+ else if (udev->speed == SPEED_FULL)
+ chrst |= QH_EPS_FULL;
+ else
+ chrst |= QH_EPS_HIGH;
+
+ chrst |= udev->dev_num;
+
+ qh->Chrst = chrst;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Write QH DWord 2 - Endpoint Capabilities */
+ /*------------------------------------------------------------------------------------*/
+ if (udev->speed == SPEED_HIGH)
+ {
+ cap = 0;
+ }
+ else
+ {
+ /*
+ * Backtrace device tree until the USB 2.0 hub found
+ */
+ HUB_DEV_T *hub;
+ int port_num;
+
+ port_num = udev->port_num;
+ hub = udev->parent;
+
+ while ((hub != NULL) && (hub->iface->udev->speed != SPEED_HIGH))
+ {
+ port_num = hub->iface->udev->port_num;
+ hub = hub->iface->udev->parent;
+ }
+
+ cap = (port_num << QH_HUB_PORT_Pos) |
+ (hub->iface->udev->dev_num << QH_HUB_ADDR_Pos);
+ }
+
+ qh->Cap = cap;
+}
+
+static void write_qtd_bptr(qTD_T *qtd, uint32_t buff_addr, int xfer_len)
+{
+ int i;
+
+ qtd->xfer_len = xfer_len;
+ qtd->Bptr[0] = buff_addr;
+
+ buff_addr = (buff_addr + 0x1000) & ~0xFFF;
+
+ for (i = 1; i < 5; i++)
+ {
+ qtd->Bptr[i] = buff_addr;
+ buff_addr += 0x1000;
+ }
+}
+
+static int ehci_ctrl_xfer(UTR_T *utr)
+{
+ UDEV_T *udev;
+ QH_T *qh;
+ qTD_T *qtd_setup, *qtd_data, *qtd_status;
+ uint32_t token;
+ int is_new_qh = 0;
+
+ udev = utr->udev;
+
+ if (utr->data_len > 0)
+ {
+ if (((uint32_t)utr->buff + utr->data_len) > (((uint32_t)utr->buff & ~0xFFF)+0x5000))
+ return USBH_ERR_BUFF_OVERRUN;
+ }
+
+ /*------------------------------------------------------------------------------------*/
+ /* Allocate and link QH */
+ /*------------------------------------------------------------------------------------*/
+ if (udev->ep0.hw_pipe != NULL)
+ {
+ qh = (QH_T *)udev->ep0.hw_pipe;
+ if (qh->qtd_list)
+ return USBH_ERR_EHCI_QH_BUSY;
+ }
+ else
+ {
+ qh = alloc_ehci_QH();
+ if (qh == NULL)
+ return USBH_ERR_MEMORY_OUT;
+
+ udev->ep0.hw_pipe = (void *)qh; /* driver can find QH from EP */
+ is_new_qh = 1;
+ }
+ write_qh(udev, NULL, qh);
+ utr->ep = &udev->ep0; /* driver can find EP from UTR */
+
+ /*------------------------------------------------------------------------------------*/
+ /* Allocate qTDs */
+ /*------------------------------------------------------------------------------------*/
+ qtd_setup = alloc_ehci_qTD(utr); /* allocate qTD for SETUP */
+
+ if (utr->data_len > 0)
+ qtd_data = alloc_ehci_qTD(utr); /* allocate qTD for DATA */
+ else
+ qtd_data = NULL;
+
+ qtd_status = alloc_ehci_qTD(utr); /* allocate qTD for USTSR */
+
+ if (qtd_status == NULL) /* out of memory? */
+ {
+ if (qtd_setup)
+ free_ehci_qTD(qtd_setup); /* free memory */
+ if (qtd_data)
+ free_ehci_qTD(qtd_data); /* free memory */
+ return USBH_ERR_MEMORY_OUT; /* out of memory */
+ }
+
+ // USB_debug("qh=0x%x, qtd_setup=0x%x, qtd_data=0x%x, qtd_status=0x%x\n", (int)qh, (int)qtd_setup, (int)qtd_data, (int)qtd_status);
+
+ /*------------------------------------------------------------------------------------*/
+ /* prepare SETUP stage qTD */
+ /*------------------------------------------------------------------------------------*/
+ qtd_setup->qh = qh;
+ //qtd_setup->utr = utr;
+ write_qtd_bptr(qtd_setup, (uint32_t)&utr->setup, 8);
+ append_to_qtd_list_of_QH(qh, qtd_setup);
+ qtd_setup->Token = (8 << 16) | QTD_ERR_COUNTER | QTD_PID_SETUP | QTD_STS_ACTIVE;
+
+ /*------------------------------------------------------------------------------------*/
+ /* prepare DATA stage qTD */
+ /*------------------------------------------------------------------------------------*/
+ if (utr->data_len > 0)
+ {
+ qtd_setup->Next_qTD = (uint32_t)qtd_data;
+ qtd_data->Next_qTD = (uint32_t)qtd_status;
+
+ if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT)
+ token = QTD_ERR_COUNTER | QTD_PID_OUT | QTD_STS_ACTIVE;
+ else
+ token = QTD_ERR_COUNTER | QTD_PID_IN | QTD_STS_ACTIVE;
+
+ qtd_data->qh = qh;
+ //qtd_data->utr = utr;
+ write_qtd_bptr(qtd_data, (uint32_t)utr->buff, utr->data_len);
+ append_to_qtd_list_of_QH(qh, qtd_data);
+ qtd_data->Token = QTD_DT | (utr->data_len << 16) | token;
+ }
+ else
+ {
+ qtd_setup->Next_qTD = (uint32_t)qtd_status;
+ }
+
+ /*------------------------------------------------------------------------------------*/
+ /* prepare USTSR stage qTD */
+ /*------------------------------------------------------------------------------------*/
+ qtd_status->Next_qTD = (uint32_t)_ghost_qtd;
+ qtd_status->Alt_Next_qTD = QTD_LIST_END;
+
+ if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT)
+ token = QTD_ERR_COUNTER | QTD_PID_IN | QTD_STS_ACTIVE;
+ else
+ token = QTD_ERR_COUNTER | QTD_PID_OUT | QTD_STS_ACTIVE;
+
+ qtd_status->qh = qh;
+ //qtd_status->utr = utr;
+ append_to_qtd_list_of_QH(qh, qtd_status);
+ qtd_status->Token = QTD_DT | QTD_IOC | token;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Update QH overlay */
+ /*------------------------------------------------------------------------------------*/
+ qh->Curr_qTD = 0;
+ qh->OL_Next_qTD = (uint32_t)qtd_setup;
+ qh->OL_Alt_Next_qTD = QTD_LIST_END;
+ qh->OL_Token = 0;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Link QH and start asynchronous transfer */
+ /*------------------------------------------------------------------------------------*/
+ if (is_new_qh)
+ {
+ qh->HLink = _H_qh->HLink;
+ _H_qh->HLink = QH_HLNK_QH(qh);
+ }
+
+ /* Start transfer */
+ _ehci->UCMDR |= HSUSBH_UCMDR_ASEN_Msk; /* start asynchronous transfer */
+ return 0;
+}
+
+static int ehci_bulk_xfer(UTR_T *utr)
+{
+ UDEV_T *udev;
+ EP_INFO_T *ep = utr->ep;
+ QH_T *qh;
+ qTD_T *qtd, *qtd_pre;
+ uint32_t data_len, xfer_len;
+ uint8_t *buff;
+ uint32_t token;
+ int is_new_qh = 0;
+
+ //USB_debug("Bulk XFER =>\n");
+ // dump_ehci_asynclist_simple();
+
+ udev = utr->udev;
+
+ if (ep->hw_pipe != NULL)
+ {
+ qh = (QH_T *)ep->hw_pipe ;
+ if (qh->qtd_list)
+ {
+ return USBH_ERR_EHCI_QH_BUSY;
+ }
+ }
+ else
+ {
+ qh = alloc_ehci_QH();
+ if (qh == NULL)
+ return USBH_ERR_MEMORY_OUT;
+ is_new_qh = 1;
+ write_qh(udev, ep, qh);
+ ep->hw_pipe = (void *)qh; /* associate QH with endpoint */
+ }
+
+ /*------------------------------------------------------------------------------------*/
+ /* Prepare qTDs */
+ /*------------------------------------------------------------------------------------*/
+ data_len = utr->data_len;
+ buff = utr->buff;
+ qtd_pre = NULL;
+
+ while (data_len > 0)
+ {
+ qtd = alloc_ehci_qTD(utr);
+ if (qtd == NULL) /* failed to allocate a qTD */
+ {
+ qtd = qh->qtd_list;
+ while (qtd != NULL)
+ {
+ qtd_pre = qtd;
+ qtd = qtd->next;
+ free_ehci_qTD(qtd_pre);
+ }
+ if (is_new_qh)
+ {
+ free_ehci_QH(qh);
+ ep->hw_pipe = NULL;
+ }
+ return USBH_ERR_MEMORY_OUT;
+ }
+
+ if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT)
+ token = QTD_ERR_COUNTER | QTD_PID_OUT | QTD_STS_ACTIVE;
+ else
+ token = QTD_ERR_COUNTER | QTD_PID_IN | QTD_STS_ACTIVE;
+
+ if (data_len > 0x4000) /* force maximum x'fer length 16K per qTD */
+ xfer_len = 0x4000;
+ else
+ xfer_len = data_len; /* remaining data length < 4K */
+
+ qtd->qh = qh;
+ qtd->Next_qTD = (uint32_t)_ghost_qtd;
+ qtd->Alt_Next_qTD = QTD_LIST_END; //(uint32_t)_ghost_qtd;
+ write_qtd_bptr(qtd, (uint32_t)buff, xfer_len);
+ append_to_qtd_list_of_QH(qh, qtd);
+ qtd->Token = (xfer_len << 16) | token;
+
+ buff += xfer_len; /* advanced buffer pointer */
+ data_len -= xfer_len;
+
+ if (data_len == 0) /* is this the latest qTD? */
+ {
+ qtd->Token |= QTD_IOC; /* ask to raise an interrupt on the last qTD */
+ qtd->Next_qTD = (uint32_t)_ghost_qtd; /* qTD list end */
+ }
+
+ if (qtd_pre != NULL)
+ qtd_pre->Next_qTD = (uint32_t)qtd;
+ qtd_pre = qtd;
+ }
+
+ //USB_debug("utr=0x%x, qh=0x%x, qtd=0x%x\n", (int)utr, (int)qh, (int)qh->qtd_list);
+
+ qtd = qh->qtd_list;
+
+// qh->Curr_qTD = 0; //(uint32_t)qtd;
+ qh->OL_Next_qTD = (uint32_t)qtd;
+// qh->OL_Alt_Next_qTD = QTD_LIST_END;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Link QH and start asynchronous transfer */
+ /*------------------------------------------------------------------------------------*/
+ if (is_new_qh)
+ {
+ memcpy(&(qh->OL_Bptr[0]), &(qtd->Bptr[0]), 20);
+ qh->Curr_qTD = (uint32_t)qtd;
+
+ qh->OL_Token = 0; //qtd->Token;
+
+ if (utr->ep->bToggle)
+ qh->OL_Token |= QTD_DT;
+
+ qh->HLink = _H_qh->HLink;
+ _H_qh->HLink = QH_HLNK_QH(qh);
+ }
+
+ /* Start transfer */
+ _ehci->UCMDR |= HSUSBH_UCMDR_ASEN_Msk; /* start asynchronous transfer */
+
+ return 0;
+}
+
+static int ehci_int_xfer(UTR_T *utr)
+{
+ UDEV_T *udev = utr->udev;
+ EP_INFO_T *ep = utr->ep;
+ QH_T *qh, *iqh;
+ qTD_T *qtd, *dummy_qtd;
+ uint32_t token;
+
+ dummy_qtd = alloc_ehci_qTD(NULL); /* allocate a new dummy qTD */
+ if (dummy_qtd == NULL)
+ return USBH_ERR_MEMORY_OUT;
+ dummy_qtd->Token &= ~(QTD_STS_ACTIVE | QTD_STS_HALT);
+
+ if (ep->hw_pipe != NULL)
+ {
+ qh = (QH_T *)ep->hw_pipe ;
+ }
+ else
+ {
+ qh = alloc_ehci_QH();
+ if (qh == NULL)
+ {
+ free_ehci_qTD(dummy_qtd);
+ return USBH_ERR_MEMORY_OUT;
+ }
+ write_qh(udev, ep, qh);
+ qh->Chrst &= ~0xF0000000;
+
+ if (udev->speed == SPEED_HIGH)
+ {
+ qh->Cap = (0x1 << QH_MULT_Pos) | (qh->Cap & 0xff) | make_int_s_mask(ep->bInterval);
+ }
+ else
+ {
+ qh->Cap = (0x1 << QH_MULT_Pos) | (qh->Cap & ~(QH_C_MASK_Msk | QH_S_MASK_Msk)) | 0x7802;
+ }
+ ep->hw_pipe = (void *)qh; /* associate QH with endpoint */
+
+ /*
+ * Allocate another dummy qTD
+ */
+ qtd = alloc_ehci_qTD(NULL); /* allocate a new dummy qTD */
+ if (qtd == NULL)
+ {
+ free_ehci_qTD(dummy_qtd);
+ free_ehci_QH(qh);
+ return USBH_ERR_MEMORY_OUT;
+ }
+ qtd->Token &= ~(QTD_STS_ACTIVE | QTD_STS_HALT);
+
+ qh->dummy = dummy_qtd;
+ qh->OL_Next_qTD = (uint32_t)dummy_qtd;
+ qh->OL_Token = 0; /* !Active & !Halted */
+
+ /*
+ * link QH
+ */
+ if (udev->speed == SPEED_HIGH) /* get head node of this interval */
+ iqh = get_int_tree_head_node(ep->bInterval);
+ else
+ iqh = get_int_tree_head_node(ep->bInterval * 8);
+ qh->HLink = iqh->HLink; /* Add to list of the same interval */
+ iqh->HLink = QH_HLNK_QH(qh);
+
+ dummy_qtd = qtd;
+ }
+
+ qtd = qh->dummy; /* use the current dummy qTD */
+ qtd->Next_qTD = (uint32_t)dummy_qtd;
+ qtd->utr = utr;
+ qh->dummy = dummy_qtd; /* give the new dummy qTD */
+
+ /*------------------------------------------------------------------------------------*/
+ /* Prepare qTD */
+ /*------------------------------------------------------------------------------------*/
+
+ if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT)
+ token = QTD_ERR_COUNTER | QTD_PID_OUT;
+ else
+ token = QTD_ERR_COUNTER | QTD_PID_IN;
+
+ qtd->qh = qh;
+ qtd->Alt_Next_qTD = QTD_LIST_END;
+ write_qtd_bptr(qtd, (uint32_t)utr->buff, utr->data_len);
+ append_to_qtd_list_of_QH(qh, qtd);
+ qtd->Token = QTD_IOC | (utr->data_len << 16) | token | QTD_STS_ACTIVE;
+
+ // printf("ehci_int_xfer - qh: 0x%x, 0x%x, 0x%x\n", (int)qh, (int)qh->Chrst, (int)qh->Cap);
+
+ _ehci->UCMDR |= HSUSBH_UCMDR_PSEN_Msk; /* periodic list enable */
+ return 0;
+}
+
+/*
+ * Quit current trasnfer via UTR or hardware EP.
+ */
+static int ehci_quit_xfer(UTR_T *utr, EP_INFO_T *ep)
+{
+ QH_T *qh;
+
+ // USB_debug("ehci_quit_xfer - utr: 0x%x, ep: 0x%x\n", (int)utr, (int)ep);
+
+ DISABLE_EHCI_IRQ();
+ if (ehci_quit_iso_xfer(utr, ep) == 0)
+ {
+ ENABLE_EHCI_IRQ();
+ return 0;
+ }
+ ENABLE_EHCI_IRQ();
+
+ if (utr != NULL)
+ {
+ if (utr->ep == NULL)
+ return USBH_ERR_NOT_FOUND;
+
+ qh = (QH_T *)(utr->ep->hw_pipe);
+
+ if (!qh)
+ return USBH_ERR_NOT_FOUND;
+
+ /* add the QH to remove list, it will be removed on the next IAAD interrupt */
+ move_qh_to_remove_list(qh);
+ utr->ep->hw_pipe = NULL;
+ }
+
+ if ((ep != NULL) && (ep->hw_pipe != NULL))
+ {
+ qh = (QH_T *)(ep->hw_pipe);
+ /* add the QH to remove list, it will be removed on the next IAAD interrupt */
+ move_qh_to_remove_list(qh);
+ ep->hw_pipe = NULL;
+ }
+ usbh_delay_ms(2);
+
+ return 0;
+}
+
+static int visit_qtd(qTD_T *qtd)
+{
+ if ((qtd->Token == 0x11197B3F) || (qtd->Token == 0x1197B3F))
+ return 0; /* A Dummy qTD or qTD on writing, don't touch it. */
+
+ // USB_debug("Visit qtd 0x%x - 0x%x\n", (int)qtd, qtd->Token);
+
+ if ((qtd->Token & QTD_STS_ACTIVE) == 0)
+ {
+ if (qtd->Token & (QTD_STS_HALT | QTD_STS_DATA_BUFF_ERR | QTD_STS_BABBLE | QTD_STS_XactErr | QTD_STS_MISS_MF))
+ {
+ USB_error("qTD error token=0x%x! 0x%x\n", qtd->Token, qtd->Bptr[0]);
+ if (qtd->utr->status == 0)
+ qtd->utr->status = USBH_ERR_TRANSACTION;
+ }
+ else
+ {
+ if ((qtd->Token & QTD_PID_Msk) != QTD_PID_SETUP)
+ {
+ qtd->utr->xfer_len += qtd->xfer_len - QTD_TODO_LEN(qtd->Token);
+ // USB_debug("0x%x utr->xfer_len += %d\n", qtd->Token, qtd->xfer_len - QTD_TODO_LEN(qtd->Token));
+ }
+ }
+ return 1;
+ }
+ return 0;
+}
+
+static void scan_asynchronous_list()
+{
+ QH_T *qh, *qh_tmp;
+ qTD_T *q_pre=NULL, *qtd, *qtd_tmp;
+ UTR_T *utr;
+
+ qh = QH_PTR(_H_qh->HLink);
+ while (qh != _H_qh)
+ {
+ // USB_debug("Scan qh=0x%x, 0x%x\n", (int)qh, qh->OL_Token);
+
+ utr = NULL;
+ qtd = qh->qtd_list;
+ while (qtd != NULL)
+ {
+ if (visit_qtd(qtd)) /* if TRUE, reclaim this qtd */
+ {
+ /* qTD is completed, will remove it */
+ utr = qtd->utr;
+ if (qtd == qh->qtd_list)
+ qh->qtd_list = qtd->next; /* unlink the qTD from qtd_list */
+ else
+ q_pre->next = qtd->next; /* unlink the qTD from qtd_list */
+
+ qtd_tmp = qtd; /* remember this qTD for freeing later */
+ qtd = qtd->next; /* advance to the next qTD */
+
+ qtd_tmp->next = qh->done_list; /* push this qTD to QH's done list */
+ qh->done_list = qtd_tmp;
+ }
+ else
+ {
+ q_pre = qtd; /* remember this qTD as a preceder */
+ qtd = qtd->next; /* advance to next qTD */
+ }
+ }
+
+ qh_tmp = qh;
+ qh = QH_PTR(qh->HLink); /* advance to the next QH */
+
+ /* If all TDs are done, call-back to requester and then remove this QH. */
+ if ((qh_tmp->qtd_list == NULL) && utr)
+ {
+ // printf("T %d [%d]\n", (qh_tmp->Chrst>>8)&0xf, (qh_tmp->OL_Token&QTD_DT) ? 1 : 0);
+ if (qh_tmp->OL_Token & QTD_DT)
+ utr->ep->bToggle = 1;
+ else
+ utr->ep->bToggle = 0;
+
+ utr->bIsTransferDone = 1;
+ if (utr->func)
+ utr->func(utr);
+
+ _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA to reclaim done_list */
+ }
+ }
+}
+
+static void scan_periodic_frame_list()
+{
+ QH_T *qh;
+ qTD_T *qtd, *qNext;
+ UTR_T *utr;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Scan interrupt frame list */
+ /*------------------------------------------------------------------------------------*/
+ qh = _Iqh[NUM_IQH-1];
+ while (qh != NULL)
+ {
+ qtd = qh->qtd_list;
+
+ if (qtd == NULL)
+ {
+ /* empty QH */
+ qh = QH_PTR(qh->HLink); /* advance to the next QH */
+ continue;
+ }
+
+ while (qtd != NULL)
+ {
+ qNext = qtd->next;
+
+ if (visit_qtd(qtd)) /* if TRUE, reclaim this qtd */
+ {
+ qh->qtd_list = qtd->next; /* proceed to next qTD or NULL */
+ qtd->next = qh->done_list; /* push qTD into the done list */
+ qh->done_list = qtd; /* move qTD to done list */
+ }
+ qtd = qNext;
+ }
+
+ qtd = qh->done_list;
+
+ while (qtd != NULL)
+ {
+ utr = qtd->utr;
+
+ if (qh->OL_Token & QTD_DT)
+ utr->ep->bToggle = 1;
+ else
+ utr->ep->bToggle = 0;
+
+ utr->bIsTransferDone = 1;
+ if (utr->func)
+ utr->func(utr);
+
+ _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA to reclaim done_list */
+
+ qtd = qtd->next;
+ }
+
+ qh = QH_PTR(qh->HLink); /* advance to the next QH */
+ }
+
+ /*------------------------------------------------------------------------------------*/
+ /* Scan isochronous frame list */
+ /*------------------------------------------------------------------------------------*/
+
+ scan_isochronous_list();
+}
+
+void iaad_remove_qh()
+{
+ QH_T *qh;
+ qTD_T *qtd;
+ UTR_T *utr;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Remove all QHs in qh_remove_list... */
+ /*------------------------------------------------------------------------------------*/
+ while (qh_remove_list != NULL)
+ {
+ qh = qh_remove_list;
+ qh_remove_list = qh->next;
+
+ // USB_debug("iaad_remove_qh - remove QH 0x%x\n", (int)qh);
+
+ while (qh->done_list) /* we can free the qTDs now */
+ {
+ qtd = qh->done_list;
+ qh->done_list = qtd->next;
+ free_ehci_qTD(qtd);
+ }
+
+ if (qh->qtd_list != NULL) /* still have incomplete qTDs? */
+ {
+ utr = qh->qtd_list->utr;
+ while (qh->qtd_list)
+ {
+ qtd = qh->qtd_list;
+ qh->qtd_list = qtd->next;
+ free_ehci_qTD(qtd);
+ }
+ utr->status = USBH_ERR_ABORT;
+ utr->bIsTransferDone = 1;
+ if (utr->func)
+ utr->func(utr); /* call back */
+ }
+ free_ehci_QH(qh); /* free the QH */
+ }
+
+ /*------------------------------------------------------------------------------------*/
+ /* Free all qTD in done_list of each asynchronous QH */
+ /*------------------------------------------------------------------------------------*/
+ qh = QH_PTR(_H_qh->HLink);
+ while (qh != _H_qh)
+ {
+ while (qh->done_list) /* we can free the qTDs now */
+ {
+ qtd = qh->done_list;
+ qh->done_list = qtd->next;
+ free_ehci_qTD(qtd);
+ }
+ qh = QH_PTR(qh->HLink); /* advance to the next QH */
+ }
+
+ /*------------------------------------------------------------------------------------*/
+ /* Free all qTD in done_list of each QH of periodic frame list */
+ /*------------------------------------------------------------------------------------*/
+ qh = _Iqh[NUM_IQH-1];
+ while (qh != NULL)
+ {
+ while (qh->done_list) /* we can free the qTDs now */
+ {
+ qtd = qh->done_list;
+ qh->done_list = qtd->next;
+ free_ehci_qTD(qtd);
+ }
+ qh = QH_PTR(qh->HLink); /* advance to the next QH */
+ }
+}
+
+//static irqreturn_t ehci_irq (struct usb_hcd *hcd)
+void EHCI_IRQHandler(void)
+{
+ uint32_t intsts;
+
+ intsts = _ehci->USTSR;
+ _ehci->USTSR = intsts; /* clear interrupt status */
+
+ // USB_debug("Eirq USTSR=0x%x\n", intsts);
+
+ if (intsts & HSUSBH_USTSR_UERRINT_Msk)
+ {
+ // USB_error("Transfer error!\n");
+ }
+
+ if (intsts & HSUSBH_USTSR_USBINT_Msk)
+ {
+ /* some transfers completed, travel asynchronous */
+ /* and periodic lists to find and reclaim them. */
+ scan_asynchronous_list();
+
+ scan_periodic_frame_list();
+ }
+
+ if (intsts & HSUSBH_USTSR_IAA_Msk)
+ {
+ iaad_remove_qh();
+ }
+}
+
+static UDEV_T * ehci_find_device_by_port(int port)
+{
+ UDEV_T *udev;
+
+ udev = g_udev_list;
+ while (udev != NULL)
+ {
+ if ((udev->parent == NULL) && (udev->port_num == port) && (udev->speed == SPEED_HIGH))
+ return udev;
+ udev = udev->next;
+ }
+ return NULL;
+}
+
+static int ehci_rh_port_reset(int port)
+{
+ int retry;
+ int reset_time;
+ uint32_t t0;
+
+ reset_time = usbh_tick_from_millisecond(PORT_RESET_TIME_MS);
+
+ for (retry = 0; retry < PORT_RESET_RETRY; retry++)
+ {
+ _ehci->UPSCR[port] = (_ehci->UPSCR[port] | HSUSBH_UPSCR_PRST_Msk) & ~HSUSBH_UPSCR_PE_Msk;
+
+ t0 = usbh_get_ticks();
+ while (usbh_get_ticks() - t0 < (reset_time)+1) ; /* wait at least 50 ms */
+
+ _ehci->UPSCR[port] &= ~HSUSBH_UPSCR_PRST_Msk;
+
+ t0 = usbh_get_ticks();
+ while (usbh_get_ticks() - t0 < (reset_time)+1)
+ {
+ if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) ||
+ ((_ehci->UPSCR[port] & (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)) == (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)))
+ goto port_reset_done;
+ }
+ reset_time += PORT_RESET_RETRY_INC_MS;
+ }
+
+ USB_debug("EHCI port %d - port reset failed!\n", port+1);
+ return USBH_ERR_PORT_RESET;
+
+port_reset_done:
+ if ((_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) == 0) /* check again if device disconnected */
+ {
+ _ehci->UPSCR[port] |= HSUSBH_UPSCR_CSC_Msk; /* clear CSC */
+ return USBH_ERR_DISCONNECTED;
+ }
+ _ehci->UPSCR[port] |= HSUSBH_UPSCR_PEC_Msk; /* clear port enable change status */
+ return USBH_OK; /* port reset success */
+}
+
+static int ehci_rh_polling(void)
+{
+ UDEV_T *udev;
+ int ret;
+ int connect_status, t0, debounce_tick;
+
+ if (!(_ehci->UPSCR[0] & HSUSBH_UPSCR_CSC_Msk))
+ return 0;
+
+ /*------------------------------------------------------------------------------------*/
+ /* connect status change */
+ /*------------------------------------------------------------------------------------*/
+
+ USB_debug("EHCI port1 status change: 0x%x\n", _ehci->UPSCR[0]);
+
+ /*--------------------------------------------------------------------------------*/
+ /* Disconnect the devices attached to this port. */
+ /*--------------------------------------------------------------------------------*/
+ while (1)
+ {
+ udev = ehci_find_device_by_port(1);
+ if (udev == NULL)
+ break;
+ usbh_disconnect_device(udev);
+ }
+
+ /*--------------------------------------------------------------------------------*/
+ /* Port de-bounce */
+ /*--------------------------------------------------------------------------------*/
+ t0 = usbh_get_ticks();
+ debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME);
+ connect_status = _ehci->UPSCR[0] & HSUSBH_UPSCR_CCS_Msk;
+ while (usbh_get_ticks() - t0 < debounce_tick)
+ {
+ if (connect_status != (_ehci->UPSCR[0] & HSUSBH_UPSCR_CCS_Msk))
+ {
+ /* reset stable time counting */
+ t0 = usbh_get_ticks();
+ connect_status = _ehci->UPSCR[0] & HSUSBH_UPSCR_CCS_Msk;
+ }
+ }
+
+ _ehci->UPSCR[0] |= HSUSBH_UPSCR_CSC_Msk; /* clear connect status change bit */
+
+ if (connect_status == HSUSBH_UPSCR_CCS_Msk)
+ {
+ /*--------------------------------------------------------------------------------*/
+ /* A new device connected. */
+ /*--------------------------------------------------------------------------------*/
+ if (ehci_rh_port_reset(0) != USBH_OK)
+ {
+ /* port reset failed, maybe an USB 1.1 device */
+ _ehci->UPSCR[0] |= HSUSBH_UPSCR_PO_Msk; /* change port owner to OHCI */
+ _ehci->UPSCR[0] |= HSUSBH_UPSCR_CSC_Msk; /* clear all status change bits */
+ return 0;
+ }
+
+ /*
+ * Port reset success. Start to enumerate this new device.
+ */
+ udev = alloc_device();
+ if (udev == NULL)
+ return 0; /* out-of-memory, do nothing... */
+
+ udev->parent = NULL;
+ udev->port_num = 1;
+ udev->speed = SPEED_HIGH;
+ udev->hc_driver = &ehci_driver;
+
+ ret = usbh_connect_device(udev);
+ if (ret < 0)
+ {
+ USB_error("connect_device error! [%d]\n", ret);
+ free_device(udev);
+ }
+ }
+ else
+ {
+ /*
+ * Device disconnected
+ */
+ while (1)
+ {
+ udev = ehci_find_device_by_port(1);
+ if (udev == NULL)
+ break;
+ usbh_disconnect_device(udev);
+ }
+ }
+ return 1;
+}
+
+
+HC_DRV_T ehci_driver =
+{
+ ehci_init, /* init */
+ ehci_shutdown, /* shutdown */
+ ehci_suspend, /* suspend */
+ ehci_resume, /* resume */
+ ehci_ctrl_xfer, /* ctrl_xfer */
+ ehci_bulk_xfer, /* bulk_xfer */
+ ehci_int_xfer, /* int_xfer */
+ ehci_iso_xfer, /* iso_xfer */
+ ehci_quit_xfer, /* quit_xfer */
+ ehci_rh_port_reset, /* rthub_port_reset */
+ ehci_rh_polling /* rthub_polling */
+};
+
+
+/// @endcond HIDDEN_SYMBOLS
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci_iso.c b/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci_iso.c
new file mode 100644
index 00000000000..58cbc6fb03c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci_iso.c
@@ -0,0 +1,916 @@
+/**************************************************************************//**
+ * @file ehci_iso.c
+ * @version V1.10
+ * @brief USB EHCI isochronous transfer driver.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include
+#include
+
+#include "NuMicro.h"
+
+#include "usb.h"
+#include "hub.h"
+
+
+/// @cond HIDDEN_SYMBOLS
+
+uint32_t g_flr_cnt; /* frame list rollover counter */
+
+ISO_EP_T *iso_ep_list; /* list of activated isochronous pipes */
+
+extern uint32_t _PFList[FL_SIZE]; /* Periodic frame list */
+
+static const uint16_t sitd_OUT_Smask [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
+
+static int ehci_iso_split_xfer(UTR_T *utr, ISO_EP_T *iso_ep);
+
+/*
+ * Inspect the iTD can be reclaimed or not. If yes, collect the transaction results.
+ * Return: 1 - reclaimed
+ * 0 - not completed
+ */
+static int review_itd(iTD_T *itd)
+{
+ UTR_T *utr;
+ uint32_t frnidx = itd->sched_frnidx;
+ uint32_t now_frame = (_ehci->UFINDR >> 3) & 0x3FF;
+ int i, fidx;
+
+ // printf("R - %d %d, 0x%x\n", now_frame, frnidx, itd->Transaction[0]);
+
+ if (now_frame == frnidx)
+ {
+ for (i = 0; i < 8; i++)
+ {
+ if (itd->Transaction[i] & ITD_STATUS_ACTIVE)
+ return 0; /* have any not completed frames */
+ }
+ }
+ else if (now_frame > frnidx)
+ {
+ if ((now_frame - frnidx) > EHCI_ISO_RCLM_RANGE)
+ return 0; /* don't touch it */
+ }
+ else
+ {
+ if (now_frame + FL_SIZE - frnidx > EHCI_ISO_RCLM_RANGE)
+ return 0; /* don't touch it */
+ }
+
+ /*
+ * Reclaim this iTD
+ */
+ utr = itd->utr;
+ fidx = itd->fidx;
+ for (i = 0; i < 8; i++)
+ {
+ if (!(itd->trans_mask & (0x1<Transaction[i]))
+ {
+ if (itd->Transaction[i] & ITD_STATUS_ACTIVE)
+ {
+ utr->iso_status[fidx] = USBH_ERR_NOT_ACCESS0;
+ utr->status = USBH_ERR_NOT_ACCESS0;
+ }
+ else if (itd->Transaction[i] & ITD_STATUS_BABBLE)
+ {
+ utr->iso_status[fidx] = USBH_ERR_BABBLE_DETECTED;
+ utr->status = USBH_ERR_TRANSFER;
+ }
+ else if (itd->Transaction[i] & ITD_STATUS_BUFF_ERR)
+ {
+ utr->iso_status[fidx] = USBH_ERR_DATA_BUFF;
+ utr->status = USBH_ERR_TRANSFER;
+ }
+ else
+ {
+ utr->iso_status[fidx] = USBH_ERR_TRANSACTION;
+ utr->status = USBH_ERR_TRANSFER;
+ }
+ }
+ else
+ {
+ utr->iso_status[fidx] = 0;
+ utr->iso_xlen[fidx] = ITD_XFER_LEN(itd->Transaction[i]);
+ }
+ fidx++;
+ }
+ utr->td_cnt--;
+
+ if (utr->td_cnt == 0) /* All iTD of this UTR done */
+ {
+ utr->bIsTransferDone = 1;
+ if (utr->func)
+ utr->func(utr);
+ }
+
+ return 1; /* to be reclaimed */
+}
+
+/*
+ * Inspect the siTD can be reclaimed or not. If yes, collect the transaction results.
+ * Return: 1 - reclaimed
+ * 0 - not completed
+ */
+static int review_sitd(siTD_T *sitd)
+{
+ UTR_T *utr;
+ uint32_t frnidx = sitd->sched_frnidx;
+ uint32_t now_frame = (_ehci->UFINDR >> 3) & 0x3FF;
+ int fidx;
+ uint32_t TotalBytesToTransfer;
+
+ if (now_frame == frnidx)
+ {
+ if (SITD_STATUS(sitd->StsCtrl) == SITD_STATUS_ACTIVE)
+ return 0;
+ }
+ else if (now_frame > frnidx)
+ {
+ if ((now_frame - frnidx) > EHCI_ISO_RCLM_RANGE)
+ return 0; /* don't touch it */
+ }
+ else
+ {
+ if (now_frame + FL_SIZE - frnidx > EHCI_ISO_RCLM_RANGE)
+ return 0; /* don't touch it */
+ }
+
+ /*
+ * Reclaim this siTD
+ */
+ utr = sitd->utr;
+ fidx = sitd->fidx;
+
+ if (SITD_STATUS(sitd->StsCtrl))
+ {
+ if (sitd->StsCtrl & SITD_STATUS_ACTIVE)
+ {
+ utr->iso_status[fidx] = USBH_ERR_NOT_ACCESS0;
+ }
+ else if (sitd->StsCtrl & SITD_BABBLE_DETECTED)
+ {
+ utr->iso_status[fidx] = USBH_ERR_BABBLE_DETECTED;
+ utr->status = USBH_ERR_TRANSFER;
+ }
+ else if (sitd->StsCtrl & SITD_STATUS_BUFF_ERR)
+ {
+ utr->iso_status[fidx] = USBH_ERR_DATA_BUFF;
+ utr->status = USBH_ERR_TRANSFER;
+ }
+ else
+ {
+ utr->iso_status[fidx] = USBH_ERR_TRANSACTION;
+ utr->status = USBH_ERR_TRANSFER;
+ }
+ }
+ else
+ {
+ TotalBytesToTransfer = (sitd->StsCtrl & SITD_XFER_CNT_Msk) >> SITD_XFER_CNT_Pos;
+ utr->iso_xlen[fidx] = utr->iso_xlen[fidx] - TotalBytesToTransfer;
+ utr->iso_status[fidx] = 0;
+ }
+ utr->td_cnt--;
+
+ if (utr->td_cnt == 0) /* All iTD of this UTR done */
+ {
+ utr->bIsTransferDone = 1;
+ if (utr->func)
+ utr->func(utr);
+ }
+ return 1; /* to be reclaimed */
+}
+
+/*
+ * Some iTD/siTD may be scheduled but not serviced due to time missed.
+ * This function scan several earlier frames and drop unserviced iTD/siTD if found.
+ */
+void scan_isochronous_list(void)
+{
+ ISO_EP_T *iso_ep = iso_ep_list;
+ iTD_T *itd, *itd_pre, *p;
+ siTD_T *sitd, *sitd_pre, *sp;
+ uint32_t frnidx;
+
+ DISABLE_EHCI_IRQ();
+
+ while (iso_ep != NULL) /* Search all activated iso endpoints */
+ {
+ /*--------------------------------------------------------------------------------*/
+ /* Scan all iTDs */
+ /*--------------------------------------------------------------------------------*/
+ itd = iso_ep->itd_list; /* get the first iTD from iso_ep's iTD list */
+ itd_pre = NULL;
+ while (itd != NULL) /* traverse all iTDs of itd list */
+ {
+ if (review_itd(itd)) /* inspect and reclaim iTD */
+ {
+ /*------------------------------------------------------------------------*/
+ /* Remove this iTD from period frame list */
+ /*------------------------------------------------------------------------*/
+ frnidx = itd->sched_frnidx;
+ if (_PFList[frnidx] == ITD_HLNK_ITD(itd))
+ {
+ /* is the first entry, just change to next */
+ _PFList[frnidx] = itd->Next_Link;
+ }
+ else
+ {
+ p = ITD_PTR(_PFList[frnidx]); /* find the preceding iTD */
+ while ((ITD_PTR(p->Next_Link) != itd) && (p != NULL))
+ {
+ p = ITD_PTR(p->Next_Link);
+ }
+
+ if (p == NULL) /* link list out of control! */
+ {
+ USB_error("An iTD lost refernece to periodic frame list! 0x%x -> %d\n", (int)itd, frnidx);
+ }
+ else /* remove iTD from list */
+ {
+ p->Next_Link = itd->Next_Link;
+ }
+ }
+
+ /*------------------------------------------------------------------------*/
+ /* Remove this iTD from iso_ep's iTD list */
+ /*------------------------------------------------------------------------*/
+ if (itd_pre == NULL)
+ {
+ iso_ep->itd_list = itd->next;
+ }
+ else
+ {
+ itd_pre->next = itd->next;
+ }
+ p = itd->next;
+ free_ehci_iTD(itd);
+ itd = p;
+ }
+ else
+ {
+ itd_pre = itd;
+ itd = itd->next; /* traverse to the next iTD of iTD list */
+ }
+ }
+
+ /*--------------------------------------------------------------------------------*/
+ /* Scan all siTDs */
+ /*--------------------------------------------------------------------------------*/
+ sitd = iso_ep->sitd_list; /* get the first siTD from iso_ep's siTD list */
+ sitd_pre = NULL;
+ while (sitd != NULL) /* traverse all siTDs of sitd list */
+ {
+ if (review_sitd(sitd)) /* inspect and reclaim siTD */
+ {
+ /*------------------------------------------------------------------------*/
+ /* Remove this siTD from period frame list */
+ /*------------------------------------------------------------------------*/
+ frnidx = sitd->sched_frnidx;
+ if (_PFList[frnidx] == SITD_HLNK_SITD(sitd))
+ {
+ /* is the first entry, just change to next */
+ _PFList[frnidx] = sitd->Next_Link;
+ }
+ else
+ {
+ sp = SITD_PTR(_PFList[frnidx]); /* find the preceding siTD */
+ while ((SITD_PTR(sp->Next_Link) != sitd) && (sp != NULL))
+ {
+ sp = SITD_PTR(sp->Next_Link);
+ }
+
+ if (sp == NULL) /* link list out of control! */
+ {
+ USB_error("An siTD lost reference to periodic frame list! 0x%x -> %d\n", (int)sitd, frnidx);
+ }
+ else /* remove iTD from list */
+ {
+ sp->Next_Link = sitd->Next_Link;
+ }
+ }
+
+ /*------------------------------------------------------------------------*/
+ /* Remove this siTD from iso_ep's siTD list */
+ /*------------------------------------------------------------------------*/
+ if (sitd_pre == NULL)
+ {
+ iso_ep->sitd_list = sitd->next;
+ }
+ else
+ {
+ sitd_pre->next = sitd->next;
+ }
+ sp = sitd->next;
+ free_ehci_siTD(sitd);
+ sitd = sp;
+ }
+ else
+ {
+ sitd_pre = sitd;
+ sitd = sitd->next; /* traverse to the next siTD of siTD list */
+ }
+ }
+
+ iso_ep = iso_ep->next;
+ }
+
+ ENABLE_EHCI_IRQ();
+}
+
+
+static void write_itd_info(UTR_T *utr, iTD_T *itd)
+{
+ UDEV_T *udev = utr->udev;
+ EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */
+ uint32_t buff_page_addr;
+ int i;
+
+ buff_page_addr = itd->buff_base & 0xFFFFF000; /* 4K page */
+
+ for (i = 0; i < 7; i++)
+ {
+ itd->Bptr[i] = buff_page_addr + (0x1000 * i);
+ }
+ /* EndPtr R Device Address */
+ itd->Bptr[0] |= (udev->dev_num) | ((ep->bEndpointAddress & 0xF) << ITD_EP_NUM_Pos);
+ itd->Bptr[1] |= ep->wMaxPacketSize; /* Maximum Packet Size */
+
+ if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_IN) /* I/O */
+ itd->Bptr[1] |= ITD_DIR_IN;
+ else
+ itd->Bptr[1] |= ITD_DIR_OUT;
+
+ itd->Bptr[2] |= (ep->wMaxPacketSize + 1023)/1024; /* Mult */
+}
+
+static void write_itd_micro_frame(UTR_T *utr, int fidx, iTD_T *itd, int mf)
+{
+ uint32_t buff_addr;
+
+ buff_addr = (uint32_t)(utr->iso_buff[fidx]); /* xfer buffer start address of this frame */
+
+ itd->Transaction[mf] = ITD_STATUS_ACTIVE | /* Status */
+ ((utr->iso_xlen[fidx] & 0xFFF) << ITD_XLEN_Pos) | /* Transaction Length */
+ ((buff_addr & 0xFFFFF000) - (itd->buff_base & 0xFFFFF000)) | /* PG */
+ (buff_addr & 0xFFF); /* Transaction offset */
+}
+
+
+static void remove_iso_ep_from_list(ISO_EP_T *iso_ep)
+{
+ ISO_EP_T *p;
+
+ if (iso_ep_list == iso_ep)
+ {
+ iso_ep_list = iso_ep->next; /* it's the first entry, remove it */
+ return;
+ }
+
+ p = iso_ep_list; /* find the previous entry of iso_ep */
+ while (p->next != NULL)
+ {
+ if (p->next == iso_ep)
+ {
+ break;
+ }
+ p = p->next;
+ }
+
+ if (p->next == NULL)
+ {
+ return; /* not found */
+ }
+ p->next = iso_ep->next; /* remove iso_ep from list */
+}
+
+
+static __inline void add_itd_to_iso_ep(ISO_EP_T *iso_ep, iTD_T *itd)
+{
+ iTD_T *p;
+
+ itd->next = NULL;
+
+ if (iso_ep->itd_list == NULL)
+ {
+ iso_ep->itd_list = itd;
+ return;
+ }
+
+ /*
+ * Find the tail entry of iso_ep->itd_list
+ */
+ p = iso_ep->itd_list;
+ while (p->next != NULL)
+ {
+ p = p->next;
+ }
+ p->next = itd;
+}
+
+int ehci_iso_xfer(UTR_T *utr)
+{
+ EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */
+ ISO_EP_T *iso_ep; /* software iso endpoint descriptor */
+ iTD_T *itd, *itd_next, *itd_list = NULL;
+ int i, itd_cnt;
+ int trans_mask; /* bit mask of used xfer in an iTD */
+ int fidx; /* index to the 8 iso frames of UTR */
+ int interval; /* frame interval of iTD */
+
+ if (ep->hw_pipe != NULL)
+ {
+ iso_ep = (ISO_EP_T *)ep->hw_pipe; /* get reference of the isochronous endpoint */
+
+ if (utr->bIsoNewSched)
+ iso_ep->next_frame = (((_ehci->UFINDR + (EHCI_ISO_DELAY * 8)) & HSUSBH_UFINDR_FI_Msk) >> 3) & 0x3FF;
+ }
+ else
+ {
+ /* first time transfer of this iso endpoint */
+ iso_ep = usbh_alloc_mem(sizeof(*iso_ep));
+ if (iso_ep == NULL)
+ return USBH_ERR_MEMORY_OUT;
+
+ memset(iso_ep, 0, sizeof(*iso_ep));
+ iso_ep->ep = ep;
+ iso_ep->next_frame = (((_ehci->UFINDR + (EHCI_ISO_DELAY * 8)) & HSUSBH_UFINDR_FI_Msk) >> 3) & 0x3FF;
+
+ ep->hw_pipe = iso_ep;
+
+ /*
+ * Add this iso_ep into iso_ep_list
+ */
+ DISABLE_EHCI_IRQ();
+ iso_ep->next = iso_ep_list;
+ iso_ep_list = iso_ep;
+ ENABLE_EHCI_IRQ();
+ }
+
+ if (utr->udev->speed == SPEED_FULL)
+ return ehci_iso_split_xfer(utr, iso_ep);
+
+ /*------------------------------------------------------------------------------------*/
+ /* Allocate iTDs */
+ /*------------------------------------------------------------------------------------*/
+
+ if (ep->bInterval < 2) /* transfer interval is 1 micro-frame */
+ {
+ trans_mask = 0xFF;
+ itd_cnt = 1; /* required 1 iTD for one UTR */
+ interval = 1; /* iTD frame interval of this endpoint */
+ }
+ else if (ep->bInterval < 4) /* transfer interval is 2 micro-frames */
+ {
+ trans_mask = 0x55;
+ itd_cnt = 2; /* required 2 iTDs for one UTR */
+ interval = 1; /* iTD frame interval of this endpoint */
+ }
+ else if (ep->bInterval < 8) /* transfer interval is 4 micro-frames */
+ {
+ trans_mask = 0x44;
+ itd_cnt = 4; /* required 4 iTDs for one UTR */
+ interval = 1; /* iTD frame interval of this endpoint */
+ }
+ else if (ep->bInterval < 16) /* transfer interval is 8 micro-frames */
+ {
+ trans_mask = 0x08; /* there's 1 transfer in one iTD */
+ itd_cnt = 8; /* required 8 iTDs for one UTR */
+ interval = 1; /* iTD frame interval of this endpoint */
+ }
+ else if (ep->bInterval < 32) /* transfer interval is 16 micro-frames */
+ {
+ trans_mask = 0x10; /* there's 1 transfer in one iTD */
+ itd_cnt = 8; /* required 8 iTDs for one UTR */
+ interval = 2; /* iTD frame interval of this endpoint */
+ }
+ else if (ep->bInterval < 64) /* transfer interval is 32 micro-frames */
+ {
+ trans_mask = 0x02; /* there's 1 transfer in one iTD */
+ itd_cnt = 8; /* required 8 iTDs for one UTR */
+ interval = 4; /* iTD frame interval of this endpoint */
+ }
+ else /* transfer interval is 64 micro-frames */
+ {
+ trans_mask = 0x04; /* there's 1 transfer in one iTD */
+ itd_cnt = 8; /* required 8 iTDs for one UTR */
+ interval = 8; /* iTD frame interval of this endpoint */
+ }
+
+ for (i = 0; i < itd_cnt; i++) /* allocate all iTDs required by UTR */
+ {
+ itd = alloc_ehci_iTD();
+ if (itd == NULL)
+ goto malloc_failed;
+
+ if (itd_list == NULL) /* link all iTDs */
+ {
+ itd_list = itd;
+ }
+ else
+ {
+ itd->next = itd_list;
+ itd_list = itd;
+ }
+ }
+
+ utr->td_cnt = itd_cnt;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Fill and link all iTDs */
+ /*------------------------------------------------------------------------------------*/
+
+ utr->iso_sf = iso_ep->next_frame;
+ fidx = 0; /* index to UTR iso frmes (total IF_PER_UTR) */
+
+ for (itd = itd_list; (itd != NULL); )
+ {
+ if (fidx >= IF_PER_UTR) /* unlikely */
+ {
+ USB_error("EHCI driver ITD bug!?\n");
+ goto malloc_failed;
+ }
+
+ itd->utr = utr;
+ itd->fidx = fidx; /* index to UTR's n'th IF_PER_UTR frame */
+ itd->buff_base = (uint32_t)(utr->iso_buff[fidx]); /* iTD buffer base is buffer of the first UTR iso frame serviced by this iTD */
+ itd->trans_mask = trans_mask;
+
+ write_itd_info(utr, itd);
+
+ for (i = 0; i < 8; i++) /* settle xfer into micro-frames */
+ {
+ if (!(trans_mask & (0x1<Transaction[i] = 0; /* not accesed */
+ continue; /* not scheduled micro-frame */
+ }
+
+ write_itd_micro_frame(utr, fidx, itd, i);
+
+ fidx++; /* preceed to next UTR iso frame */
+
+ if (fidx == IF_PER_UTR) /* is the last scheduled micro-frame? */
+ {
+ /* raise interrupt on completed */
+ itd->Transaction[i] |= ITD_IOC;
+ break;
+ }
+ }
+
+ itd_next = itd->next; /* remember the next itd */
+
+ // USB_debug("Link iTD 0x%x, %d\n", (int)itd, iso_ep->next_frame);
+ /*
+ * Link iTD to period frame list
+ */
+ DISABLE_EHCI_IRQ();
+ itd->sched_frnidx = iso_ep->next_frame; /* remember it for reclamation scan */
+ add_itd_to_iso_ep(iso_ep, itd); /* add to software itd list */
+ itd->Next_Link = _PFList[itd->sched_frnidx]; /* keep the next link */
+ _PFList[itd->sched_frnidx] = ITD_HLNK_ITD(itd);
+ iso_ep->next_frame = (iso_ep->next_frame + interval) % FL_SIZE;
+ ENABLE_EHCI_IRQ();
+
+ itd = itd_next;
+ }
+
+ _ehci->UCMDR |= HSUSBH_UCMDR_PSEN_Msk; /* periodic list enable */
+ return 0;
+
+malloc_failed:
+
+ while (itd_list != NULL)
+ {
+ itd = itd_list;
+ itd_list = itd->next;
+ free_ehci_iTD(itd);
+ }
+ return USBH_ERR_MEMORY_OUT;
+}
+
+static __inline void add_sitd_to_iso_ep(ISO_EP_T *iso_ep, siTD_T *sitd)
+{
+ siTD_T *p;
+
+ sitd->next = NULL;
+
+ if (iso_ep->sitd_list == NULL)
+ {
+ iso_ep->sitd_list = sitd;
+ return;
+ }
+
+ /*
+ * Find the tail entry of iso_ep->itd_list
+ */
+ p = iso_ep->sitd_list;
+ while (p->next != NULL)
+ {
+ p = p->next;
+ }
+ p->next = sitd;
+}
+
+static void write_sitd_info(UTR_T *utr, siTD_T *sitd)
+{
+ UDEV_T *udev = utr->udev;
+ EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */
+ uint32_t buff_page_addr;
+ int xlen = utr->iso_xlen[sitd->fidx];
+ int scnt;
+
+ sitd->Chrst = (udev->port_num << SITD_PORT_NUM_Pos) |
+ (udev->parent->iface->udev->dev_num << SITD_HUB_ADDR_Pos) |
+ ((ep->bEndpointAddress & 0xF) << SITD_EP_NUM_Pos) |
+ (udev->dev_num << SITD_DEV_ADDR_Pos);
+
+ buff_page_addr = ((uint32_t)utr->iso_buff[sitd->fidx]) & 0xFFFFF000;
+ sitd->Bptr[0] = (uint32_t)(utr->iso_buff[sitd->fidx]);
+ sitd->Bptr[1] = buff_page_addr + 0x1000;
+
+ scnt = (xlen + 187) / 188;
+
+ if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_IN) /* I/O */
+ {
+ sitd->Chrst |= SITD_XFER_IN;
+ sitd->Sched = (1 << (scnt + 2)) - 1;
+ sitd->Sched = (sitd->Sched << 10) | 0x1;
+ //sitd->Sched <<= 1;
+ }
+ else
+ {
+ sitd->Chrst |= SITD_XFER_OUT;
+ sitd->Sched = sitd_OUT_Smask[scnt-1];
+ if (scnt > 1)
+ {
+ sitd->Bptr[1] |= (0x1 << 3); /* Transaction position (TP) 01b: Begin */
+ }
+ sitd->Bptr[1] |= scnt; /* Transaction count (T-Count) */
+ }
+
+ if (sitd->fidx == IF_PER_UTR)
+ {
+ sitd->Sched |= SITD_IOC;
+ }
+
+ sitd->StsCtrl = (xlen << SITD_XFER_CNT_Pos) | SITD_STATUS_ACTIVE;
+
+ sitd->BackLink = SITD_LIST_END;
+}
+
+
+static void ehci_sitd_adjust_schedule(siTD_T *sitd)
+{
+ siTD_T *hlink = (siTD_T *)_PFList[sitd->sched_frnidx];
+ uint32_t uframe_mask = 0x00;
+
+ while (hlink && !HLINK_IS_TERMINATED(hlink) && HLINK_IS_SITD(hlink))
+ {
+ hlink = SITD_PTR(hlink);
+ if (hlink != sitd)
+ {
+ if ((hlink->Chrst & SITD_XFER_IO_Msk) == SITD_XFER_IN)
+ {
+ uframe_mask |= (hlink->Sched & 0xFF); /* mark micro-frames used by IN S-mask */
+ uframe_mask |= ((hlink->Sched >> 8) & 0xFF); /* mark micro-frames used by IN C-mask */
+ }
+ else
+ {
+ uframe_mask |= (hlink->Sched & 0xFF); /* mark micro-frames used by OUT S-mask */
+ }
+ }
+ hlink = SITD_PTR(hlink->Next_Link);
+ }
+
+ uframe_mask = uframe_mask | (uframe_mask << 8); /* mark both S-mask and C-mask */
+
+ if (uframe_mask)
+ {
+ /*
+ * Shift afterward one micro-frame until no conflicts.
+ */
+ while (1)
+ {
+ if (sitd->Sched & uframe_mask)
+ {
+ sitd->Sched = (sitd->Sched & 0xFFFF0000) | ((sitd->Sched << 1) & 0xFFFF);
+ }
+ else
+ {
+ break; /* no conflit, done. */
+ }
+ }
+ }
+}
+
+
+static int ehci_iso_split_xfer(UTR_T *utr, ISO_EP_T *iso_ep)
+{
+ EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */
+ siTD_T *sitd, *sitd_next, *sitd_list = NULL;
+ int i;
+ int fidx; /* index to the 8 iso frames of UTR */
+
+ if (utr->udev->parent == NULL)
+ {
+ USB_error("siso xfer - parent lost!\n");
+ return USBH_ERR_INVALID_PARAM;
+ }
+
+ /*------------------------------------------------------------------------------------*/
+ /* Allocate siTDs */
+ /*------------------------------------------------------------------------------------*/
+ for (i = 0; i < IF_PER_UTR; i++) /* allocate all siTDs required by UTR */
+ {
+ sitd = alloc_ehci_siTD();
+ if (sitd == NULL)
+ goto malloc_failed;
+
+ if (sitd_list == NULL) /* link all siTDs */
+ {
+ sitd_list = sitd;
+ }
+ else
+ {
+ sitd->next = sitd_list;
+ sitd_list = sitd;
+ }
+ }
+
+ utr->td_cnt = IF_PER_UTR;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Fill and link all siTDs */
+ /*------------------------------------------------------------------------------------*/
+
+ utr->iso_sf = iso_ep->next_frame;
+ fidx = 0; /* index to UTR iso frmes (total IF_PER_UTR) */
+
+ for (sitd = sitd_list; (sitd != NULL); fidx++)
+ {
+ if (fidx >= IF_PER_UTR) /* unlikely */
+ {
+ USB_error("EHCI driver siTD bug!?\n");
+ goto malloc_failed;
+ }
+
+ sitd->utr = utr;
+ sitd->fidx = fidx; /* index to UTR's n'th IF_PER_UTR frame */
+
+ write_sitd_info(utr, sitd);
+
+ sitd_next = sitd->next; /* remember the next itd */
+
+ // USB_debug("Link iTD 0x%x, %d\n", (int)itd, iso_ep->next_frame);
+ /*
+ * Link iTD to period frame list
+ */
+ sitd->sched_frnidx = iso_ep->next_frame; /* remember it for reclamation scan */
+ DISABLE_EHCI_IRQ();
+ ehci_sitd_adjust_schedule(sitd);
+ add_sitd_to_iso_ep(iso_ep, sitd); /* add to software itd list */
+ sitd->Next_Link = _PFList[sitd->sched_frnidx];/* keep the next link */
+ _PFList[sitd->sched_frnidx] = SITD_HLNK_SITD(sitd);
+ iso_ep->next_frame = (iso_ep->next_frame + ep->bInterval) % FL_SIZE;
+ ENABLE_EHCI_IRQ();
+
+ sitd = sitd_next;
+ }
+
+ _ehci->UCMDR |= HSUSBH_UCMDR_PSEN_Msk; /* periodic list enable */
+ return 0;
+
+malloc_failed:
+
+ while (sitd_list != NULL)
+ {
+ sitd = sitd_list;
+ sitd_list = sitd->next;
+ free_ehci_siTD(sitd);
+ }
+ return USBH_ERR_MEMORY_OUT;
+}
+
+/*
+ * If it's an isochronous endpoint, quit current transfer via UTR or hardware EP.
+ */
+int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep)
+{
+ ISO_EP_T *iso_ep;
+ iTD_T *itd, *itd_next, *p;
+ uint32_t frnidx;
+ uint32_t now_frame;
+
+ if (ep == NULL)
+ {
+ if (utr == NULL)
+ return USBH_ERR_NOT_FOUND;
+
+ if (utr->ep == NULL)
+ return USBH_ERR_NOT_FOUND;
+
+ ep = utr->ep;
+ }
+
+ if ((ep->bmAttributes & EP_ATTR_TT_MASK) != EP_ATTR_TT_ISO)
+ return USBH_ERR_NOT_FOUND; /* not isochronous endpoint */
+
+ /*------------------------------------------------------------------------------------*/
+ /* It's an iso endpoint. Remove it as required. */
+ /*------------------------------------------------------------------------------------*/
+ iso_ep = iso_ep_list;
+ while (iso_ep != NULL) /* Search all activated iso endpoints */
+ {
+ if (iso_ep->ep == ep)
+ break;
+ iso_ep = iso_ep->next;
+ }
+ if (iso_ep == NULL)
+ return 0; /* should have been removed */
+
+ itd = iso_ep->itd_list; /* get the first iTD from iso_ep's iTD list */
+
+ while (itd != NULL) /* traverse all iTDs of itd list */
+ {
+ itd_next = itd->next; /* remember the next iTD */
+ utr = itd->utr;
+
+ /*--------------------------------------------------------------------------------*/
+ /* Remove this iTD from period frame list */
+ /*--------------------------------------------------------------------------------*/
+ frnidx = itd->sched_frnidx;
+
+ /*
+ * Prevent to race with Host Controller. If the iTD to be removed is located in
+ * current or next frame, wait until HC passed through it.
+ */
+ while (1)
+ {
+ now_frame = (_ehci->UFINDR >> 3) & 0x3FF;
+ if ((now_frame == frnidx) || (((now_frame+1)%1024) == frnidx))
+ continue;
+ break;
+ }
+
+ if (_PFList[frnidx] == ITD_HLNK_ITD(itd))
+ {
+ /* is the first entry, just change to next */
+ _PFList[frnidx] = itd->Next_Link;
+ }
+ else
+ {
+ p = ITD_PTR(_PFList[frnidx]); /* find the preceding iTD */
+ while ((ITD_PTR(p->Next_Link) != itd) && (p != NULL))
+ {
+ p = ITD_PTR(p->Next_Link);
+ }
+
+ if (p == NULL) /* link list out of control! */
+ {
+ USB_error("ehci_quit_iso_xfer - An iTD lost reference to periodic frame list! 0x%x on %d\n", (int)itd, frnidx);
+ }
+ else /* remove iTD from list */
+ {
+ p->Next_Link = itd->Next_Link;
+ }
+ }
+
+ utr->td_cnt--;
+
+ if (utr->td_cnt == 0) /* All iTD of this UTR done */
+ {
+ utr->bIsTransferDone = 1;
+ if (utr->func)
+ utr->func(utr);
+ utr->status = USBH_ERR_ABORT;
+ }
+ free_ehci_iTD(itd);
+ itd = itd_next;
+ }
+
+ /*
+ * Remove iso_ep from iso_ep_list
+ */
+ remove_iso_ep_from_list(iso_ep);
+ usbh_free_mem(iso_ep, sizeof(*iso_ep)); /* free this iso_ep */
+ ep->hw_pipe = NULL;
+
+ if (iso_ep_list == NULL)
+ _ehci->UCMDR &= ~HSUSBH_UCMDR_PSEN_Msk;
+
+ return 0;
+}
+
+
+/// @endcond HIDDEN_SYMBOLS
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/src/mem_alloc.c b/bsp/nuvoton/libraries/m480/USBHostLib/src/mem_alloc.c
new file mode 100644
index 00000000000..d0eab237700
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/USBHostLib/src/mem_alloc.c
@@ -0,0 +1,503 @@
+/**************************************************************************//**
+ * @file mem_alloc.c
+ * @version V1.10
+ * @brief USB host library memory allocation functions.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include
+#include
+
+#include "NuMicro.h"
+
+#include "usb.h"
+
+
+/// @cond HIDDEN_SYMBOLS
+
+//#define MEM_DEBUG
+
+#ifdef MEM_DEBUG
+#define mem_debug rt_kprintf
+#else
+#define mem_debug(...)
+#endif
+
+#ifdef __ICCARM__
+#pragma data_alignment=32
+static uint8_t _mem_pool[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE];
+#else
+static uint8_t _mem_pool[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE] __attribute__((aligned(32)));
+#endif
+static uint8_t _unit_used[MEM_POOL_UNIT_NUM];
+
+static volatile int _usbh_mem_used;
+static volatile int _usbh_max_mem_used;
+static volatile int _mem_pool_used;
+
+
+UDEV_T * g_udev_list;
+
+uint8_t _dev_addr_pool[128];
+static volatile int _device_addr;
+
+static int _sidx = 0;;
+
+/*--------------------------------------------------------------------------*/
+/* Memory alloc/free recording */
+/*--------------------------------------------------------------------------*/
+
+void usbh_memory_init(void)
+{
+ if (sizeof(TD_T) > MEM_POOL_UNIT_SIZE)
+ {
+ USB_error("TD_T - MEM_POOL_UNIT_SIZE too small!\n");
+ while (1);
+ }
+
+ if (sizeof(ED_T) > MEM_POOL_UNIT_SIZE)
+ {
+ USB_error("ED_T - MEM_POOL_UNIT_SIZE too small!\n");
+ while (1);
+ }
+
+ _usbh_mem_used = 0L;
+ _usbh_max_mem_used = 0L;
+
+ memset(_unit_used, 0, sizeof(_unit_used));
+ _mem_pool_used = 0;
+ _sidx = 0;
+
+ g_udev_list = NULL;
+
+ memset(_dev_addr_pool, 0, sizeof(_dev_addr_pool));
+ _device_addr = 1;
+}
+
+uint32_t usbh_memory_used(void)
+{
+ rt_kprintf("USB static memory: %d/%d, heap used: %d\n", _mem_pool_used, MEM_POOL_UNIT_NUM, _usbh_mem_used);
+ return _usbh_mem_used;
+}
+
+static void memory_counter(int size)
+{
+ _usbh_mem_used += size;
+ if (_usbh_mem_used > _usbh_max_mem_used)
+ _usbh_max_mem_used = _usbh_mem_used;
+}
+
+void * usbh_alloc_mem(int size)
+{
+ void *p;
+
+ p = malloc(size);
+ if (p == NULL)
+ {
+ USB_error("usbh_alloc_mem failed! %d\n", size);
+ return NULL;
+ }
+
+ memset(p, 0, size);
+ memory_counter(size);
+ return p;
+}
+
+void usbh_free_mem(void *p, int size)
+{
+ free(p);
+ memory_counter(0-size);
+}
+
+
+/*--------------------------------------------------------------------------*/
+/* USB device allocate/free */
+/*--------------------------------------------------------------------------*/
+
+UDEV_T * alloc_device(void)
+{
+ UDEV_T *udev;
+
+ udev = malloc(sizeof(*udev));
+ if (udev == NULL)
+ {
+ USB_error("alloc_device failed!\n");
+ return NULL;
+ }
+ memset(udev, 0, sizeof(*udev));
+ memory_counter(sizeof(*udev));
+ udev->cur_conf = -1; /* must! used to identify the first SET CONFIGURATION */
+ udev->next = g_udev_list; /* chain to global device list */
+ g_udev_list = udev;
+ return udev;
+}
+
+void free_device(UDEV_T *udev)
+{
+ UDEV_T *d;
+
+ if (udev == NULL)
+ return;
+
+ if (udev->cfd_buff != NULL)
+ usbh_free_mem(udev->cfd_buff, MAX_DESC_BUFF_SIZE);
+
+ /*
+ * Remove it from the global device list
+ */
+ if (g_udev_list == udev)
+ {
+ g_udev_list = g_udev_list->next;
+ }
+ else
+ {
+ d = g_udev_list;
+ while (d != NULL)
+ {
+ if (d->next == udev)
+ {
+ d->next = udev->next;
+ break;
+ }
+ d = d->next;
+ }
+ }
+
+ free(udev);
+ memory_counter(-sizeof(*udev));
+}
+
+int alloc_dev_address(void)
+{
+ _device_addr++;
+
+ if (_device_addr >= 128)
+ _device_addr = 1;
+
+ while (1)
+ {
+ if (_dev_addr_pool[_device_addr] == 0)
+ {
+ _dev_addr_pool[_device_addr] = 1;
+ return _device_addr;
+ }
+ _device_addr++;
+ if (_device_addr >= 128)
+ _device_addr = 1;
+ }
+}
+
+void free_dev_address(int dev_addr)
+{
+ if (dev_addr < 128)
+ _dev_addr_pool[dev_addr] = 0;
+}
+
+/*--------------------------------------------------------------------------*/
+/* UTR (USB Transfer Request) allocate/free */
+/*--------------------------------------------------------------------------*/
+
+UTR_T * alloc_utr(UDEV_T *udev)
+{
+ UTR_T *utr;
+
+ utr = malloc(sizeof(*utr));
+ if (utr == NULL)
+ {
+ USB_error("alloc_utr failed!\n");
+ return NULL;
+ }
+ memory_counter(sizeof(*utr));
+ memset(utr, 0, sizeof(*utr));
+ utr->udev = udev;
+ mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr);
+ return utr;
+}
+
+void free_utr(UTR_T *utr)
+{
+ if (utr == NULL)
+ return;
+
+ mem_debug("[FREE] [UTR] - 0x%x\n", (int)utr);
+ free(utr);
+ memory_counter(0-(int)sizeof(*utr));
+}
+
+/*--------------------------------------------------------------------------*/
+/* OHCI ED allocate/free */
+/*--------------------------------------------------------------------------*/
+
+ED_T * alloc_ohci_ED(void)
+{
+ int i;
+ ED_T *ed;
+
+ for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+ {
+ if (_unit_used[i] == 0)
+ {
+ _unit_used[i] = 1;
+ _mem_pool_used++;
+ ed = (ED_T *)&_mem_pool[i];
+ memset(ed, 0, sizeof(*ed));
+ mem_debug("[ALLOC] [ED] - 0x%x\n", (int)ed);
+ return ed;
+ }
+ }
+ USB_error("alloc_ohci_ED failed!\n");
+ return NULL;
+}
+
+void free_ohci_ED(ED_T *ed)
+{
+ int i;
+
+ for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+ {
+ if ((uint32_t)&_mem_pool[i] == (uint32_t)ed)
+ {
+ mem_debug("[FREE] [ED] - 0x%x\n", (int)ed);
+ _unit_used[i] = 0;
+ _mem_pool_used--;
+ return;
+ }
+ }
+ USB_debug("free_ohci_ED - not found! (ignored in case of multiple UTR)\n");
+}
+
+/*--------------------------------------------------------------------------*/
+/* OHCI TD allocate/free */
+/*--------------------------------------------------------------------------*/
+TD_T * alloc_ohci_TD(UTR_T *utr)
+{
+ int i;
+ TD_T *td;
+
+ for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+ {
+ if (_unit_used[i] == 0)
+ {
+ _unit_used[i] = 1;
+ _mem_pool_used++;
+ td = (TD_T *)&_mem_pool[i];
+
+ memset(td, 0, sizeof(*td));
+ td->utr = utr;
+ mem_debug("[ALLOC] [TD] - 0x%x\n", (int)td);
+ return td;
+ }
+ }
+ USB_error("alloc_ohci_TD failed!\n");
+ return NULL;
+}
+
+void free_ohci_TD(TD_T *td)
+{
+ int i;
+
+ for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+ {
+ if ((uint32_t)&_mem_pool[i] == (uint32_t)td)
+ {
+ mem_debug("[FREE] [TD] - 0x%x\n", (int)td);
+ _unit_used[i] = 0;
+ _mem_pool_used--;
+ return;
+ }
+ }
+ USB_error("free_ohci_TD - not found!\n");
+}
+
+/*--------------------------------------------------------------------------*/
+/* EHCI QH allocate/free */
+/*--------------------------------------------------------------------------*/
+QH_T * alloc_ehci_QH(void)
+{
+ int i;
+ QH_T *qh = NULL;
+
+ for (i = (_sidx+1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i+1) % MEM_POOL_UNIT_NUM)
+ {
+ if (_unit_used[i] == 0)
+ {
+ _unit_used[i] = 1;
+ _sidx = i;
+ _mem_pool_used++;
+ qh = (QH_T *)&_mem_pool[i];
+ memset(qh, 0, sizeof(*qh));
+ mem_debug("[ALLOC] [QH] - 0x%x\n", (int)qh);
+ break;
+ }
+ }
+ if (qh == NULL)
+ {
+ USB_error("alloc_ehci_QH failed!\n");
+ return NULL;
+ }
+ qh->Curr_qTD = QTD_LIST_END;
+ qh->OL_Next_qTD = QTD_LIST_END;
+ qh->OL_Alt_Next_qTD = QTD_LIST_END;
+ qh->OL_Token = QTD_STS_HALT;
+ return qh;
+}
+
+void free_ehci_QH(QH_T *qh)
+{
+ int i;
+
+ for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+ {
+ if ((uint32_t)&_mem_pool[i] == (uint32_t)qh)
+ {
+ mem_debug("[FREE] [QH] - 0x%x\n", (int)qh);
+ _unit_used[i] = 0;
+ _mem_pool_used--;
+ return;
+ }
+ }
+ USB_debug("free_ehci_QH - not found! (ignored in case of multiple UTR)\n");
+}
+
+/*--------------------------------------------------------------------------*/
+/* EHCI qTD allocate/free */
+/*--------------------------------------------------------------------------*/
+qTD_T * alloc_ehci_qTD(UTR_T *utr)
+{
+ int i;
+ qTD_T *qtd;
+
+ for (i = (_sidx+1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i+1) % MEM_POOL_UNIT_NUM)
+ {
+ if (_unit_used[i] == 0)
+ {
+ _unit_used[i] = 1;
+ _sidx = i;
+ _mem_pool_used++;
+ qtd = (qTD_T *)&_mem_pool[i];
+
+ memset(qtd, 0, sizeof(*qtd));
+ qtd->Next_qTD = QTD_LIST_END;
+ qtd->Alt_Next_qTD = QTD_LIST_END;
+ qtd->Token = 0x1197B3F; // QTD_STS_HALT; visit_qtd() will not remove a qTD with this mark. It means the qTD still not ready for transfer.
+ qtd->utr = utr;
+ mem_debug("[ALLOC] [qTD] - 0x%x\n", (int)qtd);
+ return qtd;
+ }
+ }
+ USB_error("alloc_ehci_qTD failed!\n");
+ return NULL;
+}
+
+void free_ehci_qTD(qTD_T *qtd)
+{
+ int i;
+
+ for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+ {
+ if ((uint32_t)&_mem_pool[i] == (uint32_t)qtd)
+ {
+ mem_debug("[FREE] [qTD] - 0x%x\n", (int)qtd);
+ _unit_used[i] = 0;
+ _mem_pool_used--;
+ return;
+ }
+ }
+ USB_error("free_ehci_qTD 0x%x - not found!\n", (int)qtd);
+}
+
+/*--------------------------------------------------------------------------*/
+/* EHCI iTD allocate/free */
+/*--------------------------------------------------------------------------*/
+iTD_T * alloc_ehci_iTD(void)
+{
+ int i;
+ iTD_T *itd;
+
+ for (i = (_sidx+1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i+1) % MEM_POOL_UNIT_NUM)
+ {
+ if (i+2 >= MEM_POOL_UNIT_NUM)
+ continue;
+
+ if ((_unit_used[i] == 0) && (_unit_used[i+1] == 0))
+ {
+ _unit_used[i] = _unit_used[i+1] = 1;
+ _sidx = i+1;
+ _mem_pool_used += 2;
+ itd = (iTD_T *)&_mem_pool[i];
+ memset(itd, 0, sizeof(*itd));
+ mem_debug("[ALLOC] [iTD] - 0x%x\n", (int)itd);
+ return itd;
+ }
+ }
+ USB_error("alloc_ehci_iTD failed!\n");
+ return NULL;
+}
+
+void free_ehci_iTD(iTD_T *itd)
+{
+ int i;
+
+ for (i = 0; i+1 < MEM_POOL_UNIT_NUM; i++)
+ {
+ if ((uint32_t)&_mem_pool[i] == (uint32_t)itd)
+ {
+ mem_debug("[FREE] [iTD] - 0x%x\n", (int)itd);
+ _unit_used[i] = _unit_used[i+1] = 0;
+ _mem_pool_used -= 2;
+ return;
+ }
+ }
+ USB_error("free_ehci_iTD 0x%x - not found!\n", (int)itd);
+}
+
+/*--------------------------------------------------------------------------*/
+/* EHCI iTD allocate/free */
+/*--------------------------------------------------------------------------*/
+siTD_T * alloc_ehci_siTD(void)
+{
+ int i;
+ siTD_T *sitd;
+
+ for (i = (_sidx+1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i+1) % MEM_POOL_UNIT_NUM)
+ {
+ if (_unit_used[i] == 0)
+ {
+ _unit_used[i] = 1;
+ _sidx = i;
+ _mem_pool_used ++;
+ sitd = (siTD_T *)&_mem_pool[i];
+ memset(sitd, 0, sizeof(*sitd));
+ mem_debug("[ALLOC] [siTD] - 0x%x\n", (int)sitd);
+ return sitd;
+ }
+ }
+ USB_error("alloc_ehci_siTD failed!\n");
+ return NULL;
+}
+
+void free_ehci_siTD(siTD_T *sitd)
+{
+ int i;
+
+ for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+ {
+ if ((uint32_t)&_mem_pool[i] == (uint32_t)sitd)
+ {
+ mem_debug("[FREE] [siTD] - 0x%x\n", (int)sitd);
+ _unit_used[i] = 0;
+ _mem_pool_used--;
+ return;
+ }
+ }
+ USB_error("free_ehci_siTD 0x%x - not found!\n", (int)sitd);
+}
+
+/// @endcond HIDDEN_SYMBOLS
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/src/ohci.c b/bsp/nuvoton/libraries/m480/USBHostLib/src/ohci.c
new file mode 100644
index 00000000000..fd5a87fb9fb
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/USBHostLib/src/ohci.c
@@ -0,0 +1,1292 @@
+/**************************************************************************//**
+ * @file ohci.c
+ * @version V1.10
+ * @brief USB Host library OHCI (USB 1.1) host controller driver.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include
+#include
+
+#include "NuMicro.h"
+
+#include "usb.h"
+#include "hub.h"
+#include "ohci.h"
+
+/// @cond HIDDEN_SYMBOLS
+
+//#define TD_debug printf
+#define TD_debug(...)
+
+//#define ED_debug printf
+#define ED_debug(...)
+
+#ifdef __ICCARM__
+#pragma data_alignment=256
+HCCA_T _hcca;
+#else
+HCCA_T _hcca __attribute__((aligned(256)));
+#endif
+
+ED_T * _Ied[6];
+
+
+static ED_T *ed_remove_list;
+
+static void add_to_ED_remove_list(ED_T *ed)
+{
+ ED_T *p;
+
+ ED_debug("add_to_ED_remove_list - 0x%x (0x%x)\n", (int)ed, ed->Info);
+ DISABLE_OHCI_IRQ();
+
+ /* check if this ED found in ed_remove_list */
+ p = ed_remove_list;
+ while (p)
+ {
+ if (p == ed)
+ {
+ ENABLE_OHCI_IRQ(); /* This ED found in ed_remove_list */
+ return; /* do nothing */
+ }
+ p = p->next;
+ }
+
+ ed->Info |= ED_SKIP; /* ask OHCI controller skip this ED */
+ ed->next = ed_remove_list;
+ ed_remove_list = ed; /* insert to the head of ed_remove_list */
+ ENABLE_OHCI_IRQ();
+ _ohci->HcInterruptStatus = USBH_HcInterruptStatus_SF_Msk;
+ _ohci->HcInterruptEnable |= USBH_HcInterruptEnable_SF_Msk;
+ usbh_delay_ms(2); /* Full speed wait 2 ms is enough */
+}
+
+static int ohci_reset(void)
+{
+ volatile int t0;
+
+ /* Disable HC interrupts */
+ _ohci->HcInterruptDisable = USBH_HcInterruptDisable_MIE_Msk;
+
+ /* HC Reset requires max 10 ms delay */
+ _ohci->HcControl = 0;
+ _ohci->HcCommandStatus = USBH_HcCommandStatus_HCR_Msk;
+
+ usbh_delay_ms(10);
+
+ /* Check if OHCI reset completed? */
+ if ((USBH->HcCommandStatus & USBH_HcCommandStatus_HCR_Msk) != 0)
+ {
+ USB_error("Error! - USB OHCI reset timed out!\n");
+ return -1;
+ }
+
+ USBH->HcRhStatus = USBH_HcRhStatus_OCI_Msk | USBH_HcRhStatus_LPS_Msk;
+
+ USBH->HcControl = HCFS_RESET;
+
+ usbh_delay_ms(10);
+
+ /* Check if OHCI reset completed? */
+ if ((USBH->HcCommandStatus & USBH_HcCommandStatus_HCR_Msk) != 0)
+ {
+ USB_error("Error! - USB HC reset timed out!\n");
+ return -1;
+ }
+ return 0;
+}
+
+static void init_hcca_int_table()
+{
+ ED_T *ed_p;
+ int i, idx, interval;
+
+ memset(_hcca.int_table, 0, sizeof(_hcca.int_table));
+
+ for (i = 5; i >= 0; i--) /* interval = i^2 */
+ {
+ _Ied[i] = alloc_ohci_ED();
+ _Ied[i]->Info = ED_SKIP;
+
+ interval = 0x1 << i;
+
+ for (idx = interval - 1; idx < 32; idx += interval)
+ {
+ if (_hcca.int_table[idx] == 0) /* is empty list, insert directly */
+ {
+ _hcca.int_table[idx] = (uint32_t)_Ied[i];
+ }
+ else
+ {
+ ed_p = (ED_T *)_hcca.int_table[idx];
+
+ while (1)
+ {
+ if (ed_p == _Ied[i])
+ break; /* already chained by previous visit */
+
+ if (ed_p->NextED == 0) /* reach end of list? */
+ {
+ ed_p->NextED = (uint32_t)_Ied[i];
+ break;
+ }
+ ed_p = (ED_T *)ed_p->NextED;
+ }
+ }
+ }
+ }
+}
+
+static ED_T * get_int_tree_head_node(int interval)
+{
+ int i;
+
+ for (i = 0; i < 5; i++)
+ {
+ interval >>= 1;
+ if (interval == 0)
+ return _Ied[i];
+ }
+ return _Ied[5]; /* for interval >= 32 */
+}
+
+static int get_ohci_interval(int interval)
+{
+ int i, bInterval = 1;
+
+ for (i = 0; i < 5; i++)
+ {
+ interval >>= 1;
+ if (interval == 0)
+ return bInterval;
+ bInterval *= 2;
+ }
+ return 32; /* for interval >= 32 */
+}
+
+
+static int ohci_init(void)
+{
+ uint32_t fminterval;
+ volatile int i;
+
+ if (ohci_reset() < 0)
+ return -1;
+
+ ed_remove_list = NULL;
+
+ init_hcca_int_table();
+
+ /* Tell the controller where the control and bulk lists are
+ * The lists are empty now. */
+ _ohci->HcControlHeadED = 0; /* control ED list head */
+ _ohci->HcBulkHeadED = 0; /* bulk ED list head */
+
+ _ohci->HcHCCA = (uint32_t)&_hcca; /* HCCA area */
+
+ /* periodic start 90% of frame interval */
+ fminterval = 0x2edf; /* 11,999 */
+ _ohci->HcPeriodicStart = (fminterval*9)/10;
+
+ /* set FSLargestDataPacket, 10,104 for 0x2edf frame interval */
+ fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+ _ohci->HcFmInterval = fminterval;
+
+ _ohci->HcLSThreshold = 0x628;
+
+ /* start controller operations */
+ _ohci->HcControl = HCFS_OPER | (0x3 << USBH_HcControl_CBSR_Pos);
+
+#ifdef OHCI_PER_PORT_POWER
+ _ohci->HcRhDescriptorB = 0x60000;
+ _ohci->HcRhPortStatus[0] = USBH_HcRhPortStatus_PPS_Msk;
+ _ohci->HcRhPortStatus[1] = USBH_HcRhPortStatus_PPS_Msk;
+#else
+ _ohci->HcRhDescriptorA = (USBH->HcRhDescriptorA | (1<<9)) & ~USBH_HcRhDescriptorA_PSM_Msk;
+ _ohci->HcRhStatus = USBH_HcRhStatus_LPSC_Msk;
+#endif
+
+ _ohci->HcInterruptEnable = USBH_HcInterruptEnable_MIE_Msk | USBH_HcInterruptEnable_WDH_Msk | USBH_HcInterruptEnable_SF_Msk;
+
+ /* POTPGT delay is bits 24-31, in 20 ms units. */
+ usbh_delay_ms(20);
+ return 0;
+}
+
+static void ohci_suspend(void)
+{
+ /* set port suspend if connected */
+ if (_ohci->HcRhPortStatus[0] & 0x1)
+ _ohci->HcRhPortStatus[0] = 0x4;
+
+ if (_ohci->HcRhPortStatus[1] & 0x1)
+ _ohci->HcRhPortStatus[1] = 0x4;
+
+ /* enable Device Remote Wakeup */
+ _ohci->HcRhStatus |= USBH_HcRhStatus_DRWE_Msk;
+
+ /* enable USBH RHSC interrupt for system wakeup */
+ _ohci->HcInterruptEnable |= USBH_HcInterruptEnable_RHSC_Msk | USBH_HcInterruptEnable_RD_Msk;
+
+ /* set Host Controller enter suspend state */
+ _ohci->HcControl = (USBH->HcControl & ~USBH_HcControl_HCFS_Msk) | (3 << USBH_HcControl_HCFS_Pos);
+}
+
+static void ohci_resume(void)
+{
+ _ohci->HcControl = (USBH->HcControl & ~USBH_HcControl_HCFS_Msk) | (1 << USBH_HcControl_HCFS_Pos);
+ _ohci->HcControl = (USBH->HcControl & ~USBH_HcControl_HCFS_Msk) | (2 << USBH_HcControl_HCFS_Pos);
+
+ if (_ohci->HcRhPortStatus[0] & 0x4)
+ _ohci->HcRhPortStatus[0] = 0x8;
+ if (_ohci->HcRhPortStatus[1] & 0x4)
+ _ohci->HcRhPortStatus[1] = 0x8;
+}
+
+static void ohci_shutdown(void)
+{
+ ohci_suspend();
+ NVIC_DisableIRQ(USBH_IRQn);
+#ifndef OHCI_PER_PORT_POWER
+ _ohci->HcRhStatus = USBH_HcRhStatus_LPS_Msk;
+#endif
+}
+
+
+/*
+ * Quit current trasnfer via UTR or hardware EP.
+ */
+static int ohci_quit_xfer(UTR_T *utr, EP_INFO_T *ep)
+{
+ ED_T *ed;
+
+ if (utr != NULL)
+ {
+ if (utr->ep == NULL)
+ return USBH_ERR_NOT_FOUND;
+
+ ed = (ED_T *)(utr->ep->hw_pipe);
+
+ if (!ed)
+ return USBH_ERR_NOT_FOUND;
+
+ /* add the endpoint to remove list, it will be removed on the next start of frame */
+ add_to_ED_remove_list(ed);
+ utr->ep->hw_pipe = NULL;
+ }
+
+ if ((ep != NULL) && (ep->hw_pipe != NULL))
+ {
+ ed = (ED_T *)(ep->hw_pipe);
+ /* add the endpoint to remove list, it will be removed on the next start of frame */
+ add_to_ED_remove_list(ed);
+ ep->hw_pipe = NULL;
+ }
+
+ return 0;
+}
+
+uint32_t ed_make_info(UDEV_T *udev, EP_INFO_T *ep)
+{
+ uint32_t info;
+
+ if (ep == NULL) /* is a control endpoint */
+ {
+ /* control endpoint direction is from TD */
+ if (udev->descriptor.bMaxPacketSize0 == 0) /* is 0 if device descriptor still not obtained. */
+ {
+ if (udev->speed == SPEED_LOW) /* give a default maximum packet size */
+ udev->descriptor.bMaxPacketSize0 = 8;
+ else
+ udev->descriptor.bMaxPacketSize0 = 64;
+ }
+ info = (udev->descriptor.bMaxPacketSize0 << 16) /* Control endpoint Maximum Packet Size from device descriptor */
+ | ED_DIR_BY_TD /* Direction (Get direction From TD) */
+ | ED_FORMAT_GENERAL /* General format */
+ | (0 << ED_CTRL_EN_Pos); /* Endpoint address 0 */
+ }
+ else /* Other endpoint direction is from endpoint descriptor */
+ {
+ info = (ep->wMaxPacketSize << 16); /* Maximum Packet Size from endpoint */
+
+ info |= ((ep->bEndpointAddress & 0xf) << ED_CTRL_EN_Pos); /* Endpoint Number */
+
+ if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_IN)
+ info |= ED_DIR_IN;
+ else
+ info |= ED_DIR_OUT;
+
+ if ((ep->bmAttributes & EP_ATTR_TT_MASK) == EP_ATTR_TT_ISO)
+ info |= ED_FORMAT_ISO;
+ else
+ info |= ED_FORMAT_GENERAL;
+ }
+
+ info |= ((udev->speed == SPEED_LOW) ? ED_SPEED_LOW : ED_SPEED_FULL); /* Speed */
+ info |= (udev->dev_num); /* Function Address */
+
+ return info;
+}
+
+static void write_td(TD_T *td, uint32_t info, uint8_t *buff, uint32_t data_len)
+{
+ td->Info = info;
+ td->CBP = (uint32_t)((!buff || !data_len) ? 0 : buff);
+ td->BE = (uint32_t)((!buff || !data_len ) ? 0 : (uint32_t)buff + data_len - 1);
+ td->buff_start = td->CBP;
+ // TD_debug("TD [0x%x]: 0x%x, 0x%x, 0x%x\n", (int)td, td->Info, td->CBP, td->BE);
+}
+
+static int ohci_ctrl_xfer(UTR_T *utr)
+{
+ UDEV_T *udev;
+ ED_T *ed;
+ TD_T *td_setup, *td_data, *td_status;
+ uint32_t info;
+
+ udev = utr->udev;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Allocate ED and TDs */
+ /*------------------------------------------------------------------------------------*/
+ td_setup = alloc_ohci_TD(utr);
+
+ if (utr->data_len > 0)
+ td_data = alloc_ohci_TD(utr);
+ else
+ td_data = NULL;
+
+ td_status = alloc_ohci_TD(utr);
+
+ if (td_status == NULL)
+ {
+ free_ohci_TD(td_setup);
+ if (utr->data_len > 0)
+ free_ohci_TD(td_data);
+ return USBH_ERR_MEMORY_OUT;
+ }
+
+ /* Check if there's any transfer pending on this endpoint... */
+ if (udev->ep0.hw_pipe == NULL)
+ {
+ ed = alloc_ohci_ED();
+ if (ed == NULL)
+ {
+ free_ohci_TD(td_setup);
+ free_ohci_TD(td_status);
+ if (utr->data_len > 0)
+ free_ohci_TD(td_data);
+ return USBH_ERR_MEMORY_OUT;
+ }
+ }
+ else
+ ed = (ED_T *)udev->ep0.hw_pipe;
+
+ /*------------------------------------------------------------------------------------*/
+ /* prepare SETUP stage TD */
+ /*------------------------------------------------------------------------------------*/
+ info = TD_CC | TD_T_DATA0 | TD_TYPE_CTRL;
+ write_td(td_setup, info, (uint8_t *)&utr->setup, 8);
+ td_setup->ed = ed;
+
+ /*------------------------------------------------------------------------------------*/
+ /* prepare DATA stage TD */
+ /*------------------------------------------------------------------------------------*/
+ if (utr->data_len > 0)
+ {
+ if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT)
+ info = (TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 | TD_TYPE_CTRL | TD_CTRL_DATA);
+ else
+ info = (TD_CC | TD_R | TD_DP_IN | TD_T_DATA1 | TD_TYPE_CTRL | TD_CTRL_DATA);
+
+ write_td(td_data, info, utr->buff, utr->data_len);
+ td_data->ed = ed;
+ td_setup->NextTD = (uint32_t)td_data;
+ td_setup->next = td_data;
+ td_data->NextTD = (uint32_t)td_status;
+ td_data->next = td_status;
+ }
+ else
+ {
+ td_setup->NextTD = (uint32_t)td_status;
+ td_setup->next = td_status;
+ }
+
+ /*------------------------------------------------------------------------------------*/
+ /* prepare STATUS stage TD */
+ /*------------------------------------------------------------------------------------*/
+ ed->Info = ed_make_info(udev, NULL);
+ if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT)
+ info = (TD_CC | TD_DP_IN | TD_T_DATA1 | TD_TYPE_CTRL);
+ else
+ info = (TD_CC | TD_DP_OUT | TD_T_DATA1 | TD_TYPE_CTRL);
+
+ write_td(td_status, info, NULL, 0);
+ td_status->ed = ed;
+ td_status->NextTD = 0;
+ td_status->next = 0;
+
+ /*------------------------------------------------------------------------------------*/
+ /* prepare ED */
+ /*------------------------------------------------------------------------------------*/
+ ed->TailP = 0;
+ ed->HeadP = (uint32_t)td_setup;
+ ed->Info = ed_make_info(udev, NULL);
+ ed->NextED = 0;
+
+ //TD_debug("TD SETUP [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_setup, td_setup->Info, td_setup->CBP, td_setup->BE, td_setup->NextTD);
+ //if (td_data)
+ // TD_debug("TD DATA [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_data, td_data->Info, td_data->CBP, td_data->BE, td_data->NextTD);
+ //TD_debug("TD STATUS [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_status, td_status->Info, td_status->CBP, td_status->BE, td_status->NextTD);
+ ED_debug("Xfer ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED);
+
+ if (utr->data_len > 0)
+ utr->td_cnt = 3;
+ else
+ utr->td_cnt = 2;
+
+ utr->ep = &udev->ep0; /* driver can find EP from UTR */
+ udev->ep0.hw_pipe = (void *)ed; /* driver can find ED from EP */
+
+ /*------------------------------------------------------------------------------------*/
+ /* Start transfer */
+ /*------------------------------------------------------------------------------------*/
+ DISABLE_OHCI_IRQ();
+ _ohci->HcControlHeadED = (uint32_t)ed; /* Link ED to OHCI */
+ _ohci->HcControl |= USBH_HcControl_CLE_Msk; /* enable control list */
+ ENABLE_OHCI_IRQ();
+ _ohci->HcCommandStatus = USBH_HcCommandStatus_CLF_Msk; /* start Control list */
+
+ return 0;
+}
+
+static int ohci_bulk_xfer(UTR_T *utr)
+{
+ UDEV_T *udev = utr->udev;
+ EP_INFO_T *ep = utr->ep;
+ ED_T *ed;
+ TD_T *td, *td_p, *td_list = NULL;
+ uint32_t info;
+ uint32_t data_len, xfer_len;
+ int8_t bIsNewED = 0;
+ uint8_t *buff;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Check if there's uncompleted transfer on this endpoint... */
+ /* Prepare ED */
+ /*------------------------------------------------------------------------------------*/
+ info = ed_make_info(udev, ep);
+
+ /* Check if there's any transfer pending on this endpoint... */
+ ed = (ED_T *)_ohci->HcBulkHeadED; /* get the head of bulk endpoint list */
+ while (ed != NULL)
+ {
+ if (ed->Info == info) /* have transfer of this EP not completed? */
+ {
+ if ((ed->HeadP & 0xFFFFFFF0) != (ed->TailP & 0xFFFFFFF0))
+ return USBH_ERR_OHCI_EP_BUSY; /* endpoint is busy */
+ else
+ break; /* ED already there... */
+ }
+ ed = (ED_T *)ed->NextED;
+ }
+
+ if (ed == NULL)
+ {
+ bIsNewED = 1;
+ ed = alloc_ohci_ED(); /* allocate an Endpoint Descriptor */
+ if (ed == NULL)
+ return USBH_ERR_MEMORY_OUT;
+ ed->Info = info;
+ ed->HeadP = 0;
+ ED_debug("Link BULK ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED);
+ }
+
+ ep->hw_pipe = (void *)ed;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Prepare TDs */
+ /*------------------------------------------------------------------------------------*/
+ utr->td_cnt = 0;
+ data_len = utr->data_len;
+ buff = utr->buff;
+
+ do
+ {
+ if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT)
+ info = (TD_CC | TD_R | TD_DP_OUT | TD_TYPE_BULK);
+ else
+ info = (TD_CC | TD_R | TD_DP_IN | TD_TYPE_BULK);
+
+ info &= ~(1 << 25); /* Data toggle from ED toggleCarry bit */
+
+ if (data_len > 4096) /* maximum transfer length is 4K for each TD */
+ xfer_len = 4096;
+ else
+ xfer_len = data_len; /* remaining data length < 4K */
+
+ td = alloc_ohci_TD(utr); /* allocate a TD */
+ if (td == NULL)
+ goto mem_out;
+ /* fill this TD */
+ write_td(td, info, buff, xfer_len);
+ td->ed = ed;
+
+ utr->td_cnt++; /* increase TD count, for recalim counter */
+
+ buff += xfer_len; /* advanced buffer pointer */
+ data_len -= xfer_len;
+
+ /* chain to end of TD list */
+ if (td_list == NULL)
+ {
+ td_list = td;
+ }
+ else
+ {
+ td_p = td_list;
+ while (td_p->NextTD != 0)
+ td_p = (TD_T *)td_p->NextTD;
+ td_p->NextTD = (uint32_t)td;
+ }
+
+ }
+ while (data_len > 0);
+
+ /*------------------------------------------------------------------------------------*/
+ /* Start transfer */
+ /*------------------------------------------------------------------------------------*/
+ utr->status = 0;
+ DISABLE_OHCI_IRQ();
+ ed->HeadP = (ed->HeadP & 0x2) | (uint32_t)td_list; /* keep toggleCarry bit */
+ if (bIsNewED)
+ {
+ ed->HeadP = (uint32_t)td_list;
+ /* Link ED to OHCI Bulk List */
+ ed->NextED = _ohci->HcBulkHeadED;
+ _ohci->HcBulkHeadED = (uint32_t)ed;
+ }
+ ENABLE_OHCI_IRQ();
+ _ohci->HcControl |= USBH_HcControl_BLE_Msk; /* enable bulk list */
+ _ohci->HcCommandStatus = USBH_HcCommandStatus_BLF_Msk; /* start bulk list */
+
+ return 0;
+
+mem_out:
+ while (td_list != NULL)
+ {
+ td = td_list;
+ td_list = (TD_T *)td_list->NextTD;
+ free_ohci_TD(td);
+ }
+ free_ohci_ED(ed);
+ return USBH_ERR_MEMORY_OUT;
+}
+
+static int ohci_int_xfer(UTR_T *utr)
+{
+ UDEV_T *udev = utr->udev;
+ EP_INFO_T *ep = utr->ep;
+ ED_T *ed, *ied;
+ TD_T *td, *td_new;
+ uint32_t info;
+ int8_t bIsNewED = 0;
+
+ if (utr->data_len > 64) /* USB 1.1 interrupt transfer maximum packet size is 64 */
+ return USBH_ERR_INVALID_PARAM;
+
+ td_new = alloc_ohci_TD(utr); /* allocate a TD for dummy TD */
+ if (td_new == NULL)
+ return USBH_ERR_MEMORY_OUT;
+
+ ied = get_int_tree_head_node(ep->bInterval); /* get head node of this interval */
+
+ /*------------------------------------------------------------------------------------*/
+ /* Find if this ED was already in the list */
+ /*------------------------------------------------------------------------------------*/
+ info = ed_make_info(udev, ep);
+ ed = ied;
+ while (ed != NULL)
+ {
+ if (ed->Info == info)
+ break; /* Endpoint found */
+ ed = (ED_T *)ed->NextED;
+ }
+
+ if (ed == NULL) /* ED not found, create it */
+ {
+ bIsNewED = 1;
+ ed = alloc_ohci_ED(); /* allocate an Endpoint Descriptor */
+ if (ed == NULL)
+ return USBH_ERR_MEMORY_OUT;
+ ed->Info = info;
+ ed->HeadP = 0;
+ ed->bInterval = ep->bInterval;
+
+ td = alloc_ohci_TD(NULL); /* allocate the initial dummy TD for ED */
+ if (td == NULL)
+ {
+ free_ohci_ED(ed);
+ free_ohci_TD(td_new);
+ return USBH_ERR_MEMORY_OUT;
+ }
+ ed->HeadP = (uint32_t)td; /* Let both HeadP and TailP point to dummy TD */
+ ed->TailP = ed->HeadP;
+ }
+ else
+ {
+ td = (TD_T *)(ed->TailP & ~0xf); /* TailP always point to the dummy TD */
+ }
+ ep->hw_pipe = (void *)ed;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Prepare TD */
+ /*------------------------------------------------------------------------------------*/
+ if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT)
+ info = (TD_CC | TD_R | TD_DP_OUT | TD_TYPE_INT);
+ else
+ info = (TD_CC | TD_R | TD_DP_IN | TD_TYPE_INT);
+
+ /* Keep data toggle */
+ info = (info & ~(1<<25)) | (td->Info & (1<<25));
+
+ /* fill this TD */
+ write_td(td, info, utr->buff, utr->data_len);
+ td->ed = ed;
+ td->NextTD = (uint32_t)td_new;
+ td->utr = utr;
+ utr->td_cnt = 1; /* increase TD count, for recalim counter */
+ utr->status = 0;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Hook ED and TD list to HCCA interrupt table */
+ /*------------------------------------------------------------------------------------*/
+ DISABLE_OHCI_IRQ();
+
+ ed->TailP = (uint32_t)td_new;
+ if (bIsNewED)
+ {
+ /* Add to list of the same interval */
+ ed->NextED = ied->NextED;
+ ied->NextED = (uint32_t)ed;
+ }
+
+ ENABLE_OHCI_IRQ();
+
+ //printf("Link INT ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED);
+
+ _ohci->HcControl |= USBH_HcControl_PLE_Msk; /* periodic list enable */
+ return 0;
+}
+
+static int ohci_iso_xfer(UTR_T *utr)
+{
+ UDEV_T *udev = utr->udev;
+ EP_INFO_T *ep = utr->ep;
+ ED_T *ed, *ied;
+ TD_T *td, *td_list, *last_td;
+ int i;
+ uint32_t info;
+ uint32_t buff_addr;
+ int8_t bIsNewED = 0;
+
+ ied = get_int_tree_head_node(ep->bInterval); /* get head node of this interval */
+
+ /*------------------------------------------------------------------------------------*/
+ /* Find if this ED was already in the list */
+ /*------------------------------------------------------------------------------------*/
+ info = ed_make_info(udev, ep);
+ ed = ied;
+ while (ed != NULL)
+ {
+ if (ed->Info == info)
+ break; /* Endpoint found */
+ ed = (ED_T *)ed->NextED;
+ }
+
+ if (ed == NULL) /* ED not found, create it */
+ {
+ bIsNewED = 1;
+ ed = alloc_ohci_ED(); /* allocate an Endpoint Descriptor */
+ if (ed == NULL)
+ return USBH_ERR_MEMORY_OUT;
+ ed->Info = info;
+ ed->HeadP = 0;
+ ed->bInterval = ep->bInterval;
+ }
+ else
+
+ ep->hw_pipe = (void *)ed;
+
+ /*------------------------------------------------------------------------------------*/
+ /* Prepare TDs */
+ /*------------------------------------------------------------------------------------*/
+ if (utr->bIsoNewSched) /* Is the starting of isochronous streaming? */
+ ed->next_sf = _hcca.frame_no + OHCI_ISO_DELAY;
+
+ utr->td_cnt = 0;
+ utr->iso_sf = ed->next_sf;
+
+ last_td = NULL;
+ td_list = NULL;
+
+ for (i = 0; i < IF_PER_UTR; i++)
+ {
+ utr->iso_status[i] = USBH_ERR_NOT_ACCESS1;
+
+ td = alloc_ohci_TD(utr); /* allocate a TD */
+ if (td == NULL)
+ goto mem_out;
+ /* fill this TD */
+ buff_addr = (uint32_t)(utr->iso_buff[i]);
+ td->Info = (TD_CC | TD_TYPE_ISO) | ed->next_sf;
+ ed->next_sf += get_ohci_interval(ed->bInterval);
+ td->CBP = buff_addr & ~0xFFF;
+ td->BE = buff_addr + utr->iso_xlen[i] - 1;
+ td->PSW[0] = 0xE000 | (buff_addr & 0xFFF);
+
+ td->ed = ed;
+ utr->td_cnt++; /* increase TD count, for reclaim counter */
+
+ /* chain to end of TD list */
+ if (td_list == NULL)
+ td_list = td;
+ else
+ last_td->NextTD = (uint32_t)td;
+
+ last_td = td;
+ };
+
+ /*------------------------------------------------------------------------------------*/
+ /* Hook ED and TD list to HCCA interrupt table */
+ /*------------------------------------------------------------------------------------*/
+ utr->status = 0;
+ DISABLE_OHCI_IRQ();
+
+ if ((ed->HeadP & ~0x3) == 0)
+ ed->HeadP = (ed->HeadP & 0x2) | (uint32_t)td_list; /* keep toggleCarry bit */
+ else
+ {
+ /* find the tail of TDs under this ED */
+ td = (TD_T *)(ed->HeadP & ~0x3);
+ while (td->NextTD != 0)
+ {
+ td = (TD_T *)td->NextTD;
+ }
+ td->NextTD = (uint32_t)td_list;
+ }
+
+ if (bIsNewED)
+ {
+ /* Add to list of the same interval */
+ ed->NextED = ied->NextED;
+ ied->NextED = (uint32_t)ed;
+ }
+
+ ENABLE_OHCI_IRQ();
+ ED_debug("Link ISO ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED);
+ _ohci->HcControl |= USBH_HcControl_PLE_Msk | USBH_HcControl_IE_Msk; /* enable periodic list and isochronous transfer */
+
+ return 0;
+
+mem_out:
+ while (td_list != NULL)
+ {
+ td = td_list;
+ td_list = (TD_T *)td_list->NextTD;
+ free_ohci_TD(td);
+ }
+ free_ohci_ED(ed);
+ return USBH_ERR_MEMORY_OUT;
+}
+
+static UDEV_T * ohci_find_device_by_port(int port)
+{
+ UDEV_T *udev;
+
+ udev = g_udev_list;
+ while (udev != NULL)
+ {
+ if ((udev->parent == NULL) && (udev->port_num == port) &&
+ ((udev->speed == SPEED_LOW) || (udev->speed == SPEED_FULL)))
+ return udev;
+ udev = udev->next;
+ }
+ return NULL;
+}
+
+static int ohci_rh_port_reset(int port)
+{
+ int retry;
+ int reset_time;
+ uint32_t t0;
+
+ reset_time = usbh_tick_from_millisecond(PORT_RESET_TIME_MS);
+
+ for (retry = 0; retry < PORT_RESET_RETRY; retry++)
+ {
+ _ohci->HcRhPortStatus[port] = USBH_HcRhPortStatus_PRS_Msk;
+
+ t0 = usbh_get_ticks();
+ while (usbh_get_ticks() - t0 < (reset_time)+1)
+ {
+ /*
+ * If device is disconnected or port enabled, we can stop port reset.
+ */
+ if (((_ohci->HcRhPortStatus[port] & USBH_HcRhPortStatus_CCS_Msk) == 0) ||
+ ((_ohci->HcRhPortStatus[port] & (USBH_HcRhPortStatus_PES_Msk | USBH_HcRhPortStatus_CCS_Msk)) == (USBH_HcRhPortStatus_PES_Msk | USBH_HcRhPortStatus_CCS_Msk)))
+ goto port_reset_done;
+ }
+ reset_time += PORT_RESET_RETRY_INC_MS;
+ }
+
+ USB_debug("OHCI port %d - port reset failed!\n", port+1);
+ return USBH_ERR_PORT_RESET;
+
+port_reset_done:
+ if ((_ohci->HcRhPortStatus[port] & USBH_HcRhPortStatus_CCS_Msk) == 0) /* check again if device disconnected */
+ {
+ _ohci->HcRhPortStatus[port] = USBH_HcRhPortStatus_CSC_Msk; /* clear CSC */
+ return USBH_ERR_DISCONNECTED;
+ }
+ return USBH_OK; /* port reset success */
+}
+
+static int ohci_rh_polling(void)
+{
+ int i, change = 0;
+ UDEV_T *udev;
+ int ret;
+
+ for (i = 0; i < 2; i++)
+ {
+ if (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) && (i == 0))
+ continue; /* M480LD OHCI has no root hub port 0 */
+
+ /* clear unwanted port change status */
+ _ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_OCIC_Msk | USBH_HcRhPortStatus_PRSC_Msk |
+ USBH_HcRhPortStatus_PSSC_Msk | USBH_HcRhPortStatus_PESC_Msk;
+
+ if ((_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_CSC_Msk) == 0)
+ continue;
+
+ /*--------------------------------------------------------------------------------*/
+ /* connect status change */
+ /*--------------------------------------------------------------------------------*/
+
+ _ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_CSC_Msk; /* clear CSC */
+
+ if (_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_CCS_Msk)
+ {
+ /*----------------------------------------------------------------------------*/
+ /* First of all, check if there's any previously connected device. */
+ /*----------------------------------------------------------------------------*/
+ while (1)
+ {
+ udev = ohci_find_device_by_port(i+1);
+ if (udev == NULL)
+ break;
+ usbh_disconnect_device(udev);
+ }
+
+ if (ohci_rh_port_reset(i) != USBH_OK)
+ continue;
+
+ /*
+ * Port reset success...
+ */
+ udev = alloc_device();
+ if (udev == NULL)
+ continue;
+
+ udev->parent = NULL;
+ udev->port_num = i+1;
+ if (_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_LSDA_Msk)
+ udev->speed = SPEED_LOW;
+ else
+ udev->speed = SPEED_FULL;
+ udev->hc_driver = &ohci_driver;
+
+ ret = usbh_connect_device(udev);
+ if (ret < 0)
+ {
+ USB_error("connect_device error! [%d]\n", ret);
+ free_device(udev);
+ }
+
+ change = 1;
+ }
+ else
+ {
+ /*
+ * Device disconnected
+ */
+ while (1)
+ {
+ udev = ohci_find_device_by_port(i+1);
+ if (udev == NULL)
+ break;
+ usbh_disconnect_device(udev);
+ }
+ change = 1;
+ }
+ }
+ return change;
+}
+
+void td_done(TD_T *td)
+{
+ UTR_T *utr = td->utr;
+ uint32_t info;
+ int cc;
+
+ info = td->Info;
+
+ TD_debug("td_done: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td, td->Info, td->CBP, td->NextTD, td->BE);
+
+ /* ISO ... drivers see per-TD length/status */
+ if ((info & TD_TYPE_Msk) == TD_TYPE_ISO)
+ {
+ uint16_t sf;
+ int idx;
+
+ sf = info & 0xFFFF;
+ idx = ((sf + 0x10000 - utr->iso_sf) & 0xFFFF) / get_ohci_interval(td->ed->bInterval);
+ if (idx >= IF_PER_UTR)
+ {
+ USB_error("ISO invalid index!! %d, %d\n", sf, utr->iso_sf);
+ goto td_out;
+ }
+
+ cc = (td->PSW[0] >> 12) & 0xF;
+ if (cc == 0xF) /* this frame was not transferred */
+ {
+ USB_debug("ISO F %d N/A!\n", sf);
+ utr->iso_status[idx] = USBH_ERR_SCH_OVERRUN;
+ goto td_out;
+ }
+ if ((cc != 0) && (cc != CC_DATA_UNDERRUN))
+ {
+ utr->iso_status[idx] = USBH_ERR_CC_NO_ERR - cc;
+ goto td_out;
+ }
+ utr->iso_status[idx] = 0;
+ utr->iso_xlen[idx] = td->PSW[0] & 0x7FF;
+ }
+ else
+ {
+ cc = TD_CC_GET(info);
+
+ /* short packet is fine */
+ if ((cc != CC_NOERROR) && (cc != CC_DATA_UNDERRUN))
+ {
+ USB_error("TD error, CC = 0x%x\n", cc);
+ if (cc == CC_STALL)
+ utr->status = USBH_ERR_STALL;
+ else
+ utr->status = USBH_ERR_TRANSFER;
+ }
+
+ switch (info & TD_TYPE_Msk)
+ {
+ case TD_TYPE_CTRL:
+ if (info & TD_CTRL_DATA)
+ {
+ if (td->CBP == 0)
+ utr->xfer_len += td->BE - td->buff_start + 1;
+ else
+ utr->xfer_len += td->CBP - td->buff_start;
+ }
+ break;
+
+ case TD_TYPE_BULK:
+ case TD_TYPE_INT:
+ if (td->CBP == 0)
+ utr->xfer_len += td->BE - td->buff_start + 1;
+ else
+ utr->xfer_len += td->CBP - td->buff_start;
+ break;
+ }
+ }
+
+td_out:
+
+ utr->td_cnt--;
+
+ /* If all TDs are done, call-back to requester. */
+ if (utr->td_cnt == 0)
+ {
+ utr->bIsTransferDone = 1;
+ if (utr->func)
+ utr->func(utr);
+ }
+}
+
+/* in IRQ context */
+static void remove_ed()
+{
+ ED_T *ed, *ed_p, *ied;
+ TD_T *td, *td_next;
+ UTR_T *utr;
+ int found;
+
+ while (ed_remove_list != NULL)
+ {
+ ED_debug("Remove ED: 0x%x, %d\n", (int)ed_remove_list, ed_remove_list->bInterval);
+ ed_p = ed_remove_list;
+ found = 0;
+
+ /*--------------------------------------------------------------------------------*/
+ /* Remove endpoint from Control List if found */
+ /*--------------------------------------------------------------------------------*/
+ if ((ed_p->Info & ED_EP_ADDR_Msk) == 0)
+ {
+ if (_ohci->HcControlHeadED == (uint32_t)ed_p)
+ {
+ _ohci->HcControlHeadED = (uint32_t)ed_p->NextED;
+ found = 1;
+ }
+ else
+ {
+ ed = (ED_T *)_ohci->HcControlHeadED;
+ while (ed != NULL)
+ {
+ if (ed->NextED == (uint32_t)ed_p)
+ {
+ ed->NextED = ed_p->NextED;
+ found = 1;
+ }
+ ed = (ED_T *)ed->NextED;
+ }
+ }
+ }
+
+ /*--------------------------------------------------------------------------------*/
+ /* Remove INT or ISO endpoint from HCCA interrupt table */
+ /*--------------------------------------------------------------------------------*/
+ else if (ed_p->bInterval > 0)
+ {
+ ied = get_int_tree_head_node(ed_p->bInterval);
+
+ ed = ied;
+ while (ed != NULL)
+ {
+ if (ed->NextED == (uint32_t)ed_p)
+ {
+ ed->NextED = ed_p->NextED;
+ found = 1;
+ break;
+ }
+ ed = (ED_T *)ed->NextED;
+ }
+ }
+
+ /*--------------------------------------------------------------------------------*/
+ /* Remove endpoint from Bulk List if found */
+ /*--------------------------------------------------------------------------------*/
+ else
+ {
+ if (_ohci->HcBulkHeadED == (uint32_t)ed_p)
+ {
+ ed = (ED_T *)ed_p;
+ _ohci->HcBulkHeadED = ed_p->NextED;
+ found = 1;
+ }
+ else
+ {
+ ed = (ED_T *)_ohci->HcBulkHeadED;
+ while (ed != NULL)
+ {
+ if (ed->NextED == (uint32_t)ed_p)
+ {
+ ed->NextED = ed_p->NextED;
+ found = 1;
+ }
+ ed = (ED_T *)ed->NextED;
+ }
+ }
+ }
+
+ /*--------------------------------------------------------------------------------*/
+ /* Remove and free all TDs under this endpoint */
+ /*--------------------------------------------------------------------------------*/
+ if (found)
+ {
+ td = (TD_T *)(ed_p->HeadP & ~0x3);
+ if (td != NULL)
+ {
+ while (td != NULL)
+ {
+ utr = td->utr;
+ td_next = (TD_T *)td->NextTD;
+ free_ohci_TD(td);
+ td = td_next;
+
+ utr->td_cnt--;
+ if (utr->td_cnt == 0)
+ {
+ utr->status = USBH_ERR_ABORT;
+ utr->bIsTransferDone = 1;
+ if (utr->func)
+ utr->func(utr);
+ }
+ }
+ }
+ }
+
+ /*
+ * Done. Remove this ED from [ed_remove_list] and free it.
+ */
+ ed_remove_list = ed_p->next;
+ free_ohci_ED(ed_p);
+ }
+}
+
+
+//static irqreturn_t ohci_irq (struct usb_hcd *hcd)
+void OHCI_IRQHandler(void)
+{
+ TD_T *td, *td_prev, *td_next;
+ uint32_t int_sts;
+
+ int_sts = _ohci->HcInterruptStatus;
+
+ //USB_debug("ohci int_sts = 0x%x\n", int_sts);
+
+ if ((_ohci->HcInterruptEnable & USBH_HcInterruptEnable_SF_Msk) &&
+ (int_sts & USBH_HcInterruptStatus_SF_Msk))
+ {
+ int_sts &= ~USBH_HcInterruptStatus_SF_Msk;
+
+ _ohci->HcInterruptDisable = USBH_HcInterruptDisable_SF_Msk;
+ remove_ed();
+ _ohci->HcInterruptStatus = USBH_HcInterruptStatus_SF_Msk;
+ }
+
+ if (int_sts & USBH_HcInterruptStatus_WDH_Msk)
+ {
+ //printf("!%02x\n", _ohci->HcFmNumber & 0xff);
+ int_sts &= ~USBH_HcInterruptStatus_WDH_Msk;
+ /*
+ * reverse done list
+ */
+ td = (TD_T *)(_hcca.done_head & TD_ADDR_MASK);
+ _hcca.done_head = 0;
+ td_prev = NULL;
+ _ohci->HcInterruptStatus = USBH_HcInterruptStatus_WDH_Msk;
+
+ while (td != NULL)
+ {
+ //TD_debug("Done list TD 0x%x => 0x%x\n", (int)td, (int)td->NextTD);
+ td_next = (TD_T *)(td->NextTD & TD_ADDR_MASK);
+ td->NextTD = (uint32_t)td_prev;
+ td_prev = td;
+ td = td_next;
+ }
+ td = td_prev; /* first TD of the reversed done list */
+
+ /*
+ * reclaim TDs
+ */
+ while (td != NULL)
+ {
+ TD_debug("Reclaim TD 0x%x, next 0x%x\n", (int)td, td->NextTD);
+ td_next = (TD_T *)td->NextTD;
+ td_done(td);
+ free_ohci_TD(td);
+ td = td_next;
+ }
+ }
+
+ if (int_sts & USBH_HcInterruptStatus_RHSC_Msk)
+ {
+ _ohci->HcInterruptDisable = USBH_HcInterruptDisable_RHSC_Msk;
+ }
+
+ _ohci->HcInterruptStatus = int_sts;
+}
+
+#ifdef ENABLE_DEBUG_MSG
+
+void dump_ohci_int_table()
+{
+ int i;
+ ED_T *ed;
+
+ for (i = 0; i < 32; i++)
+// for (i = 0; i < 1; i++)
+
+ {
+ USB_debug("%02d: ", i);
+
+ ed = (ED_T *)_hcca.int_table[i];
+
+ while (ed != NULL)
+ {
+ USB_debug("0x%x (0x%x) => ", (int)ed, ed->HeadP);
+ ed = (ED_T *)ed->NextED;
+ }
+ rt_kprintf("0\n");
+ }
+}
+
+void dump_ohci_regs()
+{
+ USB_debug("Dump OCHI registers:\n");
+ USB_debug(" HcRevision = 0x%x\n", _ohci->HcRevision);
+ USB_debug(" HcControl = 0x%x\n", _ohci->HcControl);
+ USB_debug(" HcCommandStatus = 0x%x\n", _ohci->HcCommandStatus);
+ USB_debug(" HcInterruptStatus = 0x%x\n", _ohci->HcInterruptStatus);
+ USB_debug(" HcInterruptEnable = 0x%x\n", _ohci->HcInterruptEnable);
+ USB_debug(" HcInterruptDisable = 0x%x\n", _ohci->HcInterruptDisable);
+ USB_debug(" HcHCCA = 0x%x\n", _ohci->HcHCCA);
+ USB_debug(" HcPeriodCurrentED = 0x%x\n", _ohci->HcPeriodCurrentED);
+ USB_debug(" HcControlHeadED = 0x%x\n", _ohci->HcControlHeadED);
+ USB_debug(" HcControlCurrentED = 0x%x\n", _ohci->HcControlCurrentED);
+ USB_debug(" HcBulkHeadED = 0x%x\n", _ohci->HcBulkHeadED);
+ USB_debug(" HcBulkCurrentED = 0x%x\n", _ohci->HcBulkCurrentED);
+ USB_debug(" HcDoneHead = 0x%x\n", _ohci->HcDoneHead);
+ USB_debug(" HcFmInterval = 0x%x\n", _ohci->HcFmInterval);
+ USB_debug(" HcFmRemaining = 0x%x\n", _ohci->HcFmRemaining);
+ USB_debug(" HcFmNumber = 0x%x\n", _ohci->HcFmNumber);
+ USB_debug(" HcPeriodicStart = 0x%x\n", _ohci->HcPeriodicStart);
+ USB_debug(" HcLSThreshold = 0x%x\n", _ohci->HcLSThreshold);
+ USB_debug(" HcRhDescriptorA = 0x%x\n", _ohci->HcRhDescriptorA);
+ USB_debug(" HcRhDescriptorB = 0x%x\n", _ohci->HcRhDescriptorB);
+ USB_debug(" HcRhStatus = 0x%x\n", _ohci->HcRhStatus);
+ USB_debug(" HcRhPortStatus0 = 0x%x\n", _ohci->HcRhPortStatus[0]);
+ USB_debug(" HcRhPortStatus1 = 0x%x\n", _ohci->HcRhPortStatus[1]);
+ USB_debug(" HcPhyControl = 0x%x\n", _ohci->HcPhyControl);
+ USB_debug(" HcMiscControl = 0x%x\n", _ohci->HcMiscControl);
+}
+
+void dump_ohci_ports()
+{
+ USB_debug("_ohci port0=0x%x, port1=0x%x\n", _ohci->HcRhPortStatus[0], _ohci->HcRhPortStatus[1]);
+}
+
+#endif // ENABLE_DEBUG_MSG
+
+HC_DRV_T ohci_driver =
+{
+ ohci_init, /* init */
+ ohci_shutdown, /* shutdown */
+ ohci_suspend, /* suspend */
+ ohci_resume, /* resume */
+ ohci_ctrl_xfer, /* ctrl_xfer */
+ ohci_bulk_xfer, /* bulk_xfer */
+ ohci_int_xfer, /* int_xfer */
+ ohci_iso_xfer, /* iso_xfer */
+ ohci_quit_xfer, /* quit_xfer */
+ ohci_rh_port_reset, /* rthub_port_reset */
+ ohci_rh_polling /* rthub_polling */
+};
+
+/// @endcond HIDDEN_SYMBOLS
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/src/usb_core.c b/bsp/nuvoton/libraries/m480/USBHostLib/src/usb_core.c
new file mode 100644
index 00000000000..abfb4891c28
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/USBHostLib/src/usb_core.c
@@ -0,0 +1,299 @@
+/**************************************************************************//**
+ * @file usb_core.c
+ * @version V1.10
+ * @brief USB Host library core.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include
+#include
+
+#include "NuMicro.h"
+
+#include "usb.h"
+#include "hub.h"
+
+/// @cond HIDDEN_SYMBOLS
+
+USBH_T *_ohci;
+HSUSBH_T *_ehci;
+
+static UDEV_DRV_T * _drivers[MAX_UDEV_DRIVER];
+static CONN_FUNC *g_conn_func, *g_disconn_func;
+
+/**
+ * @brief Initialize M480 USB Host controller and USB stack.
+ *
+ * @return None.
+ */
+void usbh_core_init()
+{
+ NVIC_DisableIRQ(HSUSBH_IRQn);
+ NVIC_DisableIRQ(USBH_IRQn);
+
+ _ohci = USBH;
+ _ehci = HSUSBH;
+
+ memset(_drivers, 0, sizeof(_drivers));
+
+ g_conn_func = NULL;
+ g_disconn_func = NULL;
+
+// usbh_hub_init();
+
+ if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0) /* Only M480MD has EHCI. */
+ {
+ _ehci->USBPCR0 = 0x160; /* enable PHY 0 */
+ _ehci->USBPCR1 = 0x520; /* enable PHY 1 */
+ }
+
+ usbh_memory_init();
+
+ _ohci->HcMiscControl |= USBH_HcMiscControl_OCAL_Msk; /* Over-current active low */
+ //_ohci->HcMiscControl &= ~USBH_HcMiscControl_OCAL_Msk; /* Over-current active high */
+
+#ifdef ENABLE_OHCI
+ ohci_driver.init();
+ ENABLE_OHCI_IRQ();
+#endif
+
+#ifdef ENABLE_EHCI
+ if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0) /* Only M480MD has EHCI. */
+ {
+ ehci_driver.init();
+ ENABLE_EHCI_IRQ();
+ }
+#endif
+}
+
+/**
+ * @brief Let USB stack polls all root hubs. If there's any hub port
+ * change found, USB stack will manage the hub events in this function call.
+ * In this function, USB stack enumerates newly connected devices and remove staff
+ * of disconnected devices. User's application should periodically invoke this
+ * function.
+ * @return There's hub port change or not.
+ * @retval 0 No any hub port status changes found.
+ * @retval 1 There's hub port status changes.
+ */
+int usbh_pooling_root_hubs(void)
+{
+ int ret, change = 0;
+
+#ifdef ENABLE_EHCI
+ if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0) /* Only M480MD has EHCI. */
+ {
+ _ehci->UPSCR[1] = HSUSBH_UPSCR_PP_Msk | HSUSBH_UPSCR_PO_Msk; /* set port 2 owner to OHCI */
+ do
+ {
+ ret = ehci_driver.rthub_polling();
+ if (ret)
+ change = 1;
+ }
+ while (ret == 1);
+ }
+#endif
+
+#ifdef ENABLE_OHCI
+ do
+ {
+ ret = ohci_driver.rthub_polling();
+ if (ret)
+ change = 1;
+ }
+ while (ret == 1);
+#endif
+
+ return change;
+}
+
+/**
+ * @brief Force to quit an endpoint transfer.
+ * @param[in] udev The USB device.
+ * @param[in] ep The endpoint to be quit.
+ * @retval 0 Transfer success
+ * @retval < 0 Failed. Refer to error code definitions.
+ */
+int usbh_quit_xfer(UDEV_T *udev, EP_INFO_T *ep)
+{
+ return udev->hc_driver->quit_xfer(NULL, ep);
+}
+
+
+int usbh_connect_device(UDEV_T *udev)
+{
+ usbh_delay_ms(100); /* initially, give 100 ms delay */
+
+ if (g_conn_func)
+ g_conn_func(udev, 0);
+
+ return 0;
+}
+
+
+void usbh_disconnect_device(UDEV_T *udev)
+{
+ USB_debug("disconnect device...\n");
+
+ if (g_disconn_func)
+ g_disconn_func(udev, 0);
+
+
+#if 1 //CHECK: Maybe create a new API to quit_xfer and free udev for application
+ usbh_quit_xfer(udev, &(udev->ep0)); /* Quit control transfer if hw_pipe is not NULL. */
+
+ /* remove device from global device list */
+// free_dev_address(udev->dev_num);
+ free_device(udev);
+
+// usbh_memory_used();
+#endif
+}
+
+/**
+ * @brief Install device connect and disconnect callback function.
+ *
+ * @param[in] conn_func Device connect callback function.
+ * @param[in] disconn_func Device disconnect callback function.
+ * @return None.
+ */
+void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func)
+{
+ g_conn_func = conn_func;
+ g_disconn_func = disconn_func;
+}
+
+int usbh_reset_port(UDEV_T *udev)
+{
+ if (udev->parent == NULL)
+ {
+ if (udev->hc_driver)
+ return udev->hc_driver->rthub_port_reset(udev->port_num-1);
+ else
+ return USBH_ERR_NOT_FOUND;
+ }
+ else
+ {
+ return udev->parent->port_reset(udev->parent, udev->port_num);
+ }
+}
+
+
+/**
+ * @brief Force to quit an UTR transfer.
+ * @param[in] utr The UTR transfer to be quit.
+ * @retval 0 Transfer success
+ * @retval < 0 Failed. Refer to error code definitions.
+ */
+int usbh_quit_utr(UTR_T *utr)
+{
+ if (!utr || !utr->udev)
+ return USBH_ERR_NOT_FOUND;
+
+ return utr->udev->hc_driver->quit_xfer(utr, NULL);
+}
+
+
+/**
+ * @brief Execute an USB request in control transfer. This function returns after the request
+ * was done or aborted.
+ * @param[in] udev The target USB device.
+ * @param[in] bmRequestType Characteristics of request
+ * @param[in] bRequest Specific request
+ * @param[in] wValue Word-sized field that varies according to request
+ * @param[in] wIndex Word-sized field that varies according to request
+ * @param[in] wLength Number of bytes to transfer if there is a Data stage
+ * @param[in] buff Data buffer used in data stage
+ * @param[out] xfer_len Transmitted/received length of data
+ * @param[in] timeout Time-out limit (in 10ms - timer tick) of this transfer
+ * @retval 0 Transfer success
+ * @retval < 0 Transfer failed. Refer to error code definitions.
+ */
+int usbh_ctrl_xfer(UDEV_T *udev, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
+ uint16_t wLength, uint8_t *buff, uint32_t *xfer_len, uint32_t timeout)
+{
+ UTR_T *utr;
+ uint32_t t0, timeout_tick;
+ int status;
+
+ *xfer_len = 0;
+
+ //if (check_device(udev))
+ // return USBH_ERR_INVALID_PARAM;
+
+ utr = alloc_utr(udev);
+ if (utr == NULL)
+ return USBH_ERR_MEMORY_OUT;
+
+ utr->setup.bmRequestType = bmRequestType;
+ utr->setup.bRequest = bRequest;
+ utr->setup.wValue = wValue;
+ utr->setup.wIndex = wIndex;
+ utr->setup.wLength = wLength;
+
+ utr->buff = buff;
+ utr->data_len = wLength;
+ utr->bIsTransferDone = 0;
+ status = udev->hc_driver->ctrl_xfer(utr);
+ if (status < 0)
+ {
+ udev->ep0.hw_pipe = NULL;
+ free_utr(utr);
+ return status;
+ }
+
+ timeout_tick = usbh_tick_from_millisecond(timeout);
+ t0 = usbh_get_ticks();
+ while (utr->bIsTransferDone == 0)
+ {
+ if (usbh_get_ticks() - t0 > timeout_tick)
+ {
+ usbh_quit_utr(utr);
+ free_utr(utr);
+ udev->ep0.hw_pipe = NULL;
+ return USBH_ERR_TIMEOUT;
+ }
+ }
+
+ status = utr->status;
+
+ if (status == 0)
+ {
+ *xfer_len = utr->xfer_len;
+ }
+ free_utr(utr);
+
+ return status;
+}
+
+/**
+ * @brief Execute a bulk transfer request. This function will return immediately after
+ * issued the bulk transfer. USB stack will later call back utr->func() once the bulk
+ * transfer was done or aborted.
+ * @param[in] utr The bulk transfer request.
+ * @retval 0 Transfer success
+ * @retval < 0 Failed. Refer to error code definitions.
+ */
+int usbh_bulk_xfer(UTR_T *utr)
+{
+ return utr->udev->hc_driver->bulk_xfer(utr);
+}
+
+/**
+ * @brief Execute an interrupt transfer request. This function will return immediately after
+ * issued the interrupt transfer. USB stack will later call back utr->func() once the
+ * interrupt transfer was done or aborted.
+ * @param[in] utr The interrupt transfer request.
+ * @retval 0 Transfer success
+ * @retval < 0 Failed. Refer to error code definitions.
+ */
+int usbh_int_xfer(UTR_T *utr)
+{
+ return utr->udev->hc_driver->int_xfer(utr);
+}
+
+
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/Kconfig b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig
new file mode 100644
index 00000000000..262776534d3
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig
@@ -0,0 +1,937 @@
+config SOC_SERIES_M480
+ bool
+ select ARCH_ARM_CORTEX_M4
+ select SOC_FAMILY_NUMICRO
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+ config BSP_USE_STDDRIVER_SOURCE
+ bool "Build StdDriver source"
+ default n
+
+ menuconfig BSP_USING_PDMA
+ bool "Enable Peripheral Direct Memory Access Controller(PDMA)"
+ default y
+
+ if BSP_USING_PDMA
+ config NU_PDMA_MEMFUN_ACTOR_MAX
+ int "Specify maximum mem actor for memfun"
+ range 1 4
+ default 4
+
+ config NU_PDMA_SGTBL_POOL_SIZE
+ int "Specify maximum scatter-gather pool size"
+ range 1 32
+ default 16
+ endif
+
+ config BSP_USING_FMC
+ bool "Enable Flash Memory Controller(FMC)"
+ select PKG_USING_FAL
+ default n
+
+ config BSP_USING_GPIO
+ bool "Enable General Purpose I/O(GPIO)"
+ select RT_USING_PIN
+ default y
+
+ menuconfig BSP_USING_CLK
+ bool "Enable Clock Controller(CLK)"
+ select RT_USING_PM
+ select BSP_USING_TMR
+ default y
+ help
+ Choose this option if you need CLK/PM function.
+ Notice: Enable the option will hold timer3 resource
+
+ if BSP_USING_CLK
+ config NU_CLK_INVOKE_WKTMR
+ bool "Enable SPD1 and DPD mode wakeup timer. (About 6.6 Secs)"
+ default y
+ endif
+
+ menuconfig BSP_USING_EMAC
+ bool "Enable Ethernet MAC Controller(EMAC)"
+ select RT_USING_LWIP
+ select RT_USING_NETDEV
+
+ config NU_EMAC_PDMA_MEMCOPY
+ bool "Use PDMA for data tranferring"
+ select BSP_USING_PDMA
+ depends on BSP_USING_EMAC
+ default y
+
+ config NU_EMAC_PDMA_MEMCOPY_THRESHOLD
+ int "Min threshold to do PDMA memcpy"
+ range 32 1500
+ default 128
+ depends on NU_EMAC_PDMA_MEMCOPY
+
+ menuconfig BSP_USING_RTC
+ bool "Enable Real Time Clock(RTC)"
+ select RT_USING_RTC
+
+ config NU_RTC_SUPPORT_IO_RW
+ bool "Support device RW entry"
+ depends on BSP_USING_RTC && RT_USING_RTC
+
+ config NU_RTC_SUPPORT_MSH_CMD
+ bool "Support module shell command"
+ depends on BSP_USING_RTC && RT_USING_RTC
+
+ menuconfig BSP_USING_EADC
+ bool "Enable Enhanced Analog-to-Digital Converter(EADC)"
+
+ config BSP_USING_EADC0
+ bool "Enable EADC0"
+ depends on BSP_USING_EADC && RT_USING_ADC
+
+ config BSP_USING_EADC1
+ bool "Enable EADC1"
+ depends on BSP_USING_EADC && RT_USING_ADC
+
+ menuconfig BSP_USING_TMR
+ bool "Enable Timer Controller(TIMER)"
+
+ config BSP_USING_TIMER
+ bool
+
+ config BSP_USING_TPWM
+ bool
+
+ config BSP_USING_TIMER_CAPTURE
+ bool
+
+ config BSP_USING_TMR0
+ bool "Enable TIMER0"
+ depends on BSP_USING_TMR
+
+ if BSP_USING_TMR0
+ choice
+ prompt "Select TIMER0 function mode"
+
+ config BSP_USING_TIMER0
+ select BSP_USING_TIMER
+ select RT_USING_HWTIMER
+ bool "TIMER"
+ help
+ Choose this option if you need TIMER function mode.
+
+ config BSP_USING_TPWM0
+ select BSP_USING_TPWM
+ select RT_USING_PWM
+ bool "TIMER PWM"
+ help
+ Choose this option if you need PWM function mode.
+
+ config BSP_USING_TIMER0_CAPTURE
+ select BSP_USING_TIMER_CAPTURE
+ select RT_USING_INPUT_CAPTURE
+ bool "TIMER CAPTURE"
+ help
+ Choose this option if you need CAPTURE function mode.
+
+ endchoice
+ endif
+
+ config BSP_USING_TMR1
+ bool "Enable TIMER1"
+ depends on BSP_USING_TMR
+
+ if BSP_USING_TMR1
+ choice
+ prompt "Select TIMER1 function mode"
+
+ config BSP_USING_TIMER1
+ select BSP_USING_TIMER
+ select RT_USING_HWTIMER
+ bool "TIMER"
+ help
+ Choose this option if you need TIMER function mode.
+
+ config BSP_USING_TPWM1
+ select BSP_USING_TPWM
+ select RT_USING_PWM
+ bool "TIMER PWM"
+ help
+ Choose this option if you need PWM function mode.
+
+ config BSP_USING_TIMER1_CAPTURE
+ select BSP_USING_TIMER_CAPTURE
+ select RT_USING_INPUT_CAPTURE
+ bool "TIMER CAPTURE"
+ help
+ Choose this option if you need CAPTURE function mode.
+ endchoice
+ endif
+
+ config BSP_USING_TMR2
+ bool "Enable TIMER2"
+ depends on BSP_USING_TMR
+
+ if BSP_USING_TMR2
+ choice
+ prompt "Select TIMER2 function mode"
+
+ config BSP_USING_TIMER2
+ select BSP_USING_TIMER
+ select RT_USING_HWTIMER
+ bool "TIMER"
+ help
+ Choose this option if you need TIMER function mode.
+
+ config BSP_USING_TPWM2
+ select BSP_USING_TPWM
+ select RT_USING_PWM
+ bool "TIMER PWM"
+ help
+ Choose this option if you need PWM function mode.
+
+ config BSP_USING_TIMER2_CAPTURE
+ select BSP_USING_TIMER_CAPTURE
+ select RT_USING_INPUT_CAPTURE
+ bool "TIMER CAPTURE"
+ help
+ Choose this option if you need CAPTURE function mode.
+ endchoice
+ endif
+
+ config BSP_USING_TMR3
+ bool "Enable TIMER3"
+ depends on BSP_USING_TMR && !BSP_USING_CLK
+
+ if BSP_USING_TMR3
+ choice
+ prompt "Select TIMER3 function mode"
+
+ config BSP_USING_TIMER3
+ select BSP_USING_TIMER
+ select RT_USING_HWTIMER
+ bool "TIMER"
+ help
+ Choose this option if you need TIMER function mode.
+
+ config BSP_USING_TPWM3
+ select BSP_USING_TPWM
+ select RT_USING_PWM
+ bool "TIMER PWM"
+ help
+ Choose this option if you need PWM function mode.
+
+ config BSP_USING_TIMER3_CAPTURE
+ select BSP_USING_TIMER_CAPTURE
+ select RT_USING_INPUT_CAPTURE
+ bool "TIMER CAPTURE"
+ help
+ Choose this option if you need CAPTURE function mode.
+ endchoice
+ endif
+
+ menuconfig BSP_USING_UART
+ bool "Enable Universal Asynchronous Receiver/Transmitters(UART)"
+ select RT_USING_SERIAL
+
+ if BSP_USING_UART
+ config BSP_USING_UART0
+ bool "Enable UART0"
+
+ config BSP_USING_UART0_TX_DMA
+ bool "Enable UART0 TX DMA"
+ depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART0_RX_DMA
+ bool "Enable UART0 RX DMA"
+ depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART1
+ bool "Enable UART1"
+
+ config BSP_USING_UART1_TX_DMA
+ bool "Enable UART1 TX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART1_RX_DMA
+ bool "Enable UART1 RX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART2
+ bool "Enable UART2"
+
+ config BSP_USING_UART2_TX_DMA
+ bool "Enable UART2 TX DMA"
+ depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART2_RX_DMA
+ bool "Enable UART2 RX DMA"
+ depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART3
+ bool "Enable UART3"
+
+ config BSP_USING_UART3_TX_DMA
+ bool "Enable UART3 TX DMA"
+ depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART3_RX_DMA
+ bool "Enable UART3 RX DMA"
+ depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART4
+ bool "Enable UART4"
+
+ config BSP_USING_UART4_TX_DMA
+ bool "Enable UART4 TX DMA"
+ depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART4_RX_DMA
+ bool "Enable UART4 RX DMA"
+ depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART5
+ bool "Enable UART5"
+
+ config BSP_USING_UART5_TX_DMA
+ bool "Enable UART5 TX DMA"
+ depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART5_RX_DMA
+ bool "Enable UART5 RX DMA"
+ depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART6
+ bool "Enable UART6"
+
+ config BSP_USING_UART6_TX_DMA
+ bool "Enable UART6 TX DMA"
+ depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART6_RX_DMA
+ bool "Enable UART6 RX DMA"
+ depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART7
+ bool "Enable UART7"
+
+ config BSP_USING_UART7_TX_DMA
+ bool "Enable UART7 TX DMA"
+ depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UART7_RX_DMA
+ bool "Enable UART7 RX DMA"
+ depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
+ endif
+
+ menuconfig BSP_USING_I2C
+ bool "Enable I2C Serial Interface Controller(I2C)"
+ select RT_USING_I2C
+
+ if BSP_USING_I2C
+ config BSP_USING_I2C0
+ bool "Enable I2C0"
+
+ config BSP_USING_I2C1
+ bool "Enable I2C1"
+
+ config BSP_USING_I2C2
+ bool "Enable I2C2"
+ endif
+
+ menuconfig BSP_USING_USCI
+ bool "Enable Universal Serial Control Interface Controller(USCI)"
+
+ if BSP_USING_USCI
+
+ config BSP_USING_UUART
+ bool
+
+ config BSP_USING_USPI
+ bool
+
+ config BSP_USING_USPI_PDMA
+ bool
+ default n
+
+ config BSP_USING_UI2C
+ bool
+
+ config BSP_USING_USCI0
+ bool "Enable USCI0"
+
+ if BSP_USING_USCI0
+ choice
+ prompt "Select USCI0 function mode"
+
+ config BSP_USING_UUART0
+ select RT_USING_SERIAL
+ select BSP_USING_UUART
+ bool "UUART0"
+ help
+ Choose this option if you need UART function mode.
+
+ config BSP_USING_UI2C0
+ select RT_USING_I2C
+ bool "UI2C0"
+ help
+ Choose this option if you need I2C function mode.
+
+ config BSP_USING_USPI0
+ select RT_USING_SPI
+ bool "USPI0"
+ help
+ Choose this option if you need SPI function mode.
+ endchoice
+
+ config BSP_USING_UUART0_TX_DMA
+ bool "Enable UUART0 TX DMA"
+ depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UUART0_RX_DMA
+ bool "Enable UUART0 RX DMA"
+ depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_USPI0_PDMA
+ bool "Use PDMA for data tranferring"
+ select BSP_USING_USPI_PDMA
+ depends on BSP_USING_USPI0
+ endif
+
+ config BSP_USING_USCI1
+ bool "Enable USCI1"
+
+ if BSP_USING_USCI1
+ choice
+ prompt "Select USCI1 function mode"
+
+ config BSP_USING_UUART1
+ select RT_USING_SERIAL
+ select BSP_USING_UUART
+ bool "UUART1"
+ help
+ Choose this option if you need UART function mode.
+
+ config BSP_USING_UI2C1
+ select RT_USING_I2C
+ select BSP_USING_UI2C
+ bool "UI2C1"
+ help
+ Choose this option if you need I2C function mode.
+
+ config BSP_USING_USPI1
+ select RT_USING_SPI
+ select BSP_USING_USPI
+ bool "USPI1"
+ help
+ Choose this option if you need SPI function mode.
+ endchoice
+
+ config BSP_USING_UUART1_TX_DMA
+ bool "Enable UUART1 TX DMA"
+ depends on BSP_USING_UUART1 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_UUART1_RX_DMA
+ bool "Enable UUART1 RX DMA"
+ depends on BSP_USING_UUART1 && RT_SERIAL_USING_DMA
+
+ config BSP_USING_USPI1_PDMA
+ bool "Use PDMA for data tranferring"
+ select BSP_USING_USPI_PDMA
+ depends on BSP_USING_USPI1
+ endif
+
+ endif
+
+ menuconfig BSP_USING_SDH
+ bool "Enable Secure Digital Host Controller(SDH)"
+ select RT_USING_DFS
+
+ if BSP_USING_SDH
+ config BSP_USING_SDH0
+ bool "Enable SDH0"
+
+ config BSP_USING_SDH1
+ bool "Enable SDH1"
+
+ config NU_SDH_USING_PDMA
+ bool "Using PDMA"
+ select BSP_USING_PDMA
+
+ config NU_SDH_HOTPLUG
+ bool "Using HOTPLUG"
+ default y
+ endif
+
+ menuconfig BSP_USING_CAN
+ bool "Enable Controller Area Network(CAN)"
+ select RT_USING_CAN
+
+ if BSP_USING_CAN
+ config BSP_USING_CAN0
+ bool "Enable CAN0"
+
+ config BSP_USING_CAN1
+ bool "Enable CAN1"
+ endif
+
+ menuconfig BSP_USING_BPWM
+ bool "Enable Basic PWM Generator and Capture Timer(BPWM)"
+ select RT_USING_PWM
+
+ if BSP_USING_BPWM
+
+ config BSP_USING_BPWM_CAPTURE
+ bool
+
+ choice
+ prompt "Select BPWM0 function mode"
+ config BSP_USING_BPWM0
+ select RT_USING_PWM
+ bool "Enable BPWM0"
+ help
+ Choose this option if you need PWM function mode.
+
+ config BSP_USING_BPWM0_CAPTURE
+ select RT_USING_INPUT_CAPTURE
+ select BSP_USING_BPWM_CAPTURE
+ bool "Enable BPWM0_CAPTURE"
+ help
+ Choose this option if you need PWM capture function mode.
+ endchoice
+
+ if BSP_USING_BPWM0_CAPTURE
+ config BSP_USING_BPWM0_CAPTURE_CHMSK
+ hex "Specify channel mask for BPWM0_CAP channel."
+ range 0 0x3F
+ default 0
+ endif
+
+ choice
+ prompt "Select BPWM1 function mode"
+ config BSP_USING_BPWM1
+ select RT_USING_PWM
+ bool "Enable BPWM1"
+ help
+ Choose this option if you need PWM function mode.
+
+ config BSP_USING_BPWM1_CAPTURE
+ select RT_USING_INPUT_CAPTURE
+ select BSP_USING_BPWM_CAPTURE
+ bool "Enable BPWM1_CAPTURE"
+ help
+ Choose this option if you need PWM capture function mode.
+ endchoice
+
+ if BSP_USING_BPWM1_CAPTURE
+ config BSP_USING_BPWM1_CAPTURE_CHMSK
+ hex "Specify channel mask for BPWM1_CAP channel."
+ range 0 0x3F
+ default 0
+ endif
+
+ endif
+
+ menuconfig BSP_USING_EPWM
+ bool "Enable EPWM Generator and Capture Timer(EPWM)"
+
+ if BSP_USING_EPWM
+
+ config BSP_USING_EPWM_CAPTURE
+ bool
+
+ choice
+ prompt "Select EPWM0 function mode"
+ config BSP_USING_EPWM0
+ select RT_USING_PWM
+ bool "Enable EPWM0"
+ help
+ Choose this option if you need PWM function mode.
+
+ config BSP_USING_EPWM0_CAPTURE
+ select RT_USING_INPUT_CAPTURE
+ select BSP_USING_EPWM_CAPTURE
+ bool "Enable EPWM0_CAPTURE"
+ help
+ Choose this option if you need PWM capture function mode.
+ endchoice
+
+ if BSP_USING_EPWM0_CAPTURE
+ config BSP_USING_EPWM0_CAPTURE_CHMSK
+ hex "Specify channel mask for EPWM0_CAP channel."
+ range 0 0x3F
+ default 0
+ endif
+
+ choice
+ prompt "Select EPWM1 function mode"
+ config BSP_USING_EPWM1
+ select RT_USING_PWM
+ bool "Enable EPWM1"
+ help
+ Choose this option if you need PWM function mode.
+
+ config BSP_USING_EPWM1_CAPTURE
+ select RT_USING_INPUT_CAPTURE
+ select BSP_USING_EPWM_CAPTURE
+ bool "Enable EPWM1_CAPTURE"
+ help
+ Choose this option if you need PWM capture function mode.
+ endchoice
+
+ if BSP_USING_EPWM1_CAPTURE
+ config BSP_USING_EPWM1_CAPTURE_CHMSK
+ hex "Specify channel mask for EPWM1_CAP channel."
+ range 0 0x3F
+ default 0
+ endif
+
+ endif
+
+ menuconfig BSP_USING_SPI
+ bool "Enable Serial Peripheral Interface(SPI)"
+ select RT_USING_SPI
+
+ if BSP_USING_SPI
+ config BSP_USING_SPI_PDMA
+ bool
+ default n
+
+ config BSP_USING_SPII2S
+ bool
+ default n
+
+ choice
+ prompt "Select SPI0 function mode"
+ config BSP_USING_SPI0_NONE
+ bool "NONE"
+ help
+ Choose this option if you need not SPI0.
+
+ config BSP_USING_SPI0
+ bool "Enable SPI0"
+ help
+ Choose this option if you need SPI function mode.
+
+ config BSP_USING_SPII2S0
+ select RT_USING_AUDIO
+ select BSP_USING_SPII2S
+ bool "Enable SPII2S0"
+ help
+ Choose this option if you need SPII2S function mode.
+ endchoice
+
+ if BSP_USING_SPI0
+ config BSP_USING_SPI0_PDMA
+ bool "Enable PDMA for SPI0"
+ select BSP_USING_SPI_PDMA
+ depends on BSP_USING_SPI0
+ endif
+
+ choice
+ prompt "Select SPI1 function mode"
+ config BSP_USING_SPI1_NONE
+ bool "NONE"
+ help
+ Choose this option if you need not SPI1.
+
+ config BSP_USING_SPI1
+ bool "Enable SPI1"
+ help
+ Choose this option if you need SPI function mode.
+
+ config BSP_USING_SPII2S1
+ select RT_USING_AUDIO
+ select BSP_USING_SPII2S
+ bool "Enable SPII2S1"
+ help
+ Choose this option if you need SPII2S function mode.
+ endchoice
+
+ if BSP_USING_SPI1
+ config BSP_USING_SPI1_PDMA
+ bool "Enable PDMA for SPI1"
+ select BSP_USING_SPI_PDMA
+ depends on BSP_USING_SPI1
+ endif
+
+ choice
+ prompt "Select SPI2 function mode"
+ config BSP_USING_SPI2_NONE
+ bool "NONE"
+ help
+ Choose this option if you need not SPI2.
+
+ config BSP_USING_SPI2
+ bool "Enable SPI2"
+ help
+ Choose this option if you need SPI function mode.
+
+ config BSP_USING_SPII2S2
+ select RT_USING_AUDIO
+ select BSP_USING_SPII2S
+ bool "Enable SPII2S2"
+ help
+ Choose this option if you need SPII2S function mode.
+ endchoice
+
+ if BSP_USING_SPI2
+ config BSP_USING_SPI2_PDMA
+ bool "Enable PDMA for SPI2"
+ select BSP_USING_SPI_PDMA
+ depends on BSP_USING_SPI2
+ endif
+
+ choice
+ prompt "Select SPI3 function mode"
+ config BSP_USING_SPI3_NONE
+ bool "NONE"
+ help
+ Choose this option if you need not SPI3.
+
+ config BSP_USING_SPI3
+ bool "Enable SPI3"
+ help
+ Choose this option if you need SPI function mode.
+
+ config BSP_USING_SPII2S3
+ select RT_USING_AUDIO
+ select BSP_USING_SPII2S
+ bool "Enable SPII2S3"
+ help
+ Choose this option if you need SPII2S function mode.
+ endchoice
+
+ if BSP_USING_SPI3
+ config BSP_USING_SPI3_PDMA
+ bool "Enable PDMA for SPI3"
+ select BSP_USING_SPI_PDMA
+ depends on BSP_USING_SPI3
+ endif
+
+ endif
+
+ config BSP_USING_I2S
+ bool "Enable I2S Controller(I2S)"
+ select RT_USING_AUDIO
+
+ if BSP_USING_I2S || BSP_USING_SPII2S
+ config NU_I2S_DMA_FIFO_SIZE
+ int "DMA Buffer size of capture and playback"
+ range 2048 4096
+ default 2048
+ endif
+
+ menuconfig BSP_USING_QSPI
+ bool "Enable Quad Serial Peripheral Interface(QSPI)"
+ select RT_USING_SPI
+ select RT_USING_QSPI
+
+ if BSP_USING_QSPI
+ config BSP_USING_QSPI0
+ bool "Enable QSPI0"
+
+ config BSP_USING_QSPI0_PDMA
+ bool "Enable PDMA for QSPI0"
+ depends on BSP_USING_QSPI0
+
+ config BSP_USING_QSPI1
+ bool "Enable QSPI1"
+
+ config BSP_USING_QSPI1_PDMA
+ bool "Enable PDMA for QSPI1"
+ depends on BSP_USING_QSPI1
+ endif
+
+ menuconfig BSP_USING_SCUART
+ bool "Enable Smart Card Host Interface - UART(SCUART)"
+
+ if BSP_USING_SCUART
+ config BSP_USING_SCUART0
+ bool "Enable SCUART0"
+
+ config BSP_USING_SCUART1
+ bool "Enable SCUART1"
+
+ config BSP_USING_SCUART2
+ bool "Enable SCUART2"
+ endif
+
+ menuconfig BSP_USING_ECAP
+ bool "Enable Enhanced Input Capture Timer(ECAP)"
+
+ if BSP_USING_ECAP
+
+ config BSP_USING_ECAP0
+ select RT_USING_INPUT_CAPTURE
+ bool "Enable ECAP0"
+ help
+ Choose this option if you need ECAP0.
+
+ if BSP_USING_ECAP0
+ config BSP_USING_ECAP0_CHMSK
+ hex "Specify channel mask for ECAP0 channel."
+ range 0 0x7
+ default 0
+ endif
+
+ config BSP_USING_ECAP1
+ select RT_USING_INPUT_CAPTURE
+ bool "Enable ECAP1"
+ help
+ Choose this option if you need ECAP1.
+
+ if BSP_USING_ECAP1
+ config BSP_USING_ECAP1_CHMSK
+ hex "Specify channel mask for ECAP1 channel."
+ range 0 0x7
+ default 0
+ endif
+
+ endif
+
+ menuconfig BSP_USING_QEI
+ bool "Enable Quadrature Encoder Interface(QEI)"
+
+ if BSP_USING_QEI
+ config BSP_USING_QEI0
+ bool "Enable QEI0"
+ select RT_USING_PULSE_ENCODER
+
+ config BSP_USING_QEI1
+ bool "Enable QEI1"
+ select RT_USING_PULSE_ENCODER
+ endif
+
+ menuconfig BSP_USING_CRYPTO
+ bool "Enable Cryptographic Accelerator(CRYPTO)"
+ select RT_USING_HWCRYPTO
+ select RT_HWCRYPTO_USING_AES
+ select RT_HWCRYPTO_USING_AES_ECB
+ select RT_HWCRYPTO_USING_AES_CBC
+ select RT_HWCRYPTO_USING_AES_CFB
+ select RT_HWCRYPTO_USING_AES_CTR
+ select RT_HWCRYPTO_USING_AES_CFB
+ select RT_HWCRYPTO_USING_AES_OFB
+ select RT_HWCRYPTO_USING_DES
+ select RT_HWCRYPTO_USING_DES_ECB
+ select RT_HWCRYPTO_USING_DES_CBC
+ select RT_HWCRYPTO_USING_3DES
+ select RT_HWCRYPTO_USING_3DES_ECB
+ select RT_HWCRYPTO_USING_3DES_CBC
+ select RT_HWCRYPTO_USING_SHA1
+ select RT_HWCRYPTO_USING_SHA2
+ select RT_HWCRYPTO_USING_SHA2_224
+ select RT_HWCRYPTO_USING_SHA2_256
+ select RT_HWCRYPTO_USING_SHA2_384
+ select RT_HWCRYPTO_USING_SHA2_512
+ select RT_HWCRYPTO_USING_RNG
+
+ if BSP_USING_CRYPTO
+ config NU_PRNG_USE_SEED
+ bool "Use specified seed value."
+ help
+ Specify the seed value to PRNG.
+
+ if NU_PRNG_USE_SEED
+ config NU_PRNG_SEED_VALUE
+ hex "Enter seed value"
+ range 0 0xFFFFFFFF
+ default 0
+ endif
+ endif
+
+ config BSP_USING_TRNG
+ bool "Enable True Random Number Generator(TRNG)"
+ select BSP_USING_CRYPTO
+ select RT_USING_HWCRYPTO
+ select RT_HWCRYPTO_USING_RNG
+
+ menuconfig BSP_USING_CRC
+ bool "Enable Cyclic Redundancy Check Generator(CRC)"
+ select BSP_USING_CRYPTO
+ select RT_USING_HWCRYPTO
+ select RT_HWCRYPTO_USING_CRC
+ select RT_HWCRYPTO_USING_CRC_07
+ select RT_HWCRYPTO_USING_CRC_8005
+ select RT_HWCRYPTO_USING_CRC_1021
+ select RT_HWCRYPTO_USING_CRC_04C11DB7
+
+ if BSP_USING_CRC
+ config NU_CRC_USE_PDMA
+ bool "Use PDMA for data tranferring."
+ select BSP_USING_PDMA
+ default y
+ endif
+
+
+ menuconfig BSP_USING_SOFT_I2C
+ bool "Enable SOFT I2C"
+
+ if BSP_USING_SOFT_I2C
+ config BSP_USING_SOFT_I2C0
+ bool "Enable SOFT I2C0"
+ select RT_USING_I2C
+ select RT_USING_I2C_BITOPS
+ default n
+
+ if BSP_USING_SOFT_I2C0
+ config BSP_SOFT_I2C0_SCL_PIN
+ hex "Specify the pin index of SCL of SOFT I2C0"
+ range 0 0x7F
+ default 0x18
+
+ config BSP_SOFT_I2C0_SDA_PIN
+ hex "Specify the pin index of SDA of SOFT I2C0"
+ range 0 0x7F
+ default 0x17
+ endif
+
+ config BSP_USING_SOFT_I2C1
+ bool "Enable SOFT I2C1"
+ select RT_USING_I2C
+ select RT_USING_I2C_BITOPS
+ default n
+
+ if BSP_USING_SOFT_I2C1
+ config BSP_SOFT_I2C1_SCL_PIN
+ hex "Specify the pin index of SCL of SOFT I2C1"
+ range 0 0x7F
+ default 0x0B
+
+ config BSP_SOFT_I2C1_SDA_PIN
+ hex "Specify the pin index of SDA of SOFT I2C1"
+ range 0 0x7F
+ default 0x0A
+ endif
+ endif
+
+ config BSP_USING_WDT
+ bool "Enable Watchdog Timer(WDT)"
+ select RT_USING_WDT
+ default y
+
+ config BSP_USING_EBI
+ bool "Enable External Bus Interface(EBI)"
+ default n
+
+ config BSP_USING_USBD
+ bool "Enable Full-Speed USB Device Controller(USBD)"
+ select RT_USING_USB_DEVICE
+
+ config BSP_USING_HSUSBD
+ bool "Enable High-Speed USB Device Controller(HSUSBD)"
+ select RT_USING_USB_DEVICE
+
+ config BSP_USING_USBH
+ bool "Enable Full-Speed USB Host Controller(USBH)"
+ select RT_USING_USB_HOST
+ select RT_USBH_MSTORAGE
+
+ config BSP_USING_HSUSBH
+ bool "Enable High-Speed USB Host Controller(HSUSBH)"
+ select RT_USING_USB_HOST
+ select RT_USBH_MSTORAGE
+
+ config BSP_USING_HSOTG
+ bool "Enable High-Speed USB On-The-Go(HSOTG)"
+ select BSP_USING_HSUSBH
+ select BSP_USING_HSUSBD
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/SConscript b/bsp/nuvoton/libraries/m480/rtt_port/SConscript
new file mode 100644
index 00000000000..a155044a304
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/SConscript
@@ -0,0 +1,35 @@
+# RT-Thread building script for component
+
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+group = []
+
+# USB driver constrain
+if GetDepend('BOARD_USING_HSUSBD') and ( GetDepend('BSP_USING_USBD') or GetDepend('BSP_USING_HSUSBH') or GetDepend('BSP_USING_HSOTG') ):
+ print 'Sorry, wrong selection.'
+ print '[Hint] You already select BOARD_USING_HSUSBD. Please de-select BSP_USING_USBD, BSP_USING_HSUSBH and BSP_USING_HSOTG options.'
+ sys.exit(1)
+elif GetDepend('BOARD_USING_HSUSBD_USBH') and ( GetDepend('BSP_USING_USBD') or GetDepend('BSP_USING_HSUSBH') or GetDepend('BSP_USING_HSOTG') ):
+ print 'Sorry, wrong selection.'
+ print '[Hint] You already select BOARD_USING_HSUSBD_USBH. Please de-select BSP_USING_USBD, BSP_USING_HSUSBH and BSP_USING_HSOTG options.'
+ sys.exit(1)
+elif GetDepend('BOARD_USING_HSUSBH') and ( GetDepend('BSP_USING_USBH') or GetDepend('BSP_USING_HSUSBD') or GetDepend('BSP_USING_HSOTG') ):
+ print 'Sorry, wrong selection.'
+ print '[Hint] You already select BOARD_USING_HSUSBH. Please de-select BSP_USING_USBH, BSP_USING_HSUSBD and BSP_USING_HSOTG options.'
+ sys.exit(1)
+elif GetDepend('BOARD_USING_HSUSBH_USBD') and ( GetDepend('BSP_USING_USBH') or GetDepend('BSP_USING_HSUSBD') or GetDepend('BSP_USING_HSOTG') ):
+ print 'Sorry, wrong selection.'
+ print '[Hint] You already select BOARD_USING_HSUSBH_USBD. Please de-select BSP_USING_USBH, BSP_USING_HSUSBD and BSP_USING_HSOTG options.'
+ sys.exit(1)
+elif GetDepend('BOARD_USING_HSOTG') and ( GetDepend('BSP_USING_USBD') or GetDepend('BSP_USING_USBH') ):
+ print 'Sorry, wrong selection.'
+ print '[Hint] You already select BOARD_USING_HSOTG. Please de-select BSP_USING_USBD and BSP_USING_USBH options.'
+ sys.exit(1)
+else:
+ group = DefineGroup('m480_rttport', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm.c
new file mode 100644
index 00000000000..14c0b89479f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm.c
@@ -0,0 +1,228 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-5-22 YHKuo First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_BPWM)
+
+#define LOG_TAG "drv.bpwm"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME LOG_TAG
+#define DBG_LEVEL DBG_INFO
+#define DBG_COLOR
+#include
+
+#include
+#include
+#include
+#include "NuMicro.h"
+
+#define DEFAULT_DUTY 50
+#define DEFAULT_FREQ 1000
+
+enum
+{
+ BPWM_START = -1,
+#if defined(BSP_USING_BPWM0)
+ BPWM0_IDX,
+#endif
+#if defined(BSP_USING_BPWM1)
+ BPWM1_IDX,
+#endif
+ BPWM_CNT
+};
+
+struct nu_bpwm
+{
+ struct rt_device_pwm dev;
+ char *name;
+ BPWM_T *bpwm_base;
+ rt_int32_t pwm_period_time;
+};
+
+typedef struct nu_bpwm *nu_bpwm_t;
+
+static struct nu_bpwm nu_bpwm_arr [] =
+{
+#if defined(BSP_USING_BPWM0)
+ {
+ .name = "bpwm0",
+ .bpwm_base = BPWM0,
+ },
+#endif
+
+#if defined(BSP_USING_BPWM1)
+ {
+ .name = "bpwm1",
+ .bpwm_base = BPWM1,
+ },
+#endif
+ {0}
+}; /* bpwm nu_epwm */
+
+static rt_err_t nu_bpwm_control(struct rt_device_pwm *device, int cmd, void *arg);
+
+static struct rt_pwm_ops nu_bpwm_ops =
+{
+ .control = nu_bpwm_control
+};
+
+static rt_err_t nu_bpwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+ rt_err_t result = RT_EOK;
+
+ BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base;
+ rt_uint32_t pwm_channel = configuration->channel;
+
+ if (enable == RT_TRUE)
+ {
+ BPWM_EnableOutput(pwm_base, 1 << pwm_channel);
+ BPWM_Start(pwm_base, 1 << pwm_channel);
+ }
+ else if (enable == RT_FALSE)
+ {
+ BPWM_DisableOutput(pwm_base, 1 << pwm_channel);
+ BPWM_ForceStop(pwm_base, 1 << pwm_channel);
+ }
+
+ return result;
+}
+
+static rt_err_t nu_bpwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+ if ((configuration->period) <= 0)
+ return -(RT_ERROR);
+ rt_uint32_t pwm_freq, pwm_dutycycle;
+ BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base;
+ rt_uint8_t pwm_channel = configuration->channel;
+ rt_uint32_t pwm_period = configuration->period;
+ rt_uint32_t pwm_pulse = configuration->pulse;
+
+ pwm_dutycycle = (pwm_pulse * 100) / pwm_period;
+
+ if (BPWM_GET_CNR(pwm_base, pwm_channel) != 0)
+ {
+ pwm_period = ((nu_bpwm_t)device)->pwm_period_time;
+ LOG_I("%s output frequency is determined, user can only change the duty\n", ((nu_bpwm_t)device)->name);
+ }
+ else
+ {
+ ((nu_bpwm_t)device)->pwm_period_time = pwm_period;
+ }
+
+ pwm_freq = 1000000000 / pwm_period;
+
+
+ BPWM_ConfigOutputChannel(pwm_base, pwm_channel, pwm_freq, pwm_dutycycle) ;
+
+ return RT_EOK;
+}
+
+static rt_uint32_t nu_bpwm_clksr(struct rt_device_pwm *device)
+{
+ rt_uint32_t u32Src, u32BPWMClockSrc;
+ BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base;
+ if (pwm_base == BPWM0)
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
+ }
+ else /* (bpwm == BPWM1) */
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
+ }
+
+ if (u32Src == 0U)
+ {
+ /* clock source is from PLL clock */
+ u32BPWMClockSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ /* clock source is from PCLK */
+ SystemCoreClockUpdate();
+ if (pwm_base == BPWM0)
+ {
+ u32BPWMClockSrc = CLK_GetPCLK0Freq();
+ }
+ else /* (bpwm == BPWM1) */
+ {
+ u32BPWMClockSrc = CLK_GetPCLK1Freq();
+ }
+ }
+ return u32BPWMClockSrc;
+}
+
+static rt_err_t nu_bpwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+ rt_uint32_t pwm_real_period, pwm_real_duty, time_tick, u32BPWMClockSrc ;
+
+ BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base;
+ rt_uint32_t pwm_channel = configuration->channel;
+ rt_uint32_t pwm_prescale = pwm_base->CLKPSC;
+ rt_uint32_t pwm_period = BPWM_GET_CNR(pwm_base, pwm_channel);
+ rt_uint32_t pwm_pulse = BPWM_GET_CMR(pwm_base, pwm_channel);
+
+ u32BPWMClockSrc = nu_bpwm_clksr(device);
+ time_tick = 1000000000000 / u32BPWMClockSrc;
+
+ pwm_real_period = (((pwm_prescale + 1) * (pwm_period + 1)) * time_tick) / 1000;
+ pwm_real_duty = (((pwm_prescale + 1) * pwm_pulse * time_tick)) / 1000;
+ configuration->period = pwm_real_period;
+ configuration->pulse = pwm_real_duty;
+
+ LOG_I("%s %d %d %d\n", ((nu_bpwm_t)device)->name, configuration->channel, configuration->period, configuration->pulse);
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_bpwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+ struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(configuration != RT_NULL);
+
+ if (((configuration->channel) + 1) > BPWM_CHANNEL_NUM)
+ return -(RT_ERROR);
+
+ switch (cmd)
+ {
+ case PWM_CMD_ENABLE:
+ return nu_bpwm_enable(device, configuration, RT_TRUE);
+ case PWM_CMD_DISABLE:
+ return nu_bpwm_enable(device, configuration, RT_FALSE);
+ case PWM_CMD_SET:
+ return nu_bpwm_set(device, configuration);
+ case PWM_CMD_GET:
+ return nu_bpwm_get(device, configuration);
+ default:
+ return RT_EINVAL;
+ }
+}
+
+int rt_hw_bpwm_init(void)
+{
+ rt_err_t ret;
+ rt_uint8_t i;
+
+ for (i = (BPWM_START + 1); i < BPWM_CNT; i++)
+ {
+ ret = rt_device_pwm_register(&nu_bpwm_arr[i].dev, nu_bpwm_arr[i].name, &nu_bpwm_ops, RT_NULL);
+ RT_ASSERT(ret == RT_EOK);
+ }
+
+ return 0;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_bpwm_init);
+
+#endif
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c
new file mode 100644
index 00000000000..c7235fe7ae2
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c
@@ -0,0 +1,333 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-6-5 Philo First version
+*
+******************************************************************************/
+#include
+
+#if defined(BSP_USING_BPWM_CAPTURE)
+#include
+#include
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct _bpwm_dev
+{
+ BPWM_T *bpwm_base;
+ IRQn_Type irq;
+ float fUsPerTick;
+} nu_bpwm_dev_t;
+
+typedef struct _bpwm
+{
+ struct rt_inputcapture_device parent;
+ nu_bpwm_dev_t *bpwm_dev;
+ uint8_t u8Channel;
+ uint8_t u8DummyData;
+ uint32_t u32CurrentRisingCnt;
+ uint32_t u32CurrentFallingCnt;
+ uint32_t u32LastRisingCnt;
+ uint32_t u32LastFallingCnt;
+ rt_bool_t input_data_level;
+} nu_capture_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture);
+static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture);
+static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture);
+static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us);
+
+/* Private define ---------------------------------------------------------------*/
+#define NU_DUMMY_DATA 2 /* First rising and falling edge should be ignore */
+
+#define NU_NO_EDGE 0
+#define NU_RISING_EDGE 1
+#define NU_FALLING_EDGE 2
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0)
+static const char *nu_bpwm0_device_name[BPWM_CHANNEL_NUM] = { "bpwm0i0", "bpwm0i1", "bpwm0i2", "bpwm0i3", "bpwm0i4", "bpwm0i5"};
+static nu_capture_t *nu_bpwm0_capture[BPWM_CHANNEL_NUM] = {0};
+static nu_bpwm_dev_t nu_bpwm0_dev = {.bpwm_base = BPWM0};
+#endif
+
+#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0)
+static const char *nu_bpwm1_device_name[BPWM_CHANNEL_NUM] = { "bpwm1i0", "bpwm1i1", "bpwm1i2", "bpwm1i3", "bpwm1i4", "bpwm1i5"};
+static nu_capture_t *nu_bpwm1_capture[BPWM_CHANNEL_NUM] = {0};
+static nu_bpwm_dev_t nu_bpwm1_dev = {.bpwm_base = BPWM1};
+#endif
+
+static struct rt_inputcapture_ops nu_capture_ops =
+{
+ .init = nu_capture_init,
+ .open = nu_capture_open,
+ .close = nu_capture_close,
+ .get_pulsewidth = nu_capture_get_pulsewidth,
+};
+
+/* Functions define ------------------------------------------------------------*/
+void bpwm_interrupt_handler(nu_capture_t *nu_capture[], uint32_t u32ChMsk)
+{
+ uint32_t u32Status;
+
+ for (uint8_t i = 0; i < BPWM_CHANNEL_NUM ; i++)
+ {
+ if ((0x1 << i) & u32ChMsk)
+ {
+ if (nu_capture[i]->u8DummyData < NU_DUMMY_DATA)
+ {
+ nu_capture[i]->u8DummyData++;
+ }
+ else
+ {
+ u32Status = BPWM_GetCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel);
+
+ switch (u32Status)
+ {
+ case NU_NO_EDGE:
+ break;
+ case NU_RISING_EDGE:
+ BPWM_ClearCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel, BPWM_CAPTURE_INT_RISING_LATCH);
+ nu_capture[i]->u32CurrentRisingCnt = BPWM_GET_CAPTURE_RISING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel);
+ rt_hw_inputcapture_isr(&nu_capture[i]->parent, nu_capture[i]->input_data_level);
+
+ break;
+ case NU_FALLING_EDGE:
+ BPWM_ClearCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel, BPWM_CAPTURE_INT_FALLING_LATCH);
+ nu_capture[i]->u32CurrentFallingCnt = BPWM_GET_CAPTURE_FALLING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel);
+ rt_hw_inputcapture_isr(&nu_capture[i]->parent, nu_capture[i]->input_data_level);
+
+ break;
+ default:
+ BPWM_ClearCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel, BPWM_CAPTURE_INT_RISING_LATCH | BPWM_CAPTURE_INT_FALLING_LATCH);
+ BPWM_GET_CAPTURE_RISING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel);
+ BPWM_GET_CAPTURE_FALLING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel);
+
+ break;
+ }
+ }
+ }
+ }
+}
+
+#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0)
+void BPWM0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ bpwm_interrupt_handler(nu_bpwm0_capture, BSP_USING_BPWM0_CAPTURE_CHMSK);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif //(BSP_USING_BPWM0_CAPTURE_CHMSK!=0)
+
+#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0)
+void BPWM1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ bpwm_interrupt_handler(nu_bpwm1_capture, BSP_USING_BPWM1_CAPTURE_CHMSK);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif //(BSP_USING_BPWM1_CAPTURE_CHMSK!=0)
+
+static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us)
+{
+ rt_err_t ret = RT_EOK;
+ nu_capture_t *nu_capture;
+ float fTempCnt;
+
+ nu_capture = (nu_capture_t *)inputcapture;
+
+ if (nu_capture->u32CurrentFallingCnt)
+ {
+ if (nu_capture->u32CurrentFallingCnt > nu_capture->u32LastRisingCnt)
+ fTempCnt = nu_capture->u32CurrentFallingCnt - nu_capture->u32LastRisingCnt;
+ else /* Overrun case */
+ fTempCnt = nu_capture->u32CurrentFallingCnt + (0x10000 - nu_capture->u32LastRisingCnt);
+
+ *pulsewidth_us = fTempCnt * nu_capture->bpwm_dev->fUsPerTick;
+ nu_capture->input_data_level = RT_FALSE;
+ nu_capture->u32LastFallingCnt = nu_capture->u32CurrentFallingCnt;
+ nu_capture->u32CurrentFallingCnt = 0;
+ }
+ else if (nu_capture->u32CurrentRisingCnt)
+ {
+ if (nu_capture->u32CurrentRisingCnt > nu_capture->u32LastFallingCnt)
+ fTempCnt = nu_capture->u32CurrentRisingCnt - nu_capture->u32LastFallingCnt;
+ else /* Overrun case */
+ fTempCnt = nu_capture->u32CurrentRisingCnt + (0x10000 - nu_capture->u32LastFallingCnt);
+
+ *pulsewidth_us = fTempCnt * nu_capture->bpwm_dev->fUsPerTick;
+ nu_capture->input_data_level = RT_TRUE;
+ nu_capture->u32LastRisingCnt = nu_capture->u32CurrentRisingCnt;
+ nu_capture->u32CurrentRisingCnt = 0;
+ }
+ else
+ {
+ ret = RT_ERROR;
+ }
+ return -(ret);
+}
+
+static void bpwm_config(nu_capture_t *nu_capture)
+{
+ /* Set capture time as 500 nano second */
+ nu_capture->bpwm_dev->fUsPerTick = (float)BPWM_ConfigCaptureChannel(nu_capture->bpwm_dev->bpwm_base, 0, 500, 0) / 1000;
+
+ /* Enable BPWM NVIC interrupt */
+ NVIC_EnableIRQ(nu_capture->bpwm_dev->irq);
+
+ /* Set counter type as up count */
+ BPWM_SET_ALIGNED_TYPE(nu_capture->bpwm_dev->bpwm_base, 0, BPWM_UP_COUNTER);
+
+ /* Enable BPWM Timer */
+ BPWM_Start(nu_capture->bpwm_dev->bpwm_base, 0);
+}
+
+static rt_err_t nu_bpwm_init(nu_capture_t *nu_capture)
+{
+ rt_err_t ret = RT_ERROR;
+ static rt_bool_t bBPWM0Inited = RT_FALSE;
+ static rt_bool_t bBPWM1Inited = RT_FALSE;
+
+ if (nu_capture->bpwm_dev->bpwm_base == BPWM0)
+ {
+ if (bBPWM0Inited == RT_FALSE)
+ {
+ /* Enable BPWM0 clock */
+ SYS_UnlockReg();
+ CLK_EnableModuleClock(BPWM0_MODULE);
+ CLK_SetModuleClock(BPWM0_MODULE, CLK_CLKSEL2_BPWM0SEL_PLL, (uint32_t)NULL);
+ SYS_LockReg();
+ bpwm_config(nu_capture);
+ bBPWM0Inited = RT_TRUE;
+ }
+ ret = RT_EOK;
+ }
+ else if (nu_capture->bpwm_dev->bpwm_base == BPWM1)
+ {
+ if (bBPWM1Inited == RT_FALSE)
+ {
+ /* Enable BPWM1 clock */
+ SYS_UnlockReg();
+ CLK_EnableModuleClock(BPWM1_MODULE);
+ CLK_SetModuleClock(BPWM1_MODULE, CLK_CLKSEL2_BPWM1SEL_PLL, (uint32_t)NULL);
+ SYS_LockReg();
+ bpwm_config(nu_capture);
+ bBPWM1Inited = RT_TRUE;
+ }
+ ret = RT_EOK;
+ }
+
+ return -(ret);
+}
+
+static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture)
+{
+ rt_err_t ret = RT_EOK;
+ nu_capture_t *nu_capture;
+
+ RT_ASSERT(inputcapture != RT_NULL);
+
+ nu_capture = (nu_capture_t *) inputcapture;
+
+ if (nu_bpwm_init(nu_capture) != RT_EOK)
+ {
+ rt_kprintf("Failed to initialize BPWM.\n");
+ ret = RT_ERROR;
+ }
+
+ return -(ret);
+}
+
+static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture)
+{
+ nu_capture_t *nu_capture;
+
+ RT_ASSERT(inputcapture != RT_NULL);
+
+ nu_capture = (nu_capture_t *) inputcapture;
+
+ /* Enable capture rising/falling edge interrupt */
+ BPWM_EnableCaptureInt(nu_capture->bpwm_dev->bpwm_base, nu_capture->u8Channel, BPWM_CAPTURE_INT_FALLING_LATCH | BPWM_CAPTURE_INT_RISING_LATCH);
+
+ /* Enable Capture Function for BPWM */
+ BPWM_EnableCapture(nu_capture->bpwm_dev->bpwm_base, 0x1 << nu_capture->u8Channel);
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture)
+{
+ nu_capture_t *nu_capture;
+
+ RT_ASSERT(inputcapture != RT_NULL);
+
+ nu_capture = (nu_capture_t *) inputcapture;
+
+ /* Enable Capture Function for BPWM */
+ BPWM_DisableCapture(nu_capture->bpwm_dev->bpwm_base, 0x1 << nu_capture->u8Channel);
+
+ /* Disable capture rising/falling edge interrupt */
+ BPWM_DisableCaptureInt(nu_capture->bpwm_dev->bpwm_base, nu_capture->u8Channel, BPWM_CAPTURE_INT_FALLING_LATCH | BPWM_CAPTURE_INT_RISING_LATCH);
+
+ return RT_EOK;
+}
+
+static void bpwm_init(nu_capture_t *nu_capture, uint8_t u8Channel, nu_bpwm_dev_t *bpwm_dev, const char *device_name, IRQn_Type irq)
+{
+ nu_capture->bpwm_dev = bpwm_dev;
+ nu_capture->bpwm_dev->irq = irq;
+ nu_capture->u8Channel = u8Channel;
+ nu_capture->u8DummyData = 0;
+ nu_capture->u32CurrentFallingCnt = 0;
+ nu_capture->u32CurrentRisingCnt = 0;
+ nu_capture->u32LastRisingCnt = 0;
+ nu_capture->u32LastFallingCnt = 0;
+ nu_capture->parent.ops = &nu_capture_ops;
+
+ /* register inputcapture device */
+ rt_device_inputcapture_register(&nu_capture->parent, device_name, &nu_capture);
+}
+
+/* Init and register bpwm capture */
+static int nu_bpwm_capture_device_init(void)
+{
+ for (int i = 0; i < BPWM_CHANNEL_NUM; i++)
+ {
+#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0)
+ if (BSP_USING_BPWM0_CAPTURE_CHMSK & (0x1 << i))
+ {
+ nu_bpwm0_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t));
+ bpwm_init(nu_bpwm0_capture[i], i, &nu_bpwm0_dev, nu_bpwm0_device_name[i], BPWM0_IRQn);
+ }
+#endif //#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0)
+
+#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0)
+ if (BSP_USING_BPWM1_CAPTURE_CHMSK & (0x1 << i))
+ {
+ nu_bpwm1_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t));
+ bpwm_init(nu_bpwm1_capture[i], i, &nu_bpwm1_dev, nu_bpwm1_device_name[i], BPWM1_IRQn);
+ }
+#endif //#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0)
+ }
+
+ return 0;
+}
+INIT_DEVICE_EXPORT(nu_bpwm_capture_device_init);
+
+#endif //#if defined(BSP_USING_BPWM_CAPTURE)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
new file mode 100644
index 00000000000..f9cc4a97383
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
@@ -0,0 +1,564 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-07 ChingI First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_CAN)
+
+#include
+#include
+#include
+
+/* Private Define ---------------------------------------------------------------*/
+#define RX_MSG_ID_INDEX 16
+#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
+
+/* Default config for serial_configure structure */
+#define NU_CAN_CONFIG_DEFAULT \
+{ \
+ CAN1MBaud, /* 1M bits/s */ \
+ RT_CANMSG_BOX_SZ, /* message box max size */ \
+ RT_CANSND_BOX_NUM, /* message box number */ \
+ RT_CAN_MODE_NORMAL, /* Normal mode */ \
+ 0, /* privmode */ \
+ 0, /* reserved */ \
+ 100, /* Timeout Tick */ \
+}
+
+enum
+{
+ CAN_START = -1,
+#if defined(BSP_USING_CAN0)
+ CAN0_IDX,
+#endif
+#if defined(BSP_USING_CAN1)
+ CAN1_IDX,
+#endif
+#if defined(BSP_USING_CAN2)
+ CAN2_IDX,
+#endif
+ CAN_CNT
+};
+
+/* Private Typedef --------------------------------------------------------------*/
+struct nu_can
+{
+ struct rt_can_device dev;
+ char *name;
+ CAN_T *can_base;
+ uint32_t can_rst;
+ IRQn_Type can_irq_n;
+};
+typedef struct nu_can *nu_can_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure *cfg);
+static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg);
+static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno);
+static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno);
+static void nu_can_isr(nu_can_t can);
+
+static struct nu_can nu_can_arr[] =
+{
+#if defined(BSP_USING_CAN0)
+ {
+ .name = "can0",
+ .can_base = CAN0,
+ .can_rst = CAN0_RST,
+ .can_irq_n = CAN0_IRQn,
+ },
+#endif
+#if defined(BSP_USING_CAN1)
+ {
+ .name = "can1",
+ .can_base = CAN1,
+ .can_rst = CAN1_RST,
+ .can_irq_n = CAN1_IRQn,
+ },
+#endif
+
+#if defined(BSP_USING_CAN2)
+ {
+ .name = "can2",
+ .can_base = CAN2,
+ .can_rst = CAN2_RST,
+ .can_irq_n = CAN2_IRQn,
+ },
+#endif
+ {0}
+}; /* usart nu_usart */
+
+/* Public functions ------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+static const struct rt_can_ops nu_can_ops =
+{
+ .configure = nu_can_configure,
+ .control = nu_can_control,
+ .sendmsg = nu_can_sendmsg,
+ .recvmsg = nu_can_recvmsg,
+};
+
+static const struct can_configure nu_can_default_config = NU_CAN_CONFIG_DEFAULT;
+
+/* Interrupt Handle Funtion ----------------------------------------------------*/
+#if defined(BSP_USING_CAN0)
+/* CAN0 interrupt entry */
+void CAN0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ nu_can_isr(&nu_can_arr[CAN0_IDX]);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_CAN1)
+/* CAN1 interrupt entry */
+void CAN1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ nu_can_isr(&nu_can_arr[CAN1_IDX]);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_CAN2)
+/* CAN2 interrupt entry */
+void CAN2_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ nu_can_isr(&nu_can_arr[CAN2_IDX]);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+
+/* Private Variables ------------------------------------------------------------*/
+
+
+static void nu_can_isr(nu_can_t can)
+{
+ uint32_t u32IIDRstatus;
+ /* Get base address of CAN register */
+ CAN_T *can_base = ((nu_can_t)can)->can_base;
+
+ /* Get interrupt event */
+ u32IIDRstatus = can_base->IIDR;
+
+ if (u32IIDRstatus == 0x00008000) /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+ {
+ /**************************/
+ /* Status Change interrupt*/
+ /**************************/
+ if (can_base->STATUS & CAN_STATUS_RXOK_Msk)
+ {
+
+#ifndef RT_CAN_USING_HDR
+ /* Using as Lisen,Loopback,Loopback+Lisen mode*/
+ rt_hw_can_isr(&can->dev, RT_CAN_EVENT_RX_IND);
+#endif
+ can_base->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/
+ rt_kprintf("RX OK INT\n") ;
+ }
+
+ if (can_base->STATUS & CAN_STATUS_TXOK_Msk)
+ {
+
+#ifndef RT_CAN_USING_HDR
+ /* Using as Lisen,Loopback,Loopback+Lisen mode*/
+ rt_hw_can_isr(&can->dev, RT_CAN_EVENT_TX_DONE);
+#endif
+ can_base->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/
+ rt_kprintf("TX OK INT\n") ;
+ }
+
+ /**************************/
+ /* Error Status interrupt */
+ /**************************/
+ if (can_base->STATUS & CAN_STATUS_EWARN_Msk)
+ {
+ rt_kprintf("EWARN INT\n") ;
+ }
+
+ if (can_base->STATUS & CAN_STATUS_BOFF_Msk)
+ {
+ rt_kprintf("BOFF INT\n") ;
+
+ /* Do Init to release busoff pin */
+ can_base->CON = (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+ can_base->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
+ while (can_base->CON & CAN_CON_INIT_Msk);
+ }
+ }
+#ifdef RT_CAN_USING_HDR
+ /*Number of Message Object which caused the interrupt*/
+ else if (u32IIDRstatus != 0 && u32IIDRstatus <= 32)
+ {
+ rt_kprintf("=> Interrupt Pointer = %d\n", can_base->IIDR - 1);
+ /*Message RAM 0~15 for CAN Tx using*/
+ if (u32IIDRstatus < 16)
+ rt_hw_can_isr(&can->dev, RT_CAN_EVENT_TX_DONE);
+ else /*Message RAM 16~31 for CAN Rx using*/
+ {
+ rt_hw_can_isr(&can->dev, (RT_CAN_EVENT_RX_IND | (((can_base->IIDR) - 1) << 8)));
+ }
+ CAN_CLR_INT_PENDING_BIT(can_base, ((can_base->IIDR) - 1)); /* Clear Interrupt Pending */
+ }
+#endif
+
+}
+
+
+static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure *cfg)
+{
+
+ RT_ASSERT(can != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+
+ /* Get base address of uart register */
+ CAN_T *can_base = ((nu_can_t)can)->can_base;
+
+ RT_ASSERT(can_base != RT_NULL);
+
+ /* Reset this module */
+ SYS_ResetModule(((nu_can_t)can)->can_rst);
+
+ switch (cfg->mode)
+ {
+ /* CAN default Normal mode */
+ case RT_CAN_MODE_NORMAL:
+ can->config.mode = CAN_NORMAL_MODE;
+ break;
+ case RT_CAN_MODE_LISEN:
+ can->config.mode = RT_CAN_MODE_LISEN;
+ break;
+ case RT_CAN_MODE_LOOPBACK:
+ can->config.mode = RT_CAN_MODE_LOOPBACK;
+ break;
+ case RT_CAN_MODE_LOOPBACKANLISEN:
+ can->config.mode = RT_CAN_MODE_LOOPBACKANLISEN;
+ break;
+ default:
+ rt_kprintf("Unsupported Operating mode");
+ goto exit_nu_can_configure;
+ }
+
+ /*Set the CAN Bit Rate and Operating mode*/
+ if (CAN_Open(can_base, can->config.baud_rate, can->config.mode) < 1)
+ return -(RT_ERROR);
+
+
+ switch (cfg->mode)
+ {
+ /* CAN default Normal mode */
+ case RT_CAN_MODE_NORMAL:
+#ifdef RT_CAN_USING_HDR
+ CAN_LeaveTestMode(can_base);
+#else
+ CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk);
+#endif
+ break;
+ case RT_CAN_MODE_LISEN:
+ CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk);
+ break;
+ case RT_CAN_MODE_LOOPBACK:
+ CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_LBACK_Msk);
+ break;
+ case RT_CAN_MODE_LOOPBACKANLISEN:
+ CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
+ break;
+ default:
+ rt_kprintf("Unsupported Operating mode");
+ goto exit_nu_can_configure;
+ }
+
+
+ return RT_EOK;
+
+exit_nu_can_configure:
+
+ CAN_Close(can_base);
+
+ return -(RT_ERROR);
+}
+
+static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
+{
+ rt_uint32_t argval;
+
+#ifdef RT_CAN_USING_HDR
+ struct rt_can_filter_config *filter_cfg;
+#endif
+ /* Get base address of uart register */
+ CAN_T *can_base = ((nu_can_t)can)->can_base;
+
+ RT_ASSERT(can_base != RT_NULL);
+ /* Check baudrate */
+ RT_ASSERT(can->config.baud_rate != 0);
+
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_CLR_INT:
+ argval = (rt_uint32_t) arg;
+ if ((argval == RT_DEVICE_FLAG_INT_RX) || (argval == RT_DEVICE_FLAG_INT_TX))
+ {
+ /* Disable NVIC interrupt. */
+ NVIC_DisableIRQ(((nu_can_t)can)->can_irq_n);
+ /* Disable Status Change Interrupt */
+ CAN_DisableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
+
+ }
+ else if (argval == RT_DEVICE_CAN_INT_ERR)
+ {
+ /* Disable NVIC interrupt. */
+ NVIC_DisableIRQ(((nu_can_t)can)->can_irq_n);
+ /* Disable Error Interrupt */
+ CAN_DisableInt(can_base, CAN_CON_EIE_Msk);
+ }
+ break;
+
+ case RT_DEVICE_CTRL_SET_INT:
+ argval = (rt_uint32_t) arg;
+ if (argval == RT_DEVICE_FLAG_INT_RX || (argval == RT_DEVICE_FLAG_INT_TX))
+ {
+ /* Enable Status Change Interrupt */
+ CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
+ NVIC_SetPriority(((nu_can_t)can)->can_irq_n, (1 << __NVIC_PRIO_BITS) - 2);
+ /* Enable NVIC interrupt. */
+ NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n);
+
+ }
+ else if (argval == RT_DEVICE_CAN_INT_ERR)
+ {
+ /* Enable Error Status and Status Change Interrupt */
+ CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+ NVIC_SetPriority(((nu_can_t)can)->can_irq_n, (1 << __NVIC_PRIO_BITS) - 2);
+ /* Enable NVIC interrupt. */
+ NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n);
+ }
+ break;
+
+ case RT_CAN_CMD_SET_FILTER:
+#ifdef RT_CAN_USING_HDR
+ filter_cfg = (struct rt_can_filter_config *)arg;
+
+ for (int i = 0; i < filter_cfg->count; i++)
+ {
+
+ /*set the filter message object*/
+ if (filter_cfg->items[i].mode == 1)
+ {
+ if (CAN_SetRxMsgObjAndMsk(can_base, MSG(i + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
+ {
+ return -(RT_ERROR);
+ }
+ }
+ else
+
+ {
+ /*set the filter message object*/
+ if (CAN_SetRxMsgAndMsk(can_base, MSG(i + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
+ {
+ return -(RT_ERROR);
+ }
+ }
+ }
+#endif
+ break;
+ case RT_CAN_CMD_SET_MODE:
+ argval = (rt_uint32_t) arg;
+ if (argval != RT_CAN_MODE_NORMAL && argval != RT_CAN_MODE_LISEN &&
+ argval != RT_CAN_MODE_LOOPBACK && argval != RT_CAN_MODE_LOOPBACKANLISEN)
+ {
+ return -(RT_ERROR);
+ }
+ if (argval != can->config.mode)
+ {
+ can->config.mode = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ break;
+ case RT_CAN_CMD_SET_BAUD:
+ argval = (rt_uint32_t) arg;
+ if (argval != CAN1MBaud && argval != CAN800kBaud && argval != CAN500kBaud && argval != CAN250kBaud &&
+ argval != CAN125kBaud && argval != CAN100kBaud && argval != CAN50kBaud && argval != CAN20kBaud && argval != CAN10kBaud)
+ {
+ return -(RT_ERROR);
+ }
+ if (argval != can->config.baud_rate)
+ {
+ can->config.baud_rate = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ break;
+ case RT_CAN_CMD_SET_PRIV:
+ argval = (rt_uint32_t) arg;
+ if (argval != RT_CAN_MODE_PRIV && argval != RT_CAN_MODE_NOPRIV)
+ {
+ return -(RT_ERROR);
+ }
+ if (argval != can->config.privmode)
+ {
+ can->config.privmode = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ break;
+ case RT_CAN_CMD_GET_STATUS:
+ {
+ rt_uint32_t errtype;
+ errtype = can_base->ERR;
+ /*Receive Error Counter*/
+ can->status.rcverrcnt = (errtype >> 8);
+ /*Transmit Error Counter*/
+ can->status.snderrcnt = ((errtype >> 24) & 0xFF);
+ can->status.lasterrtype = CAN_GET_INT_STATUS(can_base) & 0x8000;
+ /*status error code*/
+ can->status.errcode = CAN_GET_INT_STATUS(can_base) & 0x07;
+ rt_memcpy(arg, &can->status, sizeof(can->status));
+ }
+ break;
+ }
+
+ return RT_EOK;
+}
+
+static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno)
+{
+ STR_CANMSG_T tMsg;
+ struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+ /* Get base address of uart register */
+ CAN_T *can_base = ((nu_can_t)can)->can_base;
+
+ RT_ASSERT(can_base != RT_NULL);
+ RT_ASSERT(buf != RT_NULL);
+ /* Check the parameters */
+ RT_ASSERT(IS_CAN_DLC(pmsg->len));
+ /* Standard ID (11 bits)*/
+ if (pmsg->ide == RT_CAN_STDID)
+ {
+ tMsg.IdType = CAN_STD_ID;
+ RT_ASSERT(IS_CAN_STDID(pmsg->id))
+ tMsg.Id = pmsg->id ;
+ }
+ else
+ {
+ /* Extended ID (29 bits)*/
+ tMsg.IdType = CAN_EXT_ID;
+ RT_ASSERT(IS_CAN_EXTID(pmsg->id));
+ tMsg.Id = pmsg->id ;
+ }
+
+ if (pmsg->rtr == RT_CAN_DTR)
+ {
+ /* Data frame */
+ tMsg.FrameType = CAN_DATA_FRAME;
+ }
+ else
+ {
+ /* Remote frame */
+ tMsg.FrameType = CAN_REMOTE_FRAME;
+ }
+ tMsg.DLC = pmsg->len;
+ rt_memcpy(tMsg.Data, pmsg->data, pmsg->len);
+
+ if (CAN_Transmit(can_base, MSG(boxno), &tMsg) == FALSE) // Configure Msg RAM and send the Msg in the RAM
+ {
+ return -(RT_ERROR);
+ }
+
+ return RT_EOK;
+}
+static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
+{
+ STR_CANMSG_T tMsg;
+ struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+ /* Get base address of uart register */
+ CAN_T *can_base = ((nu_can_t)can)->can_base;
+
+ RT_ASSERT(can_base != RT_NULL);
+ RT_ASSERT(buf != RT_NULL);
+
+ /* get data */
+ CAN_Receive(can_base, boxno, &tMsg);
+
+#ifdef RT_CAN_USING_HDR
+ /* Hardware filter messages are valid */
+ can->hdr->connected = 1;
+#endif
+
+ /* Standard ID (11 bits)*/
+ if (tMsg.IdType == CAN_STD_ID)
+ {
+ pmsg->ide = RT_CAN_STDID;
+ pmsg->id = tMsg.Id;
+ }
+ else /* Extended ID (29 bits)*/
+ {
+ pmsg->ide = RT_CAN_EXTID;
+ pmsg->id = tMsg.Id;
+ }
+ if (tMsg.FrameType == CAN_DATA_FRAME)
+ {
+ /* Data frame */
+ pmsg->rtr = RT_CAN_DTR;
+ }
+ else
+ {
+ /* Remote frame */
+ pmsg->rtr = RT_CAN_RTR;
+ }
+ pmsg->len = tMsg.DLC ;
+ rt_memcpy(pmsg->data, tMsg.Data, pmsg->len);
+
+
+ return RT_EOK;
+}
+
+/**
+ * Hardware CAN Initialization
+ */
+static int rt_hw_can_init(void)
+{
+ int i;
+ rt_err_t ret = RT_EOK;
+
+ for (i = (CAN_START + 1); i < CAN_CNT; i++)
+ {
+
+ nu_can_arr[i].dev.ops = &nu_can_ops;
+ nu_can_arr[i].dev.config = nu_can_default_config;
+
+#ifdef RT_CAN_USING_HDR
+ nu_can_arr[i].dev.config.maxhdr = RT_CANMSG_BOX_SZ;
+#endif
+ ret = rt_hw_can_register(&nu_can_arr[i].dev, nu_can_arr[i].name, &nu_can_ops, NULL);
+ RT_ASSERT(ret == RT_EOK);
+ }
+
+ return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_can_init);
+#endif //#if defined(BSP_USING_CAN)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c
new file mode 100644
index 00000000000..9ed0233bb2f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c
@@ -0,0 +1,329 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-03-25 klcheng First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_CLK)
+
+#include
+#include
+#include
+#include
+#include
+
+
+/* Private define ---------------------------------------------------------------*/
+
+/* pm run mode speed mapping */
+#define CONFIG_HIGH_SPEED_FREQ (192000000ul)
+#define CONFIG_NORMAL_SPEED_FREQ (192000000ul)
+#define CONFIG_MEDIMUM_SPEED_FREQ (144000000ul)
+#define CONFIG_LOW_SPEED_FREQ (72000000ul)
+
+/* pm sleep mode mapping */
+#define CONFIG_MODE_LIGHT (CLK_PMUCTL_PDMSEL_FWPD)
+#define CONFIG_MODE_DEEP (CLK_PMUCTL_PDMSEL_PD)
+#define CONFIG_MODE_STANDBY (CLK_PMUCTL_PDMSEL_SPD1)
+#define CONFIG_MODE_SHUTDOWN (CLK_PMUCTL_PDMSEL_DPD)
+
+
+#if defined (NU_CLK_INVOKE_WKTMR)
+ /* Wake-up timer clock source is OSC10K */
+ #define WKTMR_INTERVAL (CLK_PMUCTL_WKTMRIS_65536)
+#endif
+
+
+/* Timer module assigned for pm device usage. */
+/* e.g. If TIMERn is reserved for pm, then define the PM_TIMER_USE_INSTANCE
+ macro to n value (without parentheses). */
+#define PM_TIMER_USE_INSTANCE 3
+
+
+/* Concatenate */
+#define _CONCAT2_(x, y) x##y
+#define _CONCAT3_(x, y, z) x##y##z
+#define CONCAT2(x, y) _CONCAT2_(x, y)
+#define CONCAT3(x, y, z) _CONCAT3_(x,y,z)
+
+/* Concatenate the macros of timer instance for driver usage. */
+#define PM_TIMER CONCAT2(TIMER, PM_TIMER_USE_INSTANCE)
+#define PM_TMR CONCAT2(TMR, PM_TIMER_USE_INSTANCE)
+#define PM_TIMER_MODULE CONCAT2(PM_TMR, _MODULE)
+#define PM_TIMER_IRQn CONCAT2(PM_TMR, _IRQn)
+#define PM_TIMER_IRQHandler CONCAT2(PM_TMR, _IRQHandler)
+#define PM_TIMER_SEL_LXT CONCAT3(CLK_CLKSEL1_, PM_TMR, SEL_LXT)
+
+/* Private typedef --------------------------------------------------------------*/
+
+
+/* Private functions ------------------------------------------------------------*/
+static void pm_sleep(struct rt_pm *pm, rt_uint8_t mode);
+static void pm_run(struct rt_pm *pm, rt_uint8_t mode);
+static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout);
+static void pm_timer_stop(struct rt_pm *pm);
+static rt_tick_t pm_timer_get_tick(struct rt_pm *pm);
+static rt_tick_t pm_tick_from_os_tick(rt_tick_t os_tick);
+static rt_tick_t os_tick_from_pm_tick(rt_tick_t pm_tick);
+
+/* Public functions -------------------------------------------------------------*/
+int rt_hw_pm_init(void);
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_pm_ops ops =
+{
+ .sleep = pm_sleep,
+ .run = pm_run,
+ .timer_start = pm_timer_start,
+ .timer_stop = pm_timer_stop,
+ .timer_get_tick = pm_timer_get_tick,
+};
+
+struct rt_device pm;
+
+
+
+/* pm sleep() entry */
+static void pm_sleep(struct rt_pm *pm, rt_uint8_t mode)
+{
+ SYS_UnlockReg();
+
+ switch (mode)
+ {
+ /* wake-up source: */
+ /* PM_SLEEP_MODE_LIGHT : TIMERn */
+ /* PM_SLEEP_MODE_DEEP : TIMERn */
+ /* PM_SLEEP_MODE_STANDBY : wake-up timer (optional) */
+ /* PM_SLEEP_MODE_SHUTDOWN : wake-up timer (optional) */
+
+ case PM_SLEEP_MODE_NONE:
+ case PM_SLEEP_MODE_IDLE:
+ break;
+
+ case PM_SLEEP_MODE_LIGHT:
+
+ CLK_SetPowerDownMode(CONFIG_MODE_LIGHT);
+ CLK_PowerDown();
+ break;
+
+ case PM_SLEEP_MODE_DEEP:
+
+ CLK_SetPowerDownMode(CONFIG_MODE_DEEP);
+ CLK_PowerDown();
+ break;
+
+ case PM_SLEEP_MODE_STANDBY:
+
+#if defined (NU_CLK_INVOKE_WKTMR)
+
+ /* Enable wake-up timer with pre-defined interval if it is invoked */
+ CLK_SET_WKTMR_INTERVAL(WKTMR_INTERVAL);
+ CLK_ENABLE_WKTMR();
+#endif
+ CLK_SetPowerDownMode(CONFIG_MODE_STANDBY);
+ CLK_PowerDown();
+ break;
+
+ case PM_SLEEP_MODE_SHUTDOWN:
+
+#if defined (NU_CLK_INVOKE_WKTMR)
+ /* Enable wake-up timer with pre-defined interval if it is invoked */
+ CLK_SET_WKTMR_INTERVAL(WKTMR_INTERVAL);
+ CLK_ENABLE_WKTMR();
+#endif
+ CLK_SetPowerDownMode(CONFIG_MODE_SHUTDOWN);
+ CLK_PowerDown();
+ break;
+
+ default:
+ RT_ASSERT(0);
+ break;
+ }
+
+ SYS_LockReg();
+}
+
+
+/* pm run() entry */
+static void pm_run(struct rt_pm *pm, rt_uint8_t mode)
+{
+ static uint8_t prev_mode = RT_PM_DEFAULT_RUN_MODE;
+
+ /* ignore it if power mode is the same. */
+ if (mode == prev_mode)
+ return;
+
+ prev_mode = mode;
+
+ SYS_UnlockReg();
+
+ /* Switch run mdoe frequency using PLL + HXT if HXT is enabled.
+ Otherwise, the systme clock will use PLL + HIRC. */
+ switch (mode)
+ {
+ case PM_RUN_MODE_HIGH_SPEED:
+
+ CLK_SetCoreClock(CONFIG_HIGH_SPEED_FREQ);
+ break;
+
+ case PM_RUN_MODE_NORMAL_SPEED:
+
+ CLK_SetCoreClock(CONFIG_NORMAL_SPEED_FREQ);
+ break;
+
+ case PM_RUN_MODE_MEDIUM_SPEED:
+
+ CLK_SetCoreClock(CONFIG_MEDIMUM_SPEED_FREQ);
+ break;
+
+ case PM_RUN_MODE_LOW_SPEED:
+
+ CLK_SetCoreClock(CONFIG_LOW_SPEED_FREQ);
+ break;
+
+ default:
+ RT_ASSERT(0);
+ break;
+ }
+
+ SystemCoreClockUpdate();
+ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+ SYS_LockReg();
+}
+
+
+static void hw_timer_init(void)
+{
+ /* Assign a hardware timer for pm usage. */
+ SYS_UnlockReg();
+ CLK_SetModuleClock(PM_TIMER_MODULE, PM_TIMER_SEL_LXT, MODULE_NoMsk);
+ CLK_EnableModuleClock(PM_TIMER_MODULE);
+ SYS_LockReg();
+
+ /* Initialise timer and enable wakeup function. */
+ TIMER_Open(PM_TIMER, TIMER_CONTINUOUS_MODE, 1);
+ TIMER_SET_PRESCALE_VALUE(PM_TIMER, 0);
+ TIMER_EnableInt(PM_TIMER);
+ TIMER_EnableWakeup(PM_TIMER);
+ NVIC_EnableIRQ(PM_TIMER_IRQn);
+}
+
+
+/* convert os tick to pm timer tick */
+static rt_tick_t pm_tick_from_os_tick(rt_tick_t os_tick)
+{
+ rt_uint32_t hz = TIMER_GetModuleClock(PM_TIMER);
+
+ return (rt_tick_t)(hz * os_tick / RT_TICK_PER_SECOND);
+}
+
+
+/* convert pm timer tick to os tick */
+static rt_tick_t os_tick_from_pm_tick(rt_tick_t pm_tick)
+{
+ static rt_uint32_t os_tick_remain = 0;
+ rt_uint32_t ret, hz;
+
+ hz = TIMER_GetModuleClock(PM_TIMER);
+ ret = (pm_tick * RT_TICK_PER_SECOND + os_tick_remain) / hz;
+
+ os_tick_remain += (pm_tick * RT_TICK_PER_SECOND);
+ os_tick_remain %= hz;
+
+ return ret;
+}
+
+
+/* pm_ops timer_get_tick() entry */
+static rt_tick_t pm_timer_get_tick(struct rt_pm *pm)
+{
+ rt_tick_t tick;
+
+ tick = TIMER_GetCounter(PM_TIMER);
+
+ return os_tick_from_pm_tick(tick);
+}
+
+
+/* pm timer_start() entry */
+static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout)
+{
+ int tick;
+
+ if (timeout == RT_TICK_MAX)
+ return;
+
+ /* start pm timer to compenstate the os tick in power down mode */
+ tick = pm_tick_from_os_tick(timeout);
+ TIMER_SET_CMP_VALUE(PM_TIMER, tick);
+ TIMER_Start(PM_TIMER);
+}
+
+
+/* pm timer_stop() entry */
+static void pm_timer_stop(struct rt_pm *pm)
+{
+ TIMER_Stop(PM_TIMER);
+ TIMER_ResetCounter(PM_TIMER);
+}
+
+
+/* pm device driver initialise. */
+int rt_hw_pm_init(void)
+{
+ rt_uint8_t timer_mask;
+
+ if (CLK_GetPMUWKSrc())
+ {
+ /* Release I/O hold status after wake-up from Standby Power-down Mode (SPD) */
+ CLK->IOPDCTL = 1;
+
+ /* Clear Power Manager Status register */
+ CLK->PMUSTS = CLK_PMUSTS_CLRWK_Msk;
+ }
+
+ hw_timer_init();
+
+ /* initialize timer mask */
+ timer_mask = (1UL << PM_SLEEP_MODE_LIGHT) |
+ (1UL << PM_SLEEP_MODE_DEEP);
+
+ /* initialize system pm module */
+ rt_system_pm_init(&ops, timer_mask, RT_NULL);
+
+ return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_pm_init);
+
+
+/* pm timer interrupt entry */
+void PM_TIMER_IRQHandler(void)
+{
+ rt_interrupt_enter();
+
+ if (TIMER_GetIntFlag(PM_TIMER))
+ {
+ TIMER_ClearIntFlag(PM_TIMER);
+ }
+
+ if (TIMER_GetWakeupFlag(PM_TIMER))
+ {
+ TIMER_ClearWakeupFlag(PM_TIMER);
+ }
+
+ rt_interrupt_leave();
+}
+
+#endif /* BSP_USING_CLK */
+
+
+
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c
new file mode 100644
index 00000000000..50c056730e5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c
@@ -0,0 +1,134 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-3-4 CHChen First version
+*
+******************************************************************************/
+
+#include
+
+#if (defined(BSP_USING_CRC) && defined(RT_HWCRYPTO_USING_CRC))
+
+#include
+
+#include
+#include
+
+#include "NuMicro.h"
+#include "drv_pdma.h"
+
+/* Private define ---------------------------------------------------------------*/
+#define NU_CRYPTO_CRC_NAME "nu_CRC"
+
+/* Private variables ------------------------------------------------------------*/
+
+static struct rt_mutex s_CRC_mutex;
+
+static rt_uint32_t nu_crc_run(
+ uint32_t u32OpMode,
+ uint32_t u32Seed,
+ uint32_t u32Attr,
+ uint8_t *pu8InData,
+ uint32_t u32DataLen
+)
+{
+ uint32_t u32CalChecksum = 0;
+ uint32_t i = 0;
+
+ rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
+
+ /* Configure CRC controller */
+ CRC_Open(u32OpMode, u32Attr, u32Seed, CRC_CPU_WDATA_8);
+
+ uint8_t *pu8InTempData = pu8InData;
+
+ while (i < u32DataLen)
+ {
+ if (((((uint32_t)pu8InTempData) % 4) != 0) || (u32DataLen - i < 4))
+ {
+ CRC->CTL &= ~CRC_CTL_DATLEN_Msk;
+ CRC_WRITE_DATA((*pu8InTempData) & 0xFF);
+ pu8InTempData ++;
+ i++;
+ }
+ else
+ {
+ CRC->CTL &= ~CRC_CTL_DATLEN_Msk;
+ CRC->CTL |= CRC_CPU_WDATA_32;
+#if defined (NU_CRC_USE_PDMA)
+ int32_t i32PDMATransCnt = (u32DataLen - i) / 4 ;
+
+ i32PDMATransCnt = nu_pdma_mempush((void *)&CRC->DAT, pu8InTempData, 32, i32PDMATransCnt);
+
+ if (i32PDMATransCnt > 0)
+ {
+ pu8InTempData += (i32PDMATransCnt * 4);
+ i += (i32PDMATransCnt * 4);
+ }
+#else
+ CRC_WRITE_DATA(*(uint32_t *)pu8InTempData);
+ pu8InTempData += 4;
+ i += 4;
+#endif
+ }
+ }
+
+ /* Get checksum value */
+ u32CalChecksum = CRC_GetChecksum();
+ rt_mutex_release(&s_CRC_mutex);
+
+ return u32CalChecksum;
+}
+
+
+rt_err_t nu_crc_init(void)
+{
+ SYS_ResetModule(CRC_RST);
+
+ rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_FIFO);
+ return RT_EOK;
+}
+
+rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
+{
+ uint32_t u32OpMode;
+ uint32_t u32CRCAttr = 0;
+ rt_uint32_t crc_result = 0;
+
+ //select CRC operation mode
+ switch (ctx->crc_cfg.poly)
+ {
+ case 0x04C11DB7:
+ u32OpMode = CRC_32;
+ break;
+ case 0x00001021:
+ u32OpMode = CRC_CCITT;
+ break;
+ case 0x00008005:
+ u32OpMode = CRC_16;
+ break;
+ case 0x00000007:
+ u32OpMode = CRC_8;
+ break;
+ default:
+ return 0;
+ }
+
+
+ u32CRCAttr |= ctx->crc_cfg.flags & CRC_FLAG_REFOUT ? CRC_CHECKSUM_RVS : 0; //CRC Checksum Reverse
+ u32CRCAttr |= ctx->crc_cfg.flags & CRC_FLAG_REFIN ? CRC_WDATA_RVS : 0; //CRC Write Data Reverse
+
+ //Calcluate CRC checksum, using config's last value as CRC seed
+ crc_result = nu_crc_run(u32OpMode, ctx->crc_cfg.last_val, u32CRCAttr, (uint8_t *)in, length);
+
+ //update CRC result to config's last vaule
+ ctx->crc_cfg.last_val = crc_result;
+ return crc_result ^ 0x00 ^ ctx->crc_cfg.xorout;
+}
+
+#endif //#if (defined(BSP_USING_CRC) && defined(RT_HWCRYPTO_USING_CRC))
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.h
new file mode 100644
index 00000000000..04c2038c07e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.h
@@ -0,0 +1,21 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-3-4 CHChen First version
+*
+******************************************************************************/
+
+#ifndef __DRV_CRC_H__
+#define __DRV_CRC_H__
+
+rt_err_t nu_crc_init(void);
+
+rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length);
+
+
+#endif
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c
new file mode 100644
index 00000000000..6cc1f0b3093
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c
@@ -0,0 +1,842 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-3-3 CHChen First version
+* 2020-5-3 YCHuang12 Add TDES and SHA
+*
+******************************************************************************/
+
+#include
+
+#if ((defined(BSP_USING_CRYPTO) || defined(BSP_USING_TRNG) || defined(BSP_USING_CRC)) && defined(RT_USING_HWCRYPTO))
+
+#include
+
+#include
+#include
+#include "NuMicro.h"
+#include
+
+#if defined(BSP_USING_TRNG)
+ #include "drv_trng.h"
+#endif
+
+#if defined(BSP_USING_CRC)
+ #include "drv_crc.h"
+#endif
+
+/* Private typedef --------------------------------------------------------------*/
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx);
+static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx);
+static rt_err_t nu_hwcrypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src);
+static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx);
+
+/* Private variables ------------------------------------------------------------*/
+static const struct rt_hwcrypto_ops nu_hwcrypto_ops =
+{
+ .create = nu_hwcrypto_create,
+ .destroy = nu_hwcrypto_destroy,
+ .copy = nu_hwcrypto_clone,
+ .reset = nu_hwcrypto_reset,
+};
+
+/* Crypto engine operation ------------------------------------------------------------*/
+#if defined(BSP_USING_CRYPTO)
+
+//define NU_HWCRYPTO_NOT_ALIGN_CHECK to disable plain/cipher buffer address alignment checking
+//#define NU_HWCRYPTO_NOT_ALIGN_CHECK
+
+#define NU_HWCRYPTO_DES_3KEYS 1
+#define NU_HWCRYPTO_DES_NO3KEYS 0
+#define NU_HWCRYPTO_AES_NAME "nu_AES"
+#define NU_HWCRYPTO_TDES_NAME "nu_TDES"
+#define NU_HWCRYPTO_SHA_NAME "nu_SHA"
+#if !defined(BSP_USING_TRNG)
+ #define NU_HWCRYPTO_PRNG_NAME "nu_PRNG"
+#endif
+
+static struct rt_mutex s_AES_mutex;
+static struct rt_mutex s_TDES_mutex;
+static struct rt_mutex s_SHA_mutex;
+
+#if !defined(BSP_USING_TRNG)
+ static struct rt_mutex s_PRNG_mutex;
+ static volatile int s_PRNG_done;
+#endif
+
+static volatile int s_AES_done;
+static volatile int s_TDES_done;
+static volatile int s_SHA_done;
+
+static rt_err_t nu_crypto_init(void)
+{
+ /* Enable Crypto engine interrupt */
+ NVIC_EnableIRQ(CRPT_IRQn);
+
+ AES_ENABLE_INT(CRPT);
+ TDES_ENABLE_INT(CRPT);
+ SHA_ENABLE_INT(CRPT);
+
+ //init cipher mutex
+ rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_FIFO);
+ rt_mutex_init(&s_TDES_mutex, NU_HWCRYPTO_TDES_NAME, RT_IPC_FLAG_FIFO);
+ rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_FIFO);
+#if !defined(BSP_USING_TRNG)
+ PRNG_ENABLE_INT(CRPT);
+ rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_FIFO);
+#endif
+
+ return RT_EOK;
+}
+
+//Crypto engine IRQ handler
+
+void CRYPTO_IRQHandler()
+{
+ if (AES_GET_INT_FLAG(CRPT))
+ {
+ s_AES_done = 1;
+ AES_CLR_INT_FLAG(CRPT);
+ }
+
+ if (TDES_GET_INT_FLAG(CRPT))
+ {
+ s_TDES_done = 1;
+ TDES_CLR_INT_FLAG(CRPT);
+ }
+
+ if (SHA_GET_INT_FLAG(CRPT))
+ {
+ s_SHA_done = 1;
+ SHA_CLR_INT_FLAG(CRPT);
+ }
+
+#if !defined(BSP_USING_TRNG)
+ if (PRNG_GET_INT_FLAG(CRPT))
+ {
+ s_PRNG_done = 1;
+ PRNG_CLR_INT_FLAG(CRPT);
+ }
+#endif
+}
+
+static rt_err_t nu_aes_crypt_run(
+ rt_bool_t bEncrypt,
+ uint32_t u32OpMode,
+ uint8_t *pu8Key,
+ uint32_t u32KeySize,
+ uint8_t *pu8IV,
+ uint8_t *pu8InData,
+ uint8_t *pu8OutData,
+ uint32_t u32DataLen
+)
+{
+ uint32_t au32SwapKey[8];
+ uint32_t au32SwapIV[4];
+
+ au32SwapKey[0] = nu_get32_be(&pu8Key[0]);
+ au32SwapKey[1] = nu_get32_be(&pu8Key[4]);
+ au32SwapKey[2] = nu_get32_be(&pu8Key[8]);
+ au32SwapKey[3] = nu_get32_be(&pu8Key[12]);
+
+ if ((u32KeySize == AES_KEY_SIZE_192) || (u32KeySize == AES_KEY_SIZE_256))
+ {
+ au32SwapKey[4] = nu_get32_be(&pu8Key[16]);
+ au32SwapKey[5] = nu_get32_be(&pu8Key[20]);
+ }
+
+ if (u32KeySize == AES_KEY_SIZE_256)
+ {
+ au32SwapKey[6] = nu_get32_be(&pu8Key[24]);
+ au32SwapKey[7] = nu_get32_be(&pu8Key[28]);
+ }
+
+ au32SwapIV[0] = nu_get32_be(&pu8IV[0]);
+ au32SwapIV[1] = nu_get32_be(&pu8IV[4]);
+ au32SwapIV[2] = nu_get32_be(&pu8IV[8]);
+ au32SwapIV[3] = nu_get32_be(&pu8IV[12]);
+
+ rt_mutex_take(&s_AES_mutex, RT_WAITING_FOREVER);
+
+ //Using Channel 0
+ AES_Open(CRPT, 0, bEncrypt, u32OpMode, u32KeySize, AES_IN_OUT_SWAP);
+ AES_SetKey(CRPT, 0, (uint32_t *)au32SwapKey, u32KeySize);
+ AES_SetInitVect(CRPT, 0, (uint32_t *)au32SwapIV);
+
+ //Setup AES DMA
+ AES_SetDMATransfer(CRPT, 0, (uint32_t)pu8InData, (uint32_t)pu8OutData, u32DataLen);
+ AES_CLR_INT_FLAG(CRPT);
+ //Start AES encryption/decryption
+ s_AES_done = 0;
+ AES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT);
+ while (!s_AES_done) {};
+
+ rt_mutex_release(&s_AES_mutex);
+
+ return RT_EOK;
+}
+
+#if !defined(BSP_USING_TRNG)
+//Using PRNG instead of TRNG
+static void nu_prng_open(uint32_t u32Seed)
+{
+ rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
+
+ //Open PRNG 64 bits. But always return 32 bits
+ PRNG_Open(CRPT, PRNG_KEY_SIZE_64, PRNG_SEED_RELOAD, u32Seed);
+
+ rt_mutex_release(&s_PRNG_mutex);
+}
+
+static rt_uint32_t nu_prng_run(void)
+{
+ uint32_t au32RNGValue[2];
+
+ rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
+
+ s_PRNG_done = 0;
+ PRNG_Start(CRPT);
+ while (!s_PRNG_done) {};
+
+ PRNG_Read(CRPT, au32RNGValue);
+
+ rt_mutex_release(&s_PRNG_mutex);
+ return au32RNGValue[0];
+}
+
+#endif
+
+static rt_err_t nu_aes_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hwcrypto_symmetric_info *symmetric_info)
+{
+ uint32_t u32AESOpMode;
+ uint32_t u32AESKeySize;
+ unsigned char *in, *out;
+
+ if ((symmetric_info->length % 16) != 0)
+ {
+ return -RT_EINVAL;
+ }
+
+ //Checking key length
+ if (symmetric_ctx->key_bitlen == 128)
+ {
+ u32AESKeySize = AES_KEY_SIZE_128;
+ }
+ else if (symmetric_ctx->key_bitlen == 192)
+ {
+ u32AESKeySize = AES_KEY_SIZE_192;
+ }
+ else if (symmetric_ctx->key_bitlen == 256)
+ {
+ u32AESKeySize = AES_KEY_SIZE_256;
+ }
+ else
+ {
+ return -RT_EINVAL;
+ }
+
+ //Select AES operation mode
+ switch (symmetric_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
+ {
+ case HWCRYPTO_TYPE_AES_ECB:
+ u32AESOpMode = AES_MODE_ECB;
+ break;
+ case HWCRYPTO_TYPE_AES_CBC:
+ u32AESOpMode = AES_MODE_CBC;
+ break;
+ case HWCRYPTO_TYPE_AES_CFB:
+ u32AESOpMode = AES_MODE_CFB;
+ break;
+ case HWCRYPTO_TYPE_AES_OFB:
+ u32AESOpMode = AES_MODE_OFB;
+ break;
+ case HWCRYPTO_TYPE_AES_CTR:
+ u32AESOpMode = AES_MODE_CTR;
+ break;
+ default :
+ return -RT_ERROR;
+ }
+
+ in = (unsigned char *)symmetric_info->in;
+ out = (unsigned char *)symmetric_info->out;
+
+#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK)
+ unsigned char in_align_flag = 0;
+ unsigned char out_align_flag = 0;
+
+ //Checking in/out data buffer address alignment or not
+ if (((rt_uint32_t)in % 4) != 0)
+ {
+ in = rt_malloc(symmetric_info->length);
+ if (in == RT_NULL)
+ {
+ LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, symmetric_info->length);
+ return -RT_ENOMEM;
+ }
+
+ memcpy(in, symmetric_info->in, symmetric_info->length);
+ in_align_flag = 1;
+ }
+
+ if (((rt_uint32_t)out % 4) != 0)
+ {
+ out = rt_malloc(symmetric_info->length);
+ if (out == RT_NULL)
+ {
+ if (in_align_flag)
+ rt_free(in);
+ LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, symmetric_info->length);
+ return -RT_ENOMEM;
+ }
+
+ out_align_flag = 1;
+ }
+#endif
+
+ nu_aes_crypt_run(symmetric_info->mode == HWCRYPTO_MODE_ENCRYPT ? TRUE : FALSE, u32AESOpMode, symmetric_ctx->key, u32AESKeySize, symmetric_ctx->iv, in, out, symmetric_info->length);
+
+#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK)
+ if (out_align_flag)
+ {
+ memcpy(symmetric_info->out, out, symmetric_info->length);
+ rt_free(out);
+ }
+
+ if (in_align_flag)
+ {
+ rt_free(in);
+ }
+#endif
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_des_crypt_run(
+ rt_bool_t bEncrypt,
+ uint32_t u32OpMode,
+ uint8_t *pu8Key,
+ uint32_t u32KeySize,
+ uint8_t *pu8IV,
+ uint8_t *pu8InData,
+ uint8_t *pu8OutData,
+ uint32_t u32DataLen
+)
+{
+ uint32_t au32SwapKey[3][2];
+ uint32_t au32SwapIV[2];
+
+ au32SwapKey[0][0] = nu_get32_be(&pu8Key[0]);
+ au32SwapKey[0][1] = nu_get32_be(&pu8Key[4]);
+ au32SwapKey[1][0] = nu_get32_be(&pu8Key[8]);
+ au32SwapKey[1][1] = nu_get32_be(&pu8Key[12]);
+
+ if (u32KeySize == NU_HWCRYPTO_DES_3KEYS)
+ {
+ au32SwapKey[2][0] = nu_get32_be(&pu8Key[16]);
+ au32SwapKey[2][1] = nu_get32_be(&pu8Key[20]);
+ }
+
+ au32SwapIV[0] = nu_get32_be(&pu8IV[0]);
+ au32SwapIV[1] = nu_get32_be(&pu8IV[4]);
+
+ rt_mutex_take(&s_TDES_mutex, RT_WAITING_FOREVER);
+
+ //Using Channel 0
+ TDES_Open(CRPT, 0, bEncrypt, (u32OpMode & CRPT_TDES_CTL_TMODE_Msk), u32KeySize, u32OpMode, TDES_IN_OUT_WHL_SWAP);
+ TDES_SetKey(CRPT, 0, au32SwapKey);
+ TDES_SetInitVect(CRPT, 0, au32SwapIV[0], au32SwapIV[1]);
+
+ //Setup TDES DMA
+ TDES_SetDMATransfer(CRPT, 0, (uint32_t)pu8InData, (uint32_t)pu8OutData, u32DataLen);
+ TDES_CLR_INT_FLAG(CRPT);
+ //Start TDES encryption/decryption
+ s_TDES_done = 0;
+ TDES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT);
+ while (!s_TDES_done) {};
+
+ rt_mutex_release(&s_TDES_mutex);
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_des_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hwcrypto_symmetric_info *symmetric_info)
+{
+ uint32_t u32DESOpMode;
+ uint32_t u32DESKeySize;
+ unsigned char *in, *out;
+
+ if ((symmetric_info->length % 8) != 0)
+ {
+ return -RT_EINVAL;
+ }
+
+ //Checking key length
+ if (symmetric_ctx->key_bitlen == 128 || symmetric_ctx->key_bitlen == 64)
+ {
+ u32DESKeySize = NU_HWCRYPTO_DES_NO3KEYS;
+ }
+ else if (symmetric_ctx->key_bitlen == 192)
+ {
+ u32DESKeySize = NU_HWCRYPTO_DES_3KEYS;
+ }
+ else
+ {
+ return -RT_EINVAL;
+ }
+
+ //Select DES operation mode
+ switch (symmetric_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
+ {
+ case HWCRYPTO_TYPE_DES_ECB:
+ u32DESOpMode = DES_MODE_ECB;
+ break;
+ case HWCRYPTO_TYPE_DES_CBC:
+ u32DESOpMode = DES_MODE_CBC;
+ break;
+ case HWCRYPTO_TYPE_3DES_ECB:
+ u32DESOpMode = TDES_MODE_ECB;
+ break;
+ case HWCRYPTO_TYPE_3DES_CBC:
+ u32DESOpMode = TDES_MODE_CBC;
+ break;
+ default :
+ return -RT_ERROR;
+ }
+
+ in = (unsigned char *)symmetric_info->in;
+ out = (unsigned char *)symmetric_info->out;
+
+#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK)
+ unsigned char in_align_flag = 0;
+ unsigned char out_align_flag = 0;
+
+ //Checking in/out data buffer address alignment or not
+ if (((rt_uint32_t)in % 4) != 0)
+ {
+ in = rt_malloc(symmetric_info->length);
+ if (in == RT_NULL)
+ {
+ LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, symmetric_info->length);
+ return -RT_ENOMEM;
+ }
+
+ memcpy(in, symmetric_info->in, symmetric_info->length);
+ in_align_flag = 1;
+ }
+
+ if (((rt_uint32_t)out % 4) != 0)
+ {
+ out = rt_malloc(symmetric_info->length);
+ if (out == RT_NULL)
+ {
+ if (in_align_flag)
+ rt_free(in);
+ LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, symmetric_info->length);
+ return -RT_ENOMEM;
+ }
+
+ out_align_flag = 1;
+ }
+#endif
+
+ nu_des_crypt_run(symmetric_info->mode == HWCRYPTO_MODE_ENCRYPT ? TRUE : FALSE, u32DESOpMode, symmetric_ctx->key, u32DESKeySize, symmetric_ctx->iv, in, out, symmetric_info->length);
+
+#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK)
+ if (out_align_flag)
+ {
+ memcpy(symmetric_info->out, out, symmetric_info->length);
+ rt_free(out);
+ }
+
+ if (in_align_flag)
+ {
+ rt_free(in);
+ }
+#endif
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_sha_hash_run(
+ uint32_t u32OpMode,
+ uint8_t *pu8InData,
+ uint32_t u32DataLen
+)
+{
+ rt_mutex_take(&s_SHA_mutex, RT_WAITING_FOREVER);
+
+ //Using SHA
+ SHA_Open(CRPT, u32OpMode, SHA_IN_OUT_SWAP, 0);
+
+ //Setup SHA DMA
+ SHA_SetDMATransfer(CRPT, (uint32_t)pu8InData, u32DataLen);
+ SHA_CLR_INT_FLAG(CRPT);
+ //Start SHA
+ s_SHA_done = 0;
+ SHA_Start(CRPT, CRYPTO_DMA_ONE_SHOT);
+ while (!s_SHA_done) {};
+
+ rt_mutex_release(&s_SHA_mutex);
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_sha_update(struct hwcrypto_hash *hash_ctx, const rt_uint8_t *in, rt_size_t length)
+{
+ uint32_t u32SHAOpMode;
+ unsigned char *nu_in;
+
+ //Select SHA operation mode
+ switch (hash_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
+ {
+ case HWCRYPTO_TYPE_SHA1:
+ u32SHAOpMode = SHA_MODE_SHA1;
+ break;
+ case HWCRYPTO_TYPE_SHA224:
+ u32SHAOpMode = SHA_MODE_SHA224;
+ break;
+ case HWCRYPTO_TYPE_SHA256:
+ u32SHAOpMode = SHA_MODE_SHA256;
+ break;
+ case HWCRYPTO_TYPE_SHA384:
+ u32SHAOpMode = SHA_MODE_SHA384;
+ break;
+ case HWCRYPTO_TYPE_SHA512:
+ u32SHAOpMode = SHA_MODE_SHA512;
+ break;
+ default :
+ return -RT_ERROR;
+ }
+
+ nu_in = (unsigned char *)in;
+
+#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK)
+ unsigned char in_align_flag = 0;
+
+ //Checking in data buffer address alignment or not
+ if (((rt_uint32_t)nu_in % 4) != 0)
+ {
+ nu_in = rt_malloc(length);
+ if (nu_in == RT_NULL)
+ {
+ LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, length);
+ return -RT_ENOMEM;
+ }
+
+ memcpy(nu_in, in, length);
+ in_align_flag = 1;
+ }
+#endif
+
+ nu_sha_hash_run(u32SHAOpMode, nu_in, length);
+
+#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK)
+ if (in_align_flag)
+ {
+ rt_free(nu_in);
+ }
+#endif
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_sha_finish(struct hwcrypto_hash *hash_ctx, rt_uint8_t *out, rt_size_t length)
+{
+ unsigned char *nu_out;
+
+ //Check SHA Hash value buffer length
+ switch (hash_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
+ {
+ case HWCRYPTO_TYPE_SHA1:
+ if (length < 5UL)
+ {
+ return -RT_EINVAL;
+ }
+ break;
+ case HWCRYPTO_TYPE_SHA224:
+ if (length < 7UL)
+ {
+ return -RT_EINVAL;
+ }
+ break;
+ case HWCRYPTO_TYPE_SHA256:
+ if (length < 8UL)
+ {
+ return -RT_EINVAL;
+ }
+ break;
+ case HWCRYPTO_TYPE_SHA384:
+ if (length < 12UL)
+ {
+ return -RT_EINVAL;
+ }
+ break;
+ case HWCRYPTO_TYPE_SHA512:
+ if (length < 16UL)
+ {
+ return -RT_EINVAL;
+ }
+ break;
+ default :
+ return -RT_ERROR;
+ }
+
+ nu_out = (unsigned char *)out;
+
+#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK)
+ unsigned char out_align_flag = 0;
+
+ //Checking out data buffer address alignment or not
+ if (((rt_uint32_t)nu_out % 4) != 0)
+ {
+ nu_out = rt_malloc(length);
+ if (nu_out == RT_NULL)
+ {
+ LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, length);
+ return -RT_ENOMEM;
+ }
+
+ out_align_flag = 1;
+ }
+#endif
+
+ SHA_Read(CRPT, (uint32_t *)nu_out);
+
+#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK)
+ if (out_align_flag)
+ {
+ memcpy(out, out, length);
+ rt_free(out);
+ }
+#endif
+
+ return RT_EOK;
+}
+
+#if !defined(BSP_USING_TRNG)
+static rt_uint32_t nu_prng_rand(struct hwcrypto_rng *ctx)
+{
+ return nu_prng_run();
+}
+
+#endif
+
+static const struct hwcrypto_symmetric_ops nu_aes_ops =
+{
+ .crypt = nu_aes_crypt,
+};
+
+static const struct hwcrypto_symmetric_ops nu_des_ops =
+{
+ .crypt = nu_des_crypt,
+};
+
+static const struct hwcrypto_hash_ops nu_sha_ops =
+{
+ .update = nu_sha_update,
+ .finish = nu_sha_finish,
+};
+
+#endif
+
+/* CRC operation ------------------------------------------------------------*/
+#if defined(BSP_USING_CRC)
+
+static const struct hwcrypto_crc_ops nu_crc_ops =
+{
+ .update = nu_crc_update,
+};
+
+#endif
+
+/* TRNG operation ------------------------------------------------------------*/
+#if defined(BSP_USING_TRNG)
+
+static const struct hwcrypto_rng_ops nu_rng_ops =
+{
+ .update = nu_trng_rand,
+};
+
+#elif defined(BSP_USING_CRYPTO)
+
+static const struct hwcrypto_rng_ops nu_rng_ops =
+{
+ .update = nu_prng_rand,
+};
+
+#endif
+
+/* Register crypto interface ----------------------------------------------------------*/
+static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
+{
+ rt_err_t res = RT_EOK;
+
+ switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+ {
+#if defined(BSP_USING_TRNG)
+ case HWCRYPTO_TYPE_RNG:
+ {
+ ctx->contex = RT_NULL;
+ //Setup RNG operation
+ ((struct hwcrypto_rng *)ctx)->ops = &nu_rng_ops;
+ break;
+ }
+#endif /* BSP_USING_TRNG */
+
+#if defined(BSP_USING_CRC)
+ case HWCRYPTO_TYPE_CRC:
+ {
+ ctx->contex = RT_NULL;
+ //Setup CRC operation
+ ((struct hwcrypto_crc *)ctx)->ops = &nu_crc_ops;
+ break;
+ }
+#endif /* BSP_USING_CRC */
+
+#if defined(BSP_USING_CRYPTO)
+ case HWCRYPTO_TYPE_AES:
+ {
+ ctx->contex = RT_NULL;
+ //Setup AES operation
+ ((struct hwcrypto_symmetric *)ctx)->ops = &nu_aes_ops;
+ break;
+ }
+
+ case HWCRYPTO_TYPE_DES:
+ {
+ ctx->contex = RT_NULL;
+ //Setup DES operation
+ ((struct hwcrypto_symmetric *)ctx)->ops = &nu_des_ops;
+ break;
+ }
+
+ case HWCRYPTO_TYPE_3DES:
+ {
+ ctx->contex = RT_NULL;
+ //Setup 3DES operation
+ ((struct hwcrypto_symmetric *)ctx)->ops = &nu_des_ops;
+ break;
+ }
+
+
+ case HWCRYPTO_TYPE_SHA1:
+ {
+ ctx->contex = RT_NULL;
+ //Setup SHA1 operation
+ ((struct hwcrypto_hash *)ctx)->ops = &nu_sha_ops;
+ break;
+ }
+
+ case HWCRYPTO_TYPE_SHA2:
+ {
+ ctx->contex = RT_NULL;
+ //Setup SHA2 operation
+ ((struct hwcrypto_hash *)ctx)->ops = &nu_sha_ops;
+ break;
+ }
+
+#if !defined(BSP_USING_TRNG)
+ case HWCRYPTO_TYPE_RNG:
+ {
+ ctx->contex = RT_NULL;
+ ((struct hwcrypto_rng *)ctx)->ops = &nu_rng_ops;
+#if defined(NU_PRNG_USE_SEED)
+ nu_prng_open(NU_PRNG_SEED_VALUE);
+#else
+ nu_prng_open(rt_tick_get());
+#endif
+ break;
+ }
+#endif /* !BSP_USING_TRNG */
+
+#endif /* BSP_USING_CRYPTO */
+
+
+ default:
+ res = -RT_ERROR;
+ break;
+ }
+
+ return res;
+}
+
+static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx)
+{
+ if (ctx->contex)
+ rt_free(ctx->contex);
+}
+
+static rt_err_t nu_hwcrypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
+{
+ rt_err_t res = RT_EOK;
+
+ if (des->contex && src->contex)
+ {
+ rt_memcpy(des->contex, src->contex, sizeof(struct rt_hwcrypto_ctx));
+ }
+ else
+ return -RT_EINVAL;
+ return res;
+}
+
+static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx)
+{
+ switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+ {
+#if !defined(BSP_USING_TRNG)
+ case HWCRYPTO_TYPE_RNG:
+ {
+#if defined(NU_PRNG_USE_SEED)
+ nu_prng_open(NU_PRNG_SEED_VALUE);
+#else
+ nu_prng_open(rt_tick_get());
+#endif
+ break;
+ }
+#endif /* !BSP_USING_TRNG */
+
+ default:
+ break;
+ }
+}
+
+/* Init and register nu_hwcrypto_dev */
+
+int nu_hwcrypto_device_init(void)
+{
+ static struct rt_hwcrypto_device nu_hwcrypto_dev;
+
+ nu_hwcrypto_dev.ops = &nu_hwcrypto_ops;
+ nu_hwcrypto_dev.id = 0;
+ nu_hwcrypto_dev.user_data = &nu_hwcrypto_dev;
+
+#if defined(BSP_USING_CRYPTO)
+ nu_crypto_init();
+#endif
+
+#if defined(BSP_USING_CRC)
+ nu_crc_init();
+#endif
+
+#if defined(BSP_USING_TRNG)
+ nu_trng_init();
+#endif
+
+ // register hwcrypto operation
+ if (rt_hwcrypto_register(&nu_hwcrypto_dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
+ {
+ return -1;
+ }
+
+ return 0;
+}
+INIT_DEVICE_EXPORT(nu_hwcrypto_device_init);
+
+#endif //#if ((defined(BSP_USING_CRYPTO) || defined(BSP_USING_TRNG) || defined(BSP_USING_CRC)) && defined(RT_USING_HWCRYPTO))
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c
new file mode 100644
index 00000000000..60fb68e44c1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c
@@ -0,0 +1,162 @@
+/**************************************************************************//**
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-11 FYChou First version
+*
+******************************************************************************/
+
+#include
+#include
+#include
+
+#ifdef BSP_USING_EADC
+
+/* Private define ---------------------------------------------------------------*/
+
+/* Private Typedef --------------------------------------------------------------*/
+struct nu_eadc
+{
+ struct rt_adc_device dev;
+ char *name;
+ EADC_T *eadc_base;
+ int eadc_reg_tab;
+ int eadc_max_ch_num;
+
+};
+typedef struct nu_eadc *nu_eadc_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_eadc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled);
+static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value);
+static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value);
+
+
+/* Public functions ------------------------------------------------------------*/
+int rt_hw_eadc_init(void);
+
+/* Private variables ------------------------------------------------------------*/
+
+static struct nu_eadc nu_eadc_arr [] =
+{
+#if defined(BSP_USING_EADC0)
+ {
+ .name = "eadc0",
+ .eadc_base = EADC0,
+ .eadc_max_ch_num = 19,
+ },
+#endif
+
+#if defined(BSP_USING_EADC1)
+ {
+ .name = "eadc1",
+ .eadc_base = EADC1,
+ .eadc_max_ch_num = 19,
+ },
+#endif
+
+ {0}
+};
+
+static const struct rt_adc_ops nu_adc_ops =
+{
+ nu_eadc_enabled,
+ nu_get_eadc_value,
+};
+typedef struct rt_adc_ops *rt_adc_ops_t;
+
+
+/* nu_adc_enabled - Enable ADC clock and wait for ready */
+static rt_err_t nu_eadc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+
+ EADC_T *eadc_base = ((nu_eadc_t)device)->eadc_base;
+ int *peadc_reg_tab = &((nu_eadc_t)device)->eadc_reg_tab;
+ RT_ASSERT(device != RT_NULL);
+
+ if (channel >= ((nu_eadc_t)device)->eadc_max_ch_num)
+ return -(RT_EINVAL);
+
+ if (enabled)
+ {
+ if (*peadc_reg_tab == 0)
+ {
+ EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);
+ }
+
+ *peadc_reg_tab |= (0x1 << channel);
+ }
+ else
+ {
+ *peadc_reg_tab &= ~(0x1 << channel);
+
+ if (*peadc_reg_tab == 0)
+ {
+ EADC_Close(eadc_base);
+ }
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(value != RT_NULL);
+
+ EADC_T *eadc_base = ((nu_eadc_t)device)->eadc_base;
+ int *peadc_reg_tab = &((nu_eadc_t)device)->eadc_reg_tab;
+
+ if (channel >= ((nu_eadc_t)device)->eadc_max_ch_num)
+ {
+ *value = 0xFFFFFFFF;
+ return -(RT_EINVAL);
+ }
+
+ if ((*peadc_reg_tab & (1 << channel)) == 0)
+ {
+ *value = 0xFFFFFFFF;
+ return -(RT_EBUSY);
+ }
+
+ EADC_ConfigSampleModule(eadc_base, 0, EADC_SOFTWARE_TRIGGER, channel);
+
+ EADC_CLR_INT_FLAG(eadc_base, EADC_STATUS2_ADIF0_Msk);
+
+ EADC_ENABLE_INT(eadc_base, BIT0);
+
+ EADC_ENABLE_SAMPLE_MODULE_INT(eadc_base, 0, BIT0);
+
+ EADC_START_CONV(eadc_base, BIT0);
+
+ while (EADC_GET_INT_FLAG(eadc_base, BIT0) == 0);
+
+ *value = EADC_GET_CONV_DATA(eadc_base, 0);
+
+ return RT_EOK;
+}
+
+int rt_hw_eadc_init(void)
+{
+ rt_err_t result = RT_ERROR;
+ int nu_sel = 0;
+
+ while (nu_eadc_arr[nu_sel].name != 0)
+ {
+ nu_eadc_arr[nu_sel].eadc_reg_tab = 0;
+
+ result = rt_hw_adc_register(&nu_eadc_arr[nu_sel].dev, nu_eadc_arr[nu_sel].name, &nu_adc_ops, NULL);
+ RT_ASSERT(result == RT_EOK);
+ nu_sel++;
+ }
+
+ return result;
+}
+INIT_BOARD_EXPORT(rt_hw_eadc_init);
+
+
+#endif //#if defined(BSP_USING_EADC)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.c
new file mode 100644
index 00000000000..aa20ab8e83f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.c
@@ -0,0 +1,38 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-3-4 Philo First version
+*
+******************************************************************************/
+#include
+
+#ifdef BSP_USING_EBI
+#define MAX_BANK EBI_BANK2
+
+/* Private variables ------------------------------------------------------------*/
+static uint8_t nu_ebi_bank_mask = 0;
+
+/* Public functions -------------------------------------------------------------*/
+rt_err_t nu_ebi_init(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
+{
+ if (u32Bank > MAX_BANK)
+ return -(RT_ERROR);
+
+ /* Check this bank is not used */
+ if ((1 << u32Bank) & nu_ebi_bank_mask)
+ return -(RT_ERROR);
+
+ /* Initialize EBI */
+ EBI_Open(u32Bank, u32DataWidth, u32TimingClass, u32BusMode, u32CSActiveLevel);
+
+ nu_ebi_bank_mask |= (1 << u32Bank);
+
+ return RT_EOK;
+}
+
+#endif //BSP_USING_EBI
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h
new file mode 100644
index 00000000000..1b5aa5abd40
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h
@@ -0,0 +1,48 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-3-5 Philo First version
+*
+******************************************************************************/
+#ifndef __DRV_EBI_H___
+#define __DRV_EBI_H___
+
+#include
+#include
+
+/**
+ * @brief Initialize EBI for specify Bank
+ *
+ * @param[in] u32Bank Bank number for EBI. Valid values are:
+ * - \ref EBI_BANK0
+ * - \ref EBI_BANK1
+ * - \ref EBI_BANK2
+ * @param[in] u32DataWidth Data bus width. Valid values are:
+ * - \ref EBI_BUSWIDTH_8BIT
+ * - \ref EBI_BUSWIDTH_16BIT
+ * @param[in] u32TimingClass Default timing configuration. Valid values are:
+ * - \ref EBI_TIMING_FASTEST
+ * - \ref EBI_TIMING_VERYFAST
+ * - \ref EBI_TIMING_FAST
+ * - \ref EBI_TIMING_NORMAL
+ * - \ref EBI_TIMING_SLOW
+ * - \ref EBI_TIMING_VERYSLOW
+ * - \ref EBI_TIMING_SLOWEST
+ * @param[in] u32BusMode Set EBI bus operate mode. Valid values are:
+ * - \ref EBI_OPMODE_NORMAL
+ * - \ref EBI_OPMODE_CACCESS
+ * - \ref EBI_OPMODE_ADSEPARATE
+ * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are:
+ * - \ref EBI_CS_ACTIVE_HIGH
+ * - \ref EBI_CS_ACTIVE_LOW
+ *
+ * @return RT_EOK/RT_ERROR Bank is used or not
+ */
+rt_err_t nu_ebi_init(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
+
+#endif // __DRV_EBI_H___
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c
new file mode 100644
index 00000000000..c714338d9e2
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c
@@ -0,0 +1,451 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-5-21 Philo First version
+*
+******************************************************************************/
+#include
+
+#if defined(BSP_USING_ECAP)
+#include
+#include
+
+#define ECAP_CH0_POS (0)
+#define ECAP_CH1_POS (1)
+#define ECAP_CH2_POS (2)
+
+#define ECAP_CHANNEL_NUM 0x3
+#define ECAP_CLK_DIV ECAP_CAPTURE_TIMER_CLKDIV_32
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct _ecap_dev
+{
+ ECAP_T *ecap_base;
+ float fUsPerTick;
+} nu_ecap_dev_t;
+
+typedef struct _ecap
+{
+ struct rt_inputcapture_device parent;
+ nu_ecap_dev_t *ecap_dev;
+ uint8_t u8Channel;
+ rt_bool_t bfirstData;
+ uint32_t u32CurrentCnt;
+ uint32_t u32LastCnt;
+ rt_bool_t input_data_level;
+} nu_capture_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture);
+static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture);
+static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture);
+static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us);
+
+/* Private define ---------------------------------------------------------------*/
+#define NU_ECAP_GET_LEVEL(status, channel) ((status&(ECAP_STATUS_CAP0_Msk<CTL1 = ((ecap)->CTL1 & ECAP_CTL1_CLKSEL_Msk)>>ECAP_CTL1_CLKSEL_Pos)
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+#if (BSP_USING_ECAP0_CHMSK!=0)
+static const char *nu_ecap0_device_name[ECAP_CHANNEL_NUM] = { "ecap0i0", "ecap0i1", "ecap0i2" };
+static nu_capture_t *nu_ecap0_capture[ECAP_CHANNEL_NUM] = {0};
+static nu_ecap_dev_t nu_ecap0_dev = {.ecap_base = ECAP0};
+#endif
+
+#if (BSP_USING_ECAP1_CHMSK!=0)
+static const char *nu_ecap1_device_name[ECAP_CHANNEL_NUM] = { "ecap1i0", "ecap1i1", "ecap1i2" };
+static nu_capture_t *nu_ecap1_capture[ECAP_CHANNEL_NUM] = {0};
+static nu_ecap_dev_t nu_ecap1_dev = {.ecap_base = ECAP1};
+#endif
+
+static struct rt_inputcapture_ops nu_capture_ops =
+{
+ .init = nu_capture_init,
+ .open = nu_capture_open,
+ .close = nu_capture_close,
+ .get_pulsewidth = nu_capture_get_pulsewidth,
+};
+
+/* Functions define ------------------------------------------------------------*/
+#if (BSP_USING_ECAP0_CHMSK!=0)
+void ECAP0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uint32_t u32Status;
+
+ /* Get input Capture status */
+ u32Status = ECAP_GET_INT_STATUS(ECAP0);
+
+#if (BSP_USING_ECAP0_CHMSK & (0x1<input_data_level = RT_FALSE;
+ }
+ else
+ {
+ nu_ecap0_capture[0]->input_data_level = RT_TRUE;
+ }
+
+ nu_ecap0_capture[0]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP0, ECAP_IC0);
+
+ rt_hw_inputcapture_isr(&nu_ecap0_capture[0]->parent, nu_ecap0_capture[0]->input_data_level);
+ }
+#endif
+
+
+#if (BSP_USING_ECAP0_CHMSK & (0x1<input_data_level = RT_FALSE;
+ }
+ else
+ {
+ nu_ecap0_capture[1]->input_data_level = RT_TRUE;
+ }
+
+ nu_ecap0_capture[1]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP0, ECAP_IC1);
+
+ rt_hw_inputcapture_isr(&nu_ecap0_capture[1]->parent, nu_ecap0_capture[1]->input_data_level);
+ }
+#endif
+
+#if (BSP_USING_ECAP0_CHMSK & (0x1<input_data_level = RT_FALSE;
+ }
+ else
+ {
+ nu_ecap0_capture[2]->input_data_level = RT_TRUE;
+ }
+
+ nu_ecap0_capture[2]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP0, ECAP_IC2);
+
+ rt_hw_inputcapture_isr(&nu_ecap0_capture[2]->parent, nu_ecap0_capture[2]->input_data_level);
+ }
+#endif
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif //(BSP_USING_ECAP0_CHMSK!=0)
+
+
+#if (BSP_USING_ECAP1_CHMSK!=0)
+void ECAP1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uint32_t u32Status;
+
+ /* Get input Capture status */
+ u32Status = ECAP_GET_INT_STATUS(ECAP1);
+
+#if (BSP_USING_ECAP1_CHMSK & (0x1<input_data_level = RT_FALSE;
+ }
+ else
+ {
+ nu_ecap1_capture[0]->input_data_level = RT_TRUE;
+ }
+
+ nu_ecap1_capture[0]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP1, ECAP_IC0);
+
+ rt_hw_inputcapture_isr(&nu_ecap1_capture[0]->parent, nu_ecap1_capture[0]->input_data_level);
+ }
+#endif
+
+
+#if (BSP_USING_ECAP1_CHMSK & (0x1<input_data_level = RT_FALSE;
+ }
+ else
+ {
+ nu_ecap1_capture[1]->input_data_level = RT_TRUE;
+ }
+
+ nu_ecap1_capture[1]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP1, ECAP_IC1);
+
+ rt_hw_inputcapture_isr(&nu_ecap1_capture[1]->parent, nu_ecap1_capture[1]->input_data_level);
+ }
+#endif
+
+#if (BSP_USING_ECAP1_CHMSK & (0x1<input_data_level = RT_FALSE;
+ }
+ else
+ {
+ nu_ecap1_capture[2]->input_data_level = RT_TRUE;
+ }
+
+ nu_ecap1_capture[2]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP1, ECAP_IC2);
+
+ rt_hw_inputcapture_isr(&nu_ecap1_capture[2]->parent, nu_ecap1_capture[2]->input_data_level);
+ }
+#endif
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif //(BSP_USING_ECAP1_CHMSK!=0)
+
+static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us)
+{
+ rt_err_t ret = RT_EOK;
+ nu_capture_t *nu_capture;
+ float fTempCnt;
+
+ nu_capture = (nu_capture_t *)inputcapture;
+
+ if (nu_capture->bfirstData)
+ {
+ nu_capture->bfirstData = RT_FALSE;
+ ret = RT_ERROR;
+
+ return -(ret);
+ }
+
+ if (nu_capture->u32CurrentCnt > nu_capture->u32LastCnt)
+ fTempCnt = nu_capture->u32CurrentCnt - nu_capture->u32LastCnt;
+ else /* Overrun case */
+ fTempCnt = nu_capture->u32CurrentCnt + ((0x1000000 - nu_capture->u32LastCnt) + 1);
+
+ *pulsewidth_us =(int)(fTempCnt * nu_capture->ecap_dev->fUsPerTick);
+
+ nu_capture->u32LastCnt = nu_capture->u32CurrentCnt;
+
+ return -(ret);
+}
+
+static float get_ecap_tick_time_us(nu_capture_t *nu_capture)
+{
+ uint8_t u8ClockDivider[8] = { 1, 4, 16, 32, 64, 96, 112, 128};
+ if (nu_capture->ecap_dev->ecap_base == ECAP0)
+ return ((float)1000000 / ((float)CLK_GetPCLK0Freq() / u8ClockDivider[(nu_capture->ecap_dev->ecap_base->CTL1 & ECAP_CTL1_CLKSEL_Msk) >> ECAP_CTL1_CLKSEL_Pos]));
+ else
+ return ((float)1000000 / ((float)CLK_GetPCLK1Freq() / u8ClockDivider[(nu_capture->ecap_dev->ecap_base->CTL1 & ECAP_CTL1_CLKSEL_Msk) >> ECAP_CTL1_CLKSEL_Pos]));
+}
+
+static rt_err_t nu_ecap_init(nu_capture_t *nu_capture)
+{
+ rt_err_t ret = RT_ERROR;
+ static rt_bool_t bECAP0Inited = RT_FALSE;
+ static rt_bool_t bECAP1Inited = RT_FALSE;
+
+ if (nu_capture->ecap_dev->ecap_base == ECAP0)
+ {
+ if (bECAP0Inited == RT_FALSE)
+ {
+ /* Enable ECAP0 clock */
+ SYS_UnlockReg();
+ CLK_EnableModuleClock(ECAP0_MODULE);
+ SYS_LockReg();
+
+ NVIC_EnableIRQ(ECAP0_IRQn);
+ bECAP0Inited = RT_TRUE;
+ }
+ else
+ {
+ return ret = RT_EOK;
+ }
+ }
+ else if (nu_capture->ecap_dev->ecap_base == ECAP1)
+ {
+ if (bECAP1Inited == RT_FALSE)
+ {
+ /* Enable ECAP1 clock */
+ SYS_UnlockReg();
+ CLK_EnableModuleClock(ECAP1_MODULE);
+ SYS_LockReg();
+
+ NVIC_EnableIRQ(ECAP1_IRQn);
+ bECAP1Inited = RT_TRUE;
+ }
+ else
+ {
+ return ret = RT_EOK;
+ }
+ }
+ else
+ {
+ return ret;
+ }
+
+ /* Enable ECAP */
+ ECAP_Open(nu_capture->ecap_dev->ecap_base, ECAP_DISABLE_COMPARE);
+
+ ECAP_SEL_TIMER_CLK_DIV(nu_capture->ecap_dev->ecap_base, ECAP_CLK_DIV);
+
+ /* Select Reload function */
+ ECAP_SET_CNT_CLEAR_EVENT(nu_capture->ecap_dev->ecap_base, ECAP_CTL1_OVRLDEN_Msk);
+
+ /* Enable ECAP0 source IC */
+ ECAP_SEL_INPUT_SRC(nu_capture->ecap_dev->ecap_base, ECAP_IC0, ECAP_CAP_INPUT_SRC_FROM_IC);
+ ECAP_SEL_INPUT_SRC(nu_capture->ecap_dev->ecap_base, ECAP_IC1, ECAP_CAP_INPUT_SRC_FROM_IC);
+ ECAP_SEL_INPUT_SRC(nu_capture->ecap_dev->ecap_base, ECAP_IC2, ECAP_CAP_INPUT_SRC_FROM_IC);
+
+ /* Select IC detect rising edge */
+ ECAP_SEL_CAPTURE_EDGE(nu_capture->ecap_dev->ecap_base, ECAP_IC0, ECAP_RISING_FALLING_EDGE);
+ ECAP_SEL_CAPTURE_EDGE(nu_capture->ecap_dev->ecap_base, ECAP_IC1, ECAP_RISING_FALLING_EDGE);
+ ECAP_SEL_CAPTURE_EDGE(nu_capture->ecap_dev->ecap_base, ECAP_IC2, ECAP_RISING_FALLING_EDGE);
+
+ ret = RT_EOK;
+
+ return -(ret);
+}
+
+static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture)
+{
+ rt_err_t ret = RT_EOK;
+ nu_capture_t *nu_capture;
+
+ RT_ASSERT(inputcapture != RT_NULL);
+
+ nu_capture = (nu_capture_t *) inputcapture;
+
+ if (nu_ecap_init(nu_capture) != RT_EOK)
+ {
+ rt_kprintf("Failed to initialize ECAP.\n");
+ ret = RT_ERROR;
+ }
+
+ return -(ret);
+}
+
+static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture)
+{
+ rt_err_t ret = RT_EOK;
+ nu_capture_t *nu_capture;
+
+ RT_ASSERT(inputcapture != RT_NULL);
+
+ nu_capture = (nu_capture_t *) inputcapture;
+
+ nu_capture->ecap_dev->fUsPerTick = get_ecap_tick_time_us(nu_capture);
+
+ /* Enable ECAP Input Channel */
+ ECAP_ENABLE_INPUT_CHANNEL(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_IC0EN_Pos + nu_capture->u8Channel));
+
+ /* Input Channel interrupt enabled */
+ ECAP_EnableINT(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_CAPIEN0_Pos + nu_capture->u8Channel));
+
+ /* ECAP_CNT starts up-counting */
+ ECAP_CNT_START(nu_capture->ecap_dev->ecap_base);
+
+ return ret;
+}
+
+static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture)
+{
+ rt_err_t ret = RT_EOK;
+
+ nu_capture_t *nu_capture;
+
+ RT_ASSERT(inputcapture != RT_NULL);
+
+ nu_capture = (nu_capture_t *) inputcapture;
+
+ /* Input Channel interrupt disabled */
+ ECAP_DisableINT(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_CAPIEN0_Pos + nu_capture->u8Channel));
+
+ /* Disable ECAP Input Channel */
+ ECAP_DISABLE_INPUT_CHANNEL(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_IC0EN_Pos + nu_capture->u8Channel));
+
+ /* Clear input capture channel flag */
+ ECAP_CLR_CAPTURE_FLAG(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_STATUS_CAPTF0_Pos + nu_capture->u8Channel));
+
+ return ret;
+}
+
+static void ecap_init(nu_capture_t *nu_capture, uint8_t u8Channel, nu_ecap_dev_t *ecap_dev, const char *device_name)
+{
+ nu_capture->ecap_dev = ecap_dev;
+ nu_capture->u8Channel = u8Channel;
+ nu_capture->bfirstData = RT_TRUE;
+ nu_capture->u32CurrentCnt = 0;
+ nu_capture->u32LastCnt = 0;
+ nu_capture->parent.ops = &nu_capture_ops;
+
+ /* register inputcapture device */
+ rt_device_inputcapture_register(&nu_capture->parent, device_name, &nu_capture);
+}
+
+/* Init and register ecap capture */
+static int nu_ecap_capture_device_init(void)
+{
+ for (int i = 0; i < ECAP_CHANNEL_NUM; i++)
+ {
+#if (BSP_USING_ECAP0_CHMSK!=0)
+ if (BSP_USING_ECAP0_CHMSK & (0x1 << i))
+ {
+ nu_ecap0_capture[i] = (nu_capture_t*)rt_malloc(sizeof(nu_capture_t));
+ ecap_init(nu_ecap0_capture[i], i, &nu_ecap0_dev, nu_ecap0_device_name[i]);
+ }
+#endif //#if (BSP_USING_ECAP0_CHMSK!=0)
+
+#if (BSP_USING_ECAP1_CHMSK!=0)
+ if (BSP_USING_ECAP1_CHMSK & (0x1 << i))
+ {
+ nu_ecap1_capture[i] = (nu_capture_t*)rt_malloc(sizeof(nu_capture_t));
+ ecap_init(nu_ecap1_capture[i], i, &nu_ecap1_dev, nu_ecap1_device_name[i]);
+ }
+#endif //#if (BSP_USING_ECAP1_CHMSK!=0)
+ }
+
+ return 0;
+}
+INIT_DEVICE_EXPORT(nu_ecap_capture_device_init);
+
+#endif //#if defined(BSP_USING_ECAP)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c
new file mode 100644
index 00000000000..b612e708d25
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c
@@ -0,0 +1,515 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-7 Wayne First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_EMAC)
+
+#if defined(RT_USING_LWIP)
+
+#include
+#include
+#include
+#include
+#include
+#include "lwipopts.h"
+
+
+#include "drv_pdma.h"
+
+/* Private define ---------------------------------------------------------------*/
+// RT_DEV_NAME_PREFIX e
+
+#if !defined(NU_EMAC_PDMA_MEMCOPY)
+ #define NU_EMAC_PDMA_MEMCOPY
+#endif
+
+#if !defined(NU_EMAC_PDMA_MEMCOPY_THRESHOLD)
+ #define NU_EMAC_PDMA_MEMCOPY_THRESHOLD 128
+#endif
+
+#define NU_EMAC_DEBUG
+#if defined(NU_EMAC_DEBUG)
+ // #define NU_EMAC_RX_DUMP
+ // #define NU_EMAC_TX_DUMP
+ #define NU_EMAC_TRACE rt_kprintf
+#else
+ #define NU_EMAC_TRACE(...)
+#endif
+
+#define NU_EMAC_TID_STACK_SIZE 256
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_emac
+{
+ struct eth_device eth;
+ rt_uint8_t mac_addr[6];
+ struct rt_semaphore eth_sem;
+};
+typedef struct nu_emac *nu_emac_t;
+
+/* Private functions ------------------------------------------------------------*/
+#if defined(NU_EMAC_RX_DUMP) || defined(NU_EMAC_TX_DUMP)
+ static void nu_emac_pkt_dump(const char *msg, const struct pbuf *p);
+#endif
+#if LWIP_IPV4 && LWIP_IGMP
+ static err_t nu_igmp_mac_filter(struct netif *netif, const ip4_addr_t *ip4_addr, enum netif_mac_filter_action action);
+#endif
+static void nu_emac_halt(void);
+static void nu_emac_reinit(void);
+static void link_monitor(void *param);
+static rt_err_t nu_emac_init(rt_device_t dev);
+
+static rt_err_t nu_emac_open(rt_device_t dev, rt_uint16_t oflag);
+static rt_err_t nu_emac_close(rt_device_t dev);
+static rt_size_t nu_emac_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size);
+static rt_size_t nu_emac_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size);
+static rt_err_t nu_emac_control(rt_device_t dev, int cmd, void *args);
+static rt_err_t nu_emac_tx(rt_device_t dev, struct pbuf *p);
+static struct pbuf *nu_emac_rx(rt_device_t dev);
+static rt_err_t rt_hw_nu_emac_register(char *dev_name);
+static int rt_hw_nu_emac_init(void);
+static void *nu_emac_memcpy(void *dest, void *src, unsigned int count);
+
+/* Public functions -------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+static struct nu_emac nu_emac_dev = {0};
+static struct rt_thread eth_tid;
+static rt_uint8_t eth_stack[NU_EMAC_TID_STACK_SIZE];
+
+#if defined(NU_EMAC_RX_DUMP) || defined(NU_EMAC_TX_DUMP)
+static void nu_emac_pkt_dump(const char *msg, const struct pbuf *p)
+{
+ rt_uint32_t i;
+ rt_uint8_t *ptr = p->payload;
+
+ NU_EMAC_TRACE("%s %d byte\n", msg, p->tot_len);
+
+ for (i = 0; i < p->tot_len; i++)
+ {
+ if ((i % 8) == 0)
+ {
+ NU_EMAC_TRACE(" ");
+ }
+ if ((i % 16) == 0)
+ {
+ NU_EMAC_TRACE("\r\n");
+ }
+ NU_EMAC_TRACE("%02x ", *ptr);
+ ptr++;
+ }
+ NU_EMAC_TRACE("\n\n");
+}
+#endif /* dump */
+
+static void nu_emac_halt(void)
+{
+ EMAC_DISABLE_RX();
+ EMAC_DISABLE_TX();
+}
+
+static void *nu_emac_memcpy(void *dest, void *src, unsigned int count)
+{
+#if defined(NU_EMAC_PDMA_MEMCOPY)
+ if (count >= NU_EMAC_PDMA_MEMCOPY_THRESHOLD)
+ return nu_pdma_memcpy(dest, src, count);
+#endif
+ return memcpy(dest, src, count);
+}
+
+static void nu_emac_reinit(void)
+{
+ rt_uint32_t EMAC_CAMxM[EMAC_CAMENTRY_NB];
+ rt_uint32_t EMAC_CAMxL[EMAC_CAMENTRY_NB];
+ rt_uint32_t EMAC_CAMEN;
+
+ // Backup MAC address.
+ EMAC_CAMEN = EMAC->CAMEN;
+ for (rt_uint8_t index = 0 ; index < EMAC_CAMENTRY_NB; index ++)
+ {
+ rt_uint32_t *CAMxM = (rt_uint32_t *)((rt_uint32_t)&EMAC->CAM0M + (index * 8));
+ rt_uint32_t *CAMxL = (rt_uint32_t *)((rt_uint32_t)&EMAC->CAM0L + (index * 8));
+
+ EMAC_CAMxM[index] = *CAMxM;
+ EMAC_CAMxL[index] = *CAMxL;
+ }
+
+ nu_emac_halt();
+ EMAC_Close();
+ EMAC_Open((uint8_t *)&nu_emac_dev.mac_addr[0]);
+ EMAC_ENABLE_TX();
+ EMAC_ENABLE_RX();
+
+ // Restore MAC address.
+ for (rt_uint8_t index = 0 ; index < EMAC_CAMENTRY_NB; index ++)
+ {
+ rt_uint32_t *CAMxM = (rt_uint32_t *)((rt_uint32_t)&EMAC->CAM0M + (index * 8));
+ rt_uint32_t *CAMxL = (rt_uint32_t *)((rt_uint32_t)&EMAC->CAM0L + (index * 8));
+
+ *CAMxM = EMAC_CAMxM[index];
+ *CAMxL = EMAC_CAMxL[index];
+ }
+ EMAC->CAMEN = EMAC_CAMEN;
+}
+
+#if LWIP_IPV4 && LWIP_IGMP
+static err_t nu_igmp_mac_filter(struct netif *netif, const ip4_addr_t *ip4_addr, enum netif_mac_filter_action action)
+{
+ rt_uint8_t mac[6];
+ int32_t ret = 0;
+ const uint8_t *p = (const uint8_t *)ip4_addr;
+
+ mac[0] = 0x01;
+ mac[1] = 0x00;
+ mac[2] = 0x5E;
+ mac[3] = *(p + 1) & 0x7F;
+ mac[4] = *(p + 2);
+ mac[5] = *(p + 3);
+
+ ret = EMAC_FillCamEntry((uint8_t *)&mac[0]);
+ if (ret >= 0)
+ {
+ NU_EMAC_TRACE("%s %s %s ", __FUNCTION__, (action == NETIF_ADD_MAC_FILTER) ? "add" : "del", ip4addr_ntoa(ip4_addr));
+ NU_EMAC_TRACE("%02X:%02X:%02X:%02X:%02X:%02X\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ }
+
+ return (ret >= 0) ? RT_EOK : -(RT_ERROR);
+}
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+
+static void link_monitor(void *param)
+{
+ nu_emac_t psNuEMAC = (nu_emac_t)param;
+ uint32_t LinkStatus_Last = EMAC_LINK_DOWN;
+
+ EMAC_PhyInit();
+
+ while (1)
+ {
+ uint32_t LinkStatus_Current = EMAC_CheckLinkStatus();
+ /* linkchange */
+ if (LinkStatus_Last != LinkStatus_Current)
+ {
+
+ switch (LinkStatus_Current)
+ {
+ case EMAC_LINK_DOWN:
+ NU_EMAC_TRACE("Link status: Down\n");
+ break;
+
+ case EMAC_LINK_100F:
+ NU_EMAC_TRACE("Link status: 100F\n");
+ break;
+
+ case EMAC_LINK_100H:
+ NU_EMAC_TRACE("Link status: 100H\n");
+ break;
+
+ case EMAC_LINK_10F:
+ NU_EMAC_TRACE("Link status: 10F\n");
+ break;
+
+ case EMAC_LINK_10H:
+ NU_EMAC_TRACE("Link status: 10H\n");
+ break;
+ } /* switch( LinkStatus_Current ) */
+
+ /* Send link status to upper layer. */
+ if (LinkStatus_Current == EMAC_LINK_DOWN)
+ eth_device_linkchange(&psNuEMAC->eth, RT_FALSE);
+ else
+ eth_device_linkchange(&psNuEMAC->eth, RT_TRUE);
+
+ LinkStatus_Last = LinkStatus_Current;
+
+ } /* if ( LinkStatus_Last != LinkStatus_Current ) */
+
+ rt_thread_delay(RT_TICK_PER_SECOND);
+
+ } /* while(1) */
+
+}
+
+static rt_err_t nu_emac_init(rt_device_t dev)
+{
+ nu_emac_t psNuEMAC = (nu_emac_t)dev;
+
+ EMAC_Close();
+ EMAC_Open((uint8_t *)&psNuEMAC->mac_addr[0]);
+ EMAC_ENABLE_RX();
+ EMAC_ENABLE_TX();
+
+ NVIC_SetPriority(EMAC_TX_IRQn, 1);
+ NVIC_EnableIRQ(EMAC_TX_IRQn);
+ NVIC_SetPriority(EMAC_RX_IRQn, 1);
+ NVIC_EnableIRQ(EMAC_RX_IRQn);
+
+ rt_sem_init(&psNuEMAC->eth_sem, "eth_sem", 0, RT_IPC_FLAG_FIFO);
+
+ rt_thread_init(ð_tid, "eth", link_monitor, (void *)psNuEMAC, eth_stack, sizeof(eth_stack), RT_THREAD_PRIORITY_MAX - 2, 10);
+ rt_thread_startup(ð_tid);
+
+#if defined(LWIP_IPV4) && defined(LWIP_IGMP)
+ netif_set_igmp_mac_filter(psNuEMAC->eth.netif, nu_igmp_mac_filter);
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_emac_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ return RT_EOK;
+}
+
+static rt_err_t nu_emac_close(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_size_t nu_emac_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
+}
+
+static rt_size_t nu_emac_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
+}
+
+static rt_err_t nu_emac_control(rt_device_t dev, int cmd, void *args)
+{
+ nu_emac_t psNuEMAC = (nu_emac_t)dev;
+ switch (cmd)
+ {
+ case NIOCTL_GADDR:
+ /* Get MAC address */
+ if (args)
+ rt_memcpy(args, &psNuEMAC->mac_addr[0], 6);
+ else
+ return -RT_ERROR;
+
+ break;
+ default :
+ break;
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_emac_tx(rt_device_t dev, struct pbuf *p)
+{
+ nu_emac_t psNuEMAC = (nu_emac_t)dev;
+ struct pbuf *q;
+ rt_uint32_t offset = 0;
+
+ rt_uint8_t *buf = (rt_uint8_t *)EMAC_ClaimFreeTXBuf();
+
+ /* Get free TX buffer */
+ if (buf == RT_NULL)
+ {
+ rt_sem_control(&psNuEMAC->eth_sem, RT_IPC_CMD_RESET, 0);
+
+ EMAC_CLEAR_INT_FLAG(EMAC, EMAC_INTSTS_TXCPIF_Msk);
+ EMAC_ENABLE_INT(EMAC, EMAC_INTEN_TXCPIEN_Msk);
+
+ do
+ {
+ rt_sem_take(&psNuEMAC->eth_sem, 1);
+ buf = (rt_uint8_t *)EMAC_ClaimFreeTXBuf();
+ }
+ while (buf == RT_NULL);
+ }
+
+ for (q = p; q != NULL; q = q->next)
+ {
+ rt_uint8_t *ptr;
+ rt_uint32_t len;
+
+ len = q->len;
+ ptr = q->payload;
+
+ nu_emac_memcpy(&buf[offset], ptr, len);
+
+ offset += len;
+ }
+
+#if defined(NU_EMAC_TX_DUMP)
+ nu_emac_pkt_dump("TX dump", p);
+#endif
+
+ /* Return SUCCESS */
+ return (EMAC_SendPktWoCopy(offset) == 1) ? RT_EOK : RT_ERROR;
+}
+
+static struct pbuf *nu_emac_rx(rt_device_t dev)
+{
+ struct pbuf *p = RT_NULL;
+ uint8_t *pu8DataBuf = NULL;
+ unsigned int avaialbe_size;
+
+ if ((avaialbe_size = EMAC_GetAvailRXBufSize(&pu8DataBuf)) > 0)
+ {
+ /* Allocate RX packet buffer. */
+ p = pbuf_alloc(PBUF_RAW, avaialbe_size, PBUF_RAM);
+ if (p != RT_NULL)
+ {
+ RT_ASSERT(p->next == RT_NULL);
+ nu_emac_memcpy((void *)p->payload, (void *)pu8DataBuf, avaialbe_size);
+
+#if defined(NU_EMAC_RX_DUMP)
+ nu_emac_pkt_dump("RX dump", p);
+#endif
+ }
+ else
+ {
+ NU_EMAC_TRACE("Can't allocate memory for RX packet.(%d)\n", avaialbe_size);
+ }
+
+ /* Update RX descriptor */
+ EMAC_RecvPktDoneWoRxTrigger();
+
+ } // if ( (avaialbe_size= EMAC_GetAvaiableRXBufSize()) > 0 )
+ else
+ {
+ /* No avaiable RX packet, we enable RXGD/RDUIEN interrupts. */
+ if (!(EMAC->INTEN & EMAC_INTEN_RDUIEN_Msk))
+ {
+ EMAC_CLEAR_INT_FLAG(EMAC, (EMAC_INTSTS_RDUIF_Msk | EMAC_INTSTS_RXGDIF_Msk));
+ EMAC_ENABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk));
+ }
+ else
+ {
+ EMAC_CLEAR_INT_FLAG(EMAC, EMAC_INTSTS_RXGDIF_Msk);
+ EMAC_ENABLE_INT(EMAC, EMAC_INTEN_RXGDIEN_Msk);
+ }
+ EMAC_TRIGGER_RX();
+ } //else
+
+ return p;
+}
+
+void EMAC_RX_IRQHandler(void)
+{
+ /* Enter interrupt */
+ rt_interrupt_enter();
+
+ /* No RX descriptor avaiable, we need to get data from RX pool */
+ if (EMAC_GET_INT_FLAG(EMAC, EMAC_INTSTS_RDUIF_Msk))
+ {
+ EMAC_DISABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk));
+ eth_device_ready(&nu_emac_dev.eth);
+ }
+ /* A good packet ready. */
+ else if (EMAC_GET_INT_FLAG(EMAC, EMAC_INTSTS_RXGDIF_Msk))
+ {
+ EMAC_DISABLE_INT(EMAC, EMAC_INTEN_RXGDIEN_Msk);
+ eth_device_ready(&nu_emac_dev.eth);
+ }
+
+ /* Receive Bus Error Interrupt */
+ if (EMAC_GET_INT_FLAG(EMAC, EMAC_INTSTS_RXBEIF_Msk))
+ {
+ NU_EMAC_TRACE("Reinit Rx EMAC\n");
+ EMAC_CLEAR_INT_FLAG(EMAC, EMAC_INTSTS_RXBEIF_Msk);
+ nu_emac_reinit();
+ }
+
+ /* Leave interrupt */
+ rt_interrupt_leave();
+}
+
+void EMAC_TX_IRQHandler(void)
+{
+ /* Enter interrupt */
+ rt_interrupt_enter();
+
+ unsigned int status = EMAC->INTSTS;
+
+ /* Wake-up suspended process to send */
+ if (EMAC_GET_INT_FLAG(EMAC, EMAC_INTSTS_TXCPIF_Msk))
+ {
+ EMAC_DISABLE_INT(EMAC, EMAC_INTEN_TXCPIEN_Msk);
+ rt_sem_release(&nu_emac_dev.eth_sem);
+ }
+
+ if (EMAC_GET_INT_FLAG(EMAC, EMAC_INTSTS_TXBEIF_Msk))
+ {
+ NU_EMAC_TRACE("Reinit Tx EMAC\n");
+ EMAC->INTSTS = EMAC_INTSTS_TXBEIF_Msk;
+ EMAC_CLEAR_INT_FLAG(EMAC, EMAC_INTSTS_TXBEIF_Msk);
+ nu_emac_reinit();
+ }
+ else
+ EMAC_SendPktDone();
+
+ /* Leave interrupt */
+ rt_interrupt_leave();
+}
+
+static rt_err_t rt_hw_nu_emac_register(char *dev_name)
+{
+ rt_uint32_t value = 0;
+ nu_emac_t psNuEMAC = (nu_emac_t)&nu_emac_dev;
+
+ /* Read UID from FMC */
+ SYS_UnlockReg();
+ FMC_Open();
+ for (rt_uint8_t i = 0; i < 3; i++)
+ {
+ value += FMC_ReadUID(i);
+ }
+ FMC_Close();
+ SYS_LockReg();
+
+ /* Assign MAC address */
+ psNuEMAC->mac_addr[0] = 0x82;
+ psNuEMAC->mac_addr[1] = 0x06;
+ psNuEMAC->mac_addr[2] = 0x21;
+ psNuEMAC->mac_addr[3] = (value >> 16) & 0xff;
+ psNuEMAC->mac_addr[4] = (value >> 8) & 0xff;
+ psNuEMAC->mac_addr[5] = (value) & 0xff;
+ NU_EMAC_TRACE("MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", \
+ psNuEMAC->mac_addr[0], \
+ psNuEMAC->mac_addr[1], \
+ psNuEMAC->mac_addr[2], \
+ psNuEMAC->mac_addr[3], \
+ psNuEMAC->mac_addr[4], \
+ psNuEMAC->mac_addr[5]);
+
+ /* Register member functions */
+ psNuEMAC->eth.parent.init = nu_emac_init;
+ psNuEMAC->eth.parent.open = nu_emac_open;
+ psNuEMAC->eth.parent.close = nu_emac_close;
+ psNuEMAC->eth.parent.read = nu_emac_read;
+ psNuEMAC->eth.parent.write = nu_emac_write;
+ psNuEMAC->eth.parent.control = nu_emac_control;
+ psNuEMAC->eth.parent.user_data = RT_NULL;
+ psNuEMAC->eth.eth_rx = nu_emac_rx;
+ psNuEMAC->eth.eth_tx = nu_emac_tx;
+
+ /* Register eth device */
+ return eth_device_init(&nu_emac_dev.eth, dev_name);
+}
+
+static int rt_hw_nu_emac_init(void)
+{
+ return rt_hw_nu_emac_register("e0");
+}
+
+INIT_APP_EXPORT(rt_hw_nu_emac_init);
+
+#endif /* #if defined( RT_USING_LWIP ) */
+
+#endif /* #if defined( BSP_USING_EMAC ) */
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm.c
new file mode 100644
index 00000000000..ea4d29339e8
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm.c
@@ -0,0 +1,268 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-3-16 YH First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_EPWM)
+
+#define LOG_TAG "drv.epwm"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME "drv.epwm"
+#define DBG_LEVEL DBG_INFO
+#define DBG_COLOR
+#include
+
+#include
+#include
+#include
+#include "NuMicro.h"
+
+enum
+{
+ EPWM_START = -1,
+#if defined(BSP_USING_EPWM0)
+ EPWM0_IDX,
+#endif
+#if defined(BSP_USING_EPWM1)
+ EPWM1_IDX,
+#endif
+ EPWM_CNT
+};
+
+struct nu_epwm
+{
+ struct rt_device_pwm dev;
+ char *name;
+ EPWM_T *epwm_base;
+};
+
+typedef struct nu_epwm *nu_epwm_t;
+
+static struct nu_epwm nu_epwm_arr [] =
+{
+#if defined(BSP_USING_EPWM0)
+ {
+ .name = "epwm0",
+ .epwm_base = EPWM0,
+ },
+#endif
+
+#if defined(BSP_USING_EPWM1)
+ {
+ .name = "epwm1",
+ .epwm_base = EPWM1,
+ },
+#endif
+ {0}
+}; /* epwm nu_epwm */
+
+static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg);
+
+static struct rt_pwm_ops nu_epwm_ops =
+{
+ .control = nu_epwm_control
+};
+
+static rt_err_t nu_epwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+ rt_err_t result = RT_EOK;
+
+ EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
+ rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel;
+
+ if (enable == RT_TRUE)
+ {
+ EPWM_EnableOutput(pwm_base, 1 << pwm_channel);
+ EPWM_Start(pwm_base, 1 << pwm_channel);
+ }
+ else
+ {
+ EPWM_DisableOutput(pwm_base, 1 << pwm_channel);
+ EPWM_ForceStop(pwm_base, 1 << pwm_channel);
+ }
+
+ return result;
+}
+
+static rt_err_t nu_epwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+ if ((((struct rt_pwm_configuration *)configuration)->period) <= 0)
+ return -(RT_ERROR);
+ rt_uint8_t pwm_channel_pair;
+ rt_uint32_t pwm_freq, pwm_dutycycle ;
+ EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
+ rt_uint8_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel;
+ rt_uint32_t pwm_period = ((struct rt_pwm_configuration *)configuration)->period;
+ rt_uint32_t pwm_pulse = ((struct rt_pwm_configuration *)configuration)->pulse;
+ rt_uint32_t pre_pwm_prescaler = EPWM_GET_PRESCALER(pwm_base, pwm_channel);
+
+ if ((pwm_channel % 2) == 0)
+ pwm_channel_pair = pwm_channel + 1;
+ else
+ pwm_channel_pair = pwm_channel - 1;
+
+ pwm_freq = 1000000000 / pwm_period;
+ pwm_dutycycle = (pwm_pulse * 100) / pwm_period;
+
+ EPWM_ConfigOutputChannel(pwm_base, pwm_channel, pwm_freq, pwm_dutycycle) ;
+
+ if ((pre_pwm_prescaler != 0) || (EPWM_GET_CNR(pwm_base, pwm_channel_pair) != 0) || (EPWM_GET_CMR(pwm_base, pwm_channel_pair) != 0))
+ {
+ if (pre_pwm_prescaler < EPWM_GET_PRESCALER(pwm_base, pwm_channel))
+ {
+ EPWM_SET_CNR(pwm_base, pwm_channel_pair, ((EPWM_GET_CNR(pwm_base, pwm_channel_pair) + 1) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1));
+ EPWM_SET_CMR(pwm_base, pwm_channel_pair, (EPWM_GET_CMR(pwm_base, pwm_channel_pair) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1));
+ }
+ else if (pre_pwm_prescaler > EPWM_GET_PRESCALER(pwm_base, pwm_channel))
+ {
+ EPWM_SET_CNR(pwm_base, pwm_channel, ((EPWM_GET_CNR(pwm_base, pwm_channel) + 1) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1));
+ EPWM_SET_CMR(pwm_base, pwm_channel, (EPWM_GET_CMR(pwm_base, pwm_channel) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1));
+ }
+ }
+ return RT_EOK;
+}
+
+static rt_uint32_t nu_epwm_clksr(struct rt_device_pwm *device)
+{
+ rt_uint32_t u32Src, u32EPWMClockSrc;
+ EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
+ if (pwm_base == EPWM0)
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk;
+ }
+ else /* (epwm == EPWM1) */
+ {
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk;
+ }
+
+ if (u32Src == 0U)
+ {
+ /* clock source is from PLL clock */
+ u32EPWMClockSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ /* clock source is from PCLK */
+ SystemCoreClockUpdate();
+ if (pwm_base == EPWM0)
+ {
+ u32EPWMClockSrc = CLK_GetPCLK0Freq();
+ }
+ else /* (epwm == EPWM1) */
+ {
+ u32EPWMClockSrc = CLK_GetPCLK1Freq();
+ }
+ }
+ return u32EPWMClockSrc;
+}
+
+static rt_err_t nu_epwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+ rt_uint32_t pwm_real_period, pwm_real_duty, time_tick, u32EPWMClockSrc ;
+
+ EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
+ rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel;
+ rt_uint32_t pwm_prescale = EPWM_GET_PRESCALER(pwm_base, pwm_channel);
+ rt_uint32_t pwm_period = EPWM_GET_CNR(pwm_base, pwm_channel);
+ rt_uint32_t pwm_pulse = EPWM_GET_CMR(pwm_base, pwm_channel);
+
+ u32EPWMClockSrc = nu_epwm_clksr(device);
+ time_tick = 1000000000000 / u32EPWMClockSrc;
+
+ pwm_real_period = (((pwm_prescale + 1) * (pwm_period + 1)) * time_tick) / 1000;
+ pwm_real_duty = (((pwm_prescale + 1) * pwm_pulse * time_tick)) / 1000;
+ ((struct rt_pwm_configuration *)configuration)->period = pwm_real_period;
+ ((struct rt_pwm_configuration *)configuration)->pulse = pwm_real_duty;
+
+ LOG_I("%s %d %d %d\n", ((nu_epwm_t)device)->name, configuration->channel, configuration->period, configuration->pulse);
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+ struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(configuration != RT_NULL);
+
+ if (((((struct rt_pwm_configuration *)configuration)->channel) + 1) > EPWM_CHANNEL_NUM)
+ return -(RT_ERROR);
+
+ switch (cmd)
+ {
+ case PWM_CMD_ENABLE:
+ return nu_epwm_enable(device, configuration, RT_TRUE);
+ case PWM_CMD_DISABLE:
+ return nu_epwm_enable(device, configuration, RT_FALSE);
+ case PWM_CMD_SET:
+ return nu_epwm_set(device, configuration);
+ case PWM_CMD_GET:
+ return nu_epwm_get(device, configuration);
+ }
+ return -(RT_EINVAL);
+}
+
+int rt_hw_epwm_init(void)
+{
+ rt_err_t ret;
+ int i;
+
+ for (i = (EPWM_START + 1); i < EPWM_CNT; i++)
+ {
+ ret = rt_device_pwm_register(&nu_epwm_arr[i].dev, nu_epwm_arr[i].name, &nu_epwm_ops, RT_NULL);
+ RT_ASSERT(ret == RT_EOK);
+ }
+
+ return 0;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_epwm_init);
+
+#ifdef RT_USING_FINSH
+#include
+
+#ifdef FINSH_USING_MSH
+
+static int pwm_get(int argc, char **argv)
+{
+ int result = 0;
+ struct rt_device_pwm *device = RT_NULL;
+ struct rt_pwm_configuration configuration = {0};
+
+ if (argc != 3)
+ {
+ rt_kprintf("Usage: pwm_get pwm1 1\n");
+ result = -RT_ERROR;
+ goto _exit;
+ }
+
+ device = (struct rt_device_pwm *)rt_device_find(argv[1]);
+ if (!device)
+ {
+ result = -RT_EIO;
+ goto _exit;
+ }
+
+ configuration.channel = atoi(argv[2]);
+ result = rt_device_control(&device->parent, PWM_CMD_GET, &configuration);
+
+_exit:
+ return result;
+}
+
+MSH_CMD_EXPORT(pwm_get, pwm_get epwm1 1);
+
+#endif /* FINSH_USING_MSH */
+#endif /* RT_USING_FINSH */
+
+#endif
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c
new file mode 100644
index 00000000000..af21f643ec8
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c
@@ -0,0 +1,509 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-5-4 Philo First version
+*
+******************************************************************************/
+#include
+
+#if defined(BSP_USING_EPWM_CAPTURE)
+#include
+#include
+
+#define EPWM_CH0CH1_POS (0)
+#define EPWM_CH2CH3_POS (2)
+#define EPWM_CH4CH5_POS (4)
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct nu_capture
+{
+ struct rt_inputcapture_device parent;
+ EPWM_T *epwm;
+ uint8_t u8Channel;
+ IRQn_Type irq;
+ uint32_t u32CurrentRisingCnt;
+ uint32_t u32CurrentFallingCnt;
+ rt_bool_t input_data_level;
+} nu_capture_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture);
+static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture);
+static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture);
+static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us);
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0)
+static const char *nu_epwm0_device_name[EPWM_CHANNEL_NUM] = { "epwm0i0", "epwm0i1", "epwm0i2", "epwm0i3", "epwm0i4", "epwm0i5"};
+static const IRQn_Type nu_epwm0_irq[EPWM_CHANNEL_NUM / 2] = { EPWM0P0_IRQn, EPWM0P1_IRQn, EPWM0P2_IRQn};
+static nu_capture_t nu_epwm0_capture[EPWM_CHANNEL_NUM] = {0};
+#endif
+
+#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0)
+static const char *nu_epwm1_device_name[EPWM_CHANNEL_NUM] = {"epwm1i0", "epwm1i1", "epwm1i2", "epwm1i3", "epwm1i4", "epwm1i5", };
+static const IRQn_Type nu_epwm1_irq[EPWM_CHANNEL_NUM / 2] = {EPWM1P0_IRQn, EPWM1P1_IRQn, EPWM1P2_IRQn };
+static nu_capture_t nu_epwm1_capture[EPWM_CHANNEL_NUM] = {0};
+#endif
+
+static struct rt_inputcapture_ops nu_capture_ops =
+{
+ .init = nu_capture_init,
+ .open = nu_capture_open,
+ .close = nu_capture_close,
+ .get_pulsewidth = nu_capture_get_pulsewidth,
+};
+
+/* Functions define ------------------------------------------------------------*/
+static rt_err_t CalPulseWidth(nu_capture_t *nu_capture)
+{
+ rt_bool_t bWrapAroundFlag = RT_FALSE;
+
+ /* Check rising/falling capture counter is overflow or not */
+ if (EPWM_GetWrapAroundFlag(nu_capture->epwm, nu_capture->u8Channel))
+ {
+ EPWM_ClearWrapAroundFlag(nu_capture->epwm, nu_capture->u8Channel);
+ bWrapAroundFlag = RT_TRUE;
+ }
+
+ /* Read the capture counter value if falling/risning edge */
+ if (EPWM_GetCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel) == 1)//Rising edge
+ {
+ EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH);
+
+ if (bWrapAroundFlag)
+ {
+ nu_capture->u32CurrentRisingCnt = 0x10000;
+ }
+ nu_capture->u32CurrentRisingCnt += EPWM_GET_CAPTURE_RISING_DATA(nu_capture->epwm, nu_capture->u8Channel);
+ }
+ else if (EPWM_GetCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel) == 2)//Falling edge
+ {
+ EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH);
+
+ if (bWrapAroundFlag)
+ {
+ nu_capture->u32CurrentFallingCnt = 0x10000;
+ }
+ nu_capture->u32CurrentFallingCnt += EPWM_GET_CAPTURE_FALLING_DATA(nu_capture->epwm, nu_capture->u8Channel);
+ }
+ else
+ {
+ EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH);
+ EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH);
+
+ return -(RT_ERROR);
+ }
+
+ return RT_EOK;
+}
+
+#if (BSP_USING_EPWM0_CAPTURE_CHMSK&(0x3<u32CurrentFallingCnt)
+ {
+ *pulsewidth_us = nu_capture->u32CurrentFallingCnt;
+ nu_capture->input_data_level = RT_FALSE;
+ nu_capture->u32CurrentFallingCnt = 0;
+ }
+ else if (nu_capture->u32CurrentRisingCnt)
+ {
+ *pulsewidth_us = nu_capture->u32CurrentRisingCnt;
+ nu_capture->input_data_level = RT_TRUE;
+ nu_capture->u32CurrentRisingCnt = 0;
+ }
+ else
+ {
+ ret = RT_ERROR;
+ }
+ return -(ret);
+}
+
+static rt_err_t nu_epwm_init(nu_capture_t *nu_capture)
+{
+ rt_err_t ret = RT_ERROR;
+ static rt_bool_t bEPWM0Inited = RT_FALSE;
+ static rt_bool_t bEPWM1Inited = RT_FALSE;
+
+ if (nu_capture->epwm == EPWM0)
+ {
+ if (bEPWM0Inited == RT_FALSE)
+ {
+ /* Enable EPWM0 clock */
+ SYS_UnlockReg();
+ CLK_EnableModuleClock(EPWM0_MODULE);
+ CLK_SetModuleClock(EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PLL, (uint32_t)NULL);
+ SYS_LockReg();
+ bEPWM0Inited = RT_TRUE;
+ }
+ ret = RT_EOK;
+ }
+ else if (nu_capture->epwm == EPWM1)
+ {
+ if (bEPWM1Inited == RT_FALSE)
+ {
+ /* Enable EPWM1 clock */
+ SYS_UnlockReg();
+ CLK_EnableModuleClock(EPWM1_MODULE);
+ CLK_SetModuleClock(EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PLL, (uint32_t)NULL);
+ SYS_LockReg();
+ bEPWM1Inited = RT_TRUE;
+ }
+ ret = RT_EOK;
+ }
+
+ return -(ret);
+}
+
+static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture)
+{
+ rt_err_t ret = RT_EOK;
+ nu_capture_t *nu_capture;
+
+ RT_ASSERT(inputcapture != RT_NULL);
+
+ nu_capture = (nu_capture_t *) inputcapture;
+
+ if (nu_epwm_init(nu_capture) != RT_EOK)
+ {
+ rt_kprintf("Failed to initialize EPWM%d.\n", nu_capture->epwm);
+ ret = RT_ERROR;
+ }
+
+ return -(ret);
+}
+
+static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture)
+{
+ rt_err_t ret = RT_EOK;
+ nu_capture_t *nu_capture;
+
+ RT_ASSERT(inputcapture != RT_NULL);
+
+ nu_capture = (nu_capture_t *) inputcapture;
+
+ /* Set capture time as 1000 nano second */
+ EPWM_ConfigCaptureChannel(nu_capture->epwm, nu_capture->u8Channel, 1000, 0);
+
+ /* Enable capture rising/falling edge interrupt */
+ EPWM_EnableCaptureInt(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH);
+
+ /* Enable EPWM NVIC interrupt */
+ NVIC_EnableIRQ(nu_capture->irq);
+
+ /* Enable Capture Function for EPWM */
+ EPWM_EnableCapture(nu_capture->epwm, 0x1 << nu_capture->u8Channel);
+
+ /* Enable rising/falling capture reload */
+ nu_capture->epwm->CAPCTL |= (0x1 << (EPWM_CAPCTL_RCRLDEN0_Pos + nu_capture->u8Channel))
+ | (0x1 << (EPWM_CAPCTL_FCRLDEN0_Pos + nu_capture->u8Channel));
+
+ /* Set counter type as down count */
+ EPWM_SET_ALIGNED_TYPE(nu_capture->epwm, 0x1 << nu_capture->u8Channel, EPWM_UP_COUNTER);
+
+ /* Enable EPWM Timer */
+ EPWM_Start(nu_capture->epwm, 0x1 << nu_capture->u8Channel);
+
+ return ret;
+}
+
+static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture)
+{
+ rt_err_t ret = RT_EOK;
+
+ nu_capture_t *nu_capture;
+
+ RT_ASSERT(inputcapture != RT_NULL);
+
+ nu_capture = (nu_capture_t *) inputcapture;
+
+ /* Disable capture rising/falling edge interrupt */
+ EPWM_DisableCaptureInt(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH);
+
+ /* Disable EPWM NVIC interrupt */
+ NVIC_DisableIRQ(nu_capture->irq);
+
+ /* Enable EPWM Timer */
+ EPWM_Stop(nu_capture->epwm, 0x1 << nu_capture->u8Channel);
+ return ret;
+}
+
+/* Init and register epwm capture */
+int nu_epwm_capture_device_init(void)
+{
+ /* Init EPWM0 6 channel and EPWM1 6 channel */
+#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0)
+ for (int i = 0; i < EPWM_CHANNEL_NUM; i++)
+ {
+ if (BSP_USING_EPWM0_CAPTURE_CHMSK & (0x1 << i))
+ {
+ nu_epwm0_capture[i].epwm = EPWM0;
+ nu_epwm0_capture[i].u8Channel = i;
+ nu_epwm0_capture[i].irq = nu_epwm0_irq[i / 2];
+ nu_epwm0_capture[i].u32CurrentRisingCnt = 0;
+ nu_epwm0_capture[i].u32CurrentFallingCnt = 0;
+ nu_epwm0_capture[i].parent.ops = &nu_capture_ops;
+
+ /* register inputcapture device */
+ rt_device_inputcapture_register(&nu_epwm0_capture[i].parent, nu_epwm0_device_name[i], &nu_epwm0_capture[i]);
+
+ }
+ }
+#endif //#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0)
+#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0)
+ for (int i = 0; i < EPWM_CHANNEL_NUM; i++)
+ {
+ if (BSP_USING_EPWM1_CAPTURE_CHMSK & (0x1 << i))
+ {
+ nu_epwm1_capture[i].epwm = EPWM1;
+ nu_epwm1_capture[i].u8Channel = i;
+ nu_epwm1_capture[i].irq = nu_epwm1_irq[i / 2];
+ nu_epwm1_capture[i].u32CurrentRisingCnt = 0;
+ nu_epwm1_capture[i].u32CurrentFallingCnt = 0;
+ nu_epwm1_capture[i].parent.ops = &nu_capture_ops;
+
+ /* register inputcapture device */
+ rt_device_inputcapture_register(&nu_epwm1_capture[i].parent, nu_epwm1_device_name[i], &nu_epwm1_capture[i]);
+ }
+ }
+#endif //#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0)
+ return 0;
+
+}
+INIT_DEVICE_EXPORT(nu_epwm_capture_device_init);
+
+#endif //#if defined(BSP_USING_EPWM_CAPTURE)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c
new file mode 100644
index 00000000000..79e66dbac0d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c
@@ -0,0 +1,322 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-3-03 FYChou First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_FMC)
+#include
+#include "NuMicro.h"
+
+#if defined(PKG_USING_FAL)
+ #include
+#endif
+
+/* Private define ---------------------------------------------------------------*/
+#define NU_GETBYTE_OFST(addr) ((addr&0x3)*8)
+#define NU_GET_WALIGN(addr) (addr&~0x3)
+#define NU_GET_LSB2BIT(addr) (addr&0x3)
+/* Private typedef --------------------------------------------------------------*/
+
+/* Private functions ------------------------------------------------------------*/
+static int nu_fmc_init(void);
+#if defined(PKG_USING_FAL)
+ static int aprom_read(long offset, uint8_t *buf, size_t size);
+ static int aprom_write(long offset, const uint8_t *buf, size_t size);
+ static int aprom_erase(long offset, size_t size);
+
+ static int ldrom_read(long offset, uint8_t *buf, size_t size);
+ static int ldrom_write(long offset, const uint8_t *buf, size_t size);
+ static int ldrom_erase(long offset, size_t size);
+#endif /* PKG_USING_FAL */
+
+/* Public functions -------------------------------------------------------------*/
+int nu_fmc_read(long offset, uint8_t *buf, size_t size);
+int nu_fmc_write(long offset, const uint8_t *buf, size_t size);
+int nu_fmc_erase(long offset, size_t size);
+
+/* Private variables ------------------------------------------------------------*/
+static rt_mutex_t g_mutex_fmc = RT_NULL;
+
+/* Public variables -------------------------------------------------------------*/
+#if defined(PKG_USING_FAL)
+const struct fal_flash_dev Onchip_aprom_flash = { "OnChip_APROM", FMC_APROM_BASE, FMC_APROM_END, FMC_FLASH_PAGE_SIZE, {NULL, aprom_read, aprom_write, aprom_erase} };
+const struct fal_flash_dev Onchip_ldrom_flash = { "OnChip_LDROM", FMC_LDROM_BASE, FMC_LDROM_END, FMC_FLASH_PAGE_SIZE, {NULL, ldrom_read, ldrom_write, ldrom_erase} };
+#endif /* PKG_USING_FAL */
+
+int nu_fmc_read(long addr, uint8_t *buf, size_t size)
+{
+ size_t read_size = 0;
+ uint32_t addr_end = addr + size;
+ uint32_t isp_rdata = 0;
+ rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER);
+ SYS_UnlockReg();
+
+ if (NU_GET_LSB2BIT(addr))
+ isp_rdata = FMC_Read(NU_GET_WALIGN(addr));
+
+
+ for (; addr < addr_end ;)
+ {
+ if (NU_GET_LSB2BIT(addr) == 0)
+ {
+ isp_rdata = FMC_Read(addr);
+ if (addr_end - addr >= 4)
+ {
+ *(uint32_t *)buf = isp_rdata;
+ addr += 4;
+ buf += 4;
+ read_size += 4;
+ continue;
+ }
+ }
+
+ *buf = isp_rdata >> NU_GETBYTE_OFST(addr);
+ addr++;
+ buf++;
+ read_size++;
+
+ }
+
+ SYS_LockReg();
+ rt_mutex_release(g_mutex_fmc);
+
+ return read_size;
+}
+
+int nu_fmc_write(long addr, const uint8_t *buf, size_t size)
+{
+ size_t write_size = 0;
+ uint32_t addr_end = addr + size;
+ uint32_t isp_rdata = 0;
+
+ rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER);
+ SYS_UnlockReg();
+
+ if (addr < FMC_APROM_END)
+ FMC_ENABLE_AP_UPDATE();
+ else if ((addr < FMC_LDROM_END) && addr >= FMC_LDROM_BASE)
+ FMC_ENABLE_LD_UPDATE();
+ else
+ {
+ goto Exit2;
+ }
+
+ if (NU_GET_LSB2BIT(addr))
+ isp_rdata = FMC_Read(NU_GET_WALIGN(addr));
+
+ for (; addr < addr_end ;)
+ {
+
+ if (addr_end - addr >= 4 && NU_GET_LSB2BIT(addr) == 0)
+ {
+ FMC_Write(addr, *((uint32_t *)buf));
+ addr += 4;
+ buf += 4;
+ write_size += 4;
+ continue;
+ }
+
+ if ((NU_GET_LSB2BIT(addr)) == 0x0)
+ isp_rdata = FMC_Read(NU_GET_WALIGN(addr));
+
+ isp_rdata = (isp_rdata & ~(0xFF << NU_GETBYTE_OFST(addr))) | ((*buf) << NU_GETBYTE_OFST(addr));
+
+ if ((NU_GET_LSB2BIT(addr)) == 0x3)
+ FMC_Write(NU_GET_WALIGN(addr), isp_rdata);
+
+ addr++;
+ buf++;
+ write_size++;
+
+ }
+
+ if (NU_GET_LSB2BIT(addr))
+ FMC_Write(NU_GET_WALIGN(addr), isp_rdata);
+
+ FMC_DISABLE_AP_UPDATE();
+ FMC_DISABLE_LD_UPDATE();
+Exit2:
+ SYS_LockReg();
+ rt_mutex_release(g_mutex_fmc);
+
+ return write_size;
+
+}
+
+int nu_fmc_erase(long addr, size_t size)
+{
+ size_t erased_size = 0;
+ uint32_t addrptr;
+ uint32_t addr_end = addr + size;
+
+#if defined(NU_SUPPORT_NONALIGN)
+ uint8_t *page_sdtemp = RT_NULL, *page_edtemp = RT_NULL;
+
+
+ addrptr = addr & (FMC_FLASH_PAGE_SIZE - 1);
+ if (addrptr)
+ {
+ page_sdtemp = rt_malloc(addrptr);
+ if (page_sdtemp == RT_NULL)
+ {
+ erased_size = 0;
+
+ goto Exit3;
+ }
+
+ if (nu_fmc_read(addr & ~(FMC_FLASH_PAGE_SIZE - 1), page_sdtemp, addrptr) != addrptr)
+ {
+
+ erased_size = 0;
+
+ goto Exit3;
+ }
+
+ }
+
+ addrptr = addr_end & (FMC_FLASH_PAGE_SIZE - 1);
+ if (addrptr)
+ {
+ page_edtemp = rt_malloc(FMC_FLASH_PAGE_SIZE - addrptr);
+ if (page_edtemp == RT_NULL)
+ {
+ erased_size = 0;
+
+ goto Exit3;
+ }
+
+ if (nu_fmc_read(addr_end, page_edtemp, FMC_FLASH_PAGE_SIZE - addrptr) != FMC_FLASH_PAGE_SIZE - addrptr)
+ {
+ erased_size = 0;
+
+ goto Exit3;
+ }
+
+ }
+#endif
+
+ rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER);
+ SYS_UnlockReg();
+
+ if (addr <= FMC_APROM_END)
+ FMC_ENABLE_AP_UPDATE();
+ else if ((addr < FMC_LDROM_END) && addr >= FMC_LDROM_BASE)
+ FMC_ENABLE_LD_UPDATE();
+ else
+ {
+ goto Exit2;
+ }
+
+ addrptr = (addr & ~(FMC_FLASH_PAGE_SIZE - 1));
+ while (addrptr < addr_end)
+ {
+ if (FMC_Erase(addrptr) != RT_EOK)
+ {
+ goto Exit1;
+ }
+ erased_size += FMC_FLASH_PAGE_SIZE;
+ addrptr += FMC_FLASH_PAGE_SIZE;
+ }
+
+Exit1:
+ FMC_DISABLE_AP_UPDATE();
+ FMC_DISABLE_LD_UPDATE();
+Exit2:
+ SYS_LockReg();
+ rt_mutex_release(g_mutex_fmc);
+
+#if defined(NU_SUPPORT_NONALIGN)
+
+ if (erased_size >= size)
+ {
+ addrptr = addr & (FMC_FLASH_PAGE_SIZE - 1);
+ if (addrptr)
+ {
+ if (nu_fmc_write(addr & ~(FMC_FLASH_PAGE_SIZE - 1), page_sdtemp, addrptr) != addrptr)
+ goto Exit3;
+
+ erased_size += addrptr;
+ }
+
+ addrptr = addr_end & (FMC_FLASH_PAGE_SIZE - 1);
+ if (addrptr)
+ {
+
+ if (nu_fmc_write(addr_end, page_edtemp, FMC_FLASH_PAGE_SIZE - addrptr) != FMC_FLASH_PAGE_SIZE - addrptr)
+ goto Exit3;
+
+ erased_size += FMC_FLASH_PAGE_SIZE - addrptr;
+
+ }
+ }
+ else
+ erased_size = 0;
+
+
+Exit3:
+ if (page_sdtemp != RT_NULL)
+ rt_free(page_sdtemp);
+
+ if (page_edtemp != RT_NULL)
+ rt_free(page_edtemp);
+#endif
+
+ return erased_size;
+}
+
+#if defined(PKG_USING_FAL)
+
+static int aprom_read(long offset, uint8_t *buf, size_t size)
+{
+ return nu_fmc_read(Onchip_aprom_flash.addr + offset, buf, size);
+}
+
+static int aprom_write(long offset, const uint8_t *buf, size_t size)
+{
+ return nu_fmc_write(Onchip_aprom_flash.addr + offset, buf, size);
+}
+
+static int aprom_erase(long offset, size_t size)
+{
+ return nu_fmc_erase(Onchip_aprom_flash.addr + offset, size);
+}
+
+static int ldrom_read(long offset, uint8_t *buf, size_t size)
+{
+ return nu_fmc_read(Onchip_ldrom_flash.addr + offset, buf, size);
+}
+
+static int ldrom_write(long offset, const uint8_t *buf, size_t size)
+{
+ return nu_fmc_write(Onchip_ldrom_flash.addr + offset, buf, size);
+}
+
+static int ldrom_erase(long offset, size_t size)
+{
+ return nu_fmc_erase(Onchip_ldrom_flash.addr + offset, size);
+}
+
+#endif /* PKG_USING_FAL */
+
+static int nu_fmc_init(void)
+{
+ SYS_UnlockReg();
+ FMC_ENABLE_ISP();
+ SYS_LockReg();
+
+ g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_FIFO);
+
+ return RT_EOK;
+}
+INIT_APP_EXPORT(nu_fmc_init);
+
+#endif /* BSP_USING_FMC */
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h
new file mode 100644
index 00000000000..9a9ef373c3a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h
@@ -0,0 +1,24 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-3-03 FYChou First version
+*
+******************************************************************************/
+
+#ifndef __DRV_FMC_H__
+#define __DRV_FMC_H__
+
+#include
+#include
+
+int nu_fmc_read(long offset, uint8_t *buf, size_t size);
+int nu_fmc_write(long offset, const uint8_t *buf, size_t size);
+int nu_fmc_erase(long offset, size_t size);
+
+
+#endif // __DRV_FMC_H___
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c
new file mode 100644
index 00000000000..4790d650014
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c
@@ -0,0 +1,394 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-7 YCHuang12 First version
+*
+******************************************************************************/
+
+#include
+
+#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN))
+
+#include
+#include
+#include
+#include
+#include
+
+/* Private define ---------------------------------------------------------------*/
+
+#define PORT_OFFSET 0x40
+#define IRQ_MAX_NUM 16 //Max support 32
+#define MAX_PORTH_PIN_MAX 11
+
+/* Private functions ------------------------------------------------------------*/
+
+static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode);
+static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_base_t value);
+static int nu_gpio_read(struct rt_device *device, rt_base_t pin);
+static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args);
+static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin);
+static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled);
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[IRQ_MAX_NUM];
+static struct rt_pin_ops nu_gpio_ops =
+{
+ nu_gpio_mode,
+ nu_gpio_write,
+ nu_gpio_read,
+ nu_gpio_attach_irq,
+ nu_gpio_detach_irq,
+ nu_gpio_irq_enable
+};
+
+static IRQn_Type au32GPIRQ[NU_PORT_CNT] = {GPA_IRQn, GPB_IRQn, GPC_IRQn, GPD_IRQn, GPE_IRQn, GPF_IRQn, GPG_IRQn, GPH_IRQn};
+
+static rt_uint32_t g_u32PinIrqMask = 0x0;
+
+/* Functions define ------------------------------------------------------------*/
+
+static rt_err_t nu_port_check(rt_int32_t pin)
+{
+ if (NU_GET_PORT(pin) >= NU_PORT_CNT)
+ return -(RT_ERROR);
+ else if ((NU_GET_PORT(pin) == NU_PH) && (NU_GET_PINS(pin) > MAX_PORTH_PIN_MAX))
+ return -(RT_ERROR);
+
+ return RT_EOK;
+}
+
+static rt_int32_t nu_find_irqindex(rt_uint32_t pin_index)
+{
+ rt_int32_t irqindex;
+ rt_int32_t u32PinIrqStatus = g_u32PinIrqMask;
+
+ // Find index of pin is attached in pool.
+ while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM) // Count Trailing Zeros ==> Find First One
+ {
+ if (pin_irq_hdr_tab[irqindex].pin == pin_index)
+ return irqindex;
+
+ u32PinIrqStatus &= ~(1 << irqindex);
+ }
+
+ return -(RT_ERROR);
+}
+
+static void pin_irq_hdr(rt_uint32_t irq_status, rt_uint32_t port_index)
+{
+ rt_int32_t irqindex, i;
+ rt_int32_t pinindex = port_index * GPIO_PIN_MAX ;
+
+ while ((i = nu_ctz(irq_status)) < GPIO_PIN_MAX)// Count Trailing Zeros ==> Find First One
+ {
+ int pin_mask = (1 << i);
+ irqindex = nu_find_irqindex(pinindex + i);
+ if (irqindex != -(RT_ERROR))
+ {
+ if (pin_irq_hdr_tab[irqindex].hdr)
+ {
+ pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
+ }
+ }
+ // Clear the served bit.
+ irq_status &= ~pin_mask;
+ }
+}
+
+static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+{
+ GPIO_T *PORT;
+
+ if (nu_port_check(pin))
+ return;
+
+ PORT = (GPIO_T *)(GPIOA_BASE + (NU_GET_PORT(pin) * PORT_OFFSET));
+
+ if (mode == PIN_MODE_INPUT_PULLUP)
+ {
+ GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT);
+ GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_UP);
+ }
+ else if (mode == PIN_MODE_INPUT_PULLDOWN)
+ {
+ GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT);
+ GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_DOWN);
+ }
+ else if (mode == PIN_MODE_OUTPUT)
+ {
+ GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OUTPUT);
+ }
+ else if (mode == PIN_MODE_INPUT)
+ {
+ GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT);
+ GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE);
+ }
+ else if (mode == PIN_MODE_OUTPUT_OD)
+ {
+ GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OPEN_DRAIN);
+ GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE);
+ }
+}
+
+static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+{
+ if (nu_port_check(pin))
+ return;
+
+ GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value;
+}
+
+static int nu_gpio_read(struct rt_device *device, rt_base_t pin)
+{
+ if (nu_port_check(pin))
+ return PIN_LOW;
+
+ return GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin));
+}
+
+static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+ rt_base_t level;
+ rt_int32_t irqindex;
+
+ if (nu_port_check(pin))
+ return -(RT_ERROR);
+
+ level = rt_hw_interrupt_disable();
+
+ // Find index of pin is attached in pool.
+ if ((irqindex = nu_find_irqindex(pin)) >= 0)
+ goto exit_nu_gpio_attach_irq;
+
+ // Find avaiable index of pin in pool.
+ if ((irqindex = nu_cto(g_u32PinIrqMask)) < IRQ_MAX_NUM) // Count Trailing Ones ==> Find First Zero
+ goto exit_nu_gpio_attach_irq;
+
+ rt_hw_interrupt_enable(level);
+
+ return -(RT_EBUSY);
+
+exit_nu_gpio_attach_irq:
+
+ pin_irq_hdr_tab[irqindex].pin = pin;
+ pin_irq_hdr_tab[irqindex].hdr = hdr;
+ pin_irq_hdr_tab[irqindex].mode = mode;
+ pin_irq_hdr_tab[irqindex].args = args;
+
+ g_u32PinIrqMask |= (1 << irqindex);
+ rt_hw_interrupt_enable(level);
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+ rt_base_t level;
+ rt_int32_t irqindex;
+ rt_int32_t u32PinIrqStatus;
+
+ if (nu_port_check(pin))
+ return -(RT_ERROR);
+
+ level = rt_hw_interrupt_disable();
+
+ u32PinIrqStatus = g_u32PinIrqMask;
+
+ // Find index of pin is attached in pool.
+ while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM)// Count Trailing Zeros ==> Find First One
+ {
+ if (pin_irq_hdr_tab[irqindex].pin == pin)
+ {
+ pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE;
+ pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+ pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING;
+ pin_irq_hdr_tab[irqindex].args = RT_NULL;
+ g_u32PinIrqMask &= ~(1 << irqindex);
+ break;
+ }
+ u32PinIrqStatus &= ~(1 << irqindex);
+ }
+
+ rt_hw_interrupt_enable(level);
+ return RT_EOK;
+}
+
+static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+ GPIO_T *PORT;
+ rt_base_t level;
+ uint32_t u32IntAttribs;
+ rt_int32_t irqindex;
+ rt_err_t ret = RT_EOK;
+
+ if (nu_port_check(pin))
+ return -(RT_ERROR);
+
+ level = rt_hw_interrupt_disable();
+
+ irqindex = nu_find_irqindex(pin);
+ if (irqindex == -(RT_ERROR))
+ {
+ ret = RT_ERROR;
+ goto exit_nu_gpio_irq_enable;
+ }
+
+ PORT = (GPIO_T *)(GPIOA_BASE + (NU_GET_PORT(pin) * PORT_OFFSET));
+
+ if (enabled == PIN_IRQ_ENABLE)
+ {
+ if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING)
+ u32IntAttribs = GPIO_INT_RISING;
+ else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_FALLING)
+ u32IntAttribs = GPIO_INT_FALLING;
+ else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING_FALLING)
+ u32IntAttribs = GPIO_INT_BOTH_EDGE;
+ else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_HIGH_LEVEL)
+ u32IntAttribs = GPIO_INT_HIGH;
+ else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_LOW_LEVEL)
+ u32IntAttribs = GPIO_INT_LOW;
+ else
+ goto exit_nu_gpio_irq_enable;
+
+ GPIO_EnableInt(PORT, NU_GET_PINS(pin), u32IntAttribs);
+
+ NVIC_EnableIRQ(au32GPIRQ[NU_GET_PORT(pin)]);
+ }
+ else
+ {
+ GPIO_DisableInt(PORT, NU_GET_PINS(pin));
+ }
+
+exit_nu_gpio_irq_enable:
+
+ rt_hw_interrupt_enable(level);
+ return -(ret);
+}
+
+int rt_hw_gpio_init(void)
+{
+ rt_int32_t irqindex;
+ for (irqindex = 0; irqindex < IRQ_MAX_NUM ; irqindex++)
+ {
+ pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE;
+ pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+ pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING;
+ pin_irq_hdr_tab[irqindex].args = RT_NULL;
+ }
+
+ return rt_device_pin_register("gpio", &nu_gpio_ops, RT_NULL);
+}
+
+INIT_BOARD_EXPORT(rt_hw_gpio_init);
+
+void GPA_IRQHandler(void)
+{
+ rt_uint32_t int_status;
+
+ rt_interrupt_enter();
+
+ int_status = PA->INTSRC;
+ pin_irq_hdr(int_status, NU_PA);
+ PA->INTSRC = int_status;
+
+ rt_interrupt_leave();
+}
+
+void GPB_IRQHandler(void)
+{
+ rt_uint32_t int_status;
+
+ rt_interrupt_enter();
+
+ int_status = PB->INTSRC;
+ pin_irq_hdr(int_status, NU_PB);
+ PB->INTSRC = int_status;
+
+ rt_interrupt_leave();
+}
+
+void GPC_IRQHandler(void)
+{
+ rt_uint32_t int_status;
+
+ rt_interrupt_enter();
+
+ int_status = PC->INTSRC;
+ pin_irq_hdr(int_status, NU_PC);
+ PC->INTSRC = int_status;
+
+ rt_interrupt_leave();
+}
+
+void GPD_IRQHandler(void)
+{
+ rt_uint32_t int_status;
+
+ rt_interrupt_enter();
+
+ int_status = PD->INTSRC;
+ pin_irq_hdr(int_status, NU_PD);
+ PD->INTSRC = int_status;
+
+ rt_interrupt_leave();
+}
+
+void GPE_IRQHandler(void)
+{
+ rt_uint32_t int_status;
+
+ rt_interrupt_enter();
+
+ int_status = PE->INTSRC;
+ pin_irq_hdr(int_status, NU_PE);
+ PE->INTSRC = int_status;
+
+ rt_interrupt_leave();
+}
+
+void GPF_IRQHandler(void)
+{
+ rt_uint32_t int_status;
+
+ rt_interrupt_enter();
+
+ int_status = PF->INTSRC;
+ pin_irq_hdr(int_status, NU_PF);
+ PF->INTSRC = int_status;
+
+ rt_interrupt_leave();
+}
+
+void GPG_IRQHandler(void)
+{
+ rt_uint32_t int_status;
+
+ rt_interrupt_enter();
+
+ int_status = PG->INTSRC;
+ pin_irq_hdr(int_status, NU_PG);
+ PG->INTSRC = int_status;
+
+ rt_interrupt_leave();
+}
+
+void GPH_IRQHandler(void)
+{
+ rt_uint32_t int_status;
+
+ rt_interrupt_enter();
+
+ int_status = PH->INTSRC;
+ pin_irq_hdr(int_status, NU_PH);
+ PH->INTSRC = int_status;
+
+ rt_interrupt_leave();
+}
+
+#endif //#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN))
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h
new file mode 100644
index 00000000000..c353a1e7725
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h
@@ -0,0 +1,34 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-7 YCHuang12 First version
+*
+******************************************************************************/
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+typedef enum
+{
+ NU_PA,
+ NU_PB,
+ NU_PC,
+ NU_PD,
+ NU_PE,
+ NU_PF,
+ NU_PG,
+ NU_PH,
+ NU_PORT_CNT,
+} nu_gpio_port;
+
+#define NU_GET_PININDEX(port, pin) (port*16+pin)
+#define NU_GET_PINS(rt_pin_index) ((rt_pin_index) & 0x0000000F)
+#define NU_GET_PORT(rt_pin_index) (((rt_pin_index)>>4) & 0x0000000F)
+#define NU_GET_PIN_MASK(nu_gpio_pin) (1 << (nu_gpio_pin))
+
+#endif //__DRV_GPIO_H__
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c
new file mode 100644
index 00000000000..17244d5e0a0
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c
@@ -0,0 +1,125 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-05-22 klcheng First version
+*
+******************************************************************************/
+#include
+
+#if defined(BSP_USING_HSOTG)
+#include
+#include
+#include
+
+
+/* This delay must be at least 10 us */
+static void _usb_init_delay(void)
+{
+ volatile uint32_t i = 0x1000;
+
+ while (i--)
+ __NOP();
+
+ return;
+}
+
+/* Check current usb role */
+static void usb_role(void)
+{
+ uint32_t status;
+
+ status = (HSOTG->STATUS) & (HSOTG_STATUS_ASHOST_Msk | HSOTG_STATUS_ASPERI_Msk | HSOTG_STATUS_IDSTS_Msk);
+
+ if (status == (HSOTG_STATUS_IDSTS_Msk | HSOTG_STATUS_ASPERI_Msk))
+ rt_kprintf("usb frame acts as peripheral\n");
+
+ else if (status == HSOTG_STATUS_ASHOST_Msk)
+ rt_kprintf("usb frame acts as host\n");
+
+ else
+ rt_kprintf("usb frame is unknown state: 0x%x\n", status);
+
+ return;
+}
+MSH_CMD_EXPORT_ALIAS(usb_role, usb_role, check usb role);
+
+
+static int hsotg_init(void)
+{
+ SYS_UnlockReg();
+
+ /* Set HSOTG as ID dependent role */
+ SYS->USBPHY = SYS_USBPHY_HSUSBEN_Msk | (0x2 << SYS_USBPHY_HSUSBROLE_Pos);
+
+ /* user should keep HSUSB PHY at reset mode at lease 10 us before changing to active mode */
+ _usb_init_delay();
+ SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;
+
+ /* Enable OTG and ID detection function */
+ HSOTG_ENABLE_PHY();
+ HSOTG_ENABLE_ID_DETECT();
+ NVIC_EnableIRQ(USBOTG20_IRQn);
+
+ /* clear interrupt and enable relative interrupts */
+ HSOTG_ENABLE_INT(HSOTG_INTEN_IDCHGIEN_Msk | HSOTG_INTEN_HOSTIEN_Msk | HSOTG_INTEN_PDEVIEN_Msk |
+ HSOTG_INTEN_BVLDCHGIEN_Msk | HSOTG_INTEN_AVLDCHGIEN_Msk);
+
+ SYS_LockReg();
+
+ return (int)RT_EOK;
+}
+INIT_DEVICE_EXPORT(hsotg_init);
+
+
+/* HSOTG interrupt entry */
+void USBOTG20_IRQHandler(void)
+{
+ __IO uint32_t reg;
+
+ reg = HSOTG->INTSTS;
+
+ /* usb id pin status change */
+ if (reg & HSOTG_INTSTS_IDCHGIF_Msk)
+ {
+ HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_IDCHGIF_Msk);
+ LOG_D("usb id change");
+ }
+
+ /* usb acts as host */
+ if (reg & HSOTG_INTSTS_HOSTIF_Msk)
+ {
+ HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_HOSTIF_Msk);
+ LOG_D("usb acts as host");
+ }
+
+ /* usb acts as peripheral */
+ if (reg & HSOTG_INTSTS_PDEVIF_Msk)
+ {
+ HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_PDEVIF_Msk);
+ LOG_D("usb acts as peripheral");
+ }
+
+ /* A-device session valid state change */
+ if (reg & HSOTG_INTSTS_AVLDCHGIF_Msk)
+ {
+ HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_AVLDCHGIF_Msk);
+ LOG_D("usb a-device session valid state change");
+ }
+
+ /* B-device session valid state change */
+ if (reg & HSOTG_INTSTS_BVLDCHGIF_Msk)
+ {
+ HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_BVLDCHGIF_Msk);
+ LOG_D("usb b-device session valid state change");
+ }
+}
+
+#endif /* defined(BSP_USING_HSOTG) */
+
+
+
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_hsusbd.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_hsusbd.c
new file mode 100644
index 00000000000..47329cc294b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_hsusbd.c
@@ -0,0 +1,974 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-5-26 Egbert First version
+*
+******************************************************************************/
+
+
+#include
+
+#ifdef BSP_USING_HSUSBD
+#include
+#include
+#include
+#include "NuMicro.h"
+
+
+#define LOG_TAG "drv.hsusbd"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME "drv.hsusbd"
+#define DBG_LEVEL DBG_ERROR
+#define DBG_COLOR
+#include
+
+/* Private define ---------------------------------------------------------------*/
+#define ENABLE_FULL_SPEED_MODE_ONLY 0 /* 0: default hi-speed mode; 1: full-speed mode only */
+
+/* Define EP maximum packet size */
+#define CEP_MAX_PKT_SIZE 64
+#define CEP_OTHER_MAX_PKT_SIZE 64
+
+#define EPA_MAX_PKT_SIZE 512
+#define EPA_OTHER_MAX_PKT_SIZE 64
+
+#define EPB_MAX_PKT_SIZE 512
+#define EPB_OTHER_MAX_PKT_SIZE 64
+
+#define EPC_MAX_PKT_SIZE 64
+#define EPC_OTHER_MAX_PKT_SIZE 64
+
+#define EPD_MAX_PKT_SIZE 64
+#define EPD_OTHER_MAX_PKT_SIZE 64
+
+#define EPE_MAX_PKT_SIZE 512
+#define EPE_OTHER_MAX_PKT_SIZE 64
+
+#define EPF_MAX_PKT_SIZE 512
+#define EPF_OTHER_MAX_PKT_SIZE 64
+
+#define EPG_MAX_PKT_SIZE 64
+#define EPG_OTHER_MAX_PKT_SIZE 64
+
+#define EPH_MAX_PKT_SIZE 64
+#define EPH_OTHER_MAX_PKT_SIZE 64
+
+#define CEP_BUF_BASE 0
+#define CEP_BUF_LEN CEP_MAX_PKT_SIZE
+#define EPA_BUF_BASE (CEP_BUF_BASE + CEP_BUF_LEN)
+#define EPA_BUF_LEN EPA_MAX_PKT_SIZE
+#define EPB_BUF_BASE (EPA_BUF_BASE + EPA_BUF_LEN)
+#define EPB_BUF_LEN EPB_MAX_PKT_SIZE
+#define EPC_BUF_BASE (EPB_BUF_BASE + EPB_BUF_LEN)
+#define EPC_BUF_LEN EPC_MAX_PKT_SIZE
+#define EPD_BUF_BASE (EPC_BUF_BASE + EPC_BUF_LEN)
+#define EPD_BUF_LEN EPD_MAX_PKT_SIZE
+#define EPE_BUF_BASE (EPD_BUF_BASE + EPD_BUF_LEN)
+#define EPE_BUF_LEN EPE_MAX_PKT_SIZE
+#define EPF_BUF_BASE (EPE_BUF_BASE + EPE_BUF_LEN)
+#define EPF_BUF_LEN EPF_MAX_PKT_SIZE
+#define EPG_BUF_BASE (EPF_BUF_BASE + EPF_BUF_LEN)
+#define EPG_BUF_LEN EPG_MAX_PKT_SIZE
+#define EPH_BUF_BASE (EPG_BUF_BASE + EPG_BUF_LEN)
+#define EPH_BUF_LEN EPH_MAX_PKT_SIZE
+
+#define EPADR_SW2HW(address) ((address & USB_EPNO_MASK) - 1) /* for non-control endpoint */
+#define EPADR_HW2SW(address) ((address & USB_EPNO_MASK) + 1) /* for non-control endpoint */
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct _nu_usbd_t
+{
+ HSUSBD_T *Instance; /* REG base */
+ uint8_t address_tmp; /* Keep assigned address for flow control */
+} nu_usbd_t;
+
+
+/* Private variables ------------------------------------------------------------*/
+static nu_usbd_t nu_usbd =
+{
+ .Instance = HSUSBD,
+ .address_tmp = 0,
+};
+
+static struct udcd _rt_obj_udc;
+
+static struct ep_id _ep_pool[] =
+{
+ {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, CEP_MAX_PKT_SIZE, ID_ASSIGNED },
+ {EPADR_HW2SW(EPA), USB_EP_ATTR_BULK, USB_DIR_IN, EPA_MAX_PKT_SIZE, ID_UNASSIGNED},
+ {EPADR_HW2SW(EPB), USB_EP_ATTR_BULK, USB_DIR_OUT, EPB_MAX_PKT_SIZE, ID_UNASSIGNED},
+ {EPADR_HW2SW(EPC), USB_EP_ATTR_INT, USB_DIR_IN, EPC_MAX_PKT_SIZE, ID_UNASSIGNED},
+ {EPADR_HW2SW(EPD), USB_EP_ATTR_INT, USB_DIR_OUT, EPD_MAX_PKT_SIZE, ID_UNASSIGNED},
+ {EPADR_HW2SW(EPE), USB_EP_ATTR_BULK, USB_DIR_IN, EPE_MAX_PKT_SIZE, ID_UNASSIGNED},
+ {EPADR_HW2SW(EPF), USB_EP_ATTR_BULK, USB_DIR_OUT, EPF_MAX_PKT_SIZE, ID_UNASSIGNED},
+ {EPADR_HW2SW(EPG), USB_EP_ATTR_INT, USB_DIR_IN, EPG_MAX_PKT_SIZE, ID_UNASSIGNED},
+ {EPADR_HW2SW(EPH), USB_EP_ATTR_INT, USB_DIR_OUT, EPH_MAX_PKT_SIZE, ID_UNASSIGNED},
+ {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED },
+};
+
+
+static void _nu_ep_partition_fs(void)
+{
+ /*****************************************************/
+ /* EPA ==> Bulk IN endpoint, address 1 */
+ HSUSBD_SetEpBufAddr(EPA, EPA_BUF_BASE, EPA_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPA, EPA_OTHER_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPA, EPADR_HW2SW(EPA), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_IN);
+
+
+ /* EPB ==> Bulk OUT endpoint, address 2 */
+ HSUSBD_SetEpBufAddr(EPB, EPB_BUF_BASE, EPB_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPB, EPB_OTHER_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPB, EPADR_HW2SW(EPB), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_OUT);
+ HSUSBD_ENABLE_EP_INT(EPB, HSUSBD_EPINTEN_RXPKIEN_Msk);
+
+ /*****************************************************/
+ /* EPC ==> Interrupt IN endpoint, address 3 */
+ HSUSBD_SetEpBufAddr(EPC, EPC_BUF_BASE, EPC_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPC, EPC_OTHER_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPC, EPADR_HW2SW(EPC), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_IN);
+
+ /* EPD ==> Interrupt OUT endpoint, address 4 */
+ HSUSBD_SetEpBufAddr(EPD, EPD_BUF_BASE, EPD_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPD, EPD_OTHER_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPD, EPADR_HW2SW(EPD), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_OUT);
+ HSUSBD_ENABLE_EP_INT(EPD, HSUSBD_EPINTEN_RXPKIEN_Msk);
+
+ /*****************************************************/
+ /* EPE ==> Bulk IN endpoint, address 5 */
+ HSUSBD_SetEpBufAddr(EPE, EPE_BUF_BASE, EPE_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPE, EPE_OTHER_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPE, EPADR_HW2SW(EPE), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_IN);
+
+
+ /* EPF ==> Bulk OUT endpoint, address 6 */
+ HSUSBD_SetEpBufAddr(EPF, EPF_BUF_BASE, EPF_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPF, EPF_OTHER_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPF, EPADR_HW2SW(EPF), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_OUT);
+ HSUSBD_ENABLE_EP_INT(EPF, HSUSBD_EPINTEN_RXPKIEN_Msk);
+
+ /*****************************************************/
+ /* EPG ==> Interrupt IN endpoint, address 7 */
+ HSUSBD_SetEpBufAddr(EPG, EPG_BUF_BASE, EPG_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPG, EPG_OTHER_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPG, EPADR_HW2SW(EPG), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_IN);
+
+ /* EPH ==> Interrupt OUT endpoint, address 8 */
+ HSUSBD_SetEpBufAddr(EPH, EPH_BUF_BASE, EPH_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPH, EPH_OTHER_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPH, EPADR_HW2SW(EPH), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_OUT);
+ HSUSBD_ENABLE_EP_INT(EPH, HSUSBD_EPINTEN_RXPKIEN_Msk);
+}
+
+static void _nu_ep_partition_hs(void)
+{
+ /*****************************************************/
+ /* EPA ==> Bulk IN endpoint, address 1 */
+ HSUSBD_SetEpBufAddr(EPA, EPA_BUF_BASE, EPA_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPA, EPA_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPA, EPADR_HW2SW(EPA), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_IN);
+
+
+ /* EPB ==> Bulk OUT endpoint, address 2 */
+ HSUSBD_SetEpBufAddr(EPB, EPB_BUF_BASE, EPB_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPB, EPB_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPB, EPADR_HW2SW(EPB), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_OUT);
+ HSUSBD_ENABLE_EP_INT(EPB, HSUSBD_EPINTEN_RXPKIEN_Msk);
+
+ /*****************************************************/
+ /* EPC ==> Interrupt IN endpoint, address 3 */
+ HSUSBD_SetEpBufAddr(EPC, EPC_BUF_BASE, EPC_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPC, EPC_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPC, EPADR_HW2SW(EPC), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_IN);
+
+ /* EPD ==> Interrupt OUT endpoint, address 4 */
+ HSUSBD_SetEpBufAddr(EPD, EPD_BUF_BASE, EPD_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPD, EPD_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPD, EPADR_HW2SW(EPD), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_OUT);
+ HSUSBD_ENABLE_EP_INT(EPD, HSUSBD_EPINTEN_RXPKIEN_Msk);
+
+ /*****************************************************/
+ /* EPE ==> Bulk IN endpoint, address 5 */
+ HSUSBD_SetEpBufAddr(EPE, EPE_BUF_BASE, EPE_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPE, EPE_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPE, EPADR_HW2SW(EPE), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_IN);
+
+
+ /* EPF ==> Bulk OUT endpoint, address 6 */
+ HSUSBD_SetEpBufAddr(EPF, EPF_BUF_BASE, EPF_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPF, EPF_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPF, EPADR_HW2SW(EPF), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_OUT);
+ HSUSBD_ENABLE_EP_INT(EPF, HSUSBD_EPINTEN_RXPKIEN_Msk);
+
+ /*****************************************************/
+ /* EPG ==> Interrupt IN endpoint, address 7 */
+ HSUSBD_SetEpBufAddr(EPG, EPG_BUF_BASE, EPG_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPG, EPG_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPG, EPADR_HW2SW(EPG), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_IN);
+
+ /* EPH ==> Interrupt OUT endpoint, address 8 */
+ HSUSBD_SetEpBufAddr(EPH, EPH_BUF_BASE, EPH_BUF_LEN);
+ HSUSBD_SET_MAX_PAYLOAD(EPH, EPH_MAX_PKT_SIZE);
+ HSUSBD_ConfigEp(EPH, EPADR_HW2SW(EPH), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_OUT);
+ HSUSBD_ENABLE_EP_INT(EPH, HSUSBD_EPINTEN_RXPKIEN_Msk);
+}
+
+static void _nu_ep_partition(void)
+{
+ /* Configure USB controller */
+ /* Enable USB BUS, CEP and EPA ~ EPH global interrupt */
+ HSUSBD_ENABLE_USB_INT(HSUSBD_GINTEN_USBIEN_Msk
+ | HSUSBD_GINTEN_CEPIEN_Msk
+ | HSUSBD_GINTEN_EPAIEN_Msk
+ | HSUSBD_GINTEN_EPBIEN_Msk
+ | HSUSBD_GINTEN_EPCIEN_Msk
+ | HSUSBD_GINTEN_EPDIEN_Msk
+ | HSUSBD_GINTEN_EPEIEN_Msk
+ | HSUSBD_GINTEN_EPFIEN_Msk
+ | HSUSBD_GINTEN_EPGIEN_Msk
+ | HSUSBD_GINTEN_EPHIEN_Msk
+ );
+
+ /* Enable BUS interrupt */
+ HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_DMADONEIEN_Msk
+ | HSUSBD_BUSINTEN_RESUMEIEN_Msk
+ | HSUSBD_BUSINTEN_RSTIEN_Msk
+ | HSUSBD_BUSINTEN_VBUSDETIEN_Msk);
+ /* Reset Address to 0 */
+ HSUSBD_SET_ADDR(0);
+
+ /*****************************************************/
+ /* Control endpoint */
+ HSUSBD_SetEpBufAddr(CEP, CEP_BUF_BASE, CEP_BUF_LEN);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk
+ | HSUSBD_CEPINTEN_STSDONEIEN_Msk
+ );
+
+ _nu_ep_partition_hs();
+}
+
+static void NU_SetupStageCallback(nu_usbd_t *nu_udc)
+{
+ struct urequest setup_packet;
+
+ /* Setup packet process */
+ setup_packet.request_type = (uint8_t)(nu_udc->Instance->SETUP1_0 & 0xfful);
+ setup_packet.bRequest = (uint8_t)((nu_udc->Instance->SETUP1_0 >> 8) & 0xfful);
+ setup_packet.wValue = (uint16_t) nu_udc->Instance->SETUP3_2;
+ setup_packet.wIndex = (uint16_t) nu_udc->Instance->SETUP5_4;
+ setup_packet.wLength = (uint16_t) nu_udc->Instance->SETUP7_6;
+
+ rt_usbd_ep0_setup_handler(&_rt_obj_udc, (struct urequest *)&setup_packet);
+}
+
+static rt_err_t _ep_set_stall(rt_uint8_t address)
+{
+
+ if (address & USB_EPNO_MASK)
+ {
+ HSUSBD_SetEpStall(EPADR_SW2HW(address));
+ }
+ else
+ {
+ /* Not support. Reply STALL. */
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk);
+ }
+ return RT_EOK;
+}
+
+static rt_err_t _ep_clear_stall(rt_uint8_t address)
+{
+ if (address & USB_EPNO_MASK)
+ {
+ HSUSBD_ClearEpStall(EPADR_SW2HW(address));
+ }
+
+ return RT_EOK;
+}
+
+
+static rt_err_t _set_address(rt_uint8_t address)
+{
+ if (0 != address)
+ {
+ nu_usbd.address_tmp = address;
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t _set_config(rt_uint8_t address)
+{
+ return RT_EOK;
+}
+
+static rt_err_t _ep_enable(uep_t ep)
+{
+ RT_ASSERT(ep != RT_NULL);
+ RT_ASSERT(ep->ep_desc != RT_NULL);
+
+ HSUSBD->EP[EPADR_SW2HW(ep->ep_desc->bEndpointAddress)].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE;
+ HSUSBD->EP[EPADR_SW2HW(ep->ep_desc->bEndpointAddress)].EPCFG |= HSUSBD_EP_CFG_VALID;
+
+ return RT_EOK;
+}
+
+static rt_err_t _ep_disable(uep_t ep)
+{
+ RT_ASSERT(ep != RT_NULL);
+ RT_ASSERT(ep->ep_desc != RT_NULL);
+ HSUSBD->EP[EPADR_SW2HW(ep->ep_desc->bEndpointAddress)].EPCFG &= ~HSUSBD_EP_CFG_VALID;
+
+ return RT_EOK;
+}
+
+static rt_err_t _ep0_send_status(void)
+{
+ /* Status Stage */
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk
+ | HSUSBD_CEPINTSTS_SETUPPKIF_Msk
+ );
+
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+
+ return RT_EOK;
+}
+
+__STATIC_INLINE void nu_buffer_cpy(rt_uint8_t address, void *buffer, rt_size_t size)
+{
+ rt_uint32_t i, cnt;
+ rt_uint32_t *_buf_word;
+ rt_uint8_t *_buf_byte;
+
+ _buf_word = (rt_uint32_t *)buffer;
+ cnt = size >> 2;
+ _buf_byte = (rt_uint8_t *)((rt_uint8_t *)buffer + (cnt * 4));
+
+ if ((address & USB_EPNO_MASK)) //EPs
+ {
+ if (address & USB_DIR_IN) //IN
+ {
+ /* Non-control endpoint IN*/
+ for (i = 0; i < cnt; i++)
+ {
+ HSUSBD->EP[EPADR_SW2HW(address)].EPDAT = _buf_word[i];
+ }
+
+ for (i = 0ul; i < (size % 4ul); i++)
+ HSUSBD->EP[EPADR_SW2HW(address)].EPDAT_BYTE = _buf_byte[i];
+ }
+ else //OUT
+ {
+ for (i = 0; i < cnt; i++)
+ {
+ _buf_word[i] = HSUSBD->EP[EPADR_SW2HW(address)].EPDAT;
+ }
+
+ for (i = 0ul; i < (size % 4ul); i++)
+ _buf_byte[i] = HSUSBD->EP[EPADR_SW2HW(address)].EPDAT_BYTE;
+ }
+ }
+ else //Control
+ {
+ if (address & USB_DIR_IN) //IN
+ {
+ for (i = 0; i < cnt; i++)
+ {
+ HSUSBD->CEPDAT = _buf_word[i];
+ }
+
+ for (i = 0ul; i < (size % 4ul); i++)
+ HSUSBD->CEPDAT_BYTE = _buf_byte[i];
+
+ }
+ else //OUT
+ {
+ for (i = 0; i < cnt; i++)
+ {
+ _buf_word[i] = HSUSBD->CEPDAT;
+ }
+
+ for (i = 0ul; i < (size % 4ul); i++)
+ _buf_byte[i] = HSUSBD->CEPDAT_BYTE;
+ }
+ }
+}
+
+static rt_size_t _ep_read(rt_uint8_t address, void *buffer)
+{
+ rt_size_t size = 0;
+
+ RT_ASSERT(!(address & USB_DIR_IN));
+
+ if ((address & USB_EPNO_MASK))
+ {
+ RT_ASSERT(buffer != RT_NULL);
+ size = HSUSBD->EP[EPADR_SW2HW(address)].EPDATCNT & 0xffff;
+ nu_buffer_cpy(address, buffer, size);
+ }
+ else //control transfer
+ {
+
+ size = HSUSBD->CEPRXCNT & 0xffff;
+ if (size)
+ {
+ RT_ASSERT(_rt_obj_udc.stage == STAGE_DOUT);
+ nu_buffer_cpy(address, buffer, size);
+ }
+
+ _ep0_send_status();
+ }
+
+ return size;
+}
+
+static rt_size_t _ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size)
+{
+ RT_ASSERT(!(address & USB_DIR_IN));
+
+ if ((address & USB_EPNO_MASK))
+ {
+ HSUSBD_ENABLE_EP_INT(EPADR_SW2HW(address),
+ HSUSBD_EPINTEN_RXPKIEN_Msk
+ );
+ }
+ else //control transfer
+ {
+ if (size)
+ {
+ RT_ASSERT(_rt_obj_udc.stage == STAGE_DOUT);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_OUTTKIEN_Msk);
+ }
+ else
+ {
+
+ RT_ASSERT(_rt_obj_udc.stage == STAGE_STATUS_OUT);
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk
+ | HSUSBD_CEPINTSTS_STSDONEIF_Msk
+ );
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk
+ | HSUSBD_CEPINTEN_STSDONEIEN_Msk
+ );
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+ }
+
+ }
+
+ return size;
+}
+
+static rt_size_t _ep_write(rt_uint8_t address, void *buffer, rt_size_t size)
+{
+
+ RT_ASSERT((address & USB_DIR_IN));
+
+ if (!(address & USB_EPNO_MASK)) //control transfer
+ {
+ if (size)
+ {
+ nu_buffer_cpy(address, buffer, size);
+ HSUSBD_START_CEP_IN(size);
+ }
+ else//zero length
+ {
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_ZEROLEN);
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk
+ | HSUSBD_CEPINTSTS_SETUPPKIF_Msk);
+
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk
+ | HSUSBD_CEPINTEN_STSDONEIEN_Msk
+ );
+ }
+
+ if (_rt_obj_udc.stage == STAGE_DIN)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_TXPKIF_Msk);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_TXPKIEN_Msk);
+ }
+ else if (_rt_obj_udc.stage == STAGE_DOUT)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_RXPKIF_Msk);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_RXPKIEN_Msk);
+ }
+ }
+ else
+ {
+ /* Non-control endpoint IN*/
+ nu_buffer_cpy(address, buffer, size);
+ HSUSBD->EP[EPADR_SW2HW(address)].EPRSPCTL = HSUSBD_EP_RSPCTL_SHORTTXEN; // packet end
+ HSUSBD->EP[EPADR_SW2HW(address)].EPTXCNT = size;
+
+ if ((HSUSBD->EP[EPADR_SW2HW(address)].EPCFG & HSUSBD_EPCFG_EPTYPE_Msk) == HSUSBD_EP_CFG_TYPE_INT)
+ {
+ HSUSBD_ENABLE_EP_INT(EPADR_SW2HW(address), HSUSBD_EPINTEN_INTKIEN_Msk); //for interrupt transfer timing
+ }
+ else
+ {
+ HSUSBD_ENABLE_EP_INT(EPADR_SW2HW(address), HSUSBD_EPINTEN_TXPKIEN_Msk); //for bulk transfer timing
+ }
+ }
+
+ return size;
+}
+
+
+
+
+static rt_err_t _suspend(void)
+{
+ return RT_EOK;
+}
+
+static rt_err_t _wakeup(void)
+{
+ return RT_EOK;
+}
+
+void _USBD20_IRQHandler(void)
+{
+ __IO rt_uint32_t IrqStL, IrqSt;
+
+ IrqStL = HSUSBD->GINTSTS & HSUSBD->GINTEN; /* get interrupt status */
+
+ if (!IrqStL) return;
+
+ /* USB interrupt */
+ if (IrqStL & HSUSBD_GINTSTS_USBIF_Msk)
+ {
+ IrqSt = HSUSBD->BUSINTSTS & HSUSBD->BUSINTEN;
+
+ if (IrqSt & HSUSBD_BUSINTSTS_SOFIF_Msk)
+ {
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_SOFIF_Msk);
+ rt_usbd_sof_handler(&_rt_obj_udc);
+ }
+ if (IrqSt & HSUSBD_BUSINTSTS_RSTIF_Msk)
+ {
+ /* Reset USB device address */
+ HSUSBD_SET_ADDR(0ul);
+
+ HSUSBD_ResetDMA();
+ HSUSBD->EP[EPA].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk;
+ HSUSBD->EP[EPB].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk;
+ HSUSBD->EP[EPC].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk;
+ HSUSBD->EP[EPD].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk;
+ HSUSBD->EP[EPE].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk;
+ HSUSBD->EP[EPF].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk;
+ HSUSBD->EP[EPG].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk;
+ HSUSBD->EP[EPH].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk;
+
+ if (HSUSBD->OPER & 0x04) /* high speed */
+ {
+ LOG_I("-High Speed-");
+ _nu_ep_partition_hs();
+ }
+ else /* full speed */
+ {
+ LOG_I("-Full Speed-");
+ _nu_ep_partition_fs();
+ }
+
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk);
+ HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk
+ | HSUSBD_BUSINTEN_RESUMEIEN_Msk
+ | HSUSBD_BUSINTEN_SUSPENDIEN_Msk
+ | HSUSBD_BUSINTEN_VBUSDETIEN_Msk
+ );
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_RSTIF_Msk);
+ HSUSBD_CLR_CEP_INT_FLAG(0x1ffc);
+
+ for (rt_uint32_t i = 0ul; i < HSUSBD_MAX_EP; i++)
+ {
+ if ((HSUSBD->EP[i].EPCFG & 0x1ul) == 0x1ul)
+ {
+ HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE;
+ }
+ }
+ rt_usbd_reset_handler(&_rt_obj_udc);
+ HSUSBD_ENABLE_USB();
+ }
+
+ if (IrqSt & HSUSBD_BUSINTSTS_RESUMEIF_Msk)
+ {
+ LOG_I("-Resume-");
+ HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_SUSPENDIEN_Msk);
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_RESUMEIF_Msk);
+ }
+
+ if (IrqSt & HSUSBD_BUSINTSTS_SUSPENDIF_Msk)
+ {
+ LOG_I("-Suspend-");
+ HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_RESUMEIEN_Msk | HSUSBD_BUSINTEN_VBUSDETIEN_Msk);
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_SUSPENDIF_Msk);
+ }
+
+ if (IrqSt & HSUSBD_BUSINTSTS_HISPDIF_Msk)
+ {
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk);
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_HISPDIF_Msk);
+ }
+
+ if (IrqSt & HSUSBD_BUSINTSTS_DMADONEIF_Msk)
+ {
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_DMADONEIF_Msk);
+
+ if (!(HSUSBD->DMACTL & HSUSBD_DMACTL_DMARD_Msk))
+ {
+ HSUSBD_ENABLE_EP_INT(EPD, HSUSBD_EPINTEN_RXPKIEN_Msk);
+ }
+ }
+
+ if (IrqSt & HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk)
+ {
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk);
+ }
+
+ if (IrqSt & HSUSBD_BUSINTSTS_VBUSDETIF_Msk)
+ {
+ if (HSUSBD_IS_ATTACHED())
+ {
+ LOG_I("PLUG IN");
+ /* USB Plug In */
+ HSUSBD_ENABLE_USB();
+ rt_usbd_connect_handler(&_rt_obj_udc);
+
+ }
+ else
+ {
+ LOG_I("Un-Plug");
+ /* USB Un-plug */
+ HSUSBD_DISABLE_USB();
+ rt_usbd_disconnect_handler(&_rt_obj_udc);
+ }
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_VBUSDETIF_Msk);
+ }
+ }
+
+ /* Control Transfer */
+ if (IrqStL & HSUSBD_GINTSTS_CEPIF_Msk)
+ {
+ IrqSt = HSUSBD->CEPINTSTS & HSUSBD->CEPINTEN;
+
+ if (IrqSt & HSUSBD_CEPINTSTS_SETUPTKIF_Msk)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPTKIF_Msk);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_SETUPPKIF_Msk)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk);
+ NU_SetupStageCallback(&nu_usbd);
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk
+ | HSUSBD_CEPINTSTS_RXPKIF_Msk
+ | HSUSBD_CEPINTSTS_STSDONEIF_Msk
+ );
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_OUTTKIF_Msk)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_OUTTKIF_Msk);
+ rt_usbd_ep0_out_handler(&_rt_obj_udc, 0);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_RXPKIEN_Msk);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_INTKIF_Msk)
+ {
+ HSUSBD_ENABLE_CEP_INT(0);
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk);
+ rt_usbd_ep0_in_handler(&_rt_obj_udc);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_PINGIF_Msk)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_PINGIF_Msk);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_TXPKIF_Msk)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_TXPKIF_Msk
+ | HSUSBD_CEPINTSTS_SETUPPKIF_Msk
+ | HSUSBD_CEPINTSTS_STSDONEIF_Msk
+ );
+
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk
+ | HSUSBD_CEPINTEN_SETUPPKIEN_Msk
+ | HSUSBD_CEPINTEN_STSDONEIEN_Msk
+ );
+
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_RXPKIF_Msk)
+ {
+
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk
+ | HSUSBD_CEPINTSTS_STSDONEIF_Msk
+ | HSUSBD_CEPINTSTS_RXPKIF_Msk
+ );
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk
+ | HSUSBD_CEPINTEN_STSDONEIEN_Msk
+ | HSUSBD_CEPINTEN_RXPKIEN_Msk
+ );
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_NAKIF_Msk)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_NAKIF_Msk);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_STALLIF_Msk)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STALLIF_Msk);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_ERRIF_Msk)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_ERRIF_Msk);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_STSDONEIF_Msk)
+ {
+
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk | HSUSBD_CEPINTSTS_SETUPPKIF_Msk);
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk);
+
+ if ((HSUSBD_GET_ADDR() == 0)
+ && ((uint8_t)((nu_usbd.Instance->SETUP1_0 >> 8) & 0xfful) == SET_ADDRESS)
+ )
+ {
+ HSUSBD_SET_ADDR(nu_usbd.address_tmp);
+ LOG_I("SET ADDR: 0x%02x", nu_usbd.address_tmp);
+ nu_usbd.address_tmp = 0;
+
+ }
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_BUFFULLIF_Msk)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_BUFFULLIF_Msk);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk)
+ {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk);
+ return;
+ }
+ }
+
+ /* bulk in */
+ if (IrqStL & HSUSBD_GINTSTS_EPAIF_Msk)
+ {
+ IrqSt = HSUSBD->EP[EPA].EPINTSTS & HSUSBD->EP[EPA].EPINTEN;
+ HSUSBD_ENABLE_EP_INT(EPA, 0);
+ HSUSBD_CLR_EP_INT_FLAG(EPA, IrqSt);
+ rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EPA), 0);
+ }
+
+ /* bulk out */
+ if (IrqStL & HSUSBD_GINTSTS_EPBIF_Msk)
+ {
+ IrqSt = HSUSBD->EP[EPB].EPINTSTS & HSUSBD->EP[EPB].EPINTEN;
+ HSUSBD_CLR_EP_INT_FLAG(EPB, IrqSt);
+ rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EPB), 0);
+ }
+
+ /* interrupt in */
+ if (IrqStL & HSUSBD_GINTSTS_EPCIF_Msk)
+ {
+ IrqSt = HSUSBD->EP[EPC].EPINTSTS & HSUSBD->EP[EPC].EPINTEN;
+ HSUSBD_ENABLE_EP_INT(EPC, 0);
+ HSUSBD_CLR_EP_INT_FLAG(EPC, IrqSt);
+ rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EPC), 0);
+ }
+
+ /* interrupt out */
+ if (IrqStL & HSUSBD_GINTSTS_EPDIF_Msk)
+ {
+ IrqSt = HSUSBD->EP[EPD].EPINTSTS & HSUSBD->EP[EPD].EPINTEN;
+ HSUSBD_CLR_EP_INT_FLAG(EPD, IrqSt);
+ rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EPD), 0);
+ }
+
+ /* bulk in */
+ if (IrqStL & HSUSBD_GINTSTS_EPEIF_Msk)
+ {
+ IrqSt = HSUSBD->EP[EPE].EPINTSTS & HSUSBD->EP[EPE].EPINTEN;
+ HSUSBD_ENABLE_EP_INT(EPE, 0);
+ HSUSBD_CLR_EP_INT_FLAG(EPE, IrqSt);
+
+ rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EPE), 0);
+ }
+
+ /* bulk out */
+ if (IrqStL & HSUSBD_GINTSTS_EPFIF_Msk)
+ {
+ IrqSt = HSUSBD->EP[EPF].EPINTSTS & HSUSBD->EP[EPF].EPINTEN;
+ HSUSBD_CLR_EP_INT_FLAG(EPF, IrqSt);
+ rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EPF), 0);
+ }
+
+ /* interrupt in */
+ if (IrqStL & HSUSBD_GINTSTS_EPGIF_Msk)
+ {
+ IrqSt = HSUSBD->EP[EPG].EPINTSTS & HSUSBD->EP[EPG].EPINTEN;
+ HSUSBD_ENABLE_EP_INT(EPG, 0);
+ HSUSBD_CLR_EP_INT_FLAG(EPG, IrqSt);
+ rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EPG), 0);
+ }
+
+ /* interrupt out */
+ if (IrqStL & HSUSBD_GINTSTS_EPHIF_Msk)
+ {
+ IrqSt = HSUSBD->EP[EPH].EPINTSTS & HSUSBD->EP[EPH].EPINTEN;
+ HSUSBD_CLR_EP_INT_FLAG(EPH, IrqSt);
+ rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EPH), 0);
+ }
+
+}
+
+void USBD20_IRQHandler(void)
+{
+ rt_interrupt_enter();
+
+ _USBD20_IRQHandler();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+static rt_err_t _init(rt_device_t device)
+{
+#if !defined(BSP_USING_HSOTG)
+ uint32_t volatile i;
+
+ /* Initialize USB PHY */
+ SYS_UnlockReg();
+ SYS->USBPHY &= ~SYS_USBPHY_HSUSBROLE_Msk; /* select HSUSBD */
+
+ /* Enable USB PHY */
+ SYS->USBPHY = (SYS->USBPHY & ~(SYS_USBPHY_HSUSBROLE_Msk | SYS_USBPHY_HSUSBACT_Msk)) | SYS_USBPHY_HSUSBEN_Msk;
+
+ for (i = 0; i < 0x1000; i++)
+ __NOP(); // delay > 10 us
+
+ SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;
+ SYS_LockReg();
+#endif
+
+ /* HSUSBD Open */
+ HSUSBD->PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk | HSUSBD_PHYCTL_DPPUEN_Msk);
+ while (1)
+ {
+ HSUSBD->EP[EPA].EPMPS = 0x20ul;
+ if (HSUSBD->EP[EPA].EPMPS == 0x20ul)
+ {
+ break;
+ }
+ }
+
+ /* Force SE0 */
+ HSUSBD_SET_SE0();
+
+ _nu_ep_partition();
+
+#if ENABLE_FULL_SPEED_MODE_ONLY
+ HSUSBD->OPER &= ~HSUSBD_OPER_HISPDEN_Msk;
+#else
+ HSUSBD->OPER |= HSUSBD_OPER_HISPDEN_Msk;
+#endif
+
+ /* Enable USBD interrupt */
+ NVIC_EnableIRQ(USBD20_IRQn);
+
+ /* Start transaction */
+ HSUSBD_Start();
+ return RT_EOK;
+}
+
+const static struct udcd_ops _udc_ops =
+{
+ _set_address,
+ _set_config,
+ _ep_set_stall,
+ _ep_clear_stall,
+ _ep_enable,
+ _ep_disable,
+ _ep_read_prepare,
+ _ep_read,
+ _ep_write,
+ _ep0_send_status,
+ _suspend,
+ _wakeup,
+};
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops _ops =
+{
+ _init,
+ RT_NULL,
+ RT_NULL,
+ RT_NULL,
+ RT_NULL,
+ RT_NULL,
+};
+#endif
+
+int nu_hsusbd_register(void)
+{
+ if (RT_NULL != rt_device_find("usbd"))
+ {
+ LOG_E("\nHSUSBD Register failed. Another USBD device is registered\n");
+ return -RT_ERROR;
+ }
+
+ rt_memset((void *)&_rt_obj_udc, 0, sizeof(struct udcd));
+ _rt_obj_udc.parent.type = RT_Device_Class_USBDevice;
+
+#ifdef RT_USING_DEVICE_OPS
+ _rt_obj_udc.parent.ops = &_ops;
+#else
+ _rt_obj_udc.parent.init = _init;
+#endif
+
+ _rt_obj_udc.parent.user_data = &nu_usbd;
+ _rt_obj_udc.ops = &_udc_ops;
+
+ /* Register endpoint information */
+ _rt_obj_udc.ep_pool = _ep_pool;
+ _rt_obj_udc.ep0.id = &_ep_pool[0];
+
+#if ENABLE_FULL_SPEED_MODE_ONLY
+ _rt_obj_udc.device_is_hs = RT_FALSE; /* Enable Full-speed only */
+#else
+ _rt_obj_udc.device_is_hs = RT_TRUE; /* Support Hi-Speed */
+#endif
+
+ rt_device_register((rt_device_t)&_rt_obj_udc, "usbd", 0);
+
+ rt_usb_device_init();
+ return RT_EOK;
+}
+INIT_DEVICE_EXPORT(nu_hsusbd_register);
+#endif
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
new file mode 100644
index 00000000000..0c96c5336f6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
@@ -0,0 +1,393 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-05 HPHuang First version
+******************************************************************************/
+
+
+#include
+
+#ifdef BSP_USING_I2C
+#include
+#include
+
+/* Private define ---------------------------------------------------------------*/
+#define LOG_TAG "drv.i2c"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME "drv.i2c"
+#define DBG_LEVEL DBG_ERROR
+#define DBG_COLOR
+#include
+
+const rt_uint32_t u32I2C_MASTER_STATUS_START = 0x08UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_REPEAT_START = 0x10UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK = 0x18UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_NACK = 0x20UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_DATA_ACK = 0x28UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_DATA_NACK = 0x30UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_ARBITRATION_LOST = 0x38UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK = 0x40UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_NACK = 0x48UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_DATA_ACK = 0x50UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_DATA_NACK = 0x58UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_BUS_ERROR = 0x00UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_BUS_RELEASED = 0xF8UL;
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct _nu_i2c_bus
+{
+ struct rt_i2c_bus_device parent;
+ I2C_T *I2C;
+ struct rt_i2c_msg *msg;
+ char *device_name;
+} nu_i2c_bus_t;
+
+/* Private variables ------------------------------------------------------------*/
+#ifdef BSP_USING_I2C0
+#define I2C0BUS_NAME "i2c0"
+static nu_i2c_bus_t nu_i2c0 =
+{
+ .I2C = I2C0,
+ .device_name = I2C0BUS_NAME,
+};
+#endif /* BSP_USING_I2C0 */
+
+#ifdef BSP_USING_I2C1
+#define I2C1BUS_NAME "i2c1"
+static nu_i2c_bus_t nu_i2c1 =
+{
+ .I2C = I2C1,
+ .device_name = I2C1BUS_NAME,
+};
+#endif /* BSP_USING_I2C1 */
+
+#ifdef BSP_USING_I2C2
+#define I2C2BUS_NAME "i2c2"
+static nu_i2c_bus_t nu_i2c2 =
+{
+ .I2C = I2C2,
+ .device_name = I2C2BUS_NAME,
+};
+#endif /* BSP_USING_I2C2 */
+
+/* Private functions ------------------------------------------------------------*/
+#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2))
+
+static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+ struct rt_i2c_msg msgs[],
+ rt_uint32_t num);
+
+static const struct rt_i2c_bus_device_ops nu_i2c_ops =
+{
+ .master_xfer = nu_i2c_mst_xfer,
+ .slave_xfer = NULL,
+ .i2c_bus_control = NULL,
+};
+
+static rt_err_t nu_i2c_configure(nu_i2c_bus_t *bus)
+{
+ RT_ASSERT(bus != RT_NULL);
+
+ bus->parent.ops = &nu_i2c_ops;
+ I2C_Open(bus->I2C, 100000);
+
+ return RT_EOK;
+}
+
+static inline rt_err_t nu_i2c_wait_ready_with_timeout(nu_i2c_bus_t *bus)
+{
+ rt_tick_t start = rt_tick_get();
+ while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk))
+ {
+ if ((rt_tick_get() - start) > bus->parent.timeout)
+ {
+ LOG_E("\ni2c: timeout!\n");
+ return -RT_ETIMEOUT;
+ }
+ }
+
+ return RT_EOK;
+}
+
+static inline rt_err_t nu_i2c_send_data(nu_i2c_bus_t *nu_i2c, rt_uint8_t data)
+{
+ I2C_SET_DATA(nu_i2c->I2C, data);
+ I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI);
+ return nu_i2c_wait_ready_with_timeout(nu_i2c);
+}
+
+static rt_err_t nu_i2c_send_address(nu_i2c_bus_t *nu_i2c,
+ struct rt_i2c_msg *msg)
+{
+ rt_uint16_t flags = msg->flags;
+ rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
+ rt_uint8_t addr1, addr2;
+ rt_err_t ret;
+
+
+ if (flags & RT_I2C_ADDR_10BIT)
+ {
+ nu_i2c->I2C->CTL1 |= I2C_CTL1_ADDR10EN_Msk;
+ addr1 = 0xf0 | ((msg->addr >> 7) & 0x06);
+ addr2 = msg->addr & 0xff;
+
+ LOG_D("address1: %d, address2: %d\n", addr1, addr2);
+
+ ret = nu_i2c_send_data(nu_i2c, addr1);
+ if (ret != RT_EOK) /* for timeout condition */
+ return -RT_EIO;
+
+ if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack)
+ {
+ LOG_E("NACK: sending first address failed\n");
+
+ return -RT_EIO;
+ }
+
+ ret = nu_i2c_send_data(nu_i2c, addr2);
+ if (ret != RT_EOK) /* for timeout condition */
+ return -RT_EIO;
+
+ if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack)
+ {
+ LOG_E("NACK: sending second address failed\n");
+
+ return -RT_EIO;
+ }
+
+ if (flags & RT_I2C_RD)
+ {
+ LOG_D("send repeated START signal\n");
+
+ I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_STA_SI);
+ ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
+ if (ret != RT_EOK) /* for timeout condition */
+ return -RT_EIO;
+
+ if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_REPEAT_START) && !ignore_nack)
+ {
+ LOG_E("sending repeated START failed\n");
+
+ return -RT_EIO;
+ }
+
+ addr1 |= 0x01;
+
+ ret = nu_i2c_send_data(nu_i2c, addr1);
+ if (ret != RT_EOK) /* for timeout condition */
+ return -RT_EIO;
+
+ if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK) && !ignore_nack)
+ {
+ LOG_E("NACK: sending read address failed\n");
+
+ return -RT_EIO;
+ }
+ }
+ }
+ else
+ {
+ /* 7-bit addr */
+ addr1 = msg->addr << 1;
+ if (flags & RT_I2C_RD)
+ addr1 |= 1;
+
+ /* Send device address */
+ ret = nu_i2c_send_data(nu_i2c, addr1); /* Send Address */
+ if (ret != RT_EOK) /* for timeout condition */
+ return -RT_EIO;
+
+ if ( (I2C_GET_STATUS(nu_i2c->I2C)
+ != ((flags & RT_I2C_RD) ? u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK : u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK))
+ && !ignore_nack)
+ {
+ LOG_E("sending address failed\n");
+ return -RT_EIO;
+ }
+ }
+
+ return RT_EOK;
+}
+
+static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+ struct rt_i2c_msg msgs[],
+ rt_uint32_t num)
+{
+ struct rt_i2c_msg *msg;
+ nu_i2c_bus_t *nu_i2c;
+ rt_size_t i;
+ rt_uint32_t cnt_data;
+ rt_uint16_t ignore_nack;
+ rt_err_t ret;
+
+ RT_ASSERT(bus != RT_NULL);
+ nu_i2c = (nu_i2c_bus_t *) bus;
+
+ nu_i2c->msg = msgs;
+
+ nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk;
+ ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
+ if (ret != RT_EOK) /* for timeout condition */
+ {
+ rt_set_errno(-RT_ETIMEOUT);
+ return 0;
+ }
+ if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_START)
+ {
+ i = 0;
+ LOG_E("Send START Failed");
+ return i;
+ }
+
+ for (i = 0; i < num; i++)
+ {
+ msg = &msgs[i];
+ ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
+
+ if (!(msg->flags & RT_I2C_NO_START))
+ {
+ if (i)
+ {
+ I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_STA_SI);
+ ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
+ if (ret != RT_EOK) /* for timeout conditrion */
+ break;
+
+ if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_REPEAT_START)
+ {
+ i = 0;
+ LOG_E("Send repeat START Fail");
+ break;
+ }
+ }
+
+ if ((RT_EOK != nu_i2c_send_address(nu_i2c, msg))
+ && !ignore_nack)
+ {
+ i = 0;
+ LOG_E("Send Address Fail");
+ break;
+ }
+ }
+
+
+ if (nu_i2c->msg[i].flags & RT_I2C_RD) /* Receive Bytes */
+ {
+ rt_uint32_t do_rd_nack = (i == (num - 1));
+ for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++)
+ {
+ do_rd_nack += (cnt_data == (nu_i2c->msg[i].len - 1)); /* NACK after last byte for hardware setting */
+ if (do_rd_nack == 2)
+ {
+ I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI);
+ }
+ else
+ {
+ I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI_AA);
+ }
+
+ ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
+ if (ret != RT_EOK) /* for timeout condition */
+ break;
+
+ if (nu_i2c->I2C->CTL0 & I2C_CTL_AA)
+ {
+ if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_DATA_ACK)
+ {
+ i = 0;
+ break;
+ }
+ }
+ else
+ {
+ if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_DATA_NACK)
+ {
+ i = 0;
+ break;
+ }
+ }
+
+ nu_i2c->msg[i].buf[cnt_data] = nu_i2c->I2C->DAT;
+ }
+ }
+ else /* Send Bytes */
+ {
+ for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++)
+ {
+ /* Send register number and MSB of data */
+ ret = nu_i2c_send_data(nu_i2c, (uint8_t)(nu_i2c->msg[i].buf[cnt_data]));
+ if (ret != RT_EOK) /* for timeout condition */
+ break;
+
+ if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_DATA_ACK
+ && !ignore_nack
+ ) /* Send aata and get Ack */
+ {
+ i = 0;
+ break;
+ }
+ }
+ }
+ }
+
+ I2C_STOP(nu_i2c->I2C);
+
+ RT_ASSERT(I2C_GET_STATUS(nu_i2c->I2C) == u32I2C_MASTER_STATUS_BUS_RELEASED);
+ if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_BUS_RELEASED)
+ {
+ i = 0;
+ }
+
+ nu_i2c->msg = RT_NULL;
+ nu_i2c->I2C->CTL1 = 0; /*clear all sub modes like 10 bit mode*/
+ return i;
+}
+
+#endif
+
+/* Public functions -------------------------------------------------------------*/
+int rt_hw_i2c_init(void)
+{
+ rt_err_t ret = RT_ERROR;
+#if defined(BSP_USING_I2C0)
+ SYS_UnlockReg();
+ /* Enable I2C0 clock */
+ SYS_ResetModule(I2C0_RST);
+ SYS_LockReg();
+ nu_i2c_configure(&nu_i2c0);
+ ret = rt_i2c_bus_device_register(&nu_i2c0.parent, nu_i2c0.device_name);
+ RT_ASSERT(RT_EOK == ret);
+#endif /* BSP_USING_I2C0 */
+
+#if defined(BSP_USING_I2C1)
+ SYS_UnlockReg();
+ /* Enable I2C1 clock */
+ SYS_ResetModule(I2C1_RST);
+ SYS_LockReg();
+ nu_i2c_configure(&nu_i2c1);
+ ret = rt_i2c_bus_device_register(&nu_i2c1.parent, nu_i2c1.device_name);
+ RT_ASSERT(RT_EOK == ret);
+#endif /* BSP_USING_I2C1 */
+
+#if defined(BSP_USING_I2C2)
+ SYS_UnlockReg();
+ /* Enable I2C2 clock */
+ SYS_ResetModule(I2C2_RST);
+ SYS_LockReg();
+ nu_i2c_configure(&nu_i2c2);
+ ret = rt_i2c_bus_device_register(&nu_i2c2.parent, nu_i2c2.device_name);
+ RT_ASSERT(RT_EOK == ret);
+#endif /* BSP_USING_I2C2 */
+
+ return ret;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
+
+#endif /* BSP_USING_I2C */
+
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c
new file mode 100644
index 00000000000..35b73832103
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c
@@ -0,0 +1,583 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-7 Wayne Lin First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_I2S)
+
+#include
+#include
+#include
+
+/* Private define ---------------------------------------------------------------*/
+#define DBG_ENABLE
+#define DBG_LEVEL DBG_LOG
+#define DBG_SECTION_NAME "i2s"
+#define DBG_COLOR
+#include
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps);
+static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps);
+static rt_err_t nu_i2s_init(struct rt_audio_device *audio);
+static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream);
+static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream);
+static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info);
+/* Public functions -------------------------------------------------------------*/
+rt_err_t nu_i2s_acodec_register(nu_acodec_ops_t);
+
+/* Private variables ------------------------------------------------------------*/
+static struct nu_i2s g_nu_i2s_dev =
+{
+ .name = "sound0",
+ .i2s_base = I2S0,
+ .i2s_rst = I2S0_RST,
+ .i2s_dais = {
+ [NU_I2S_DAI_PLAYBACK] = {
+ .pdma_perp = PDMA_I2S0_TX,
+ },
+ [NU_I2S_DAI_CAPTURE] = {
+ .pdma_perp = PDMA_I2S0_RX,
+ }
+ }
+};
+
+static void nu_pdma_i2s_rx_cb(void *pvUserData, uint32_t u32EventFilter)
+{
+ nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData;
+ nu_i2s_dai_t psNuI2sDai;
+
+ RT_ASSERT(psNuI2s != RT_NULL);
+ psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE];
+
+ if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
+ {
+ // Report a buffer ready.
+ rt_uint8_t *pbuf_old = &psNuI2sDai->fifo[psNuI2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] ;
+ psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
+
+ /* Report upper layer. */
+ rt_audio_rx_done(&psNuI2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE);
+ }
+}
+
+static void nu_pdma_i2s_tx_cb(void *pvUserData, uint32_t u32EventFilter)
+{
+ nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData;
+ nu_i2s_dai_t psNuI2sDai;
+
+ RT_ASSERT(psNuI2s != RT_NULL);
+ psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
+
+ if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
+ {
+ rt_audio_tx_complete(&psNuI2s->audio);
+ psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
+ }
+}
+
+static rt_err_t nu_i2s_pdma_sc_config(nu_i2s_t psNuI2s, E_NU_I2S_DAI dai)
+{
+ rt_err_t result = RT_EOK;
+ I2S_T *i2s_base;
+ nu_i2s_dai_t psNuI2sDai;
+ int i;
+ uint32_t u32Src, u32Dst;
+ nu_pdma_cb_handler_t pfm_pdma_cb;
+
+ RT_ASSERT(psNuI2s != RT_NULL);
+
+ /* Get base address of i2s register */
+ i2s_base = psNuI2s->i2s_base;
+ psNuI2sDai = &psNuI2s->i2s_dais[dai];
+
+ switch ((int)dai)
+ {
+ case NU_I2S_DAI_PLAYBACK:
+ pfm_pdma_cb = nu_pdma_i2s_tx_cb;
+ u32Src = (uint32_t)&psNuI2sDai->fifo[0];
+ u32Dst = (uint32_t)&i2s_base->TXFIFO;
+ break;
+
+ case NU_I2S_DAI_CAPTURE:
+ pfm_pdma_cb = nu_pdma_i2s_rx_cb;
+ u32Src = (uint32_t)&i2s_base->RXFIFO;
+ u32Dst = (uint32_t)&psNuI2sDai->fifo[0];
+ break;
+
+ default:
+ return -RT_EINVAL;
+ }
+
+ result = nu_pdma_callback_register(psNuI2sDai->pdma_chanid,
+ pfm_pdma_cb,
+ (void *)psNuI2s,
+ NU_PDMA_EVENT_TRANSFER_DONE);
+ RT_ASSERT(result == RT_EOK);
+
+ for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++)
+ {
+ /* Setup dma descriptor entry */
+ result = nu_pdma_desc_setup(psNuI2sDai->pdma_chanid, // Channel ID
+ psNuI2sDai->pdma_descs[i], // this descriptor
+ 32, // 32-bits
+ (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO
+ (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory
+ (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4, // Transfer count
+ psNuI2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER]); // Next descriptor
+ RT_ASSERT(result == RT_EOK);
+ }
+
+ /* Assign head descriptor */
+ result = nu_pdma_sg_transfer(psNuI2sDai->pdma_chanid, psNuI2sDai->pdma_descs[0], 0);
+ RT_ASSERT(result == RT_EOK);
+
+ return result;
+}
+
+static rt_bool_t nu_i2s_capacity_check(struct rt_audio_configure *pconfig)
+{
+ switch (pconfig->samplebits)
+ {
+ case 8:
+ case 16:
+ /* case 24: PDMA constrain */
+ case 32:
+ break;
+ default:
+ goto exit_nu_i2s_capacity_check;
+ }
+
+ switch (pconfig->channels)
+ {
+ case 1:
+ case 2:
+ break;
+ default:
+ goto exit_nu_i2s_capacity_check;
+ }
+
+ return RT_TRUE;
+
+exit_nu_i2s_capacity_check:
+
+ return RT_FALSE;
+}
+
+static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pconfig)
+{
+ rt_err_t result = RT_EOK;
+ nu_acodec_ops_t pNuACodecOps = RT_NULL;
+ RT_ASSERT(psNuI2s->AcodecOps != RT_NULL);
+ pNuACodecOps = psNuI2s->AcodecOps;
+ rt_uint32_t real_samplerate;
+
+ /* Open I2S */
+ if (nu_i2s_capacity_check(pconfig) == RT_TRUE)
+ {
+ /* Reset audio codec */
+ if (pNuACodecOps->nu_acodec_reset)
+ result = pNuACodecOps->nu_acodec_reset();
+
+ if (result != RT_EOK)
+ goto exit_nu_i2s_dai_setup;
+
+ /* Setup audio codec */
+ if (pNuACodecOps->nu_acodec_init)
+ result = pNuACodecOps->nu_acodec_init();
+
+ if (!pNuACodecOps->nu_acodec_init || result != RT_EOK)
+ goto exit_nu_i2s_dai_setup;
+
+ /* Setup acodec samplerate/samplebit/channel */
+ if (pNuACodecOps->nu_acodec_dsp_control)
+ result = pNuACodecOps->nu_acodec_dsp_control(pconfig);
+
+ if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK)
+ goto exit_nu_i2s_dai_setup;
+
+ real_samplerate = I2S_Open(psNuI2s->i2s_base,
+ (psNuI2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? I2S_MODE_SLAVE : I2S_MODE_MASTER,
+ pconfig->samplerate,
+ (((pconfig->samplebits / 8) - 1) << I2S_CTL0_DATWIDTH_Pos),
+ (pconfig->channels == 1) ? I2S_ENABLE_MONO : I2S_DISABLE_MONO,
+ I2S_FORMAT_I2S);
+ LOG_I("Open I2S.");
+
+ /* Open I2S0 interface and set to slave mode, stereo channel, I2S format */
+ if (pconfig->samplerate != real_samplerate)
+ {
+ LOG_W("Real sample rate: %d Hz != preferred sample rate: %d Hz\n", real_samplerate, pconfig->samplerate);
+ }
+
+ /* Set MCLK and enable MCLK */
+ I2S_EnableMCLK(psNuI2s->i2s_base, __HXT);
+
+ /* Set unmute */
+ if (pNuACodecOps->nu_acodec_mixer_control)
+ pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE);
+ }
+ else
+ result = -RT_EINVAL;
+
+exit_nu_i2s_dai_setup:
+
+ return result;
+}
+
+static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
+{
+ rt_err_t result = RT_EOK;
+ nu_i2s_t psNuI2s;
+ nu_acodec_ops_t pNuACodecOps = RT_NULL;
+
+ RT_ASSERT(audio != RT_NULL);
+ RT_ASSERT(caps != RT_NULL);
+
+ psNuI2s = (nu_i2s_t)audio;
+
+ RT_ASSERT(psNuI2s->AcodecOps != RT_NULL);
+
+ pNuACodecOps = psNuI2s->AcodecOps;
+
+ switch (caps->main_type)
+ {
+ case AUDIO_TYPE_QUERY:
+ switch (caps->sub_type)
+ {
+ case AUDIO_TYPE_QUERY:
+ caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER;
+ break;
+ default:
+ result = -RT_ERROR;
+ break;
+ } // switch (caps->sub_type)
+ break;
+
+ case AUDIO_TYPE_MIXER:
+
+ if (pNuACodecOps->nu_acodec_mixer_query)
+ {
+ switch (caps->sub_type)
+ {
+ case AUDIO_MIXER_QUERY:
+ return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask);
+
+ default:
+ return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value);
+ } // switch (caps->sub_type)
+
+ } // if (pNuACodecOps->nu_acodec_mixer_query)
+
+ result = -RT_ERROR;
+ break;
+
+ case AUDIO_TYPE_INPUT:
+ case AUDIO_TYPE_OUTPUT:
+
+ switch (caps->sub_type)
+ {
+ case AUDIO_DSP_PARAM:
+ caps->udata.config.channels = psNuI2s->config.channels;
+ caps->udata.config.samplebits = psNuI2s->config.samplebits;
+ caps->udata.config.samplerate = psNuI2s->config.samplerate;
+ break;
+ case AUDIO_DSP_SAMPLERATE:
+ caps->udata.config.samplerate = psNuI2s->config.samplerate;
+ break;
+ case AUDIO_DSP_CHANNELS:
+ caps->udata.config.channels = psNuI2s->config.channels;
+ break;
+ case AUDIO_DSP_SAMPLEBITS:
+ caps->udata.config.samplebits = psNuI2s->config.samplebits;
+ break;
+ default:
+ result = -RT_ERROR;
+ break;
+ } // switch (caps->sub_type)
+ break;
+
+ } // switch (caps->main_type)
+
+ return result;
+}
+
+static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
+{
+ rt_err_t result = RT_EOK;
+ nu_i2s_t psNuI2s;
+ nu_acodec_ops_t pNuACodecOps = RT_NULL;
+ int stream = -1;
+
+ RT_ASSERT(audio != RT_NULL);
+ RT_ASSERT(caps != RT_NULL);
+
+ psNuI2s = (nu_i2s_t)audio;
+
+ RT_ASSERT(psNuI2s->AcodecOps != RT_NULL);
+ pNuACodecOps = psNuI2s->AcodecOps;
+
+ switch (caps->main_type)
+ {
+ case AUDIO_TYPE_MIXER:
+ if (psNuI2s->AcodecOps->nu_acodec_mixer_control)
+ psNuI2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value);
+ break;
+
+
+ case AUDIO_TYPE_INPUT:
+ stream = AUDIO_STREAM_RECORD;
+ case AUDIO_TYPE_OUTPUT:
+ {
+ rt_bool_t bNeedReset = RT_FALSE;
+
+ if (stream < 0)
+ stream = AUDIO_STREAM_REPLAY;
+
+ switch (caps->sub_type)
+ {
+ case AUDIO_DSP_PARAM:
+ if (rt_memcmp(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0)
+ {
+ rt_memcpy(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure));
+ bNeedReset = RT_TRUE;
+ }
+ break;
+ case AUDIO_DSP_SAMPLEBITS:
+ if (psNuI2s->config.samplerate != caps->udata.config.samplebits)
+ {
+ psNuI2s->config.samplerate = caps->udata.config.samplebits;
+ bNeedReset = RT_TRUE;
+ }
+ break;
+ case AUDIO_DSP_CHANNELS:
+ if (psNuI2s->config.channels != caps->udata.config.channels)
+ {
+ pNuACodecOps->config.channels = caps->udata.config.channels;
+ bNeedReset = RT_TRUE;
+ }
+ break;
+ case AUDIO_DSP_SAMPLERATE:
+ if (psNuI2s->config.samplerate != caps->udata.config.samplerate)
+ {
+ psNuI2s->config.samplerate = caps->udata.config.samplerate;
+ bNeedReset = RT_TRUE;
+ }
+ break;
+ default:
+ result = -RT_ERROR;
+ break;
+ } // switch (caps->sub_type)
+
+ if (bNeedReset)
+ {
+ return nu_i2s_start(audio, stream);
+ }
+ }
+ break;
+ default:
+ result = -RT_ERROR;
+ break;
+ } // switch (caps->main_type)
+
+ return result;
+}
+
+static rt_err_t nu_i2s_init(struct rt_audio_device *audio)
+{
+ rt_err_t result = RT_EOK;
+ nu_i2s_t psNuI2s;
+
+ RT_ASSERT(audio != RT_NULL);
+
+ psNuI2s = (nu_i2s_t)audio;
+
+ /* Reset this module */
+ SYS_ResetModule(psNuI2s->i2s_rst);
+
+ return -(result);
+}
+
+static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream)
+{
+ nu_i2s_t psNuI2s;
+
+ RT_ASSERT(audio != RT_NULL);
+
+ psNuI2s = (nu_i2s_t)audio;
+
+ /* Restart all: I2S and codec. */
+ nu_i2s_stop(audio, stream);
+ if (nu_i2s_dai_setup(psNuI2s, &psNuI2s->config) != RT_EOK)
+ return -RT_ERROR;
+
+ switch (stream)
+ {
+ case AUDIO_STREAM_REPLAY:
+ {
+ nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_PLAYBACK);
+
+ /* Start TX DMA */
+ I2S_ENABLE_TXDMA(psNuI2s->i2s_base);
+
+ /* Enable I2S Tx function */
+ I2S_ENABLE_TX(psNuI2s->i2s_base);
+
+ LOG_I("Start replay.");
+ }
+ break;
+
+ case AUDIO_STREAM_RECORD:
+ {
+ nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_CAPTURE);
+
+ /* Start RX DMA */
+ I2S_ENABLE_RXDMA(psNuI2s->i2s_base);
+
+ /* Enable I2S Rx function */
+ I2S_ENABLE_RX(psNuI2s->i2s_base);
+
+ LOG_I("Start record.");
+ }
+ break;
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream)
+{
+ nu_i2s_t psNuI2s;
+ nu_i2s_dai_t psNuI2sDai = RT_NULL;
+
+ RT_ASSERT(audio != RT_NULL);
+
+ psNuI2s = (nu_i2s_t)audio;
+
+ switch (stream)
+ {
+ case AUDIO_STREAM_REPLAY:
+ psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
+
+ // Disable TX
+ I2S_DISABLE_TXDMA(psNuI2s->i2s_base);
+ I2S_DISABLE_TX(psNuI2s->i2s_base);
+
+ LOG_I("Stop replay.");
+ break;
+
+ case AUDIO_STREAM_RECORD:
+ psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE];
+
+ // Disable RX
+ I2S_DISABLE_RXDMA(psNuI2s->i2s_base);
+ I2S_DISABLE_RX(psNuI2s->i2s_base);
+
+ LOG_I("Stop record.");
+ break;
+
+ default:
+ return -RT_EINVAL;
+ }
+
+ /* Stop DMA transfer. */
+ nu_pdma_channel_terminate(psNuI2sDai->pdma_chanid);
+
+ /* Close I2S */
+ if (!(psNuI2s->i2s_base->CTL0 & (I2S_CTL0_TXEN_Msk | I2S_CTL0_RXEN_Msk)))
+ {
+ I2S_DisableMCLK(psNuI2s->i2s_base);
+ I2S_Close(psNuI2s->i2s_base);
+ LOG_I("Close I2S.");
+ }
+
+ /* Silence */
+ rt_memset((void *)psNuI2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE);
+ psNuI2sDai->fifo_block_idx = 0;
+
+ return RT_EOK;
+}
+
+static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info)
+{
+ nu_i2s_t psNuI2s;
+
+ RT_ASSERT(audio != RT_NULL);
+ RT_ASSERT(info != RT_NULL);
+
+ psNuI2s = (nu_i2s_t)audio;
+
+ info->buffer = (rt_uint8_t *)psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo ;
+ info->total_size = NU_I2S_DMA_FIFO_SIZE;
+ info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE;
+ info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER;
+
+ return;
+}
+
+static struct rt_audio_ops nu_i2s_audio_ops =
+{
+ .getcaps = nu_i2s_getcaps,
+ .configure = nu_i2s_configure,
+
+ .init = nu_i2s_init,
+ .start = nu_i2s_start,
+ .stop = nu_i2s_stop,
+ .transmit = RT_NULL,
+ .buffer_info = nu_i2s_buffer_info
+};
+
+static rt_err_t nu_hw_i2s_pdma_allocate(nu_i2s_dai_t psNuI2sDai)
+{
+ /* Allocate I2S nu_dma channel */
+ if ((psNuI2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuI2sDai->pdma_perp)) < 0)
+ {
+ goto nu_hw_i2s_pdma_allocate;
+ }
+
+ return RT_EOK;
+
+nu_hw_i2s_pdma_allocate:
+
+ return -(RT_ERROR);
+}
+
+int rt_hw_i2s_init(void)
+{
+ int i = 0;
+ nu_i2s_dai_t psNuI2sDai;
+
+ for (i = 0; i < NU_I2S_DAI_CNT; i++)
+ {
+ uint8_t *pu8ptr = rt_malloc(NU_I2S_DMA_FIFO_SIZE);
+ psNuI2sDai = &g_nu_i2s_dev.i2s_dais[i];
+ psNuI2sDai->fifo = pu8ptr;
+ rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE);
+ RT_ASSERT(psNuI2sDai->fifo != RT_NULL);
+
+ psNuI2sDai->pdma_chanid = -1;
+ psNuI2sDai->fifo_block_idx = 0;
+ RT_ASSERT(nu_hw_i2s_pdma_allocate(psNuI2sDai) == RT_EOK);
+
+ RT_ASSERT(nu_pdma_sgtbls_allocate(&psNuI2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK);
+ }
+
+ /* Register ops of audio device */
+ g_nu_i2s_dev.audio.ops = &nu_i2s_audio_ops;
+
+ /* Register device, RW: it is with replay and record functions. */
+ rt_audio_register(&g_nu_i2s_dev.audio, g_nu_i2s_dev.name, RT_DEVICE_FLAG_RDWR, &g_nu_i2s_dev);
+
+ return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2s_init);
+#endif //#if defined(BSP_USING_I2S)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h
new file mode 100644
index 00000000000..3fe99f3e3b9
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-7 Wayne First version
+*
+******************************************************************************/
+
+#ifndef __DRV_I2S_H__
+#define __DRV_I2S_H__
+
+#include
+#include
+#include
+
+#if !defined(NU_I2S_DMA_FIFO_SIZE)
+ #define NU_I2S_DMA_FIFO_SIZE (2048)
+#endif
+
+#if !defined(NU_I2S_DMA_BUF_BLOCK_NUMBER)
+ #define NU_I2S_DMA_BUF_BLOCK_NUMBER (2)
+#endif
+
+#if ( (NU_I2S_DMA_FIFO_SIZE % NU_I2S_DMA_BUF_BLOCK_NUMBER) != 0 )
+ #error "Please give an aligned definition"
+#endif
+#if ( NU_I2S_DMA_FIFO_SIZE < 2048 )
+ #warning "DMA FIFO too small, miss voice?"
+#endif
+
+#define NU_I2S_DMA_BUF_BLOCK_SIZE (NU_I2S_DMA_FIFO_SIZE/NU_I2S_DMA_BUF_BLOCK_NUMBER)
+
+typedef enum
+{
+ NU_I2S_DAI_PLAYBACK,
+ NU_I2S_DAI_CAPTURE,
+ NU_I2S_DAI_CNT
+} E_NU_I2S_DAI;
+
+typedef enum
+{
+ NU_ACODEC_ROLE_MASTER,
+ NU_ACODEC_ROLE_SLAVE,
+} E_NU_ACODEC_ROLE;
+
+typedef struct
+{
+ char *name;
+
+ E_NU_ACODEC_ROLE role;
+
+ struct rt_audio_configure config;
+
+ rt_err_t (*nu_acodec_init)(void);
+
+ rt_err_t (*nu_acodec_reset)(void);
+
+ rt_err_t (*nu_acodec_dsp_control)(struct rt_audio_configure *config);
+
+ rt_err_t (*nu_acodec_mixer_control)(rt_uint32_t ui32Item, rt_uint32_t ui32Value);
+
+ rt_err_t (*nu_acodec_mixer_query)(rt_uint32_t ui32Item, rt_uint32_t *ui32Value);
+
+} nu_acodec_ops;
+
+typedef nu_acodec_ops *nu_acodec_ops_t;
+
+struct nu_i2s_dai
+{
+ int16_t pdma_perp;
+ int8_t pdma_chanid;
+ rt_uint8_t *fifo;
+ int16_t fifo_block_idx;
+ nu_pdma_desc_t pdma_descs[NU_I2S_DMA_BUF_BLOCK_NUMBER];
+};
+typedef struct nu_i2s_dai *nu_i2s_dai_t;
+
+struct nu_i2s
+{
+ struct rt_audio_device audio;
+ struct rt_audio_configure config;
+
+ char *name;
+ I2S_T *i2s_base;
+ uint32_t i2s_rst;
+
+ struct nu_i2s_dai i2s_dais[NU_I2S_DAI_CNT];
+ nu_acodec_ops_t AcodecOps;
+};
+typedef struct nu_i2s *nu_i2s_t;
+
+#endif // __DRV_I2S_H___
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.c
new file mode 100644
index 00000000000..6e3a86ae313
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.c
@@ -0,0 +1,997 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-7 Wayne First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_PDMA)
+
+#include
+#include
+#include
+#include
+
+/* Private define ---------------------------------------------------------------*/
+// RT_DEV_NAME_PREFIX pdma
+
+#ifndef NU_PDMA_MEMFUN_ACTOR_MAX
+ #define NU_PDMA_MEMFUN_ACTOR_MAX (4)
+#endif
+
+#define NU_PDMA_SG_TBL_MAXSIZE (NU_PDMA_SG_LIMITED_DISTANCE/sizeof(DSCT_T))
+
+#define NU_PDMA_CH_MAX (PDMA_CH_MAX) /* Specify maximum channels of PDMA */
+#define NU_PDMA_CH_Pos (0) /* Specify first channel number of PDMA */
+#define NU_PDMA_CH_Msk (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos)
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_pdma_periph_ctl
+{
+ uint32_t m_u32Peripheral;
+ nu_pdma_memctrl_t m_eMemCtl;
+};
+typedef struct nu_pdma_periph_ctl nu_pdma_periph_ctl_t;
+
+struct nu_pdma_chn
+{
+ nu_pdma_cb_handler_t m_pfnCBHandler;
+ void *m_pvUserData;
+ uint32_t m_u32EventFilter;
+ uint32_t m_u32IdleTimeout_us;
+ nu_pdma_periph_ctl_t m_spPeripCtl;
+};
+typedef struct nu_pdma_chn nu_pdma_chn_t;
+
+struct nu_pdma_memfun_actor
+{
+ int m_i32ChannID;
+ uint32_t m_u32Result;
+ uint32_t m_u32TrigTransferCnt;
+ rt_sem_t m_psSemMemFun;
+} ;
+typedef struct nu_pdma_memfun_actor *nu_pdma_memfun_actor_t;
+
+/* Private functions ------------------------------------------------------------*/
+static int nu_pdma_peripheral_set(uint32_t u32PeriphType);
+static void nu_pdma_init(void);
+static void nu_pdma_channel_enable(int i32ChannID);
+static void nu_pdma_channel_disable(int i32ChannID);
+static void nu_pdma_channel_reset(int i32ChannID);
+static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us);
+static void nu_pdma_periph_ctrl_fill(int i32ChannID, int i32CtlPoolIdx);
+static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int count, nu_pdma_memctrl_t eMemCtl);
+static void nu_pdma_memfun_cb(void *pvUserData, uint32_t u32Events);
+static void nu_pdma_memfun_actor_init(void);
+static int nu_pdma_memfun_employ(void);
+static int nu_pdma_non_transfer_count_get(int32_t i32ChannID);
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+static volatile int nu_pdma_inited = 0;
+static volatile uint32_t nu_pdma_chn_mask = 0;
+static nu_pdma_chn_t nu_pdma_chn_arr[NU_PDMA_CH_MAX];
+static rt_mutex_t g_mutex_res = RT_NULL;
+static volatile uint32_t nu_pdma_memfun_actor_mask = 0;
+static volatile uint32_t nu_pdma_memfun_actor_maxnum = 0;
+static rt_sem_t nu_pdma_memfun_actor_pool_sem = RT_NULL;
+static rt_mutex_t nu_pdma_memfun_actor_pool_lock = RT_NULL;
+
+static const nu_pdma_periph_ctl_t g_nu_pdma_peripheral_ctl_pool[ ] =
+{
+ // M2M
+ { PDMA_MEM, eMemCtl_SrcInc_DstInc },
+
+ // M2P
+ { PDMA_USB_TX, eMemCtl_SrcInc_DstFix },
+
+ { PDMA_UART0_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_UART1_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_UART2_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_UART3_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_UART4_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_UART5_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_UART6_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_UART7_TX, eMemCtl_SrcInc_DstFix },
+
+ { PDMA_USCI0_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_USCI1_TX, eMemCtl_SrcInc_DstFix },
+
+ { PDMA_QSPI0_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_QSPI1_TX, eMemCtl_SrcInc_DstFix },
+
+ { PDMA_SPI0_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_SPI1_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_SPI2_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_SPI3_TX, eMemCtl_SrcInc_DstFix },
+
+ { PDMA_I2C0_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_I2C1_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_I2C2_TX, eMemCtl_SrcInc_DstFix },
+
+ { PDMA_I2S0_TX, eMemCtl_SrcInc_DstFix },
+
+ { PDMA_DAC0_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_DAC1_TX, eMemCtl_SrcInc_DstFix },
+
+ { PDMA_EPWM0_CH0_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_EPWM0_CH1_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_EPWM0_CH2_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_EPWM0_CH3_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_EPWM0_CH4_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_EPWM1_CH0_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_EPWM1_CH1_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_EPWM1_CH2_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_EPWM1_CH3_TX, eMemCtl_SrcInc_DstFix },
+ { PDMA_EPWM1_CH4_TX, eMemCtl_SrcInc_DstFix },
+
+ // P2M
+ { PDMA_USB_RX, eMemCtl_SrcFix_DstInc },
+
+ { PDMA_UART0_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_UART1_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_UART2_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_UART3_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_UART4_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_UART5_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_UART6_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_UART7_RX, eMemCtl_SrcFix_DstInc },
+
+ { PDMA_USCI0_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_USCI1_RX, eMemCtl_SrcFix_DstInc },
+
+ { PDMA_QSPI0_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_QSPI1_RX, eMemCtl_SrcFix_DstInc },
+
+ { PDMA_SPI0_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_SPI1_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_SPI2_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_SPI3_RX, eMemCtl_SrcFix_DstInc },
+
+ { PDMA_EPWM0_P1_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_EPWM0_P2_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_EPWM0_P3_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_EPWM1_P1_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_EPWM1_P2_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_EPWM1_P3_RX, eMemCtl_SrcFix_DstInc },
+
+ { PDMA_I2C0_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_I2C1_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_I2C2_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_I2S0_RX, eMemCtl_SrcFix_DstInc },
+
+ { PDMA_EADC0_RX, eMemCtl_SrcFix_DstInc },
+ { PDMA_EADC1_RX, eMemCtl_SrcFix_DstInc },
+};
+#define NU_PERIPHERAL_SIZE ( sizeof(g_nu_pdma_peripheral_ctl_pool) / sizeof(g_nu_pdma_peripheral_ctl_pool[0]) )
+
+static struct nu_pdma_memfun_actor nu_pdma_memfun_actor_arr[NU_PDMA_MEMFUN_ACTOR_MAX];
+
+/* SG table pool */
+static DSCT_T nu_pdma_sgtbl_arr[NU_PDMA_SGTBL_POOL_SIZE] = { 0 };
+static uint32_t nu_pdma_sgtbl_token[RT_ALIGN(NU_PDMA_SGTBL_POOL_SIZE, 32) / 32];
+static rt_mutex_t g_mutex_sg = RT_NULL;
+
+static int nu_pdma_peripheral_set(uint32_t u32PeriphType)
+{
+ int idx = 0;
+
+ while (idx < NU_PERIPHERAL_SIZE)
+ {
+ if (g_nu_pdma_peripheral_ctl_pool[idx].m_u32Peripheral == u32PeriphType)
+ return idx;
+ idx++;
+ }
+
+ // Not such peripheral
+ return -1;
+}
+
+static void nu_pdma_periph_ctrl_fill(int i32ChannID, int i32CtlPoolIdx)
+{
+ nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos];
+ psPdmaChann->m_spPeripCtl.m_u32Peripheral = g_nu_pdma_peripheral_ctl_pool[i32CtlPoolIdx].m_u32Peripheral;
+ psPdmaChann->m_spPeripCtl.m_eMemCtl = g_nu_pdma_peripheral_ctl_pool[i32CtlPoolIdx].m_eMemCtl;
+}
+
+static void nu_pdma_init(void)
+{
+ int latest = 0;
+ if (nu_pdma_inited)
+ return;
+
+ g_mutex_res = rt_mutex_create("pdmalock", RT_IPC_FLAG_FIFO);
+ RT_ASSERT(g_mutex_res != RT_NULL);
+
+ g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_FIFO);
+ RT_ASSERT(g_mutex_sg != RT_NULL);
+
+ nu_pdma_chn_mask = ~NU_PDMA_CH_Msk;
+ rt_memset(nu_pdma_chn_arr, 0x00, sizeof(nu_pdma_chn_t));
+
+ NVIC_EnableIRQ(PDMA_IRQn);
+
+ /* Initialize PDMA setting */
+ PDMA_Open(PDMA, NU_PDMA_CH_Msk);
+ PDMA_Close(PDMA);
+
+ rt_memset(&nu_pdma_sgtbl_arr[0], 0x00, sizeof(nu_pdma_sgtbl_arr));
+
+ /* Assign first SG table address as PDMA SG table base address */
+ PDMA->SCATBA = (uint32_t)&nu_pdma_sgtbl_arr[0];
+
+ /* Initializa token pool. */
+ rt_memset(&nu_pdma_sgtbl_token[0], 0xff, sizeof(nu_pdma_sgtbl_token));
+ latest = NU_PDMA_SGTBL_POOL_SIZE / 32;
+ nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
+
+ nu_pdma_inited = 1;
+}
+
+static void nu_pdma_channel_enable(int i32ChannID)
+{
+ PDMA_Open(PDMA, 1 << i32ChannID);
+}
+
+static inline void nu_pdma_channel_disable(int i32ChannID)
+{
+ PDMA->CHCTL &= ~(1 << i32ChannID);
+}
+
+static inline void nu_pdma_channel_reset(int i32ChannID)
+{
+ PDMA->CHRST = (1 << i32ChannID);
+}
+
+void nu_pdma_channel_terminate(int i32ChannID)
+{
+ int i;
+ uint32_t u32EnabledChans;
+ int ch_mask = 0;
+
+ if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+ goto exit_pdma_channel_terminate;
+
+ rt_mutex_take(g_mutex_res, RT_WAITING_FOREVER);
+
+ // Suspend all channels.
+ u32EnabledChans = nu_pdma_chn_mask & NU_PDMA_CH_Msk;
+ while ((i = nu_ctz(u32EnabledChans)) != 32)
+ {
+ ch_mask = (1 << i);
+ if (i == i32ChannID)
+ {
+ u32EnabledChans &= ~ch_mask;
+ continue;
+ }
+
+ // Pause the channel
+ PDMA_PAUSE(PDMA, i);
+
+ // Wait for channel to finish current transfer
+ while (PDMA->TACTSTS & ch_mask) { }
+
+ u32EnabledChans &= ~ch_mask;
+ } //while
+
+ // Reset specified channel ID
+ nu_pdma_channel_reset(i32ChannID);
+
+ // Clean descriptor table control register.
+ PDMA->DSCT[i32ChannID].CTL = 0UL;
+
+ // Resume all channels.
+ u32EnabledChans = nu_pdma_chn_mask & NU_PDMA_CH_Msk;
+ while ((i = nu_ctz(u32EnabledChans)) != 32)
+ {
+ ch_mask = (1 << i);
+
+ PDMA->CHCTL |= ch_mask;
+ PDMA_Trigger(PDMA, i);
+ u32EnabledChans &= ~ch_mask;
+ }
+
+ rt_mutex_release(g_mutex_res);
+
+exit_pdma_channel_terminate:
+
+ return;
+}
+
+static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us)
+{
+ rt_err_t ret = RT_EINVAL;
+
+ if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+ goto exit_nu_pdma_timeout_set;
+
+ nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32IdleTimeout_us = i32Timeout_us;
+
+ if (i32Timeout_us && i32ChannID <= 1) // M480 limit
+ {
+ uint32_t u32ToClk_Max = 1000000 / (CLK_GetHCLKFreq() / (1 << 8));
+ uint32_t u32Divider = (i32Timeout_us / u32ToClk_Max) / (1 << 16);
+ uint32_t u32TOutCnt = (i32Timeout_us / u32ToClk_Max) % (1 << 16);
+
+ PDMA_DisableTimeout(PDMA, 1 << i32ChannID);
+ PDMA_EnableInt(PDMA, i32ChannID, PDMA_INT_TIMEOUT); // Interrupt type
+
+ if (u32Divider > 7)
+ {
+ u32Divider = 7;
+ u32TOutCnt = (1 << 16);
+ }
+ PDMA->TOUTPSC |= (u32Divider << (PDMA_TOUTPSC_TOUTPSC1_Pos * i32ChannID));
+ PDMA_SetTimeOut(PDMA, i32ChannID, 1, u32TOutCnt);
+
+ ret = RT_EOK;
+ }
+ else
+ {
+ PDMA_DisableInt(PDMA, i32ChannID, PDMA_INT_TIMEOUT); // Interrupt type
+ PDMA_DisableTimeout(PDMA, 1 << i32ChannID);
+ }
+
+exit_nu_pdma_timeout_set:
+
+ return -(ret);
+}
+
+int nu_pdma_channel_allocate(int32_t i32PeripType)
+{
+ int i, i32PeripCtlIdx;
+
+ nu_pdma_init();
+
+ if ((i32PeripCtlIdx = nu_pdma_peripheral_set(i32PeripType)) < 0)
+ goto exit_nu_pdma_channel_allocate;
+
+ /* Find the position of first '0' in nu_pdma_chn_mask. */
+ i = nu_cto(nu_pdma_chn_mask);
+ if (i != 32)
+ {
+ nu_pdma_chn_mask |= (1 << i);
+ rt_memset(nu_pdma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof(nu_pdma_chn_t));
+
+ /* Set idx number of g_nu_pdma_peripheral_ctl_pool */
+ nu_pdma_periph_ctrl_fill(i, i32PeripCtlIdx);
+
+ /* Reset channel */
+ nu_pdma_channel_reset(i);
+
+ nu_pdma_channel_enable(i);
+
+ return i;
+ }
+
+exit_nu_pdma_channel_allocate:
+ // No channel available
+ return -(RT_ERROR);
+}
+
+rt_err_t nu_pdma_channel_free(int i32ChannID)
+{
+ rt_err_t ret = RT_EINVAL;
+
+ if (! nu_pdma_inited)
+ goto exit_nu_pdma_channel_free;
+
+ if (i32ChannID < NU_PDMA_CH_MAX && i32ChannID >= NU_PDMA_CH_Pos)
+ {
+ nu_pdma_chn_mask &= ~(1 << i32ChannID);
+ nu_pdma_channel_disable(i32ChannID);
+ ret = RT_EOK;
+ }
+exit_nu_pdma_channel_free:
+
+ return -(ret);
+}
+
+rt_err_t nu_pdma_callback_register(int i32ChannID, nu_pdma_cb_handler_t pfnHandler, void *pvUserData, uint32_t u32EventFilter)
+{
+ rt_err_t ret = RT_EINVAL;
+
+ if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+ goto exit_nu_pdma_callback_register;
+
+ nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pfnCBHandler = pfnHandler;
+ nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pvUserData = pvUserData;
+ nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter = u32EventFilter;
+
+ ret = RT_EOK;
+
+exit_nu_pdma_callback_register:
+
+ return -(ret) ;
+}
+
+nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cb_handler_t *ppfnHandler_Hijack,
+ void **ppvUserData_Hijack, uint32_t *pu32Events_Hijack)
+{
+ nu_pdma_cb_handler_t pfnHandler_Org = NULL;
+ void *pvUserData_Org;
+ uint32_t u32Events_Org;
+
+ RT_ASSERT(ppfnHandler_Hijack != NULL);
+ RT_ASSERT(ppvUserData_Hijack != NULL);
+ RT_ASSERT(pu32Events_Hijack != NULL);
+
+ if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+ goto exit_nu_pdma_callback_hijack;
+
+ pfnHandler_Org = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pfnCBHandler;
+ pvUserData_Org = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pvUserData;
+ u32Events_Org = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter;
+
+ nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pfnCBHandler = *ppfnHandler_Hijack;
+ nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pvUserData = *ppvUserData_Hijack;
+ nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter = *pu32Events_Hijack;
+
+ *ppfnHandler_Hijack = pfnHandler_Org;
+ *ppvUserData_Hijack = pvUserData_Org;
+ *pu32Events_Hijack = u32Events_Org;
+
+exit_nu_pdma_callback_hijack:
+
+ return pfnHandler_Org;
+}
+
+static int nu_pdma_non_transfer_count_get(int32_t i32ChannID)
+{
+ return ((PDMA->DSCT[i32ChannID].CTL & PDMA_DSCT_CTL_TXCNT_Msk) >> PDMA_DSCT_CTL_TXCNT_Pos) + 1;
+}
+
+int nu_pdma_transferred_byte_get(int32_t i32ChannID, int32_t i32TriggerByteLen)
+{
+ int i32BitWidth = 0;
+ int cur_txcnt = 0;
+
+ if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+ goto exit_nu_pdma_transferred_byte_get;
+
+ i32BitWidth = PDMA->DSCT[i32ChannID].CTL & PDMA_DSCT_CTL_TXWIDTH_Msk;
+ i32BitWidth = (i32BitWidth == PDMA_WIDTH_8) ? 1 : (i32BitWidth == PDMA_WIDTH_16) ? 2 : (i32BitWidth == PDMA_WIDTH_32) ? 4 : 0;
+
+ cur_txcnt = nu_pdma_non_transfer_count_get(i32ChannID);
+
+ return (i32TriggerByteLen - (cur_txcnt) * i32BitWidth);
+
+exit_nu_pdma_transferred_byte_get:
+
+ return -1;
+}
+
+nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID)
+{
+ nu_pdma_memctrl_t eMemCtrl = eMemCtl_Undefined;
+
+ if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+ goto exit_nu_pdma_channel_memctrl_get;
+
+ eMemCtrl = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl.m_eMemCtl;
+
+exit_nu_pdma_channel_memctrl_get:
+
+ return eMemCtrl;
+}
+
+rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl)
+{
+ rt_err_t ret = RT_EINVAL;
+ nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos];
+
+
+ if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+ goto exit_nu_pdma_channel_memctrl_set;
+ else if ((eMemCtrl < eMemCtl_SrcFix_DstFix) || (eMemCtrl > eMemCtl_SrcInc_DstInc))
+ goto exit_nu_pdma_channel_memctrl_set;
+
+ /* PDMA_MEM/SAR_FIX/BURST mode is not supported. */
+ if ((psPdmaChann->m_spPeripCtl.m_u32Peripheral == PDMA_MEM) &&
+ ((eMemCtrl == eMemCtl_SrcFix_DstInc) || (eMemCtrl == eMemCtl_SrcFix_DstFix)))
+ goto exit_nu_pdma_channel_memctrl_set;
+
+ nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl.m_eMemCtl = eMemCtrl;
+
+ ret = RT_EOK;
+
+exit_nu_pdma_channel_memctrl_set:
+
+ return -(ret);
+}
+
+static void nu_pdma_channel_memctrl_fill(nu_pdma_memctrl_t eMemCtl, uint32_t *pu32SrcCtl, uint32_t *pu32DstCtl)
+{
+ switch ((int)eMemCtl)
+ {
+ case eMemCtl_SrcFix_DstFix:
+ *pu32SrcCtl = PDMA_SAR_FIX;
+ *pu32DstCtl = PDMA_DAR_FIX;
+ break;
+ case eMemCtl_SrcFix_DstInc:
+ *pu32SrcCtl = PDMA_SAR_FIX;
+ *pu32DstCtl = PDMA_DAR_INC;
+ break;
+ case eMemCtl_SrcInc_DstFix:
+ *pu32SrcCtl = PDMA_SAR_INC;
+ *pu32DstCtl = PDMA_DAR_FIX;
+ break;
+ case eMemCtl_SrcInc_DstInc:
+ *pu32SrcCtl = PDMA_SAR_INC;
+ *pu32DstCtl = PDMA_DAR_INC;
+ break;
+ default:
+ break;
+ }
+}
+
+/* This is for Scatter-gather DMA. */
+rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc,
+ uint32_t u32AddrDst, int32_t i32TransferCnt, nu_pdma_desc_t next)
+{
+ nu_pdma_periph_ctl_t *psPeriphCtl = NULL;
+
+ uint32_t u32SrcCtl = 0;
+ uint32_t u32DstCtl = 0;
+
+ rt_err_t ret = RT_EINVAL;
+
+ if (!dma_desc)
+ goto exit_nu_pdma_desc_setup;
+ else if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+ goto exit_nu_pdma_desc_setup;
+ else if (!(u32DataWidth == 8 || u32DataWidth == 16 || u32DataWidth == 32))
+ goto exit_nu_pdma_desc_setup;
+ else if ((u32AddrSrc % (u32DataWidth / 8)) || (u32AddrDst % (u32DataWidth / 8)))
+ goto exit_nu_pdma_desc_setup;
+
+ psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl;
+
+ nu_pdma_channel_memctrl_fill(psPeriphCtl->m_eMemCtl, &u32SrcCtl, &u32DstCtl);
+
+ dma_desc->CTL = ((i32TransferCnt - 1) << PDMA_DSCT_CTL_TXCNT_Pos) |
+ ((u32DataWidth == 8) ? PDMA_WIDTH_8 : (u32DataWidth == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32) |
+ u32SrcCtl |
+ u32DstCtl |
+ PDMA_OP_BASIC;
+
+ dma_desc->SA = u32AddrSrc;
+ dma_desc->DA = u32AddrDst;
+ dma_desc->NEXT = 0; /* Terminating node by default. */
+
+ if (psPeriphCtl->m_u32Peripheral == PDMA_MEM)
+ {
+ /* For M2M transfer */
+ dma_desc->CTL |= (PDMA_REQ_BURST | PDMA_BURST_32);
+ }
+ else
+ {
+ /* For P2M and M2P transfer */
+ dma_desc->CTL |= (PDMA_REQ_SINGLE);
+ }
+
+ if (next)
+ {
+ /* Link to Next and modify to scatter-gather DMA mode. */
+ dma_desc->CTL = (dma_desc->CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
+ dma_desc->NEXT = (uint32_t)next - (PDMA->SCATBA);
+ }
+
+ ret = RT_EOK;
+
+exit_nu_pdma_desc_setup:
+
+ return -(ret);
+}
+
+static int nu_pdma_sgtbls_token_allocate(void)
+{
+ int idx, i;
+
+ int pool_size = sizeof(nu_pdma_sgtbl_token) / sizeof(uint32_t);
+
+ for (i = 0; i < pool_size; i++)
+ {
+ if ((idx = nu_ctz(nu_pdma_sgtbl_token[i])) != 32)
+ {
+ nu_pdma_sgtbl_token[i] &= ~(1 << idx);
+ idx += i * 32;
+ return idx;
+ }
+ }
+
+ /* No available */
+ return -1;
+}
+
+static void nu_pdma_sgtbls_token_free(nu_pdma_desc_t psSgtbls)
+{
+ int idx = (int)(psSgtbls - &nu_pdma_sgtbl_arr[0]);
+ RT_ASSERT(idx >= 0);
+ RT_ASSERT((idx + 1) <= NU_PDMA_SGTBL_POOL_SIZE);
+ nu_pdma_sgtbl_token[idx / 32] |= (1 << (idx % 32));
+}
+
+rt_err_t nu_pdma_sgtbls_allocate(nu_pdma_desc_t *ppsSgtbls, int num)
+{
+ int i, j, idx;
+
+ RT_ASSERT(ppsSgtbls != NULL);
+ RT_ASSERT(num <= NU_PDMA_SG_TBL_MAXSIZE);
+
+ rt_mutex_take(g_mutex_sg, RT_WAITING_FOREVER);
+
+ for (i = 0; i < num; i++)
+ {
+ ppsSgtbls[i] = NULL;
+ /* Get token. */
+ if ((idx = nu_pdma_sgtbls_token_allocate()) < 0)
+ {
+ rt_kprintf("No available sgtbl.\n");
+ goto fail_nu_pdma_sgtbls_allocate;
+ }
+
+ ppsSgtbls[i] = (nu_pdma_desc_t)&nu_pdma_sgtbl_arr[idx];
+ }
+
+ rt_mutex_release(g_mutex_sg);
+
+ return RT_EOK;
+
+fail_nu_pdma_sgtbls_allocate:
+
+ /* Release allocated tables. */
+ for (j = 0; j < i; j++)
+ {
+ if (ppsSgtbls[j] != NULL)
+ {
+ nu_pdma_sgtbls_token_free(ppsSgtbls[j]);
+ }
+ ppsSgtbls[j] = NULL;
+ }
+
+ rt_mutex_release(g_mutex_sg);
+ return -RT_ERROR;
+}
+
+void nu_pdma_sgtbls_free(nu_pdma_desc_t *ppsSgtbls, int num)
+{
+ int i;
+
+ RT_ASSERT(ppsSgtbls != NULL);
+ RT_ASSERT(num <= NU_PDMA_SG_TBL_MAXSIZE);
+
+ rt_mutex_take(g_mutex_sg, RT_WAITING_FOREVER);
+
+ for (i = 0; i < num; i++)
+ {
+ if (ppsSgtbls[i] != NULL)
+ {
+ nu_pdma_sgtbls_token_free(ppsSgtbls[i]);
+ }
+ ppsSgtbls[i] = NULL;
+ }
+
+ rt_mutex_release(g_mutex_sg);
+}
+
+static rt_err_t nu_pdma_sgtbls_valid(nu_pdma_desc_t head)
+{
+ uint32_t node_addr;
+ nu_pdma_desc_t node = head;
+
+ do
+ {
+ node_addr = (uint32_t)node;
+ if ((node_addr < PDMA->SCATBA) || (node_addr - PDMA->SCATBA) >= NU_PDMA_SG_LIMITED_DISTANCE)
+ {
+ rt_kprintf("The distance is over %d between 0x%08x and 0x%08x. \n", NU_PDMA_SG_LIMITED_DISTANCE, PDMA->SCATBA, node);
+ rt_kprintf("Please use nu_pdma_sgtbl_allocate to allocate valid sg-table.\n");
+ return RT_ERROR;
+ }
+
+ node = (nu_pdma_desc_t)(node->NEXT + PDMA->SCATBA);
+
+ } while (((uint32_t)node != PDMA->SCATBA) && (node != head));
+
+ return RT_EOK;
+}
+
+static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us)
+{
+ PDMA_DisableTimeout(PDMA, 1 << i32ChannID);
+
+ PDMA_EnableInt(PDMA, i32ChannID, PDMA_INT_TRANS_DONE);
+
+ nu_pdma_timeout_set(i32ChannID, u32IdleTimeout_us);
+
+ /* Set scatter-gather mode and head */
+ PDMA_SetTransferMode(PDMA,
+ i32ChannID,
+ u32Peripheral,
+ (head != NULL) ? 1 : 0,
+ (uint32_t)head);
+
+ /* If peripheral is M2M, trigger it. */
+ if (u32Peripheral == PDMA_MEM)
+ PDMA_Trigger(PDMA, i32ChannID);
+}
+
+rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t i32TransferCnt, uint32_t u32IdleTimeout_us)
+{
+ rt_err_t ret = RT_EINVAL;
+
+ nu_pdma_periph_ctl_t *psPeriphCtl = NULL;
+
+ if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+ goto exit_nu_pdma_transfer;
+
+ psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl;
+
+ ret = nu_pdma_desc_setup(i32ChannID,
+ &PDMA->DSCT[i32ChannID],
+ u32DataWidth,
+ u32AddrSrc,
+ u32AddrDst,
+ i32TransferCnt,
+ NULL);
+ if (ret != RT_EOK)
+ goto exit_nu_pdma_transfer;
+
+ _nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, NULL, u32IdleTimeout_us);
+
+ ret = RT_EOK;
+
+exit_nu_pdma_transfer:
+
+ return -(ret);
+}
+
+rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us)
+{
+ rt_err_t ret = RT_EINVAL;
+ nu_pdma_periph_ctl_t *psPeriphCtl = NULL;
+
+ if (!head)
+ goto exit_nu_pdma_sg_transfer;
+ else if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+ goto exit_nu_pdma_sg_transfer;
+ else if ( (ret=nu_pdma_sgtbls_valid(head)) != RT_EOK ) /* Check SG-tbls. */
+ goto exit_nu_pdma_sg_transfer;
+
+ psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl;
+
+ _nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, head, u32IdleTimeout_us);
+
+ ret = RT_EOK;
+
+exit_nu_pdma_sg_transfer:
+
+ return -(ret);
+}
+
+void PDMA_IRQHandler(void)
+{
+ int i;
+
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uint32_t intsts = PDMA_GET_INT_STATUS(PDMA);
+ uint32_t abtsts = PDMA_GET_ABORT_STS(PDMA);
+ uint32_t tdsts = PDMA_GET_TD_STS(PDMA);
+ uint32_t reqto = intsts & (PDMA_INTSTS_REQTOF0_Msk | PDMA_INTSTS_REQTOF1_Msk);
+ uint32_t reqto_ch = ((reqto & PDMA_INTSTS_REQTOF0_Msk) ? (1 << 0) : 0x0) | ((reqto & PDMA_INTSTS_REQTOF1_Msk) ? (1 << 1) : 0x0);
+
+ int allch_sts = (reqto_ch | tdsts | abtsts);
+
+ // Abort
+ if (intsts & PDMA_INTSTS_ABTIF_Msk)
+ {
+ // Clear all Abort flags
+ PDMA_CLR_ABORT_FLAG(PDMA, abtsts);
+ }
+
+ // Transfer done
+ if (intsts & PDMA_INTSTS_TDIF_Msk)
+ {
+ // Clear all transfer done flags
+ PDMA_CLR_TD_FLAG(PDMA, tdsts);
+ }
+
+ // Timeout
+ if (reqto)
+ {
+ // Clear all Timeout flags
+ PDMA->INTSTS = reqto;
+ }
+
+ // Find the position of first '1' in allch_sts.
+ while ((i = nu_ctz(allch_sts)) != 32)
+ {
+ int ch_mask = (1 << i);
+
+ if (nu_pdma_chn_mask & ch_mask)
+ {
+ int ch_event = 0;
+ nu_pdma_chn_t *dma_chn = nu_pdma_chn_arr + i - NU_PDMA_CH_Pos;
+
+ if (dma_chn->m_pfnCBHandler)
+ {
+ if (abtsts & ch_mask)
+ {
+ ch_event |= NU_PDMA_EVENT_ABORT;
+ }
+
+ if (tdsts & ch_mask) ch_event |= NU_PDMA_EVENT_TRANSFER_DONE;
+
+ if (reqto_ch & ch_mask)
+ {
+ PDMA_DisableTimeout(PDMA, ch_mask);
+ ch_event |= NU_PDMA_EVENT_TIMEOUT;
+ }
+
+ if (dma_chn->m_u32EventFilter & ch_event)
+ dma_chn->m_pfnCBHandler(dma_chn->m_pvUserData, ch_event);
+
+ if (reqto_ch & ch_mask)
+ nu_pdma_timeout_set(i, nu_pdma_chn_arr[i - NU_PDMA_CH_Pos].m_u32IdleTimeout_us);
+
+ }//if(dma_chn->handler)
+ } //if (nu_pdma_chn_mask & ch_mask)
+
+ // Clear the served bit.
+ allch_sts &= ~ch_mask;
+
+ } //while
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+static void nu_pdma_memfun_actor_init(void)
+{
+ int i = 0 ;
+ nu_pdma_init();
+ for (i = 0; i < NU_PDMA_MEMFUN_ACTOR_MAX; i++)
+ {
+ rt_memset(&nu_pdma_memfun_actor_arr[i], 0, sizeof(struct nu_pdma_memfun_actor));
+ if (-(RT_ERROR) != (nu_pdma_memfun_actor_arr[i].m_i32ChannID = nu_pdma_channel_allocate(PDMA_MEM)))
+ {
+ nu_pdma_memfun_actor_arr[i].m_psSemMemFun = rt_sem_create("memactor_sem", 0, RT_IPC_FLAG_FIFO);
+ }
+ else
+ break;
+ }
+ if (i)
+ {
+ nu_pdma_memfun_actor_maxnum = i;
+ nu_pdma_memfun_actor_mask = ~(((1 << i) - 1));
+ nu_pdma_memfun_actor_pool_sem = rt_sem_create("mempool_sem", nu_pdma_memfun_actor_maxnum, RT_IPC_FLAG_FIFO);
+ nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_FIFO);
+ }
+}
+
+static void nu_pdma_memfun_cb(void *pvUserData, uint32_t u32Events)
+{
+ nu_pdma_memfun_actor_t psMemFunActor = (nu_pdma_memfun_actor_t)pvUserData;
+ psMemFunActor->m_u32Result = u32Events;
+ rt_sem_release(psMemFunActor->m_psSemMemFun);
+}
+
+static int nu_pdma_memfun_employ(void)
+{
+ int idx = -1 ;
+
+ /* Headhunter */
+ if (nu_pdma_memfun_actor_pool_sem && (rt_sem_take(nu_pdma_memfun_actor_pool_sem, RT_WAITING_FOREVER) == RT_EOK))
+ {
+ rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER);
+ /* Find the position of first '0' in nu_pdma_memfun_actor_mask. */
+ idx = nu_cto(nu_pdma_memfun_actor_mask);
+ if (idx != 32)
+ {
+ nu_pdma_memfun_actor_mask |= (1 << idx);
+ }
+ else
+ {
+ idx = -1;
+ }
+ rt_mutex_release(nu_pdma_memfun_actor_pool_lock);
+ }
+
+ return idx;
+}
+
+static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int count, nu_pdma_memctrl_t eMemCtl)
+{
+ nu_pdma_memfun_actor_t psMemFunActor = NULL;
+ int idx;
+ rt_size_t ret = 0;
+ while (1)
+ {
+ /* Employ actor */
+ if ((idx = nu_pdma_memfun_employ()) < 0)
+ continue;
+
+ psMemFunActor = &nu_pdma_memfun_actor_arr[idx];
+
+ psMemFunActor->m_u32TrigTransferCnt = count;
+
+ /* Set PDMA memory control to eMemCtl. */
+ nu_pdma_channel_memctrl_set(psMemFunActor->m_i32ChannID, eMemCtl);
+
+ /* Register ISR callback function */
+ nu_pdma_callback_register(psMemFunActor->m_i32ChannID, nu_pdma_memfun_cb, (void *)psMemFunActor, NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE);
+
+ psMemFunActor->m_u32Result = 0;
+
+ /* Trigger it */
+ nu_pdma_transfer(psMemFunActor->m_i32ChannID, u32DataWidth, (uint32_t)src, (uint32_t)dest, count, 0);
+
+ /* Wait it done. */
+ rt_sem_take(psMemFunActor->m_psSemMemFun, RT_WAITING_FOREVER);
+
+ /* Give result if get NU_PDMA_EVENT_TRANSFER_DONE.*/
+ if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_TRANSFER_DONE)
+ {
+ ret = psMemFunActor->m_u32TrigTransferCnt;
+ }
+ else
+ {
+ ret = psMemFunActor->m_u32TrigTransferCnt - nu_pdma_non_transfer_count_get(psMemFunActor->m_i32ChannID);
+ }
+
+ /* Terminate it if get ABORT event */
+ if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_ABORT)
+ {
+ nu_pdma_channel_terminate(psMemFunActor->m_i32ChannID);
+ }
+
+ rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER);
+ nu_pdma_memfun_actor_mask &= ~(1 << idx);
+ rt_mutex_release(nu_pdma_memfun_actor_pool_lock);
+
+ /* Fire actor */
+ rt_sem_release(nu_pdma_memfun_actor_pool_sem);
+
+ break;
+ }
+
+ return ret;
+}
+
+rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned int transfer_count)
+{
+ if (data_width == 8 || data_width == 16 || data_width == 32)
+ return nu_pdma_memfun(dest, src, data_width, transfer_count, eMemCtl_SrcInc_DstFix);
+ return 0;
+}
+
+void *nu_pdma_memcpy(void *dest, void *src, unsigned int count)
+{
+ if (count == nu_pdma_memfun(dest, src, 8, count, eMemCtl_SrcInc_DstInc))
+ return dest;
+ else
+ return NULL;
+}
+
+/**
+ * PDMA memfun actor initialization
+ */
+int rt_hw_pdma_memfun_init(void)
+{
+ nu_pdma_memfun_actor_init();
+ return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_pdma_memfun_init);
+#endif // #if defined(BSP_USING_PDMA)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h
new file mode 100644
index 00000000000..e379323633e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h
@@ -0,0 +1,71 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-7 Wayne First version
+*
+******************************************************************************/
+
+#ifndef __DRV_PDMA_H__
+#define __DRV_PDMA_H__
+
+#include
+#include
+#include
+
+#ifndef NU_PDMA_SGTBL_POOL_SIZE
+ #define NU_PDMA_SGTBL_POOL_SIZE (16)
+#endif
+
+#define NU_PDMA_CAP_NONE (0 << 0)
+
+#define NU_PDMA_EVENT_ABORT (1 << 0)
+#define NU_PDMA_EVENT_TRANSFER_DONE (1 << 1)
+#define NU_PDMA_EVENT_TIMEOUT (1 << 2)
+#define NU_PDMA_EVENT_ALL (NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT)
+#define NU_PDMA_EVENT_MASK NU_PDMA_EVENT_ALL
+#define NU_PDMA_UNUSED (-1)
+
+#define NU_PDMA_SG_LIMITED_DISTANCE ((PDMA_DSCT_NEXT_NEXT_Msk>>PDMA_DSCT_NEXT_NEXT_Pos)+1)
+
+typedef enum
+{
+ eMemCtl_SrcFix_DstFix,
+ eMemCtl_SrcFix_DstInc,
+ eMemCtl_SrcInc_DstFix,
+ eMemCtl_SrcInc_DstInc,
+ eMemCtl_Undefined = (-1)
+} nu_pdma_memctrl_t;
+
+typedef DSCT_T *nu_pdma_desc_t;
+
+typedef void (*nu_pdma_cb_handler_t)(void *, uint32_t);
+
+int nu_pdma_channel_allocate(int32_t i32PeripType);
+rt_err_t nu_pdma_channel_free(int i32ChannID);
+rt_err_t nu_pdma_callback_register(int i32ChannID, nu_pdma_cb_handler_t pfnHandler, void *pvUserData, uint32_t u32EventFilter);
+rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t i32TransferCnt, uint32_t u32IdleTimeout_us);
+int nu_pdma_transferred_byte_get(int32_t i32ChannID, int32_t i32TriggerByteLen);
+void nu_pdma_channel_terminate(int i32ChannID);
+nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID);
+rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl);
+
+nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cb_handler_t *ppfnHandler_Hijack,
+ void **ppvUserData_Hijack, uint32_t *pu32EventFilter_Hijack);
+
+// For scatter-gather DMA
+rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t TransferCnt, nu_pdma_desc_t next);
+rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us);
+rt_err_t nu_pdma_sgtbls_allocate(nu_pdma_desc_t *ppsSgtbls, int num);
+void nu_pdma_sgtbls_free(nu_pdma_desc_t *ppsSgtbls, int num);
+
+
+// For memory actor
+void *nu_pdma_memcpy(void *dest, void *src, unsigned int count);
+rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned int transfer_count);
+
+#endif // __DRV_PDMA_H___
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.c
new file mode 100644
index 00000000000..3be7e62b31e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.c
@@ -0,0 +1,305 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-4-20 FYChou First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_QEI)
+#include
+#include "NuMicro.h"
+
+/* Private define ---------------------------------------------------------------*/
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_qei
+{
+ struct rt_pulse_encoder_device dev;
+ char *name;
+ QEI_T *qei_base;
+ rt_uint32_t max_cntval;
+ rt_uint32_t cmp_val;
+ IRQn_Type IRQn;
+ rt_uint8_t qei_type;
+ rt_uint8_t qei_flag;
+};
+typedef struct nu_qei *nu_qei_t;
+
+
+/* Private functions ------------------------------------------------------------*/
+static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder);
+static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder);
+static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder);
+static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder);
+static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args);
+
+/* Public functions -------------------------------------------------------------*/
+rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder);
+rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder);
+rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder);
+void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type);
+void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val);
+
+/* Private variables ------------------------------------------------------------*/
+static struct nu_qei nu_qei_arr [] =
+{
+#if defined(BSP_USING_QEI0)
+ {
+ .name = "qei0",
+ .qei_base = QEI0,
+ .max_cntval = 1000,
+ .cmp_val = 100,
+ .IRQn = QEI0_IRQn,
+ .qei_type = AB_PHASE_PULSE_ENCODER,
+ .qei_flag = 0
+ },
+#endif
+
+#if defined(BSP_USING_QEI1)
+ {
+ .name = "qei1",
+ .qei_base = QEI1,
+ .max_cntval = 1000,
+ .cmp_val = 100,
+ .IRQn = QEI1_IRQn,
+ .qei_type = AB_PHASE_PULSE_ENCODER,
+ .qei_flag = 0
+ },
+#endif
+
+ {0}
+};
+
+static const struct rt_pulse_encoder_ops nu_qei_ops =
+{
+ .init = nu_qei_init,
+ .get_count = nu_qei_get_count,
+ .clear_count = nu_qei_clear_count,
+ .control = nu_qei_control,
+};
+typedef struct rt_pulse_encoder_ops *nu_qei_ops_t;
+
+/* Public variables -------------------------------------------------------------*/
+
+
+static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder)
+{
+ rt_uint32_t u32type;
+ switch (pulse_encoder->type)
+ {
+ case SINGLE_PHASE_PULSE_ENCODER:
+ u32type = (((nu_qei_t)pulse_encoder)->cmp_val) ? QEI_CTL_X2_COMPARE_COUNTING_MODE : QEI_CTL_X2_FREE_COUNTING_MODE;
+ break;
+
+ case UNKNOWN_PULSE_ENCODER_TYPE:
+ case AB_PHASE_PULSE_ENCODER:
+ default:
+ u32type = (((nu_qei_t)pulse_encoder)->cmp_val) ? QEI_CTL_X4_COMPARE_COUNTING_MODE : QEI_CTL_X4_FREE_COUNTING_MODE;
+ break;
+ }
+
+ return u32type;
+}
+
+static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder)
+{
+ rt_uint32_t u32type;
+ QEI_T *qui_base;
+
+ RT_ASSERT(pulse_encoder != RT_NULL);
+ qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
+
+ /* enable noise filter */
+ QEI_ENABLE_NOISE_FILTER(qui_base, QEI_CTL_NFCLKSEL_DIV2);
+
+ /* set qei mode */
+ u32type = nu_qei_type(pulse_encoder);
+
+ /* set compare value and interrupt */
+ if (((nu_qei_t)pulse_encoder)->cmp_val)
+ {
+ QEI_SET_CNT_CMP(qui_base, ((nu_qei_t)pulse_encoder)->cmp_val);
+ QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk);
+ QEI_ENABLE_CNT_CMP(qui_base);
+ NVIC_EnableIRQ(((nu_qei_t)pulse_encoder)->IRQn);
+ }
+ QEI_Open(qui_base, u32type, ((nu_qei_t)pulse_encoder)->max_cntval);
+
+
+ return RT_EOK;
+}
+
+static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder)
+{
+ QEI_T *qui_base;
+ RT_ASSERT(pulse_encoder != RT_NULL);
+ qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
+ return (rt_int32_t)QEI_GET_CNT_VALUE(qui_base);
+}
+
+
+static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
+{
+ QEI_T *qui_base;
+ RT_ASSERT(pulse_encoder != RT_NULL);
+ qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
+ QEI_Stop(qui_base);
+ QEI_SET_CNT_VALUE(qui_base, 0);
+ QEI_Start(qui_base);
+ return RT_EOK;
+}
+
+static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
+{
+ rt_err_t result;
+ QEI_T *qui_base;
+
+ RT_ASSERT(pulse_encoder != RT_NULL);
+ qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
+
+ RT_ASSERT(cmd != RT_NULL);
+
+ result = RT_EOK;
+
+ switch (cmd)
+ {
+ case PULSE_ENCODER_CMD_ENABLE:
+ QEI_Start(qui_base);
+ if (((nu_qei_t)pulse_encoder)->cmp_val)
+ {
+ QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk);
+ QEI_ENABLE_CNT_CMP(qui_base);
+ NVIC_EnableIRQ(((nu_qei_t)pulse_encoder)->IRQn);
+ }
+ break;
+ case PULSE_ENCODER_CMD_DISABLE:
+ if (((nu_qei_t)pulse_encoder)->cmp_val)
+ {
+ QEI_DisableInt(qui_base, QEI_CTL_CMPIEN_Msk);
+ QEI_DISABLE_CNT_CMP(qui_base);
+ NVIC_DisableIRQ(((nu_qei_t)pulse_encoder)->IRQn);
+ }
+ QEI_Stop(qui_base);
+ break;
+ default:
+ result = -RT_ENOSYS;
+ break;
+ }
+
+ return result;
+}
+
+#if defined(BSP_USING_QEI0)
+/* QEI0 interrupt entry */
+void QEI0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ if (QEI_GET_INT_FLAG(nu_qei_arr[0].qei_base, QEI_STATUS_CMPF_Msk))
+ {
+ nu_qei_arr[0].qei_flag = 1;
+ QEI_CLR_INT_FLAG(nu_qei_arr[0].qei_base, QEI_STATUS_CMPF_Msk);
+ rt_kprintf("QEI0 CMP flag rising\n") ;
+ }
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_QEI1)
+/* QEI1 interrupt entry */
+void QEI1_IRQHandler(void)
+{
+
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ if (QEI_GET_INT_FLAG(nu_qei_arr[1].qei_base, QEI_STATUS_CMPF_Msk))
+ {
+ nu_qei_arr[1].qei_flag = 1;
+ QEI_CLR_INT_FLAG(nu_qei_arr[1].qei_base, QEI_STATUS_CMPF_Msk);
+ rt_kprintf("QEI1 CMP flag rising\n") ;
+ }
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder)
+{
+ return ((nu_qei_t) * pulse_encoder)->max_cntval;
+}
+
+rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder)
+{
+ return ((nu_qei_t) * pulse_encoder)->cmp_val;
+}
+
+rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder)
+{
+ return ((nu_qei_t) * pulse_encoder)->qei_type;
+}
+
+void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type)
+{
+ QEI_T *qui_base;
+ RT_ASSERT(pulse_encoder != RT_NULL);
+ qui_base = ((nu_qei_t) * pulse_encoder)->qei_base;
+
+ RT_ASSERT(u8type <= AB_PHASE_PULSE_ENCODER);
+ ((nu_qei_t)*pulse_encoder)->qei_type = u8type;
+ ((nu_qei_t)*pulse_encoder)->dev.type = (enum rt_pulse_encoder_type)u8type;
+ ((nu_qei_t)*pulse_encoder)->max_cntval = u32val;
+ QEI_Open(qui_base, nu_qei_type(&(((nu_qei_t)*pulse_encoder)->dev)), u32val);
+}
+
+void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val)
+{
+ QEI_T *qui_base;
+ RT_ASSERT(pulse_encoder != RT_NULL);
+ qui_base = ((nu_qei_t) * pulse_encoder)->qei_base;
+
+ ((nu_qei_t)*pulse_encoder)->cmp_val = u32val;
+ QEI_SET_CNT_CMP(qui_base, ((nu_qei_t)*pulse_encoder)->cmp_val);
+
+ if (((nu_qei_t)*pulse_encoder)->cmp_val)
+ {
+ QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk);
+ QEI_ENABLE_CNT_CMP(qui_base);
+ NVIC_EnableIRQ(((nu_qei_t)*pulse_encoder)->IRQn);
+ }
+ else
+ {
+ QEI_DisableInt(qui_base, QEI_CTL_CMPIEN_Msk);
+ QEI_DISABLE_CNT_CMP(qui_base);
+ NVIC_DisableIRQ(((nu_qei_t)*pulse_encoder)->IRQn);
+ }
+}
+
+
+int rt_hw_qei_init(void)
+{
+ int result = RT_ERROR;
+ int nu_sel = 0;
+ while (nu_qei_arr[nu_sel].name != 0)
+ {
+ nu_qei_arr[nu_sel].dev.type = (enum rt_pulse_encoder_type)nu_qei_arr[nu_sel].qei_type;
+ nu_qei_arr[nu_sel].dev.ops = &nu_qei_ops;
+
+ result = rt_device_pulse_encoder_register((void *)&nu_qei_arr[nu_sel], nu_qei_arr[nu_sel].name, &(nu_qei_arr[nu_sel].qei_flag));
+ RT_ASSERT(result == RT_EOK);
+ nu_sel++;
+ }
+ return result;
+}
+INIT_APP_EXPORT(rt_hw_qei_init);
+
+#endif /* BSP_USING_QEI */
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.h
new file mode 100644
index 00000000000..ae8f5a65eb4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.h
@@ -0,0 +1,30 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-4-20 FYChou First version
+*
+* Tips:
+* QEI compare interrupt flag *(pulse_encoder->user_data): If compare value is
+* not null, after execute device init, compare interrupt will be enabled automatic.
+* When the interrupt occur, interrupt flag will be set 1.
+*
+******************************************************************************/
+
+#ifndef __DRV_QEI_H__
+#define __DRV_QEI_H__
+
+#include
+
+rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder);
+rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder);
+rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder);
+void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type);
+void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val);
+
+
+#endif // __DRV_QEI_H___
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c
new file mode 100644
index 00000000000..a39e0716392
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c
@@ -0,0 +1,407 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-5-19 YHKuo First version
+*
+******************************************************************************/
+#include
+
+#if defined(BSP_USING_QSPI)
+#include
+#include
+
+#include
+
+/* Private define ---------------------------------------------------------------*/
+enum
+{
+ QSPI_START = -1,
+#if defined(BSP_USING_QSPI0)
+ QSPI0_IDX,
+#endif
+#if defined(BSP_USING_QSPI1)
+ QSPI1_IDX,
+#endif
+ QSPI_CNT
+};
+
+/* Private typedef --------------------------------------------------------------*/
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
+static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message);
+static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name);
+
+/* Public functions -------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_spi_ops nu_qspi_poll_ops =
+{
+ .configure = nu_qspi_bus_configure,
+ .xfer = nu_qspi_bus_xfer,
+};
+
+static struct nu_spi nu_qspi_arr [] =
+{
+#if defined(BSP_USING_QSPI0)
+ {
+ .name = "qspi0",
+ .spi_base = (SPI_T *)QSPI0,
+
+#if defined(BSP_USING_QSPI_PDMA)
+#if defined(BSP_USING_QSPI0_PDMA)
+ .pdma_perp_tx = PDMA_QSPI0_TX,
+ .pdma_perp_rx = PDMA_QSPI0_RX,
+#else
+ .pdma_perp_tx = NU_PDMA_UNUSED,
+ .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+ },
+#endif
+#if defined(BSP_USING_QSPI1)
+ {
+ .name = "qspi1",
+ .spi_base = (SPI_T *)QSPI1,
+
+#if defined(BSP_USING_QSPI_PDMA)
+#if defined(BSP_USING_QSPI1_PDMA)
+ .pdma_perp_tx = PDMA_QSPI1_TX,
+ .pdma_perp_rx = PDMA_QSPI1_RX,
+#else
+ .pdma_perp_tx = NU_PDMA_UNUSED,
+ .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+ },
+#endif
+ {0}
+}; /* qspi nu_qspi */
+
+static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device,
+ struct rt_spi_configuration *configuration)
+{
+ struct nu_spi *spi_bus;
+ uint32_t u32SPIMode;
+ uint32_t u32BusClock;
+ rt_err_t ret = RT_EOK;
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(configuration != RT_NULL);
+
+ spi_bus = (struct nu_spi *) device->bus;
+
+ /* Check mode */
+ switch (configuration->mode & RT_SPI_MODE_3)
+ {
+ case RT_SPI_MODE_0:
+ u32SPIMode = SPI_MODE_0;
+ break;
+ case RT_SPI_MODE_1:
+ u32SPIMode = SPI_MODE_1;
+ break;
+ case RT_SPI_MODE_2:
+ u32SPIMode = SPI_MODE_2;
+ break;
+ case RT_SPI_MODE_3:
+ u32SPIMode = SPI_MODE_3;
+ break;
+ default:
+ ret = RT_EIO;
+ goto exit_nu_qspi_bus_configure;
+ }
+
+ /* Check data width */
+ if (!(configuration->data_width == 8 ||
+ configuration->data_width == 16 ||
+ configuration->data_width == 24 ||
+ configuration->data_width == 32))
+ {
+ ret = RT_EINVAL;
+ goto exit_nu_qspi_bus_configure;
+ }
+
+ /* Try to set clock and get actual spi bus clock */
+ u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz);
+ if (configuration->max_hz > u32BusClock)
+ {
+ rt_kprintf("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz);
+ configuration->max_hz = u32BusClock;
+ }
+
+ /* Need to initialize new configuration? */
+ if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(struct rt_spi_configuration)) != 0)
+ {
+ rt_memcpy(&spi_bus->configuration, configuration, sizeof(struct rt_spi_configuration));
+
+ QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock);
+
+ if (configuration->mode & RT_SPI_CS_HIGH)
+ {
+ /* Set CS pin to LOW */
+ SPI_SET_SS_LOW(spi_bus->spi_base);
+ }
+ else
+ {
+ /* Set CS pin to HIGH */
+ SPI_SET_SS_HIGH(spi_bus->spi_base);
+ }
+
+ if (configuration->mode & RT_SPI_MSB)
+ {
+ /* Set sequence to MSB first */
+ SPI_SET_MSB_FIRST(spi_bus->spi_base);
+ }
+ else
+ {
+ /* Set sequence to LSB first */
+ SPI_SET_LSB_FIRST(spi_bus->spi_base);
+ }
+ }
+
+ /* Clear SPI RX FIFO */
+ nu_spi_drain_rxfifo(spi_bus->spi_base);
+
+exit_nu_qspi_bus_configure:
+
+ return -(ret);
+}
+
+#if defined(RT_SFUD_USING_QSPI)
+static int nu_qspi_mode_config(struct nu_spi *qspi_bus, uint8_t *tx, uint8_t *rx, int qspi_lines)
+{
+ QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base;
+ if (qspi_lines > 1)
+ {
+ if (tx)
+ {
+ switch (qspi_lines)
+ {
+ case 2:
+ QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi_base);
+ break;
+ case 4:
+ QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi_base);
+ break;
+ }
+ }
+ else
+ {
+ switch (qspi_lines)
+ {
+ case 2:
+ QSPI_ENABLE_DUAL_INPUT_MODE(qspi_base);
+ break;
+ case 4:
+ QSPI_ENABLE_QUAD_INPUT_MODE(qspi_base);
+ break;
+ }
+ }
+ }
+ else
+ {
+ QSPI_DISABLE_DUAL_MODE(qspi_base);
+ QSPI_DISABLE_QUAD_MODE(qspi_base);
+ }
+ return qspi_lines;
+}
+#endif
+
+static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+ struct nu_spi *qspi_bus;
+ struct rt_qspi_configuration *qspi_configuration;
+#if defined(RT_SFUD_USING_QSPI)
+ struct rt_qspi_message *qspi_message;
+ int last = 1;
+#endif
+ uint8_t bytes_per_word;
+ QSPI_T *qspi_base;
+ int len = 0;
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(message != RT_NULL);
+
+ qspi_bus = (struct nu_spi *) device->bus;
+ qspi_base = (QSPI_T *)qspi_bus->spi_base;
+ qspi_configuration = &qspi_bus->configuration;
+
+ bytes_per_word = qspi_configuration->parent.data_width / 8;
+
+ if (message->cs_take && !(qspi_configuration->parent.mode & RT_SPI_NO_CS))
+ {
+ if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH)
+ {
+ QSPI_SET_SS_HIGH(qspi_base);
+ }
+ else
+ {
+ QSPI_SET_SS_LOW(qspi_base);
+ }
+ }
+
+#if defined(RT_SFUD_USING_QSPI)
+ qspi_message = (struct rt_qspi_message *)message;
+
+ /* Command + Address + Dummy + Data */
+ /* Command stage */
+ if (qspi_message->instruction.content != 0)
+ {
+ last = nu_qspi_mode_config(qspi_bus, (uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines);
+ nu_spi_transfer((struct nu_spi *)qspi_bus,
+ (uint8_t *) &qspi_message->instruction.content,
+ RT_NULL,
+ 1,
+ 1);
+ }
+
+ /* Address stage */
+ if (qspi_message->address.size != 0)
+ {
+ uint32_t u32ReversedAddr = 0;
+ uint32_t u32AddrNumOfByte = qspi_message->address.size / 8;
+ switch (u32AddrNumOfByte)
+ {
+ case 1:
+ u32ReversedAddr = (qspi_message->address.content & 0xff);
+ break;
+ case 2:
+ nu_set16_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content);
+ break;
+ case 3:
+ nu_set24_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content);
+ break;
+ case 4:
+ nu_set32_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content);
+ break;
+ default:
+ RT_ASSERT(0);
+ break;
+ }
+ last = nu_qspi_mode_config(qspi_bus, (uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines);
+ nu_spi_transfer((struct nu_spi *)qspi_bus,
+ (uint8_t *) &u32ReversedAddr,
+ RT_NULL,
+ u32AddrNumOfByte,
+ 1);
+ }
+
+ /* Dummy_cycles stage */
+ if (qspi_message->dummy_cycles != 0)
+ {
+ qspi_bus->dummy = 0xff;
+
+ last = nu_qspi_mode_config(qspi_bus, (uint8_t *) &qspi_bus->dummy, RT_NULL, last);
+ nu_spi_transfer((struct nu_spi *)qspi_bus,
+ (uint8_t *) &qspi_bus->dummy,
+ RT_NULL,
+ qspi_message->dummy_cycles / (8 / last),
+ 1);
+ }
+
+ /* Data stage */
+ nu_qspi_mode_config(qspi_bus, (uint8_t *) message->send_buf, (uint8_t *) message->recv_buf, qspi_message->qspi_data_lines);
+#endif //#if defined(RT_SFUD_USING_QSPI)
+
+ if (message->length != 0)
+ {
+ nu_spi_transfer((struct nu_spi *)qspi_bus,
+ (uint8_t *) message->send_buf,
+ (uint8_t *) message->recv_buf,
+ message->length,
+ bytes_per_word);
+ len = message->length;
+ }
+ else
+ {
+ len = 1;
+ }
+
+ if (message->cs_release && !(qspi_configuration->parent.mode & RT_SPI_NO_CS))
+ {
+ if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH)
+ {
+ QSPI_SET_SS_LOW(qspi_base);
+ }
+ else
+ {
+ QSPI_SET_SS_HIGH(qspi_base);
+ }
+ }
+
+ return len;
+}
+
+static int nu_qspi_register_bus(struct nu_spi *qspi_device, const char *name)
+{
+ return rt_qspi_bus_register(&qspi_device->dev, name, &nu_qspi_poll_ops);
+}
+
+/**
+ * Hardware SPI Initial
+ */
+static int rt_hw_qspi_init(void)
+{
+ int i;
+
+ for (i = (QSPI_START + 1); i < QSPI_CNT; i++)
+ {
+ nu_qspi_register_bus(&nu_qspi_arr[i], nu_qspi_arr[i].name);
+#if defined(BSP_USING_QSPI_PDMA)
+ nu_qspi_arr[i].pdma_chanid_tx = -1;
+ nu_qspi_arr[i].pdma_chanid_rx = -1;
+ if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
+ {
+ if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK)
+ {
+ rt_kprintf("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_qspi_arr[i].name);
+ }
+ }
+#endif
+ }
+
+ return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_qspi_init);
+
+rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
+{
+ struct rt_qspi_device *qspi_device = RT_NULL;
+ rt_err_t result = RT_EOK;
+
+ RT_ASSERT(bus_name != RT_NULL);
+ RT_ASSERT(device_name != RT_NULL);
+ RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
+
+ qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
+ if (qspi_device == RT_NULL)
+ {
+ rt_kprintf("no memory, qspi bus attach device failed!\n");
+ result = -RT_ENOMEM;
+ goto __exit;
+ }
+
+ qspi_device->enter_qspi_mode = enter_qspi_mode;
+ qspi_device->exit_qspi_mode = exit_qspi_mode;
+ qspi_device->config.qspi_dl_width = data_line_width;
+
+ result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, RT_NULL);
+
+__exit:
+ if (result != RT_EOK)
+ {
+ if (qspi_device)
+ {
+ rt_free(qspi_device);
+ }
+ }
+
+ return result;
+}
+
+#endif //#if defined(BSP_USING_QSPI)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.h
new file mode 100644
index 00000000000..87be3e6e421
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.h
@@ -0,0 +1,20 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-7 Wayne First version
+*
+******************************************************************************/
+
+#ifndef __DRV_QSPI_H__
+#define __DRV_QSPI_H__
+
+#include
+
+rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)());
+
+#endif // __DRV_QSPI_H___
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c
new file mode 100644
index 00000000000..361ee87755f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c
@@ -0,0 +1,353 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-02-10 klcheng First version
+*
+******************************************************************************/
+#include
+
+#if defined (BSP_USING_RTC)
+
+#include
+#include
+
+/* Private define ---------------------------------------------------------------*/
+
+/* convert the real year and month value to the format of struct tm. */
+#define CONV_TO_TM_YEAR(year) ((year) - 1900)
+#define CONV_TO_TM_MON(mon) ((mon) - 1)
+
+/* convert the tm_year and tm_mon from struct tm to the real value. */
+#define CONV_FROM_TM_YEAR(tm_year) ((tm_year) + 1900)
+#define CONV_FROM_TM_MON(tm_mon) ((tm_mon) + 1)
+
+/* rtc date upper bound reaches the year of 2099. */
+#define RTC_TM_UPPER_BOUND \
+{ .tm_year = CONV_TO_TM_YEAR(2099), \
+ .tm_mon = CONV_TO_TM_MON(12), \
+ .tm_mday = 31, \
+ .tm_hour = 23, \
+ .tm_min = 59, \
+ .tm_sec = 59, \
+}
+
+/* rtc date lower bound reaches the year of 2000. */
+#define RTC_TM_LOWER_BOUND \
+{ .tm_year = CONV_TO_TM_YEAR(2000), \
+ .tm_mon = CONV_TO_TM_MON(1), \
+ .tm_mday = 1, \
+ .tm_hour = 0, \
+ .tm_min = 0, \
+ .tm_sec = 0, \
+}
+
+/* Private typedef --------------------------------------------------------------*/
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args);
+
+#if defined (NU_RTC_SUPPORT_IO_RW)
+static rt_size_t nu_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size);
+static rt_size_t nu_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size);
+#endif
+
+static rt_err_t nu_rtc_is_date_valid(const time_t *const t);
+static void nu_rtc_init(void);
+
+#if defined(RT_USING_ALARM)
+static void nu_rtc_alarm_reset(void);
+#endif
+
+/* Public functions -------------------------------------------------------------*/
+#if defined (NU_RTC_SUPPORT_MSH_CMD)
+extern rt_err_t set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day);
+extern rt_err_t set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second);
+#endif
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_device device_rtc;
+
+
+static void nu_rtc_init(void)
+{
+ /* hw rtc initialise */
+ RTC_Open(NULL);
+ RTC_DisableInt(RTC_INTEN_ALMIEN_Msk | RTC_INTEN_TICKIEN_Msk | RTC_INTEN_TAMP0IEN_Msk |
+ RTC_INTEN_TAMP1IEN_Msk | RTC_INTEN_TAMP2IEN_Msk | RTC_INTEN_TAMP3IEN_Msk |
+ RTC_INTEN_TAMP4IEN_Msk | RTC_INTEN_TAMP5IEN_Msk);
+
+#if defined(RT_USING_ALARM)
+
+ nu_rtc_alarm_reset();
+ RTC_EnableInt(RTC_INTEN_ALMIEN_Msk);
+ NVIC_EnableIRQ(RTC_IRQn);
+#endif
+}
+
+
+#if defined(RT_USING_ALARM)
+/* Reset alarm settings to avoid the unwanted values remain in rtc registers. */
+static void nu_rtc_alarm_reset(void)
+{
+ S_RTC_TIME_DATA_T alarm;
+
+ /* Reset alarm time and calendar. */
+ alarm.u32Year = RTC_YEAR2000;
+ alarm.u32Month = 0;
+ alarm.u32Day = 0;
+ alarm.u32Hour = 0;
+ alarm.u32Minute = 0;
+ alarm.u32Second = 0;
+ alarm.u32TimeScale = RTC_CLOCK_24;
+
+ RTC_SetAlarmDateAndTime(&alarm);
+
+ /* Reset alarm time mask and calendar mask. */
+ RTC_SetAlarmDateMask(0, 0, 0, 0, 0, 0);
+ RTC_SetAlarmTimeMask(0, 0, 0, 0, 0, 0);
+
+ /* Clear alarm flag for safe */
+ RTC_CLEAR_ALARM_INT_FLAG();
+}
+#endif
+
+
+/* rtc device driver initialise. */
+int rt_hw_rtc_init(void)
+{
+ rt_err_t ret;
+
+ nu_rtc_init();
+
+ /* register rtc device IO operations */
+ device_rtc.type = RT_Device_Class_RTC;
+ device_rtc.init = NULL;
+ device_rtc.open = NULL;
+ device_rtc.close = NULL;
+ device_rtc.control = nu_rtc_control;
+
+#if defined (NU_RTC_SUPPORT_IO_RW)
+ device_rtc.read = nu_rtc_read;
+ device_rtc.write = nu_rtc_write;
+#else
+ device_rtc.read = NULL;
+ device_rtc.write = NULL;
+#endif
+
+ device_rtc.user_data = RT_NULL;
+ device_rtc.rx_indicate = RT_NULL;
+ device_rtc.tx_complete = RT_NULL;
+
+ ret = rt_device_register(&device_rtc, "rtc", RT_DEVICE_FLAG_RDWR);
+
+ return (int)ret;
+}
+INIT_BOARD_EXPORT(rt_hw_rtc_init);
+
+
+#if defined (NU_RTC_SUPPORT_IO_RW)
+/* Register rt-thread device.read() entry. */
+static rt_size_t nu_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+ (void) pos;
+ nu_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer);
+
+ return size;
+}
+#endif
+
+
+#if defined (NU_RTC_SUPPORT_IO_RW)
+/* Register rt-thread device.write() entry. */
+static rt_size_t nu_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+ (void) pos;
+ nu_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer);
+
+ return size;
+}
+#endif
+
+
+static rt_err_t nu_rtc_is_date_valid(const time_t *const t)
+{
+ static struct tm tm_upper = RTC_TM_UPPER_BOUND;
+ static struct tm tm_lower = RTC_TM_LOWER_BOUND;
+ static time_t t_upper, t_lower;
+ static rt_bool_t initialised = RT_FALSE;
+
+ if (!initialised)
+ {
+ t_upper = mktime((struct tm *)&tm_upper);
+ t_lower = mktime((struct tm *)&tm_lower);
+ initialised = RT_TRUE;
+ }
+
+ /* check the date is supported by rtc. */
+ if ((*t > t_upper) || (*t < t_lower))
+ return -(RT_EINVAL);
+
+ return RT_EOK;
+}
+
+
+/* Register rt-thread device.control() entry. */
+static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+ struct tm tm_out, *tm_in;
+ time_t *time;
+ S_RTC_TIME_DATA_T hw_time;
+
+#if defined(RT_USING_ALARM)
+
+ struct rt_rtc_wkalarm *wkalarm;
+ S_RTC_TIME_DATA_T hw_alarm;
+#endif
+
+ if ((dev == NULL) || (args == NULL))
+ return -(RT_EINVAL);
+
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_RTC_GET_TIME:
+
+ time = (time_t *)args;
+ RTC_GetDateAndTime(&hw_time);
+
+ tm_out.tm_year = CONV_TO_TM_YEAR(hw_time.u32Year);
+ tm_out.tm_mon = CONV_TO_TM_MON(hw_time.u32Month);
+ tm_out.tm_mday = hw_time.u32Day;
+ tm_out.tm_hour = hw_time.u32Hour;
+ tm_out.tm_min = hw_time.u32Minute;
+ tm_out.tm_sec = hw_time.u32Second;
+ *time = mktime(&tm_out);
+ break;
+
+ case RT_DEVICE_CTRL_RTC_SET_TIME:
+
+ time = (time_t *) args;
+ tm_in = localtime(time);
+
+ if (nu_rtc_is_date_valid(time) != RT_EOK)
+ return RT_ERROR;
+
+ hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year);
+ hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon);
+ hw_time.u32Day = tm_in->tm_mday;
+ hw_time.u32Hour = tm_in->tm_hour;
+ hw_time.u32Minute = tm_in->tm_min;
+ hw_time.u32Second = tm_in->tm_sec;
+ hw_time.u32TimeScale = RTC_CLOCK_24;
+ hw_time.u32AmPm = 0;
+
+ RTC_SetDateAndTime(&hw_time);
+ break;
+
+#if defined(RT_USING_ALARM)
+ case RT_DEVICE_CTRL_RTC_GET_ALARM:
+
+ wkalarm = (struct rt_rtc_wkalarm *) args;
+ RTC_GetAlarmDateAndTime(&hw_alarm);
+
+ wkalarm->tm_hour = hw_alarm.u32Hour;
+ wkalarm->tm_min = hw_alarm.u32Minute;
+ wkalarm->tm_sec = hw_alarm.u32Second;
+ break;
+
+ case RT_DEVICE_CTRL_RTC_SET_ALARM:
+
+ wkalarm = (struct rt_rtc_wkalarm *) args;
+ hw_alarm.u32Hour = wkalarm->tm_hour;
+ hw_alarm.u32Minute = wkalarm->tm_min;
+ hw_alarm.u32Second = wkalarm->tm_sec;
+
+ RTC_SetAlarmDateMask(1, 1, 1, 1, 1, 1);
+ RTC_SetAlarmDateAndTime(&hw_alarm);
+ break;
+
+ default:
+ return -(RT_EINVAL);
+#endif
+ }
+
+ return RT_EOK;
+}
+
+
+#if defined (NU_RTC_SUPPORT_MSH_CMD)
+
+/* Support "rtc_det_date" command line in msh mode */
+static rt_err_t msh_rtc_set_date(int argc, char **argv)
+{
+ rt_uint32_t index, len, arg[3];
+
+ rt_memset(arg, 0, sizeof(arg));
+ len = (argc >= 4) ? 4 : argc;
+
+ /* The date information stored in argv is represented by the following order :
+ argv[0,1,2,3] = [cmd, year, month, day] */
+ for (index = 0; index < (len - 1); index ++)
+ {
+ arg[index] = atol(argv[index + 1]);
+ }
+
+ return set_date(arg[0], arg[1], arg[2]);
+}
+MSH_CMD_EXPORT_ALIAS(msh_rtc_set_date, rtc_set_date, e.g: rtc_set_date 2020 1 20);
+#endif
+
+
+#if defined (NU_RTC_SUPPORT_MSH_CMD)
+
+/* Support "rtc_det_time" command line in msh mode */
+static rt_err_t msh_rtc_set_time(int argc, char **argv)
+{
+ rt_uint32_t index, len, arg[3];
+
+ rt_memset(arg, 0, sizeof(arg));
+ len = (argc >= 4) ? 4 : argc;
+
+ /* The time information stored in argv is represented by the following order :
+ argv[0,1,2,3] = [cmd, hour, minute, second] */
+ for (index = 0; index < (len - 1); index ++)
+ {
+ arg[index] = atol(argv[index + 1]);
+ }
+
+ return set_time(arg[0], arg[1], arg[2]);
+}
+MSH_CMD_EXPORT_ALIAS(msh_rtc_set_time, rtc_set_time, e.g: rtc_set_time 18 30 00);
+#endif
+
+
+/* rtc interrupt entry */
+void RTC_IRQHandler(void)
+{
+ rt_interrupt_enter();
+
+ if (RTC_GET_TICK_INT_FLAG())
+ {
+ RTC_CLEAR_TICK_INT_FLAG();
+ }
+
+#if defined(RT_USING_ALARM)
+
+ if (RTC_GET_ALARM_INT_FLAG())
+ {
+ RTC_CLEAR_ALARM_INT_FLAG();
+
+ /* Send an alarm event to notify rt-thread alarm service. */
+ rt_alarm_update(&device_rtc, NULL);
+ }
+#endif
+
+ rt_interrupt_leave();
+}
+
+#endif /* BSP_USING_RTC */
+
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c
new file mode 100644
index 00000000000..d15750e7768
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c
@@ -0,0 +1,381 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-5-31 Egbert First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_SCUART)
+
+#include
+#include
+#include
+
+/* Private define ---------------------------------------------------------------*/
+#define LOG_TAG "drv.scuart"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME "drv.scuart"
+#define DBG_LEVEL DBG_ERROR
+#define DBG_COLOR
+#include
+
+enum
+{
+ SCUART_START = -1,
+#if defined(BSP_USING_SCUART0)
+ SCUART0_IDX,
+#endif
+#if defined(BSP_USING_SCUART1)
+ SCUART1_IDX,
+#endif
+#if defined(BSP_USING_SCUART2)
+ SCUART2_IDX,
+#endif
+ SCUART_CNT
+};
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_scuart
+{
+ rt_serial_t dev;
+ char *name;
+ SC_T *scuart_base;
+ uint32_t scuart_rst;
+ IRQn_Type scuart_irq_n;
+
+};
+typedef struct nu_scuart *nu_scuart_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
+static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void *arg);
+static int nu_scuart_send(struct rt_serial_device *serial, char c);
+static int nu_scuart_receive(struct rt_serial_device *serial);
+static void nu_scuart_isr(nu_scuart_t serial);
+
+/* Public functions ------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+
+static const struct rt_uart_ops nu_scuart_ops =
+{
+ .configure = nu_scuart_configure,
+ .control = nu_scuart_control,
+ .putc = nu_scuart_send,
+ .getc = nu_scuart_receive,
+ .dma_transmit = RT_NULL /* not support DMA mode */
+};
+
+static const struct serial_configure nu_scuart_default_config =
+ RT_SERIAL_CONFIG_DEFAULT;
+
+static struct nu_scuart nu_scuart_arr [] =
+{
+#if defined(BSP_USING_SCUART0)
+ {
+ .name = "scuart0",
+ .scuart_base = SC0,
+ .scuart_rst = SC0_RST,
+ .scuart_irq_n = SC0_IRQn,
+ },
+#endif
+
+#if defined(BSP_USING_SCUART1)
+ {
+ .name = "scuart1",
+ .scuart_base = SC1,
+ .scuart_rst = SC1_RST,
+ .scuart_irq_n = SC1_IRQn,
+ },
+#endif
+
+#if defined(BSP_USING_SCUART2)
+ {
+ .name = "scuart2",
+ .scuart_base = SC2,
+ .scuart_rst = SC2_RST,
+ .scuart_irq_n = SC2_IRQn,
+ },
+#endif
+
+ {0}
+}; /* scuart nu_scuart */
+
+/* Interrupt Handle Funtion ----------------------------------------------------*/
+#if defined(BSP_USING_SCUART0)
+/* SCUART0 interrupt entry */
+void SC0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ nu_scuart_isr(&nu_scuart_arr[SCUART0_IDX]);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SCUART1)
+/* SCUART1 interrupt entry */
+void SC1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ nu_scuart_isr(&nu_scuart_arr[SCUART1_IDX]);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SCUART2)
+/* SCUART2 interrupt entry */
+void SC2_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ nu_scuart_isr(&nu_scuart_arr[SCUART2_IDX]);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+
+
+/**
+ * All SCUART interrupt service routine
+ */
+static void nu_scuart_isr(nu_scuart_t serial)
+{
+ /* Get base address of scuart register */
+ SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
+
+ /* Get interrupt event */
+ uint32_t u32IntSts = scuart_base->INTSTS;
+
+ /* Handle RX event */
+ if (u32IntSts & (SC_INTSTS_RDAIF_Msk | SC_INTSTS_RXTOIF_Msk))
+ {
+ rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND);
+
+ // RDA is the only interrupt enabled in this driver, this status bit
+ // automatically cleared after Rx FIFO empty. So no need to clear interrupt
+ // status here.
+ scuart_base->INTSTS = SC_INTSTS_RXTOIF_Msk;
+ }
+}
+
+/**
+ * Configurae scuart port
+ */
+static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+ rt_err_t ret = RT_EOK;
+ uint32_t scuart_word_len = 0;
+ uint32_t scuart_stop_bit = 0;
+ uint32_t scuart_parity = 0;
+
+ /* Get base address of scuart register */
+ SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
+
+ /* Check baudrate */
+ RT_ASSERT(cfg->baud_rate != 0);
+
+ /* Check word len */
+ switch (cfg->data_bits)
+ {
+ case DATA_BITS_5:
+ scuart_word_len = SCUART_CHAR_LEN_5;
+ break;
+
+ case DATA_BITS_6:
+ scuart_word_len = SCUART_CHAR_LEN_6;
+ break;
+
+ case DATA_BITS_7:
+ scuart_word_len = SCUART_CHAR_LEN_7;
+ break;
+
+ case DATA_BITS_8:
+ scuart_word_len = SCUART_CHAR_LEN_8;
+ break;
+
+ default:
+ LOG_E("Unsupported data length");
+ ret = RT_EINVAL;
+ goto exit_nu_scuart_configure;
+ }
+
+ /* Check stop bit */
+ switch (cfg->stop_bits)
+ {
+ case STOP_BITS_1:
+ scuart_stop_bit = SCUART_STOP_BIT_1;
+ break;
+
+ case STOP_BITS_2:
+ scuart_stop_bit = SCUART_STOP_BIT_2;
+ break;
+
+ default:
+ LOG_E("Unsupported stop bit");
+ ret = RT_EINVAL;
+ goto exit_nu_scuart_configure;
+ }
+
+ /* Check parity */
+ switch (cfg->parity)
+ {
+ case PARITY_NONE:
+ scuart_parity = SCUART_PARITY_NONE;
+ break;
+
+ case PARITY_ODD:
+ scuart_parity = SCUART_PARITY_ODD;
+ break;
+
+ case PARITY_EVEN:
+ scuart_parity = SCUART_PARITY_EVEN;
+ break;
+
+ default:
+ LOG_E("Unsupported parity");
+ ret = RT_EINVAL;
+ goto exit_nu_scuart_configure;
+ }
+
+ /* Reset this module */
+ SYS_ResetModule(((nu_scuart_t)serial)->scuart_rst);
+
+ /* Open SCUART and set SCUART Baudrate */
+ SCUART_Open(scuart_base, cfg->baud_rate);
+
+ /* Set line configuration. */
+ SCUART_SetLineConfig(scuart_base, 0, scuart_word_len, scuart_parity, scuart_stop_bit);
+
+ /* Enable NVIC interrupt. */
+ NVIC_EnableIRQ(((nu_scuart_t)serial)->scuart_irq_n);
+
+exit_nu_scuart_configure:
+
+ if (ret != RT_EOK)
+ SCUART_Close(scuart_base);
+
+ return -(ret);
+}
+
+/**
+ * SCUART interrupt control
+ */
+static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+ rt_err_t result = RT_EOK;
+ rt_uint32_t flag;
+ rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(arg != RT_NULL);
+
+ /* Get base address of scuart register */
+ SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
+
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_CLR_INT:
+ if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
+ {
+ flag = SC_INTEN_RDAIEN_Msk | SC_INTEN_RXTOIEN_Msk;
+ SCUART_DISABLE_INT(scuart_base, flag);
+ }
+ else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
+ {
+ LOG_E("SCUART does not support dma transmission");
+ }
+ break;
+
+ case RT_DEVICE_CTRL_SET_INT:
+ if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
+ {
+ flag = SC_INTEN_RDAIEN_Msk | SC_INTEN_RXTOIEN_Msk;
+ SCUART_ENABLE_INT(scuart_base, flag);
+ }
+ break;
+
+ }
+ return result;
+}
+
+/**
+ * SCUART put char
+ */
+static int nu_scuart_send(struct rt_serial_device *serial, char c)
+{
+ RT_ASSERT(serial != RT_NULL);
+
+ /* Get base address of scuart register */
+ SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
+
+ /* Waiting if TX-FIFO is full. */
+ while (SCUART_IS_TX_FULL(scuart_base));
+
+ /* Put char into TX-FIFO */
+ SCUART_WRITE(scuart_base, c);
+
+ return 1;
+}
+
+/**
+ * SCUART get char
+ */
+static int nu_scuart_receive(struct rt_serial_device *serial)
+{
+ RT_ASSERT(serial != RT_NULL);
+
+ /* Get base address of scuart register */
+ SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
+
+ /* Return failure if RX-FIFO is empty. */
+ if (SCUART_GET_RX_EMPTY(scuart_base))
+ {
+ return -1;
+ }
+
+ /* Get char from RX-FIFO */
+ return SCUART_READ(scuart_base);
+}
+
+/**
+ * Hardware SCUART Initialization
+ */
+static int rt_hw_scuart_init(void)
+{
+ int i;
+ rt_uint32_t flag;
+ rt_err_t ret = RT_EOK;
+
+ for (i = (SCUART_START + 1); i < SCUART_CNT; i++)
+ {
+ flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
+
+ nu_scuart_arr[i].dev.ops = &nu_scuart_ops;
+ nu_scuart_arr[i].dev.config = nu_scuart_default_config;
+
+ ret = rt_hw_serial_register(&nu_scuart_arr[i].dev, nu_scuart_arr[i].name, flag, NULL);
+ RT_ASSERT(ret == RT_EOK);
+ }
+
+ return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_scuart_init);
+#endif //#if defined(BSP_USING_SCUART)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c
new file mode 100644
index 00000000000..6c6dd768b82
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c
@@ -0,0 +1,629 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-2-7 Wayne First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_SDH)
+
+#include
+#include
+#include
+#include
+
+#if defined(RT_USING_DFS)
+ #include
+ #include
+#endif
+
+/* Private define ---------------------------------------------------------------*/
+// RT_DEV_NAME_PREFIX sdh
+
+#ifndef NU_SDH_MOUNTPOINT_ROOT
+ #define NU_SDH_MOUNTPOINT_ROOT "/mnt"
+#endif
+
+#ifndef NU_SDH_MOUNTPOINT_SDH0
+ #define NU_SDH_MOUNTPOINT_SDH0 NU_SDH_MOUNTPOINT_ROOT"/sd0"
+#endif
+
+#ifndef NU_SDH_MOUNTPOINT_SDH1
+ #define NU_SDH_MOUNTPOINT_SDH1 NU_SDH_MOUNTPOINT_ROOT"/sd1"
+#endif
+
+#if defined(NU_SDH_USING_PDMA)
+ #define NU_SDH_MEMCPY nu_pdma_memcpy
+#else
+ #define NU_SDH_MEMCPY memcpy
+#endif
+
+enum
+{
+ SDH_START = -1,
+#if defined(BSP_USING_SDH0)
+ SDH0_IDX,
+#endif
+#if defined(BSP_USING_SDH1)
+ SDH1_IDX,
+#endif
+ SDH_CNT
+};
+
+#define SDH_BLOCK_SIZE 512ul
+
+#if defined(NU_SDH_HOTPLUG)
+ #define NU_SDH_TID_STACK_SIZE 1024
+#endif
+
+#if defined(NU_SDH_HOTPLUG)
+enum
+{
+ NU_SDH_CARD_INSERTED_SD0 = (1 << 0),
+ NU_SDH_CARD_REMOVED_SD0 = (1 << 1),
+ NU_SDH_CARD_INSERTED_SD1 = (1 << 2),
+ NU_SDH_CARD_REMOVED_SD1 = (1 << 3),
+ NU_SDH_CARD_EVENT_ALL = (NU_SDH_CARD_INSERTED_SD0 | NU_SDH_CARD_REMOVED_SD0 | NU_SDH_CARD_INSERTED_SD1 | NU_SDH_CARD_REMOVED_SD1)
+};
+#endif
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_sdh
+{
+ struct rt_device dev;
+ char *name;
+#if defined(NU_SDH_HOTPLUG)
+ char *mounted_point;
+#endif
+ SDH_T *base;
+ uint32_t is_card_inserted;
+ SDH_INFO_T *info;
+ struct rt_semaphore lock;
+ uint8_t *pbuf;
+};
+typedef struct nu_sdh *nu_sdh_t;
+
+#if defined(NU_SDH_HOTPLUG)
+ static struct rt_thread sdh_tid;
+ static rt_uint8_t sdh_stack[NU_SDH_TID_STACK_SIZE];
+#endif
+
+/* Private functions ------------------------------------------------------------*/
+static void nu_sdh_isr(nu_sdh_t sdh);
+static rt_err_t nu_sdh_init(rt_device_t dev);
+static rt_err_t nu_sdh_open(rt_device_t dev, rt_uint16_t oflag);
+static rt_err_t nu_sdh_close(rt_device_t dev);
+static rt_size_t nu_sdh_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t blk_nb);
+static rt_err_t nu_sdh_control(rt_device_t dev, int cmd, void *args);
+static int rt_hw_sdh_init(void);
+
+#if defined(NU_SDH_HOTPLUG)
+ static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path);
+ static void sdh_hotplugger(void *param);
+ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh);
+ static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh);
+#endif
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+static struct nu_sdh nu_sdh_arr [] =
+{
+#if defined(BSP_USING_SDH0)
+ {
+ .name = "sdh0",
+#if defined(NU_SDH_HOTPLUG)
+ .mounted_point = NU_SDH_MOUNTPOINT_SDH0,
+#endif
+ .base = SDH0,
+ .info = &SD0,
+ },
+#endif
+#if defined(BSP_USING_SDH1)
+ {
+ .name = "sdh1",
+#if defined(NU_SDH_HOTPLUG)
+ .mounted_point = NU_SDH_MOUNTPOINT_SDH1,
+#endif
+ .base = SDH1,
+ .info = &SD1,
+ },
+#endif
+ {0}
+}; /* struct nu_sdh nu_sdh_arr [] */
+static struct rt_event sdh_event;
+
+static void nu_sdh_isr(nu_sdh_t sdh)
+{
+ SDH_T *sdh_base = sdh->base;
+ unsigned int volatile isr;
+ unsigned int volatile ier;
+ SDH_INFO_T *pSD = sdh->info;
+
+ // FMI data abort interrupt
+ if (sdh_base->GINTSTS & SDH_GINTSTS_DTAIF_Msk)
+ {
+ /* ResetAllEngine() */
+ sdh_base->GCTL |= SDH_GCTL_GCTLRST_Msk;
+ }
+
+ //----- SD interrupt status
+ isr = sdh_base->INTSTS;
+ if (isr & SDH_INTSTS_BLKDIF_Msk)
+ {
+ // block down
+ pSD->DataReadyFlag = TRUE;
+ SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_BLKDIF_Msk);
+ }
+
+ if (isr & SDH_INTSTS_CDIF_Msk) // card detect
+ {
+ /* SD interrupt status */
+ // it is work to delay 50 times for SD_CLK = 200KHz
+ {
+ int volatile i; // delay 30 fail, 50 OK
+ for (i = 0; i < 0x500; i++); // delay to make sure got updated value from REG_SDISR.
+ isr = sdh_base->INTSTS;
+ }
+
+ if (isr & SDH_INTSTS_CDSTS_Msk)
+ {
+ /* Card removed */
+#if defined(NU_SDH_HOTPLUG)
+ if (sdh->base == SDH0)
+ rt_event_send(&sdh_event, NU_SDH_CARD_REMOVED_SD0);
+ else if (sdh->base == SDH1)
+ rt_event_send(&sdh_event, NU_SDH_CARD_REMOVED_SD1);
+#endif
+ sdh->info->IsCardInsert = FALSE; // SDISR_CD_Card = 1 means card remove for GPIO mode
+ rt_memset((void *)sdh->info, 0, sizeof(SDH_INFO_T));
+ }
+ else
+ {
+ SDH_Open(sdh_base, CardDetect_From_GPIO);
+ if (!SDH_Probe(sdh_base))
+ {
+ /* Card inserted */
+#if defined(NU_SDH_HOTPLUG)
+ if (sdh->base == SDH0)
+ rt_event_send(&sdh_event, NU_SDH_CARD_INSERTED_SD0);
+ else if (sdh->base == SDH1)
+ rt_event_send(&sdh_event, NU_SDH_CARD_INSERTED_SD1);
+#endif
+ }
+ }
+ /* Clear CDIF interrupt flag */
+ SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_CDIF_Msk);
+ }
+
+ // CRC error interrupt
+ if (isr & SDH_INTSTS_CRCIF_Msk)
+ {
+ if (!(isr & SDH_INTSTS_CRC16_Msk))
+ {
+ /* CRC_16 error */
+ // handle CRC 16 error
+ }
+ else if (!(isr & SDH_INTSTS_CRC7_Msk))
+ {
+ if (!pSD->R3Flag)
+ {
+ /* CRC_7 error */
+ // handle CRC 7 error
+ }
+ }
+ /* Clear CRCIF interrupt flag */
+ SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_CRCIF_Msk);
+ }
+
+ /* Data-in timeout */
+ if (isr & SDH_INTSTS_DITOIF_Msk)
+ {
+ sdh_base->INTSTS |= SDH_INTSTS_DITOIF_Msk;
+ }
+
+ /* Response-in timeout interrupt */
+ if (isr & SDH_INTSTS_RTOIF_Msk)
+ {
+ sdh_base->INTSTS |= SDH_INTSTS_RTOIF_Msk;
+ }
+}
+
+#if defined(BSP_USING_SDH0)
+void SDH0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ nu_sdh_isr(&nu_sdh_arr[SDH0_IDX]);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SDH1)
+void SDH1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ nu_sdh_isr(&nu_sdh_arr[SDH1_IDX]);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+/* RT-Thread Device Driver Interface */
+static rt_err_t nu_sdh_init(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_err_t nu_sdh_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ nu_sdh_t sdh = (nu_sdh_t)dev;
+
+ RT_ASSERT(dev != RT_NULL);
+
+ return (SDH_Probe(sdh->base) == 0) ? RT_EOK : -(RT_ERROR);
+}
+
+static rt_err_t nu_sdh_close(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_size_t nu_sdh_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t blk_nb)
+{
+ rt_uint32_t ret = 0;
+ nu_sdh_t sdh = (nu_sdh_t)dev;
+
+ RT_ASSERT(dev != RT_NULL);
+ RT_ASSERT(buffer != RT_NULL);
+
+ rt_sem_take(&sdh->lock, RT_WAITING_FOREVER);
+
+ /* Check alignment. */
+ if (((uint32_t)buffer & 0x03) != 0)
+ {
+ /* Non-aligned. */
+ uint32_t i;
+ uint8_t *copy_buffer = (uint8_t *)buffer;
+
+ sdh->pbuf = rt_malloc(SDH_BLOCK_SIZE);
+ if (sdh->pbuf == RT_NULL)
+ goto exit_nu_sdh_read;
+
+ for (i = 0; i < blk_nb; i++)
+ {
+ /* Read to temp buffer from specified sector. */
+ ret = SDH_Read(sdh->base, &sdh->pbuf[0], pos, 1);
+ if (ret != Successful)
+ goto exit_nu_sdh_read;
+
+ /* Move to user's buffer */
+ NU_SDH_MEMCPY((void *)copy_buffer, (void *)&sdh->pbuf[0], SDH_BLOCK_SIZE);
+
+ pos ++;
+ copy_buffer += SDH_BLOCK_SIZE;
+ }
+ }
+ else
+ {
+ /* Read to user's buffer from specified sector. */
+ ret = SDH_Read(sdh->base, (uint8_t *)buffer, pos, blk_nb);
+ }
+
+exit_nu_sdh_read:
+
+ if (sdh->pbuf)
+ {
+ rt_free(sdh->pbuf);
+ sdh->pbuf = RT_NULL;
+ }
+
+ rt_sem_release(&sdh->lock);
+
+ if (ret == Successful)
+ return blk_nb;
+
+ rt_kprintf("Read failed: %d, buffer 0x%08x\n", ret, buffer);
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
+}
+
+static rt_size_t nu_sdh_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t blk_nb)
+{
+ rt_uint32_t ret = 0;
+ nu_sdh_t sdh = (nu_sdh_t)dev;
+
+ RT_ASSERT(dev != RT_NULL);
+ RT_ASSERT(buffer != RT_NULL);
+
+ rt_sem_take(&sdh->lock, RT_WAITING_FOREVER);
+
+ /* Check alignment. */
+ if (((uint32_t)buffer & 0x03) != 0)
+ {
+ /* Non-aligned. */
+ uint32_t i;
+ uint8_t *copy_buffer = (uint8_t *)buffer;
+
+ sdh->pbuf = rt_malloc(SDH_BLOCK_SIZE);
+ if (sdh->pbuf == RT_NULL)
+ goto exit_nu_sdh_write;
+
+ for (i = 0; i < blk_nb; i++)
+ {
+ NU_SDH_MEMCPY((void *)&sdh->pbuf[0], copy_buffer, SDH_BLOCK_SIZE);
+
+ ret = SDH_Write(sdh->base, (uint8_t *)&sdh->pbuf[0], pos, 1);
+ if (ret != Successful)
+ goto exit_nu_sdh_write;
+
+ pos++;
+ copy_buffer += SDH_BLOCK_SIZE;
+ }
+ }
+ else
+ {
+ /* Write to device directly. */
+ ret = SDH_Write(sdh->base, (uint8_t *)buffer, pos, blk_nb);
+ }
+
+exit_nu_sdh_write:
+
+ if (sdh->pbuf)
+ {
+ rt_free(sdh->pbuf);
+ sdh->pbuf = RT_NULL;
+ }
+
+ rt_sem_release(&sdh->lock);
+
+ if (ret == Successful) return blk_nb;
+
+ rt_kprintf("write failed: %d, buffer 0x%08x\n", ret, buffer);
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
+}
+
+static rt_err_t nu_sdh_control(rt_device_t dev, int cmd, void *args)
+{
+ nu_sdh_t sdh = (nu_sdh_t)dev;
+
+ RT_ASSERT(dev != RT_NULL);
+
+ if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
+ {
+ SDH_INFO_T *sdh_info = sdh->info;
+
+ struct rt_device_blk_geometry *geometry;
+
+ geometry = (struct rt_device_blk_geometry *)args;
+ if (geometry == RT_NULL) return -RT_ERROR;
+
+ geometry->bytes_per_sector = sdh_info->sectorSize;
+ geometry->block_size = sdh_info->sectorSize;
+ geometry->sector_count = sdh_info->totalSectorN;
+ }
+
+ return RT_EOK;
+}
+
+
+static int rt_hw_sdh_init(void)
+{
+ int i;
+ rt_err_t ret = RT_EOK;
+ rt_uint32_t flags = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE;
+
+ rt_event_init(&sdh_event, "sdh_event", RT_IPC_FLAG_FIFO);
+
+ for (i = (SDH_START + 1); i < SDH_CNT; i++)
+ {
+ /* Register sdcard device */
+ nu_sdh_arr[i].dev.type = RT_Device_Class_Block;
+ nu_sdh_arr[i].dev.init = nu_sdh_init;
+ nu_sdh_arr[i].dev.open = nu_sdh_open;
+ nu_sdh_arr[i].dev.close = nu_sdh_close;
+ nu_sdh_arr[i].dev.read = nu_sdh_read;
+ nu_sdh_arr[i].dev.write = nu_sdh_write;
+ nu_sdh_arr[i].dev.control = nu_sdh_control;
+
+ /* Private */
+ nu_sdh_arr[i].dev.user_data = (void *)&nu_sdh_arr[i];
+
+ rt_sem_init(&nu_sdh_arr[i].lock, "sdhlock", 1, RT_IPC_FLAG_FIFO);
+
+ SDH_Open(nu_sdh_arr[i].base, CardDetect_From_GPIO);
+
+ nu_sdh_arr[i].pbuf = RT_NULL;
+ ret = rt_device_register(&nu_sdh_arr[i].dev, nu_sdh_arr[i].name, flags);
+ RT_ASSERT(ret == RT_EOK);
+ }
+
+ return (int)ret;
+}
+INIT_BOARD_EXPORT(rt_hw_sdh_init);
+
+#if defined(NU_SDH_HOTPLUG)
+static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path)
+{
+ rt_bool_t ret = RT_FALSE;
+
+#if defined(RT_USING_DFS)
+
+ struct dfs_filesystem *psFS = dfs_filesystem_lookup(mounting_path);
+ if (psFS == RT_NULL)
+ {
+ goto exit_nu_sdh_hotplug_is_mounted;
+ }
+ else if (!rt_memcmp(psFS->path, mounting_path, rt_strlen(mounting_path)))
+ {
+ ret = RT_TRUE;
+ }
+ else
+ {
+ ret = RT_FALSE;
+ }
+
+#endif
+
+exit_nu_sdh_hotplug_is_mounted:
+
+ return ret;
+}
+static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
+{
+ rt_err_t ret = RT_ERROR;
+ DIR *t;
+
+#if defined(RT_USING_DFS)
+
+ if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_TRUE)
+ {
+ ret = RT_EOK;
+ goto exit_nu_sdh_hotplug_mount;
+ }
+
+ /* Check the SD folder path is valid. */
+ if ((t = opendir(sdh->mounted_point)) != RT_NULL)
+ {
+ closedir(t);
+ }
+ else
+ {
+
+ /* Check the ROOT path is valid. */
+ if ((t = opendir(NU_SDH_MOUNTPOINT_ROOT)) != RT_NULL)
+ {
+ closedir(t);
+ }
+ else if ((ret = mkdir(NU_SDH_MOUNTPOINT_ROOT, 0)) != RT_EOK)
+ {
+ rt_kprintf("Failed to mkdir %s\n", NU_SDH_MOUNTPOINT_ROOT);
+ goto exit_nu_sdh_hotplug_mount;
+ }
+
+ if ((ret = mkdir(sdh->mounted_point, 0)) != RT_EOK)
+ {
+ rt_kprintf("Failed to mkdir %s\n", sdh->mounted_point);
+ goto exit_nu_sdh_hotplug_mount;
+ }
+
+ } //else
+
+ if ((ret = dfs_mount(sdh->name, sdh->mounted_point, "elm", 0, 0)) == 0)
+ {
+ rt_kprintf("Mounted %s on %s\n", sdh->name, sdh->mounted_point);
+ }
+ else
+ {
+ rt_kprintf("Failed to mount %s on %s\n", sdh->name, sdh->mounted_point);
+ ret = RT_ERROR;
+ }
+
+exit_nu_sdh_hotplug_mount:
+
+#endif
+ return -(ret);
+}
+
+static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh)
+{
+ rt_err_t ret = RT_ERROR;
+
+#if defined(RT_USING_DFS)
+ if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_FALSE)
+ {
+ ret = RT_EOK;
+ goto exit_nu_sdh_hotplug_unmount;
+ }
+
+ ret = dfs_unmount(sdh->mounted_point);
+ if (ret != RT_EOK)
+ {
+ rt_kprintf("Failed to unmount %s.\n", sdh->mounted_point);
+ }
+ else
+ {
+ rt_kprintf("Succeed to unmount %s.\n", sdh->mounted_point);
+ ret = RT_EOK;
+ }
+#endif
+
+exit_nu_sdh_hotplug_unmount:
+
+ return -(ret);
+}
+static void sdh_hotplugger(void *param)
+{
+ rt_uint32_t e;
+ int i;
+
+ for (i = (SDH_START + 1); i < SDH_CNT; i++)
+ {
+ if (SDH_IS_CARD_PRESENT(nu_sdh_arr[i].base))
+ {
+ nu_sdh_hotplug_mount(&nu_sdh_arr[i]);
+ }
+ }
+
+ while (1)
+ {
+ if (rt_event_recv(&sdh_event, (NU_SDH_CARD_EVENT_ALL),
+ RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
+ RT_WAITING_FOREVER, &e) == RT_EOK)
+ {
+ /* Debouce */
+ rt_thread_delay(200);
+ switch (e)
+ {
+#if defined(BSP_USING_SDH0)
+ case NU_SDH_CARD_INSERTED_SD0:
+ nu_sdh_hotplug_mount(&nu_sdh_arr[SDH0_IDX]);
+ break;
+ case NU_SDH_CARD_REMOVED_SD0:
+ nu_sdh_hotplug_unmount(&nu_sdh_arr[SDH0_IDX]);
+ break;
+#endif
+#if defined(BSP_USING_SDH1)
+ case NU_SDH_CARD_INSERTED_SD1:
+ nu_sdh_hotplug_mount(&nu_sdh_arr[SDH1_IDX]);
+ break;
+ case NU_SDH_CARD_REMOVED_SD1:
+ nu_sdh_hotplug_unmount(&nu_sdh_arr[SDH1_IDX]);
+ break;
+#endif
+ default:
+ break;
+
+ } //switch(e)
+
+ } //if
+
+ } /* while(1) */
+}
+
+int mnt_init_sdcard_hotplug(void)
+{
+ rt_thread_init(&sdh_tid, "hotplug", sdh_hotplugger, NULL, sdh_stack, sizeof(sdh_stack), RT_THREAD_PRIORITY_MAX - 2, 10);
+ rt_thread_startup(&sdh_tid);
+
+ return 0;
+}
+INIT_ENV_EXPORT(mnt_init_sdcard_hotplug);
+#endif
+
+#endif //#if defined(BSP_USING_SDH)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c
new file mode 100644
index 00000000000..05f9906def1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c
@@ -0,0 +1,254 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2020-5-28 YCHuang12 First version
+*
+******************************************************************************/
+
+#include