From f00d7eba0b97f5e9eb51903a3b6311d35b048945 Mon Sep 17 00:00:00 2001 From: Soumil Kushwaha Date: Mon, 29 Jun 2026 17:03:33 -0500 Subject: [PATCH 1/6] adding liveness checks to handle partial defs --- .../src/rocjitsu/analysis/def_use_chain.cpp | 14 ++++- .../rocjitsu/tests/analysis/liveness_test.cpp | 59 ++++++++++++++++++- 2 files changed, 69 insertions(+), 4 deletions(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp index 34ffb9b9706d..896099a99ab6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp @@ -18,8 +18,18 @@ namespace { return ref.cls == RegClass::VGPR || ref.cls == RegClass::ACC_VGPR; } -void add_def(InstDefUse &du, RegisterRef ref) { +// A 32-bit register lane is the finest granularity RegisterSet tracks. An +// operand narrower than that (e.g. a 16-bit dst) writes only part of its +// lowest lane and leaves the remaining bits intact, so the instruction +// read-modify-writes that register rather than fully redefining it. +[[nodiscard]] bool is_partial_def(int size_bits) { return size_bits > 0 && size_bits < 32; } + +void add_def(InstDefUse &du, RegisterRef ref, int size_bits) { du.defs.expand(ref); + // Record a sub-lane def as a use as well: liveness must keep the register + // live across the instruction because the untouched bits survive the write. + if (is_partial_def(size_bits)) + du.uses.expand(ref); if (is_exec_masked_def(ref)) du.has_exec_masked_vector_def = true; } @@ -34,7 +44,7 @@ InstDefUse::InstDefUse(const Instruction &inst) { if (op == nullptr) continue; if (auto ref = op->to_register_ref()) - add_def(*this, *ref); + add_def(*this, *ref, op->size_bits()); } inst.implicit_defs(defs); diff --git a/emulation/rocjitsu/tests/analysis/liveness_test.cpp b/emulation/rocjitsu/tests/analysis/liveness_test.cpp index 17c0b8e2d198..80c3424293a6 100644 --- a/emulation/rocjitsu/tests/analysis/liveness_test.cpp +++ b/emulation/rocjitsu/tests/analysis/liveness_test.cpp @@ -34,6 +34,9 @@ class TestOperand : public Operand { public: TestOperand() = default; explicit TestOperand(RegisterRef ref) : Operand(ref.width * 32, ref.index), ref_(ref) {} + // Sub-lane operand: same RegisterRef, but a caller-chosen bit width so partial + // (less-than-32-bit) defs can be exercised. + TestOperand(RegisterRef ref, int size_bits) : Operand(size_bits, ref.index), ref_(ref) {} std::optional to_register_ref() const override { return ref_; } @@ -46,13 +49,16 @@ class TestInstruction : public Instruction { TestInstruction(std::string_view mnemonic, std::initializer_list defs = {}, std::initializer_list uses = {}, uint64_t flags = 0, std::optional branch_delta = std::nullopt, - std::initializer_list implicit_uses = {}) + std::initializer_list implicit_uses = {}, int def_size_bits = 0) : Instruction(mnemonic, nullptr), implicit_uses_(implicit_uses), branch_delta_(branch_delta) { size_ = 4; flags_ = flags; for (RegisterRef ref : defs) { - dst_storage_[num_dst_] = TestOperand(ref); + // def_size_bits == 0 keeps the default full-lane width; a non-zero value + // models a partial (sub-32-bit) def of the same register. + dst_storage_[num_dst_] = + def_size_bits == 0 ? TestOperand(ref) : TestOperand(ref, def_size_bits); dst_operands_[num_dst_] = &dst_storage_[num_dst_]; ++num_dst_; } @@ -122,6 +128,7 @@ enum class TestOpcode : uint32_t { CBranchToElseAfterTwo = 14, IndirectCall = 15, IndirectBranch = 16, + PartialDefSgpr4 = 17, }; class TestDecoder : public Decoder { @@ -164,6 +171,10 @@ class TestDecoder : public Decoder { return new TestInstruction("test_indirect_call", {}, {}, INDIRECT_CALL); case TestOpcode::IndirectBranch: return new TestInstruction("test_indirect_branch", {}, {}, INDIRECT_BRANCH); + case TestOpcode::PartialDefSgpr4: + // 16-bit write to s4: defines only part of the lane, so it also reads s4. + return new TestInstruction("test_partial_def_s4", {{RegClass::SGPR, 4, 1}}, {}, 0, + std::nullopt, {}, /*def_size_bits=*/16); } return new TestInstruction("test_end", {}, {}, PROGRAM_TERMINATOR); } @@ -661,6 +672,34 @@ TEST(LivenessAnalysis, ReadWriteRegisterStaysLiveOutWhenUsedBySuccessor) { EXPECT_TRUE(liveness.block_liveness(*blocks[0]).live_out.contains({RegClass::SGPR, 4, 1})); } +TEST(LivenessAnalysis, PartialDefKeepsRegisterLiveBeforeInstruction) { + auto blocks = build_test_blocks({TestOpcode::PartialDefSgpr4, TestOpcode::End}); + LivenessAnalysis liveness = analyze_scope(blocks); + + const Instruction &partial_def = *blocks[0]->instructions().begin(); + EXPECT_TRUE(liveness.is_live_before(partial_def, {RegClass::SGPR, 4, 1})); +} + +TEST(LivenessAnalysis, PartialDefRegisterStaysLiveOutWhenUsedBySuccessor) { + std::array extra_leaders{4}; + auto blocks = build_test_blocks( + {TestOpcode::PartialDefSgpr4, TestOpcode::UseSgpr4, TestOpcode::End}, extra_leaders); + LivenessAnalysis liveness = analyze_scope(blocks); + + ASSERT_EQ(blocks.size(), 2u); + const Instruction &partial_def = *blocks[0]->instructions().begin(); + EXPECT_TRUE(liveness.is_live_before(partial_def, {RegClass::SGPR, 4, 1})); + EXPECT_TRUE(liveness.block_liveness(*blocks[0]).live_out.contains({RegClass::SGPR, 4, 1})); +} + +TEST(LivenessAnalysis, FullWidthDefKillsRegisterBeforeInstruction) { + auto blocks = build_test_blocks({TestOpcode::DefSgpr4, TestOpcode::End}); + LivenessAnalysis liveness = analyze_scope(blocks); + + const Instruction &def = *blocks[0]->instructions().begin(); + EXPECT_FALSE(liveness.is_live_before(def, {RegClass::SGPR, 4, 1})); +} + TEST(LivenessAnalysis, ImplicitUseIsLiveBeforeInstruction) { auto blocks = build_test_blocks({TestOpcode::ImplicitUseSgpr6Pair, TestOpcode::End}); LivenessAnalysis liveness = analyze_scope(blocks); @@ -742,6 +781,22 @@ TEST(InstDefUse, RWSgpr) { EXPECT_TRUE(idu.uses.contains({RegClass::SGPR, 4, 1})); } +TEST(InstDefUse, PartialDefIsAlsoUse) { + const TestInstruction test_inst("test_partial_def_s4", {{RegClass::SGPR, 4, 1}}, {}, 0, + std::nullopt, {}, /*def_size_bits=*/16); + InstDefUse idu(test_inst); + EXPECT_TRUE(idu.defs.contains({RegClass::SGPR, 4, 1})); + EXPECT_TRUE(idu.uses.contains({RegClass::SGPR, 4, 1})); +} + +TEST(InstDefUse, FullWidthDefIsNotUse) { + const TestInstruction test_inst("test_def_s4", {{RegClass::SGPR, 4, 1}}, {}, 0, std::nullopt, {}, + /*def_size_bits=*/32); + InstDefUse idu(test_inst); + EXPECT_TRUE(idu.defs.contains({RegClass::SGPR, 4, 1})); + EXPECT_FALSE(idu.uses.contains({RegClass::SGPR, 4, 1})); +} + TEST(InstDefUse, Predicated) { const TestInstruction test_inst("test_pred_def_s4", {{RegClass::SGPR, 4, 1}}, {}, PREDICATED_DEF); InstDefUse idu(test_inst); From 0ab7507616f083fc62ed9ef62da7c554b78e9bb7 Mon Sep 17 00:00:00 2001 From: Soumil Kushwaha Date: Wed, 1 Jul 2026 16:19:59 -0500 Subject: [PATCH 2/6] addressed Allyson and James' comments --- .../lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp | 4 +++- emulation/rocjitsu/tests/analysis/liveness_test.cpp | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp index 896099a99ab6..18059530dee4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp @@ -10,6 +10,8 @@ namespace rocjitsu { namespace { +constexpr int MaxLaneWidth = 32; + // TODO: Replace this class-based approximation with instruction metadata that // identifies vector defs whose inactive lanes are preserved under EXEC, and pair // it with program-point EXEC state so full-EXEC writes can be treated as normal @@ -22,7 +24,7 @@ namespace { // operand narrower than that (e.g. a 16-bit dst) writes only part of its // lowest lane and leaves the remaining bits intact, so the instruction // read-modify-writes that register rather than fully redefining it. -[[nodiscard]] bool is_partial_def(int size_bits) { return size_bits > 0 && size_bits < 32; } +[[nodiscard]] bool is_partial_def(int size_bits) { return size_bits > 0 && size_bits < MaxLaneWidth; } void add_def(InstDefUse &du, RegisterRef ref, int size_bits) { du.defs.expand(ref); diff --git a/emulation/rocjitsu/tests/analysis/liveness_test.cpp b/emulation/rocjitsu/tests/analysis/liveness_test.cpp index 80c3424293a6..05fe108a677e 100644 --- a/emulation/rocjitsu/tests/analysis/liveness_test.cpp +++ b/emulation/rocjitsu/tests/analysis/liveness_test.cpp @@ -34,7 +34,7 @@ class TestOperand : public Operand { public: TestOperand() = default; explicit TestOperand(RegisterRef ref) : Operand(ref.width * 32, ref.index), ref_(ref) {} - // Sub-lane operand: same RegisterRef, but a caller-chosen bit width so partial + // Sub-register operand: same RegisterRef, but a caller-chosen bit width so partial // (less-than-32-bit) defs can be exercised. TestOperand(RegisterRef ref, int size_bits) : Operand(size_bits, ref.index), ref_(ref) {} From a1a7d4c91eb014c0eed19968f99feaaa6cd10054 Mon Sep 17 00:00:00 2001 From: Soumil Kushwaha Date: Wed, 1 Jul 2026 16:50:01 -0500 Subject: [PATCH 3/6] pre-commit fix --- .../lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp index 18059530dee4..08b3facc2b2a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp @@ -24,7 +24,9 @@ constexpr int MaxLaneWidth = 32; // operand narrower than that (e.g. a 16-bit dst) writes only part of its // lowest lane and leaves the remaining bits intact, so the instruction // read-modify-writes that register rather than fully redefining it. -[[nodiscard]] bool is_partial_def(int size_bits) { return size_bits > 0 && size_bits < MaxLaneWidth; } +[[nodiscard]] bool is_partial_def(int size_bits) { + return size_bits > 0 && size_bits < MaxLaneWidth; +} void add_def(InstDefUse &du, RegisterRef ref, int size_bits) { du.defs.expand(ref); From 02ed915bd61f6e3eb065cf893e704530ce68ea93 Mon Sep 17 00:00:00 2001 From: Soumil Kushwaha Date: Mon, 6 Jul 2026 13:03:32 -0500 Subject: [PATCH 4/6] removed TODO --- .../lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp index 08b3facc2b2a..ff4fdd377b4f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp @@ -12,10 +12,6 @@ namespace { constexpr int MaxLaneWidth = 32; -// TODO: Replace this class-based approximation with instruction metadata that -// identifies vector defs whose inactive lanes are preserved under EXEC, and pair -// it with program-point EXEC state so full-EXEC writes can be treated as normal -// kills. [[nodiscard]] bool is_exec_masked_def(RegisterRef ref) { return ref.cls == RegClass::VGPR || ref.cls == RegClass::ACC_VGPR; } From 222d277a6c7034208d24c70e3107741462c9858a Mon Sep 17 00:00:00 2001 From: Soumil Kushwaha Date: Tue, 7 Jul 2026 16:39:32 -0500 Subject: [PATCH 5/6] moved MaxLaneWidth to isa_traits.h and changed name to REGISTER_GRANULARITY --- .../lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp | 5 ++--- .../rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h | 8 ++++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp index ff4fdd377b4f..0de0520ee408 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp @@ -4,14 +4,13 @@ #include "rocjitsu/analysis/def_use_chain.h" #include "rocjitsu/isa/instruction.h" +#include "rocjitsu/isa/isa_traits.h" #include "rocjitsu/isa/operand.h" namespace rocjitsu { namespace { -constexpr int MaxLaneWidth = 32; - [[nodiscard]] bool is_exec_masked_def(RegisterRef ref) { return ref.cls == RegClass::VGPR || ref.cls == RegClass::ACC_VGPR; } @@ -21,7 +20,7 @@ constexpr int MaxLaneWidth = 32; // lowest lane and leaves the remaining bits intact, so the instruction // read-modify-writes that register rather than fully redefining it. [[nodiscard]] bool is_partial_def(int size_bits) { - return size_bits > 0 && size_bits < MaxLaneWidth; + return size_bits > 0 && size_bits < REGISTER_GRANULARITY; } void add_def(InstDefUse &du, RegisterRef ref, int size_bits) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h index 7987782100f5..74f62bc6b87e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h @@ -14,6 +14,14 @@ namespace rocjitsu { +/// @brief Width in bits of a single register lane — the finest granularity at +/// which registers are tracked. +/// +/// @details A 32-bit lane is the smallest unit RegisterSet addresses. An operand +/// narrower than this writes only part of its lowest lane and read-modify-writes +/// the register rather than fully redefining it. +inline constexpr int REGISTER_GRANULARITY = 32; + /// @brief Compile-time mapping from rj_code_arch_t enum values to Isa trait types. /// /// @details Specialize this template in each architecture's isa.h to bind its From 227b37791ef5a640c8136ca36820b74c4e6c410e Mon Sep 17 00:00:00 2001 From: Soumil Kushwaha Date: Fri, 10 Jul 2026 17:58:05 -0500 Subject: [PATCH 6/6] moved sub-32 bit src operand coverage to implicit_uses rather than in analysis, analysis gets the proper info with no changes --- .../lib/python/amdisa/codegen/_generator.py | 39 ++ .../src/rocjitsu/analysis/def_use_chain.cpp | 17 +- .../rocjitsu/isa/arch/amdgpu/cdna1/vop1.cpp | 132 +++++ .../src/rocjitsu/isa/arch/amdgpu/cdna1/vop1.h | 22 + .../rocjitsu/isa/arch/amdgpu/cdna1/vop2.cpp | 126 ++++ .../src/rocjitsu/isa/arch/amdgpu/cdna1/vop2.h | 21 + .../rocjitsu/isa/arch/amdgpu/cdna1/vop3.cpp | 372 ++++++++++++ .../src/rocjitsu/isa/arch/amdgpu/cdna1/vop3.h | 62 ++ .../rocjitsu/isa/arch/amdgpu/cdna1/vop3p.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/cdna1/vop3p.h | 2 + .../rocjitsu/isa/arch/amdgpu/cdna2/vop1.cpp | 132 +++++ .../src/rocjitsu/isa/arch/amdgpu/cdna2/vop1.h | 22 + .../rocjitsu/isa/arch/amdgpu/cdna2/vop2.cpp | 126 ++++ .../src/rocjitsu/isa/arch/amdgpu/cdna2/vop2.h | 21 + .../rocjitsu/isa/arch/amdgpu/cdna2/vop3.cpp | 372 ++++++++++++ .../src/rocjitsu/isa/arch/amdgpu/cdna2/vop3.h | 62 ++ .../rocjitsu/isa/arch/amdgpu/cdna2/vop3p.cpp | 108 ++++ .../rocjitsu/isa/arch/amdgpu/cdna2/vop3p.h | 18 + .../rocjitsu/isa/arch/amdgpu/cdna3/vop1.cpp | 132 +++++ .../src/rocjitsu/isa/arch/amdgpu/cdna3/vop1.h | 22 + .../rocjitsu/isa/arch/amdgpu/cdna3/vop2.cpp | 126 ++++ .../src/rocjitsu/isa/arch/amdgpu/cdna3/vop2.h | 21 + .../rocjitsu/isa/arch/amdgpu/cdna3/vop3.cpp | 396 +++++++++++++ .../src/rocjitsu/isa/arch/amdgpu/cdna3/vop3.h | 66 +++ .../rocjitsu/isa/arch/amdgpu/cdna3/vop3p.cpp | 66 +++ .../rocjitsu/isa/arch/amdgpu/cdna3/vop3p.h | 11 + .../rocjitsu/isa/arch/amdgpu/cdna4/sopk.cpp | 12 + .../src/rocjitsu/isa/arch/amdgpu/cdna4/sopk.h | 2 + .../rocjitsu/isa/arch/amdgpu/cdna4/vop1.cpp | 132 +++++ .../src/rocjitsu/isa/arch/amdgpu/cdna4/vop1.h | 22 + .../rocjitsu/isa/arch/amdgpu/cdna4/vop2.cpp | 126 ++++ .../src/rocjitsu/isa/arch/amdgpu/cdna4/vop2.h | 21 + .../rocjitsu/isa/arch/amdgpu/cdna4/vop3.cpp | 546 ++++++++++++++++++ .../src/rocjitsu/isa/arch/amdgpu/cdna4/vop3.h | 91 +++ .../rocjitsu/isa/arch/amdgpu/cdna4/vop3p.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/cdna4/vop3p.h | 2 + .../rocjitsu/isa/arch/amdgpu/gfx1250/sop1.cpp | 30 + .../rocjitsu/isa/arch/amdgpu/gfx1250/sop1.h | 5 + .../rocjitsu/isa/arch/amdgpu/gfx1250/sop2.cpp | 48 ++ .../rocjitsu/isa/arch/amdgpu/gfx1250/sop2.h | 8 + .../rocjitsu/isa/arch/amdgpu/gfx1250/sopk.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/gfx1250/sopk.h | 2 + .../rocjitsu/isa/arch/amdgpu/gfx1250/vop1.cpp | 230 ++++++++ .../rocjitsu/isa/arch/amdgpu/gfx1250/vop1.h | 38 ++ .../rocjitsu/isa/arch/amdgpu/gfx1250/vop2.cpp | 60 ++ .../rocjitsu/isa/arch/amdgpu/gfx1250/vop2.h | 10 + .../rocjitsu/isa/arch/amdgpu/gfx1250/vop3.h | 93 +++ .../isa/arch/amdgpu/gfx1250/vop3_alu.cpp | 308 ++++++---- .../isa/arch/amdgpu/gfx1250/vop3_alu_2.cpp | 194 +++++++ .../isa/arch/amdgpu/gfx1250/vop3_cvt.cpp | 156 +++-- .../isa/arch/amdgpu/gfx1250/vop3_cvt_2.cpp | 138 +++++ .../isa/arch/amdgpu/gfx1250/vop3_data.cpp | 12 + .../isa/arch/amdgpu/gfx1250/vop3_misc.cpp | 18 + .../isa/arch/amdgpu/gfx1250/vop3_ternary.cpp | 120 ++++ .../isa/arch/amdgpu/gfx1250/vop3p.cpp | 24 + .../rocjitsu/isa/arch/amdgpu/gfx1250/vop3p.h | 4 + .../src/rocjitsu/isa/arch/amdgpu/rdna1/ds.cpp | 60 ++ .../src/rocjitsu/isa/arch/amdgpu/rdna1/ds.h | 10 + .../rocjitsu/isa/arch/amdgpu/rdna1/sopk.cpp | 12 + .../src/rocjitsu/isa/arch/amdgpu/rdna1/sopk.h | 2 + .../rocjitsu/isa/arch/amdgpu/rdna1/vop1.cpp | 126 ++++ .../src/rocjitsu/isa/arch/amdgpu/rdna1/vop1.h | 21 + .../rocjitsu/isa/arch/amdgpu/rdna1/vop2.cpp | 60 ++ .../src/rocjitsu/isa/arch/amdgpu/rdna1/vop2.h | 10 + .../rocjitsu/isa/arch/amdgpu/rdna1/vop3.cpp | 330 +++++++++++ .../src/rocjitsu/isa/arch/amdgpu/rdna1/vop3.h | 55 ++ .../rocjitsu/isa/arch/amdgpu/rdna1/vop3p.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/rdna1/vop3p.h | 2 + .../src/rocjitsu/isa/arch/amdgpu/rdna2/ds.cpp | 60 ++ .../src/rocjitsu/isa/arch/amdgpu/rdna2/ds.h | 10 + .../rocjitsu/isa/arch/amdgpu/rdna2/sopk.cpp | 12 + .../src/rocjitsu/isa/arch/amdgpu/rdna2/sopk.h | 2 + .../rocjitsu/isa/arch/amdgpu/rdna2/vop1.cpp | 126 ++++ .../src/rocjitsu/isa/arch/amdgpu/rdna2/vop1.h | 21 + .../rocjitsu/isa/arch/amdgpu/rdna2/vop2.cpp | 60 ++ .../src/rocjitsu/isa/arch/amdgpu/rdna2/vop2.h | 10 + .../rocjitsu/isa/arch/amdgpu/rdna2/vop3.cpp | 330 +++++++++++ .../src/rocjitsu/isa/arch/amdgpu/rdna2/vop3.h | 55 ++ .../rocjitsu/isa/arch/amdgpu/rdna2/vop3p.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/rdna2/vop3p.h | 2 + .../rocjitsu/isa/arch/amdgpu/rdna3/sopk.cpp | 12 + .../src/rocjitsu/isa/arch/amdgpu/rdna3/sopk.h | 2 + .../isa/arch/amdgpu/rdna3/vinterp.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/rdna3/vinterp.h | 2 + .../rocjitsu/isa/arch/amdgpu/rdna3/vop1.cpp | 152 +++++ .../src/rocjitsu/isa/arch/amdgpu/rdna3/vop1.h | 25 + .../rocjitsu/isa/arch/amdgpu/rdna3/vop2.cpp | 60 ++ .../src/rocjitsu/isa/arch/amdgpu/rdna3/vop2.h | 10 + .../rocjitsu/isa/arch/amdgpu/rdna3/vop3.cpp | 390 +++++++++++++ .../src/rocjitsu/isa/arch/amdgpu/rdna3/vop3.h | 65 +++ .../rocjitsu/isa/arch/amdgpu/rdna3/vop3p.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/rdna3/vop3p.h | 2 + .../rocjitsu/isa/arch/amdgpu/rdna3_5/sop1.cpp | 30 + .../rocjitsu/isa/arch/amdgpu/rdna3_5/sop1.h | 5 + .../rocjitsu/isa/arch/amdgpu/rdna3_5/sop2.cpp | 42 ++ .../rocjitsu/isa/arch/amdgpu/rdna3_5/sop2.h | 7 + .../rocjitsu/isa/arch/amdgpu/rdna3_5/sopk.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/rdna3_5/sopk.h | 2 + .../isa/arch/amdgpu/rdna3_5/vinterp.cpp | 12 + .../isa/arch/amdgpu/rdna3_5/vinterp.h | 2 + .../rocjitsu/isa/arch/amdgpu/rdna3_5/vop1.cpp | 152 +++++ .../rocjitsu/isa/arch/amdgpu/rdna3_5/vop1.h | 25 + .../rocjitsu/isa/arch/amdgpu/rdna3_5/vop2.cpp | 60 ++ .../rocjitsu/isa/arch/amdgpu/rdna3_5/vop2.h | 10 + .../rocjitsu/isa/arch/amdgpu/rdna3_5/vop3.cpp | 390 +++++++++++++ .../rocjitsu/isa/arch/amdgpu/rdna3_5/vop3.h | 65 +++ .../isa/arch/amdgpu/rdna3_5/vop3p.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/rdna3_5/vop3p.h | 2 + .../rocjitsu/isa/arch/amdgpu/rdna4/sop1.cpp | 30 + .../src/rocjitsu/isa/arch/amdgpu/rdna4/sop1.h | 5 + .../rocjitsu/isa/arch/amdgpu/rdna4/sop2.cpp | 54 ++ .../src/rocjitsu/isa/arch/amdgpu/rdna4/sop2.h | 9 + .../rocjitsu/isa/arch/amdgpu/rdna4/sopk.cpp | 12 + .../src/rocjitsu/isa/arch/amdgpu/rdna4/sopk.h | 2 + .../isa/arch/amdgpu/rdna4/vinterp.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/rdna4/vinterp.h | 2 + .../rocjitsu/isa/arch/amdgpu/rdna4/vop1.cpp | 152 +++++ .../src/rocjitsu/isa/arch/amdgpu/rdna4/vop1.h | 25 + .../rocjitsu/isa/arch/amdgpu/rdna4/vop2.cpp | 60 ++ .../src/rocjitsu/isa/arch/amdgpu/rdna4/vop2.h | 10 + .../rocjitsu/isa/arch/amdgpu/rdna4/vop3.cpp | 450 +++++++++++++++ .../src/rocjitsu/isa/arch/amdgpu/rdna4/vop3.h | 75 +++ .../rocjitsu/isa/arch/amdgpu/rdna4/vop3p.cpp | 12 + .../rocjitsu/isa/arch/amdgpu/rdna4/vop3p.h | 2 + .../rocjitsu/tests/analysis/liveness_test.cpp | 10 + 125 files changed, 8667 insertions(+), 209 deletions(-) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index 18a986a7b3f0..ef60c02367ef 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -5659,6 +5659,30 @@ def gen_insts(self) -> None: public_members.append( cgen.Statement('void execute_impl(amdgpu::Wavefront &wf)') ) + # A sub-dword (< 32-bit) destination writes only part of its + # 32-bit register lane, so the old value survives and the + # register is also a read. Surface these partial defs as + # implicit uses. Runtime-sized outputs are never sub-dword, + # so a static size check suffices. Immediate/label outputs + # (e.g. the S_SETREG hwreg selector) never name a register, + # so skip them to avoid dead overrides. + _partial_def_outputs = [ + o.name + for o in inst.operands + if o.is_output + and operand_size_exprs.get(o.name, str(o.size)) == str(o.size) + and 0 < o.size < 32 + and not any( + tag in o.operand_type.upper() + for tag in ('IMM', 'LABEL', 'CONST') + ) + ] + if _partial_def_outputs: + public_members.append( + cgen.Statement( + 'void implicit_uses(RegisterSet &uses) const override' + ) + ) if gfx1250_f8f6f4_shape is not None or gfx1250_swmmac_has_modifiers: public_members.append( cgen.Statement( @@ -6508,6 +6532,21 @@ def _dpp_write_mask_lines( f'}}' ) ) + if _partial_def_outputs: + _pd_body = ''.join( + f' if (auto r = {name}.to_register_ref())\n' + f' uses.expand(*r);\n' + for name in _partial_def_outputs + ) + inst_impls.append( + cgen.Line( + f'void {inst.fmt_name}::implicit_uses' + f'(RegisterSet &uses) const {{\n' + f' {inst.fmt_true_enc_name}::implicit_uses(uses);\n' + f'{_pd_body}' + f'}}' + ) + ) inst_impls.append(exec_impl) class_func_impls.extend(inst_impls) source_impl_units.append( diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp index 0de0520ee408..3ab1486738b5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp @@ -4,7 +4,6 @@ #include "rocjitsu/analysis/def_use_chain.h" #include "rocjitsu/isa/instruction.h" -#include "rocjitsu/isa/isa_traits.h" #include "rocjitsu/isa/operand.h" namespace rocjitsu { @@ -15,20 +14,8 @@ namespace { return ref.cls == RegClass::VGPR || ref.cls == RegClass::ACC_VGPR; } -// A 32-bit register lane is the finest granularity RegisterSet tracks. An -// operand narrower than that (e.g. a 16-bit dst) writes only part of its -// lowest lane and leaves the remaining bits intact, so the instruction -// read-modify-writes that register rather than fully redefining it. -[[nodiscard]] bool is_partial_def(int size_bits) { - return size_bits > 0 && size_bits < REGISTER_GRANULARITY; -} - -void add_def(InstDefUse &du, RegisterRef ref, int size_bits) { +void add_def(InstDefUse &du, RegisterRef ref) { du.defs.expand(ref); - // Record a sub-lane def as a use as well: liveness must keep the register - // live across the instruction because the untouched bits survive the write. - if (is_partial_def(size_bits)) - du.uses.expand(ref); if (is_exec_masked_def(ref)) du.has_exec_masked_vector_def = true; } @@ -43,7 +30,7 @@ InstDefUse::InstDefUse(const Instruction &inst) { if (op == nullptr) continue; if (auto ref = op->to_register_ref()) - add_def(*this, *ref, op->size_bits()); + add_def(*this, *ref); } inst.implicit_defs(defs); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop1.cpp index 973339818bea..6fcc0264f4d7 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop1.cpp @@ -1119,6 +1119,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } } +void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6764,6 +6770,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } } +void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6885,6 +6897,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } } +void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7006,6 +7024,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } } +void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7127,6 +7151,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } } +void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7248,6 +7278,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } } +void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7381,6 +7417,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } } +void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7514,6 +7556,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } } +void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7647,6 +7695,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } } +void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7780,6 +7834,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } } +void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7913,6 +7973,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } } +void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8046,6 +8112,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } } +void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8179,6 +8251,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } } +void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8312,6 +8390,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } } +void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8445,6 +8529,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } } +void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8578,6 +8668,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } } +void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8711,6 +8807,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } } +void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8844,6 +8946,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } } +void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8977,6 +9085,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } } +void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9110,6 +9224,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } } +void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9243,6 +9363,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } } +void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9376,6 +9502,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } } +void VSatPkU8I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop1.h index 6fe50f0e3227..604c9654a1a2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop1.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop1 : public Vop1 { public: VCvtF16F32Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -446,6 +447,7 @@ class VCvtF16U16Vop1 : public Vop1 { public: VCvtF16U16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -454,6 +456,7 @@ class VCvtF16I16Vop1 : public Vop1 { public: VCvtF16I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -462,6 +465,7 @@ class VCvtU16F16Vop1 : public Vop1 { public: VCvtU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -470,6 +474,7 @@ class VCvtI16F16Vop1 : public Vop1 { public: VCvtI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +483,7 @@ class VRcpF16Vop1 : public Vop1 { public: VRcpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +492,7 @@ class VSqrtF16Vop1 : public Vop1 { public: VSqrtF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +501,7 @@ class VRsqF16Vop1 : public Vop1 { public: VRsqF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +510,7 @@ class VLogF16Vop1 : public Vop1 { public: VLogF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +519,7 @@ class VExpF16Vop1 : public Vop1 { public: VExpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +528,7 @@ class VFrexpMantF16Vop1 : public Vop1 { public: VFrexpMantF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +537,7 @@ class VFrexpExpI16F16Vop1 : public Vop1 { public: VFrexpExpI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +546,7 @@ class VFloorF16Vop1 : public Vop1 { public: VFloorF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +555,7 @@ class VCeilF16Vop1 : public Vop1 { public: VCeilF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +564,7 @@ class VTruncF16Vop1 : public Vop1 { public: VTruncF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +573,7 @@ class VRndneF16Vop1 : public Vop1 { public: VRndneF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +582,7 @@ class VFractF16Vop1 : public Vop1 { public: VFractF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +591,7 @@ class VSinF16Vop1 : public Vop1 { public: VSinF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +600,7 @@ class VCosF16Vop1 : public Vop1 { public: VCosF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +609,7 @@ class VCvtNormI16F16Vop1 : public Vop1 { public: VCvtNormI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +618,7 @@ class VCvtNormU16F16Vop1 : public Vop1 { public: VCvtNormU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +627,7 @@ class VSatPkU8I16Vop1 : public Vop1 { public: VSatPkU8I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop2.cpp index f7fbed27ff6b..cb9dd84fee90 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop2.cpp @@ -4159,6 +4159,12 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } } +void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4299,6 +4305,12 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } } +void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4439,6 +4451,12 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } } +void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4579,6 +4597,12 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } } +void VMulF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4720,6 +4744,12 @@ VMacF16Vop2::VMacF16Vop2(const MachineInst *inst) } } +void VMacF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMacF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4866,6 +4896,12 @@ VMadmkF16Vop2::VMadmkF16Vop2(const MachineInst *inst) } } +void VMadmkF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadmkF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5012,6 +5048,12 @@ VMadakF16Vop2::VMadakF16Vop2(const MachineInst *inst) } } +void VMadakF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadakF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5152,6 +5194,12 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) } } +void VAddU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5280,6 +5328,12 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) } } +void VSubU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5408,6 +5462,12 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) } } +void VSubrevU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5536,6 +5596,12 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) } } +void VMulLoU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5664,6 +5730,12 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) } } +void VLshlrevB16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5792,6 +5864,12 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) } } +void VLshrrevB16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5920,6 +5998,12 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) } } +void VAshrrevI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6048,6 +6132,12 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } } +void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6188,6 +6278,12 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } } +void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6328,6 +6424,12 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) } } +void VMaxU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6456,6 +6558,12 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) } } +void VMaxI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6584,6 +6692,12 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) } } +void VMinU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6712,6 +6826,12 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) } } +void VMinI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6840,6 +6960,12 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } } +void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop2.h index 2aa165c277c3..c452b791a83d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop2.h @@ -299,6 +299,7 @@ class VAddF16Vop2 : public Vop2 { public: VAddF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -308,6 +309,7 @@ class VSubF16Vop2 : public Vop2 { public: VSubF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -317,6 +319,7 @@ class VSubrevF16Vop2 : public Vop2 { public: VSubrevF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -326,6 +329,7 @@ class VMulF16Vop2 : public Vop2 { public: VMulF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -335,6 +339,7 @@ class VMacF16Vop2 : public Vop2 { public: VMacF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -344,6 +349,7 @@ class VMadmkF16Vop2 : public Vop2 { public: VMadmkF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand simm32; @@ -354,6 +360,7 @@ class VMadakF16Vop2 : public Vop2 { public: VMadakF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -364,6 +371,7 @@ class VAddU16Vop2 : public Vop2 { public: VAddU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -373,6 +381,7 @@ class VSubU16Vop2 : public Vop2 { public: VSubU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -382,6 +391,7 @@ class VSubrevU16Vop2 : public Vop2 { public: VSubrevU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -391,6 +401,7 @@ class VMulLoU16Vop2 : public Vop2 { public: VMulLoU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -400,6 +411,7 @@ class VLshlrevB16Vop2 : public Vop2 { public: VLshlrevB16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -409,6 +421,7 @@ class VLshrrevB16Vop2 : public Vop2 { public: VLshrrevB16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -418,6 +431,7 @@ class VAshrrevI16Vop2 : public Vop2 { public: VAshrrevI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -427,6 +441,7 @@ class VMaxF16Vop2 : public Vop2 { public: VMaxF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -436,6 +451,7 @@ class VMinF16Vop2 : public Vop2 { public: VMinF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -445,6 +461,7 @@ class VMaxU16Vop2 : public Vop2 { public: VMaxU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -454,6 +471,7 @@ class VMaxI16Vop2 : public Vop2 { public: VMaxI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -463,6 +481,7 @@ class VMinU16Vop2 : public Vop2 { public: VMinU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -472,6 +491,7 @@ class VMinI16Vop2 : public Vop2 { public: VMinI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -481,6 +501,7 @@ class VLdexpF16Vop2 : public Vop2 { public: VLdexpF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3.cpp index 65c08fce6476..e8267c931cde 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3.cpp @@ -215,6 +215,12 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -876,6 +882,12 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -902,6 +914,12 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -928,6 +946,12 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -960,6 +984,12 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -993,6 +1023,12 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRcpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rcp_f32_simd(a); }); @@ -1040,6 +1076,12 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSqrtF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { @@ -1092,6 +1134,12 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRsqF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rsq_f32_simd(a); }); @@ -1139,6 +1187,12 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLogF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::log_f32_simd(a); }); @@ -1186,6 +1240,12 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VExpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::exp_f32_simd(a); }); @@ -1234,6 +1294,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFrexpMantF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16( @@ -1288,6 +1354,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFrexpExpI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { @@ -1345,6 +1417,12 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFloorF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::floor_simd(a); }); @@ -1392,6 +1470,12 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCeilF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::ceil_simd(a); }); @@ -1440,6 +1524,12 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VTruncF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::trunc_simd(a); }); @@ -1488,6 +1578,12 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRndneF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rndne_simd(a); }); @@ -1536,6 +1632,12 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFractF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return a - util::floor_simd(a); }); @@ -1586,6 +1688,12 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1631,6 +1739,12 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCosF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1677,6 +1791,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtNormI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1708,6 +1828,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtNormU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1739,6 +1865,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSatPkU8I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -2134,6 +2266,12 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2194,6 +2332,12 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2255,6 +2399,12 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubrevF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2315,6 +2465,12 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMulF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2376,6 +2532,12 @@ VMacF16Vop3::VMacF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMacF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMacF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_FMAC_VOP3_TRUE16_FP16( @@ -2439,6 +2601,12 @@ VAddU16Vop3::VAddU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2468,6 +2636,12 @@ VSubU16Vop3::VSubU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2498,6 +2672,12 @@ VSubrevU16Vop3::VSubrevU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubrevU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2528,6 +2708,12 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMulLoU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2559,6 +2745,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLshlrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2585,6 +2777,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLshrrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2611,6 +2809,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAshrrevI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2638,6 +2842,12 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2700,6 +2910,12 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2762,6 +2978,12 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2792,6 +3014,12 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2822,6 +3050,12 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2852,6 +3086,12 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2883,6 +3123,12 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLdexpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -3795,6 +4041,12 @@ VMadLegacyF16Vop3::VMadLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { return a * b + c; }); @@ -3865,6 +4117,12 @@ VMadLegacyU16Vop3::VMadLegacyU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -3897,6 +4155,12 @@ VMadLegacyI16Vop3::VMadLegacyI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -3950,6 +4214,12 @@ VFmaLegacyF16Vop3::VFmaLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFmaLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4022,6 +4292,12 @@ VDivFixupLegacyF16Vop3::VDivFixupLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VDivFixupLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4204,6 +4480,12 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4276,6 +4558,12 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4320,6 +4608,12 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4361,6 +4655,12 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4433,6 +4733,12 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4477,6 +4783,12 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4518,6 +4830,12 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { @@ -4592,6 +4910,12 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4638,6 +4962,12 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4792,6 +5122,12 @@ VMadF16Vop3::VMadF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { return a * b + c; }); @@ -4861,6 +5197,12 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -4889,6 +5231,12 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -4920,6 +5268,12 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFmaF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4992,6 +5346,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VDivFixupF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -5609,6 +5969,12 @@ VAddI16Vop3::VAddI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -5637,6 +6003,12 @@ VSubI16Vop3::VSubI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3.h index db3a5fcb3822..6d30f3f2ace4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3.h @@ -115,6 +115,7 @@ class VCvtF16F32Vop3 : public Vop3 { public: VCvtF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -473,6 +474,7 @@ class VCvtF16U16Vop3 : public Vop3 { public: VCvtF16U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -481,6 +483,7 @@ class VCvtF16I16Vop3 : public Vop3 { public: VCvtF16I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -489,6 +492,7 @@ class VCvtU16F16Vop3 : public Vop3 { public: VCvtU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -497,6 +501,7 @@ class VCvtI16F16Vop3 : public Vop3 { public: VCvtI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -505,6 +510,7 @@ class VRcpF16Vop3 : public Vop3 { public: VRcpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -513,6 +519,7 @@ class VSqrtF16Vop3 : public Vop3 { public: VSqrtF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -521,6 +528,7 @@ class VRsqF16Vop3 : public Vop3 { public: VRsqF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -529,6 +537,7 @@ class VLogF16Vop3 : public Vop3 { public: VLogF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -537,6 +546,7 @@ class VExpF16Vop3 : public Vop3 { public: VExpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -545,6 +555,7 @@ class VFrexpMantF16Vop3 : public Vop3 { public: VFrexpMantF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -553,6 +564,7 @@ class VFrexpExpI16F16Vop3 : public Vop3 { public: VFrexpExpI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -561,6 +573,7 @@ class VFloorF16Vop3 : public Vop3 { public: VFloorF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -569,6 +582,7 @@ class VCeilF16Vop3 : public Vop3 { public: VCeilF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -577,6 +591,7 @@ class VTruncF16Vop3 : public Vop3 { public: VTruncF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -585,6 +600,7 @@ class VRndneF16Vop3 : public Vop3 { public: VRndneF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -593,6 +609,7 @@ class VFractF16Vop3 : public Vop3 { public: VFractF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -601,6 +618,7 @@ class VSinF16Vop3 : public Vop3 { public: VSinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -609,6 +627,7 @@ class VCosF16Vop3 : public Vop3 { public: VCosF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -617,6 +636,7 @@ class VCvtNormI16F16Vop3 : public Vop3 { public: VCvtNormI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -625,6 +645,7 @@ class VCvtNormU16F16Vop3 : public Vop3 { public: VCvtNormU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -633,6 +654,7 @@ class VSatPkU8I16Vop3 : public Vop3 { public: VSatPkU8I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -857,6 +879,7 @@ class VAddF16Vop3 : public Vop3 { public: VAddF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -866,6 +889,7 @@ class VSubF16Vop3 : public Vop3 { public: VSubF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -875,6 +899,7 @@ class VSubrevF16Vop3 : public Vop3 { public: VSubrevF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -884,6 +909,7 @@ class VMulF16Vop3 : public Vop3 { public: VMulF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -893,6 +919,7 @@ class VMacF16Vop3 : public Vop3 { public: VMacF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -902,6 +929,7 @@ class VAddU16Vop3 : public Vop3 { public: VAddU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -911,6 +939,7 @@ class VSubU16Vop3 : public Vop3 { public: VSubU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -920,6 +949,7 @@ class VSubrevU16Vop3 : public Vop3 { public: VSubrevU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -929,6 +959,7 @@ class VMulLoU16Vop3 : public Vop3 { public: VMulLoU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -938,6 +969,7 @@ class VLshlrevB16Vop3 : public Vop3 { public: VLshlrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -947,6 +979,7 @@ class VLshrrevB16Vop3 : public Vop3 { public: VLshrrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -956,6 +989,7 @@ class VAshrrevI16Vop3 : public Vop3 { public: VAshrrevI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -965,6 +999,7 @@ class VMaxF16Vop3 : public Vop3 { public: VMaxF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -974,6 +1009,7 @@ class VMinF16Vop3 : public Vop3 { public: VMinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -983,6 +1019,7 @@ class VMaxU16Vop3 : public Vop3 { public: VMaxU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -992,6 +1029,7 @@ class VMaxI16Vop3 : public Vop3 { public: VMaxI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1001,6 +1039,7 @@ class VMinU16Vop3 : public Vop3 { public: VMinU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1010,6 +1049,7 @@ class VMinI16Vop3 : public Vop3 { public: VMinI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1019,6 +1059,7 @@ class VLdexpF16Vop3 : public Vop3 { public: VLdexpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1498,6 +1539,7 @@ class VMadLegacyF16Vop3 : public Vop3 { public: VMadLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1508,6 +1550,7 @@ class VMadLegacyU16Vop3 : public Vop3 { public: VMadLegacyU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1518,6 +1561,7 @@ class VMadLegacyI16Vop3 : public Vop3 { public: VMadLegacyI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1538,6 +1582,7 @@ class VFmaLegacyF16Vop3 : public Vop3 { public: VFmaLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1548,6 +1593,7 @@ class VDivFixupLegacyF16Vop3 : public Vop3 { public: VDivFixupLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1597,6 +1643,7 @@ class VMin3F16Vop3 : public Vop3 { public: VMin3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1607,6 +1654,7 @@ class VMin3I16Vop3 : public Vop3 { public: VMin3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1617,6 +1665,7 @@ class VMin3U16Vop3 : public Vop3 { public: VMin3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1627,6 +1676,7 @@ class VMax3F16Vop3 : public Vop3 { public: VMax3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1637,6 +1687,7 @@ class VMax3I16Vop3 : public Vop3 { public: VMax3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1647,6 +1698,7 @@ class VMax3U16Vop3 : public Vop3 { public: VMax3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1657,6 +1709,7 @@ class VMed3F16Vop3 : public Vop3 { public: VMed3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1667,6 +1720,7 @@ class VMed3I16Vop3 : public Vop3 { public: VMed3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1677,6 +1731,7 @@ class VMed3U16Vop3 : public Vop3 { public: VMed3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1747,6 +1802,7 @@ class VMadF16Vop3 : public Vop3 { public: VMadF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1757,6 +1813,7 @@ class VMadU16Vop3 : public Vop3 { public: VMadU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1767,6 +1824,7 @@ class VMadI16Vop3 : public Vop3 { public: VMadI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1777,6 +1835,7 @@ class VFmaF16Vop3 : public Vop3 { public: VFmaF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1787,6 +1846,7 @@ class VDivFixupF16Vop3 : public Vop3 { public: VDivFixupF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2088,6 +2148,7 @@ class VAddI16Vop3 : public Vop3 { public: VAddI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2097,6 +2158,7 @@ class VSubI16Vop3 : public Vop3 { public: VSubI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3p.cpp index 0e2ad0eb076e..dc9a08375c13 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3p.cpp @@ -384,6 +384,12 @@ VMadMixloF16Vop3p::VMadMixloF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VMadMixloF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadMixloF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_mixlo_f16_vop3p(*this, wf); } @@ -404,6 +410,12 @@ VMadMixhiF16Vop3p::VMadMixhiF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VMadMixhiF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadMixhiF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_mixhi_f16_vop3p(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3p.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3p.h index 6c27cdf4e1ee..f4f409ca2fc4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3p.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop3p.h @@ -202,6 +202,7 @@ class VMadMixloF16Vop3p : public Vop3p { public: VMadMixloF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -212,6 +213,7 @@ class VMadMixhiF16Vop3p : public Vop3p { public: VMadMixhiF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop1.cpp index 15750ce6205f..dfc174b612af 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop1.cpp @@ -1119,6 +1119,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } } +void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6764,6 +6770,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } } +void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6885,6 +6897,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } } +void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7006,6 +7024,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } } +void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7127,6 +7151,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } } +void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7248,6 +7278,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } } +void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7381,6 +7417,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } } +void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7514,6 +7556,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } } +void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7647,6 +7695,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } } +void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7780,6 +7834,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } } +void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7913,6 +7973,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } } +void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8046,6 +8112,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } } +void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8179,6 +8251,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } } +void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8312,6 +8390,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } } +void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8445,6 +8529,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } } +void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8578,6 +8668,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } } +void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8711,6 +8807,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } } +void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8844,6 +8946,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } } +void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8977,6 +9085,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } } +void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9110,6 +9224,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } } +void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9243,6 +9363,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } } +void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9376,6 +9502,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } } +void VSatPkU8I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop1.h index f7f9d8776f35..8d8a7d6f2836 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop1.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop1 : public Vop1 { public: VCvtF16F32Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -446,6 +447,7 @@ class VCvtF16U16Vop1 : public Vop1 { public: VCvtF16U16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -454,6 +456,7 @@ class VCvtF16I16Vop1 : public Vop1 { public: VCvtF16I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -462,6 +465,7 @@ class VCvtU16F16Vop1 : public Vop1 { public: VCvtU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -470,6 +474,7 @@ class VCvtI16F16Vop1 : public Vop1 { public: VCvtI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +483,7 @@ class VRcpF16Vop1 : public Vop1 { public: VRcpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +492,7 @@ class VSqrtF16Vop1 : public Vop1 { public: VSqrtF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +501,7 @@ class VRsqF16Vop1 : public Vop1 { public: VRsqF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +510,7 @@ class VLogF16Vop1 : public Vop1 { public: VLogF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +519,7 @@ class VExpF16Vop1 : public Vop1 { public: VExpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +528,7 @@ class VFrexpMantF16Vop1 : public Vop1 { public: VFrexpMantF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +537,7 @@ class VFrexpExpI16F16Vop1 : public Vop1 { public: VFrexpExpI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +546,7 @@ class VFloorF16Vop1 : public Vop1 { public: VFloorF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +555,7 @@ class VCeilF16Vop1 : public Vop1 { public: VCeilF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +564,7 @@ class VTruncF16Vop1 : public Vop1 { public: VTruncF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +573,7 @@ class VRndneF16Vop1 : public Vop1 { public: VRndneF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +582,7 @@ class VFractF16Vop1 : public Vop1 { public: VFractF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +591,7 @@ class VSinF16Vop1 : public Vop1 { public: VSinF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +600,7 @@ class VCosF16Vop1 : public Vop1 { public: VCosF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +609,7 @@ class VCvtNormI16F16Vop1 : public Vop1 { public: VCvtNormI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +618,7 @@ class VCvtNormU16F16Vop1 : public Vop1 { public: VCvtNormU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +627,7 @@ class VSatPkU8I16Vop1 : public Vop1 { public: VSatPkU8I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop2.cpp index 2672220c424a..ddca5b06c5b8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop2.cpp @@ -4160,6 +4160,12 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } } +void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4300,6 +4306,12 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } } +void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4440,6 +4452,12 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } } +void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4580,6 +4598,12 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } } +void VMulF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4721,6 +4745,12 @@ VMacF16Vop2::VMacF16Vop2(const MachineInst *inst) } } +void VMacF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMacF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4867,6 +4897,12 @@ VMadmkF16Vop2::VMadmkF16Vop2(const MachineInst *inst) } } +void VMadmkF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadmkF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5013,6 +5049,12 @@ VMadakF16Vop2::VMadakF16Vop2(const MachineInst *inst) } } +void VMadakF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadakF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5153,6 +5195,12 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) } } +void VAddU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5281,6 +5329,12 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) } } +void VSubU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5409,6 +5463,12 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) } } +void VSubrevU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5537,6 +5597,12 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) } } +void VMulLoU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5665,6 +5731,12 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) } } +void VLshlrevB16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5793,6 +5865,12 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) } } +void VLshrrevB16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5921,6 +5999,12 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) } } +void VAshrrevI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6049,6 +6133,12 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } } +void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6189,6 +6279,12 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } } +void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6329,6 +6425,12 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) } } +void VMaxU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6457,6 +6559,12 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) } } +void VMaxI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6585,6 +6693,12 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) } } +void VMinU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6713,6 +6827,12 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) } } +void VMinI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6841,6 +6961,12 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } } +void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop2.h index fca5806f5377..25d8f2d0ffc8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop2.h @@ -299,6 +299,7 @@ class VAddF16Vop2 : public Vop2 { public: VAddF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -308,6 +309,7 @@ class VSubF16Vop2 : public Vop2 { public: VSubF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -317,6 +319,7 @@ class VSubrevF16Vop2 : public Vop2 { public: VSubrevF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -326,6 +329,7 @@ class VMulF16Vop2 : public Vop2 { public: VMulF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -335,6 +339,7 @@ class VMacF16Vop2 : public Vop2 { public: VMacF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -344,6 +349,7 @@ class VMadmkF16Vop2 : public Vop2 { public: VMadmkF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand simm32; @@ -354,6 +360,7 @@ class VMadakF16Vop2 : public Vop2 { public: VMadakF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -364,6 +371,7 @@ class VAddU16Vop2 : public Vop2 { public: VAddU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -373,6 +381,7 @@ class VSubU16Vop2 : public Vop2 { public: VSubU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -382,6 +391,7 @@ class VSubrevU16Vop2 : public Vop2 { public: VSubrevU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -391,6 +401,7 @@ class VMulLoU16Vop2 : public Vop2 { public: VMulLoU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -400,6 +411,7 @@ class VLshlrevB16Vop2 : public Vop2 { public: VLshlrevB16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -409,6 +421,7 @@ class VLshrrevB16Vop2 : public Vop2 { public: VLshrrevB16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -418,6 +431,7 @@ class VAshrrevI16Vop2 : public Vop2 { public: VAshrrevI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -427,6 +441,7 @@ class VMaxF16Vop2 : public Vop2 { public: VMaxF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -436,6 +451,7 @@ class VMinF16Vop2 : public Vop2 { public: VMinF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -445,6 +461,7 @@ class VMaxU16Vop2 : public Vop2 { public: VMaxU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -454,6 +471,7 @@ class VMaxI16Vop2 : public Vop2 { public: VMaxI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -463,6 +481,7 @@ class VMinU16Vop2 : public Vop2 { public: VMinU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -472,6 +491,7 @@ class VMinI16Vop2 : public Vop2 { public: VMinI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -481,6 +501,7 @@ class VLdexpF16Vop2 : public Vop2 { public: VLdexpF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3.cpp index 1c3754d5aad4..0710a43948d2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3.cpp @@ -163,6 +163,12 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -824,6 +830,12 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -850,6 +862,12 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -876,6 +894,12 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -908,6 +932,12 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -941,6 +971,12 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRcpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rcp_f32_simd(a); }); @@ -988,6 +1024,12 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSqrtF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { @@ -1040,6 +1082,12 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRsqF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rsq_f32_simd(a); }); @@ -1087,6 +1135,12 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLogF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::log_f32_simd(a); }); @@ -1134,6 +1188,12 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VExpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::exp_f32_simd(a); }); @@ -1182,6 +1242,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFrexpMantF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16( @@ -1236,6 +1302,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFrexpExpI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { @@ -1293,6 +1365,12 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFloorF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::floor_simd(a); }); @@ -1340,6 +1418,12 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCeilF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::ceil_simd(a); }); @@ -1388,6 +1472,12 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VTruncF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::trunc_simd(a); }); @@ -1436,6 +1526,12 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRndneF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rndne_simd(a); }); @@ -1484,6 +1580,12 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFractF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return a - util::floor_simd(a); }); @@ -1534,6 +1636,12 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1579,6 +1687,12 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCosF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1625,6 +1739,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtNormI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1656,6 +1776,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtNormU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1687,6 +1813,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSatPkU8I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -2098,6 +2230,12 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2158,6 +2296,12 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2219,6 +2363,12 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubrevF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2279,6 +2429,12 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMulF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2340,6 +2496,12 @@ VMacF16Vop3::VMacF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMacF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMacF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_FMAC_VOP3_TRUE16_FP16( @@ -2403,6 +2565,12 @@ VAddU16Vop3::VAddU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2432,6 +2600,12 @@ VSubU16Vop3::VSubU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2462,6 +2636,12 @@ VSubrevU16Vop3::VSubrevU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubrevU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2492,6 +2672,12 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMulLoU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2523,6 +2709,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLshlrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2549,6 +2741,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLshrrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2575,6 +2773,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAshrrevI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2602,6 +2806,12 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2664,6 +2874,12 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2726,6 +2942,12 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2756,6 +2978,12 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2786,6 +3014,12 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2816,6 +3050,12 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2847,6 +3087,12 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLdexpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -3759,6 +4005,12 @@ VMadLegacyF16Vop3::VMadLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { return a * b + c; }); @@ -3829,6 +4081,12 @@ VMadLegacyU16Vop3::VMadLegacyU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -3861,6 +4119,12 @@ VMadLegacyI16Vop3::VMadLegacyI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -3914,6 +4178,12 @@ VFmaLegacyF16Vop3::VFmaLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFmaLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -3986,6 +4256,12 @@ VDivFixupLegacyF16Vop3::VDivFixupLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VDivFixupLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4168,6 +4444,12 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4240,6 +4522,12 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4284,6 +4572,12 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4325,6 +4619,12 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4397,6 +4697,12 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4441,6 +4747,12 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4482,6 +4794,12 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { @@ -4556,6 +4874,12 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4602,6 +4926,12 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4756,6 +5086,12 @@ VMadF16Vop3::VMadF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { return a * b + c; }); @@ -4825,6 +5161,12 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -4853,6 +5195,12 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -4884,6 +5232,12 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFmaF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4956,6 +5310,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VDivFixupF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -5495,6 +5855,12 @@ VAddI16Vop3::VAddI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -5523,6 +5889,12 @@ VSubI16Vop3::VSubI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3.h index 36d99df8ec8f..aa23b4f2cf80 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop3 : public Vop3 { public: VCvtF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -446,6 +447,7 @@ class VCvtF16U16Vop3 : public Vop3 { public: VCvtF16U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -454,6 +456,7 @@ class VCvtF16I16Vop3 : public Vop3 { public: VCvtF16I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -462,6 +465,7 @@ class VCvtU16F16Vop3 : public Vop3 { public: VCvtU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -470,6 +474,7 @@ class VCvtI16F16Vop3 : public Vop3 { public: VCvtI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +483,7 @@ class VRcpF16Vop3 : public Vop3 { public: VRcpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +492,7 @@ class VSqrtF16Vop3 : public Vop3 { public: VSqrtF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +501,7 @@ class VRsqF16Vop3 : public Vop3 { public: VRsqF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +510,7 @@ class VLogF16Vop3 : public Vop3 { public: VLogF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +519,7 @@ class VExpF16Vop3 : public Vop3 { public: VExpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +528,7 @@ class VFrexpMantF16Vop3 : public Vop3 { public: VFrexpMantF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +537,7 @@ class VFrexpExpI16F16Vop3 : public Vop3 { public: VFrexpExpI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +546,7 @@ class VFloorF16Vop3 : public Vop3 { public: VFloorF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +555,7 @@ class VCeilF16Vop3 : public Vop3 { public: VCeilF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +564,7 @@ class VTruncF16Vop3 : public Vop3 { public: VTruncF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +573,7 @@ class VRndneF16Vop3 : public Vop3 { public: VRndneF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +582,7 @@ class VFractF16Vop3 : public Vop3 { public: VFractF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +591,7 @@ class VSinF16Vop3 : public Vop3 { public: VSinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +600,7 @@ class VCosF16Vop3 : public Vop3 { public: VCosF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +609,7 @@ class VCvtNormI16F16Vop3 : public Vop3 { public: VCvtNormI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +618,7 @@ class VCvtNormU16F16Vop3 : public Vop3 { public: VCvtNormU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +627,7 @@ class VSatPkU8I16Vop3 : public Vop3 { public: VSatPkU8I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -838,6 +860,7 @@ class VAddF16Vop3 : public Vop3 { public: VAddF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -847,6 +870,7 @@ class VSubF16Vop3 : public Vop3 { public: VSubF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -856,6 +880,7 @@ class VSubrevF16Vop3 : public Vop3 { public: VSubrevF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -865,6 +890,7 @@ class VMulF16Vop3 : public Vop3 { public: VMulF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -874,6 +900,7 @@ class VMacF16Vop3 : public Vop3 { public: VMacF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -883,6 +910,7 @@ class VAddU16Vop3 : public Vop3 { public: VAddU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -892,6 +920,7 @@ class VSubU16Vop3 : public Vop3 { public: VSubU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -901,6 +930,7 @@ class VSubrevU16Vop3 : public Vop3 { public: VSubrevU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -910,6 +940,7 @@ class VMulLoU16Vop3 : public Vop3 { public: VMulLoU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -919,6 +950,7 @@ class VLshlrevB16Vop3 : public Vop3 { public: VLshlrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -928,6 +960,7 @@ class VLshrrevB16Vop3 : public Vop3 { public: VLshrrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -937,6 +970,7 @@ class VAshrrevI16Vop3 : public Vop3 { public: VAshrrevI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -946,6 +980,7 @@ class VMaxF16Vop3 : public Vop3 { public: VMaxF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -955,6 +990,7 @@ class VMinF16Vop3 : public Vop3 { public: VMinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -964,6 +1000,7 @@ class VMaxU16Vop3 : public Vop3 { public: VMaxU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -973,6 +1010,7 @@ class VMaxI16Vop3 : public Vop3 { public: VMaxI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -982,6 +1020,7 @@ class VMinU16Vop3 : public Vop3 { public: VMinU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -991,6 +1030,7 @@ class VMinI16Vop3 : public Vop3 { public: VMinI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1000,6 +1040,7 @@ class VLdexpF16Vop3 : public Vop3 { public: VLdexpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1479,6 +1520,7 @@ class VMadLegacyF16Vop3 : public Vop3 { public: VMadLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1489,6 +1531,7 @@ class VMadLegacyU16Vop3 : public Vop3 { public: VMadLegacyU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1499,6 +1542,7 @@ class VMadLegacyI16Vop3 : public Vop3 { public: VMadLegacyI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1519,6 +1563,7 @@ class VFmaLegacyF16Vop3 : public Vop3 { public: VFmaLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1529,6 +1574,7 @@ class VDivFixupLegacyF16Vop3 : public Vop3 { public: VDivFixupLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1578,6 +1624,7 @@ class VMin3F16Vop3 : public Vop3 { public: VMin3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1588,6 +1635,7 @@ class VMin3I16Vop3 : public Vop3 { public: VMin3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1598,6 +1646,7 @@ class VMin3U16Vop3 : public Vop3 { public: VMin3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1608,6 +1657,7 @@ class VMax3F16Vop3 : public Vop3 { public: VMax3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1618,6 +1668,7 @@ class VMax3I16Vop3 : public Vop3 { public: VMax3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1628,6 +1679,7 @@ class VMax3U16Vop3 : public Vop3 { public: VMax3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1638,6 +1690,7 @@ class VMed3F16Vop3 : public Vop3 { public: VMed3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1648,6 +1701,7 @@ class VMed3I16Vop3 : public Vop3 { public: VMed3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1658,6 +1712,7 @@ class VMed3U16Vop3 : public Vop3 { public: VMed3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1728,6 +1783,7 @@ class VMadF16Vop3 : public Vop3 { public: VMadF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1738,6 +1794,7 @@ class VMadU16Vop3 : public Vop3 { public: VMadU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1748,6 +1805,7 @@ class VMadI16Vop3 : public Vop3 { public: VMadI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1758,6 +1816,7 @@ class VFmaF16Vop3 : public Vop3 { public: VFmaF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1768,6 +1827,7 @@ class VDivFixupF16Vop3 : public Vop3 { public: VDivFixupF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2030,6 +2090,7 @@ class VAddI16Vop3 : public Vop3 { public: VAddI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2039,6 +2100,7 @@ class VSubI16Vop3 : public Vop3 { public: VSubI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3p.cpp index ef07bfef495e..e6f71a898cd5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3p.cpp @@ -35,6 +35,12 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMadI16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMadI16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_mad_i16_vop3p(*this, wf); } @@ -52,6 +58,12 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMulLoU16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMulLoU16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_mul_lo_u16_vop3p(*this, wf); } @@ -69,6 +81,12 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkAddI16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkAddI16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_add_i16_vop3p(*this, wf); } @@ -86,6 +104,12 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkSubI16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkSubI16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_sub_i16_vop3p(*this, wf); } @@ -154,6 +178,12 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMaxI16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMaxI16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_max_i16_vop3p(*this, wf); } @@ -171,6 +201,12 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMinI16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMinI16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_min_i16_vop3p(*this, wf); } @@ -190,6 +226,12 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMadU16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMadU16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_mad_u16_vop3p(*this, wf); } @@ -207,6 +249,12 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkAddU16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkAddU16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_add_u16_vop3p(*this, wf); } @@ -224,6 +272,12 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkSubU16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkSubU16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_sub_u16_vop3p(*this, wf); } @@ -241,6 +295,12 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMaxU16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMaxU16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_max_u16_vop3p(*this, wf); } @@ -258,6 +318,12 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMinU16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMinU16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_min_u16_vop3p(*this, wf); } @@ -277,6 +343,12 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkFmaF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkFmaF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_fma_f16_vop3p(*this, wf); } @@ -294,6 +366,12 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkAddF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkAddF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_add_f16_vop3p(*this, wf); } @@ -311,6 +389,12 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMulF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMulF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_mul_f16_vop3p(*this, wf); } @@ -328,6 +412,12 @@ VPkMinF16Vop3p::VPkMinF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMinF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMinF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_min_f16_vop3p(*this, wf); } @@ -345,6 +435,12 @@ VPkMaxF16Vop3p::VPkMaxF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMaxF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMaxF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_max_f16_vop3p(*this, wf); } @@ -384,6 +480,12 @@ VMadMixloF16Vop3p::VMadMixloF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VMadMixloF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadMixloF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_mixlo_f16_vop3p(*this, wf); } @@ -404,6 +506,12 @@ VMadMixhiF16Vop3p::VMadMixhiF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VMadMixhiF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadMixhiF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_mixhi_f16_vop3p(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3p.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3p.h index 4c734b54e8d7..f0c37f6de9c9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3p.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/vop3p.h @@ -18,6 +18,7 @@ class VPkMadI16Vop3p : public Vop3p { public: VPkMadI16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -28,6 +29,7 @@ class VPkMulLoU16Vop3p : public Vop3p { public: VPkMulLoU16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -37,6 +39,7 @@ class VPkAddI16Vop3p : public Vop3p { public: VPkAddI16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -46,6 +49,7 @@ class VPkSubI16Vop3p : public Vop3p { public: VPkSubI16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -82,6 +86,7 @@ class VPkMaxI16Vop3p : public Vop3p { public: VPkMaxI16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -91,6 +96,7 @@ class VPkMinI16Vop3p : public Vop3p { public: VPkMinI16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -100,6 +106,7 @@ class VPkMadU16Vop3p : public Vop3p { public: VPkMadU16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -110,6 +117,7 @@ class VPkAddU16Vop3p : public Vop3p { public: VPkAddU16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -119,6 +127,7 @@ class VPkSubU16Vop3p : public Vop3p { public: VPkSubU16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -128,6 +137,7 @@ class VPkMaxU16Vop3p : public Vop3p { public: VPkMaxU16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -137,6 +147,7 @@ class VPkMinU16Vop3p : public Vop3p { public: VPkMinU16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -146,6 +157,7 @@ class VPkFmaF16Vop3p : public Vop3p { public: VPkFmaF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -156,6 +168,7 @@ class VPkAddF16Vop3p : public Vop3p { public: VPkAddF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -165,6 +178,7 @@ class VPkMulF16Vop3p : public Vop3p { public: VPkMulF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -174,6 +188,7 @@ class VPkMinF16Vop3p : public Vop3p { public: VPkMinF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -183,6 +198,7 @@ class VPkMaxF16Vop3p : public Vop3p { public: VPkMaxF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -202,6 +218,7 @@ class VMadMixloF16Vop3p : public Vop3p { public: VMadMixloF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -212,6 +229,7 @@ class VMadMixhiF16Vop3p : public Vop3p { public: VMadMixhiF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop1.cpp index 333a8cf23ac9..7c2f3ed1a533 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop1.cpp @@ -1119,6 +1119,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } } +void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6885,6 +6891,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } } +void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7006,6 +7018,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } } +void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7127,6 +7145,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } } +void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7248,6 +7272,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } } +void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7369,6 +7399,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } } +void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7502,6 +7538,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } } +void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7635,6 +7677,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } } +void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7768,6 +7816,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } } +void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7901,6 +7955,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } } +void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8034,6 +8094,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } } +void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8167,6 +8233,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } } +void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8300,6 +8372,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } } +void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8433,6 +8511,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } } +void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8566,6 +8650,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } } +void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8699,6 +8789,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } } +void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8832,6 +8928,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } } +void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8965,6 +9067,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } } +void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9098,6 +9206,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } } +void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9231,6 +9345,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } } +void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9364,6 +9484,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } } +void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9497,6 +9623,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } } +void VSatPkU8I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop1.h index da52f267c25f..7cc131c7b0e5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop1.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop1 : public Vop1 { public: VCvtF16F32Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -454,6 +455,7 @@ class VCvtF16U16Vop1 : public Vop1 { public: VCvtF16U16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -462,6 +464,7 @@ class VCvtF16I16Vop1 : public Vop1 { public: VCvtF16I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -470,6 +473,7 @@ class VCvtU16F16Vop1 : public Vop1 { public: VCvtU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +482,7 @@ class VCvtI16F16Vop1 : public Vop1 { public: VCvtI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +491,7 @@ class VRcpF16Vop1 : public Vop1 { public: VRcpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +500,7 @@ class VSqrtF16Vop1 : public Vop1 { public: VSqrtF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +509,7 @@ class VRsqF16Vop1 : public Vop1 { public: VRsqF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +518,7 @@ class VLogF16Vop1 : public Vop1 { public: VLogF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +527,7 @@ class VExpF16Vop1 : public Vop1 { public: VExpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +536,7 @@ class VFrexpMantF16Vop1 : public Vop1 { public: VFrexpMantF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +545,7 @@ class VFrexpExpI16F16Vop1 : public Vop1 { public: VFrexpExpI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +554,7 @@ class VFloorF16Vop1 : public Vop1 { public: VFloorF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +563,7 @@ class VCeilF16Vop1 : public Vop1 { public: VCeilF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +572,7 @@ class VTruncF16Vop1 : public Vop1 { public: VTruncF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +581,7 @@ class VRndneF16Vop1 : public Vop1 { public: VRndneF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +590,7 @@ class VFractF16Vop1 : public Vop1 { public: VFractF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +599,7 @@ class VSinF16Vop1 : public Vop1 { public: VSinF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +608,7 @@ class VCosF16Vop1 : public Vop1 { public: VCosF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +617,7 @@ class VCvtNormI16F16Vop1 : public Vop1 { public: VCvtNormI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +626,7 @@ class VCvtNormU16F16Vop1 : public Vop1 { public: VCvtNormU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +635,7 @@ class VSatPkU8I16Vop1 : public Vop1 { public: VSatPkU8I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop2.cpp index 0cdb6273d287..db2540ec8388 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop2.cpp @@ -4035,6 +4035,12 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } } +void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4175,6 +4181,12 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } } +void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4315,6 +4327,12 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } } +void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4455,6 +4473,12 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } } +void VMulF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4596,6 +4620,12 @@ VMacF16Vop2::VMacF16Vop2(const MachineInst *inst) } } +void VMacF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMacF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4742,6 +4772,12 @@ VMadmkF16Vop2::VMadmkF16Vop2(const MachineInst *inst) } } +void VMadmkF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadmkF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4888,6 +4924,12 @@ VMadakF16Vop2::VMadakF16Vop2(const MachineInst *inst) } } +void VMadakF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadakF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5028,6 +5070,12 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) } } +void VAddU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5156,6 +5204,12 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) } } +void VSubU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5284,6 +5338,12 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) } } +void VSubrevU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5412,6 +5472,12 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) } } +void VMulLoU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5540,6 +5606,12 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) } } +void VLshlrevB16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5668,6 +5740,12 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) } } +void VLshrrevB16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5796,6 +5874,12 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) } } +void VAshrrevI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5924,6 +6008,12 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } } +void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6064,6 +6154,12 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } } +void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6204,6 +6300,12 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) } } +void VMaxU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6332,6 +6434,12 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) } } +void VMaxI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6460,6 +6568,12 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) } } +void VMinU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6588,6 +6702,12 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) } } +void VMinI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6716,6 +6836,12 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } } +void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop2.h index 3bbab2f9446d..ae7eb5ec4d9b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop2.h @@ -290,6 +290,7 @@ class VAddF16Vop2 : public Vop2 { public: VAddF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -299,6 +300,7 @@ class VSubF16Vop2 : public Vop2 { public: VSubF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -308,6 +310,7 @@ class VSubrevF16Vop2 : public Vop2 { public: VSubrevF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -317,6 +320,7 @@ class VMulF16Vop2 : public Vop2 { public: VMulF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -326,6 +330,7 @@ class VMacF16Vop2 : public Vop2 { public: VMacF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -335,6 +340,7 @@ class VMadmkF16Vop2 : public Vop2 { public: VMadmkF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand simm32; @@ -345,6 +351,7 @@ class VMadakF16Vop2 : public Vop2 { public: VMadakF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -355,6 +362,7 @@ class VAddU16Vop2 : public Vop2 { public: VAddU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -364,6 +372,7 @@ class VSubU16Vop2 : public Vop2 { public: VSubU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -373,6 +382,7 @@ class VSubrevU16Vop2 : public Vop2 { public: VSubrevU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -382,6 +392,7 @@ class VMulLoU16Vop2 : public Vop2 { public: VMulLoU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -391,6 +402,7 @@ class VLshlrevB16Vop2 : public Vop2 { public: VLshlrevB16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -400,6 +412,7 @@ class VLshrrevB16Vop2 : public Vop2 { public: VLshrrevB16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -409,6 +422,7 @@ class VAshrrevI16Vop2 : public Vop2 { public: VAshrrevI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -418,6 +432,7 @@ class VMaxF16Vop2 : public Vop2 { public: VMaxF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -427,6 +442,7 @@ class VMinF16Vop2 : public Vop2 { public: VMinF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -436,6 +452,7 @@ class VMaxU16Vop2 : public Vop2 { public: VMaxU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -445,6 +462,7 @@ class VMaxI16Vop2 : public Vop2 { public: VMaxI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -454,6 +472,7 @@ class VMinU16Vop2 : public Vop2 { public: VMinU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -463,6 +482,7 @@ class VMinI16Vop2 : public Vop2 { public: VMinI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -472,6 +492,7 @@ class VLdexpF16Vop2 : public Vop2 { public: VLdexpF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3.cpp index 4004c58a8821..14371eee583b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3.cpp @@ -163,6 +163,12 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -836,6 +842,12 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -862,6 +874,12 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -888,6 +906,12 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -920,6 +944,12 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -953,6 +983,12 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRcpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rcp_f32_simd(a); }); @@ -1000,6 +1036,12 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSqrtF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { @@ -1052,6 +1094,12 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRsqF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rsq_f32_simd(a); }); @@ -1099,6 +1147,12 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLogF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::log_f32_simd(a); }); @@ -1146,6 +1200,12 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VExpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::exp_f32_simd(a); }); @@ -1194,6 +1254,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFrexpMantF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16( @@ -1248,6 +1314,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFrexpExpI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { @@ -1305,6 +1377,12 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFloorF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::floor_simd(a); }); @@ -1352,6 +1430,12 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCeilF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::ceil_simd(a); }); @@ -1400,6 +1484,12 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VTruncF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::trunc_simd(a); }); @@ -1448,6 +1538,12 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRndneF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rndne_simd(a); }); @@ -1496,6 +1592,12 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFractF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return a - util::floor_simd(a); }); @@ -1546,6 +1648,12 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1591,6 +1699,12 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCosF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1637,6 +1751,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtNormI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1668,6 +1788,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtNormU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1699,6 +1825,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSatPkU8I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -2209,6 +2341,12 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2269,6 +2407,12 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2330,6 +2474,12 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubrevF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2390,6 +2540,12 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMulF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2451,6 +2607,12 @@ VMacF16Vop3::VMacF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMacF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMacF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_FMAC_VOP3_TRUE16_FP16( @@ -2514,6 +2676,12 @@ VAddU16Vop3::VAddU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2543,6 +2711,12 @@ VSubU16Vop3::VSubU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2573,6 +2747,12 @@ VSubrevU16Vop3::VSubrevU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubrevU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2603,6 +2783,12 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMulLoU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2634,6 +2820,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLshlrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2660,6 +2852,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLshrrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2686,6 +2884,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAshrrevI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2713,6 +2917,12 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2775,6 +2985,12 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2837,6 +3053,12 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2867,6 +3089,12 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2897,6 +3125,12 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2927,6 +3161,12 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2958,6 +3198,12 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLdexpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -3835,6 +4081,12 @@ VMadLegacyF16Vop3::VMadLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { return a * b + c; }); @@ -3905,6 +4157,12 @@ VMadLegacyU16Vop3::VMadLegacyU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -3937,6 +4195,12 @@ VMadLegacyI16Vop3::VMadLegacyI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -3990,6 +4254,12 @@ VFmaLegacyF16Vop3::VFmaLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFmaLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4062,6 +4332,12 @@ VDivFixupLegacyF16Vop3::VDivFixupLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VDivFixupLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4244,6 +4520,12 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4316,6 +4598,12 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4360,6 +4648,12 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4401,6 +4695,12 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4473,6 +4773,12 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4517,6 +4823,12 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4558,6 +4870,12 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { @@ -4632,6 +4950,12 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4678,6 +5002,12 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4832,6 +5162,12 @@ VMadF16Vop3::VMadF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { return a * b + c; }); @@ -4901,6 +5237,12 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -4929,6 +5271,12 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -4960,6 +5308,12 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFmaF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -5032,6 +5386,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VDivFixupF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -5590,6 +5950,12 @@ VAddI16Vop3::VAddI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -5618,6 +5984,12 @@ VSubI16Vop3::VSubI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -5692,6 +6064,12 @@ VCvtPkFp8F32Vop3::VCvtPkFp8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtPkFp8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtPkFp8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5720,6 +6098,12 @@ VCvtPkBf8F32Vop3::VCvtPkBf8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtPkBf8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtPkBf8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5748,6 +6132,12 @@ VCvtSrFp8F32Vop3::VCvtSrFp8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtSrFp8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrFp8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5777,6 +6167,12 @@ VCvtSrBf8F32Vop3::VCvtSrBf8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtSrBf8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrBf8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3.h index aba23961bdb1..2d7b1e7f56ab 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop3 : public Vop3 { public: VCvtF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -454,6 +455,7 @@ class VCvtF16U16Vop3 : public Vop3 { public: VCvtF16U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -462,6 +464,7 @@ class VCvtF16I16Vop3 : public Vop3 { public: VCvtF16I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -470,6 +473,7 @@ class VCvtU16F16Vop3 : public Vop3 { public: VCvtU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +482,7 @@ class VCvtI16F16Vop3 : public Vop3 { public: VCvtI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +491,7 @@ class VRcpF16Vop3 : public Vop3 { public: VRcpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +500,7 @@ class VSqrtF16Vop3 : public Vop3 { public: VSqrtF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +509,7 @@ class VRsqF16Vop3 : public Vop3 { public: VRsqF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +518,7 @@ class VLogF16Vop3 : public Vop3 { public: VLogF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +527,7 @@ class VExpF16Vop3 : public Vop3 { public: VExpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +536,7 @@ class VFrexpMantF16Vop3 : public Vop3 { public: VFrexpMantF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +545,7 @@ class VFrexpExpI16F16Vop3 : public Vop3 { public: VFrexpExpI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +554,7 @@ class VFloorF16Vop3 : public Vop3 { public: VFloorF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +563,7 @@ class VCeilF16Vop3 : public Vop3 { public: VCeilF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +572,7 @@ class VTruncF16Vop3 : public Vop3 { public: VTruncF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +581,7 @@ class VRndneF16Vop3 : public Vop3 { public: VRndneF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +590,7 @@ class VFractF16Vop3 : public Vop3 { public: VFractF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +599,7 @@ class VSinF16Vop3 : public Vop3 { public: VSinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +608,7 @@ class VCosF16Vop3 : public Vop3 { public: VCosF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +617,7 @@ class VCvtNormI16F16Vop3 : public Vop3 { public: VCvtNormI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +626,7 @@ class VCvtNormU16F16Vop3 : public Vop3 { public: VCvtNormU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +635,7 @@ class VSatPkU8I16Vop3 : public Vop3 { public: VSatPkU8I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -869,6 +891,7 @@ class VAddF16Vop3 : public Vop3 { public: VAddF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -878,6 +901,7 @@ class VSubF16Vop3 : public Vop3 { public: VSubF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -887,6 +911,7 @@ class VSubrevF16Vop3 : public Vop3 { public: VSubrevF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -896,6 +921,7 @@ class VMulF16Vop3 : public Vop3 { public: VMulF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -905,6 +931,7 @@ class VMacF16Vop3 : public Vop3 { public: VMacF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -914,6 +941,7 @@ class VAddU16Vop3 : public Vop3 { public: VAddU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -923,6 +951,7 @@ class VSubU16Vop3 : public Vop3 { public: VSubU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -932,6 +961,7 @@ class VSubrevU16Vop3 : public Vop3 { public: VSubrevU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -941,6 +971,7 @@ class VMulLoU16Vop3 : public Vop3 { public: VMulLoU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -950,6 +981,7 @@ class VLshlrevB16Vop3 : public Vop3 { public: VLshlrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -959,6 +991,7 @@ class VLshrrevB16Vop3 : public Vop3 { public: VLshrrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -968,6 +1001,7 @@ class VAshrrevI16Vop3 : public Vop3 { public: VAshrrevI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -977,6 +1011,7 @@ class VMaxF16Vop3 : public Vop3 { public: VMaxF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -986,6 +1021,7 @@ class VMinF16Vop3 : public Vop3 { public: VMinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -995,6 +1031,7 @@ class VMaxU16Vop3 : public Vop3 { public: VMaxU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1004,6 +1041,7 @@ class VMaxI16Vop3 : public Vop3 { public: VMaxI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1013,6 +1051,7 @@ class VMinU16Vop3 : public Vop3 { public: VMinU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1022,6 +1061,7 @@ class VMinI16Vop3 : public Vop3 { public: VMinI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1031,6 +1071,7 @@ class VLdexpF16Vop3 : public Vop3 { public: VLdexpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1490,6 +1531,7 @@ class VMadLegacyF16Vop3 : public Vop3 { public: VMadLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1500,6 +1542,7 @@ class VMadLegacyU16Vop3 : public Vop3 { public: VMadLegacyU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1510,6 +1553,7 @@ class VMadLegacyI16Vop3 : public Vop3 { public: VMadLegacyI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1530,6 +1574,7 @@ class VFmaLegacyF16Vop3 : public Vop3 { public: VFmaLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1540,6 +1585,7 @@ class VDivFixupLegacyF16Vop3 : public Vop3 { public: VDivFixupLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1589,6 +1635,7 @@ class VMin3F16Vop3 : public Vop3 { public: VMin3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1599,6 +1646,7 @@ class VMin3I16Vop3 : public Vop3 { public: VMin3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1609,6 +1657,7 @@ class VMin3U16Vop3 : public Vop3 { public: VMin3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1619,6 +1668,7 @@ class VMax3F16Vop3 : public Vop3 { public: VMax3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1629,6 +1679,7 @@ class VMax3I16Vop3 : public Vop3 { public: VMax3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1639,6 +1690,7 @@ class VMax3U16Vop3 : public Vop3 { public: VMax3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1649,6 +1701,7 @@ class VMed3F16Vop3 : public Vop3 { public: VMed3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1659,6 +1712,7 @@ class VMed3I16Vop3 : public Vop3 { public: VMed3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1669,6 +1723,7 @@ class VMed3U16Vop3 : public Vop3 { public: VMed3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1739,6 +1794,7 @@ class VMadF16Vop3 : public Vop3 { public: VMadF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1749,6 +1805,7 @@ class VMadU16Vop3 : public Vop3 { public: VMadU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1759,6 +1816,7 @@ class VMadI16Vop3 : public Vop3 { public: VMadI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1769,6 +1827,7 @@ class VFmaF16Vop3 : public Vop3 { public: VFmaF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1779,6 +1838,7 @@ class VDivFixupF16Vop3 : public Vop3 { public: VDivFixupF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2051,6 +2111,7 @@ class VAddI16Vop3 : public Vop3 { public: VAddI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2060,6 +2121,7 @@ class VSubI16Vop3 : public Vop3 { public: VSubI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2087,6 +2149,7 @@ class VCvtPkFp8F32Vop3 : public Vop3 { public: VCvtPkFp8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2096,6 +2159,7 @@ class VCvtPkBf8F32Vop3 : public Vop3 { public: VCvtPkBf8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2105,6 +2169,7 @@ class VCvtSrFp8F32Vop3 : public Vop3 { public: VCvtSrFp8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2114,6 +2179,7 @@ class VCvtSrBf8F32Vop3 : public Vop3 { public: VCvtSrBf8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3p.cpp index a562480d1095..6d6d5da8812b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3p.cpp @@ -35,6 +35,12 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMadI16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMadI16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_mad_i16_vop3p(*this, wf); } @@ -52,6 +58,12 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMulLoU16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMulLoU16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_mul_lo_u16_vop3p(*this, wf); } @@ -154,6 +166,12 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMaxI16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMaxI16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_max_i16_vop3p(*this, wf); } @@ -171,6 +189,12 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMinI16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMinI16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_min_i16_vop3p(*this, wf); } @@ -190,6 +214,12 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMadU16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMadU16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_mad_u16_vop3p(*this, wf); } @@ -241,6 +271,12 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMaxU16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMaxU16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_max_u16_vop3p(*this, wf); } @@ -258,6 +294,12 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMinU16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMinU16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_min_u16_vop3p(*this, wf); } @@ -328,6 +370,12 @@ VPkMinF16Vop3p::VPkMinF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMinF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMinF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_min_f16_vop3p(*this, wf); } @@ -345,6 +393,12 @@ VPkMaxF16Vop3p::VPkMaxF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VPkMaxF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VPkMaxF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_pk_max_f16_vop3p(*this, wf); } @@ -384,6 +438,12 @@ VMadMixloF16Vop3p::VMadMixloF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VMadMixloF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadMixloF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_mixlo_f16_vop3p(*this, wf); } @@ -404,6 +464,12 @@ VMadMixhiF16Vop3p::VMadMixhiF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VMadMixhiF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadMixhiF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_mixhi_f16_vop3p(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3p.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3p.h index cc0131c70b6e..077421abf6d1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3p.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/vop3p.h @@ -18,6 +18,7 @@ class VPkMadI16Vop3p : public Vop3p { public: VPkMadI16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -28,6 +29,7 @@ class VPkMulLoU16Vop3p : public Vop3p { public: VPkMulLoU16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -82,6 +84,7 @@ class VPkMaxI16Vop3p : public Vop3p { public: VPkMaxI16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -91,6 +94,7 @@ class VPkMinI16Vop3p : public Vop3p { public: VPkMinI16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -100,6 +104,7 @@ class VPkMadU16Vop3p : public Vop3p { public: VPkMadU16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -128,6 +133,7 @@ class VPkMaxU16Vop3p : public Vop3p { public: VPkMaxU16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -137,6 +143,7 @@ class VPkMinU16Vop3p : public Vop3p { public: VPkMinU16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -174,6 +181,7 @@ class VPkMinF16Vop3p : public Vop3p { public: VPkMinF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -183,6 +191,7 @@ class VPkMaxF16Vop3p : public Vop3p { public: VPkMaxF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -202,6 +211,7 @@ class VMadMixloF16Vop3p : public Vop3p { public: VMadMixloF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -212,6 +222,7 @@ class VMadMixhiF16Vop3p : public Vop3p { public: VMadMixhiF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/sopk.cpp index 8a7e3cccad48..07d081a45ed8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/sopk.cpp @@ -333,6 +333,12 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregB32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregB32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; @@ -364,6 +370,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregImm32B32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregImm32B32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/sopk.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/sopk.h index 86e4e9390394..6c507e367902 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/sopk.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/sopk.h @@ -162,6 +162,7 @@ class SSetregB32Sopk : public Sopk { public: SSetregB32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; Operand sdst; }; @@ -170,6 +171,7 @@ class SSetregImm32B32Sopk : public Sopk { public: SSetregImm32B32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop1.cpp index 79a5e292e39d..80fbe70a6a73 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop1.cpp @@ -1119,6 +1119,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } } +void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6885,6 +6891,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } } +void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7006,6 +7018,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } } +void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7127,6 +7145,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } } +void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7248,6 +7272,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } } +void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7369,6 +7399,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } } +void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7502,6 +7538,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } } +void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7635,6 +7677,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } } +void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7768,6 +7816,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } } +void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7901,6 +7955,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } } +void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8034,6 +8094,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } } +void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8167,6 +8233,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } } +void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8300,6 +8372,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } } +void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8433,6 +8511,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } } +void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8566,6 +8650,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } } +void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8699,6 +8789,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } } +void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8832,6 +8928,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } } +void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8965,6 +9067,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } } +void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9098,6 +9206,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } } +void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9511,6 +9625,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } } +void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9644,6 +9764,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } } +void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9777,6 +9903,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } } +void VSatPkU8I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop1.h index cecd2a69e58a..5c64efd77a28 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop1.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop1 : public Vop1 { public: VCvtF16F32Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -454,6 +455,7 @@ class VCvtF16U16Vop1 : public Vop1 { public: VCvtF16U16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -462,6 +464,7 @@ class VCvtF16I16Vop1 : public Vop1 { public: VCvtF16I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -470,6 +473,7 @@ class VCvtU16F16Vop1 : public Vop1 { public: VCvtU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +482,7 @@ class VCvtI16F16Vop1 : public Vop1 { public: VCvtI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +491,7 @@ class VRcpF16Vop1 : public Vop1 { public: VRcpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +500,7 @@ class VSqrtF16Vop1 : public Vop1 { public: VSqrtF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +509,7 @@ class VRsqF16Vop1 : public Vop1 { public: VRsqF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +518,7 @@ class VLogF16Vop1 : public Vop1 { public: VLogF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +527,7 @@ class VExpF16Vop1 : public Vop1 { public: VExpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +536,7 @@ class VFrexpMantF16Vop1 : public Vop1 { public: VFrexpMantF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +545,7 @@ class VFrexpExpI16F16Vop1 : public Vop1 { public: VFrexpExpI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +554,7 @@ class VFloorF16Vop1 : public Vop1 { public: VFloorF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +563,7 @@ class VCeilF16Vop1 : public Vop1 { public: VCeilF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +572,7 @@ class VTruncF16Vop1 : public Vop1 { public: VTruncF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +581,7 @@ class VRndneF16Vop1 : public Vop1 { public: VRndneF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +590,7 @@ class VFractF16Vop1 : public Vop1 { public: VFractF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +599,7 @@ class VSinF16Vop1 : public Vop1 { public: VSinF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +608,7 @@ class VCosF16Vop1 : public Vop1 { public: VCosF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +633,7 @@ class VCvtNormI16F16Vop1 : public Vop1 { public: VCvtNormI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -622,6 +642,7 @@ class VCvtNormU16F16Vop1 : public Vop1 { public: VCvtNormU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -630,6 +651,7 @@ class VSatPkU8I16Vop1 : public Vop1 { public: VSatPkU8I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop2.cpp index 38fa67f9224e..e0a57ed82fe3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop2.cpp @@ -4154,6 +4154,12 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } } +void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4294,6 +4300,12 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } } +void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4434,6 +4446,12 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } } +void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4574,6 +4592,12 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } } +void VMulF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4715,6 +4739,12 @@ VMacF16Vop2::VMacF16Vop2(const MachineInst *inst) } } +void VMacF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMacF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4857,6 +4887,12 @@ VMadmkF16Vop2::VMadmkF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VMadmkF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadmkF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5007,6 +5043,12 @@ VMadakF16Vop2::VMadakF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VMadakF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadakF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5155,6 +5197,12 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) } } +void VAddU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5283,6 +5331,12 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) } } +void VSubU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5411,6 +5465,12 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) } } +void VSubrevU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5539,6 +5599,12 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) } } +void VMulLoU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5667,6 +5733,12 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) } } +void VLshlrevB16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5795,6 +5867,12 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) } } +void VLshrrevB16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5923,6 +6001,12 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) } } +void VAshrrevI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6051,6 +6135,12 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } } +void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6191,6 +6281,12 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } } +void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6331,6 +6427,12 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) } } +void VMaxU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6459,6 +6561,12 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) } } +void VMaxI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6587,6 +6695,12 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) } } +void VMinU16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6715,6 +6829,12 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) } } +void VMinI16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6843,6 +6963,12 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } } +void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop2.h index f93f63130973..0d8b5a37d321 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop2.h @@ -299,6 +299,7 @@ class VAddF16Vop2 : public Vop2 { public: VAddF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -308,6 +309,7 @@ class VSubF16Vop2 : public Vop2 { public: VSubF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -317,6 +319,7 @@ class VSubrevF16Vop2 : public Vop2 { public: VSubrevF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -326,6 +329,7 @@ class VMulF16Vop2 : public Vop2 { public: VMulF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -335,6 +339,7 @@ class VMacF16Vop2 : public Vop2 { public: VMacF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -344,6 +349,7 @@ class VMadmkF16Vop2 : public Vop2 { public: VMadmkF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -354,6 +360,7 @@ class VMadakF16Vop2 : public Vop2 { public: VMadakF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -364,6 +371,7 @@ class VAddU16Vop2 : public Vop2 { public: VAddU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -373,6 +381,7 @@ class VSubU16Vop2 : public Vop2 { public: VSubU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -382,6 +391,7 @@ class VSubrevU16Vop2 : public Vop2 { public: VSubrevU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -391,6 +401,7 @@ class VMulLoU16Vop2 : public Vop2 { public: VMulLoU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -400,6 +411,7 @@ class VLshlrevB16Vop2 : public Vop2 { public: VLshlrevB16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -409,6 +421,7 @@ class VLshrrevB16Vop2 : public Vop2 { public: VLshrrevB16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -418,6 +431,7 @@ class VAshrrevI16Vop2 : public Vop2 { public: VAshrrevI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -427,6 +441,7 @@ class VMaxF16Vop2 : public Vop2 { public: VMaxF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -436,6 +451,7 @@ class VMinF16Vop2 : public Vop2 { public: VMinF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -445,6 +461,7 @@ class VMaxU16Vop2 : public Vop2 { public: VMaxU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -454,6 +471,7 @@ class VMaxI16Vop2 : public Vop2 { public: VMaxI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -463,6 +481,7 @@ class VMinU16Vop2 : public Vop2 { public: VMinU16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -472,6 +491,7 @@ class VMinI16Vop2 : public Vop2 { public: VMinI16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -481,6 +501,7 @@ class VLdexpF16Vop2 : public Vop2 { public: VLdexpF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3.cpp index 13c4b88a9134..017a153eb510 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3.cpp @@ -163,6 +163,12 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -836,6 +842,12 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -862,6 +874,12 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtF16I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -888,6 +906,12 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -920,6 +944,12 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -953,6 +983,12 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRcpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rcp_f32_simd(a); }); @@ -1000,6 +1036,12 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSqrtF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { @@ -1052,6 +1094,12 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRsqF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rsq_f32_simd(a); }); @@ -1099,6 +1147,12 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLogF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::log_f32_simd(a); }); @@ -1146,6 +1200,12 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VExpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::exp_f32_simd(a); }); @@ -1194,6 +1254,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFrexpMantF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16( @@ -1248,6 +1314,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFrexpExpI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { @@ -1305,6 +1377,12 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFloorF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::floor_simd(a); }); @@ -1352,6 +1430,12 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCeilF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::ceil_simd(a); }); @@ -1400,6 +1484,12 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VTruncF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::trunc_simd(a); }); @@ -1448,6 +1538,12 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VRndneF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return util::rndne_simd(a); }); @@ -1496,6 +1592,12 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFractF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_UNARY_TRUE16_FP16([](auto a) { return a - util::floor_simd(a); }); @@ -1546,6 +1648,12 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1591,6 +1699,12 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCosF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1719,6 +1833,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtNormI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1750,6 +1870,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtNormU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -1781,6 +1907,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSatPkU8I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -2405,6 +2537,12 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2465,6 +2603,12 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2526,6 +2670,12 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubrevF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2586,6 +2736,12 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMulF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2647,6 +2803,12 @@ VMacF16Vop3::VMacF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMacF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMacF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_FMAC_VOP3_TRUE16_FP16( @@ -2710,6 +2872,12 @@ VAddU16Vop3::VAddU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2739,6 +2907,12 @@ VSubU16Vop3::VSubU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2769,6 +2943,12 @@ VSubrevU16Vop3::VSubrevU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubrevU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2799,6 +2979,12 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMulLoU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -2830,6 +3016,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLshlrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2856,6 +3048,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLshrrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2882,6 +3080,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAshrrevI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -2909,6 +3113,12 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -2971,6 +3181,12 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -3033,6 +3249,12 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -3063,6 +3285,12 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMaxI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -3093,6 +3321,12 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -3123,6 +3357,12 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMinI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -3154,6 +3394,12 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VLdexpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_BINARY_TRUE16_F16(uint32_t, [](auto a, auto b) { @@ -4030,6 +4276,12 @@ VMadLegacyF16Vop3::VMadLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { return a * b + c; }); @@ -4100,6 +4352,12 @@ VMadLegacyU16Vop3::VMadLegacyU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -4132,6 +4390,12 @@ VMadLegacyI16Vop3::VMadLegacyI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadLegacyI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadLegacyI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -4185,6 +4449,12 @@ VFmaLegacyF16Vop3::VFmaLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFmaLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4257,6 +4527,12 @@ VDivFixupLegacyF16Vop3::VDivFixupLegacyF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VDivFixupLegacyF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupLegacyF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4448,6 +4724,12 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4520,6 +4802,12 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4564,6 +4852,12 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMin3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4605,6 +4899,12 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -4677,6 +4977,12 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4721,6 +5027,12 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMax3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4762,6 +5074,12 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { @@ -4836,6 +5154,12 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -4882,6 +5206,12 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMed3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16(uint32_t, [](auto a, auto b, auto c) { @@ -5036,6 +5366,12 @@ VMadF16Vop3::VMadF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16([](auto a, auto b, auto c) { return a * b + c; }); @@ -5105,6 +5441,12 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -5133,6 +5475,12 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VMadI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); uint32_t opsel = ::rocjitsu::amdgpu::vop3_opsel(inst_); @@ -5164,6 +5512,12 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VFmaF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -5236,6 +5590,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VDivFixupF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupF16Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &inst = *this; ROCJITSU_TRY_SIMD_VOP3_TERNARY_TRUE16_FP16( @@ -5335,6 +5695,12 @@ VBitop3B16Vop3::VBitop3B16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VBitop3B16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VBitop3B16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint8_t truth_table = static_cast((inst_.omod << 6) | (inst_.abs << 3) | inst_.neg); uint64_t exec = wf.exec(); @@ -5401,6 +5767,12 @@ VCvtScalef32PkFp8F32Vop3::VCvtScalef32PkFp8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32PkFp8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32PkFp8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5446,6 +5818,12 @@ VCvtScalef32PkBf8F32Vop3::VCvtScalef32PkBf8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32PkBf8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32PkBf8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5491,6 +5869,12 @@ VCvtScalef32SrFp8F32Vop3::VCvtScalef32SrFp8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32SrFp8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32SrFp8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5529,6 +5913,12 @@ VCvtScalef32SrBf8F32Vop3::VCvtScalef32SrBf8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32SrBf8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32SrBf8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5711,6 +6101,12 @@ VCvtScalef32PkFp4F32Vop3::VCvtScalef32PkFp4F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32PkFp4F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32PkFp4F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5754,6 +6150,12 @@ VCvtScalef32SrPkFp4F32Vop3::VCvtScalef32SrPkFp4F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32SrPkFp4F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32SrPkFp4F32Vop3::execute_impl(amdgpu::Wavefront &wf) { auto &cu = wf.cu(); uint32_t vb = wf.vgpr_alloc().base; @@ -5836,6 +6238,12 @@ VCvtScalef32PkFp8F16Vop3::VCvtScalef32PkFp8F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32PkFp8F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32PkFp8F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5879,6 +6287,12 @@ VCvtScalef32PkBf8F16Vop3::VCvtScalef32PkBf8F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32PkBf8F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32PkBf8F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5924,6 +6338,12 @@ VCvtScalef32SrFp8F16Vop3::VCvtScalef32SrFp8F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32SrFp8F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32SrFp8F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -5963,6 +6383,12 @@ VCvtScalef32SrBf8F16Vop3::VCvtScalef32SrBf8F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32SrBf8F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32SrBf8F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -6000,6 +6426,12 @@ VCvtScalef32PkFp8Bf16Vop3::VCvtScalef32PkFp8Bf16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32PkFp8Bf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32PkFp8Bf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -6043,6 +6475,12 @@ VCvtScalef32PkBf8Bf16Vop3::VCvtScalef32PkBf8Bf16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32PkBf8Bf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32PkBf8Bf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -6088,6 +6526,12 @@ VCvtScalef32SrFp8Bf16Vop3::VCvtScalef32SrFp8Bf16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32SrFp8Bf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32SrFp8Bf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -6127,6 +6571,12 @@ VCvtScalef32SrBf8Bf16Vop3::VCvtScalef32SrBf8Bf16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32SrBf8Bf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32SrBf8Bf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -6244,6 +6694,12 @@ VCvtScalef32F16Fp8Vop3::VCvtScalef32F16Fp8Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32F16Fp8Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32F16Fp8Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -6282,6 +6738,12 @@ VCvtScalef32F16Bf8Vop3::VCvtScalef32F16Bf8Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32F16Bf8Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32F16Bf8Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -6320,6 +6782,12 @@ VCvtScalef32PkFp4F16Vop3::VCvtScalef32PkFp4F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32PkFp4F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32PkFp4F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -6361,6 +6829,12 @@ VCvtScalef32PkFp4Bf16Vop3::VCvtScalef32PkFp4Bf16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32PkFp4Bf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32PkFp4Bf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -6404,6 +6878,12 @@ VCvtScalef32SrPkFp4F16Vop3::VCvtScalef32SrPkFp4F16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtScalef32SrPkFp4F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32SrPkFp4F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -6449,6 +6929,12 @@ VCvtScalef32SrPkFp4Bf16Vop3::VCvtScalef32SrPkFp4Bf16Vop3(const MachineInst *inst num_dst_ = 1; } +void VCvtScalef32SrPkFp4Bf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtScalef32SrPkFp4Bf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -9994,6 +10480,12 @@ VAshrPkI8I32Vop3::VAshrPkI8I32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAshrPkI8I32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrPkI8I32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -10031,6 +10523,12 @@ VAshrPkU8I32Vop3::VAshrPkU8I32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAshrPkU8I32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrPkU8I32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -10657,6 +11155,12 @@ VAddI16Vop3::VAddI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VAddI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -10685,6 +11189,12 @@ VSubI16Vop3::VSubI16Vop3(const MachineInst *inst) num_dst_ = 1; } +void VSubI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); @@ -10758,6 +11268,12 @@ VCvtPkFp8F32Vop3::VCvtPkFp8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtPkFp8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtPkFp8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -10785,6 +11301,12 @@ VCvtPkBf8F32Vop3::VCvtPkBf8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtPkBf8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtPkBf8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -10812,6 +11334,12 @@ VCvtSrFp8F32Vop3::VCvtSrFp8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtSrFp8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrFp8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -10840,6 +11368,12 @@ VCvtSrBf8F32Vop3::VCvtSrBf8F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtSrBf8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrBf8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -10868,6 +11402,12 @@ VCvtSrF16F32Vop3::VCvtSrF16F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtSrF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -10891,6 +11431,12 @@ VCvtSrBf16F32Vop3::VCvtSrBf16F32Vop3(const MachineInst *inst) num_dst_ = 1; } +void VCvtSrBf16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrBf16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint64_t exec = wf.exec(); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3.h index 8580f5157ea1..efda9707b1a2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop3 : public Vop3 { public: VCvtF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -454,6 +455,7 @@ class VCvtF16U16Vop3 : public Vop3 { public: VCvtF16U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -462,6 +464,7 @@ class VCvtF16I16Vop3 : public Vop3 { public: VCvtF16I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -470,6 +473,7 @@ class VCvtU16F16Vop3 : public Vop3 { public: VCvtU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +482,7 @@ class VCvtI16F16Vop3 : public Vop3 { public: VCvtI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +491,7 @@ class VRcpF16Vop3 : public Vop3 { public: VRcpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +500,7 @@ class VSqrtF16Vop3 : public Vop3 { public: VSqrtF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +509,7 @@ class VRsqF16Vop3 : public Vop3 { public: VRsqF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +518,7 @@ class VLogF16Vop3 : public Vop3 { public: VLogF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +527,7 @@ class VExpF16Vop3 : public Vop3 { public: VExpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +536,7 @@ class VFrexpMantF16Vop3 : public Vop3 { public: VFrexpMantF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +545,7 @@ class VFrexpExpI16F16Vop3 : public Vop3 { public: VFrexpExpI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +554,7 @@ class VFloorF16Vop3 : public Vop3 { public: VFloorF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +563,7 @@ class VCeilF16Vop3 : public Vop3 { public: VCeilF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +572,7 @@ class VTruncF16Vop3 : public Vop3 { public: VTruncF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +581,7 @@ class VRndneF16Vop3 : public Vop3 { public: VRndneF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +590,7 @@ class VFractF16Vop3 : public Vop3 { public: VFractF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +599,7 @@ class VSinF16Vop3 : public Vop3 { public: VSinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +608,7 @@ class VCosF16Vop3 : public Vop3 { public: VCosF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +633,7 @@ class VCvtNormI16F16Vop3 : public Vop3 { public: VCvtNormI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -622,6 +642,7 @@ class VCvtNormU16F16Vop3 : public Vop3 { public: VCvtNormU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -630,6 +651,7 @@ class VSatPkU8I16Vop3 : public Vop3 { public: VSatPkU8I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -926,6 +948,7 @@ class VAddF16Vop3 : public Vop3 { public: VAddF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -935,6 +958,7 @@ class VSubF16Vop3 : public Vop3 { public: VSubF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -944,6 +968,7 @@ class VSubrevF16Vop3 : public Vop3 { public: VSubrevF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -953,6 +978,7 @@ class VMulF16Vop3 : public Vop3 { public: VMulF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -962,6 +988,7 @@ class VMacF16Vop3 : public Vop3 { public: VMacF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -971,6 +998,7 @@ class VAddU16Vop3 : public Vop3 { public: VAddU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -980,6 +1008,7 @@ class VSubU16Vop3 : public Vop3 { public: VSubU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -989,6 +1018,7 @@ class VSubrevU16Vop3 : public Vop3 { public: VSubrevU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -998,6 +1028,7 @@ class VMulLoU16Vop3 : public Vop3 { public: VMulLoU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1007,6 +1038,7 @@ class VLshlrevB16Vop3 : public Vop3 { public: VLshlrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1016,6 +1048,7 @@ class VLshrrevB16Vop3 : public Vop3 { public: VLshrrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1025,6 +1058,7 @@ class VAshrrevI16Vop3 : public Vop3 { public: VAshrrevI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1034,6 +1068,7 @@ class VMaxF16Vop3 : public Vop3 { public: VMaxF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1043,6 +1078,7 @@ class VMinF16Vop3 : public Vop3 { public: VMinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1052,6 +1088,7 @@ class VMaxU16Vop3 : public Vop3 { public: VMaxU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1061,6 +1098,7 @@ class VMaxI16Vop3 : public Vop3 { public: VMaxI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1070,6 +1108,7 @@ class VMinU16Vop3 : public Vop3 { public: VMinU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1079,6 +1118,7 @@ class VMinI16Vop3 : public Vop3 { public: VMinI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1088,6 +1128,7 @@ class VLdexpF16Vop3 : public Vop3 { public: VLdexpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1547,6 +1588,7 @@ class VMadLegacyF16Vop3 : public Vop3 { public: VMadLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1557,6 +1599,7 @@ class VMadLegacyU16Vop3 : public Vop3 { public: VMadLegacyU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1567,6 +1610,7 @@ class VMadLegacyI16Vop3 : public Vop3 { public: VMadLegacyI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1587,6 +1631,7 @@ class VFmaLegacyF16Vop3 : public Vop3 { public: VFmaLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1597,6 +1642,7 @@ class VDivFixupLegacyF16Vop3 : public Vop3 { public: VDivFixupLegacyF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1646,6 +1692,7 @@ class VMin3F16Vop3 : public Vop3 { public: VMin3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1656,6 +1703,7 @@ class VMin3I16Vop3 : public Vop3 { public: VMin3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1666,6 +1714,7 @@ class VMin3U16Vop3 : public Vop3 { public: VMin3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1676,6 +1725,7 @@ class VMax3F16Vop3 : public Vop3 { public: VMax3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1686,6 +1736,7 @@ class VMax3I16Vop3 : public Vop3 { public: VMax3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1696,6 +1747,7 @@ class VMax3U16Vop3 : public Vop3 { public: VMax3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1706,6 +1758,7 @@ class VMed3F16Vop3 : public Vop3 { public: VMed3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1716,6 +1769,7 @@ class VMed3I16Vop3 : public Vop3 { public: VMed3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1726,6 +1780,7 @@ class VMed3U16Vop3 : public Vop3 { public: VMed3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1796,6 +1851,7 @@ class VMadF16Vop3 : public Vop3 { public: VMadF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1806,6 +1862,7 @@ class VMadU16Vop3 : public Vop3 { public: VMadU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1816,6 +1873,7 @@ class VMadI16Vop3 : public Vop3 { public: VMadI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1826,6 +1884,7 @@ class VFmaF16Vop3 : public Vop3 { public: VFmaF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1836,6 +1895,7 @@ class VDivFixupF16Vop3 : public Vop3 { public: VDivFixupF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1856,6 +1916,7 @@ class VBitop3B16Vop3 : public Vop3 { public: VBitop3B16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1876,6 +1937,7 @@ class VCvtScalef32PkFp8F32Vop3 : public Vop3 { public: VCvtScalef32PkFp8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1886,6 +1948,7 @@ class VCvtScalef32PkBf8F32Vop3 : public Vop3 { public: VCvtScalef32PkBf8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1896,6 +1959,7 @@ class VCvtScalef32SrFp8F32Vop3 : public Vop3 { public: VCvtScalef32SrFp8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1906,6 +1970,7 @@ class VCvtScalef32SrBf8F32Vop3 : public Vop3 { public: VCvtScalef32SrBf8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1952,6 +2017,7 @@ class VCvtScalef32PkFp4F32Vop3 : public Vop3 { public: VCvtScalef32PkFp4F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1962,6 +2028,7 @@ class VCvtScalef32SrPkFp4F32Vop3 : public Vop3 { public: VCvtScalef32SrPkFp4F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1981,6 +2048,7 @@ class VCvtScalef32PkFp8F16Vop3 : public Vop3 { public: VCvtScalef32PkFp8F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1990,6 +2058,7 @@ class VCvtScalef32PkBf8F16Vop3 : public Vop3 { public: VCvtScalef32PkBf8F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1999,6 +2068,7 @@ class VCvtScalef32SrFp8F16Vop3 : public Vop3 { public: VCvtScalef32SrFp8F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2009,6 +2079,7 @@ class VCvtScalef32SrBf8F16Vop3 : public Vop3 { public: VCvtScalef32SrBf8F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2019,6 +2090,7 @@ class VCvtScalef32PkFp8Bf16Vop3 : public Vop3 { public: VCvtScalef32PkFp8Bf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2028,6 +2100,7 @@ class VCvtScalef32PkBf8Bf16Vop3 : public Vop3 { public: VCvtScalef32PkBf8Bf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2037,6 +2110,7 @@ class VCvtScalef32SrFp8Bf16Vop3 : public Vop3 { public: VCvtScalef32SrFp8Bf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2047,6 +2121,7 @@ class VCvtScalef32SrBf8Bf16Vop3 : public Vop3 { public: VCvtScalef32SrBf8Bf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2075,6 +2150,7 @@ class VCvtScalef32F16Fp8Vop3 : public Vop3 { public: VCvtScalef32F16Fp8Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2084,6 +2160,7 @@ class VCvtScalef32F16Bf8Vop3 : public Vop3 { public: VCvtScalef32F16Bf8Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2093,6 +2170,7 @@ class VCvtScalef32PkFp4F16Vop3 : public Vop3 { public: VCvtScalef32PkFp4F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2102,6 +2180,7 @@ class VCvtScalef32PkFp4Bf16Vop3 : public Vop3 { public: VCvtScalef32PkFp4Bf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2111,6 +2190,7 @@ class VCvtScalef32SrPkFp4F16Vop3 : public Vop3 { public: VCvtScalef32SrPkFp4F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2121,6 +2201,7 @@ class VCvtScalef32SrPkFp4Bf16Vop3 : public Vop3 { public: VCvtScalef32SrPkFp4Bf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2319,6 +2400,7 @@ class VAshrPkI8I32Vop3 : public Vop3 { public: VAshrPkI8I32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2329,6 +2411,7 @@ class VAshrPkU8I32Vop3 : public Vop3 { public: VAshrPkU8I32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2627,6 +2710,7 @@ class VAddI16Vop3 : public Vop3 { public: VAddI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2636,6 +2720,7 @@ class VSubI16Vop3 : public Vop3 { public: VSubI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2663,6 +2748,7 @@ class VCvtPkFp8F32Vop3 : public Vop3 { public: VCvtPkFp8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2672,6 +2758,7 @@ class VCvtPkBf8F32Vop3 : public Vop3 { public: VCvtPkBf8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2681,6 +2768,7 @@ class VCvtSrFp8F32Vop3 : public Vop3 { public: VCvtSrFp8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2690,6 +2778,7 @@ class VCvtSrBf8F32Vop3 : public Vop3 { public: VCvtSrBf8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2699,6 +2788,7 @@ class VCvtSrF16F32Vop3 : public Vop3 { public: VCvtSrF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2708,6 +2798,7 @@ class VCvtSrBf16F32Vop3 : public Vop3 { public: VCvtSrBf16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3p.cpp index 7b42cf6c742e..7bc8187f7ef3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3p.cpp @@ -537,6 +537,12 @@ VMadMixloF16Vop3p::VMadMixloF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VMadMixloF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadMixloF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_mixlo_f16_vop3p(*this, wf); } @@ -557,6 +563,12 @@ VMadMixhiF16Vop3p::VMadMixhiF16Vop3p(const MachineInst *inst) num_dst_ = 1; } +void VMadMixhiF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadMixhiF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_mixhi_f16_vop3p(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3p.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3p.h index d9611df174d1..1a67e17b339f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3p.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/vop3p.h @@ -233,6 +233,7 @@ class VMadMixloF16Vop3p : public Vop3p { public: VMadMixloF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -243,6 +244,7 @@ class VMadMixhiF16Vop3p : public Vop3p { public: VMadMixhiF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop1.cpp index 097a93023661..80376d59c9d8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop1.cpp @@ -2169,6 +2169,12 @@ SCvtF16F32Sop1::SCvtF16F32Sop1(const MachineInst *inst) } } +void SCvtF16F32Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SCvtF16F32Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_cvt_f16_f32_sop1(*this, wf); } @@ -2246,6 +2252,12 @@ SCeilF16Sop1::SCeilF16Sop1(const MachineInst *inst) } } +void SCeilF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SCeilF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_ceil_f16_sop1(*this, wf); } @@ -2272,6 +2284,12 @@ SFloorF16Sop1::SFloorF16Sop1(const MachineInst *inst) } } +void SFloorF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SFloorF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_floor_f16_sop1(*this, wf); } @@ -2298,6 +2316,12 @@ STruncF16Sop1::STruncF16Sop1(const MachineInst *inst) } } +void STruncF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void STruncF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_trunc_f16_sop1(*this, wf); } @@ -2324,6 +2348,12 @@ SRndneF16Sop1::SRndneF16Sop1(const MachineInst *inst) } } +void SRndneF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SRndneF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_rndne_f16_sop1(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop1.h index a38a45e14f2f..11830ef4e68a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop1.h @@ -670,6 +670,7 @@ class SCvtF16F32Sop1 : public Sop1 { public: SCvtF16F32Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -694,6 +695,7 @@ class SCeilF16Sop1 : public Sop1 { public: SCeilF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -702,6 +704,7 @@ class SFloorF16Sop1 : public Sop1 { public: SFloorF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -710,6 +713,7 @@ class STruncF16Sop1 : public Sop1 { public: STruncF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -718,6 +722,7 @@ class SRndneF16Sop1 : public Sop1 { public: SRndneF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop2.cpp index ab00123a854c..e93e7271a836 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop2.cpp @@ -2386,6 +2386,12 @@ SAddF16Sop2::SAddF16Sop2(const MachineInst *inst) } } +void SAddF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SAddF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_add_f16_sop2(*this, wf); } SSubF16Sop2::SSubF16Sop2(const MachineInst *inst) @@ -2422,6 +2428,12 @@ SSubF16Sop2::SSubF16Sop2(const MachineInst *inst) } } +void SSubF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SSubF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_sub_f16_sop2(*this, wf); } SMinNumF16Sop2::SMinNumF16Sop2(const MachineInst *inst) @@ -2459,6 +2471,12 @@ SMinNumF16Sop2::SMinNumF16Sop2(const MachineInst *inst) } } +void SMinNumF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMinNumF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_min_num_f16_sop2(*this, wf); } @@ -2498,6 +2516,12 @@ SMaxNumF16Sop2::SMaxNumF16Sop2(const MachineInst *inst) } } +void SMaxNumF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMaxNumF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_max_num_f16_sop2(*this, wf); } @@ -2536,6 +2560,12 @@ SMulF16Sop2::SMulF16Sop2(const MachineInst *inst) } } +void SMulF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMulF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_mul_f16_sop2(*this, wf); } SFmacF16Sop2::SFmacF16Sop2(const MachineInst *inst) @@ -2573,6 +2603,12 @@ SFmacF16Sop2::SFmacF16Sop2(const MachineInst *inst) } } +void SFmacF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SFmacF16Sop2::execute_impl(amdgpu::Wavefront &wf) { float result = std::fma(util::f16_to_f32(static_cast(ssrc0.read_scalar(wf))), util::f16_to_f32(static_cast(ssrc1.read_scalar(wf))), @@ -2693,6 +2729,12 @@ SMinimumF16Sop2::SMinimumF16Sop2(const MachineInst *inst) } } +void SMinimumF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMinimumF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_minimum_f16_sop2(*this, wf); } @@ -2732,6 +2774,12 @@ SMaximumF16Sop2::SMaximumF16Sop2(const MachineInst *inst) } } +void SMaximumF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMaximumF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_maximum_f16_sop2(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop2.h index b02cc7327070..4749a902bcde 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sop2.h @@ -571,6 +571,7 @@ class SAddF16Sop2 : public Sop2 { public: SAddF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -580,6 +581,7 @@ class SSubF16Sop2 : public Sop2 { public: SSubF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -589,6 +591,7 @@ class SMinNumF16Sop2 : public Sop2 { public: SMinNumF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -598,6 +601,7 @@ class SMaxNumF16Sop2 : public Sop2 { public: SMaxNumF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -607,6 +611,7 @@ class SMulF16Sop2 : public Sop2 { public: SMulF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -616,6 +621,7 @@ class SFmacF16Sop2 : public Sop2 { public: SFmacF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -643,6 +649,7 @@ class SMinimumF16Sop2 : public Sop2 { public: SMinimumF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -652,6 +659,7 @@ class SMaximumF16Sop2 : public Sop2 { public: SMaximumF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sopk.cpp index 9179ce7cdc9b..7804ee25c2a3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sopk.cpp @@ -197,6 +197,12 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregB32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregB32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; @@ -221,6 +227,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregImm32B32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregImm32B32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sopk.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sopk.h index fc4536d1a148..cbbccac6b7e5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sopk.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/sopk.h @@ -65,6 +65,7 @@ class SSetregB32Sopk : public Sopk { public: SSetregB32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; Operand sdst; }; @@ -73,6 +74,7 @@ class SSetregImm32B32Sopk : public Sopk { public: SSetregImm32B32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; Operand literal; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop1.cpp index c4757579350a..647f7249c0e5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop1.cpp @@ -1163,6 +1163,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -3468,6 +3474,12 @@ VMovB16Vop1::VMovB16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VMovB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMovB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -3885,6 +3897,12 @@ VTanhF16Vop1::VTanhF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VTanhF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTanhF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8068,6 +8086,12 @@ VTanhBf16Vop1::VTanhBf16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VTanhBf16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTanhBf16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8334,6 +8358,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8473,6 +8503,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8612,6 +8648,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8757,6 +8799,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8904,6 +8952,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9056,6 +9110,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9208,6 +9268,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9360,6 +9426,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9512,6 +9584,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9664,6 +9742,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9819,6 +9903,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9975,6 +10065,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10126,6 +10222,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10277,6 +10379,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10428,6 +10536,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10579,6 +10693,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10732,6 +10852,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10884,6 +11010,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -11035,6 +11167,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSatPkU8I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -11082,6 +11220,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -11238,6 +11382,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -11526,6 +11676,14 @@ VSwapB16Vop1::VSwapB16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); } +void VSwapB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); + if (auto r = src0.to_register_ref()) + uses.expand(*r); +} + void VSwapB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -11705,6 +11863,12 @@ VNotB16Vop1::VNotB16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VNotB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VNotB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -12777,6 +12941,12 @@ VSatPk4I4I8Vop1::VSatPk4I4I8Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSatPk4I4I8Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPk4I4I8Vop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -12823,6 +12993,12 @@ VSatPk4U4U8Vop1::VSatPk4U4U8Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSatPk4U4U8Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPk4U4U8Vop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -13147,6 +13323,12 @@ VCvtF16Fp8Vop1::VCvtF16Fp8Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtF16Fp8Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16Fp8Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -13298,6 +13480,12 @@ VCvtF16Bf8Vop1::VCvtF16Bf8Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtF16Bf8Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16Bf8Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -13450,6 +13638,12 @@ VRcpBf16Vop1::VRcpBf16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VRcpBf16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpBf16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -13590,6 +13784,12 @@ VSqrtBf16Vop1::VSqrtBf16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSqrtBf16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtBf16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -13730,6 +13930,12 @@ VRsqBf16Vop1::VRsqBf16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VRsqBf16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqBf16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -13870,6 +14076,12 @@ VLogBf16Vop1::VLogBf16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VLogBf16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogBf16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -14010,6 +14222,12 @@ VExpBf16Vop1::VExpBf16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VExpBf16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpBf16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -14150,6 +14368,12 @@ VSinBf16Vop1::VSinBf16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSinBf16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinBf16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -14290,6 +14514,12 @@ VCosBf16Vop1::VCosBf16Vop1(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCosBf16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosBf16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop1.h index de62f051aebd..25d2dbaca917 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop1.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop1 : public Vop1 { public: VCvtF16F32Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -230,6 +231,7 @@ class VMovB16Vop1 : public Vop1 { public: VMovB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -254,6 +256,7 @@ class VTanhF16Vop1 : public Vop1 { public: VTanhF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +513,7 @@ class VTanhBf16Vop1 : public Vop1 { public: VTanhBf16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +530,7 @@ class VCvtF16U16Vop1 : public Vop1 { public: VCvtF16U16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +539,7 @@ class VCvtF16I16Vop1 : public Vop1 { public: VCvtF16I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +548,7 @@ class VCvtU16F16Vop1 : public Vop1 { public: VCvtU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +557,7 @@ class VCvtI16F16Vop1 : public Vop1 { public: VCvtI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +566,7 @@ class VRcpF16Vop1 : public Vop1 { public: VRcpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +575,7 @@ class VSqrtF16Vop1 : public Vop1 { public: VSqrtF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +584,7 @@ class VRsqF16Vop1 : public Vop1 { public: VRsqF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +593,7 @@ class VLogF16Vop1 : public Vop1 { public: VLogF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +602,7 @@ class VExpF16Vop1 : public Vop1 { public: VExpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +611,7 @@ class VFrexpMantF16Vop1 : public Vop1 { public: VFrexpMantF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +620,7 @@ class VFrexpExpI16F16Vop1 : public Vop1 { public: VFrexpExpI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +629,7 @@ class VFloorF16Vop1 : public Vop1 { public: VFloorF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -622,6 +638,7 @@ class VCeilF16Vop1 : public Vop1 { public: VCeilF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -630,6 +647,7 @@ class VTruncF16Vop1 : public Vop1 { public: VTruncF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -638,6 +656,7 @@ class VRndneF16Vop1 : public Vop1 { public: VRndneF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -646,6 +665,7 @@ class VFractF16Vop1 : public Vop1 { public: VFractF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -654,6 +674,7 @@ class VSinF16Vop1 : public Vop1 { public: VSinF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -662,6 +683,7 @@ class VCosF16Vop1 : public Vop1 { public: VCosF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -670,6 +692,7 @@ class VSatPkU8I16Vop1 : public Vop1 { public: VSatPkU8I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -678,6 +701,7 @@ class VCvtNormI16F16Vop1 : public Vop1 { public: VCvtNormI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -686,6 +710,7 @@ class VCvtNormU16F16Vop1 : public Vop1 { public: VCvtNormU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -702,6 +727,7 @@ class VSwapB16Vop1 : public Vop1 { public: VSwapB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -718,6 +744,7 @@ class VNotB16Vop1 : public Vop1 { public: VNotB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -782,6 +809,7 @@ class VSatPk4I4I8Vop1 : public Vop1 { public: VSatPk4I4I8Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -790,6 +818,7 @@ class VSatPk4U4U8Vop1 : public Vop1 { public: VSatPk4U4U8Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -814,6 +843,7 @@ class VCvtF16Fp8Vop1 : public Vop1 { public: VCvtF16Fp8Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -822,6 +852,7 @@ class VCvtF16Bf8Vop1 : public Vop1 { public: VCvtF16Bf8Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -830,6 +861,7 @@ class VRcpBf16Vop1 : public Vop1 { public: VRcpBf16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -838,6 +870,7 @@ class VSqrtBf16Vop1 : public Vop1 { public: VSqrtBf16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -846,6 +879,7 @@ class VRsqBf16Vop1 : public Vop1 { public: VRsqBf16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -854,6 +888,7 @@ class VLogBf16Vop1 : public Vop1 { public: VLogBf16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -862,6 +897,7 @@ class VExpBf16Vop1 : public Vop1 { public: VExpBf16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -870,6 +906,7 @@ class VSinBf16Vop1 : public Vop1 { public: VSinBf16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -878,6 +915,7 @@ class VCosBf16Vop1 : public Vop1 { public: VCosBf16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop2.cpp index cdbf0eed4795..595155606e2e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop2.cpp @@ -5939,6 +5939,12 @@ VMinNumF16Vop2::VMinNumF16Vop2(const MachineInst *inst) vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMinNumF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinNumF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6098,6 +6104,12 @@ VMaxNumF16Vop2::VMaxNumF16Vop2(const MachineInst *inst) vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMaxNumF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxNumF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6257,6 +6269,12 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6416,6 +6434,12 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6575,6 +6599,12 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6734,6 +6764,12 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMulF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6895,6 +6931,12 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VFmacF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7064,6 +7106,12 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VFmamkF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmamkF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7224,6 +7272,12 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VFmaakF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaakF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7378,6 +7432,12 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop2.h index fa7ba69d880f..b571ba2b9887 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop2.h @@ -418,6 +418,7 @@ class VMinNumF16Vop2 : public Vop2 { public: VMinNumF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -427,6 +428,7 @@ class VMaxNumF16Vop2 : public Vop2 { public: VMaxNumF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -436,6 +438,7 @@ class VAddF16Vop2 : public Vop2 { public: VAddF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -445,6 +448,7 @@ class VSubF16Vop2 : public Vop2 { public: VSubF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -454,6 +458,7 @@ class VSubrevF16Vop2 : public Vop2 { public: VSubrevF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -463,6 +468,7 @@ class VMulF16Vop2 : public Vop2 { public: VMulF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -472,6 +478,7 @@ class VFmacF16Vop2 : public Vop2 { public: VFmacF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -481,6 +488,7 @@ class VFmamkF16Vop2 : public Vop2 { public: VFmamkF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand literal; @@ -491,6 +499,7 @@ class VFmaakF16Vop2 : public Vop2 { public: VFmaakF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -501,6 +510,7 @@ class VLdexpF16Vop2 : public Vop2 { public: VLdexpF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3.h index 3bfc261a0ff9..365fcd0dea2b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop3 : public Vop3 { public: VCvtF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -230,6 +231,7 @@ class VMovB16Vop3 : public Vop3 { public: VMovB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -254,6 +256,7 @@ class VTanhF16Vop3 : public Vop3 { public: VTanhF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +513,7 @@ class VTanhBf16Vop3 : public Vop3 { public: VTanhBf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +530,7 @@ class VCvtF16U16Vop3 : public Vop3 { public: VCvtF16U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +539,7 @@ class VCvtF16I16Vop3 : public Vop3 { public: VCvtF16I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +548,7 @@ class VCvtU16F16Vop3 : public Vop3 { public: VCvtU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +557,7 @@ class VCvtI16F16Vop3 : public Vop3 { public: VCvtI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +566,7 @@ class VRcpF16Vop3 : public Vop3 { public: VRcpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +575,7 @@ class VSqrtF16Vop3 : public Vop3 { public: VSqrtF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +584,7 @@ class VRsqF16Vop3 : public Vop3 { public: VRsqF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +593,7 @@ class VLogF16Vop3 : public Vop3 { public: VLogF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +602,7 @@ class VExpF16Vop3 : public Vop3 { public: VExpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +611,7 @@ class VFrexpMantF16Vop3 : public Vop3 { public: VFrexpMantF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +620,7 @@ class VFrexpExpI16F16Vop3 : public Vop3 { public: VFrexpExpI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +629,7 @@ class VFloorF16Vop3 : public Vop3 { public: VFloorF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -622,6 +638,7 @@ class VCeilF16Vop3 : public Vop3 { public: VCeilF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -630,6 +647,7 @@ class VTruncF16Vop3 : public Vop3 { public: VTruncF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -638,6 +656,7 @@ class VRndneF16Vop3 : public Vop3 { public: VRndneF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -646,6 +665,7 @@ class VFractF16Vop3 : public Vop3 { public: VFractF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -654,6 +674,7 @@ class VSinF16Vop3 : public Vop3 { public: VSinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -662,6 +683,7 @@ class VCosF16Vop3 : public Vop3 { public: VCosF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -670,6 +692,7 @@ class VSatPkU8I16Vop3 : public Vop3 { public: VSatPkU8I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -678,6 +701,7 @@ class VCvtNormI16F16Vop3 : public Vop3 { public: VCvtNormI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -686,6 +710,7 @@ class VCvtNormU16F16Vop3 : public Vop3 { public: VCvtNormU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -694,6 +719,7 @@ class VNotB16Vop3 : public Vop3 { public: VNotB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -758,6 +784,7 @@ class VSatPk4I4I8Vop3 : public Vop3 { public: VSatPk4I4I8Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -766,6 +793,7 @@ class VSatPk4U4U8Vop3 : public Vop3 { public: VSatPk4U4U8Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -790,6 +818,7 @@ class VCvtF16Fp8Vop3 : public Vop3 { public: VCvtF16Fp8Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -798,6 +827,7 @@ class VCvtF16Bf8Vop3 : public Vop3 { public: VCvtF16Bf8Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -806,6 +836,7 @@ class VRcpBf16Vop3 : public Vop3 { public: VRcpBf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -814,6 +845,7 @@ class VSqrtBf16Vop3 : public Vop3 { public: VSqrtBf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -822,6 +854,7 @@ class VRsqBf16Vop3 : public Vop3 { public: VRsqBf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -830,6 +863,7 @@ class VLogBf16Vop3 : public Vop3 { public: VLogBf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -838,6 +872,7 @@ class VExpBf16Vop3 : public Vop3 { public: VExpBf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -846,6 +881,7 @@ class VSinBf16Vop3 : public Vop3 { public: VSinBf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -854,6 +890,7 @@ class VCosBf16Vop3 : public Vop3 { public: VCosBf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -1196,6 +1233,7 @@ class VMinNumF16Vop3 : public Vop3 { public: VMinNumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1205,6 +1243,7 @@ class VMaxNumF16Vop3 : public Vop3 { public: VMaxNumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1214,6 +1253,7 @@ class VAddF16Vop3 : public Vop3 { public: VAddF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1223,6 +1263,7 @@ class VSubF16Vop3 : public Vop3 { public: VSubF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1232,6 +1273,7 @@ class VSubrevF16Vop3 : public Vop3 { public: VSubrevF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1241,6 +1283,7 @@ class VMulF16Vop3 : public Vop3 { public: VMulF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1250,6 +1293,7 @@ class VFmacF16Vop3 : public Vop3 { public: VFmacF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1259,6 +1303,7 @@ class VLdexpF16Vop3 : public Vop3 { public: VLdexpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1578,6 +1623,7 @@ class VMin3NumF16Vop3 : public Vop3 { public: VMin3NumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1588,6 +1634,7 @@ class VMax3NumF16Vop3 : public Vop3 { public: VMax3NumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1618,6 +1665,7 @@ class VMinimum3F16Vop3 : public Vop3 { public: VMinimum3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1628,6 +1676,7 @@ class VMaximum3F16Vop3 : public Vop3 { public: VMaximum3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1648,6 +1697,7 @@ class VMed3NumF16Vop3 : public Vop3 { public: VMed3NumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1658,6 +1708,7 @@ class VBitop3B16Vop3 : public Vop3 { public: VBitop3B16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1768,6 +1819,7 @@ class VMadU16Vop3 : public Vop3 { public: VMadU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1838,6 +1890,7 @@ class VFmaF16Vop3 : public Vop3 { public: VFmaF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1848,6 +1901,7 @@ class VMin3I16Vop3 : public Vop3 { public: VMin3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1858,6 +1912,7 @@ class VMin3U16Vop3 : public Vop3 { public: VMin3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1868,6 +1923,7 @@ class VMax3I16Vop3 : public Vop3 { public: VMax3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1878,6 +1934,7 @@ class VMax3U16Vop3 : public Vop3 { public: VMax3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1888,6 +1945,7 @@ class VMed3I16Vop3 : public Vop3 { public: VMed3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1898,6 +1956,7 @@ class VMed3U16Vop3 : public Vop3 { public: VMed3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1918,6 +1977,7 @@ class VMadI16Vop3 : public Vop3 { public: VMadI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1928,6 +1988,7 @@ class VDivFixupF16Vop3 : public Vop3 { public: VDivFixupF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2018,6 +2079,7 @@ class VCndmaskB16Vop3 : public Vop3 { public: VCndmaskB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2128,6 +2190,7 @@ class VMinmaxNumF16Vop3 : public Vop3 { public: VMinmaxNumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2138,6 +2201,7 @@ class VMaxminNumF16Vop3 : public Vop3 { public: VMaxminNumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2168,6 +2232,7 @@ class VMinimummaximumF16Vop3 : public Vop3 { public: VMinimummaximumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2178,6 +2243,7 @@ class VMaximumminimumF16Vop3 : public Vop3 { public: VMaximumminimumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2308,6 +2374,7 @@ class VAshrPkI8I32Vop3 : public Vop3 { public: VAshrPkI8I32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2318,6 +2385,7 @@ class VAshrPkU8I32Vop3 : public Vop3 { public: VAshrPkU8I32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2768,6 +2836,7 @@ class VAddNcU16Vop3 : public Vop3 { public: VAddNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2777,6 +2846,7 @@ class VSubNcU16Vop3 : public Vop3 { public: VSubNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2786,6 +2856,7 @@ class VMulLoU16Vop3 : public Vop3 { public: VMulLoU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2813,6 +2884,7 @@ class VMaxU16Vop3 : public Vop3 { public: VMaxU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2822,6 +2894,7 @@ class VMaxI16Vop3 : public Vop3 { public: VMaxI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2831,6 +2904,7 @@ class VMinU16Vop3 : public Vop3 { public: VMinU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2840,6 +2914,7 @@ class VMinI16Vop3 : public Vop3 { public: VMinI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2849,6 +2924,7 @@ class VAddNcI16Vop3 : public Vop3 { public: VAddNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2858,6 +2934,7 @@ class VSubNcI16Vop3 : public Vop3 { public: VSubNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3101,6 +3178,7 @@ class VLshlrevB16Vop3 : public Vop3 { public: VLshlrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3110,6 +3188,7 @@ class VLshrrevB16Vop3 : public Vop3 { public: VLshrrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3119,6 +3198,7 @@ class VAshrrevI16Vop3 : public Vop3 { public: VAshrrevI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3182,6 +3262,7 @@ class VAndB16Vop3 : public Vop3 { public: VAndB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3191,6 +3272,7 @@ class VOrB16Vop3 : public Vop3 { public: VOrB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3200,6 +3282,7 @@ class VXorB16Vop3 : public Vop3 { public: VXorB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3227,6 +3310,7 @@ class VMinimumF16Vop3 : public Vop3 { public: VMinimumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3236,6 +3320,7 @@ class VMaximumF16Vop3 : public Vop3 { public: VMaximumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3245,6 +3330,7 @@ class VCvtPkFp8F32Vop3 : public Vop3 { public: VCvtPkFp8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3254,6 +3340,7 @@ class VCvtPkBf8F32Vop3 : public Vop3 { public: VCvtPkBf8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3263,6 +3350,7 @@ class VCvtSrFp8F32Vop3 : public Vop3 { public: VCvtSrFp8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3272,6 +3360,7 @@ class VCvtSrBf8F32Vop3 : public Vop3 { public: VCvtSrBf8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3319,6 +3408,7 @@ class VCvtPkFp8F16Vop3 : public Vop3 { public: VCvtPkFp8F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -3327,6 +3417,7 @@ class VCvtPkBf8F16Vop3 : public Vop3 { public: VCvtPkBf8F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -3335,6 +3426,7 @@ class VCvtSrFp8F16Vop3 : public Vop3 { public: VCvtSrFp8F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -3344,6 +3436,7 @@ class VCvtSrBf8F16Vop3 : public Vop3 { public: VCvtSrBf8F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_alu.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_alu.cpp index 5278ae26d3b5..a702b352c2c6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_alu.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_alu.cpp @@ -450,6 +450,12 @@ VTanhF16Vop3::VTanhF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VTanhF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTanhF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2147,6 +2153,12 @@ VTanhBf16Vop3::VTanhBf16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VTanhBf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTanhBf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2250,6 +2262,12 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VRcpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2357,6 +2375,12 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSqrtF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2469,6 +2493,12 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VRsqF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2576,6 +2606,12 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VLogF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2683,6 +2719,12 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VExpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2791,6 +2833,12 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VFloorF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2898,6 +2946,12 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCeilF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3006,6 +3060,12 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VTruncF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3114,6 +3174,12 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VRndneF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3222,6 +3288,12 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VFractF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3332,6 +3404,12 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3435,6 +3513,12 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCosF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3538,6 +3622,12 @@ VNotB16Vop3::VNotB16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VNotB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VNotB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3621,6 +3711,12 @@ VRcpBf16Vop3::VRcpBf16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VRcpBf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpBf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3725,6 +3821,12 @@ VSqrtBf16Vop3::VSqrtBf16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSqrtBf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtBf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3828,6 +3930,12 @@ VRsqBf16Vop3::VRsqBf16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VRsqBf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqBf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3931,6 +4039,12 @@ VLogBf16Vop3::VLogBf16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VLogBf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogBf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4034,6 +4148,12 @@ VExpBf16Vop3::VExpBf16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VExpBf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpBf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4137,6 +4257,12 @@ VSinBf16Vop3::VSinBf16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSinBf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinBf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4240,6 +4366,12 @@ VCosBf16Vop3::VCosBf16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCosBf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosBf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -7515,6 +7647,12 @@ VMinNumF16Vop3::VMinNumF16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMinNumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinNumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -7653,6 +7791,12 @@ VMaxNumF16Vop3::VMaxNumF16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMaxNumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxNumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -7790,6 +7934,12 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VAddF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -7925,6 +8075,12 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VSubF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8061,6 +8217,12 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VSubrevF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8196,6 +8358,12 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMulF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8332,6 +8500,12 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VFmacF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8471,6 +8645,12 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VLdexpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8827,6 +9007,12 @@ VBitop3B16Vop3::VBitop3B16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VBitop3B16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VBitop3B16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -9271,6 +9457,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VDivFixupF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -10261,6 +10453,12 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VAddNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -10364,6 +10562,12 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VSubNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -10412,109 +10616,5 @@ void VSubNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { src1.clear_delegate(); } -VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) - : Vop3("v_mul_lo_u16", reinterpret_cast(inst), - make_exec_fn()), - vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), - src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), - src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { - dst_operands_[0] = &vdst; - src_operands_[0] = &src0; - src_operands_[1] = &src1; - num_src_ = 2; - num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == 255) - src0 = Operand( - 16, OperandType::OPR_SIMM32, - static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == 254) { - const auto *words = reinterpret_cast(inst); - uint32_t literal_word = sizeof(OpEncoding) / sizeof(uint32_t); - uint64_t literal64 = - (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; - src0 = Operand(16, OperandType::OPR_SIMM64, literal64, true); - } - if (reinterpret_cast(inst)->src1 == 255) - src1 = Operand( - 16, OperandType::OPR_SIMM32, - static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src1 == 254) { - const auto *words = reinterpret_cast(inst); - uint32_t literal_word = sizeof(OpEncoding) / sizeof(uint32_t); - uint64_t literal64 = - (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; - src1 = Operand(16, OperandType::OPR_SIMM64, literal64, true); - } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) { - auto *dp8 = reinterpret_cast(inst); - src0 = Operand(16, OperandType::OPR_VGPR, dp8->vsrc0); - dpp8_lane_sel_ = (dp8->lane_sel_0 << 0) | (dp8->lane_sel_1 << 3) | (dp8->lane_sel_2 << 6) | - (dp8->lane_sel_3 << 9) | (dp8->lane_sel_4 << 12) | (dp8->lane_sel_5 << 15) | - (dp8->lane_sel_6 << 18) | (dp8->lane_sel_7 << 21); - dpp_fi_ = amdgpu::dpp::src_dpp8_fi(reinterpret_cast(inst)->src0); - } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) { - auto *dp = reinterpret_cast(inst); - src0 = Operand(16, OperandType::OPR_VGPR, dp->vsrc0); - dpp_ctrl_ = dp->dpp_ctrl; - dpp_row_mask_ = dp->row_mask; - dpp_bank_mask_ = dp->bank_mask; - dpp_bound_ctrl_ = dp->bound_ctrl; - dpp_fi_ = dp->fi; - } - vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); - src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); - src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); -} - -void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { - uint32_t sdwa_old_dst_[64] = {}; - if (inst_.src0 == amdgpu::SRC_DPP) { - uint32_t vb = wf.vgpr_alloc().base; - uint64_t ex = wf.exec(); - for (uint32_t ln = 0; ln < wf.wf_size(); ++ln) - if (ex & (1ULL << ln)) - sdwa_old_dst_[ln] = wf.cu().read_vgpr(vb + inst_.vdst, ln); - } - if (inst_.src0 == amdgpu::SRC_DPP) - amdgpu::dpp::apply_dpp(src_operands_[0], dpp_ctrl_, dpp_row_mask_, dpp_bank_mask_, - dpp_bound_ctrl_, dpp_fi_, dpp_src0_, wf); - if (amdgpu::dpp::is_src_dpp8(inst_.src0)) - amdgpu::dpp::apply_dpp8(src_operands_[0], dpp8_lane_sel_, dpp_fi_, dpp_src0_, wf); - if (dpp_src0_) - src0.set_delegate(dpp_src0_.get()); - if (dpp_src1_) - src1.set_delegate(dpp_src1_.get()); - uint64_t exec = wf.exec(); - [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); - for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { - if (!(exec & (1ULL << lane))) - continue; - { - uint32_t src_half = static_cast(static_cast( - static_cast(static_cast(static_cast(static_cast( - static_cast(static_cast(static_cast( - ::rocjitsu::amdgpu::read_vop3_true16_src(src0, wf, lane, opsel, 0)))) * - static_cast(static_cast(static_cast( - ::rocjitsu::amdgpu::read_vop3_true16_src(src1, wf, lane, opsel, 1)))))))))); - ::rocjitsu::amdgpu::write_vop3_true16_dst(vdst, wf, lane, opsel, src_half, true); - } - } - if (inst_.src0 == amdgpu::SRC_DPP) { - uint64_t dpp_write_mask = amdgpu::dpp::dpp_write_mask(wf.wf_size(), dpp_ctrl_, dpp_row_mask_, - dpp_bank_mask_, dpp_bound_ctrl_); - if (dpp_write_mask != ~0ULL) { - uint64_t ex = wf.exec(); - uint32_t vb = wf.vgpr_alloc().base; - for (uint32_t ln = 0; ln < wf.wf_size(); ++ln) { - if ((ex & (1ULL << ln)) && !(dpp_write_mask & (1ULL << ln))) - wf.cu().write_vgpr(vb + inst_.vdst, ln, sdwa_old_dst_[ln]); - } - } - } - src0.clear_delegate(); - src1.clear_delegate(); -} - } // namespace gfx1250 } // namespace rocjitsu diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_alu_2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_alu_2.cpp index 85e9afc1ce17..3d26d0d418fa 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_alu_2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_alu_2.cpp @@ -21,6 +21,116 @@ namespace rocjitsu { namespace gfx1250 { +VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) + : Vop3("v_mul_lo_u16", reinterpret_cast(inst), + make_exec_fn()), + vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), + src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), + src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { + dst_operands_[0] = &vdst; + src_operands_[0] = &src0; + src_operands_[1] = &src1; + num_src_ = 2; + num_dst_ = 1; + if (reinterpret_cast(inst)->src0 == 255) + src0 = Operand( + 16, OperandType::OPR_SIMM32, + static_cast(reinterpret_cast(inst)->simm32)); + if (reinterpret_cast(inst)->src0 == 254) { + const auto *words = reinterpret_cast(inst); + uint32_t literal_word = sizeof(OpEncoding) / sizeof(uint32_t); + uint64_t literal64 = + (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; + src0 = Operand(16, OperandType::OPR_SIMM64, literal64, true); + } + if (reinterpret_cast(inst)->src1 == 255) + src1 = Operand( + 16, OperandType::OPR_SIMM32, + static_cast(reinterpret_cast(inst)->simm32)); + if (reinterpret_cast(inst)->src1 == 254) { + const auto *words = reinterpret_cast(inst); + uint32_t literal_word = sizeof(OpEncoding) / sizeof(uint32_t); + uint64_t literal64 = + (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; + src1 = Operand(16, OperandType::OPR_SIMM64, literal64, true); + } + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) { + auto *dp8 = reinterpret_cast(inst); + src0 = Operand(16, OperandType::OPR_VGPR, dp8->vsrc0); + dpp8_lane_sel_ = (dp8->lane_sel_0 << 0) | (dp8->lane_sel_1 << 3) | (dp8->lane_sel_2 << 6) | + (dp8->lane_sel_3 << 9) | (dp8->lane_sel_4 << 12) | (dp8->lane_sel_5 << 15) | + (dp8->lane_sel_6 << 18) | (dp8->lane_sel_7 << 21); + dpp_fi_ = amdgpu::dpp::src_dpp8_fi(reinterpret_cast(inst)->src0); + } + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) { + auto *dp = reinterpret_cast(inst); + src0 = Operand(16, OperandType::OPR_VGPR, dp->vsrc0); + dpp_ctrl_ = dp->dpp_ctrl; + dpp_row_mask_ = dp->row_mask; + dpp_bank_mask_ = dp->bank_mask; + dpp_bound_ctrl_ = dp->bound_ctrl; + dpp_fi_ = dp->fi; + } + vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); + src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); + src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); +} + +void VMulLoU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + +void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { + uint32_t sdwa_old_dst_[64] = {}; + if (inst_.src0 == amdgpu::SRC_DPP) { + uint32_t vb = wf.vgpr_alloc().base; + uint64_t ex = wf.exec(); + for (uint32_t ln = 0; ln < wf.wf_size(); ++ln) + if (ex & (1ULL << ln)) + sdwa_old_dst_[ln] = wf.cu().read_vgpr(vb + inst_.vdst, ln); + } + if (inst_.src0 == amdgpu::SRC_DPP) + amdgpu::dpp::apply_dpp(src_operands_[0], dpp_ctrl_, dpp_row_mask_, dpp_bank_mask_, + dpp_bound_ctrl_, dpp_fi_, dpp_src0_, wf); + if (amdgpu::dpp::is_src_dpp8(inst_.src0)) + amdgpu::dpp::apply_dpp8(src_operands_[0], dpp8_lane_sel_, dpp_fi_, dpp_src0_, wf); + if (dpp_src0_) + src0.set_delegate(dpp_src0_.get()); + if (dpp_src1_) + src1.set_delegate(dpp_src1_.get()); + uint64_t exec = wf.exec(); + [[maybe_unused]] uint32_t opsel = amdgpu::vop3_opsel(inst_); + for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { + if (!(exec & (1ULL << lane))) + continue; + { + uint32_t src_half = static_cast(static_cast( + static_cast(static_cast(static_cast(static_cast( + static_cast(static_cast(static_cast( + ::rocjitsu::amdgpu::read_vop3_true16_src(src0, wf, lane, opsel, 0)))) * + static_cast(static_cast(static_cast( + ::rocjitsu::amdgpu::read_vop3_true16_src(src1, wf, lane, opsel, 1)))))))))); + ::rocjitsu::amdgpu::write_vop3_true16_dst(vdst, wf, lane, opsel, src_half, true); + } + } + if (inst_.src0 == amdgpu::SRC_DPP) { + uint64_t dpp_write_mask = amdgpu::dpp::dpp_write_mask(wf.wf_size(), dpp_ctrl_, dpp_row_mask_, + dpp_bank_mask_, dpp_bound_ctrl_); + if (dpp_write_mask != ~0ULL) { + uint64_t ex = wf.exec(); + uint32_t vb = wf.vgpr_alloc().base; + for (uint32_t ln = 0; ln < wf.wf_size(); ++ln) { + if ((ex & (1ULL << ln)) && !(dpp_write_mask & (1ULL << ln))) + wf.cu().write_vgpr(vb + inst_.vdst, ln, sdwa_old_dst_[ln]); + } + } + } + src0.clear_delegate(); + src1.clear_delegate(); +} + VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) : Vop3("v_max_u16", reinterpret_cast(inst), make_exec_fn()), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), @@ -75,6 +185,12 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMaxU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -178,6 +294,12 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMaxI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -281,6 +403,12 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMinU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -384,6 +512,12 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMinI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -488,6 +622,12 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VAddNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -590,6 +730,12 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VSubNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2065,6 +2211,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VLshlrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2165,6 +2317,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VLshrrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2265,6 +2423,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VAshrrevI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2726,6 +2890,12 @@ VAndB16Vop3::VAndB16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VAndB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAndB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2828,6 +2998,12 @@ VOrB16Vop3::VOrB16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VOrB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VOrB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2930,6 +3106,12 @@ VXorB16Vop3::VXorB16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VXorB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VXorB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3213,6 +3395,12 @@ VMinimumF16Vop3::VMinimumF16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMinimumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinimumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3350,6 +3538,12 @@ VMaximumF16Vop3::VMaximumF16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VMaximumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaximumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_cvt.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_cvt.cpp index 954e05b355d8..4ca2a9a50726 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_cvt.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_cvt.cpp @@ -500,6 +500,12 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -1768,6 +1774,12 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtF16U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -1852,6 +1864,12 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtF16I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -1936,6 +1954,12 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2026,6 +2050,12 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2118,6 +2148,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VFrexpMantF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2232,6 +2268,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VFrexpExpI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2349,6 +2391,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtNormI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2438,6 +2486,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtNormU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3286,6 +3340,12 @@ VCvtF16Fp8Vop3::VCvtF16Fp8Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtF16Fp8Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16Fp8Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3378,6 +3438,12 @@ VCvtF16Bf8Vop3::VCvtF16Bf8Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtF16Bf8Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16Bf8Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -10014,95 +10080,5 @@ void VCvtPkNormU16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { src1.clear_delegate(); } -VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) - : Vop3("v_cvt_pk_u16_u32", reinterpret_cast(inst), - make_exec_fn()), - vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), - src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), - src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { - dst_operands_[0] = &vdst; - src_operands_[0] = &src0; - src_operands_[1] = &src1; - num_src_ = 2; - num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == 255) - src0 = Operand( - 32, OperandType::OPR_SIMM32, - static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == 254) { - const auto *words = reinterpret_cast(inst); - uint32_t literal_word = sizeof(OpEncoding) / sizeof(uint32_t); - uint64_t literal64 = - (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; - src0 = Operand(32, OperandType::OPR_SIMM64, literal64, true); - } - if (reinterpret_cast(inst)->src1 == 255) - src1 = Operand( - 32, OperandType::OPR_SIMM32, - static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src1 == 254) { - const auto *words = reinterpret_cast(inst); - uint32_t literal_word = sizeof(OpEncoding) / sizeof(uint32_t); - uint64_t literal64 = - (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; - src1 = Operand(32, OperandType::OPR_SIMM64, literal64, true); - } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) { - auto *dp8 = reinterpret_cast(inst); - src0 = Operand(32, OperandType::OPR_VGPR, dp8->vsrc0); - dpp8_lane_sel_ = (dp8->lane_sel_0 << 0) | (dp8->lane_sel_1 << 3) | (dp8->lane_sel_2 << 6) | - (dp8->lane_sel_3 << 9) | (dp8->lane_sel_4 << 12) | (dp8->lane_sel_5 << 15) | - (dp8->lane_sel_6 << 18) | (dp8->lane_sel_7 << 21); - dpp_fi_ = amdgpu::dpp::src_dpp8_fi(reinterpret_cast(inst)->src0); - } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) { - auto *dp = reinterpret_cast(inst); - src0 = Operand(32, OperandType::OPR_VGPR, dp->vsrc0); - dpp_ctrl_ = dp->dpp_ctrl; - dpp_row_mask_ = dp->row_mask; - dpp_bank_mask_ = dp->bank_mask; - dpp_bound_ctrl_ = dp->bound_ctrl; - dpp_fi_ = dp->fi; - } - vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); - src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); - src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); -} - -void VCvtPkU16U32Vop3::execute_impl(amdgpu::Wavefront &wf) { - uint32_t sdwa_old_dst_[64] = {}; - if (inst_.src0 == amdgpu::SRC_DPP) { - uint32_t vb = wf.vgpr_alloc().base; - uint64_t ex = wf.exec(); - for (uint32_t ln = 0; ln < wf.wf_size(); ++ln) - if (ex & (1ULL << ln)) - sdwa_old_dst_[ln] = wf.cu().read_vgpr(vb + inst_.vdst, ln); - } - if (inst_.src0 == amdgpu::SRC_DPP) - amdgpu::dpp::apply_dpp(src_operands_[0], dpp_ctrl_, dpp_row_mask_, dpp_bank_mask_, - dpp_bound_ctrl_, dpp_fi_, dpp_src0_, wf); - if (amdgpu::dpp::is_src_dpp8(inst_.src0)) - amdgpu::dpp::apply_dpp8(src_operands_[0], dpp8_lane_sel_, dpp_fi_, dpp_src0_, wf); - if (dpp_src0_) - src0.set_delegate(dpp_src0_.get()); - if (dpp_src1_) - src1.set_delegate(dpp_src1_.get()); - amdgpu::execute_v_cvt_pk_u16_u32_vop3(*this, wf); - if (inst_.src0 == amdgpu::SRC_DPP) { - uint64_t dpp_write_mask = amdgpu::dpp::dpp_write_mask(wf.wf_size(), dpp_ctrl_, dpp_row_mask_, - dpp_bank_mask_, dpp_bound_ctrl_); - if (dpp_write_mask != ~0ULL) { - uint64_t ex = wf.exec(); - uint32_t vb = wf.vgpr_alloc().base; - for (uint32_t ln = 0; ln < wf.wf_size(); ++ln) { - if ((ex & (1ULL << ln)) && !(dpp_write_mask & (1ULL << ln))) - wf.cu().write_vgpr(vb + inst_.vdst, ln, sdwa_old_dst_[ln]); - } - } - } - src0.clear_delegate(); - src1.clear_delegate(); -} - } // namespace gfx1250 } // namespace rocjitsu diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_cvt_2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_cvt_2.cpp index 7ded022583f2..65cb809bdb51 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_cvt_2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_cvt_2.cpp @@ -21,6 +21,96 @@ namespace rocjitsu { namespace gfx1250 { +VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) + : Vop3("v_cvt_pk_u16_u32", reinterpret_cast(inst), + make_exec_fn()), + vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), + src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), + src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { + dst_operands_[0] = &vdst; + src_operands_[0] = &src0; + src_operands_[1] = &src1; + num_src_ = 2; + num_dst_ = 1; + if (reinterpret_cast(inst)->src0 == 255) + src0 = Operand( + 32, OperandType::OPR_SIMM32, + static_cast(reinterpret_cast(inst)->simm32)); + if (reinterpret_cast(inst)->src0 == 254) { + const auto *words = reinterpret_cast(inst); + uint32_t literal_word = sizeof(OpEncoding) / sizeof(uint32_t); + uint64_t literal64 = + (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; + src0 = Operand(32, OperandType::OPR_SIMM64, literal64, true); + } + if (reinterpret_cast(inst)->src1 == 255) + src1 = Operand( + 32, OperandType::OPR_SIMM32, + static_cast(reinterpret_cast(inst)->simm32)); + if (reinterpret_cast(inst)->src1 == 254) { + const auto *words = reinterpret_cast(inst); + uint32_t literal_word = sizeof(OpEncoding) / sizeof(uint32_t); + uint64_t literal64 = + (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; + src1 = Operand(32, OperandType::OPR_SIMM64, literal64, true); + } + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) { + auto *dp8 = reinterpret_cast(inst); + src0 = Operand(32, OperandType::OPR_VGPR, dp8->vsrc0); + dpp8_lane_sel_ = (dp8->lane_sel_0 << 0) | (dp8->lane_sel_1 << 3) | (dp8->lane_sel_2 << 6) | + (dp8->lane_sel_3 << 9) | (dp8->lane_sel_4 << 12) | (dp8->lane_sel_5 << 15) | + (dp8->lane_sel_6 << 18) | (dp8->lane_sel_7 << 21); + dpp_fi_ = amdgpu::dpp::src_dpp8_fi(reinterpret_cast(inst)->src0); + } + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) { + auto *dp = reinterpret_cast(inst); + src0 = Operand(32, OperandType::OPR_VGPR, dp->vsrc0); + dpp_ctrl_ = dp->dpp_ctrl; + dpp_row_mask_ = dp->row_mask; + dpp_bank_mask_ = dp->bank_mask; + dpp_bound_ctrl_ = dp->bound_ctrl; + dpp_fi_ = dp->fi; + } + vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); + src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); + src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); +} + +void VCvtPkU16U32Vop3::execute_impl(amdgpu::Wavefront &wf) { + uint32_t sdwa_old_dst_[64] = {}; + if (inst_.src0 == amdgpu::SRC_DPP) { + uint32_t vb = wf.vgpr_alloc().base; + uint64_t ex = wf.exec(); + for (uint32_t ln = 0; ln < wf.wf_size(); ++ln) + if (ex & (1ULL << ln)) + sdwa_old_dst_[ln] = wf.cu().read_vgpr(vb + inst_.vdst, ln); + } + if (inst_.src0 == amdgpu::SRC_DPP) + amdgpu::dpp::apply_dpp(src_operands_[0], dpp_ctrl_, dpp_row_mask_, dpp_bank_mask_, + dpp_bound_ctrl_, dpp_fi_, dpp_src0_, wf); + if (amdgpu::dpp::is_src_dpp8(inst_.src0)) + amdgpu::dpp::apply_dpp8(src_operands_[0], dpp8_lane_sel_, dpp_fi_, dpp_src0_, wf); + if (dpp_src0_) + src0.set_delegate(dpp_src0_.get()); + if (dpp_src1_) + src1.set_delegate(dpp_src1_.get()); + amdgpu::execute_v_cvt_pk_u16_u32_vop3(*this, wf); + if (inst_.src0 == amdgpu::SRC_DPP) { + uint64_t dpp_write_mask = amdgpu::dpp::dpp_write_mask(wf.wf_size(), dpp_ctrl_, dpp_row_mask_, + dpp_bank_mask_, dpp_bound_ctrl_); + if (dpp_write_mask != ~0ULL) { + uint64_t ex = wf.exec(); + uint32_t vb = wf.vgpr_alloc().base; + for (uint32_t ln = 0; ln < wf.wf_size(); ++ln) { + if ((ex & (1ULL << ln)) && !(dpp_write_mask & (1ULL << ln))) + wf.cu().write_vgpr(vb + inst_.vdst, ln, sdwa_old_dst_[ln]); + } + } + } + src0.clear_delegate(); + src1.clear_delegate(); +} + VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) : Vop3("v_cvt_pk_i16_i32", reinterpret_cast(inst), make_exec_fn()), @@ -166,6 +256,12 @@ VCvtPkFp8F32Vop3::VCvtPkFp8F32Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VCvtPkFp8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtPkFp8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -266,6 +362,12 @@ VCvtPkBf8F32Vop3::VCvtPkBf8F32Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VCvtPkBf8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtPkBf8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -366,6 +468,12 @@ VCvtSrFp8F32Vop3::VCvtSrFp8F32Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VCvtSrFp8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrFp8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -468,6 +576,12 @@ VCvtSrBf8F32Vop3::VCvtSrBf8F32Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VCvtSrBf8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrBf8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -983,6 +1097,12 @@ VCvtPkFp8F16Vop3::VCvtPkFp8F16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtPkFp8F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtPkFp8F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -1067,6 +1187,12 @@ VCvtPkBf8F16Vop3::VCvtPkBf8F16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VCvtPkBf8F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtPkBf8F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -1165,6 +1291,12 @@ VCvtSrFp8F16Vop3::VCvtSrFp8F16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VCvtSrFp8F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrFp8F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -1268,6 +1400,12 @@ VCvtSrBf8F16Vop3::VCvtSrBf8F16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VCvtSrBf8F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrBf8F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_data.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_data.cpp index 0c6e2d31b429..3e68d02aaa91 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_data.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_data.cpp @@ -213,6 +213,12 @@ VMovB16Vop3::VMovB16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VMovB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMovB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -1747,6 +1753,12 @@ VCndmaskB16Vop3::VCndmaskB16Vop3(const MachineInst *inst) src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } +void VCndmaskB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCndmaskB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_misc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_misc.cpp index 33032880b408..8c129705fdb8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_misc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_misc.cpp @@ -297,6 +297,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSatPkU8I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -343,6 +349,12 @@ VSatPk4I4I8Vop3::VSatPk4I4I8Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSatPk4I4I8Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPk4I4I8Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -389,6 +401,12 @@ VSatPk4U4U8Vop3::VSatPk4U4U8Vop3(const MachineInst *inst) src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } +void VSatPk4U4U8Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPk4U4U8Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_ternary.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_ternary.cpp index 4fac00a96a00..e330ad21c0a0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_ternary.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3_ternary.cpp @@ -2512,6 +2512,12 @@ VMin3NumF16Vop3::VMin3NumF16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMin3NumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3NumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2672,6 +2678,12 @@ VMax3NumF16Vop3::VMax3NumF16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMax3NumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3NumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3040,6 +3052,12 @@ VMinimum3F16Vop3::VMinimum3F16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMinimum3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinimum3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3205,6 +3223,12 @@ VMaximum3F16Vop3::VMaximum3F16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMaximum3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaximum3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3474,6 +3498,12 @@ VMed3NumF16Vop3::VMed3NumF16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMed3NumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3NumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3945,6 +3975,12 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMadU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4370,6 +4406,12 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VFmaF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4528,6 +4570,12 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMin3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4659,6 +4707,12 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMin3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4787,6 +4841,12 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMax3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4918,6 +4978,12 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMax3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5046,6 +5112,12 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMed3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5179,6 +5251,12 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMed3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5415,6 +5493,12 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMadI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -7268,6 +7352,12 @@ VMinmaxNumF16Vop3::VMinmaxNumF16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMinmaxNumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinmaxNumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -7428,6 +7518,12 @@ VMaxminNumF16Vop3::VMaxminNumF16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMaxminNumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxminNumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -7796,6 +7892,12 @@ VMinimummaximumF16Vop3::VMinimummaximumF16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMinimummaximumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinimummaximumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -7961,6 +8063,12 @@ VMaximumminimumF16Vop3::VMaximumminimumF16Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VMaximumminimumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaximumminimumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8126,6 +8234,12 @@ VAshrPkI8I32Vop3::VAshrPkI8I32Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VAshrPkI8I32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrPkI8I32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8248,6 +8362,12 @@ VAshrPkU8I32Vop3::VAshrPkU8I32Vop3(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VAshrPkU8I32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrPkU8I32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3p.cpp index d29c9f485a59..46a99348da0d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3p.cpp @@ -3703,6 +3703,12 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VFmaMixloF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixloF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3834,6 +3840,12 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VFmaMixhiF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixhiF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -6209,6 +6221,12 @@ VFmaMixloBf16Vop3p::VFmaMixloBf16Vop3p(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VFmaMixloBf16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixloBf16Vop3p::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -6341,6 +6359,12 @@ VFmaMixhiBf16Vop3p::VFmaMixhiBf16Vop3p(const MachineInst *inst) src2.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } +void VFmaMixhiBf16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixhiBf16Vop3p::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3p.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3p.h index 03abb597adda..14d1ee0675c8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3p.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/vop3p.h @@ -301,6 +301,7 @@ class VFmaMixloF16Vop3p : public Vop3p { public: VFmaMixloF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -311,6 +312,7 @@ class VFmaMixhiF16Vop3p : public Vop3p { public: VFmaMixhiF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -496,6 +498,7 @@ class VFmaMixloBf16Vop3p : public Vop3p { public: VFmaMixloBf16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -506,6 +509,7 @@ class VFmaMixhiBf16Vop3p : public Vop3p { public: VFmaMixhiBf16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/ds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/ds.cpp index 3ac88dac33a9..a150d63fe565 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/ds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/ds.cpp @@ -1866,6 +1866,12 @@ DsReadI8Ds::DsReadI8Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadI8Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadI8Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -1891,6 +1897,12 @@ DsReadU8Ds::DsReadU8Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU8Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU8Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -1915,6 +1927,12 @@ DsReadI16Ds::DsReadI16Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadI16Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadI16Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -1940,6 +1958,12 @@ DsReadU16Ds::DsReadU16Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU16Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU16Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -3909,6 +3933,12 @@ DsReadU8D16Ds::DsReadU8D16Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU8D16Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU8D16Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -3935,6 +3965,12 @@ DsReadU8D16HiDs::DsReadU8D16HiDs(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU8D16HiDs::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU8D16HiDs::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -3961,6 +3997,12 @@ DsReadI8D16Ds::DsReadI8D16Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadI8D16Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadI8D16Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -3988,6 +4030,12 @@ DsReadI8D16HiDs::DsReadI8D16HiDs(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadI8D16HiDs::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadI8D16HiDs::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -4015,6 +4063,12 @@ DsReadU16D16Ds::DsReadU16D16Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU16D16Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU16D16Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -4041,6 +4095,12 @@ DsReadU16D16HiDs::DsReadU16D16HiDs(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU16D16HiDs::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU16D16HiDs::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/ds.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/ds.h index 1d0a7aa9c436..6c1f27e8da0f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/ds.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/ds.h @@ -479,6 +479,7 @@ class DsReadI8Ds : public Ds { public: DsReadI8Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -487,6 +488,7 @@ class DsReadU8Ds : public Ds { public: DsReadU8Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -495,6 +497,7 @@ class DsReadI16Ds : public Ds { public: DsReadI16Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -503,6 +506,7 @@ class DsReadU16Ds : public Ds { public: DsReadU16Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -941,6 +945,7 @@ class DsReadU8D16Ds : public Ds { public: DsReadU8D16Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -949,6 +954,7 @@ class DsReadU8D16HiDs : public Ds { public: DsReadU8D16HiDs(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -957,6 +963,7 @@ class DsReadI8D16Ds : public Ds { public: DsReadI8D16Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -965,6 +972,7 @@ class DsReadI8D16HiDs : public Ds { public: DsReadI8D16HiDs(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -973,6 +981,7 @@ class DsReadU16D16Ds : public Ds { public: DsReadU16D16Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -981,6 +990,7 @@ class DsReadU16D16HiDs : public Ds { public: DsReadU16D16HiDs(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/sopk.cpp index 6835a06bcc42..94632a642fd0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/sopk.cpp @@ -326,6 +326,12 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregB32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregB32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; @@ -357,6 +363,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregImm32B32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregImm32B32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/sopk.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/sopk.h index 0b7977fd1de5..1e163171d202 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/sopk.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/sopk.h @@ -161,6 +161,7 @@ class SSetregB32Sopk : public Sopk { public: SSetregB32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; Operand sdst; }; @@ -169,6 +170,7 @@ class SSetregImm32B32Sopk : public Sopk { public: SSetregImm32B32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop1.cpp index e97792c6cc6a..69668991fce6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop1.cpp @@ -1218,6 +1218,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } } +void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7776,6 +7782,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } } +void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7908,6 +7920,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } } +void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8040,6 +8058,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } } +void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8172,6 +8196,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } } +void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8304,6 +8334,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } } +void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8448,6 +8484,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } } +void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8592,6 +8634,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } } +void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8736,6 +8784,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } } +void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8880,6 +8934,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } } +void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9024,6 +9084,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } } +void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9168,6 +9234,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } } +void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9312,6 +9384,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } } +void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9456,6 +9534,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } } +void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9600,6 +9684,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } } +void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9744,6 +9834,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } } +void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9888,6 +9984,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } } +void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10032,6 +10134,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } } +void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10176,6 +10284,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } } +void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10372,6 +10486,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } } +void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10516,6 +10636,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } } +void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop1.h index 7d294eeddad8..9541a22eb96e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop1.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop1 : public Vop1 { public: VCvtF16F32Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -476,6 +477,7 @@ class VCvtF16U16Vop1 : public Vop1 { public: VCvtF16U16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -484,6 +486,7 @@ class VCvtF16I16Vop1 : public Vop1 { public: VCvtF16I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -492,6 +495,7 @@ class VCvtU16F16Vop1 : public Vop1 { public: VCvtU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -500,6 +504,7 @@ class VCvtI16F16Vop1 : public Vop1 { public: VCvtI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -508,6 +513,7 @@ class VRcpF16Vop1 : public Vop1 { public: VRcpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -516,6 +522,7 @@ class VSqrtF16Vop1 : public Vop1 { public: VSqrtF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -524,6 +531,7 @@ class VRsqF16Vop1 : public Vop1 { public: VRsqF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -532,6 +540,7 @@ class VLogF16Vop1 : public Vop1 { public: VLogF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -540,6 +549,7 @@ class VExpF16Vop1 : public Vop1 { public: VExpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -548,6 +558,7 @@ class VFrexpMantF16Vop1 : public Vop1 { public: VFrexpMantF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -556,6 +567,7 @@ class VFrexpExpI16F16Vop1 : public Vop1 { public: VFrexpExpI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -564,6 +576,7 @@ class VFloorF16Vop1 : public Vop1 { public: VFloorF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -572,6 +585,7 @@ class VCeilF16Vop1 : public Vop1 { public: VCeilF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -580,6 +594,7 @@ class VTruncF16Vop1 : public Vop1 { public: VTruncF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -588,6 +603,7 @@ class VRndneF16Vop1 : public Vop1 { public: VRndneF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -596,6 +612,7 @@ class VFractF16Vop1 : public Vop1 { public: VFractF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -604,6 +621,7 @@ class VSinF16Vop1 : public Vop1 { public: VSinF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -612,6 +630,7 @@ class VCosF16Vop1 : public Vop1 { public: VCosF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -628,6 +647,7 @@ class VCvtNormI16F16Vop1 : public Vop1 { public: VCvtNormI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -636,6 +656,7 @@ class VCvtNormU16F16Vop1 : public Vop1 { public: VCvtNormU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop2.cpp index 0a3b194ef92d..95bc4c9258cf 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop2.cpp @@ -5708,6 +5708,12 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } } +void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5859,6 +5865,12 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } } +void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6010,6 +6022,12 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } } +void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6161,6 +6179,12 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } } +void VMulF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6313,6 +6337,12 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) } } +void VFmacF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6466,6 +6496,12 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VFmamkF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmamkF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6619,6 +6655,12 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VFmaakF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaakF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6770,6 +6812,12 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } } +void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6921,6 +6969,12 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } } +void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7072,6 +7126,12 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } } +void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop2.h index 786610767e23..0bbc49c6f024 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop2.h @@ -373,6 +373,7 @@ class VAddF16Vop2 : public Vop2 { public: VAddF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -382,6 +383,7 @@ class VSubF16Vop2 : public Vop2 { public: VSubF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -391,6 +393,7 @@ class VSubrevF16Vop2 : public Vop2 { public: VSubrevF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -400,6 +403,7 @@ class VMulF16Vop2 : public Vop2 { public: VMulF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -409,6 +413,7 @@ class VFmacF16Vop2 : public Vop2 { public: VFmacF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -418,6 +423,7 @@ class VFmamkF16Vop2 : public Vop2 { public: VFmamkF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -428,6 +434,7 @@ class VFmaakF16Vop2 : public Vop2 { public: VFmaakF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -438,6 +445,7 @@ class VMaxF16Vop2 : public Vop2 { public: VMaxF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -447,6 +455,7 @@ class VMinF16Vop2 : public Vop2 { public: VMinF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -456,6 +465,7 @@ class VLdexpF16Vop2 : public Vop2 { public: VLdexpF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3.cpp index 41758de43e71..08b8f84af31d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3.cpp @@ -274,6 +274,12 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_f16_f32_vop3(*this, wf); } @@ -1180,6 +1186,12 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtF16U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_f16_u16_vop3(*this, wf); } @@ -1199,6 +1211,12 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtF16I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_f16_i16_vop3(*this, wf); } @@ -1218,6 +1236,12 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_u16_f16_vop3(*this, wf); } @@ -1237,6 +1261,12 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_i16_f16_vop3(*this, wf); } @@ -1255,6 +1285,12 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VRcpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_rcp_f16_vop3(*this, wf); } VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) @@ -1271,6 +1307,12 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSqrtF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_sqrt_f16_vop3(*this, wf); } @@ -1289,6 +1331,12 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VRsqF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_rsq_f16_vop3(*this, wf); } VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) @@ -1305,6 +1353,12 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VLogF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_log_f16_vop3(*this, wf); } VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) @@ -1321,6 +1375,12 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VExpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_exp_f16_vop3(*this, wf); } VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) @@ -1338,6 +1398,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFrexpMantF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_frexp_mant_f16_vop3(*this, wf); } @@ -1357,6 +1423,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFrexpExpI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_frexp_exp_i16_f16_vop3(*this, wf); } @@ -1376,6 +1448,12 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFloorF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_floor_f16_vop3(*this, wf); } @@ -1394,6 +1472,12 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCeilF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_ceil_f16_vop3(*this, wf); } @@ -1413,6 +1497,12 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VTruncF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_trunc_f16_vop3(*this, wf); } @@ -1432,6 +1522,12 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VRndneF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_rndne_f16_vop3(*this, wf); } @@ -1451,6 +1547,12 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFractF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_fract_f16_vop3(*this, wf); } @@ -1469,6 +1571,12 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_sin_f16_vop3(*this, wf); } VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) @@ -1485,6 +1593,12 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCosF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cos_f16_vop3(*this, wf); } VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) @@ -1522,6 +1636,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtNormI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_norm_i16_f16_vop3(*this, wf); } @@ -1541,6 +1661,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtNormU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_norm_u16_f16_vop3(*this, wf); } @@ -2371,6 +2497,12 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VAddF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_add_f16_vop3(*this, wf); } VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) @@ -2393,6 +2525,12 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSubF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_sub_f16_vop3(*this, wf); } VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) @@ -2416,6 +2554,12 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSubrevF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_subrev_f16_vop3(*this, wf); } @@ -2440,6 +2584,12 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMulF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mul_f16_vop3(*this, wf); } VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) @@ -2463,6 +2613,12 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFmacF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_fmac_f16_vop3(*this, wf); } @@ -2487,6 +2643,12 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMaxF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max_f16_vop3(*this, wf); } VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) @@ -2509,6 +2671,12 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min_f16_vop3(*this, wf); } VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) @@ -2532,6 +2700,12 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VLdexpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_ldexp_f16_vop3(*this, wf); } @@ -4046,6 +4220,12 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VAddNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_add_nc_u16_vop3(*this, wf); } @@ -4071,6 +4251,12 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSubNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_sub_nc_u16_vop3(*this, wf); } @@ -4096,6 +4282,12 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMulLoU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mul_lo_u16_vop3(*this, wf); } @@ -4121,6 +4313,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VLshrrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_lshrrev_b16_vop3(*this, wf); } @@ -4146,6 +4344,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VAshrrevI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_ashrrev_i16_vop3(*this, wf); } @@ -4170,6 +4374,12 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMaxU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max_u16_vop3(*this, wf); } VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) @@ -4192,6 +4402,12 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMaxI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max_i16_vop3(*this, wf); } VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) @@ -4214,6 +4430,12 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMinU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min_u16_vop3(*this, wf); } VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) @@ -4236,6 +4458,12 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMinI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min_i16_vop3(*this, wf); } VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) @@ -4259,6 +4487,12 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VAddNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_add_nc_i16_vop3(*this, wf); } @@ -4284,6 +4518,12 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSubNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_sub_nc_i16_vop3(*this, wf); } @@ -4386,6 +4626,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VLshlrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_lshlrev_b16_vop3(*this, wf); } @@ -4416,6 +4662,12 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMadU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_u16_vop3(*this, wf); } VInterpP1llF16Vop3::VInterpP1llF16Vop3(const MachineInst *inst) @@ -4622,6 +4874,12 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFmaF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_fma_f16_vop3(*this, wf); } VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) @@ -4650,6 +4908,12 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMin3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min3_f16_vop3(*this, wf); } @@ -4680,6 +4944,12 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMin3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min3_i16_vop3(*this, wf); } @@ -4710,6 +4980,12 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMin3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min3_u16_vop3(*this, wf); } @@ -4740,6 +5016,12 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMax3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max3_f16_vop3(*this, wf); } @@ -4770,6 +5052,12 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMax3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max3_i16_vop3(*this, wf); } @@ -4800,6 +5088,12 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMax3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max3_u16_vop3(*this, wf); } @@ -4830,6 +5124,12 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMed3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_med3_f16_vop3(*this, wf); } @@ -4860,6 +5160,12 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMed3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_med3_i16_vop3(*this, wf); } @@ -4890,6 +5196,12 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMed3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_med3_u16_vop3(*this, wf); } @@ -4921,6 +5233,12 @@ VInterpP2F16Vop3::VInterpP2F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VInterpP2F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VInterpP2F16Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -4952,6 +5270,12 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMadI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_i16_vop3(*this, wf); } VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) @@ -4981,6 +5305,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VDivFixupF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_div_fixup_f16_vop3(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3.h index 7b12dec116a0..0f6cc096a9d6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3.h @@ -115,6 +115,7 @@ class VCvtF16F32Vop3 : public Vop3 { public: VCvtF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -503,6 +504,7 @@ class VCvtF16U16Vop3 : public Vop3 { public: VCvtF16U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -511,6 +513,7 @@ class VCvtF16I16Vop3 : public Vop3 { public: VCvtF16I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -519,6 +522,7 @@ class VCvtU16F16Vop3 : public Vop3 { public: VCvtU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -527,6 +531,7 @@ class VCvtI16F16Vop3 : public Vop3 { public: VCvtI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -535,6 +540,7 @@ class VRcpF16Vop3 : public Vop3 { public: VRcpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -543,6 +549,7 @@ class VSqrtF16Vop3 : public Vop3 { public: VSqrtF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -551,6 +558,7 @@ class VRsqF16Vop3 : public Vop3 { public: VRsqF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -559,6 +567,7 @@ class VLogF16Vop3 : public Vop3 { public: VLogF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -567,6 +576,7 @@ class VExpF16Vop3 : public Vop3 { public: VExpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -575,6 +585,7 @@ class VFrexpMantF16Vop3 : public Vop3 { public: VFrexpMantF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -583,6 +594,7 @@ class VFrexpExpI16F16Vop3 : public Vop3 { public: VFrexpExpI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -591,6 +603,7 @@ class VFloorF16Vop3 : public Vop3 { public: VFloorF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -599,6 +612,7 @@ class VCeilF16Vop3 : public Vop3 { public: VCeilF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -607,6 +621,7 @@ class VTruncF16Vop3 : public Vop3 { public: VTruncF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -615,6 +630,7 @@ class VRndneF16Vop3 : public Vop3 { public: VRndneF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -623,6 +639,7 @@ class VFractF16Vop3 : public Vop3 { public: VFractF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -631,6 +648,7 @@ class VSinF16Vop3 : public Vop3 { public: VSinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -639,6 +657,7 @@ class VCosF16Vop3 : public Vop3 { public: VCosF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -655,6 +674,7 @@ class VCvtNormI16F16Vop3 : public Vop3 { public: VCvtNormI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -663,6 +683,7 @@ class VCvtNormU16F16Vop3 : public Vop3 { public: VCvtNormU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -960,6 +981,7 @@ class VAddF16Vop3 : public Vop3 { public: VAddF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -969,6 +991,7 @@ class VSubF16Vop3 : public Vop3 { public: VSubF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -978,6 +1001,7 @@ class VSubrevF16Vop3 : public Vop3 { public: VSubrevF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -987,6 +1011,7 @@ class VMulF16Vop3 : public Vop3 { public: VMulF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -996,6 +1021,7 @@ class VFmacF16Vop3 : public Vop3 { public: VFmacF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1005,6 +1031,7 @@ class VMaxF16Vop3 : public Vop3 { public: VMaxF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1014,6 +1041,7 @@ class VMinF16Vop3 : public Vop3 { public: VMinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1023,6 +1051,7 @@ class VLdexpF16Vop3 : public Vop3 { public: VLdexpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1540,6 +1569,7 @@ class VAddNcU16Vop3 : public Vop3 { public: VAddNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1549,6 +1579,7 @@ class VSubNcU16Vop3 : public Vop3 { public: VSubNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1558,6 +1589,7 @@ class VMulLoU16Vop3 : public Vop3 { public: VMulLoU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1567,6 +1599,7 @@ class VLshrrevB16Vop3 : public Vop3 { public: VLshrrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1576,6 +1609,7 @@ class VAshrrevI16Vop3 : public Vop3 { public: VAshrrevI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1585,6 +1619,7 @@ class VMaxU16Vop3 : public Vop3 { public: VMaxU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1594,6 +1629,7 @@ class VMaxI16Vop3 : public Vop3 { public: VMaxI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1603,6 +1639,7 @@ class VMinU16Vop3 : public Vop3 { public: VMinU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1612,6 +1649,7 @@ class VMinI16Vop3 : public Vop3 { public: VMinI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1621,6 +1659,7 @@ class VAddNcI16Vop3 : public Vop3 { public: VAddNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1630,6 +1669,7 @@ class VSubNcI16Vop3 : public Vop3 { public: VSubNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1666,6 +1706,7 @@ class VLshlrevB16Vop3 : public Vop3 { public: VLshlrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1675,6 +1716,7 @@ class VMadU16Vop3 : public Vop3 { public: VMadU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1744,6 +1786,7 @@ class VFmaF16Vop3 : public Vop3 { public: VFmaF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1754,6 +1797,7 @@ class VMin3F16Vop3 : public Vop3 { public: VMin3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1764,6 +1808,7 @@ class VMin3I16Vop3 : public Vop3 { public: VMin3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1774,6 +1819,7 @@ class VMin3U16Vop3 : public Vop3 { public: VMin3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1784,6 +1830,7 @@ class VMax3F16Vop3 : public Vop3 { public: VMax3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1794,6 +1841,7 @@ class VMax3I16Vop3 : public Vop3 { public: VMax3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1804,6 +1852,7 @@ class VMax3U16Vop3 : public Vop3 { public: VMax3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1814,6 +1863,7 @@ class VMed3F16Vop3 : public Vop3 { public: VMed3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1824,6 +1874,7 @@ class VMed3I16Vop3 : public Vop3 { public: VMed3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1834,6 +1885,7 @@ class VMed3U16Vop3 : public Vop3 { public: VMed3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1844,6 +1896,7 @@ class VInterpP2F16Vop3 : public Vop3 { public: VInterpP2F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src1; Operand src0; @@ -1854,6 +1907,7 @@ class VMadI16Vop3 : public Vop3 { public: VMadI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1864,6 +1918,7 @@ class VDivFixupF16Vop3 : public Vop3 { public: VDivFixupF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3p.cpp index a6550301d764..c5cc08ad18eb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3p.cpp @@ -788,6 +788,12 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFmaMixloF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixloF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_fma_mixlo_f16_vop3p(*this, wf); } @@ -820,6 +826,12 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFmaMixhiF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixhiF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_fma_mixhi_f16_vop3p(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3p.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3p.h index 5bcc32ddeb1a..e8d480946fc0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3p.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/vop3p.h @@ -272,6 +272,7 @@ class VFmaMixloF16Vop3p : public Vop3p { public: VFmaMixloF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -282,6 +283,7 @@ class VFmaMixhiF16Vop3p : public Vop3p { public: VFmaMixhiF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/ds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/ds.cpp index ab91775e5727..f06b11462d85 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/ds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/ds.cpp @@ -1866,6 +1866,12 @@ DsReadI8Ds::DsReadI8Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadI8Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadI8Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -1891,6 +1897,12 @@ DsReadU8Ds::DsReadU8Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU8Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU8Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -1915,6 +1927,12 @@ DsReadI16Ds::DsReadI16Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadI16Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadI16Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -1940,6 +1958,12 @@ DsReadU16Ds::DsReadU16Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU16Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU16Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -3909,6 +3933,12 @@ DsReadU8D16Ds::DsReadU8D16Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU8D16Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU8D16Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -3935,6 +3965,12 @@ DsReadU8D16HiDs::DsReadU8D16HiDs(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU8D16HiDs::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU8D16HiDs::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -3961,6 +3997,12 @@ DsReadI8D16Ds::DsReadI8D16Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadI8D16Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadI8D16Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -3988,6 +4030,12 @@ DsReadI8D16HiDs::DsReadI8D16HiDs(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadI8D16HiDs::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadI8D16HiDs::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -4015,6 +4063,12 @@ DsReadU16D16Ds::DsReadU16D16Ds(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU16D16Ds::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU16D16Ds::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); @@ -4041,6 +4095,12 @@ DsReadU16D16HiDs::DsReadU16D16HiDs(const MachineInst *inst) flags_ |= MEMORY_OP; } +void DsReadU16D16HiDs::implicit_uses(RegisterSet &uses) const { + Ds::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void DsReadU16D16HiDs::execute_impl(amdgpu::Wavefront &wf) { if (inst_.gds) throw util::UnimplementedInst(mnemonic()); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/ds.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/ds.h index 7f71e1814cc1..8891fa431e3e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/ds.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/ds.h @@ -479,6 +479,7 @@ class DsReadI8Ds : public Ds { public: DsReadI8Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -487,6 +488,7 @@ class DsReadU8Ds : public Ds { public: DsReadU8Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -495,6 +497,7 @@ class DsReadI16Ds : public Ds { public: DsReadI16Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -503,6 +506,7 @@ class DsReadU16Ds : public Ds { public: DsReadU16Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -941,6 +945,7 @@ class DsReadU8D16Ds : public Ds { public: DsReadU8D16Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -949,6 +954,7 @@ class DsReadU8D16HiDs : public Ds { public: DsReadU8D16HiDs(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -957,6 +963,7 @@ class DsReadI8D16Ds : public Ds { public: DsReadI8D16Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -965,6 +972,7 @@ class DsReadI8D16HiDs : public Ds { public: DsReadI8D16HiDs(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -973,6 +981,7 @@ class DsReadU16D16Ds : public Ds { public: DsReadU16D16Ds(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; @@ -981,6 +990,7 @@ class DsReadU16D16HiDs : public Ds { public: DsReadU16D16HiDs(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand addr; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/sopk.cpp index cb4f1badee8f..a26f4e8424a0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/sopk.cpp @@ -326,6 +326,12 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregB32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregB32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; @@ -357,6 +363,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregImm32B32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregImm32B32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/sopk.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/sopk.h index ba2b2afad62e..9875d9904b28 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/sopk.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/sopk.h @@ -161,6 +161,7 @@ class SSetregB32Sopk : public Sopk { public: SSetregB32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; Operand sdst; }; @@ -169,6 +170,7 @@ class SSetregImm32B32Sopk : public Sopk { public: SSetregImm32B32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop1.cpp index 23d3cf1247fa..a698ecc4b3a3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop1.cpp @@ -1218,6 +1218,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } } +void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7776,6 +7782,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } } +void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7908,6 +7920,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } } +void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8040,6 +8058,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } } +void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8172,6 +8196,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } } +void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8304,6 +8334,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } } +void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8448,6 +8484,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } } +void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8592,6 +8634,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } } +void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8736,6 +8784,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } } +void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8880,6 +8934,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } } +void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9024,6 +9084,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } } +void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9168,6 +9234,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } } +void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9312,6 +9384,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } } +void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9456,6 +9534,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } } +void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9600,6 +9684,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } } +void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9744,6 +9834,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } } +void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9888,6 +9984,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } } +void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10032,6 +10134,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } } +void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10176,6 +10284,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } } +void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10372,6 +10486,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } } +void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10516,6 +10636,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } } +void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop1.h index ed137c447e8c..06eba5d40b43 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop1.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop1 : public Vop1 { public: VCvtF16F32Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -476,6 +477,7 @@ class VCvtF16U16Vop1 : public Vop1 { public: VCvtF16U16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -484,6 +486,7 @@ class VCvtF16I16Vop1 : public Vop1 { public: VCvtF16I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -492,6 +495,7 @@ class VCvtU16F16Vop1 : public Vop1 { public: VCvtU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -500,6 +504,7 @@ class VCvtI16F16Vop1 : public Vop1 { public: VCvtI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -508,6 +513,7 @@ class VRcpF16Vop1 : public Vop1 { public: VRcpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -516,6 +522,7 @@ class VSqrtF16Vop1 : public Vop1 { public: VSqrtF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -524,6 +531,7 @@ class VRsqF16Vop1 : public Vop1 { public: VRsqF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -532,6 +540,7 @@ class VLogF16Vop1 : public Vop1 { public: VLogF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -540,6 +549,7 @@ class VExpF16Vop1 : public Vop1 { public: VExpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -548,6 +558,7 @@ class VFrexpMantF16Vop1 : public Vop1 { public: VFrexpMantF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -556,6 +567,7 @@ class VFrexpExpI16F16Vop1 : public Vop1 { public: VFrexpExpI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -564,6 +576,7 @@ class VFloorF16Vop1 : public Vop1 { public: VFloorF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -572,6 +585,7 @@ class VCeilF16Vop1 : public Vop1 { public: VCeilF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -580,6 +594,7 @@ class VTruncF16Vop1 : public Vop1 { public: VTruncF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -588,6 +603,7 @@ class VRndneF16Vop1 : public Vop1 { public: VRndneF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -596,6 +612,7 @@ class VFractF16Vop1 : public Vop1 { public: VFractF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -604,6 +621,7 @@ class VSinF16Vop1 : public Vop1 { public: VSinF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -612,6 +630,7 @@ class VCosF16Vop1 : public Vop1 { public: VCosF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -628,6 +647,7 @@ class VCvtNormI16F16Vop1 : public Vop1 { public: VCvtNormI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -636,6 +656,7 @@ class VCvtNormU16F16Vop1 : public Vop1 { public: VCvtNormU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop2.cpp index fd3a6510382b..db8cad6f1004 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop2.cpp @@ -5234,6 +5234,12 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } } +void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5385,6 +5391,12 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } } +void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5536,6 +5548,12 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } } +void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5687,6 +5705,12 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } } +void VMulF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5839,6 +5863,12 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) } } +void VFmacF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5992,6 +6022,12 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VFmamkF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmamkF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6145,6 +6181,12 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VFmaakF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaakF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6296,6 +6338,12 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } } +void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6447,6 +6495,12 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } } +void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6598,6 +6652,12 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } } +void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop2.h index 3bca40735dc0..b1aac8eb8ebc 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop2.h @@ -344,6 +344,7 @@ class VAddF16Vop2 : public Vop2 { public: VAddF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -353,6 +354,7 @@ class VSubF16Vop2 : public Vop2 { public: VSubF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -362,6 +364,7 @@ class VSubrevF16Vop2 : public Vop2 { public: VSubrevF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -371,6 +374,7 @@ class VMulF16Vop2 : public Vop2 { public: VMulF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -380,6 +384,7 @@ class VFmacF16Vop2 : public Vop2 { public: VFmacF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -389,6 +394,7 @@ class VFmamkF16Vop2 : public Vop2 { public: VFmamkF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -399,6 +405,7 @@ class VFmaakF16Vop2 : public Vop2 { public: VFmaakF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -409,6 +416,7 @@ class VMaxF16Vop2 : public Vop2 { public: VMaxF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -418,6 +426,7 @@ class VMinF16Vop2 : public Vop2 { public: VMinF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -427,6 +436,7 @@ class VLdexpF16Vop2 : public Vop2 { public: VLdexpF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3.cpp index 6cc23a7eb52e..f8228e03b147 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3.cpp @@ -274,6 +274,12 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_f16_f32_vop3(*this, wf); } @@ -1180,6 +1186,12 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtF16U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_f16_u16_vop3(*this, wf); } @@ -1199,6 +1211,12 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtF16I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_f16_i16_vop3(*this, wf); } @@ -1218,6 +1236,12 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_u16_f16_vop3(*this, wf); } @@ -1237,6 +1261,12 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_i16_f16_vop3(*this, wf); } @@ -1255,6 +1285,12 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VRcpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_rcp_f16_vop3(*this, wf); } VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) @@ -1271,6 +1307,12 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSqrtF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_sqrt_f16_vop3(*this, wf); } @@ -1289,6 +1331,12 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VRsqF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_rsq_f16_vop3(*this, wf); } VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) @@ -1305,6 +1353,12 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VLogF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_log_f16_vop3(*this, wf); } VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) @@ -1321,6 +1375,12 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VExpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_exp_f16_vop3(*this, wf); } VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) @@ -1338,6 +1398,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFrexpMantF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_frexp_mant_f16_vop3(*this, wf); } @@ -1357,6 +1423,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFrexpExpI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_frexp_exp_i16_f16_vop3(*this, wf); } @@ -1376,6 +1448,12 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFloorF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_floor_f16_vop3(*this, wf); } @@ -1394,6 +1472,12 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCeilF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_ceil_f16_vop3(*this, wf); } @@ -1413,6 +1497,12 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VTruncF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_trunc_f16_vop3(*this, wf); } @@ -1432,6 +1522,12 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VRndneF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_rndne_f16_vop3(*this, wf); } @@ -1451,6 +1547,12 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFractF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_fract_f16_vop3(*this, wf); } @@ -1469,6 +1571,12 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_sin_f16_vop3(*this, wf); } VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) @@ -1485,6 +1593,12 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCosF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cos_f16_vop3(*this, wf); } VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) @@ -1522,6 +1636,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtNormI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_norm_i16_f16_vop3(*this, wf); } @@ -1541,6 +1661,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VCvtNormU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_cvt_norm_u16_f16_vop3(*this, wf); } @@ -2296,6 +2422,12 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VAddF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_add_f16_vop3(*this, wf); } VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) @@ -2318,6 +2450,12 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSubF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_sub_f16_vop3(*this, wf); } VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) @@ -2341,6 +2479,12 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSubrevF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_subrev_f16_vop3(*this, wf); } @@ -2365,6 +2509,12 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMulF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mul_f16_vop3(*this, wf); } VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) @@ -2388,6 +2538,12 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFmacF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_fmac_f16_vop3(*this, wf); } @@ -2412,6 +2568,12 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMaxF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max_f16_vop3(*this, wf); } VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) @@ -2434,6 +2596,12 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min_f16_vop3(*this, wf); } VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) @@ -2457,6 +2625,12 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VLdexpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_ldexp_f16_vop3(*this, wf); } @@ -3986,6 +4160,12 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VAddNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_add_nc_u16_vop3(*this, wf); } @@ -4011,6 +4191,12 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSubNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_sub_nc_u16_vop3(*this, wf); } @@ -4036,6 +4222,12 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMulLoU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mul_lo_u16_vop3(*this, wf); } @@ -4061,6 +4253,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VLshrrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_lshrrev_b16_vop3(*this, wf); } @@ -4086,6 +4284,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VAshrrevI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_ashrrev_i16_vop3(*this, wf); } @@ -4110,6 +4314,12 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMaxU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max_u16_vop3(*this, wf); } VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) @@ -4132,6 +4342,12 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMaxI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max_i16_vop3(*this, wf); } VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) @@ -4154,6 +4370,12 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMinU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min_u16_vop3(*this, wf); } VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) @@ -4176,6 +4398,12 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMinI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min_i16_vop3(*this, wf); } VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) @@ -4199,6 +4427,12 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VAddNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_add_nc_i16_vop3(*this, wf); } @@ -4224,6 +4458,12 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VSubNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_sub_nc_i16_vop3(*this, wf); } @@ -4326,6 +4566,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VLshlrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_lshlrev_b16_vop3(*this, wf); } @@ -4356,6 +4602,12 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMadU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadU16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_u16_vop3(*this, wf); } VInterpP1llF16Vop3::VInterpP1llF16Vop3(const MachineInst *inst) @@ -4562,6 +4814,12 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFmaF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_fma_f16_vop3(*this, wf); } VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) @@ -4590,6 +4848,12 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMin3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min3_f16_vop3(*this, wf); } @@ -4620,6 +4884,12 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMin3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min3_i16_vop3(*this, wf); } @@ -4650,6 +4920,12 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMin3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_min3_u16_vop3(*this, wf); } @@ -4680,6 +4956,12 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMax3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max3_f16_vop3(*this, wf); } @@ -4710,6 +4992,12 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMax3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max3_i16_vop3(*this, wf); } @@ -4740,6 +5028,12 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMax3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_max3_u16_vop3(*this, wf); } @@ -4770,6 +5064,12 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMed3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_med3_f16_vop3(*this, wf); } @@ -4800,6 +5100,12 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMed3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_med3_i16_vop3(*this, wf); } @@ -4830,6 +5136,12 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMed3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_med3_u16_vop3(*this, wf); } @@ -4861,6 +5173,12 @@ VInterpP2F16Vop3::VInterpP2F16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VInterpP2F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VInterpP2F16Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -4892,6 +5210,12 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VMadI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadI16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_mad_i16_vop3(*this, wf); } VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) @@ -4921,6 +5245,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VDivFixupF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupF16Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_div_fixup_f16_vop3(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3.h index 4bc66d00b72e..7c37e88763b7 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3.h @@ -115,6 +115,7 @@ class VCvtF16F32Vop3 : public Vop3 { public: VCvtF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -503,6 +504,7 @@ class VCvtF16U16Vop3 : public Vop3 { public: VCvtF16U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -511,6 +513,7 @@ class VCvtF16I16Vop3 : public Vop3 { public: VCvtF16I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -519,6 +522,7 @@ class VCvtU16F16Vop3 : public Vop3 { public: VCvtU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -527,6 +531,7 @@ class VCvtI16F16Vop3 : public Vop3 { public: VCvtI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -535,6 +540,7 @@ class VRcpF16Vop3 : public Vop3 { public: VRcpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -543,6 +549,7 @@ class VSqrtF16Vop3 : public Vop3 { public: VSqrtF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -551,6 +558,7 @@ class VRsqF16Vop3 : public Vop3 { public: VRsqF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -559,6 +567,7 @@ class VLogF16Vop3 : public Vop3 { public: VLogF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -567,6 +576,7 @@ class VExpF16Vop3 : public Vop3 { public: VExpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -575,6 +585,7 @@ class VFrexpMantF16Vop3 : public Vop3 { public: VFrexpMantF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -583,6 +594,7 @@ class VFrexpExpI16F16Vop3 : public Vop3 { public: VFrexpExpI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -591,6 +603,7 @@ class VFloorF16Vop3 : public Vop3 { public: VFloorF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -599,6 +612,7 @@ class VCeilF16Vop3 : public Vop3 { public: VCeilF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -607,6 +621,7 @@ class VTruncF16Vop3 : public Vop3 { public: VTruncF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -615,6 +630,7 @@ class VRndneF16Vop3 : public Vop3 { public: VRndneF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -623,6 +639,7 @@ class VFractF16Vop3 : public Vop3 { public: VFractF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -631,6 +648,7 @@ class VSinF16Vop3 : public Vop3 { public: VSinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -639,6 +657,7 @@ class VCosF16Vop3 : public Vop3 { public: VCosF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -655,6 +674,7 @@ class VCvtNormI16F16Vop3 : public Vop3 { public: VCvtNormI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -663,6 +683,7 @@ class VCvtNormU16F16Vop3 : public Vop3 { public: VCvtNormU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -933,6 +954,7 @@ class VAddF16Vop3 : public Vop3 { public: VAddF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -942,6 +964,7 @@ class VSubF16Vop3 : public Vop3 { public: VSubF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -951,6 +974,7 @@ class VSubrevF16Vop3 : public Vop3 { public: VSubrevF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -960,6 +984,7 @@ class VMulF16Vop3 : public Vop3 { public: VMulF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -969,6 +994,7 @@ class VFmacF16Vop3 : public Vop3 { public: VFmacF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -978,6 +1004,7 @@ class VMaxF16Vop3 : public Vop3 { public: VMaxF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -987,6 +1014,7 @@ class VMinF16Vop3 : public Vop3 { public: VMinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -996,6 +1024,7 @@ class VLdexpF16Vop3 : public Vop3 { public: VLdexpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1503,6 +1532,7 @@ class VAddNcU16Vop3 : public Vop3 { public: VAddNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1512,6 +1542,7 @@ class VSubNcU16Vop3 : public Vop3 { public: VSubNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1521,6 +1552,7 @@ class VMulLoU16Vop3 : public Vop3 { public: VMulLoU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1530,6 +1562,7 @@ class VLshrrevB16Vop3 : public Vop3 { public: VLshrrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1539,6 +1572,7 @@ class VAshrrevI16Vop3 : public Vop3 { public: VAshrrevI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1548,6 +1582,7 @@ class VMaxU16Vop3 : public Vop3 { public: VMaxU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1557,6 +1592,7 @@ class VMaxI16Vop3 : public Vop3 { public: VMaxI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1566,6 +1602,7 @@ class VMinU16Vop3 : public Vop3 { public: VMinU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1575,6 +1612,7 @@ class VMinI16Vop3 : public Vop3 { public: VMinI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1584,6 +1622,7 @@ class VAddNcI16Vop3 : public Vop3 { public: VAddNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1593,6 +1632,7 @@ class VSubNcI16Vop3 : public Vop3 { public: VSubNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1629,6 +1669,7 @@ class VLshlrevB16Vop3 : public Vop3 { public: VLshlrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1638,6 +1679,7 @@ class VMadU16Vop3 : public Vop3 { public: VMadU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1707,6 +1749,7 @@ class VFmaF16Vop3 : public Vop3 { public: VFmaF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1717,6 +1760,7 @@ class VMin3F16Vop3 : public Vop3 { public: VMin3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1727,6 +1771,7 @@ class VMin3I16Vop3 : public Vop3 { public: VMin3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1737,6 +1782,7 @@ class VMin3U16Vop3 : public Vop3 { public: VMin3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1747,6 +1793,7 @@ class VMax3F16Vop3 : public Vop3 { public: VMax3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1757,6 +1804,7 @@ class VMax3I16Vop3 : public Vop3 { public: VMax3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1767,6 +1815,7 @@ class VMax3U16Vop3 : public Vop3 { public: VMax3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1777,6 +1826,7 @@ class VMed3F16Vop3 : public Vop3 { public: VMed3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1787,6 +1837,7 @@ class VMed3I16Vop3 : public Vop3 { public: VMed3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1797,6 +1848,7 @@ class VMed3U16Vop3 : public Vop3 { public: VMed3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1807,6 +1859,7 @@ class VInterpP2F16Vop3 : public Vop3 { public: VInterpP2F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src1; Operand src0; @@ -1817,6 +1870,7 @@ class VMadI16Vop3 : public Vop3 { public: VMadI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1827,6 +1881,7 @@ class VDivFixupF16Vop3 : public Vop3 { public: VDivFixupF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3p.cpp index 416e4e178422..e2a2f41084a3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3p.cpp @@ -788,6 +788,12 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFmaMixloF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixloF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_fma_mixlo_f16_vop3p(*this, wf); } @@ -820,6 +826,12 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void VFmaMixhiF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixhiF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_fma_mixhi_f16_vop3p(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3p.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3p.h index c3f05c2e87c2..5a52d4beefc6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3p.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/vop3p.h @@ -272,6 +272,7 @@ class VFmaMixloF16Vop3p : public Vop3p { public: VFmaMixloF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -282,6 +283,7 @@ class VFmaMixhiF16Vop3p : public Vop3p { public: VFmaMixhiF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/sopk.cpp index af4c81e563e6..9d7745067154 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/sopk.cpp @@ -326,6 +326,12 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregB32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregB32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; @@ -357,6 +363,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregImm32B32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregImm32B32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/sopk.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/sopk.h index 14b9d395e083..3ffbf0de0a7a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/sopk.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/sopk.h @@ -161,6 +161,7 @@ class SSetregB32Sopk : public Sopk { public: SSetregB32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; Operand sdst; }; @@ -169,6 +170,7 @@ class SSetregImm32B32Sopk : public Sopk { public: SSetregImm32B32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vinterp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vinterp.cpp index 1f54c416fdb6..e4d4eb581f86 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vinterp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vinterp.cpp @@ -88,6 +88,12 @@ VInterpP2F16F32Vinterp::VInterpP2F16F32Vinterp(const MachineInst *inst) num_dst_ = 1; } +void VInterpP2F16F32Vinterp::implicit_uses(RegisterSet &uses) const { + Vinterp::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VInterpP2F16F32Vinterp::execute_impl(amdgpu::Wavefront &wf) { (void)wf; // Interpolation/LDS-direct: no-op in compute simulation. } @@ -126,6 +132,12 @@ VInterpP2RtzF16F32Vinterp::VInterpP2RtzF16F32Vinterp(const MachineInst *inst) num_dst_ = 1; } +void VInterpP2RtzF16F32Vinterp::implicit_uses(RegisterSet &uses) const { + Vinterp::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VInterpP2RtzF16F32Vinterp::execute_impl(amdgpu::Wavefront &wf) { (void)wf; // Interpolation/LDS-direct: no-op in compute simulation. } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vinterp.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vinterp.h index 90e23760d072..0aa24c9f89f4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vinterp.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vinterp.h @@ -48,6 +48,7 @@ class VInterpP2F16F32Vinterp : public Vinterp { public: VInterpP2F16F32Vinterp(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -68,6 +69,7 @@ class VInterpP2RtzF16F32Vinterp : public Vinterp { public: VInterpP2RtzF16F32Vinterp(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop1.cpp index ef5540349434..f537560ba209 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop1.cpp @@ -1083,6 +1083,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } } +void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -3235,6 +3241,12 @@ VMovB16Vop1::VMovB16Vop1(const MachineInst *inst) } } +void VMovB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMovB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6998,6 +7010,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } } +void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7128,6 +7146,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } } +void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7258,6 +7282,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } } +void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7394,6 +7424,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } } +void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7532,6 +7568,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } } +void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7675,6 +7717,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } } +void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7818,6 +7866,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } } +void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7961,6 +8015,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } } +void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8104,6 +8164,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } } +void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8247,6 +8313,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } } +void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8393,6 +8465,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } } +void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8540,6 +8618,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } } +void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8682,6 +8766,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } } +void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8824,6 +8914,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } } +void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8966,6 +9062,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } } +void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9108,6 +9210,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } } +void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9252,6 +9360,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } } +void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9395,6 +9509,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } } +void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9537,6 +9657,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } } +void VSatPkU8I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -9575,6 +9701,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } } +void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9722,6 +9854,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } } +void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10001,6 +10139,14 @@ VSwapB16Vop1::VSwapB16Vop1(const MachineInst *inst) } } +void VSwapB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); + if (auto r = src0.to_register_ref()) + uses.expand(*r); +} + void VSwapB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10287,6 +10433,12 @@ VNotB16Vop1::VNotB16Vop1(const MachineInst *inst) } } +void VNotB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VNotB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop1.h index ca03cb438291..153bfa58fdfd 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop1.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop1 : public Vop1 { public: VCvtF16F32Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -230,6 +231,7 @@ class VMovB16Vop1 : public Vop1 { public: VMovB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +480,7 @@ class VCvtF16U16Vop1 : public Vop1 { public: VCvtF16U16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +489,7 @@ class VCvtF16I16Vop1 : public Vop1 { public: VCvtF16I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +498,7 @@ class VCvtU16F16Vop1 : public Vop1 { public: VCvtU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +507,7 @@ class VCvtI16F16Vop1 : public Vop1 { public: VCvtI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +516,7 @@ class VRcpF16Vop1 : public Vop1 { public: VRcpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +525,7 @@ class VSqrtF16Vop1 : public Vop1 { public: VSqrtF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +534,7 @@ class VRsqF16Vop1 : public Vop1 { public: VRsqF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +543,7 @@ class VLogF16Vop1 : public Vop1 { public: VLogF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +552,7 @@ class VExpF16Vop1 : public Vop1 { public: VExpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +561,7 @@ class VFrexpMantF16Vop1 : public Vop1 { public: VFrexpMantF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +570,7 @@ class VFrexpExpI16F16Vop1 : public Vop1 { public: VFrexpExpI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +579,7 @@ class VFloorF16Vop1 : public Vop1 { public: VFloorF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +588,7 @@ class VCeilF16Vop1 : public Vop1 { public: VCeilF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +597,7 @@ class VTruncF16Vop1 : public Vop1 { public: VTruncF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +606,7 @@ class VRndneF16Vop1 : public Vop1 { public: VRndneF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +615,7 @@ class VFractF16Vop1 : public Vop1 { public: VFractF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +624,7 @@ class VSinF16Vop1 : public Vop1 { public: VSinF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +633,7 @@ class VCosF16Vop1 : public Vop1 { public: VCosF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -622,6 +642,7 @@ class VSatPkU8I16Vop1 : public Vop1 { public: VSatPkU8I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -630,6 +651,7 @@ class VCvtNormI16F16Vop1 : public Vop1 { public: VCvtNormI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -638,6 +660,7 @@ class VCvtNormU16F16Vop1 : public Vop1 { public: VCvtNormU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -654,6 +677,7 @@ class VSwapB16Vop1 : public Vop1 { public: VSwapB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -678,6 +702,7 @@ class VNotB16Vop1 : public Vop1 { public: VNotB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop2.cpp index 3a7f77c96e48..9255d46b1200 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop2.cpp @@ -4475,6 +4475,12 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } } +void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4624,6 +4630,12 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } } +void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4773,6 +4785,12 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } } +void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4922,6 +4940,12 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } } +void VMulF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5073,6 +5097,12 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) } } +void VFmacF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5228,6 +5258,12 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VFmamkF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmamkF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5374,6 +5410,12 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VFmaakF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaakF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5518,6 +5560,12 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } } +void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5667,6 +5715,12 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } } +void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5816,6 +5870,12 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } } +void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop2.h index 6170ecd035c2..b98e4f207998 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop2.h @@ -335,6 +335,7 @@ class VAddF16Vop2 : public Vop2 { public: VAddF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -344,6 +345,7 @@ class VSubF16Vop2 : public Vop2 { public: VSubF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -353,6 +355,7 @@ class VSubrevF16Vop2 : public Vop2 { public: VSubrevF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -362,6 +365,7 @@ class VMulF16Vop2 : public Vop2 { public: VMulF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -371,6 +375,7 @@ class VFmacF16Vop2 : public Vop2 { public: VFmacF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -380,6 +385,7 @@ class VFmamkF16Vop2 : public Vop2 { public: VFmamkF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -390,6 +396,7 @@ class VFmaakF16Vop2 : public Vop2 { public: VFmaakF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -400,6 +407,7 @@ class VMaxF16Vop2 : public Vop2 { public: VMaxF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -409,6 +417,7 @@ class VMinF16Vop2 : public Vop2 { public: VMinF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -418,6 +427,7 @@ class VLdexpF16Vop2 : public Vop2 { public: VLdexpF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3.cpp index c11a92b27922..c852b2ab6946 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3.cpp @@ -606,6 +606,12 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } } +void VCvtF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -1755,6 +1761,12 @@ VMovB16Vop3::VMovB16Vop3(const MachineInst *inst) } } +void VMovB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMovB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3707,6 +3719,12 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } } +void VCvtF16U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3782,6 +3800,12 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } } +void VCvtF16I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3857,6 +3881,12 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } } +void VCvtU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3938,6 +3968,12 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } } +void VCvtI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4020,6 +4056,12 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } } +void VRcpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4118,6 +4160,12 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } } +void VSqrtF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4221,6 +4269,12 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } } +void VRsqF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4319,6 +4373,12 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } } +void VLogF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4417,6 +4477,12 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } } +void VExpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4516,6 +4582,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } } +void VFrexpMantF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4621,6 +4693,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } } +void VFrexpExpI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4729,6 +4807,12 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } } +void VFloorF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4827,6 +4911,12 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } } +void VCeilF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4926,6 +5016,12 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } } +void VTruncF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5025,6 +5121,12 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } } +void VRndneF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5124,6 +5226,12 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } } +void VFractF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5225,6 +5333,12 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } } +void VSinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5319,6 +5433,12 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } } +void VCosF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5414,6 +5534,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } } +void VSatPkU8I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -5451,6 +5577,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } } +void VCvtNormI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5531,6 +5663,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } } +void VCvtNormU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5610,6 +5748,12 @@ VNotB16Vop3::VNotB16Vop3(const MachineInst *inst) } } +void VNotB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VNotB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -7945,6 +8089,12 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } } +void VAddF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8063,6 +8213,12 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } } +void VSubF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8182,6 +8338,12 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } } +void VSubrevF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8300,6 +8462,12 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } } +void VMulF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8419,6 +8587,12 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) } } +void VFmacF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8540,6 +8714,12 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) } } +void VMaxF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8660,6 +8840,12 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) } } +void VMinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8781,6 +8967,12 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } } +void VLdexpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -11889,6 +12081,12 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } } +void VMadU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12292,6 +12490,12 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } } +void VFmaF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12425,6 +12629,12 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) } } +void VMin3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12559,6 +12769,12 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } } +void VMin3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12665,6 +12881,12 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } } +void VMin3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12768,6 +12990,12 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) } } +void VMax3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12902,6 +13130,12 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } } +void VMax3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13008,6 +13242,12 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } } +void VMax3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13111,6 +13351,12 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) } } +void VMed3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13247,6 +13493,12 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } } +void VMed3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13355,6 +13607,12 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } } +void VMed3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13462,6 +13720,12 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } } +void VMadI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13555,6 +13819,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } } +void VDivFixupF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14408,6 +14678,12 @@ VCndmaskB16Vop3::VCndmaskB16Vop3(const MachineInst *inst) } } +void VCndmaskB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCndmaskB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14660,6 +14936,12 @@ VMaxminF16Vop3::VMaxminF16Vop3(const MachineInst *inst) } } +void VMaxminF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxminF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14795,6 +15077,12 @@ VMinmaxF16Vop3::VMinmaxF16Vop3(const MachineInst *inst) } } +void VMinmaxF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinmaxF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15246,6 +15534,12 @@ VDot2F16F16Vop3::VDot2F16F16Vop3(const MachineInst *inst) } } +void VDot2F16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDot2F16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15369,6 +15663,12 @@ VDot2Bf16Bf16Vop3::VDot2Bf16Bf16Vop3(const MachineInst *inst) } } +void VDot2Bf16Bf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDot2Bf16Bf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15486,6 +15786,12 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) } } +void VAddNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15572,6 +15878,12 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) } } +void VSubNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15658,6 +15970,12 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } } +void VMulLoU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15912,6 +16230,12 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } } +void VMaxU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15998,6 +16322,12 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } } +void VMaxI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16084,6 +16414,12 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } } +void VMinU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16170,6 +16506,12 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } } +void VMinI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16257,6 +16599,12 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) } } +void VAddNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16342,6 +16690,12 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) } } +void VSubNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18135,6 +18489,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } } +void VLshlrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18218,6 +18578,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } } +void VLshrrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18301,6 +18667,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } } +void VAshrrevI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18754,6 +19126,12 @@ VAndB16Vop3::VAndB16Vop3(const MachineInst *inst) } } +void VAndB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAndB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18839,6 +19217,12 @@ VOrB16Vop3::VOrB16Vop3(const MachineInst *inst) } } +void VOrB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VOrB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18924,6 +19308,12 @@ VXorB16Vop3::VXorB16Vop3(const MachineInst *inst) } } +void VXorB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VXorB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3.h index 479813dbafa8..72968589516e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop3 : public Vop3 { public: VCvtF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -230,6 +231,7 @@ class VMovB16Vop3 : public Vop3 { public: VMovB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +480,7 @@ class VCvtF16U16Vop3 : public Vop3 { public: VCvtF16U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +489,7 @@ class VCvtF16I16Vop3 : public Vop3 { public: VCvtF16I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +498,7 @@ class VCvtU16F16Vop3 : public Vop3 { public: VCvtU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +507,7 @@ class VCvtI16F16Vop3 : public Vop3 { public: VCvtI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +516,7 @@ class VRcpF16Vop3 : public Vop3 { public: VRcpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +525,7 @@ class VSqrtF16Vop3 : public Vop3 { public: VSqrtF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +534,7 @@ class VRsqF16Vop3 : public Vop3 { public: VRsqF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +543,7 @@ class VLogF16Vop3 : public Vop3 { public: VLogF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +552,7 @@ class VExpF16Vop3 : public Vop3 { public: VExpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +561,7 @@ class VFrexpMantF16Vop3 : public Vop3 { public: VFrexpMantF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +570,7 @@ class VFrexpExpI16F16Vop3 : public Vop3 { public: VFrexpExpI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +579,7 @@ class VFloorF16Vop3 : public Vop3 { public: VFloorF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +588,7 @@ class VCeilF16Vop3 : public Vop3 { public: VCeilF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +597,7 @@ class VTruncF16Vop3 : public Vop3 { public: VTruncF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +606,7 @@ class VRndneF16Vop3 : public Vop3 { public: VRndneF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +615,7 @@ class VFractF16Vop3 : public Vop3 { public: VFractF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +624,7 @@ class VSinF16Vop3 : public Vop3 { public: VSinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +633,7 @@ class VCosF16Vop3 : public Vop3 { public: VCosF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -622,6 +642,7 @@ class VSatPkU8I16Vop3 : public Vop3 { public: VSatPkU8I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -630,6 +651,7 @@ class VCvtNormI16F16Vop3 : public Vop3 { public: VCvtNormI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -638,6 +660,7 @@ class VCvtNormU16F16Vop3 : public Vop3 { public: VCvtNormU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -646,6 +669,7 @@ class VNotB16Vop3 : public Vop3 { public: VNotB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -932,6 +956,7 @@ class VAddF16Vop3 : public Vop3 { public: VAddF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -941,6 +966,7 @@ class VSubF16Vop3 : public Vop3 { public: VSubF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -950,6 +976,7 @@ class VSubrevF16Vop3 : public Vop3 { public: VSubrevF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -959,6 +986,7 @@ class VMulF16Vop3 : public Vop3 { public: VMulF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -968,6 +996,7 @@ class VFmacF16Vop3 : public Vop3 { public: VFmacF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -977,6 +1006,7 @@ class VMaxF16Vop3 : public Vop3 { public: VMaxF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -986,6 +1016,7 @@ class VMinF16Vop3 : public Vop3 { public: VMinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -995,6 +1026,7 @@ class VLdexpF16Vop3 : public Vop3 { public: VLdexpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1394,6 +1426,7 @@ class VMadU16Vop3 : public Vop3 { public: VMadU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1444,6 +1477,7 @@ class VFmaF16Vop3 : public Vop3 { public: VFmaF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1454,6 +1488,7 @@ class VMin3F16Vop3 : public Vop3 { public: VMin3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1464,6 +1499,7 @@ class VMin3I16Vop3 : public Vop3 { public: VMin3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1474,6 +1510,7 @@ class VMin3U16Vop3 : public Vop3 { public: VMin3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1484,6 +1521,7 @@ class VMax3F16Vop3 : public Vop3 { public: VMax3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1494,6 +1532,7 @@ class VMax3I16Vop3 : public Vop3 { public: VMax3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1504,6 +1543,7 @@ class VMax3U16Vop3 : public Vop3 { public: VMax3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1514,6 +1554,7 @@ class VMed3F16Vop3 : public Vop3 { public: VMed3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1524,6 +1565,7 @@ class VMed3I16Vop3 : public Vop3 { public: VMed3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1534,6 +1576,7 @@ class VMed3U16Vop3 : public Vop3 { public: VMed3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1544,6 +1587,7 @@ class VMadI16Vop3 : public Vop3 { public: VMadI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1554,6 +1598,7 @@ class VDivFixupF16Vop3 : public Vop3 { public: VDivFixupF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1644,6 +1689,7 @@ class VCndmaskB16Vop3 : public Vop3 { public: VCndmaskB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1674,6 +1720,7 @@ class VMaxminF16Vop3 : public Vop3 { public: VMaxminF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1684,6 +1731,7 @@ class VMinmaxF16Vop3 : public Vop3 { public: VMinmaxF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1734,6 +1782,7 @@ class VDot2F16F16Vop3 : public Vop3 { public: VDot2F16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1744,6 +1793,7 @@ class VDot2Bf16Bf16Vop3 : public Vop3 { public: VDot2Bf16Bf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1754,6 +1804,7 @@ class VAddNcU16Vop3 : public Vop3 { public: VAddNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1763,6 +1814,7 @@ class VSubNcU16Vop3 : public Vop3 { public: VSubNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1772,6 +1824,7 @@ class VMulLoU16Vop3 : public Vop3 { public: VMulLoU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1799,6 +1852,7 @@ class VMaxU16Vop3 : public Vop3 { public: VMaxU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1808,6 +1862,7 @@ class VMaxI16Vop3 : public Vop3 { public: VMaxI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1817,6 +1872,7 @@ class VMinU16Vop3 : public Vop3 { public: VMinU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1826,6 +1882,7 @@ class VMinI16Vop3 : public Vop3 { public: VMinI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1835,6 +1892,7 @@ class VAddNcI16Vop3 : public Vop3 { public: VAddNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1844,6 +1902,7 @@ class VSubNcI16Vop3 : public Vop3 { public: VSubNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2060,6 +2119,7 @@ class VLshlrevB16Vop3 : public Vop3 { public: VLshlrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2069,6 +2129,7 @@ class VLshrrevB16Vop3 : public Vop3 { public: VLshrrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2078,6 +2139,7 @@ class VAshrrevI16Vop3 : public Vop3 { public: VAshrrevI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2132,6 +2194,7 @@ class VAndB16Vop3 : public Vop3 { public: VAndB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2141,6 +2204,7 @@ class VOrB16Vop3 : public Vop3 { public: VOrB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2150,6 +2214,7 @@ class VXorB16Vop3 : public Vop3 { public: VXorB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3p.cpp index 6fc77a9d941b..7fe231720f23 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3p.cpp @@ -2024,6 +2024,12 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) } } +void VFmaMixloF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixloF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2104,6 +2110,12 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) } } +void VFmaMixhiF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixhiF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3p.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3p.h index 21f803741004..6065a00015a1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3p.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/vop3p.h @@ -262,6 +262,7 @@ class VFmaMixloF16Vop3p : public Vop3p { public: VFmaMixloF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -272,6 +273,7 @@ class VFmaMixhiF16Vop3p : public Vop3p { public: VFmaMixhiF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop1.cpp index aaf5d9ece533..60287f2685b3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop1.cpp @@ -1426,6 +1426,12 @@ SCvtF16F32Sop1::SCvtF16F32Sop1(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SCvtF16F32Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SCvtF16F32Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_cvt_f16_f32_sop1(*this, wf); } @@ -1482,6 +1488,12 @@ SCeilF16Sop1::SCeilF16Sop1(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SCeilF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SCeilF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_ceil_f16_sop1(*this, wf); } @@ -1501,6 +1513,12 @@ SFloorF16Sop1::SFloorF16Sop1(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SFloorF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SFloorF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_floor_f16_sop1(*this, wf); } @@ -1520,6 +1538,12 @@ STruncF16Sop1::STruncF16Sop1(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void STruncF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void STruncF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_trunc_f16_sop1(*this, wf); } @@ -1539,6 +1563,12 @@ SRndneF16Sop1::SRndneF16Sop1(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SRndneF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SRndneF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_rndne_f16_sop1(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop1.h index ed317695787b..69a244c1eb35 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop1.h @@ -599,6 +599,7 @@ class SCvtF16F32Sop1 : public Sop1 { public: SCvtF16F32Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -623,6 +624,7 @@ class SCeilF16Sop1 : public Sop1 { public: SCeilF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -631,6 +633,7 @@ class SFloorF16Sop1 : public Sop1 { public: SFloorF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -639,6 +642,7 @@ class STruncF16Sop1 : public Sop1 { public: STruncF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -647,6 +651,7 @@ class SRndneF16Sop1 : public Sop1 { public: SRndneF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop2.cpp index 077e253325be..bfbef46c2e7c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop2.cpp @@ -1466,6 +1466,12 @@ SCvtPkRtzF16F32Sop2::SCvtPkRtzF16F32Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SCvtPkRtzF16F32Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SCvtPkRtzF16F32Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_cvt_pk_rtz_f16_f32_sop2(*this, wf); } @@ -1490,6 +1496,12 @@ SAddF16Sop2::SAddF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SAddF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SAddF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_add_f16_sop2(*this, wf); } SSubF16Sop2::SSubF16Sop2(const MachineInst *inst) @@ -1512,6 +1524,12 @@ SSubF16Sop2::SSubF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SSubF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SSubF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_sub_f16_sop2(*this, wf); } SMinF16Sop2::SMinF16Sop2(const MachineInst *inst) @@ -1534,6 +1552,12 @@ SMinF16Sop2::SMinF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SMinF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMinF16Sop2::execute_impl(amdgpu::Wavefront &wf) { float result = std::min(util::f16_to_f32(static_cast(ssrc0.read_scalar(wf))), util::f16_to_f32(static_cast(ssrc1.read_scalar(wf)))); @@ -1560,6 +1584,12 @@ SMaxF16Sop2::SMaxF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SMaxF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMaxF16Sop2::execute_impl(amdgpu::Wavefront &wf) { float result = std::max(util::f16_to_f32(static_cast(ssrc0.read_scalar(wf))), util::f16_to_f32(static_cast(ssrc1.read_scalar(wf)))); @@ -1586,6 +1616,12 @@ SMulF16Sop2::SMulF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SMulF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMulF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_mul_f16_sop2(*this, wf); } SFmacF16Sop2::SFmacF16Sop2(const MachineInst *inst) @@ -1609,6 +1645,12 @@ SFmacF16Sop2::SFmacF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SFmacF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SFmacF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_fmac_f16_sop2(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop2.h index bf958ed36060..14ebb4ef16cd 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sop2.h @@ -560,6 +560,7 @@ class SCvtPkRtzF16F32Sop2 : public Sop2 { public: SCvtPkRtzF16F32Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -569,6 +570,7 @@ class SAddF16Sop2 : public Sop2 { public: SAddF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -578,6 +580,7 @@ class SSubF16Sop2 : public Sop2 { public: SSubF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -587,6 +590,7 @@ class SMinF16Sop2 : public Sop2 { public: SMinF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -596,6 +600,7 @@ class SMaxF16Sop2 : public Sop2 { public: SMaxF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -605,6 +610,7 @@ class SMulF16Sop2 : public Sop2 { public: SMulF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -614,6 +620,7 @@ class SFmacF16Sop2 : public Sop2 { public: SFmacF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sopk.cpp index d8f4a55842d9..3642a3ca5aa6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sopk.cpp @@ -326,6 +326,12 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregB32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregB32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; @@ -357,6 +363,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregImm32B32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregImm32B32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sopk.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sopk.h index b839aba08387..e943a528e49a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sopk.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/sopk.h @@ -161,6 +161,7 @@ class SSetregB32Sopk : public Sopk { public: SSetregB32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; Operand sdst; }; @@ -169,6 +170,7 @@ class SSetregImm32B32Sopk : public Sopk { public: SSetregImm32B32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vinterp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vinterp.cpp index 7bd3a0a86ca7..7ecccd654568 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vinterp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vinterp.cpp @@ -88,6 +88,12 @@ VInterpP2F16F32Vinterp::VInterpP2F16F32Vinterp(const MachineInst *inst) num_dst_ = 1; } +void VInterpP2F16F32Vinterp::implicit_uses(RegisterSet &uses) const { + Vinterp::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VInterpP2F16F32Vinterp::execute_impl(amdgpu::Wavefront &wf) { (void)wf; // Interpolation/LDS-direct: no-op in compute simulation. } @@ -126,6 +132,12 @@ VInterpP2RtzF16F32Vinterp::VInterpP2RtzF16F32Vinterp(const MachineInst *inst) num_dst_ = 1; } +void VInterpP2RtzF16F32Vinterp::implicit_uses(RegisterSet &uses) const { + Vinterp::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VInterpP2RtzF16F32Vinterp::execute_impl(amdgpu::Wavefront &wf) { (void)wf; // Interpolation/LDS-direct: no-op in compute simulation. } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vinterp.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vinterp.h index 3cda5cbc3d94..ee60349703e8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vinterp.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vinterp.h @@ -48,6 +48,7 @@ class VInterpP2F16F32Vinterp : public Vinterp { public: VInterpP2F16F32Vinterp(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -68,6 +69,7 @@ class VInterpP2RtzF16F32Vinterp : public Vinterp { public: VInterpP2RtzF16F32Vinterp(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop1.cpp index d69edc3f18e6..3ba32b38973a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop1.cpp @@ -1083,6 +1083,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } } +void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -3235,6 +3241,12 @@ VMovB16Vop1::VMovB16Vop1(const MachineInst *inst) } } +void VMovB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMovB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6998,6 +7010,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } } +void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7128,6 +7146,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } } +void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7258,6 +7282,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } } +void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7394,6 +7424,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } } +void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7532,6 +7568,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } } +void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7675,6 +7717,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } } +void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7818,6 +7866,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } } +void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7961,6 +8015,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } } +void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8104,6 +8164,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } } +void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8247,6 +8313,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } } +void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8393,6 +8465,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } } +void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8540,6 +8618,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } } +void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8682,6 +8766,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } } +void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8824,6 +8914,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } } +void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8966,6 +9062,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } } +void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9108,6 +9210,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } } +void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9252,6 +9360,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } } +void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9395,6 +9509,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } } +void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9537,6 +9657,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } } +void VSatPkU8I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -9575,6 +9701,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } } +void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9722,6 +9854,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } } +void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10001,6 +10139,14 @@ VSwapB16Vop1::VSwapB16Vop1(const MachineInst *inst) } } +void VSwapB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); + if (auto r = src0.to_register_ref()) + uses.expand(*r); +} + void VSwapB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10287,6 +10433,12 @@ VNotB16Vop1::VNotB16Vop1(const MachineInst *inst) } } +void VNotB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VNotB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop1.h index 67c14692d86a..3bc8688d3180 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop1.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop1 : public Vop1 { public: VCvtF16F32Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -230,6 +231,7 @@ class VMovB16Vop1 : public Vop1 { public: VMovB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +480,7 @@ class VCvtF16U16Vop1 : public Vop1 { public: VCvtF16U16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +489,7 @@ class VCvtF16I16Vop1 : public Vop1 { public: VCvtF16I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +498,7 @@ class VCvtU16F16Vop1 : public Vop1 { public: VCvtU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +507,7 @@ class VCvtI16F16Vop1 : public Vop1 { public: VCvtI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +516,7 @@ class VRcpF16Vop1 : public Vop1 { public: VRcpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +525,7 @@ class VSqrtF16Vop1 : public Vop1 { public: VSqrtF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +534,7 @@ class VRsqF16Vop1 : public Vop1 { public: VRsqF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +543,7 @@ class VLogF16Vop1 : public Vop1 { public: VLogF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +552,7 @@ class VExpF16Vop1 : public Vop1 { public: VExpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +561,7 @@ class VFrexpMantF16Vop1 : public Vop1 { public: VFrexpMantF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +570,7 @@ class VFrexpExpI16F16Vop1 : public Vop1 { public: VFrexpExpI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +579,7 @@ class VFloorF16Vop1 : public Vop1 { public: VFloorF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +588,7 @@ class VCeilF16Vop1 : public Vop1 { public: VCeilF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +597,7 @@ class VTruncF16Vop1 : public Vop1 { public: VTruncF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +606,7 @@ class VRndneF16Vop1 : public Vop1 { public: VRndneF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +615,7 @@ class VFractF16Vop1 : public Vop1 { public: VFractF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +624,7 @@ class VSinF16Vop1 : public Vop1 { public: VSinF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +633,7 @@ class VCosF16Vop1 : public Vop1 { public: VCosF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -622,6 +642,7 @@ class VSatPkU8I16Vop1 : public Vop1 { public: VSatPkU8I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -630,6 +651,7 @@ class VCvtNormI16F16Vop1 : public Vop1 { public: VCvtNormI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -638,6 +660,7 @@ class VCvtNormU16F16Vop1 : public Vop1 { public: VCvtNormU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -654,6 +677,7 @@ class VSwapB16Vop1 : public Vop1 { public: VSwapB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -678,6 +702,7 @@ class VNotB16Vop1 : public Vop1 { public: VNotB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop2.cpp index 8dc835eeceec..43264bb56b8c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop2.cpp @@ -4475,6 +4475,12 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } } +void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4624,6 +4630,12 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } } +void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4773,6 +4785,12 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } } +void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -4922,6 +4940,12 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } } +void VMulF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5073,6 +5097,12 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) } } +void VFmacF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5228,6 +5258,12 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VFmamkF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmamkF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5374,6 +5410,12 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VFmaakF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaakF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5518,6 +5560,12 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } } +void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5667,6 +5715,12 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } } +void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5816,6 +5870,12 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } } +void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop2.h index 4ea6b8c3d0c2..7c2842bf2b2d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop2.h @@ -335,6 +335,7 @@ class VAddF16Vop2 : public Vop2 { public: VAddF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -344,6 +345,7 @@ class VSubF16Vop2 : public Vop2 { public: VSubF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -353,6 +355,7 @@ class VSubrevF16Vop2 : public Vop2 { public: VSubrevF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -362,6 +365,7 @@ class VMulF16Vop2 : public Vop2 { public: VMulF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -371,6 +375,7 @@ class VFmacF16Vop2 : public Vop2 { public: VFmacF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -380,6 +385,7 @@ class VFmamkF16Vop2 : public Vop2 { public: VFmamkF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -390,6 +396,7 @@ class VFmaakF16Vop2 : public Vop2 { public: VFmaakF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -400,6 +407,7 @@ class VMaxF16Vop2 : public Vop2 { public: VMaxF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -409,6 +417,7 @@ class VMinF16Vop2 : public Vop2 { public: VMinF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -418,6 +427,7 @@ class VLdexpF16Vop2 : public Vop2 { public: VLdexpF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3.cpp index 0012e68e22e0..7e7b6e77bec8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3.cpp @@ -606,6 +606,12 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } } +void VCvtF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -1755,6 +1761,12 @@ VMovB16Vop3::VMovB16Vop3(const MachineInst *inst) } } +void VMovB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMovB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3707,6 +3719,12 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } } +void VCvtF16U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3782,6 +3800,12 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } } +void VCvtF16I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3857,6 +3881,12 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } } +void VCvtU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3938,6 +3968,12 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } } +void VCvtI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4020,6 +4056,12 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } } +void VRcpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4118,6 +4160,12 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } } +void VSqrtF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4221,6 +4269,12 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } } +void VRsqF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4319,6 +4373,12 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } } +void VLogF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4417,6 +4477,12 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } } +void VExpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4516,6 +4582,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } } +void VFrexpMantF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4621,6 +4693,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } } +void VFrexpExpI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4729,6 +4807,12 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } } +void VFloorF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4827,6 +4911,12 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } } +void VCeilF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4926,6 +5016,12 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } } +void VTruncF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5025,6 +5121,12 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } } +void VRndneF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5124,6 +5226,12 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } } +void VFractF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5225,6 +5333,12 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } } +void VSinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5319,6 +5433,12 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } } +void VCosF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5414,6 +5534,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } } +void VSatPkU8I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -5451,6 +5577,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } } +void VCvtNormI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5531,6 +5663,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } } +void VCvtNormU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5610,6 +5748,12 @@ VNotB16Vop3::VNotB16Vop3(const MachineInst *inst) } } +void VNotB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VNotB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -7945,6 +8089,12 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } } +void VAddF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8063,6 +8213,12 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } } +void VSubF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8182,6 +8338,12 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } } +void VSubrevF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8300,6 +8462,12 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } } +void VMulF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8419,6 +8587,12 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) } } +void VFmacF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8540,6 +8714,12 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) } } +void VMaxF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8660,6 +8840,12 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) } } +void VMinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8781,6 +8967,12 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } } +void VLdexpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -11889,6 +12081,12 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } } +void VMadU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12292,6 +12490,12 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } } +void VFmaF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12425,6 +12629,12 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) } } +void VMin3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12559,6 +12769,12 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } } +void VMin3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12665,6 +12881,12 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } } +void VMin3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12768,6 +12990,12 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) } } +void VMax3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12902,6 +13130,12 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } } +void VMax3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13008,6 +13242,12 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } } +void VMax3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13111,6 +13351,12 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) } } +void VMed3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13247,6 +13493,12 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } } +void VMed3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13355,6 +13607,12 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } } +void VMed3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13462,6 +13720,12 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } } +void VMadI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13555,6 +13819,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } } +void VDivFixupF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14408,6 +14678,12 @@ VCndmaskB16Vop3::VCndmaskB16Vop3(const MachineInst *inst) } } +void VCndmaskB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCndmaskB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14660,6 +14936,12 @@ VMaxminF16Vop3::VMaxminF16Vop3(const MachineInst *inst) } } +void VMaxminF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxminF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14795,6 +15077,12 @@ VMinmaxF16Vop3::VMinmaxF16Vop3(const MachineInst *inst) } } +void VMinmaxF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinmaxF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15246,6 +15534,12 @@ VDot2F16F16Vop3::VDot2F16F16Vop3(const MachineInst *inst) } } +void VDot2F16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDot2F16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15369,6 +15663,12 @@ VDot2Bf16Bf16Vop3::VDot2Bf16Bf16Vop3(const MachineInst *inst) } } +void VDot2Bf16Bf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDot2Bf16Bf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15486,6 +15786,12 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) } } +void VAddNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15572,6 +15878,12 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) } } +void VSubNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15658,6 +15970,12 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } } +void VMulLoU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15912,6 +16230,12 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } } +void VMaxU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15998,6 +16322,12 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } } +void VMaxI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16084,6 +16414,12 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } } +void VMinU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16170,6 +16506,12 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } } +void VMinI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16257,6 +16599,12 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) } } +void VAddNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16342,6 +16690,12 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) } } +void VSubNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18135,6 +18489,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } } +void VLshlrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18218,6 +18578,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } } +void VLshrrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18301,6 +18667,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } } +void VAshrrevI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18754,6 +19126,12 @@ VAndB16Vop3::VAndB16Vop3(const MachineInst *inst) } } +void VAndB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAndB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18839,6 +19217,12 @@ VOrB16Vop3::VOrB16Vop3(const MachineInst *inst) } } +void VOrB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VOrB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18924,6 +19308,12 @@ VXorB16Vop3::VXorB16Vop3(const MachineInst *inst) } } +void VXorB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VXorB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3.h index 1d39e61ebb89..bc3b6d478462 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop3 : public Vop3 { public: VCvtF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -230,6 +231,7 @@ class VMovB16Vop3 : public Vop3 { public: VMovB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +480,7 @@ class VCvtF16U16Vop3 : public Vop3 { public: VCvtF16U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +489,7 @@ class VCvtF16I16Vop3 : public Vop3 { public: VCvtF16I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +498,7 @@ class VCvtU16F16Vop3 : public Vop3 { public: VCvtU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +507,7 @@ class VCvtI16F16Vop3 : public Vop3 { public: VCvtI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +516,7 @@ class VRcpF16Vop3 : public Vop3 { public: VRcpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +525,7 @@ class VSqrtF16Vop3 : public Vop3 { public: VSqrtF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +534,7 @@ class VRsqF16Vop3 : public Vop3 { public: VRsqF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +543,7 @@ class VLogF16Vop3 : public Vop3 { public: VLogF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +552,7 @@ class VExpF16Vop3 : public Vop3 { public: VExpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +561,7 @@ class VFrexpMantF16Vop3 : public Vop3 { public: VFrexpMantF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +570,7 @@ class VFrexpExpI16F16Vop3 : public Vop3 { public: VFrexpExpI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +579,7 @@ class VFloorF16Vop3 : public Vop3 { public: VFloorF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +588,7 @@ class VCeilF16Vop3 : public Vop3 { public: VCeilF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +597,7 @@ class VTruncF16Vop3 : public Vop3 { public: VTruncF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +606,7 @@ class VRndneF16Vop3 : public Vop3 { public: VRndneF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +615,7 @@ class VFractF16Vop3 : public Vop3 { public: VFractF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +624,7 @@ class VSinF16Vop3 : public Vop3 { public: VSinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +633,7 @@ class VCosF16Vop3 : public Vop3 { public: VCosF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -622,6 +642,7 @@ class VSatPkU8I16Vop3 : public Vop3 { public: VSatPkU8I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -630,6 +651,7 @@ class VCvtNormI16F16Vop3 : public Vop3 { public: VCvtNormI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -638,6 +660,7 @@ class VCvtNormU16F16Vop3 : public Vop3 { public: VCvtNormU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -646,6 +669,7 @@ class VNotB16Vop3 : public Vop3 { public: VNotB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -932,6 +956,7 @@ class VAddF16Vop3 : public Vop3 { public: VAddF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -941,6 +966,7 @@ class VSubF16Vop3 : public Vop3 { public: VSubF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -950,6 +976,7 @@ class VSubrevF16Vop3 : public Vop3 { public: VSubrevF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -959,6 +986,7 @@ class VMulF16Vop3 : public Vop3 { public: VMulF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -968,6 +996,7 @@ class VFmacF16Vop3 : public Vop3 { public: VFmacF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -977,6 +1006,7 @@ class VMaxF16Vop3 : public Vop3 { public: VMaxF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -986,6 +1016,7 @@ class VMinF16Vop3 : public Vop3 { public: VMinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -995,6 +1026,7 @@ class VLdexpF16Vop3 : public Vop3 { public: VLdexpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1394,6 +1426,7 @@ class VMadU16Vop3 : public Vop3 { public: VMadU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1444,6 +1477,7 @@ class VFmaF16Vop3 : public Vop3 { public: VFmaF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1454,6 +1488,7 @@ class VMin3F16Vop3 : public Vop3 { public: VMin3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1464,6 +1499,7 @@ class VMin3I16Vop3 : public Vop3 { public: VMin3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1474,6 +1510,7 @@ class VMin3U16Vop3 : public Vop3 { public: VMin3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1484,6 +1521,7 @@ class VMax3F16Vop3 : public Vop3 { public: VMax3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1494,6 +1532,7 @@ class VMax3I16Vop3 : public Vop3 { public: VMax3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1504,6 +1543,7 @@ class VMax3U16Vop3 : public Vop3 { public: VMax3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1514,6 +1554,7 @@ class VMed3F16Vop3 : public Vop3 { public: VMed3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1524,6 +1565,7 @@ class VMed3I16Vop3 : public Vop3 { public: VMed3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1534,6 +1576,7 @@ class VMed3U16Vop3 : public Vop3 { public: VMed3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1544,6 +1587,7 @@ class VMadI16Vop3 : public Vop3 { public: VMadI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1554,6 +1598,7 @@ class VDivFixupF16Vop3 : public Vop3 { public: VDivFixupF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1644,6 +1689,7 @@ class VCndmaskB16Vop3 : public Vop3 { public: VCndmaskB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1674,6 +1720,7 @@ class VMaxminF16Vop3 : public Vop3 { public: VMaxminF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1684,6 +1731,7 @@ class VMinmaxF16Vop3 : public Vop3 { public: VMinmaxF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1734,6 +1782,7 @@ class VDot2F16F16Vop3 : public Vop3 { public: VDot2F16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1744,6 +1793,7 @@ class VDot2Bf16Bf16Vop3 : public Vop3 { public: VDot2Bf16Bf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1754,6 +1804,7 @@ class VAddNcU16Vop3 : public Vop3 { public: VAddNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1763,6 +1814,7 @@ class VSubNcU16Vop3 : public Vop3 { public: VSubNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1772,6 +1824,7 @@ class VMulLoU16Vop3 : public Vop3 { public: VMulLoU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1799,6 +1852,7 @@ class VMaxU16Vop3 : public Vop3 { public: VMaxU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1808,6 +1862,7 @@ class VMaxI16Vop3 : public Vop3 { public: VMaxI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1817,6 +1872,7 @@ class VMinU16Vop3 : public Vop3 { public: VMinU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1826,6 +1882,7 @@ class VMinI16Vop3 : public Vop3 { public: VMinI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1835,6 +1892,7 @@ class VAddNcI16Vop3 : public Vop3 { public: VAddNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1844,6 +1902,7 @@ class VSubNcI16Vop3 : public Vop3 { public: VSubNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2060,6 +2119,7 @@ class VLshlrevB16Vop3 : public Vop3 { public: VLshlrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2069,6 +2129,7 @@ class VLshrrevB16Vop3 : public Vop3 { public: VLshrrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2078,6 +2139,7 @@ class VAshrrevI16Vop3 : public Vop3 { public: VAshrrevI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2132,6 +2194,7 @@ class VAndB16Vop3 : public Vop3 { public: VAndB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2141,6 +2204,7 @@ class VOrB16Vop3 : public Vop3 { public: VOrB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2150,6 +2214,7 @@ class VXorB16Vop3 : public Vop3 { public: VXorB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3p.cpp index 437a7fce95ff..82e34b1ecac9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3p.cpp @@ -2024,6 +2024,12 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) } } +void VFmaMixloF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixloF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2104,6 +2110,12 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) } } +void VFmaMixhiF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixhiF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3p.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3p.h index fadcf4fa4fdb..4f3bfe86c583 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3p.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/vop3p.h @@ -262,6 +262,7 @@ class VFmaMixloF16Vop3p : public Vop3p { public: VFmaMixloF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -272,6 +273,7 @@ class VFmaMixhiF16Vop3p : public Vop3p { public: VFmaMixhiF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop1.cpp index 27dcab750061..2686150b4ea9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop1.cpp @@ -1497,6 +1497,12 @@ SCvtF16F32Sop1::SCvtF16F32Sop1(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SCvtF16F32Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SCvtF16F32Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_cvt_f16_f32_sop1(*this, wf); } @@ -1553,6 +1559,12 @@ SCeilF16Sop1::SCeilF16Sop1(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SCeilF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SCeilF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_ceil_f16_sop1(*this, wf); } @@ -1572,6 +1584,12 @@ SFloorF16Sop1::SFloorF16Sop1(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SFloorF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SFloorF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_floor_f16_sop1(*this, wf); } @@ -1591,6 +1609,12 @@ STruncF16Sop1::STruncF16Sop1(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void STruncF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void STruncF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_trunc_f16_sop1(*this, wf); } @@ -1610,6 +1634,12 @@ SRndneF16Sop1::SRndneF16Sop1(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SRndneF16Sop1::implicit_uses(RegisterSet &uses) const { + Sop1::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SRndneF16Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_rndne_f16_sop1(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop1.h index 8b9d35129fe4..a9716f8a60bf 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop1.h @@ -627,6 +627,7 @@ class SCvtF16F32Sop1 : public Sop1 { public: SCvtF16F32Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -651,6 +652,7 @@ class SCeilF16Sop1 : public Sop1 { public: SCeilF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -659,6 +661,7 @@ class SFloorF16Sop1 : public Sop1 { public: SFloorF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -667,6 +670,7 @@ class STruncF16Sop1 : public Sop1 { public: STruncF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; @@ -675,6 +679,7 @@ class SRndneF16Sop1 : public Sop1 { public: SRndneF16Sop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop2.cpp index a517c6584d87..bee8ef67c5d1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop2.cpp @@ -1478,6 +1478,12 @@ SCvtPkRtzF16F32Sop2::SCvtPkRtzF16F32Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SCvtPkRtzF16F32Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SCvtPkRtzF16F32Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_cvt_pk_rtz_f16_f32_sop2(*this, wf); } @@ -1502,6 +1508,12 @@ SAddF16Sop2::SAddF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SAddF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SAddF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_add_f16_sop2(*this, wf); } SSubF16Sop2::SSubF16Sop2(const MachineInst *inst) @@ -1524,6 +1536,12 @@ SSubF16Sop2::SSubF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SSubF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SSubF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_sub_f16_sop2(*this, wf); } SMinNumF16Sop2::SMinNumF16Sop2(const MachineInst *inst) @@ -1547,6 +1565,12 @@ SMinNumF16Sop2::SMinNumF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SMinNumF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMinNumF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_min_num_f16_sop2(*this, wf); } @@ -1572,6 +1596,12 @@ SMaxNumF16Sop2::SMaxNumF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SMaxNumF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMaxNumF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_max_num_f16_sop2(*this, wf); } @@ -1596,6 +1626,12 @@ SMulF16Sop2::SMulF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SMulF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMulF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_mul_f16_sop2(*this, wf); } SFmacF16Sop2::SFmacF16Sop2(const MachineInst *inst) @@ -1619,6 +1655,12 @@ SFmacF16Sop2::SFmacF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SFmacF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SFmacF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_fmac_f16_sop2(*this, wf); } @@ -1694,6 +1736,12 @@ SMinimumF16Sop2::SMinimumF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SMinimumF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMinimumF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_minimum_f16_sop2(*this, wf); } @@ -1719,6 +1767,12 @@ SMaximumF16Sop2::SMaximumF16Sop2(const MachineInst *inst) static_cast(reinterpret_cast(inst)->simm32)); } +void SMaximumF16Sop2::implicit_uses(RegisterSet &uses) const { + Sop2::implicit_uses(uses); + if (auto r = sdst.to_register_ref()) + uses.expand(*r); +} + void SMaximumF16Sop2::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_maximum_f16_sop2(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop2.h index 2f14b5310323..afccbf0d746f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sop2.h @@ -560,6 +560,7 @@ class SCvtPkRtzF16F32Sop2 : public Sop2 { public: SCvtPkRtzF16F32Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -569,6 +570,7 @@ class SAddF16Sop2 : public Sop2 { public: SAddF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -578,6 +580,7 @@ class SSubF16Sop2 : public Sop2 { public: SSubF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -587,6 +590,7 @@ class SMinNumF16Sop2 : public Sop2 { public: SMinNumF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -596,6 +600,7 @@ class SMaxNumF16Sop2 : public Sop2 { public: SMaxNumF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -605,6 +610,7 @@ class SMulF16Sop2 : public Sop2 { public: SMulF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -614,6 +620,7 @@ class SFmacF16Sop2 : public Sop2 { public: SFmacF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -641,6 +648,7 @@ class SMinimumF16Sop2 : public Sop2 { public: SMinimumF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; @@ -650,6 +658,7 @@ class SMaximumF16Sop2 : public Sop2 { public: SMaximumF16Sop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand sdst; Operand ssrc0; Operand ssrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sopk.cpp index 591199d1bba2..48a3e5e66ed6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sopk.cpp @@ -153,6 +153,12 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregB32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregB32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; @@ -184,6 +190,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) num_dst_ = 1; } +void SSetregImm32B32Sopk::implicit_uses(RegisterSet &uses) const { + Sopk::implicit_uses(uses); + if (auto r = simm16.to_register_ref()) + uses.expand(*r); +} + void SSetregImm32B32Sopk::execute_impl(amdgpu::Wavefront &wf) { uint16_t hwreg = simm16.encoding_value_; uint32_t reg_id = hwreg & 0x3Fu; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sopk.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sopk.h index d694ac0aa5d6..d30d0c073f9e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sopk.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/sopk.h @@ -65,6 +65,7 @@ class SSetregB32Sopk : public Sopk { public: SSetregB32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; Operand sdst; }; @@ -73,6 +74,7 @@ class SSetregImm32B32Sopk : public Sopk { public: SSetregImm32B32Sopk(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand simm16; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vinterp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vinterp.cpp index 35b013aa71e1..79e73806c2ff 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vinterp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vinterp.cpp @@ -88,6 +88,12 @@ VInterpP2F16F32Vinterp::VInterpP2F16F32Vinterp(const MachineInst *inst) num_dst_ = 1; } +void VInterpP2F16F32Vinterp::implicit_uses(RegisterSet &uses) const { + Vinterp::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VInterpP2F16F32Vinterp::execute_impl(amdgpu::Wavefront &wf) { (void)wf; // Interpolation/LDS-direct: no-op in compute simulation. } @@ -126,6 +132,12 @@ VInterpP2RtzF16F32Vinterp::VInterpP2RtzF16F32Vinterp(const MachineInst *inst) num_dst_ = 1; } +void VInterpP2RtzF16F32Vinterp::implicit_uses(RegisterSet &uses) const { + Vinterp::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VInterpP2RtzF16F32Vinterp::execute_impl(amdgpu::Wavefront &wf) { (void)wf; // Interpolation/LDS-direct: no-op in compute simulation. } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vinterp.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vinterp.h index a3288342c5ff..d93d293b03a8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vinterp.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vinterp.h @@ -48,6 +48,7 @@ class VInterpP2F16F32Vinterp : public Vinterp { public: VInterpP2F16F32Vinterp(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -68,6 +69,7 @@ class VInterpP2RtzF16F32Vinterp : public Vinterp { public: VInterpP2RtzF16F32Vinterp(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop1.cpp index 3acdf1795f92..adcccafe073c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop1.cpp @@ -1083,6 +1083,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } } +void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -3235,6 +3241,12 @@ VMovB16Vop1::VMovB16Vop1(const MachineInst *inst) } } +void VMovB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMovB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6998,6 +7010,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } } +void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7128,6 +7146,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } } +void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7258,6 +7282,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } } +void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7394,6 +7424,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } } +void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7532,6 +7568,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } } +void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7675,6 +7717,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } } +void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7818,6 +7866,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } } +void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -7961,6 +8015,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } } +void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8104,6 +8164,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } } +void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8247,6 +8313,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } } +void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8393,6 +8465,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } } +void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8540,6 +8618,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } } +void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8682,6 +8766,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } } +void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8824,6 +8914,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } } +void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -8966,6 +9062,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } } +void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9108,6 +9210,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } } +void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9252,6 +9360,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } } +void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9395,6 +9509,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } } +void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9537,6 +9657,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } } +void VSatPkU8I16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -9575,6 +9701,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } } +void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -9722,6 +9854,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } } +void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10001,6 +10139,14 @@ VSwapB16Vop1::VSwapB16Vop1(const MachineInst *inst) } } +void VSwapB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); + if (auto r = src0.to_register_ref()) + uses.expand(*r); +} + void VSwapB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -10297,6 +10443,12 @@ VNotB16Vop1::VNotB16Vop1(const MachineInst *inst) } } +void VNotB16Vop1::implicit_uses(RegisterSet &uses) const { + Vop1::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VNotB16Vop1::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop1.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop1.h index fd9cd67d9a52..3d13d1df8dbb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop1.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop1.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop1 : public Vop1 { public: VCvtF16F32Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -230,6 +231,7 @@ class VMovB16Vop1 : public Vop1 { public: VMovB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +480,7 @@ class VCvtF16U16Vop1 : public Vop1 { public: VCvtF16U16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +489,7 @@ class VCvtF16I16Vop1 : public Vop1 { public: VCvtF16I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +498,7 @@ class VCvtU16F16Vop1 : public Vop1 { public: VCvtU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +507,7 @@ class VCvtI16F16Vop1 : public Vop1 { public: VCvtI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +516,7 @@ class VRcpF16Vop1 : public Vop1 { public: VRcpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +525,7 @@ class VSqrtF16Vop1 : public Vop1 { public: VSqrtF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +534,7 @@ class VRsqF16Vop1 : public Vop1 { public: VRsqF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +543,7 @@ class VLogF16Vop1 : public Vop1 { public: VLogF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +552,7 @@ class VExpF16Vop1 : public Vop1 { public: VExpF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +561,7 @@ class VFrexpMantF16Vop1 : public Vop1 { public: VFrexpMantF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +570,7 @@ class VFrexpExpI16F16Vop1 : public Vop1 { public: VFrexpExpI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +579,7 @@ class VFloorF16Vop1 : public Vop1 { public: VFloorF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +588,7 @@ class VCeilF16Vop1 : public Vop1 { public: VCeilF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +597,7 @@ class VTruncF16Vop1 : public Vop1 { public: VTruncF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +606,7 @@ class VRndneF16Vop1 : public Vop1 { public: VRndneF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +615,7 @@ class VFractF16Vop1 : public Vop1 { public: VFractF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +624,7 @@ class VSinF16Vop1 : public Vop1 { public: VSinF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +633,7 @@ class VCosF16Vop1 : public Vop1 { public: VCosF16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -622,6 +642,7 @@ class VSatPkU8I16Vop1 : public Vop1 { public: VSatPkU8I16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -630,6 +651,7 @@ class VCvtNormI16F16Vop1 : public Vop1 { public: VCvtNormI16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -638,6 +660,7 @@ class VCvtNormU16F16Vop1 : public Vop1 { public: VCvtNormU16F16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -654,6 +677,7 @@ class VSwapB16Vop1 : public Vop1 { public: VSwapB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -678,6 +702,7 @@ class VNotB16Vop1 : public Vop1 { public: VNotB16Vop1(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop2.cpp index 0824de9f4bdc..3b32560f1a66 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop2.cpp @@ -4863,6 +4863,12 @@ VMinNumF16Vop2::VMinNumF16Vop2(const MachineInst *inst) } } +void VMinNumF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinNumF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5012,6 +5018,12 @@ VMaxNumF16Vop2::VMaxNumF16Vop2(const MachineInst *inst) } } +void VMaxNumF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxNumF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5161,6 +5173,12 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } } +void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5310,6 +5328,12 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } } +void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5459,6 +5483,12 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } } +void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5608,6 +5638,12 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } } +void VMulF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5759,6 +5795,12 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) } } +void VFmacF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -5914,6 +5956,12 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VFmamkF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmamkF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6060,6 +6108,12 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) simm32_ = reinterpret_cast(inst)->simm32; } +void VFmaakF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaakF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { @@ -6204,6 +6258,12 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } } +void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { + Vop2::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop2::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop2.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop2.h index 76f00bc01bf9..041da01b3cbb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop2.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop2.h @@ -362,6 +362,7 @@ class VMinNumF16Vop2 : public Vop2 { public: VMinNumF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -371,6 +372,7 @@ class VMaxNumF16Vop2 : public Vop2 { public: VMaxNumF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -380,6 +382,7 @@ class VAddF16Vop2 : public Vop2 { public: VAddF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -389,6 +392,7 @@ class VSubF16Vop2 : public Vop2 { public: VSubF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -398,6 +402,7 @@ class VSubrevF16Vop2 : public Vop2 { public: VSubrevF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -407,6 +412,7 @@ class VMulF16Vop2 : public Vop2 { public: VMulF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -416,6 +422,7 @@ class VFmacF16Vop2 : public Vop2 { public: VFmacF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -425,6 +432,7 @@ class VFmamkF16Vop2 : public Vop2 { public: VFmamkF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -435,6 +443,7 @@ class VFmaakF16Vop2 : public Vop2 { public: VFmaakF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; @@ -445,6 +454,7 @@ class VLdexpF16Vop2 : public Vop2 { public: VLdexpF16Vop2(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand vsrc1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3.cpp index a085344ffaeb..1add803df42b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3.cpp @@ -606,6 +606,12 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } } +void VCvtF16F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -1755,6 +1761,12 @@ VMovB16Vop3::VMovB16Vop3(const MachineInst *inst) } } +void VMovB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMovB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3707,6 +3719,12 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } } +void VCvtF16U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3782,6 +3800,12 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } } +void VCvtF16I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtF16I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3857,6 +3881,12 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } } +void VCvtU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -3938,6 +3968,12 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } } +void VCvtI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4020,6 +4056,12 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } } +void VRcpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRcpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4118,6 +4160,12 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } } +void VSqrtF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSqrtF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4221,6 +4269,12 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } } +void VRsqF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRsqF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4319,6 +4373,12 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } } +void VLogF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLogF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4417,6 +4477,12 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } } +void VExpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VExpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4516,6 +4582,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } } +void VFrexpMantF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpMantF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4621,6 +4693,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } } +void VFrexpExpI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFrexpExpI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4729,6 +4807,12 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } } +void VFloorF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFloorF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4827,6 +4911,12 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } } +void VCeilF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCeilF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -4926,6 +5016,12 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } } +void VTruncF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VTruncF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5025,6 +5121,12 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } } +void VRndneF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VRndneF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5124,6 +5226,12 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } } +void VFractF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFractF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5225,6 +5333,12 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } } +void VSinF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSinF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5319,6 +5433,12 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } } +void VCosF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCosF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5414,6 +5534,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } } +void VSatPkU8I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSatPkU8I16Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); @@ -5451,6 +5577,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } } +void VCvtNormI16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormI16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5531,6 +5663,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } } +void VCvtNormU16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtNormU16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -5610,6 +5748,12 @@ VNotB16Vop3::VNotB16Vop3(const MachineInst *inst) } } +void VNotB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VNotB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8547,6 +8691,12 @@ VMinNumF16Vop3::VMinNumF16Vop3(const MachineInst *inst) } } +void VMinNumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinNumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8668,6 +8818,12 @@ VMaxNumF16Vop3::VMaxNumF16Vop3(const MachineInst *inst) } } +void VMaxNumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxNumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8788,6 +8944,12 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } } +void VAddF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -8906,6 +9068,12 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } } +void VSubF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -9025,6 +9193,12 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } } +void VSubrevF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubrevF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -9143,6 +9317,12 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } } +void VMulF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -9262,6 +9442,12 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) } } +void VFmacF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmacF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -9384,6 +9570,12 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } } +void VLdexpF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLdexpF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -11956,6 +12148,12 @@ VMin3NumF16Vop3::VMin3NumF16Vop3(const MachineInst *inst) } } +void VMin3NumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3NumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12091,6 +12289,12 @@ VMax3NumF16Vop3::VMax3NumF16Vop3(const MachineInst *inst) } } +void VMax3NumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3NumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12384,6 +12588,12 @@ VMinimum3F16Vop3::VMinimum3F16Vop3(const MachineInst *inst) } } +void VMinimum3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinimum3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12524,6 +12734,12 @@ VMaximum3F16Vop3::VMaximum3F16Vop3(const MachineInst *inst) } } +void VMaximum3F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaximum3F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -12743,6 +12959,12 @@ VMed3NumF16Vop3::VMed3NumF16Vop3(const MachineInst *inst) } } +void VMed3NumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3NumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13334,6 +13556,12 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } } +void VMadU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13737,6 +13965,12 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } } +void VFmaF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13870,6 +14104,12 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } } +void VMin3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -13976,6 +14216,12 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } } +void VMin3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMin3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14079,6 +14325,12 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } } +void VMax3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14185,6 +14437,12 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } } +void VMax3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMax3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14288,6 +14546,12 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } } +void VMed3I16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3I16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14396,6 +14660,12 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } } +void VMed3U16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMed3U16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14503,6 +14773,12 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } } +void VMadI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMadI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -14596,6 +14872,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } } +void VDivFixupF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDivFixupF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15449,6 +15731,12 @@ VCndmaskB16Vop3::VCndmaskB16Vop3(const MachineInst *inst) } } +void VCndmaskB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCndmaskB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15859,6 +16147,12 @@ VDot2F16F16Vop3::VDot2F16F16Vop3(const MachineInst *inst) } } +void VDot2F16F16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDot2F16F16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -15982,6 +16276,12 @@ VDot2Bf16Bf16Vop3::VDot2Bf16Bf16Vop3(const MachineInst *inst) } } +void VDot2Bf16Bf16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VDot2Bf16Bf16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16263,6 +16563,12 @@ VMinmaxNumF16Vop3::VMinmaxNumF16Vop3(const MachineInst *inst) } } +void VMinmaxNumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinmaxNumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16398,6 +16704,12 @@ VMaxminNumF16Vop3::VMaxminNumF16Vop3(const MachineInst *inst) } } +void VMaxminNumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxminNumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16691,6 +17003,12 @@ VMinimummaximumF16Vop3::VMinimummaximumF16Vop3(const MachineInst *inst) } } +void VMinimummaximumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinimummaximumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -16831,6 +17149,12 @@ VMaximumminimumF16Vop3::VMaximumminimumF16Vop3(const MachineInst *inst) } } +void VMaximumminimumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaximumminimumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -17732,6 +18056,12 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) } } +void VAddNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -17818,6 +18148,12 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) } } +void VSubNcU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -17904,6 +18240,12 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } } +void VMulLoU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMulLoU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18158,6 +18500,12 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } } +void VMaxU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18244,6 +18592,12 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } } +void VMaxI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaxI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18330,6 +18684,12 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } } +void VMinU16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinU16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18416,6 +18776,12 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } } +void VMinI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18503,6 +18869,12 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) } } +void VAddNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAddNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -18588,6 +18960,12 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) } } +void VSubNcI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VSubNcI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -20281,6 +20659,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } } +void VLshlrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshlrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -20364,6 +20748,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } } +void VLshrrevB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VLshrrevB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -20447,6 +20837,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } } +void VAshrrevI16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAshrrevI16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -20973,6 +21369,12 @@ VAndB16Vop3::VAndB16Vop3(const MachineInst *inst) } } +void VAndB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VAndB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -21058,6 +21460,12 @@ VOrB16Vop3::VOrB16Vop3(const MachineInst *inst) } } +void VOrB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VOrB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -21143,6 +21551,12 @@ VXorB16Vop3::VXorB16Vop3(const MachineInst *inst) } } +void VXorB16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VXorB16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -21375,6 +21789,12 @@ VMinimumF16Vop3::VMinimumF16Vop3(const MachineInst *inst) } } +void VMinimumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMinimumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -21495,6 +21915,12 @@ VMaximumF16Vop3::VMaximumF16Vop3(const MachineInst *inst) } } +void VMaximumF16Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VMaximumF16Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -21615,6 +22041,12 @@ VCvtPkFp8F32Vop3::VCvtPkFp8F32Vop3(const MachineInst *inst) } } +void VCvtPkFp8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtPkFp8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -21698,6 +22130,12 @@ VCvtPkBf8F32Vop3::VCvtPkBf8F32Vop3(const MachineInst *inst) } } +void VCvtPkBf8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtPkBf8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -21782,6 +22220,12 @@ VCvtSrFp8F32Vop3::VCvtSrFp8F32Vop3(const MachineInst *inst) } } +void VCvtSrFp8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrFp8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -21867,6 +22311,12 @@ VCvtSrBf8F32Vop3::VCvtSrBf8F32Vop3(const MachineInst *inst) } } +void VCvtSrBf8F32Vop3::implicit_uses(RegisterSet &uses) const { + Vop3::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VCvtSrBf8F32Vop3::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3.h index 8a871b2f0752..5f9851f09aa3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3.h @@ -88,6 +88,7 @@ class VCvtF16F32Vop3 : public Vop3 { public: VCvtF16F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -230,6 +231,7 @@ class VMovB16Vop3 : public Vop3 { public: VMovB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -478,6 +480,7 @@ class VCvtF16U16Vop3 : public Vop3 { public: VCvtF16U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -486,6 +489,7 @@ class VCvtF16I16Vop3 : public Vop3 { public: VCvtF16I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -494,6 +498,7 @@ class VCvtU16F16Vop3 : public Vop3 { public: VCvtU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -502,6 +507,7 @@ class VCvtI16F16Vop3 : public Vop3 { public: VCvtI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -510,6 +516,7 @@ class VRcpF16Vop3 : public Vop3 { public: VRcpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -518,6 +525,7 @@ class VSqrtF16Vop3 : public Vop3 { public: VSqrtF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -526,6 +534,7 @@ class VRsqF16Vop3 : public Vop3 { public: VRsqF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -534,6 +543,7 @@ class VLogF16Vop3 : public Vop3 { public: VLogF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -542,6 +552,7 @@ class VExpF16Vop3 : public Vop3 { public: VExpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -550,6 +561,7 @@ class VFrexpMantF16Vop3 : public Vop3 { public: VFrexpMantF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -558,6 +570,7 @@ class VFrexpExpI16F16Vop3 : public Vop3 { public: VFrexpExpI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -566,6 +579,7 @@ class VFloorF16Vop3 : public Vop3 { public: VFloorF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -574,6 +588,7 @@ class VCeilF16Vop3 : public Vop3 { public: VCeilF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -582,6 +597,7 @@ class VTruncF16Vop3 : public Vop3 { public: VTruncF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -590,6 +606,7 @@ class VRndneF16Vop3 : public Vop3 { public: VRndneF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -598,6 +615,7 @@ class VFractF16Vop3 : public Vop3 { public: VFractF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -606,6 +624,7 @@ class VSinF16Vop3 : public Vop3 { public: VSinF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -614,6 +633,7 @@ class VCosF16Vop3 : public Vop3 { public: VCosF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -622,6 +642,7 @@ class VSatPkU8I16Vop3 : public Vop3 { public: VSatPkU8I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -630,6 +651,7 @@ class VCvtNormI16F16Vop3 : public Vop3 { public: VCvtNormI16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -638,6 +660,7 @@ class VCvtNormU16F16Vop3 : public Vop3 { public: VCvtNormU16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -646,6 +669,7 @@ class VNotB16Vop3 : public Vop3 { public: VNotB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; }; @@ -1000,6 +1024,7 @@ class VMinNumF16Vop3 : public Vop3 { public: VMinNumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1009,6 +1034,7 @@ class VMaxNumF16Vop3 : public Vop3 { public: VMaxNumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1018,6 +1044,7 @@ class VAddF16Vop3 : public Vop3 { public: VAddF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1027,6 +1054,7 @@ class VSubF16Vop3 : public Vop3 { public: VSubF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1036,6 +1064,7 @@ class VSubrevF16Vop3 : public Vop3 { public: VSubrevF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1045,6 +1074,7 @@ class VMulF16Vop3 : public Vop3 { public: VMulF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1054,6 +1084,7 @@ class VFmacF16Vop3 : public Vop3 { public: VFmacF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1063,6 +1094,7 @@ class VLdexpF16Vop3 : public Vop3 { public: VLdexpF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1382,6 +1414,7 @@ class VMin3NumF16Vop3 : public Vop3 { public: VMin3NumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1392,6 +1425,7 @@ class VMax3NumF16Vop3 : public Vop3 { public: VMax3NumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1422,6 +1456,7 @@ class VMinimum3F16Vop3 : public Vop3 { public: VMinimum3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1432,6 +1467,7 @@ class VMaximum3F16Vop3 : public Vop3 { public: VMaximum3F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1452,6 +1488,7 @@ class VMed3NumF16Vop3 : public Vop3 { public: VMed3NumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1532,6 +1569,7 @@ class VMadU16Vop3 : public Vop3 { public: VMadU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1582,6 +1620,7 @@ class VFmaF16Vop3 : public Vop3 { public: VFmaF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1592,6 +1631,7 @@ class VMin3I16Vop3 : public Vop3 { public: VMin3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1602,6 +1642,7 @@ class VMin3U16Vop3 : public Vop3 { public: VMin3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1612,6 +1653,7 @@ class VMax3I16Vop3 : public Vop3 { public: VMax3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1622,6 +1664,7 @@ class VMax3U16Vop3 : public Vop3 { public: VMax3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1632,6 +1675,7 @@ class VMed3I16Vop3 : public Vop3 { public: VMed3I16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1642,6 +1686,7 @@ class VMed3U16Vop3 : public Vop3 { public: VMed3U16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1652,6 +1697,7 @@ class VMadI16Vop3 : public Vop3 { public: VMadI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1662,6 +1708,7 @@ class VDivFixupF16Vop3 : public Vop3 { public: VDivFixupF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1752,6 +1799,7 @@ class VCndmaskB16Vop3 : public Vop3 { public: VCndmaskB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1802,6 +1850,7 @@ class VDot2F16F16Vop3 : public Vop3 { public: VDot2F16F16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1812,6 +1861,7 @@ class VDot2Bf16Bf16Vop3 : public Vop3 { public: VDot2Bf16Bf16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1842,6 +1892,7 @@ class VMinmaxNumF16Vop3 : public Vop3 { public: VMinmaxNumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1852,6 +1903,7 @@ class VMaxminNumF16Vop3 : public Vop3 { public: VMaxminNumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1882,6 +1934,7 @@ class VMinimummaximumF16Vop3 : public Vop3 { public: VMinimummaximumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1892,6 +1945,7 @@ class VMaximumminimumF16Vop3 : public Vop3 { public: VMaximumminimumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1982,6 +2036,7 @@ class VAddNcU16Vop3 : public Vop3 { public: VAddNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -1991,6 +2046,7 @@ class VSubNcU16Vop3 : public Vop3 { public: VSubNcU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2000,6 +2056,7 @@ class VMulLoU16Vop3 : public Vop3 { public: VMulLoU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2027,6 +2084,7 @@ class VMaxU16Vop3 : public Vop3 { public: VMaxU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2036,6 +2094,7 @@ class VMaxI16Vop3 : public Vop3 { public: VMaxI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2045,6 +2104,7 @@ class VMinU16Vop3 : public Vop3 { public: VMinU16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2054,6 +2114,7 @@ class VMinI16Vop3 : public Vop3 { public: VMinI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2063,6 +2124,7 @@ class VAddNcI16Vop3 : public Vop3 { public: VAddNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2072,6 +2134,7 @@ class VSubNcI16Vop3 : public Vop3 { public: VSubNcI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2270,6 +2333,7 @@ class VLshlrevB16Vop3 : public Vop3 { public: VLshlrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2279,6 +2343,7 @@ class VLshrrevB16Vop3 : public Vop3 { public: VLshrrevB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2288,6 +2353,7 @@ class VAshrrevI16Vop3 : public Vop3 { public: VAshrrevI16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2351,6 +2417,7 @@ class VAndB16Vop3 : public Vop3 { public: VAndB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2360,6 +2427,7 @@ class VOrB16Vop3 : public Vop3 { public: VOrB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2369,6 +2437,7 @@ class VXorB16Vop3 : public Vop3 { public: VXorB16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2396,6 +2465,7 @@ class VMinimumF16Vop3 : public Vop3 { public: VMinimumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2405,6 +2475,7 @@ class VMaximumF16Vop3 : public Vop3 { public: VMaximumF16Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2414,6 +2485,7 @@ class VCvtPkFp8F32Vop3 : public Vop3 { public: VCvtPkFp8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2423,6 +2495,7 @@ class VCvtPkBf8F32Vop3 : public Vop3 { public: VCvtPkBf8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2432,6 +2505,7 @@ class VCvtSrFp8F32Vop3 : public Vop3 { public: VCvtSrFp8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -2441,6 +2515,7 @@ class VCvtSrBf8F32Vop3 : public Vop3 { public: VCvtSrBf8F32Vop3(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3p.cpp index a86029b847f2..7fcb886b5449 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3p.cpp @@ -2807,6 +2807,12 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) } } +void VFmaMixloF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixloF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { @@ -2923,6 +2929,12 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) } } +void VFmaMixhiF16Vop3p::implicit_uses(RegisterSet &uses) const { + Vop3p::implicit_uses(uses); + if (auto r = vdst.to_register_ref()) + uses.expand(*r); +} + void VFmaMixhiF16Vop3p::execute_impl(amdgpu::Wavefront &wf) { uint32_t sdwa_old_dst_[64] = {}; if (inst_.src0 == amdgpu::SRC_DPP) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3p.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3p.h index 22d1de399dcf..6ccf4c4b969a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3p.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/vop3p.h @@ -280,6 +280,7 @@ class VFmaMixloF16Vop3p : public Vop3p { public: VFmaMixloF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; @@ -290,6 +291,7 @@ class VFmaMixhiF16Vop3p : public Vop3p { public: VFmaMixhiF16Vop3p(const MachineInst *inst); void execute_impl(amdgpu::Wavefront &wf); + void implicit_uses(RegisterSet &uses) const override; Operand vdst; Operand src0; Operand src1; diff --git a/emulation/rocjitsu/tests/analysis/liveness_test.cpp b/emulation/rocjitsu/tests/analysis/liveness_test.cpp index 05fe108a677e..3aca245d3950 100644 --- a/emulation/rocjitsu/tests/analysis/liveness_test.cpp +++ b/emulation/rocjitsu/tests/analysis/liveness_test.cpp @@ -9,6 +9,7 @@ #include "rocjitsu/isa/arch/amdgpu/cdna4/operand.h" #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/instruction.h" +#include "rocjitsu/isa/isa_traits.h" #include "rocjitsu/isa/operand.h" #include "rocjitsu/isa/register_set.h" @@ -74,6 +75,15 @@ class TestInstruction : public Instruction { void implicit_uses(RegisterSet &uses) const override { for (RegisterRef ref : implicit_uses_) uses.expand(ref); + // Mirror the codegen: a sub-dword (< 32-bit) destination writes only part + // of its register lane, so the old value survives and the register is also + // read. Generated instructions surface these partial defs via implicit_uses. + for (int i = 0; i < num_dst_; ++i) { + const Operand *op = dst_operands_[i]; + if (op != nullptr && op->size_bits() > 0 && op->size_bits() < REGISTER_GRANULARITY) + if (auto ref = op->to_register_ref()) + uses.expand(*ref); + } } private: