From 3fe5de0335e3e1fad4dc5d4d6408d40c54a572e9 Mon Sep 17 00:00:00 2001 From: rtom Date: Fri, 7 Nov 2025 19:57:03 +0000 Subject: [PATCH] [hipblaslt] Add missing arguments in kernelwriter.py --- projects/hipblaslt/tensilelite/Tensile/KernelWriter.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py b/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py index 4e724b2d3af..e2f26e4bb56 100644 --- a/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py +++ b/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py @@ -2295,7 +2295,7 @@ def noLoadLoopBody( self, kernel, tensorParametersA, tensorParametersB, pack, is waitLWCode.add(self._wait(kernel, tensorParametersA, tensorParametersB, -1, 0, -1, "3wait for local write")) if (kernel["DirectToVgprA"] or kernel["DirectToVgprB"]) and (kernel["DirectToLdsA"] or kernel["DirectToLdsB"]): # DirectToVgpr + DirectToLds case, add waitcnt vmcnt before s_barrier - waitLWCode.add(self.getWaitcntCodeForDirectToVgpr(kernel, localWriteEndIter, u, isNLL=(not isNGLL), beforeBarrier=True)) + waitLWCode.add(self.getWaitcntCodeForDirectToVgpr(kernel, tensorParametersA, tensorParametersB, localWriteEndIter, u, isNLL=(not isNGLL), beforeBarrier=True)) elif kernel["PrefetchGlobalRead"]==2 and (kernel["DirectToLdsA"] and kernel["DirectToLdsB"]): waitLWCode.add(self._wait(kernel, tensorParametersA, tensorParametersB, 0, -1, -1, "wait for global reads with lds")) syncCode.add(self._syncThreads(kernel))